From 06cdac8e840767f801bbd94ed991354a206adf1f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 18 Apr 2023 16:21:09 +0200 Subject: [PATCH 001/926] arm64: dts: rockchip: add GIC ITS support to rk3588 Add the two Interrupt Translation Service (ITS) IPs that are part of the GIC-600. They are mainly required for PCIe Message Signalled Interrupts (MSI). Co-developed-by: Kever Yang Signed-off-by: Kever Yang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230418142109.49762-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 657c019d27fa9..63fbf66466911 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1300,7 +1300,24 @@ gic: interrupt-controller@fe600000 { mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; + ranges; + #address-cells = <2>; #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; ppi-partitions { ppi_partition0: interrupt-partition-0 { -- GitLab From 09d5fef31f9058e3b39e3a6b8870b6fb9f28091d Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 19 Apr 2023 21:13:09 +0300 Subject: [PATCH 002/926] arm64: dts: rockchip: Add rk3588 timer Add DT node for Rockchip RK3588/RK3588S SoC timer. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230419181309.338354-4-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 63fbf66466911..944fbe0e8bdb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1417,6 +1417,14 @@ i2c5: i2c@fead0000 { status = "disabled"; }; + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + wdt: watchdog@feaf0000 { compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; reg = <0x0 0xfeaf0000 0x0 0x100>; -- GitLab From 1f8af7aa2796653f5c3c0ed5c4df564ac5b7aba3 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 6 May 2023 14:11:06 +0800 Subject: [PATCH 003/926] dt-bindings: Add doc for Fastrhino R66S / R68S Add devicetree binding documentation for the Lunzn Fastrhino R66S and R68S boards. Acked-by: Krzysztof Kozlowski Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230506061108.17658-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ec141c937b8b9..b1d271778179e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -562,6 +562,13 @@ properties: - const: leez,p710 - const: rockchip,rk3399 + - description: Lunzn FastRhino R66S / R68S + items: + - enum: + - lunzn,fastrhino-r66s + - lunzn,fastrhino-r68s + - const: rockchip,rk3568 + - description: mqmaker MiQi items: - const: mqmaker,miqi diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 82d39ab0231b0..c3d426509e7e8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -781,6 +781,8 @@ patternProperties: description: Nanjing Loongmasses Ltd. "^lsi,.*": description: LSI Corp. (LSI Logic) + "^lunzn,.*": + description: Shenzhen Lunzn Technology Co., Ltd. "^lwn,.*": description: Liebherr-Werk Nenzing GmbH "^lxa,.*": -- GitLab From c79dab407afddaf405ee8a825f434fab89fbf0c6 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 6 May 2023 14:11:07 +0800 Subject: [PATCH 004/926] arm64: dts: rockchip: Add Lunzn Fastrhino R66S Lunzn Fastrhino R66S is a high-performance mini router. Specification: - Rockchip RK3568 - 1/2GB LPDDR4 RAM - SD card slot - 2x USB 3.0 Port - 2x 2500 Base-T (PCIe, r8125b) - 12v DC Jack Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230506061108.17658-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-fastrhino-r66s.dts | 27 + .../dts/rockchip/rk3568-fastrhino-r66s.dtsi | 484 ++++++++++++++++++ 3 files changed, 512 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 2d585bbb8f3a7..15089a78555a2 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts new file mode 100644 index 0000000000000..58ab7e9971dbc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-fastrhino-r66s.dtsi" + +/ { + model = "Lunzn FastRhino R66S"; + compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568"; + + aliases { + mmc0 = &sdmmc0; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi new file mode 100644 index 0000000000000..25e205632a686 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&status_led_pin>; + + status_led: led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-init-microvolt = <950000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + status_led_pin: status-led-pin { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; -- GitLab From b9f8ca655d803a49266e73e26729882418407166 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 6 May 2023 14:11:08 +0800 Subject: [PATCH 005/926] arm64: dts: rockchip: Add Lunzn Fastrhino R68S It's similar to Fastrhino R66S with the following changes: + 2/4GB LPDDR4 RAM + 2x 1000 Base-T (native, RTL8211f) + ADC button + 16GB eMMC on-board - No SD card slot Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230506061108.17658-3-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-fastrhino-r68s.dts | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 15089a78555a2..1cf105d7407f0 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts new file mode 100644 index 0000000000000..e1fe5e442689a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-fastrhino-r66s.dtsi" + +/ { + model = "Lunzn FastRhino R68S"; + compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x4f>; + rx_delay = <0x26>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; -- GitLab From b3bd64bc457ca778258cfb3e392d9296f11b396e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 4 May 2023 23:06:06 +0100 Subject: [PATCH 006/926] MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry The Allwinner & Renesas stuff doesn't go through my tree, so it is a wee bit misleading to have them match against the "misc" entry in MAINTAINERS. Signed-off-by: Conor Dooley --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e5..12b39e9760734 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18154,6 +18154,8 @@ Q: https://patchwork.kernel.org/project/linux-riscv/list/ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ +X: arch/riscv/boot/dts/allwinner/ +X: arch/riscv/boot/dts/renesas/ RNBD BLOCK DRIVERS M: Md. Haris Iqbal -- GitLab From 6a887bcc4138de9747fdfafc4ebf0a1c6ef4b2c1 Mon Sep 17 00:00:00 2001 From: Walker Chen Date: Mon, 17 Apr 2023 11:47:28 +0800 Subject: [PATCH 007/926] riscv: dts: starfive: Add PMU controller node Add the pmu controller node for the StarFive JH7110 SoC. The PMU needs to be used by other modules, e.g. VPU,ISP,etc. Reviewed-by: Conor Dooley Reviewed-by: Hal Feng Signed-off-by: Walker Chen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da80..30e1f34d5cf8d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -496,5 +496,12 @@ aongpio: pinctrl@17020000 { gpio-controller; #gpio-cells = <2>; }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; }; }; -- GitLab From 7e16774770c57c5cad4d18acceec381673d44970 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:39 +0100 Subject: [PATCH 008/926] arm64: dts: renesas: r9a07g044: Add fcpvd node Add fcpvd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 1315be5167b95..dd98688c36616 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -697,6 +697,18 @@ csi2cru: endpoint@0 { }; }; + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g044-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; -- GitLab From fad741768e7b9572fad05fe4523c76a236c4056a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:40 +0100 Subject: [PATCH 009/926] arm64: dts: renesas: r9a07g054: Add fcpvd node Add fcpvd node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index cc11e5855d62c..cc75a93caf020 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -623,6 +623,18 @@ sbc: spi@10060000 { status = "disabled"; }; + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g054-fcpvd", + "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g054-cpg"; reg = <0 0x11010000 0 0x10000>; -- GitLab From 9af677e0747965f30b6c3540d464d34e22da5336 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:41 +0100 Subject: [PATCH 010/926] arm64: dts: renesas: r9a07g044: Add vspd node Add vspd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index dd98688c36616..796ad2034699a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -697,6 +697,19 @@ csi2cru: endpoint@0 { }; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g044-fcpvd", "renesas,fcpv"; -- GitLab From 79572c7f326ab977e1e9138643e4371067aec844 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:42 +0100 Subject: [PATCH 011/926] arm64: dts: renesas: r9a07g054: Add vspd node Add vspd node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index cc75a93caf020..e8ad19fafb530 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -623,6 +623,20 @@ sbc: spi@10060000 { status = "disabled"; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g054-vsp2", + "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g054-fcpvd", "renesas,fcpv"; -- GitLab From 862b676c3cadc8a1b1600f08408cdc5e030036e6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:43 +0100 Subject: [PATCH 012/926] arm64: dts: renesas: r9a07g044: Add DSI node Add DSI node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 796ad2034699a..140bcf1265677 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -697,6 +697,34 @@ csi2cru: endpoint@0 { }; }; + dsi: dsi@10850000 { + compatible = "renesas,r9a07g044-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + vspd: vsp@10870000 { compatible = "renesas,r9a07g044-vsp2"; reg = <0 0x10870000 0 0x10000>; -- GitLab From 33de13da4e2df73daeb38f94f2771a5ae031947d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:44 +0100 Subject: [PATCH 013/926] arm64: dts: renesas: r9a07g054: Add DSI node Add DSI node to RZ/V2L SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e8ad19fafb530..782fc204e8949 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -623,6 +623,34 @@ sbc: spi@10060000 { status = "disabled"; }; + dsi: dsi@10850000 { + compatible = "renesas,r9a07g054-mipi-dsi", + "renesas,rzg2l-mipi-dsi"; + reg = <0 0x10850000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>, + <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>; + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>, + <&cpg R9A07G054_MIPI_DSI_ARESET_N>, + <&cpg R9A07G054_MIPI_DSI_PRESET_N>; + reset-names = "rst", "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + }; + vspd: vsp@10870000 { compatible = "renesas,r9a07g054-vsp2", "renesas,r9a07g044-vsp2"; -- GitLab From 6affac45357d88c7c67418617133df82454efabd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:45 +0100 Subject: [PATCH 014/926] arm64: dts: renesas: rzg2l-smarc: Link DSI with ADV7535 Enable DSI and ADV7535 and link DSI with ADV7535 on RZ/G2L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 79 ++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index e180a955b6ac8..2a158a954b2fc 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -16,12 +16,91 @@ aliases { serial1 = &scif2; i2c3 = &i2c3; }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; }; &cpu_dai { sound-dai = <&ssi0>; }; +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; -- GitLab From 961eed28296853a81d792654f392773800df91db Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 11 Apr 2023 11:03:46 +0100 Subject: [PATCH 015/926] arm64: dts: renesas: rzg2lc-smarc: Link DSI with ADV7535 Enable DSI and ADV7535 and link DSI with ADV7535 on RZ/G2LC SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230411100346.299768-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index b6bd27196d888..6818fd49b2bed 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -17,6 +17,23 @@ aliases { serial1 = &scif1; i2c2 = &i2c2; }; + + osc1: cec-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; }; #if (SW_SCIF_CAN || SW_RSPI_CAN) @@ -36,6 +53,68 @@ &cpu_dai { sound-dai = <&ssi0>; }; +&dsi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&i2c1 { + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&osc1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; -- GitLab From a3c95a54727a81a4f3bd65b05c2e8542b2821ec3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 12 Apr 2023 19:56:07 +0100 Subject: [PATCH 016/926] arm64: dts: renesas: r9a07g054: Add CSI and CRU nodes Add CSI and CRU nodes to r9a07g054 (RZ/V2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230412185608.64628-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 782fc204e8949..e6135dfd6b36a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -623,6 +623,85 @@ sbc: spi@10060000 { status = "disabled"; }; + cru: video@10830000 { + compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>, + <&cpg CPG_MOD R9A07G054_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + cruparallel: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G054_CRU_VCLK>, + <&cpg CPG_MOD R9A07G054_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G054_CRU_PRESETN>, + <&cpg R9A07G054_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + dsi: dsi@10850000 { compatible = "renesas,r9a07g054-mipi-dsi", "renesas,rzg2l-mipi-dsi"; -- GitLab From 3cf6b4c685e635bf184ac01b09ea647f103f0c83 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 12 Apr 2023 19:56:08 +0100 Subject: [PATCH 017/926] arm64: dts: renesas: rzv2l-smarc: Enable CRU, CSI support Enable CRU, CSI on RZ/V2L SMARC EVK and tie the CSI to the OV5645 sensor using Device Tree overlay. RZ/G2L SMARC EVK and RZ/V2L SMARC EVK have the same connections for connecting the CSI to OV5645 sensor so just reuse the existing r9a07g044l2-smarc-cru-csi-ov5645.dtso and create a symbolic link to this file for RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230412185608.64628-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso | 2 +- .../boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) create mode 120000 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f130165577a83..ebcbd66ba816f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso index d834bff9bda2c..736c1e688cc8b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera + * Device Tree overlay for the RZ/{G2L, V2L} SMARC EVK with OV5645 camera * connected to CSI and CRU enabled. * * Copyright (C) 2023 Renesas Electronics Corp. diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso new file mode 120000 index 0000000000000..0f175341d3ed3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1 @@ +r9a07g044l2-smarc-cru-csi-ov5645.dtso \ No newline at end of file -- GitLab From 0c63a51990872d3396f144fea41155c89a0f1a93 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 13 Apr 2023 12:40:16 +0100 Subject: [PATCH 018/926] arm64: dts: renesas: rzg2lc-smarc: Enable CRU, CSI support Enable CRU, CSI on RZ/G2LC SMARC EVK and tie the CSI to the OV5645 sensor using Device Tree overlay. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230413114016.16068-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r9a07g044c2-smarc-cru-csi-ov5645.dtso | 21 +++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ebcbd66ba816f..7114cbbd87130 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 0000000000000..f983bdd3ea307 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2LC SMARC EVK with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>; +}; -- GitLab From 26336d66d0216b7366f80ce9fca5f98d271d43ba Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 17 Apr 2023 10:01:57 +0100 Subject: [PATCH 019/926] arm64: dts: renesas: r9a07g044: Add MTU3a node Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230417090159.191346-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 140bcf1265677..232910e07444e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -174,6 +174,76 @@ soc: soc { #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g044-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tgiv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tgiv1", "tgiu1", + "tgia2", "tgib2", "tgiv2", "tgiu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tgiv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tgiv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tgiv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tgiv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tgiv8", "tgiu8"; + clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g044-ssi", "renesas,rz-ssi"; -- GitLab From dd123dd01def6ad917703542cf7263865bed3239 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 17 Apr 2023 10:01:58 +0100 Subject: [PATCH 020/926] arm64: dts: renesas: r9a07g054: Add MTU3a node Add MTU3a node to R9A07G054 (RZ/V2L) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230417090159.191346-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e6135dfd6b36a..2eba3a8a100d0 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -174,6 +174,76 @@ soc: soc { #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g054-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tgiv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tgiv1", "tgiu1", + "tgia2", "tgib2", "tgiv2", "tgiu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tgiv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tgiv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tgiv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tgiv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tgiv8", "tgiu8"; + clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g054-ssi", "renesas,rz-ssi"; -- GitLab From 18cbbdd846c5d74bd56fd1f229d074e1f7068fc8 Mon Sep 17 00:00:00 2001 From: Phong Hoang Date: Tue, 2 May 2023 19:06:18 +0200 Subject: [PATCH 021/926] arm64: dts: renesas: r8a779a0: Add PWM nodes This patch adds PWM nodes for R-Car V3U (r8a779a0) SoC. Signed-off-by: Phong Hoang [wsa: rebased] Tested-by: Kieran Bingham Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20230502170618.55967-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index bf587a14ec195..4e67a03564971 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -943,6 +943,56 @@ avb5: ethernet@e6850000 { status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", "renesas,rcar-gen4-scif", "renesas,scif"; -- GitLab From 9972b45776aba937d0db67f8080ec627a924f56e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:19 -0500 Subject: [PATCH 022/926] arm64: dts: ti: k3-am64: Add general purpose timers There are 11 general purpose timers on am64 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am65, the timers on am64 do not have a dedicated IO mux for the timers. On am62, the timers have different interrupts, clocks and power domains compared to am65, and the MCU timers are at a different IO address. Compared to AM62, the AM64 times have different clocks and count in main domain are different as well. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 144 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 45 +++++++ 2 files changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5e8036f32d79d..f5e25d6c3c28b 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -228,6 +228,150 @@ epwm_tbclk: clock@4140 { }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 1>; + assigned-clock-parents = <&k3_clks 36 2>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 1>; + assigned-clock-parents = <&k3_clks 37 2>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 1>; + assigned-clock-parents = <&k3_clks 38 2>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 1>; + assigned-clock-parents = <&k3_clks 39 2>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 1>; + assigned-clock-parents = <&k3_clks 40 2>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 1>; + assigned-clock-parents = <&k3_clks 41 2>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 1>; + assigned-clock-parents = <&k3_clks 42 2>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 1>; + assigned-clock-parents = <&k3_clks 43 2>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 44 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 44 1>; + assigned-clock-parents = <&k3_clks 44 2>; + power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 45 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 45 1>; + assigned-clock-parents = <&k3_clks 45 2>; + power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 46 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 46 1>; + assigned-clock-parents = <&k3_clks 46 2>; + power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 47 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 47 1>; + assigned-clock-parents = <&k3_clks 47 2>; + power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 38ddf0b3b8a0c..31336b0e290e5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -6,6 +6,51 @@ */ &cbass_mcu { + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 1>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; -- GitLab From 744545ffec14f74f26f57828afa685f6f4eadd9e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:20 -0500 Subject: [PATCH 023/926] arm64: dts: ti: k3-am642-sk: Fix mmc1 pinmux Fix the pinmux for pulldirection to get stable sdcard behavior. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 2e2d40da360a2..9a65f9b1c9ab6 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -224,14 +224,15 @@ led-7 { &main_pmx0 { main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < - AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ - AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ - AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ >; }; -- GitLab From 1d79ca01e62096e87686244cdf4864f338ccd200 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:21 -0500 Subject: [PATCH 024/926] arm64: dts: ti: k3-am642-sk: Enable main_i2c0 and eeprom Enable AT24C512C on the base board. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 9a65f9b1c9ab6..3e16942c0adde 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -251,6 +251,13 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -350,6 +357,18 @@ &main_uart1 { status = "reserved"; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; -- GitLab From c8da2f207168d2c93f7fa7bff92f6b395c342e4a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:22 -0500 Subject: [PATCH 025/926] arm64: dts: ti: k3-am642-sk: Describe main_uart1 pins Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3e16942c0adde..da4121b2e2c64 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -245,6 +245,15 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + main_usb0_pins_default: main-usb0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ @@ -355,6 +364,8 @@ &main_uart0 { &main_uart1 { /* main_uart1 is reserved for firmware usage */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- GitLab From 826b6679bd08694ad7a830eb30608c3e5a780941 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:23 -0500 Subject: [PATCH 026/926] arm64: dts: ti: k3-am642-sk: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index da4121b2e2c64..5bd69a8e8063d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -94,7 +94,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { }; }; - vusb_main: fixed-regulator-vusb-main5v0 { + vusb_main: regulator-0 { /* USB MAIN INPUT 5V DC */ compatible = "regulator-fixed"; regulator-name = "vusb_main5v0"; @@ -104,7 +104,7 @@ vusb_main: fixed-regulator-vusb-main5v0 { regulator-boot-on; }; - vcc_3v3_sys: fixedregulator-vcc-3v3-sys { + vcc_3v3_sys: regulator-1 { /* output of LP8733xx */ compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; @@ -115,7 +115,7 @@ vcc_3v3_sys: fixedregulator-vcc-3v3-sys { regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-2 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -127,7 +127,7 @@ vdd_mmc1: fixed-regulator-sd { gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; - com8_ls_en: regulator-1 { + com8_ls_en: regulator-3 { compatible = "regulator-fixed"; regulator-name = "com8_ls_en"; regulator-min-microvolt = <3300000>; @@ -139,7 +139,7 @@ com8_ls_en: regulator-1 { gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; }; - wlan_en: regulator-2 { + wlan_en: regulator-4 { /* output of SN74AVC4T245RSVR */ compatible = "regulator-fixed"; regulator-name = "wlan_en"; -- GitLab From cf3b25bc3cc0b66cfaae9614620228a5c2246ecb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:24 -0500 Subject: [PATCH 027/926] arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eeprom Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 39feea78a084e..6456cc6d739b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -233,6 +233,13 @@ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -335,6 +342,19 @@ &main_uart1 { status = "reserved"; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; -- GitLab From e3e1d9ab65ebbd95907b6951637cd6809c69afc7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:25 -0500 Subject: [PATCH 028/926] arm64: dts: ti: k3-am642-evm: Describe main_uart1 pins Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 6456cc6d739b2..a1ed102a69f18 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -215,6 +215,15 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ @@ -340,6 +349,8 @@ &main_uart0 { /* main_uart1 is reserved for firmware usage */ &main_uart1 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- GitLab From 61ee5572075dfc16b480103763091b603cb06aa1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:26 -0500 Subject: [PATCH 029/926] arm64: dts: ti: k3-am642-evm: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index a1ed102a69f18..9cf181d0199f8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -94,7 +94,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main DC jack */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -104,7 +104,7 @@ evm_12v0: fixedregulator-evm12v0 { regulator-boot-on; }; - vsys_5v0: fixedregulator-vsys5v0 { + vsys_5v0: regulator-1 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; @@ -115,7 +115,7 @@ vsys_5v0: fixedregulator-vsys5v0 { regulator-boot-on; }; - vsys_3v3: fixedregulator-vsys3v3 { + vsys_3v3: regulator-2 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; @@ -126,7 +126,7 @@ vsys_3v3: fixedregulator-vsys3v3 { regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-3 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -138,7 +138,7 @@ vdd_mmc1: fixed-regulator-sd { gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; }; - vddb: fixedregulator-vddb { + vddb: regulator-4 { compatible = "regulator-fixed"; regulator-name = "vddb_3v3_display"; regulator-min-microvolt = <3300000>; -- GitLab From aca16cefdd25cdcd284212f840b70b07101f2548 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:27 -0500 Subject: [PATCH 030/926] arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDR Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 9cf181d0199f8..3d0b473d5252f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -148,6 +148,20 @@ vddb: regulator-4 { regulator-boot-on; }; + vtt_supply: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; + vin-supply = <&vsys_3v3>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; @@ -338,6 +352,12 @@ AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; + + ddr_vtt_pins_default: ddr-vtt-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ + >; + }; }; &main_uart0 { -- GitLab From bb3d657872215942cf87dd194904a7543fce3cc4 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:28 -0500 Subject: [PATCH 031/926] arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliases Drop bootargs and add aliases based on base pinout of SK as per [1] and evm per [2]. Indices chosen attempt to maintain some level of consistency with existing aliases. While at this, drop a extra EoL. While this patch could be split, it seems trivial to add additional cleanup steps. [1] https://www.ti.com/lit/df/sprr432/sprr432.pdf [2] https://www.ti.com/lit/zip/swrr171 Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64.dtsi | 16 ---------------- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 15 +++++++++++++-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 60fe95b483120..d6262b5a0a104 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -19,22 +19,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &mcu_uart0; - serial1 = &mcu_uart1; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 3d0b473d5252f..3db740f78cd25 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -18,14 +18,25 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + serial3 = &main_uart3; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 5bd69a8e8063d..003cff9a27990 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -18,14 +18,24 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { -- GitLab From d525ef9c7f077bfa8202b4b47ca9242ab936a1dc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:18 -0500 Subject: [PATCH 032/926] arm64: dts: ti: k3-am62x-sk-common: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 976f8303c84f4..a61e8648f1894 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -25,7 +25,6 @@ aliases { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- GitLab From da4159a776593f802ee211ad4823f3aed31e5375 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:19 -0500 Subject: [PATCH 033/926] arm64: dts: ti: k3-am65*: Drop bootargs Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic. Cc: Jan Kiszka Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Acked-by: Jan Kiszka Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 96ac2b476b116..7d256a1638ff2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -21,7 +21,6 @@ aliases { chosen { stdout-path = "serial3:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02810000"; }; reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 592ab2b54cb3d..0d6fc89eba7a8 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -15,7 +15,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- GitLab From af2cda7df7769d3353170b6a72d73bc4ea703480 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:20 -0500 Subject: [PATCH 034/926] arm64: dts: ti: k3-j721e-*: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 - arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7db0603125aa2..c11c092c1ce0c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -17,7 +17,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; gpio_keys: gpio-keys { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index f650a7fd66b42..ad7b45aeed0ae 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -18,7 +18,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- GitLab From f920c49f1e46a99c410e2aaf486ffb7ce3d12270 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:21 -0500 Subject: [PATCH 035/926] arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0d39d6b8cc0ca..5506341aae21b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -17,7 +17,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; evm_12v0: fixedregulator-evm12v0 { -- GitLab From cf82a026f54f54c241903add9b9bdbeb2a449db0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:22 -0500 Subject: [PATCH 036/926] arm64: dts: ti: k3-j721s2-common-proc-board: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b4b9edfe2d12c..1299c715f34ca 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -16,7 +16,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000"; }; aliases { -- GitLab From 68dd81a75192248a2c29650d21da495069c74ffa Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 20:27:15 -0500 Subject: [PATCH 037/926] arm64: dts: ti: k3-am62a: Add general purpose timers Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 96 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 45 +++++++++++ 2 files changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 393a1a40b68b8..59d1199e43c94 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -177,6 +177,102 @@ main_pmx0: pinctrl@f4000 { pinctrl-single,function-mask = <0xffffffff>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 2bb813e784a25..50c94a55fe85b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -15,6 +15,51 @@ mcu_pmx0: pinctrl@4084000 { status = "disabled"; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; -- GitLab From 804702e4c2aa5eae4611e9389833631a6b22e913 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 20:27:16 -0500 Subject: [PATCH 038/926] arm64: dts: ti: k3-am62a: Add watchdog nodes Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 45 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 11 +++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 11 +++++ 3 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 59d1199e43c94..e43e64451bc17 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -697,6 +697,51 @@ main_mcan0: can@20701000 { status = "disabled"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti4: watchdog@e040000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e040000 0x00 0x100>; + clocks = <&k3_clks 205 0>; + power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 205 0>; + assigned-clock-parents = <&k3_clks 205 2>; + }; + epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 50c94a55fe85b..04599762c2b7d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -132,4 +132,15 @@ mcu_gpio0: gpio@4201000 { clock-names = "gpio"; status = "disabled"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 81d984414fd4a..d848eb24b5522 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -51,4 +51,15 @@ wkup_rtc0: rtc@2b1f0000 { wakeup-source; status = "disabled"; }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; }; -- GitLab From 3ae28642a110485f71091f0a631492e78b396b2b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:07 -0500 Subject: [PATCH 039/926] arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart and mcu_i2c Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0d6fc89eba7a8..20d1eeadd3f7a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -119,6 +119,15 @@ vdd_mmc1_sd: fixedregulator-sd { }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ @@ -155,6 +164,15 @@ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; }; + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ @@ -178,6 +196,13 @@ AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ + >; + }; }; &main_pmx0 { @@ -268,11 +293,14 @@ AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -304,7 +332,9 @@ pca9554: gpio@39 { &mcu_i2c0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_i2c0 { -- GitLab From ec1b54824f022a7e65d858abbe74f5d7effc9817 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:08 -0500 Subject: [PATCH 040/926] arm64: dts: ti: k3-am654-base-board: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 20d1eeadd3f7a..01c0f06b599ff 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -85,7 +85,7 @@ switch-6 { }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -95,7 +95,7 @@ evm_12v0: fixedregulator-evm12v0 { regulator-boot-on; }; - vcc3v3_io: fixedregulator-vcc3v3io { + vcc3v3_io: regulator-1 { /* Output of TPS54334 */ compatible = "regulator-fixed"; regulator-name = "vcc3v3_io"; @@ -106,7 +106,7 @@ vcc3v3_io: fixedregulator-vcc3v3io { vin-supply = <&evm_12v0>; }; - vdd_mmc1_sd: fixedregulator-sd { + vdd_mmc1_sd: regulator-2 { compatible = "regulator-fixed"; regulator-name = "vdd_mmc1_sd"; regulator-min-microvolt = <3300000>; -- GitLab From 5292f504827c56406975b463eda1270d144cf06f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:09 -0500 Subject: [PATCH 041/926] arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDR Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 01c0f06b599ff..30bb1c90d4257 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -116,6 +116,20 @@ vdd_mmc1_sd: regulator-2 { vin-supply = <&vcc3v3_io>; gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; }; + + vtt_supply: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_io>; + gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; + }; }; &wkup_pmx0 { @@ -128,6 +142,12 @@ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ >; }; + ddr_vtt_pins_default: ddr-vtt-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ -- GitLab From 282621ed6e790ccf7288c4c0aadbb34f1fe25c11 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:10 -0500 Subject: [PATCH 042/926] arm64: dts: ti: k3-am654-base-board: Add missing PMIC Add the missing vdd_mpu PMIC. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 30bb1c90d4257..91471f015f967 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -336,6 +336,19 @@ &wkup_i2c0 { pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + vdd_mpu: regulator@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-always-on; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + }; + pca9554: gpio@39 { compatible = "nxp,pca9554"; reg = <0x39>; -- GitLab From 895e2f4f9852e54c0e6d16ddea9882b9b2065eae Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:11 -0500 Subject: [PATCH 043/926] arm64: dts: ti: k3-am654-base-board: Add board detect eeprom Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 91471f015f967..92915870024d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -336,6 +336,12 @@ &wkup_i2c0 { pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; + vdd_mpu: regulator@60 { compatible = "ti,tps62363"; reg = <0x60>; -- GitLab From 692e8888a84357232574caba74f60ceea7364016 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:12 -0500 Subject: [PATCH 044/926] arm64: dts: ti: k3-am654-base-board: Add aliases Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 92915870024d2..0a018bcf57353 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -13,6 +13,20 @@ / { compatible = "ti,am654-evm", "ti,am654"; model = "Texas Instruments AM654 Base Board"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + i2c0 = &wkup_i2c0; + i2c1 = &mcu_i2c0; + i2c2 = &main_i2c0; + i2c3 = &main_i2c1; + i2c4 = &main_i2c2; + ethernet0 = &cpsw_port1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- GitLab From ffc449e016e269ce4d19e648bae584f8e5afd59f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:13 -0500 Subject: [PATCH 045/926] arm64: dts: ti: k3-am65: Drop aliases iot boards have always defined their own aliases and with the base-board defining it's own aliases, there are no pending boards depending on common aliases defined in SoC level. aliases are meant to be defined appropriately based on the exposed interfaces at a board level, drop the aliases defined at SoC level. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3093ef6b9b23f..4d7b6155a76b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -19,23 +19,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - ethernet0 = &cpsw_port1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { -- GitLab From 9b8c6da0b5850bd9645d0f9b4a892e69cb7ec662 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:43 +0200 Subject: [PATCH 046/926] arm64: dts: ti: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Acked-by: Nishanth Menon Link: https://lore.kernel.org/r/20230421223143.115099-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi index 4cc329b271aca..888567b921f0a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -113,6 +113,7 @@ L2_1: l2-cache1 { msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; thermal_zones: thermal-zones { diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index bbe380c72a7ec..f1836ec8e9340 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -95,6 +95,7 @@ L2_0: l2-cache0 { msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index b912143b6a110..c577f37394071 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -97,6 +97,7 @@ L2_0: l2-cache0 { msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 376924726f1f3..f3db277628cd0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -81,6 +81,7 @@ L2_0: l2-cache0 { msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { -- GitLab From 13fdc081fbe997fbd6addc8eafc240655c2fc7e8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 24 Apr 2023 09:49:43 -0500 Subject: [PATCH 047/926] arm64: dts: ti: k3-am65-main: Remove "syscon" nodes added for pcieX_ctrl Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230424144949.244135-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 27 ++++++------------------ 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 1adba2f2c1536..bc63d10bad5af 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -481,21 +481,6 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_mode: pcie-mode@4060 { - compatible = "syscon"; - reg = <0x00004060 0x4>; - }; - - pcie1_mode: pcie-mode@4070 { - compatible = "syscon"; - reg = <0x00004070 0x4>; - }; - - pcie_devid: pcie-devid@210 { - compatible = "syscon"; - reg = <0x00000210 0x4>; - }; - serdes0_clk: clock@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; @@ -883,8 +868,8 @@ pcie0_rc: pcie@5500000 { #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -900,7 +885,7 @@ pcie0_ep: pcie-ep@5500000 { reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; @@ -918,8 +903,8 @@ pcie1_rc: pcie@5600000 { #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -935,7 +920,7 @@ pcie1_ep: pcie-ep@5600000 { reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; -- GitLab From a1ca56099819f4b2c52bfe23b7be13b0d53a2a4a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 20:32:53 +0100 Subject: [PATCH 048/926] ARM: dts: exynos: drop simple-bus from FIMC in Exynos4 The FIMC camera node wrapper is not a bus, so using simple-bus fallback compatible just to instantiate its children nodes was never correct. Dropping simple-bus node fixes warnings: exynos4210-smdkv310.dtb: camera: $nodename:0: 'camera' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' The change is not backwards compatible and expects the FIMC driver to populate its children. Link: https://lore.kernel.org/r/20230207193254.550236-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 8dd6976ab0a71..4340253310415 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -201,8 +201,8 @@ dsi_0: dsi@11c80000 { #size-cells = <0>; }; - camera: camera { - compatible = "samsung,fimc", "simple-bus"; + camera: camera@11800000 { + compatible = "samsung,fimc"; status = "disabled"; #address-cells = <1>; #size-cells = <1>; -- GitLab From 0070e0fcc522aebe2461714074f7637cab70e688 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 20:32:54 +0100 Subject: [PATCH 049/926] ARM: dts: s5pv210: drop simple-bus from FIMC The FIMC camera node wrapper is not a bus, so using simple-bus fallback compatible just to instantiate its children nodes was never correct. The change is not backwards compatible and expects the FIMC driver to populate its children. Link: https://lore.kernel.org/r/20230207193254.550236-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 1a9e4a96b2ff7..cbc108217483c 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -547,8 +547,8 @@ i2c1: i2c@fab00000 { status = "disabled"; }; - camera: camera { - compatible = "samsung,fimc", "simple-bus"; + camera: camera@fa600000 { + compatible = "samsung,fimc"; pinctrl-names = "default"; pinctrl-0 = <>; clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; -- GitLab From 8a9e495b3a07e04a7d86d9c706a38e69863348ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 22:00:14 +0100 Subject: [PATCH 050/926] ARM: dts: exynos: Remove empty camera pinctrl configuration in Trats The camera's pinctrl configuration is simply empty and not effective. Remove it to fix dtbs_check warning: arch/arm/boot/dts/exynos4210-trats.dt.yaml: camera: pinctrl-0: True is not of type 'array' Link: https://lore.kernel.org/r/20230207210020.677007-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-trats.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index ff6ee4b2c31b5..bfb04b31e11b8 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -150,8 +150,6 @@ pmic_ap_clk: pmic-ap-clk { }; &camera { - pinctrl-names = "default"; - pinctrl-0 = <>; status = "okay"; }; -- GitLab From 5f7255459587c5f0297eaa2dfb551f936789b082 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 22:00:15 +0100 Subject: [PATCH 051/926] ARM: dts: exynos: Remove empty camera pinctrl configuration in Universal C210 The camera's pinctrl configuration is simply empty and not effective. Remove it to fix dtbs_check warning: arch/arm/boot/dts/exynos4210-universal_c210.dt.yaml: camera: pinctrl-0: True is not of type 'array' Link: https://lore.kernel.org/r/20230207210020.677007-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 8fe0d5d2be2d9..c84af3d27c1c5 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -197,9 +197,6 @@ hdmi_ddc: i2c-ddc { &camera { status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <>; }; &cpu0 { -- GitLab From 043dc30113758f6b18194227447979e100d3061f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 22:00:16 +0100 Subject: [PATCH 052/926] ARM: dts: exynos: Remove empty camera pinctrl configuration in Odroid X/U3 The camera's pinctrl configuration is simply empty and not effective. Remove it to fix dtbs_check warning: arch/arm/boot/dts/exynos4412-odroidx.dt.yaml: camera: pinctrl-0: True is not of type 'array' Link: https://lore.kernel.org/r/20230207210020.677007-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 45ef7b7ba7e0f..93ddbd4b0a189 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -122,8 +122,6 @@ &bus_mfc { &camera { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <>; }; &clock { -- GitLab From 7e98d368887c08a6cb79e79684f851e9bd9a3550 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 11:57:18 +0200 Subject: [PATCH 053/926] ARM: dts: s5pv210: align pin configuration nodes with bindings Bindings expect that pins in initial and sleep states nodes end with '-pin': s5pv210-fascinate4g.dtb: pinctrl@e0200000: sleep-state: 'gpa0-0', ... 'mp07-7' do not match any of the regexes: '^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20230421095721.31857-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 6d6daef9fb7a3..ae0b4a4237465 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -19,7 +19,7 @@ #include "s5pv210-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = ; \ samsung,pin-pud-pdn = ; \ -- GitLab From 64f92c24aa57f8bfc389fe6638f0ffb7e4605928 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 11:57:19 +0200 Subject: [PATCH 054/926] ARM: dts: s5pv210: align USB node name with bindings Bindings expect USB HSOTG controller node to be named "usb": s5pv210-torbreck.dtb: hsotg@ec000000: $nodename:0: 'hsotg@ec000000' does not match '^usb(@.*)?' Link: https://lore.kernel.org/r/20230421095721.31857-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index cbc108217483c..fbe7f3d17f419 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -401,7 +401,7 @@ sdhci3: mmc@eb300000 { status = "disabled"; }; - hsotg: hsotg@ec000000 { + hsotg: usb@ec000000 { compatible = "samsung,s3c6400-hsotg"; reg = <0xec000000 0x20000>; interrupt-parent = <&vic1>; -- GitLab From 6175f658ae07804f7c347903b8c6781e0914d3e6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 11:57:20 +0200 Subject: [PATCH 055/926] ARM: dts: s5pv210: re-order MFC clock names to match Exynos and bindings Align the order of two MFC clocks with Exynos4 DTS and MFC bindings Link: https://lore.kernel.org/r/20230328114729.61436-1-aakarsh.jain@samsung.com Link: https://lore.kernel.org/r/20230421095721.31857-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index fbe7f3d17f419..d9436bbf77c8d 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -452,8 +452,8 @@ mfc: codec@f1700000 { reg = <0xf1700000 0x10000>; interrupt-parent = <&vic2>; interrupts = <14>; - clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>; - clock-names = "sclk_mfc", "mfc"; + clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>; + clock-names = "mfc", "sclk_mfc"; }; vic0: interrupt-controller@f2000000 { -- GitLab From b77904ba177a9c67b6dbc3637fdf1faa22df6e5c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 11:57:21 +0200 Subject: [PATCH 056/926] ARM: dts: s5pv210: add dummy 5V regulator for backlight on SMDKv210 Backlight is supplied by DC5V regulator. The DTS has no PMIC node, so just add a regulator-fixed to solve it and fix dtbs_check warning: s5pv210-smdkv210.dtb: backlight: 'power-supply' is a required property Link: https://lore.kernel.org/r/20230421095721.31857-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index fbae768d65e27..6e26c67e0a26e 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -55,6 +55,14 @@ backlight { default-brightness-level = <6>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_out>; + power-supply = <&dc5v_reg>; + }; + + dc5v_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "DC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; -- GitLab From b8039b4e40094e81351221275ed61ee7643cdb91 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 21:02:02 +0200 Subject: [PATCH 057/926] ARM: dts: s5pv210: remove empty camera pinctrl configuration The camera's pinctrl configuration is simply empty and not effective. Remove it to fix dtbs_check warnings like: s5pv210-torbreck.dtb: camera@fa600000: pinctrl-0: True is not of type 'array' Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20230421190202.15471-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index d9436bbf77c8d..faa3682ab5dde 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -549,8 +549,6 @@ i2c1: i2c@fab00000 { camera: camera@fa600000 { compatible = "samsung,fimc"; - pinctrl-names = "default"; - pinctrl-0 = <>; clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; clock-names = "sclk_cam0", "sclk_cam1"; #address-cells = <1>; -- GitLab From 0709e55ed13e256994e440a4e0d62dc1cf3fc6a3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:08 +0200 Subject: [PATCH 058/926] arm64: dts: broadcom: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: bcm94908.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: William Zhang Link: https://lore.kernel.org/r/20230421223208.115555-1-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 + arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 + arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++ 9 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index 457805efb385e..f549bda8c48c7 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -64,6 +64,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index 46aa8c0b79719..d658c81f7285e 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -52,6 +52,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 7020f2e995e21..4f474d47022e2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -36,6 +36,7 @@ B53_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index 6a0242cbea571..909f254dc47d1 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -52,6 +52,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index 1a12905266ef9..685ae32951c9c 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -52,6 +52,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index f41ebc30666f2..820553ce541b4 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -36,6 +36,7 @@ B53_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index fa2688f41f069..0eb93c2982972 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -51,6 +51,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index e1b80e569cdfc..9dcd25ec2c041 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -80,6 +80,7 @@ A57_3: cpu@3 { CLUSTER0_L2: l2-cache@0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 388424b3e1d39..7aece79bf882b 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -109,21 +109,25 @@ cpu@301 { CLUSTER0_L2: l2-cache@0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache@100 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER2_L2: l2-cache@200 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER3_L2: l2-cache@300 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From 0db4bb045b038ee8c832d4f19013fd88e8d7fd05 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Apr 2023 17:09:43 +0200 Subject: [PATCH 059/926] ARM: dts: broadcom: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: bcm963148.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: William Zhang Link: https://lore.kernel.org/r/20230423150943.118576-1-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47622.dtsi | 1 + arch/arm/boot/dts/bcm63148.dtsi | 1 + arch/arm/boot/dts/bcm63178.dtsi | 1 + arch/arm/boot/dts/bcm6756.dtsi | 1 + arch/arm/boot/dts/bcm6846.dtsi | 1 + arch/arm/boot/dts/bcm6855.dtsi | 1 + arch/arm/boot/dts/bcm6878.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index cd25ed2757b70..7cd38de118c32 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -52,6 +52,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index ba7f265db1210..24431de1810ed 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -36,6 +36,7 @@ B15_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index d8268a1e889bb..3f9aed96babfc 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -44,6 +44,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index 49ecc1f0c18c5..1d8d957d65dd0 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -52,6 +52,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index fbc7d3a5dc5f1..cf92cf8c46933 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -36,6 +36,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 5e0fe26530f18..52d6bc89f9f82 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -44,6 +44,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 96529d3d4dc26..2c5d706bac7e3 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -36,6 +36,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From 915fac07f053418d0ab9075af64da2872ca8a7f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 3 May 2023 14:16:10 +0200 Subject: [PATCH 060/926] =?UTF-8?q?ARM:=20dts:=20BCM5301X:=20Relicense=20R?= =?UTF-8?q?afa=C5=82's=20code=20to=20the=20GPL=202.0+=20/=20MIT?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All BCM5301X device DTS files use dual licensing. Try the same for SoC. Introduce a new .dtsi file with a proper SPDX tag. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230503121611.1629-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- MAINTAINERS | 1 + arch/arm/boot/dts/bcm-ns.dtsi | 202 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 192 +----------------------------- 3 files changed, 205 insertions(+), 190 deletions(-) create mode 100644 arch/arm/boot/dts/bcm-ns.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e5..14ff30a251228 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4001,6 +4001,7 @@ M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: arch/arm/boot/dts/bcm-ns.dtsi F: arch/arm/boot/dts/bcm470* F: arch/arm/boot/dts/bcm5301* F: arch/arm/boot/dts/bcm953012* diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi new file mode 100644 index 0000000000000..21d672aba75a9 --- /dev/null +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include +#include +#include +#include + +/ { + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + ehci: usb@21000 { + #usb-cells = <0>; + + compatible = "generic-ehci"; + reg = <0x00021000 0x1000>; + interrupts = ; + phys = <&usb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@22000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0x00022000 0x1000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&gic>; + + xhci: usb@23000 { + #usb-cells = <0>; + + compatible = "generic-xhci"; + reg = <0x00023000 0x1000>; + interrupts = ; + phys = <&usb3_phy>; + phy-names = "usb"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + }; + }; + }; + + mdio: mdio@18003000 { + compatible = "brcm,iproc-mdio"; + reg = <0x18003000 0x8>; + #size-cells = <0>; + #address-cells = <1>; + }; + + dmu-bus@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru-bus@100 { + compatible = "brcm,ns-cru", "simple-mfd"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + usb2_phy: phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&cru_clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + cru_clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + + pinctrl: pinctrl@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + pinmux_i2c: i2c-pins { + groups = "i2c_grp"; + function = "i2c"; + }; + + pinmux_pwm: pwm-pins { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1-pins { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + coefficients = <(-556) 418000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 5fc1b847f4aa5..2aa3a9f09641c 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -8,11 +8,7 @@ * Licensed under the GNU/GPL. See COPYING for details. */ -#include -#include -#include -#include -#include +#include "bcm-ns.dtsi" / { #address-cells = <1>; @@ -149,12 +145,6 @@ periph_clk: periph_clk { }; axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; interrupt-map-mask = <0x000fffff 0xffff>; interrupt-map = @@ -228,108 +218,15 @@ axi@18000000 { <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - chipcommon: chipcommon@0 { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; + chipcommon@0 { interrupt-controller; #interrupt-cells = <2>; }; - pcie0: pcie@12000 { - reg = <0x00012000 0x1000>; - }; - - pcie1: pcie@13000 { - reg = <0x00013000 0x1000>; - }; - pcie2: pcie@14000 { reg = <0x00014000 0x1000>; }; - usb2: usb2@21000 { - reg = <0x00021000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - ehci: usb@21000 { - #usb-cells = <0>; - - compatible = "generic-ehci"; - reg = <0x00021000 0x1000>; - interrupts = ; - phys = <&usb2_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - ehci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ehci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - - ohci: usb@22000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; - reg = <0x00022000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - ohci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - - ohci_port2: port@2 { - reg = <2>; - #trigger-source-cells = <0>; - }; - }; - }; - - usb3: usb3@23000 { - reg = <0x00023000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupt-parent = <&gic>; - - xhci: usb@23000 { - #usb-cells = <0>; - - compatible = "generic-xhci"; - reg = <0x00023000 0x1000>; - interrupts = ; - phys = <&usb3_phy>; - phy-names = "usb"; - - #address-cells = <1>; - #size-cells = <0>; - - xhci_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; - }; - }; - gmac0: ethernet@24000 { reg = <0x24000 0x800>; }; @@ -355,13 +252,6 @@ pwm: pwm@18002000 { status = "disabled"; }; - mdio: mdio@18003000 { - compatible = "brcm,iproc-mdio"; - reg = <0x18003000 0x8>; - #size-cells = <0>; - #address-cells = <1>; - }; - mdio-mux@18003000 { compatible = "mdio-mux-mmioreg", "mdio-mux"; mdio-parent-bus = <&mdio>; @@ -409,18 +299,7 @@ i2c0: i2c@18009000 { }; dmu-bus@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - cru-bus@100 { - compatible = "brcm,ns-cru", "simple-mfd"; - reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - lcpll0: clock-controller@100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; @@ -440,53 +319,6 @@ genpll: clock-controller@140 { "usbclk", "iprocfast", "sata1", "sata2"; }; - - usb2_phy: phy@164 { - compatible = "brcm,ns-usb2-phy"; - reg = <0x164 0x4>; - brcm,syscon-clkset = <&cru_clkset>; - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; - clock-names = "phy-ref-clk"; - #phy-cells = <0>; - }; - - cru_clkset: syscon@180 { - compatible = "brcm,cru-clkset", "syscon"; - reg = <0x180 0x4>; - }; - - pinctrl: pinctrl@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; - - spi-pins { - groups = "spi_grp"; - function = "spi"; - }; - - pinmux_i2c: i2c-pins { - groups = "i2c_grp"; - function = "i2c"; - }; - - pinmux_pwm: pwm-pins { - groups = "pwm0_grp", "pwm1_grp", - "pwm2_grp", "pwm3_grp"; - function = "pwm"; - }; - - pinmux_uart1: uart1-pins { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - thermal: thermal@2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x2c0 0x10>; - #thermal-sensor-cells = <0>; - }; }; }; @@ -558,24 +390,4 @@ partitions { }; }; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - coefficients = <(-556) 418000>; - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <125000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; }; -- GitLab From 916553449561c4f0b61c71b751b7bb583f5dddd4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 3 May 2023 14:16:11 +0200 Subject: [PATCH 061/926] ARM: dts: BCM5301X: Relicense Florian's code to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All BCM5301X device DTS files use dual licensing. Try the same for SoC. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230503121611.1629-2-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 36 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 39 --------------------------------- 2 files changed, 36 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 21d672aba75a9..cc977bbc142b5 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -19,6 +19,8 @@ chipcommon: chipcommon@0 { gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; pcie0: pcie@12000 { @@ -109,6 +111,22 @@ xhci_port1: port@1 { }; }; }; + + gmac0: ethernet@24000 { + reg = <0x24000 0x800>; + }; + + gmac1: ethernet@25000 { + reg = <0x25000 0x800>; + }; + + gmac2: ethernet@26000 { + reg = <0x26000 0x800>; + }; + + gmac3: ethernet@27000 { + reg = <0x27000 0x800>; + }; }; mdio: mdio@18003000 { @@ -118,6 +136,24 @@ mdio: mdio@18003000 { #address-cells = <1>; }; + rng: rng@18004000 { + compatible = "brcm,bcm5301x-rng"; + reg = <0x18004000 0x14>; + }; + + srab: ethernet-switch@18007000 { + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; + reg = <0x18007000 0x1000>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + dmu-bus@1800c000 { compatible = "simple-bus"; ranges = <0 0x1800c000 0x1000>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 2aa3a9f09641c..2890fa3c5e67e 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -218,30 +218,9 @@ axi@18000000 { <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - chipcommon@0 { - interrupt-controller; - #interrupt-cells = <2>; - }; - pcie2: pcie@14000 { reg = <0x00014000 0x1000>; }; - - gmac0: ethernet@24000 { - reg = <0x24000 0x800>; - }; - - gmac1: ethernet@25000 { - reg = <0x25000 0x800>; - }; - - gmac2: ethernet@26000 { - reg = <0x26000 0x800>; - }; - - gmac3: ethernet@27000 { - reg = <0x27000 0x800>; - }; }; pwm: pwm@18002000 { @@ -322,24 +301,6 @@ genpll: clock-controller@140 { }; }; - srab: ethernet-switch@18007000 { - compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - - status = "disabled"; - - /* ports are defined in board DTS */ - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - rng: rng@18004000 { - compatible = "brcm,bcm5301x-rng"; - reg = <0x18004000 0x14>; - }; - nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; -- GitLab From d3c8e2c5757153bbfad70019ec1decbca86f3def Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 3 May 2023 14:28:30 +0200 Subject: [PATCH 062/926] ARM: dts: BCM5301X: Drop "clock-names" from the SPI node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no such property in the SPI controller binding documentation. Also Linux driver doesn't look for it. This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 2890fa3c5e67e..bc36edc245101 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -335,7 +335,6 @@ spi@18029200 { "spi_lr_session_done", "spi_lr_overread"; clocks = <&iprocmed>; - clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; -- GitLab From 79a8ec38d2d05963297cd9df316b77f978ebba66 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sun, 23 Apr 2023 14:39:12 +0200 Subject: [PATCH 063/926] ARM: dts: bcm23550: Add SoC-specific I2C compatible Add BCM23550-specific compatible for brcm,kona-i2c nodes. While not currently used by the i2c-bcm-kona driver, they can serve for further customization, if required. Done in preparation for dt-binding coversion to DT schema. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/9875ec0211187e4f5e2a4379c63eacdb69b31d7a.1682252615.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm23550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index a36c9b1d23c8e..32b244b8546c0 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -159,7 +159,7 @@ uartb3: serial@2000 { }; bsc1: i2c@16000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00016000 0x70>; interrupts = ; #address-cells = <1>; @@ -169,7 +169,7 @@ bsc1: i2c@16000 { }; bsc2: i2c@17000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00017000 0x70>; interrupts = ; #address-cells = <1>; @@ -179,7 +179,7 @@ bsc2: i2c@17000 { }; bsc3: i2c@18000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x00018000 0x70>; interrupts = ; #address-cells = <1>; @@ -189,7 +189,7 @@ bsc3: i2c@18000 { }; bsc4: i2c@1c000 { - compatible = "brcm,kona-i2c"; + compatible = "brcm,bcm23550-i2c", "brcm,kona-i2c"; reg = <0x0001c000 0x70>; interrupts = ; #address-cells = <1>; -- GitLab From cb3f4e8cacfa7b32ed8b9dff1282c0d4aaf42e88 Mon Sep 17 00:00:00 2001 From: Kelvin Zhang Date: Fri, 7 Apr 2023 18:27:04 +0800 Subject: [PATCH 064/926] dt-bindings: arm: amlogic: add C3 bindings Document the new C3 SoC/board device tree bindings. C3 is an advanced edge AI processor designed for smart IP camera applications, which does not belong to Meson series. Therefore, modify the title field accordingly. Signed-off-by: Kelvin Zhang Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230407102704.1055152-1-kelvin.zhang@amlogic.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 274ee0890312e..08d59842655c7 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amlogic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic MesonX +title: Amlogic SoC based Platforms maintainers: - Kevin Hilman @@ -205,6 +205,13 @@ properties: - amlogic,ad401 - const: amlogic,a1 + - description: Boards with the Amlogic C3 C302X/C308L SoC + items: + - enum: + - amlogic,aw409 + - amlogic,aw419 + - const: amlogic,c3 + - description: Boards with the Amlogic Meson S4 S805X2 SoC items: - enum: -- GitLab From d542ce8d4769cdef6a7bc3437e59cfed9c68f0e4 Mon Sep 17 00:00:00 2001 From: "hfdevel@gmx.net" Date: Fri, 7 Apr 2023 16:36:25 +0200 Subject: [PATCH 065/926] ARM: dts: meson8b: correct uart_B and uart_C clock references With the current device tree for meson8b, uarts B (e.g. available on pins 8/10 on Odroid-C1) and C (pins 3/5 on Odroid-C1) do not work, because they are relying on incorrect clocks. Change the references of pclk to the correct CLKID, to allow use of the two uarts. Fixes: 3375aa77135f ("ARM: dts: meson8b: Fix the UART device-tree schema validation") Signed-off-by: Hans-Frieder Vogt Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/trinity-bf20bcb9-790b-4ab9-99e3-0831ef8257f4-1680878185420@3c-app-gmx-bap55 Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8b.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 5979209fe91ef..5198f5177c2c1 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -740,13 +740,13 @@ &uart_A { &uart_B { compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; &uart_C { compatible = "amlogic,meson8b-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; -- GitLab From c2258a94fae556797085b58c0b6839c41826bd3d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:10 +0200 Subject: [PATCH 066/926] arm64: dts: amlogic: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 + 6 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index eed96f2628441..c8f344596285e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -37,6 +37,7 @@ cpu1: cpu@1 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b984950591e2f..768d0ed78dbe6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -106,6 +106,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index f58fd2a6fe61c..543e70669df54 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -51,6 +51,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 431572b384db9..86e6ceb31d5e2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -106,6 +106,7 @@ cpu103: cpu@103 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 11f89bfecb56a..2673f0dbafe76 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -133,6 +133,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 617d322af0df8..643f94d9d08e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -89,6 +89,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From b4354b9761437ba136329e3f2ea1386e8d483e1c Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Mon, 1 May 2023 21:55:21 +0200 Subject: [PATCH 067/926] ARM: dts: exynos: Move common Exynos4x12 definitions to exynos4x12.dtsi In preparation for the re-introduction of the Exynos4212, move their shared definitions to a separate file. Rename the pinctrl definitions accordingly, and adapt the Exynos4412 DTSI to these changes. This reverts part of commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"). Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230501195525.6268-10-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 644 +---------------- ...2-pinctrl.dtsi => exynos4x12-pinctrl.dtsi} | 4 +- arch/arm/boot/dts/exynos4x12.dtsi | 664 ++++++++++++++++++ 3 files changed, 670 insertions(+), 642 deletions(-) rename arch/arm/boot/dts/{exynos4412-pinctrl.dtsi => exynos4x12-pinctrl.dtsi} (99%) create mode 100644 arch/arm/boot/dts/exynos4x12.dtsi diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 82a36fb5ee8b7..8660c4c76e3a6 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -14,150 +14,11 @@ * nodes can be added to this file. */ -#include "exynos4.dtsi" - -#include "exynos4-cpu-thermal.dtsi" +#include "exynos4x12.dtsi" / { compatible = "samsung,exynos4412", "samsung,exynos4"; - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - - bus_acp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - }; - - bus_c2c: bus-c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - samsung,data-clock-ratio = <4>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - interconnects = <&bus_leftbus &bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - - bus_display_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - - bus_fsys_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - interconnects = <&bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - - bus_peri_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -297,499 +158,20 @@ cpu0_opp_1500: opp-1500000000 { turbo-mode; }; }; +}; - bus_dmc_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_leftbus_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - soc: soc { - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; - }; - - pinctrl_3: pinctrl@106e0000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106e0000 0x1000>; - interrupts = ; - }; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ca0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - l2c: cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; - - timer@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 5>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos4212-adc"; - reg = <0x126c0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122a0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123c0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, - <&isp_clock CLK_ISP_FIMC_LITE1>; - #iommu-cells = <0>; - }; - }; +&clock { + compatible = "samsung,exynos4412-clock"; }; &combiner { samsung,combiner-nr = <20>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123a0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123a0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE1>, - <&isp_clock CLK_ISP_PPMUISPX>, - <&isp_clock CLK_ISP_PPMUISPMX>, - <&isp_clock CLK_ISP_FIMC_ISP>, - <&isp_clock CLK_ISP_FIMC_DRC>, - <&isp_clock CLK_ISP_FIMC_FD>, - <&isp_clock CLK_ISP_MCUISP>, - <&isp_clock CLK_ISP_GICISP>, - <&isp_clock CLK_ISP_MCUCTL_ISP>, - <&isp_clock CLK_ISP_PWM_ISP>, - <&isp_clock CLK_ISP_DIV_ISP0>, - <&isp_clock CLK_ISP_DIV_ISP1>, - <&isp_clock CLK_ISP_DIV_MCUISP0>, - <&isp_clock CLK_ISP_DIV_MCUISP1>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK200>, - <&clock CLK_DIV_ACLK400_MCUISP>, - <&clock CLK_UART_ISP_SCLK>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "mpll", "aclk200", - "aclk400mcuisp", "div_aclk200", - "div_aclk400mcuisp", "uart"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; }; &gic { cpu-offset = <0x4000>; }; -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <875000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <900000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <950000>; - }; - opp-440000000 { - opp-hz = /bits/ 64 <440000000>; - opp-microvolt = <1025000>; - }; - }; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; - interconnects = <&bus_display &bus_dmc>; -}; - &pmu { interrupts = <2 2>, <3 2>, <18 2>, <19 2>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; @@ -798,22 +180,4 @@ &pmu { &pmu_system_controller { compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; }; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100c0000 0x100>; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; - -#include "exynos4412-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4412-pinctrl.dtsi rename to arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 8ab31c3daa481..9f7ea5f2a91ff 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device + * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. */ diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi new file mode 100644 index 0000000000000..84c1db221c984 --- /dev/null +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoC series device nodes are listed in this file. + * Particular SoCs from Exynos4x12 series can include this file and provide + * values for SoCs specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4.dtsi" + +#include "exynos4-cpu-thermal.dtsi" + +/ { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + fimc-lite0 = &fimc_lite_0; + fimc-lite1 = &fimc_lite_1; + }; + + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + }; + + bus_c2c: bus-c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-suspend; + }; + }; + + bus_leftbus_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + }; + + soc: soc { + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106e0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106e0000 0x1000>; + interrupts = ; + }; + + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + + pd_isp: power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ca0 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; + + l2c: cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + clock: clock-controller@10030000 { + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + + timer@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 5>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@10060000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + adc: adc@126c0000 { + compatible = "samsung,exynos4212-adc"; + reg = <0x126c0000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <10 3>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + g2d: g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; + }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + sysmmu_g2d: sysmmu@10a40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_isp: sysmmu@12260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 2>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_drc: sysmmu@12270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 3>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_fd: sysmmu@122a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122a0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 4>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@122b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 5>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite0: sysmmu@123b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@123c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123c0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 1>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; + #iommu-cells = <0>; + }; + }; +}; + +&combiner { + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + /* fimc_[0-3] are configured outside, under phandles */ + fimc_lite_0: fimc-lite@12390000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x12390000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite0>; + status = "disabled"; + }; + + fimc_lite_1: fimc-lite@123a0000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x123a0000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite1>; + status = "disabled"; + }; + + fimc_is: fimc-is@12000000 { + compatible = "samsung,exynos4212-fimc-is"; + reg = <0x12000000 0x260000>; + interrupts = , + ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, + <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>, + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; + clock-names = "lite0", "lite1", "ppmuispx", + "ppmuispmx", "isp", + "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", + "ispdiv0", "ispdiv1", "mcuispdiv0", + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; + iommu-names = "isp", "drc", "fd", "mcuctl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pmu@10020000 { + reg = <0x10020000 0x3000>; + }; + + i2c1_isp: i2c-isp@12140000 { + compatible = "samsung,exynos4212-i2c-isp"; + reg = <0x12140000 0x100>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; + clock-names = "i2c_isp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&exynos_usbphy { + compatible = "samsung,exynos4x12-usb2-phy"; + samsung,sysreg-phandle = <&sys_reg>; +}; + +&fimc_0 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_1 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_2 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + samsung,cam-if; +}; + +&fimc_3 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; +}; + +&gpu { + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <875000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <900000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <950000>; + }; + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <1025000>; + }; + }; +}; + +&hdmi { + compatible = "samsung,exynos4212-hdmi"; +}; + +&jpeg_codec { + compatible = "samsung,exynos4212-jpeg"; +}; + +&rotator { + compatible = "samsung,exynos4212-rotator"; +}; + +&mixer { + compatible = "samsung,exynos4212-mixer"; + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + interconnects = <&bus_display &bus_dmc>; +}; + +&pmu_system_controller { + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; +}; + +&tmu { + compatible = "samsung,exynos4412-tmu"; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + reg = <0x100c0000 0x100>; + clocks = <&clock CLK_TMU_APBIF>; + clock-names = "tmu_apbif"; + status = "disabled"; +}; + +#include "exynos4x12-pinctrl.dtsi" -- GitLab From 41bf1a9f9fbdec5dd1ba69fe26157f42e44dcee4 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Mon, 1 May 2023 21:55:22 +0200 Subject: [PATCH 068/926] ARM: dts: exynos: Re-introduce Exynos4212 DTSI Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit bca9085e0ae93253bc93ce218c85ac7d7e7f1831. Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230501195525.6268-11-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4212.dtsi | 157 ++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4212.dtsi diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi new file mode 100644 index 0000000000000..aa984601ee06d --- /dev/null +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 + * based board files can include this file and provide values for board specific + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4212", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4212-clock"; +}; + +&combiner { + samsung,combiner-nr = <18>; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon"; +}; -- GitLab From fd811cce9b92635799ba5c6de657e4a53c68adf6 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Mon, 1 May 2023 21:55:24 +0200 Subject: [PATCH 069/926] dt-bindings: arm: samsung: Add Samsung Galaxy Tab3 family boards Add the compatible strings for the Samsung Galaxy Tab 3 8.0 series of tablets. Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230501195525.6268-13-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/arm/samsung/samsung-boards.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index deb2cf9718718..e3ffd8159ab6c 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -72,6 +72,16 @@ properties: - const: samsung,exynos4210 - const: samsung,exynos4 + - description: Samsung Galaxy Tab3 family boards + items: + - enum: + - samsung,t310 # Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) + - samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311) + - samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315) + - const: samsung,tab3 + - const: samsung,exynos4212 + - const: samsung,exynos4 + - description: Exynos4412 based boards items: - enum: -- GitLab From 4eaa40bdabff8f5be634f151f8e564a8976f0572 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Mon, 8 May 2023 14:45:32 +0200 Subject: [PATCH 070/926] ARM: dts: bcm-mobile: align SDHCI node name with bindings Bindings expect SDHCI/MMC node names to be "mmc". Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/88c64da50a1af868d8b14054c440e5ff96a63399.1683548624.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm11351.dtsi | 8 ++++---- arch/arm/boot/dts/bcm21664-garnet.dts | 6 +++--- arch/arm/boot/dts/bcm21664.dtsi | 8 ++++---- arch/arm/boot/dts/bcm23550.dtsi | 8 ++++---- arch/arm/boot/dts/bcm28155-ap.dts | 4 ++-- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index ba75784d66a97..c30ff1b02e037 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -125,7 +125,7 @@ GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH interrupt-controller; }; - sdio1: sdio@3f180000 { + sdio1: mmc@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x10000>; interrupts = ; @@ -133,7 +133,7 @@ sdio1: sdio@3f180000 { status = "disabled"; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x10000>; interrupts = ; @@ -141,7 +141,7 @@ sdio2: sdio@3f190000 { status = "disabled"; }; - sdio3: sdio@3f1a0000 { + sdio3: mmc@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x10000>; interrupts = ; @@ -149,7 +149,7 @@ sdio3: sdio@3f1a0000 { status = "disabled"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x10000>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index cd03fa0c2aae4..dead91d97b632 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -20,18 +20,18 @@ serial@3e000000 { status = "okay"; }; - sdio1: sdio@3f180000 { + sdio1: mmc@3f180000 { max-frequency = <48000000>; status = "okay"; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { non-removable; max-frequency = <48000000>; status = "okay"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { max-frequency = <48000000>; cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index ed4de031e48ee..4e96656dc36a9 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -113,7 +113,7 @@ GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH interrupt-controller; }; - sdio1: sdio@3f180000 { + sdio1: mmc@3f180000 { compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x801c>; interrupts = ; @@ -121,7 +121,7 @@ sdio1: sdio@3f180000 { status = "disabled"; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x801c>; interrupts = ; @@ -129,7 +129,7 @@ sdio2: sdio@3f190000 { status = "disabled"; }; - sdio3: sdio@3f1a0000 { + sdio3: mmc@3f1a0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x801c>; interrupts = ; @@ -137,7 +137,7 @@ sdio3: sdio@3f1a0000 { status = "disabled"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x801c>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index 32b244b8546c0..e1a5f1b40ef5e 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -224,7 +224,7 @@ usbphy: usb-phy@e30000 { status = "disabled"; }; - sdio1: sdio@e80000 { + sdio1: mmc@e80000 { compatible = "brcm,kona-sdhci"; reg = <0x00e80000 0x801c>; interrupts = ; @@ -232,7 +232,7 @@ sdio1: sdio@e80000 { status = "disabled"; }; - sdio2: sdio@e90000 { + sdio2: mmc@e90000 { compatible = "brcm,kona-sdhci"; reg = <0x00e90000 0x801c>; interrupts = ; @@ -240,7 +240,7 @@ sdio2: sdio@e90000 { status = "disabled"; }; - sdio3: sdio@ea0000 { + sdio3: mmc@ea0000 { compatible = "brcm,kona-sdhci"; reg = <0x00ea0000 0x801c>; interrupts = ; @@ -248,7 +248,7 @@ sdio3: sdio@ea0000 { status = "disabled"; }; - sdio4: sdio@eb0000 { + sdio4: mmc@eb0000 { compatible = "brcm,kona-sdhci"; reg = <0x00eb0000 0x801c>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index 60c8ab8a28557..c496e33a71a61 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -44,7 +44,7 @@ pmu: pmu@8 { }; }; - sdio2: sdio@3f190000 { + sdio2: mmc@3f190000 { non-removable; max-frequency = <48000000>; vmmc-supply = <&camldo1_reg>; @@ -52,7 +52,7 @@ sdio2: sdio@3f190000 { status = "okay"; }; - sdio4: sdio@3f1b0000 { + sdio4: mmc@3f1b0000 { max-frequency = <48000000>; cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; vmmc-supply = <&sdldo_reg>; -- GitLab From 5668d088ee4ea05db9daaae0645d1d1f579b20f9 Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Mon, 3 Oct 2022 09:34:43 +0200 Subject: [PATCH 071/926] ARM: dts: kirkwood: Add Endian 4i Edge 200 board Add Endian 4i Edge 200 is 5-port firewall. It have also clone: Endian UTM Mini (The same hardware, with added WLAN card). Hardware: - SoC: Marvell 88F6281-A1 ARMv5TE Processor 1.2GHz - Ram: 512MB (4x Nanya NT5TU128M8GE-AC) - NAND Flash: 512MB (Micron 29F4G08AAC) - Lan 1-4: 4x GBE (Marvell 88E6171R-TFJ2) - Lan 5: 1x GBE (Marvell 88E1116R-NNC1) - Storage: MicroSD Slot - MCPIE: MiniPCIe Slot present [fitted with SparkLan WPEA-110N/E (Atheros AR9280 chipset) in Endian UTM Mini WLAN only] - USB: 1x USB 2.0 port - Console: RJ-45 port - LEDs: 3x GPIO controlled Signed-off-by: Pawel Dembicki Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-4i-edge-200.dts | 205 +++++++++++++++++++++ 2 files changed, 206 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-4i-edge-200.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..e0dd7dcdd5105 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -304,6 +304,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2g-evm.dtb \ keystone-k2g-ice.dtb dtb-$(CONFIG_MACH_KIRKWOOD) += \ + kirkwood-4i-edge-200.dtb \ kirkwood-b3.dtb \ kirkwood-blackarmor-nas220.dtb \ kirkwood-c200-v1.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-4i-edge-200.dts b/arch/arm/boot/dts/kirkwood-4i-edge-200.dts new file mode 100644 index 0000000000000..b1749d3f60b7b --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-4i-edge-200.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Endian 4i Edge 200 Board Description + * Note: Endian UTM Mini is hardware clone of Endian Edge 200 + * Copyright 2021-2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "Endian 4i Edge 200"; + compatible = "endian,4i-edge-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_SD; + color = ; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + speed = <1000>; + duplex = <1>; +}; + +ð1 { + status = "okay"; +}; + +ð1port { + phy-handle = <ðphyb>; +}; + +&mdio { + status = "okay"; + + ethphyb: ethernet-phy@b { + reg = <0x0b>; + + marvell,reg-init = + /* link-activity, bi-color mode 4 */ + <3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */ + }; + + switch0: switch@11 { + compatible = "marvell,mv88e6085"; + reg = <0x11>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "port4"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ð0port>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000a0000>; + read-only; + }; + + partition@a0000 { + label = "u-boot-env"; + reg = <0x000a0000 0x00060000>; + read-only; + }; + + partition@100000 { + label = "kernel"; + reg = <0x00100000 0x00400000>; + }; + + partition@500000 { + label = "ubi"; + reg = <0x00500000 0x1fb00000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_sysrst>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led: pmx-led { + marvell,pins = "mpp34", "mpp35", "mpp49"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&sdio { + pinctrl-0 = <&pmx_sdio_cd>; + pinctrl-names = "default"; + status = "okay"; + cd-gpios = <&gpio0 28 9>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; -- GitLab From cc386f5c670d58fbc41dc7ee8f2281aa74b58f9e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 16:15:18 +0100 Subject: [PATCH 072/926] ARM: dts: ste: align UART node name with bindings Bindings expect UART/serial node names to be "serial". Link: https://lore.kernel.org/r/20230123151519.369158-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 6 +++--- arch/arm/boot/dts/ste-href.dtsi | 6 +++--- arch/arm/boot/dts/ste-hrefprev60.dtsi | 2 +- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 2 +- arch/arm/boot/dts/ste-nomadik-s8815.dts | 2 +- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 6 +++--- arch/arm/boot/dts/ste-snowball.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-codina.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-gavini.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-kyle.dts | 6 +++--- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 6 +++--- 14 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index fead7afd55171..8d86d26a6dab8 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -852,7 +852,7 @@ spi3: spi@80129000 { status = "disabled"; }; - serial0: uart@80120000 { + serial0: serial@80120000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80120000 0x1000>; interrupts = ; @@ -868,7 +868,7 @@ serial0: uart@80120000 { status = "disabled"; }; - serial1: uart@80121000 { + serial1: serial@80121000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80121000 0x1000>; interrupts = ; @@ -884,7 +884,7 @@ serial1: uart@80121000 { status = "disabled"; }; - serial2: uart@80007000 { + serial2: serial@80007000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80007000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index e716121a78cee..13b11dbeba1c1 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -45,7 +45,7 @@ bat_therm: thermistor { }; soc { - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -53,13 +53,13 @@ uart@80120000 { }; /* This UART is unused and thus left disabled */ - uart@80121000 { + serial@80121000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; }; - uart@80007000 { + serial@80007000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; pinctrl-1 = <&u2rxtx_c_1_sleep>; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 29b67abfc461a..9859ee91a15ec 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -17,7 +17,7 @@ button@1 { soc { /* Enable UART1 on this board */ - uart@80121000 { + serial@80121000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 4d741adc16cd9..c8a86e69efd7e 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -190,7 +190,7 @@ nomadik_clcd: endpoint { }; /* Activate RX/TX and CTS/RTS on UART 0 */ - uart0: uart@101fd000 { + uart0: serial@101fd000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_nhk_mode>; status = "okay"; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index f16314ffbf4bd..c905c2643a120 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -133,7 +133,7 @@ stw4811@2d { amba { /* Activate RXTX on UART 0 */ - uart0: uart@101fd000 { + uart0: serial@101fd000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_s8815_mode>; status = "okay"; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 1815361fe73ce..6816eef39d450 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -769,7 +769,7 @@ vicb: interrupt-controller@10140020 { reg = <0x10140020 0x20>; }; - uart0: uart@101fd000 { + uart0: serial@101fd000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101fd000 0x1000>; interrupt-parent = <&vica>; @@ -782,7 +782,7 @@ uart0: uart@101fd000 { dma-names = "rx", "tx"; }; - uart1: uart@101fb000 { + uart1: serial@101fb000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101fb000 0x1000>; interrupt-parent = <&vica>; @@ -796,7 +796,7 @@ uart1: uart@101fb000 { dma-names = "rx", "tx"; }; - uart2: uart@101f2000 { + uart2: serial@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupt-parent = <&vica>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index e2f0cdacba7d1..9a3d6546399d7 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -308,7 +308,7 @@ mmc@80114000 { status = "okay"; }; - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -316,13 +316,13 @@ uart@80120000 { }; /* This UART is unused and thus left disabled */ - uart@80121000 { + serial@80121000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep>; }; - uart@80007000 { + serial@80007000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; pinctrl-1 = <&u2rxtx_c_1_sleep>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts index e036393d5415c..463942ae755ec 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -369,7 +369,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -393,7 +393,7 @@ bluetooth { }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -403,7 +403,7 @@ uart@80121000 { }; /* Debugging console UART connected to AB8505 */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 1a6d24a7ccb88..c1ae0e23fe459 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -462,7 +462,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -485,7 +485,7 @@ bluetooth { }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -505,7 +505,7 @@ gnss { }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 5b445fa4c8c08..b21e40da3dfdb 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -417,7 +417,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -439,7 +439,7 @@ bluetooth { }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -449,7 +449,7 @@ uart@80121000 { }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 9604695edf530..f736888474e7a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -186,7 +186,7 @@ mmc@80005000 { }; /* BT UART */ - uart@80120000 { + serial@80120000 { status = "okay"; pinctrl-names = "default", "sleep"; @@ -209,7 +209,7 @@ bluetooth { }; /* GPF UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; @@ -218,7 +218,7 @@ uart@80121000 { }; /* Debugging console UART */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index e901cb76b8997..6e586e875565a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -467,7 +467,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -491,7 +491,7 @@ bluetooth { }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; /* CTS/RTS is not used, CTS is repurposed as GPIO */ @@ -520,7 +520,7 @@ gnss { }; /* Debugging console UART connected to TSU6111RSVR (FSA880) */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 45fab5283a9d3..ba4421080b2a5 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -292,7 +292,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -310,7 +310,7 @@ bluetooth { }; /* GPF UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -333,7 +333,7 @@ gnss { }; /* Debugging console UART connected to AB8505 USB */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 93e5f5ed888d1..064d6fee88210 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -271,7 +271,7 @@ mmc@80005000 { }; /* GBF (Bluetooth) UART */ - uart@80120000 { + serial@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&u0_a_1_default>; pinctrl-1 = <&u0_a_1_sleep>; @@ -290,7 +290,7 @@ bluetooth { }; /* GPS UART */ - uart@80121000 { + serial@80121000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; @@ -313,7 +313,7 @@ gnss { }; /* Debugging console UART connected to AB8505 USB */ - uart@80007000 { + serial@80007000 { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&u2rxtx_c_1_default>; -- GitLab From 7c4f1f1830648bbdce02b13ff5f215c7400e7ea0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:41 +0100 Subject: [PATCH 073/926] arm64: dts: mba6ulx: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property. Link: https://lore.kernel.org/r/20230304123341.34223-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/mba6ulx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index 5bf831b072d6a..e25f8f209760d 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -57,7 +57,7 @@ power-button { label = "POWER"; linux,code = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; + wakeup-source; }; }; -- GitLab From 590db411752dd8ef6504113643fc6c4f68660ffd Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Thu, 11 May 2023 13:28:13 +0530 Subject: [PATCH 074/926] arm64: dts: qcom: ipq9574: Enable the download mode support Enable the support for download mode to collect the crashdumps if system crashes, to debug crashes extensively. Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230511075814.2370-2-quic_poovendh@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 3bb7435f5e7f0..4d41c011523fc 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -75,6 +75,13 @@ L2_0: l2-cache { }; }; + firmware { + scm { + compatible = "qcom,scm-ipq9574", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + memory@40000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -142,6 +149,11 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq9574", "syscon"; + reg = <0x01937000 0x21000>; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; -- GitLab From 46384ac7a61885ee29cf918777d5f81a6446e9e6 Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Thu, 11 May 2023 13:28:14 +0530 Subject: [PATCH 075/926] arm64: dts: qcom: ipq9574: Add SMEM support Add the required nodes to support SMEM Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230511075814.2370-3-quic_poovendh@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 4d41c011523fc..b65d94887e1ab 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -107,6 +107,13 @@ tz_region: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x400000>; no-map; }; + + smem@4aa00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4aa00000 0x0 0x00100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; }; soc: soc@0 { @@ -149,6 +156,12 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + tcsr: syscon@1937000 { compatible = "qcom,tcsr-ipq9574", "syscon"; reg = <0x01937000 0x21000>; -- GitLab From 80550562f6bb51304c9a762f0d56632e28191525 Mon Sep 17 00:00:00 2001 From: Parth Gajjar Date: Tue, 21 Mar 2023 00:06:18 -0700 Subject: [PATCH 076/926] dt-bindings: gpu: mali-utgard: Add xlnx,zynqmp-mali compatible Xilinx zynqmp SoC contains Mali400, so add its specific compatible to bindings. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230321070619.29440-2-parth.gajjar@amd.com Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index 318122d95eb5b..0fae1ef013be8 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -33,6 +33,7 @@ properties: - rockchip,rk3228-mali - samsung,exynos4210-mali - stericsson,db8500-mali + - xlnx,zynqmp-mali - const: arm,mali-400 - items: - enum: -- GitLab From 37e7894910cc0664b25259bd154e8093af9efdf7 Mon Sep 17 00:00:00 2001 From: Parth Gajjar Date: Tue, 21 Mar 2023 00:06:19 -0700 Subject: [PATCH 077/926] arm64: zynqmp: Add mali-400 gpu node for zynqmp Add mali-400 gpu node for zynqmp. Enabled gpu node for xilinx boards. Signed-off-by: Parth Gajjar Signed-off-by: Vishal Sagar Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 3 +++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 11 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 3e9979ab60bbc..5e7e1bf5b8115 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -95,6 +95,10 @@ &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; +&gpu { + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; +}; + &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 20e83ca47b5db..34412304d09fa 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -287,3 +287,7 @@ &gpio { "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; + +&gpu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index b05be25528265..f89ef2afcd9e5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -108,6 +108,9 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; &i2c1 { status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05a2b79738afb..6e0106bf12942 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -152,6 +152,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 6948fd40554b3..c74bc3ff703b8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -161,6 +161,10 @@ &gpio { "", "", "", ""; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; pinctrl-names = "default", "gpio"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5fd6b70a154a9..13c43324f1d24 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -216,6 +216,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index bd8f20f3223d7..485585c491f42 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -122,6 +122,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 96feaad301663..44ec9edd24527 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -127,6 +127,10 @@ &gpio { status = "okay"; }; +&gpu { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 24a252317150f..09773b7200f83 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -227,6 +227,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index d685d8fbc36a1..e0305dcbb010d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -187,6 +187,10 @@ &gpio { pinctrl-0 = <&pinctrl_gpio_default>; }; +&gpu { + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 153db59dc4b3e..bb0d0be30aa0e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -411,6 +411,18 @@ gic: interrupt-controller@f9010000 { interrupts = <1 9 0xf04>; }; + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; + reg = <0x0 0xfd4b0000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, + <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; + power-domains = <&zynqmp_firmware PD_GPU>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. -- GitLab From 6efb0b43ebe0dcf035da8656ecc4aa265c78b1da Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 May 2023 09:40:14 +0200 Subject: [PATCH 078/926] dt-bindings: arm: xilinx: Change zc1275 board name to zcu1275 Internal board zc1275 was released also to public which ends up with adding missing 'u' to board name. Reflect this change by renaming DT files. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4ba0eb85629ec5f07902a93fb75d13fff9697eb8.1683099606.git.michal.simek@amd.com --- Documentation/devicetree/bindings/arm/xilinx.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index 969cfe6dc4348..b3071d10ea654 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -61,10 +61,10 @@ properties: - const: xlnx,zynqmp-zc1254 - const: xlnx,zynqmp - - description: Xilinx internal board zc1275 + - description: Xilinx evaluation board zcu1275 items: - - const: xlnx,zynqmp-zc1275-revA - - const: xlnx,zynqmp-zc1275 + - const: xlnx,zynqmp-zcu1275-revA + - const: xlnx,zynqmp-zcu1275 - const: xlnx,zynqmp - description: Xilinx 96boards compatible board zcu100 -- GitLab From 370b0e900fb0f1c74cb1ecf9f92306b6e52039e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 May 2023 09:40:15 +0200 Subject: [PATCH 079/926] arm64: zynqmp: Change zc1275 board name to zcu1275 Internal board zc1275 was released also to public which ends up with adding missing 'u' to board name. Reflect this change by renaming DT files. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9b50c72c4e634b2c72758eed6275920eedbda06f.1683099606.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/Makefile | 2 +- .../{zynqmp-zc1275-revA.dts => zynqmp-zcu1275-revA.dts} | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/xilinx/{zynqmp-zc1275-revA.dts => zynqmp-zcu1275-revA.dts} (87%) diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 4e159540d0314..db0cc5733177e 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb @@ -17,6 +16,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts similarity index 87% rename from arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts rename to arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index e971ba8c14187..4874e0ad914e5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -14,8 +14,8 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevA"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; -- GitLab From a9d37bd427ba0c873ebeef6fbd74410669cb2c54 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Tue, 2 May 2023 15:53:35 +0200 Subject: [PATCH 080/926] ARM: zynq: dts: Setting default i2c clock frequency to 400kHz Setting default i2c clock frequency for Zynq to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4dde5d1eb8e4572dae4295a19a4c83002a58e5da.1683035611.git.michal.simek@amd.com --- arch/arm/boot/dts/zynq-7000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index cd9931f6bcbdc..a7db3f3009f2a 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -149,6 +149,7 @@ i2c0: i2c@e0004000 { clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -160,6 +161,7 @@ i2c1: i2c@e0005000 { clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; -- GitLab From a0bb549e60dc267bbd85d1b1948de8e7fc7f0928 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:51:01 +0200 Subject: [PATCH 081/926] Revert "arm64: dts: zynqmp: Add address-cells property to interrupt controllers" This reverts commit c6badbd2d321c19d4f55ee56b0ef12bb3352feac. Long time ago this was discussed with Rob at link below that there is no need to add address-cells to gpio and interrupt nodes that's why reverting this patch for ZynqMP. Also there is no visible DTC warning which was seen in past. Link: https://lore.kernel.org/r/91e3405245c89f134676449cf3822285798d2ed2.1612189652.git.michal.simek@xilinx.com Reviewed-by: Krzysztof Kozlowski Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e3312910db0922bb8c24a8e681de41709ca11bdf.1683035456.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index bb0d0be30aa0e..1a24029b106ec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -400,7 +400,6 @@ fpd_dma_chan8: dma-controller@fd570000 { gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; - #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, @@ -614,7 +613,6 @@ gem3: ethernet@ff0e0000 { gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; - #address-cells = <0>; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; -- GitLab From e2b96ceb554ec964e536dd443217d514684f6c49 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:02 +0200 Subject: [PATCH 082/926] arm64: dts: s32: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: s32g274a-evb.dtb: l2-cache1: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger Signed-off-by: Chester Lin Link: https://lore.kernel.org/r/20230421223202.115472-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index d8c82da88ca07..5ac1cc9ff50ed 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -53,11 +53,13 @@ cpu3: cpu@101 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 3e306218d5331..42409ec567925 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -62,11 +62,13 @@ cpu3: cpu@101 { cluster0_l2_cache: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From b1f8ac879346bd8415e405dd9b6c032007b3198e Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Fri, 7 Apr 2023 12:49:41 +0200 Subject: [PATCH 083/926] dt-bindings: arm: fsl: Add Marantec maveo box as a DHCOR i.MX6ULL SoM based board Add Marantec maveo box. The system is used to get a smart conntection to a door drive. The core of this system is a soldered i.MX6ULL DHCOR SoM from DH electronics. Signed-off-by: Christoph Niedermaier Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 15d4110840654..5acd859d4f7b0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -726,6 +726,12 @@ properties: - const: dh,imx6ull-dhcor-som - const: fsl,imx6ull + - description: i.MX6ULL DHCOR SoM based Boards + items: + - const: marantec,imx6ull-dhcor-maveo-box + - const: dh,imx6ull-dhcor-som + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: -- GitLab From 97dadebe5fa69a32b82fb64cfec87d2e8c63ed2e Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Fri, 7 Apr 2023 12:49:42 +0200 Subject: [PATCH 084/926] ARM: dts: imx6ull-dhcor: Remove mmc aliases from DHCOR SoM To be able to define mmc aliases correctly for a DHCOR board remove mmc aliases from the DHCOR SoM layer. All DHCOM SoM boards are based on the DHCOR SoM, as the DHCOR SoM is soldered on top of the DHCOM SoM. As a result, remove the mmc /delete-property/ entries from the aliases node in the DHCOM SoM layer, because this is already removed in the DHCOR SoM layer below. Signed-off-by: Christoph Niedermaier Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-dhcom-som.dtsi | 2 -- arch/arm/boot/dts/imx6ull-dhcor-som.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi index 17837663c0b0d..830b5a5064f28 100644 --- a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi @@ -7,8 +7,6 @@ / { aliases { - /delete-property/ mmc0; /* Avoid double definitions */ - /delete-property/ mmc1; /delete-property/ spi2; /delete-property/ spi3; i2c0 = &i2c2; diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi index 5882c7565f649..a386c1e9bed36 100644 --- a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi +++ b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi @@ -11,6 +11,11 @@ #include "imx6ull.dtsi" / { + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + }; + memory@80000000 { /* Appropriate memory size will be filled by U-Boot */ reg = <0x80000000 0>; -- GitLab From 145e2732a5e979f37a8dcb88b1ed6d3123213dea Mon Sep 17 00:00:00 2001 From: Christoph Niedermaier Date: Fri, 7 Apr 2023 12:49:43 +0200 Subject: [PATCH 085/926] ARM: dts: imx6ull-dhcor: Add Marantec maveo box Add support for Marantec maveo box. The system is used to get a smart conntection to a door drive. It has USB, WiFi, Bluetooth, Zigbee and NFC interfaces. The core of this system is a soldered i.MX6ULL DHCOR SoM from DH electronics. Signed-off-by: Christoph Niedermaier Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts | 359 ++++++++++++++++++ 2 files changed, 360 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..d6874f7900422 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -751,6 +751,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-dhcom-drc02.dtb \ imx6ull-dhcom-pdk2.dtb \ imx6ull-dhcom-picoitx.dtb \ + imx6ull-dhcor-maveo-box.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts b/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts new file mode 100644 index 0000000000000..047f7b2d85261 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023 DH electronics GmbH + * Copyright (C) 2023 Marantec electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG + * DHCOR PCB number: 578-200 or newer + * maveo box PCB number: 525-200 or newer + */ + +/dts-v1/; + +#include "imx6ull-dhcor-som.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOR on maveo box"; + compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som", + "fsl,imx6ull"; + + aliases { + mmc2 = &usdhc2; + spi0 = &ecspi4; + spi3 = &ecspi1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg1-vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg2-vbus"; + }; + + /* WiFi pin WL_REG_ON is connected to GPIO 5.9 */ + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; +}; + +/* BT pin BT_REG_ON is connected to GPIO 1.18 */ +&bluetooth { + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; +}; + +/* X10 connector */ +&ecspi4 { + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi4>; + pinctrl-names = "default"; + status = "okay"; + + spidev@0 { + compatible = "dh,dhcom-board"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <54000000>; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "BUTTON-USER", "", "", + "BUTTON-RESET", "", "", "", + "", "", "", "", + "", "", "BT-REG-ON", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "PSOC-GPIO-1", "", "", "X10-12", + "X10-10", "PSOC-GPIO-2", "PSOC-GPIO-3", "", + "X10-11", "X10-9", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "DHCOR-HW0", "DHCOR-HW1", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "MAVEO-BOX-HW0", "LED-G", "MAVEO-BOX-VAR1", + "MAVEO-BOX-VAR0", "MAVEO-BOX-HW1", "MAVEO-BOX-HW2", "LED-B", + "LED-R", "", "", "", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG", + "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE", + "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* Console UART */ +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* BT on LGA */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt_gpio>; +}; + +/* Zigbee UART */ +&uart3 { + pinctrl-0 = <&pinctrl_uart3 &pinctrl_snvs_zigbee_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "otg"; + hnp-disable; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; /* Overcurrent pin isn't connected */ + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbotg2>; + pinctrl-names = "default"; + tpl-support; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +/* WiFi on LGA */ +&usdhc1 { + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&pinctrl_usdhc1_wifi &pinctrl_snvs_wifi_gpio>; +}; + +/* eMMC */ +&usdhc2 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_hog_maveo_box: hog-maveo-box-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 /* BUTTON_USER */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x120b0 /* BUTTON_RESET */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x400120b0 /* LED_G */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x400120b0 /* LED_B */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x400120b0 /* LED_R */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x400120b0 /* X10_9 */ + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x400120b0 /* X10_10 */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x400120b0 /* X10_11 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x400120b0 /* X10_12 */ + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x400120b0 /* PSOC_GPIO_1 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x400120b0 /* PSOC_GPIO_2 */ + MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x400120b0 /* PSOC_GPIO_3 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x120b0 /* MAVEO_BOX_HW0 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x120b0 /* MAVEO_BOX_HW1 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x120b0 /* MAVEO_BOX_HW2 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x120b0 /* MAVEO_BOX_VAR0 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x120b0 /* MAVEO_BOX_VAR1 */ + MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x120b0 /* DHCOR_HW0 */ + MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x120b0 /* DHCOR_HW1 */ + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x120b0 + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x120b0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x120b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x120b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x120b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x120b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x120b0 + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x120b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x120b0 + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x120b0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x120b0 + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x120b0 + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x120b0 + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x120b0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x120b0 + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x120b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x120b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x120b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x120b0 + >; + }; + + pinctrl_bt_gpio: bt-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x400120b0 /* BT_REG_ON */ + >; + }; + + pinctrl_ecspi4: ecspi4-grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x120b0 /* USB_OTG1_PWR */ + >; + }; + + pinctrl_usbotg2: usbotg2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x120b0 /* USB_OTG2_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ + >; + }; +}; + +&iomuxc_snvs { + pinctrl-0 = <&pinctrl_snvs_hog_maveo_box>; + pinctrl-names = "default"; + + pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x400120b0 /* PSOC_SWD_IO */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x400120b0 /* PSOC_SWD_CLK */ + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x400120b0 /* PSOC_RESET */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x400120b0 /* PSOC_PWR_FAIL_OUT */ + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400120b0 /* NFC_ENABLE */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x400120b0 /* NFC_IRQ */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x120b0 /* DHCOR_BOOT_M0 */ + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x120b0 /* DHCOR_BOOT_M1 */ + >; + }; + + pinctrl_snvs_wifi_gpio: snvs-wifi-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400120b0 /* WL_REG_ON */ + >; + }; + + pinctrl_snvs_zigbee_gpio: snvs-zigbee-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x400120b0 /* ZIGBEE_PROG */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x400120b0 /* ZIGBEE_RESET */ + >; + }; +}; -- GitLab From 969dd087b9395298804c9fe2802fde6e67c888e4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:38 -0300 Subject: [PATCH 086/926] ARM: dts: imx7d-sdb: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index f483bc0afe5ea..25681c430393d 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -43,8 +43,8 @@ spi-4 { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; -- GitLab From b5ed9750483248f8b4da29f881b583ef0f43e716 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:39 -0300 Subject: [PATCH 087/926] ARM: dts: imx6ul-14x14-evk: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 7275a13664135..155515fe13fad 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -89,8 +89,8 @@ spi-4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; - gpio-sck = <&gpio5 11 0>; - gpio-mosi = <&gpio5 10 0>; + sck-gpios = <&gpio5 11 0>; + mosi-gpios = <&gpio5 10 0>; cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; -- GitLab From 48800d49c9976a73c8e184d0e288c058466931db Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:40 -0300 Subject: [PATCH 088/926] ARM: dts: imx51-zii-rdu1: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-miso', 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'miso-gpios', 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index e537e06e11d7e..3ddea42196f32 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -145,9 +145,9 @@ spi_gpio: spi { pinctrl-0 = <&pinctrl_gpiospi0>; status = "okay"; - gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; -- GitLab From b5b5d74068c59ded4e466daf5d9fe2767fb6330b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:41 -0300 Subject: [PATCH 089/926] ARM: dts: vf610-zii-dev-rev-b: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-miso', 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'miso-gpios', 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 6280c5e86a124..1fafefec77410 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -294,9 +294,9 @@ spi-0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; -- GitLab From 7aac4615ea0e7c7ea4e1a343b0f1da6822a2c53f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:42 -0300 Subject: [PATCH 090/926] ARM: dts: imx6ul-tx6ul: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-miso', 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'miso-gpios', 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 70cef5e817bd1..6bd90473050b0 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -218,9 +218,9 @@ spi_gpio: spi { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi_gpio>; - gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; cs-gpios = < &gpio1 29 GPIO_ACTIVE_HIGH -- GitLab From 49855ff5daa140bcdceb288978cd7cfc57594006 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:43 -0300 Subject: [PATCH 091/926] ARM: dts: imx28-tx28: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-miso', 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'miso-gpios', 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-tx28.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index ffe58c7093e1c..23ad7cd0a1de0 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -192,9 +192,9 @@ spi_gpio: spi { pinctrl-names = "default"; pinctrl-0 = <&tx28_spi_gpio_pins>; - gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; num-chipselects = <3>; cs-gpios = < &gpio2 27 GPIO_ACTIVE_LOW -- GitLab From 63a208bf7c372f1ec800c6f54215673362007b85 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 13:14:44 -0300 Subject: [PATCH 092/926] ARM: dts: imx28-cfa: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-miso', 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'miso-gpios', 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10049.dts | 10 +++++----- arch/arm/boot/dts/imx28-cfa10055.dts | 6 +++--- arch/arm/boot/dts/imx28-cfa10056.dts | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 94d6614c1983d..c5a7f56d83dbd 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -100,9 +100,9 @@ spi-2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10049>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; @@ -124,8 +124,8 @@ spi-3 { pinctrl-names = "default"; pinctrl-0 = <&spi3_pins_cfa10049>; status = "okay"; - gpio-sck = <&gpio0 24 0>; - gpio-mosi = <&gpio0 28 0>; + sck-gpios = <&gpio0 24 0>; + mosi-gpios = <&gpio0 28 0>; cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>; num-chipselects = <3>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index 42ba7da48beb9..70e225a99fbe7 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -19,9 +19,9 @@ spi-2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10055>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index 0e15bdfd7281c..bc2d6fcad12f9 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -18,9 +18,9 @@ spi-2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_cfa10056>; status = "okay"; - gpio-sck = <&gpio2 16 0>; - gpio-mosi = <&gpio2 17 0>; - gpio-miso = <&gpio2 18 0>; + sck-gpios = <&gpio2 16 0>; + mosi-gpios = <&gpio2 17 0>; + miso-gpios = <&gpio2 18 0>; cs-gpios = <&gpio3 5 0>; num-chipselects = <1>; #address-cells = <1>; -- GitLab From 5c9347e80b0ab2da6f1d5ec174378af40b25b3e6 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 8 Apr 2023 17:27:59 +0200 Subject: [PATCH 093/926] ARM: dts: imx51: ZII: Add missing phy-mode The DSA framework has got more picky about always having a phy-mode for the CPU port. The imx51 Ethernet supports MII, and RMII. Set the switch phy-mode based on how the SoC Ethernet port has been configured. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Andrew Lunn Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 2 +- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3ddea42196f32..5d4b29d765853 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -181,7 +181,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rev-mii"; ethernet = <&fec>; fixed-link { diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts index 21dd3f7abd488..625f9ac671ae9 100644 --- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -82,7 +82,7 @@ port@3 { port@4 { reg = <4>; - label = "cpu"; + phy-mode = "rev-mii"; ethernet = <&fec>; fixed-link { diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 9f857eb44bf72..19a3b142c9649 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -267,7 +267,6 @@ fixed-link { port@6 { reg = <6>; - label = "cpu"; phy-mode = "mii"; ethernet = <&fec>; -- GitLab From 0eea5c60c15fedd61dede52883745ab7e6a28562 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 8 Apr 2023 17:28:00 +0200 Subject: [PATCH 094/926] ARM: dts: imx6qdl: Add missing phy-mode and fixed links The DSA framework has got more picky about always having a phy-mode for the CPU port. Add a phy-mode based on what the SoC ethernet is using. For RGMII mode, have the switch add the delays. Additionally, the cpu label has never actually been used in the binding, so remove it. Lastly add a fixed-link node indicating the expected speed/duplex of the link to the SoC. Signed-off-by: Andrew Lunn Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 7 ++++++- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 9fc79af2bc9aa..9594bc5745ed6 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -238,8 +238,13 @@ port@3 { port@5 { reg = <5>; - label = "cpu"; ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 5bb47c79a4da2..abd72d72ae996 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -757,7 +757,7 @@ port@1 { port@2 { reg = <2>; - label = "cpu"; + phy-mode = "rev-rmii"; ethernet = <&fec>; fixed-link { -- GitLab From 1cce2b71ef7aa7e01f894c2c720fd7febda402c5 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 8 Apr 2023 17:28:01 +0200 Subject: [PATCH 095/926] arm64: dts: freescale: ZII: Add missing phy-mode The DSA framework has got more picky about always having a phy-mode for the CPU port. The imx8mq Ethernet is being configured to RMII. Set the switch phy-mode based on this. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Andrew Lunn Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 3a52679ecd68e..cb777b47baf9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -177,7 +177,7 @@ port@1 { port@2 { reg = <2>; - label = "cpu"; + phy-mode = "rev-rmii"; ethernet = <&fec1>; fixed-link { -- GitLab From 4e959380ba823cdf4e643ff247b8359e1bcbf683 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 12 May 2023 11:20:38 -0500 Subject: [PATCH 096/926] dt-bindings: arm: rockchip: add Anbernic RG353PS Add devicetree binding for Anbernic RG353PS. This device is identical to the RG353P, except it does not have a touchscreen, does not have an eMMC, only includes 1GB of RAM, and ships with only the 2nd revision panel based on a Sitronix ST7703 controller. Support for the panel has been added in a separate commit. Signed-off-by: Chris Morgan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230512162039.31132-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index b1d271778179e..6a7ef6fdd12cd 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -40,6 +40,11 @@ properties: - const: anbernic,rg353p - const: rockchip,rk3566 + - description: Anbernic RG353PS + items: + - const: anbernic,rg353ps + - const: rockchip,rk3566 + - description: Anbernic RG353V items: - const: anbernic,rg353v -- GitLab From 4d83538aab4ccb59abdbf7f39568761a8b7d7ea1 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 12 May 2023 11:20:39 -0500 Subject: [PATCH 097/926] arm64: dts: rockchip: add Anbernic RG353PS Add support for the Anbernic RG353PS. This device is identical in form factor to the RG353P and has the following hardware differences: - No touchscreen is present on i2c2 (or at all). - Only contains 1GB of RAM. - Has no eMMC. - Only appears to ship with the 2nd revision of the display panel. Note that the display panel has been added to the st7703 panel driver in a separate commit series. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20230512162039.31132-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3566-anbernic-rg353ps.dts | 116 ++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1cf105d7407f0..d83936bc589ce 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts new file mode 100644 index 0000000000000..b211973e36c21 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3566-anbernic-rg353x.dtsi" + +/ { + model = "RG353PS"; + compatible = "anbernic,rg353ps", "rockchip,rk3566"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdmmc2; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; +}; + +&gpio_keys_control { + button-r1 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; +}; + +&panel { + compatible = "anbernic,rg353v-panel-v2"; + iovcc-supply = <&vcc3v3_lcd0_n>; + vcc-supply = <&vcc3v3_lcd0_n>; + /delete-property/ vdd-supply; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; -- GitLab From 87c692fde46a511aa365d220588d0566125f4035 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 12 May 2023 14:16:33 -0500 Subject: [PATCH 098/926] arm64: dts: rockchip: Update leds for Anbernic RGxx3 Series Each of the LEDs on the RGxx3 which is currently controlled via GPIO can also be controlled via a PWM. Change each of the LEDs to PWM so that users have the ability to adjust the brightness of the LEDs according to their preference. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20230512191633.33416-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 39 +++++++++++-------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index 8fadd8afb1906..69f332738d247 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -191,30 +191,30 @@ hdmi_con_in: endpoint { }; }; - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; + leds: pwm-leds { + compatible = "pwm-leds"; green_led: led-0 { color = ; default-state = "on"; function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; }; amber_led: led-1 { color = ; function = LED_FUNCTION_CHARGING; - gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - retain-state-suspended; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; }; red_led: led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; }; }; @@ -597,15 +597,6 @@ btn_pins_vol: btn-pins-vol { }; }; - gpio-led { - led_pins: led-pins { - rockchip,pins = - <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - joy-mux { joy_mux_en: joy-mux-en { rockchip,pins = @@ -654,10 +645,24 @@ &pmu_io_domains { vccio7-supply = <&vcc_3v3>; }; +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pwm5 { status = "okay"; }; +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; -- GitLab From 8788595d66b9d6ac62d844af013edc3b393d8aef Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 13 May 2023 21:53:06 +0800 Subject: [PATCH 099/926] dt-bindings: arm: rockchip: add FriendlyARM NanoPi R2C Plus Add devicetree binding documentation for the NanoPi R2C Plus. Acked-by: Krzysztof Kozlowski Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230513135307.26554-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6a7ef6fdd12cd..f34af97b3c1b3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -194,6 +194,7 @@ properties: items: - enum: - friendlyarm,nanopi-r2c + - friendlyarm,nanopi-r2c-plus - friendlyarm,nanopi-r2s - const: rockchip,rk3328 -- GitLab From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 13 May 2023 21:53:07 +0800 Subject: [PATCH 100/926] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board eMMC flash (8G) included. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d83936bc589ce..50d97ae28b151 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts new file mode 100644 index 0000000000000..16a1958e45727 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-nanopi-r2c.dts" + +/ { + model = "FriendlyElec NanoPi R2C Plus"; + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; + + aliases { + mmc1 = &emmc; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io_33>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; -- GitLab From bcac467b7ca045224bd0f35e245b8edfcb1c452e Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Thu, 4 May 2023 23:06:48 +0300 Subject: [PATCH 101/926] arm64: dts: rockchip: Add rk3588 OTP node Add DT node for Rockchip RK3588/RK3588S OTP memory. Co-developed-by: Finley Xiao Signed-off-by: Finley Xiao Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll [moved cpu-version subnode down, to be sorted by address] Link: https://lore.kernel.org/r/20230504200648.1119866-9-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 944fbe0e8bdb4..afcd4e806cf72 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1839,6 +1839,60 @@ spi4: spi@fecb0000 { status = "disabled"; }; + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>; -- GitLab From 7cbfdc4ec908586968b84edf5c845ae5db57181b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 22:45:02 +0200 Subject: [PATCH 102/926] arm64: dts: imx8mq-mnt-reform2: drop invalid simple-panel compatible "simple-panel" compatible is not documented and nothing in Linux kernel binds to it: imx8mq-mnt-reform2.dtb: panel: compatible: ['innolux,n125hce-gn1', 'simple-panel'] is too long Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 200268660518d..3ae3824be0271 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -26,7 +26,7 @@ backlight: backlight { }; panel { - compatible = "innolux,n125hce-gn1", "simple-panel"; + compatible = "innolux,n125hce-gn1"; power-supply = <®_main_3v3>; backlight = <&backlight>; no-hpd; -- GitLab From e9f5cd85f1f931bb7b64031492f7051187ccaac7 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 14 Apr 2023 11:19:46 +0200 Subject: [PATCH 103/926] ARM: dts: imx: Adjust dma-apbh node name Currently the dtbs_check generates warnings like this: $nodename:0: 'dma-apbh@110000' does not match '^dma-controller(@.*)?$' So fix all affected dma-apbh node names. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23.dtsi | 2 +- arch/arm/boot/dts/imx28.dtsi | 2 +- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- arch/arm/boot/dts/imx6ul.dtsi | 2 +- arch/arm/boot/dts/imx7s.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index d19508c8f9ed6..a3668a0827fc8 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -59,7 +59,7 @@ icoll: interrupt-controller@80000000 { reg = <0x80000000 0x2000>; }; - dma_apbh: dma-apbh@80004000 { + dma_apbh: dma-controller@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; interrupts = <0 14 20 0 diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a8d3c3113e0f6..29e37b1fae66f 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -78,7 +78,7 @@ hsadc: hsadc@80002000 { status = "disabled"; }; - dma_apbh: dma-apbh@80004000 { + dma_apbh: dma-controller@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; interrupts = <82 83 84 85 diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b72ec745f6d12..bda182edc5891 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -150,7 +150,7 @@ soc: soc { interrupt-parent = <&gpc>; ranges; - dma_apbh: dma-apbh@110000 { + dma_apbh: dma-controller@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 93ac2380ca1ec..4233943a1cca8 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -209,7 +209,7 @@ gpu: gpu@1800000 { power-domains = <&pd_pu>; }; - dma_apbh: dma-apbh@1804000 { + dma_apbh: dma-controller@1804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = , diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 3d9d0f8235685..118764c50d921 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -164,7 +164,7 @@ intc: interrupt-controller@a01000 { <0x00a06000 0x2000>; }; - dma_apbh: dma-apbh@1804000 { + dma_apbh: dma-controller@1804000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index efe2525b62fa1..54026c2c93fac 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1257,7 +1257,7 @@ fec1: ethernet@30be0000 { }; }; - dma_apbh: dma-apbh@33000000 { + dma_apbh: dma-controller@33000000 { compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x33000000 0x2000>; interrupts = , -- GitLab From ac0d46d5e38b3d380f742181ee879561ce6bd2f1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 14 Apr 2023 11:19:47 +0200 Subject: [PATCH 104/926] ARM: dts: imx6ul: Add clock and PGC node to GPC According to fsl,imx-gpc.yaml the General Power Control requires a ipg clock and a Power Gating Control node. So add them to fix the dtbs_check warnings on i.MX6UL boards: gpc@20dc000: 'clocks' is a required property gpc@20dc000: 'clock-names' is a required property gpc@20dc000: 'pgc' is a required property Suggested-by: Jacky Bai Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 118764c50d921..0174f3edbd162 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -719,6 +719,18 @@ gpc: gpc@20dc000 { #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + clocks = <&clks IMX6UL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + }; }; iomuxc: pinctrl@20e0000 { -- GitLab From dae1b3fd06e8416fdfbc7440a62d5cd845c633a7 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Apr 2023 18:31:03 +0300 Subject: [PATCH 105/926] arm64: dts: imx8mp: Add CSIS DT nodes Add DT nodes for the two CSI-2 receivers of the i.MX8MP. Signed-off-by: Laurent Pinchart Reviewed-by: Paul Elder Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f81391993354f..5a0424aba28c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1342,6 +1342,66 @@ ldb_lvds_ch1: endpoint { }; }; + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + pcie_phy: pcie-phy@32f00000 { compatible = "fsl,imx8mp-pcie-phy"; reg = <0x32f00000 0x10000>; -- GitLab From 9da15c4c850dd53309e07d5611f33655f8f8c05d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Apr 2023 18:31:04 +0300 Subject: [PATCH 106/926] arm64: dts: imx8mp: Add ISI DT node Add a DT node for the i.MX8MP ISI instance, and model to connection to two CSI-2 receivers (CSIS). Signed-off-by: Laurent Pinchart Reviewed-by: Paul Elder Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5a0424aba28c1..8d26bd3ceb256 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1342,6 +1342,40 @@ ldb_lvds_ch1: endpoint { }; }; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + mipi_csi_0: csi@32e40000 { compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; @@ -1368,6 +1402,10 @@ port@0 { port@1 { reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; }; }; }; @@ -1398,6 +1436,10 @@ port@0 { port@1 { reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; }; }; }; -- GitLab From 6d81b2f20c191e82a4bd6272e9ef4ec485b35c63 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 21 Apr 2023 14:20:53 +0200 Subject: [PATCH 107/926] ARM: dts: mba6ulx: add missing vcc supplies to i2c devices This fixes the warnings: pca953x 3-0020: supply vcc not found, using dummy regulator pca953x 3-0021: supply vcc not found, using dummy regulator pca953x 3-0022: supply vcc not found, using dummy regulator at24 3-0051: supply vcc not found, using dummy regulator Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/mba6ulx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index 5bf831b072d6a..52684b2dbeb60 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -235,6 +235,7 @@ expander_out0: gpio-expander@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; }; expander_in0: gpio-expander@21 { @@ -248,6 +249,7 @@ expander_in0: gpio-expander@21 { #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; enet1_int-hog { gpio-hog; @@ -267,6 +269,7 @@ expander_out1: gpio-expander@22 { reg = <0x22>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <®_mba6ul_3v3>; }; analog_touch: touchscreen@41 { @@ -300,6 +303,7 @@ se97b: eeprom@51 { compatible = "nxp,se97b", "atmel,24c02"; reg = <0x51>; pagesize = <16>; + vcc-supply = <®_mba6ul_3v3>; }; }; -- GitLab From d2bd947176f855ea5a07fa9cce7bf15b0ce0467f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:04 +0200 Subject: [PATCH 108/926] arm64: dts: imx: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: imx8dxl-evk.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 70fadd79851a4..792b7224ca5b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -60,6 +60,7 @@ A35_1: cpu@1 { A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 32193a43ff49d..57627bdaa851b 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -52,6 +52,7 @@ A35_1: cpu@1 { A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From c290d09a998c810d11cca972810849fe7c2ec711 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:06 +0200 Subject: [PATCH 109/926] arm64: dts: freescale: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ 5 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 678bb0358751e..9cbb31191cf92 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -47,6 +47,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index b9fd24cdc919b..f8acbefc805b2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -85,6 +85,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index a01e3cfec77fb..50f68ca5a9af7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -80,6 +80,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1e5d76c4d83db..1aa38ed09aa4f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -96,21 +96,25 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index c12c86915ec87..8581ea55d2540 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -96,21 +96,25 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CPU_PW20: cpu-pw20 { -- GitLab From 4088f98e2580cc66d6cb7d1aaa5c92fb237a96bb Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 1 May 2023 13:02:50 -0400 Subject: [PATCH 110/926] arm64: dts: imx8mn-var-som: add SOM EEPROM The 4Kbit EEPROM located on the SOM contains hardware configuration options, manufacturing infos and ethernet MAC address. Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 67072e6c77d5f..682b8e08adcd8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -222,6 +222,12 @@ ldo6_reg: LDO6 { }; }; }; + + eeprom_som: eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + pagesize = <16>; + }; }; &i2c3 { -- GitLab From e6e81f10ca7455e9c8367c85d9f0bfac5b0c463f Mon Sep 17 00:00:00 2001 From: Johannes Schneider Date: Wed, 3 May 2023 17:20:04 +0200 Subject: [PATCH 111/926] dt-bindings: arm: fsl: Add i.MX8MM-EVKB Add DT compatible for the imx8mm EVKB [1]. [1] https://www.nxp.com/design/development-boards/ \ i-mx-evaluation-and-development-boards/ \ evaluation-kit-for-the-i-mx-8m-mini-applications-processor:8MMINILPD4-EVK Signed-off-by: Johannes Schneider [m.felsch@pengutronix.de: Adapt the commit message] [m.felsch@pengutronix.de: Adapt the yaml comment] Signed-off-by: Marco Felsch Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5acd859d4f7b0..ff73a23bbe490 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -907,6 +907,7 @@ properties: - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board + - fsl,imx8mm-evkb # i.MX8MM EVKB Board - gateworks,imx8mm-gw7904 - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit -- GitLab From b87f4ff57db90677f2c52b1c42c900b142231e00 Mon Sep 17 00:00:00 2001 From: Johannes Schneider Date: Wed, 3 May 2023 17:20:05 +0200 Subject: [PATCH 112/926] arm64: dts: add NXP i.MX8MM-EVKB support Add the i.MX8MM-EVKB [1] devicetree support. The EVKB is basically the same device except for the different used PMIC. [1] https://www.nxp.com/design/development-boards/ \ i-mx-evaluation-and-development-boards/ \ evaluation-kit-for-the-i-mx-8m-mini-applications-processor:8MMINILPD4-EVK Signed-off-by: Johannes Schneider [m.felsch@pengutronix.de: Adapt the commit message] [m.felsch@pengutronix.de: Include Shawns feedback] [m.felsch@pengutronix.de: Fix the regulator settings] Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mm-evkb.dts | 128 ++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-evkb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ef7d17aef58f0..0a6a646712a54 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts b/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts new file mode 100644 index 0000000000000..164df627a213a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-evkb.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019-2020 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dtsi" + +/ { + model = "FSL i.MX8MM EVKB"; + compatible = "fsl,imx8mm-evkb", "fsl,imx8mm"; +}; + +&i2c1 { + /delete-node/ pmic@4b; + + pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* VDD_SOC with PCIe */ + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-standby-voltage = <850000>; + }; + + /* VDD_GPU, VDD_VPU, VDD_DRAM */ + buck3_reg: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_3V3 */ + buck4_reg: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_1V8, NVCC_1V8, NVCC_ENET */ + buck5_reg: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_DRAM for LPDDR4 */ + buck6_reg: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_SNVS_1P8 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_SNVS_0P8 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_*_1V8 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* VDD_PHY_0V9 */ + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* NVCC_SD2 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; -- GitLab From 6de27598cf30bf0956731a3853b2def9fe22d8c5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 May 2023 08:42:55 +0200 Subject: [PATCH 113/926] ARM: dts: imx7ulp: add address/size-cells to OCOTP The OCOTP node should have address/size-cells so the cells can have unit address: imx7ulp-evk.dtb: efuse@410a6000: '#address-cells' is a required property imx7ulp-evk.dtb: efuse@410a6000: '#size-cells' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index f91bf719d4e2f..b01ddda7bd9e2 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -459,6 +459,8 @@ ocotp: efuse@410a6000 { compatible = "fsl,imx7ulp-ocotp", "syscon"; reg = <0x410a6000 0x4000>; clocks = <&scg1 IMX7ULP_CLK_DUMMY>; + #address-cells = <1>; + #size-cells = <1>; }; }; }; -- GitLab From ae9279f301b53e25a2b2635500fbd6f9b8249a61 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 7 May 2023 10:15:46 -0500 Subject: [PATCH 114/926] arm64: dts: imx8mn: Add CSI and ISI Nodes The CSI in the imx8mn is the same as what is used in the imx8mm, but it's routed to the ISI on the Nano. Add both the ISI and CSI nodes, and pointing them to each other. Since the CSI capture is dependent on an attached camera, mark both ISI and CSI as disabled by default. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index bd84db5500531..925b1637e38cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1117,6 +1117,30 @@ dsim_from_lcdif: endpoint { }; }; + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1145,6 +1169,42 @@ disp_blk_ctrl: blk-ctrl@32e28000 { #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; -- GitLab From 6bc3ea47332648a4211926ba7afc1e1fb935c71a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 7 May 2023 10:15:48 -0500 Subject: [PATCH 115/926] arm64: dts: imx8mn-beacon: Add support for OV5640 Camera The baseboard has a very specific pinout for the TD Next 5640 camera which uses an OV5640 sensor. Enable it as part of the deveopment kit baseboard instead of an overlay. Enable the camera with the following media-ctl -l "'ov5640 1-0010':0 -> 'csis-32e30000.mipi-csi':0 [1]" media-ctl -v -V "'ov5640 1-0010':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'crossbar':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'mxc_isi.0':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../freescale/imx8mn-beacon-baseboard.dtsi | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 9e82069c941fa..6dce77a6114c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -43,6 +43,17 @@ reg_audio: regulator-audio { enable-active-high; }; + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "vsd_3v3"; @@ -96,6 +107,36 @@ eeprom@0 { }; }; +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; &i2c4 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -145,11 +186,28 @@ wm8962: audio-codec@1a { }; }; +&isi { + status = "okay"; +}; + &easrc { fsl,asrc-rate = <48000>; status = "okay"; }; +&mipi_csi { + status = "okay"; + + ports { + port@0 { + mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -226,6 +284,14 @@ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 -- GitLab From b86c3afabb4f4ea146c206508527eb2a15485bcc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 May 2023 13:42:35 +0200 Subject: [PATCH 116/926] arm64: dts: imx8mp: Add SAI, SDMA, AudioMIX Add all SAI nodes, SDMA2 and SDMA3 nodes, and AudioMIX node. This is needed to get audio operational on i.MX8MP . Acked-by: Peng Fan Reviewed-by: Fabio Estevam Reviewed-by: Luca Ceresoli Reviewed-by: Marco Felsch Tested-by: Adam Ford #imx8mp-beacon-kit Tested-by: Alexander Stein Tested-by: Luca Ceresoli Tested-by: Richard Leitner Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 158 ++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8d26bd3ceb256..245c560674de7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -595,6 +595,13 @@ pgc_usb2_phy: power-domain@3 { reg = ; }; + pgc_audio: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI>; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = ; @@ -1167,6 +1174,157 @@ opp-1000000000 { }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + spba-bus@30c00000 { + compatible = "fsl,spba-bus", "simple-bus"; + reg = <0x30c00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sai1: sai@30c10000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c10000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai2: sai@30c20000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c20000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai3: sai@30c30000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c30000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai5: sai@30c50000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c50000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai6: sai@30c60000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c60000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + + sai7: sai@30c80000 { + compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; + reg = <0x30c80000 0x10000>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + interrupts = ; + status = "disabled"; + }; + }; + + sdma3: dma-controller@30e00000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e00000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + sdma2: dma-controller@30e10000 { + compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg = <0x30e10000 0x10000>; + #dma-cells = <3>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names = "ipg", "ahb"; + interrupts = ; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + audio_blk_ctrl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl"; + reg = <0x30e20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, + <&clk IMX8MP_CLK_SAI1>, + <&clk IMX8MP_CLK_SAI2>, + <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_CLK_SAI5>, + <&clk IMX8MP_CLK_SAI6>, + <&clk IMX8MP_CLK_SAI7>; + clock-names = "ahb", + "sai1", "sai2", "sai3", + "sai5", "sai6", "sai7"; + power-domains = <&pgc_audio>; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; -- GitLab From 9b4176ae2fc3b28fb41f882f24cd617d8a3be253 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 May 2023 13:42:36 +0200 Subject: [PATCH 117/926] arm64: dts: imx8mp: Add analog audio output on i.MX8MP EVK Enable SAI3 on i.MX8MP EVK, add WM8960 codec binding and regulator. This is all that is needed to get analog audio output operational on i.MX8MP EVK. Acked-by: Peng Fan Reviewed-by: Fabio Estevam Reviewed-by: Marco Felsch Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7816853162b3f..fa37ce89f8d3d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -40,6 +40,17 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audio_pwr_reg>; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; regulator-name = "can1-stby"; @@ -83,6 +94,37 @@ reg_usdhc2_vmmc: regulator-usdhc2 { gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8960-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "External Speaker", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "External Speaker", "SPK_LP", + "External Speaker", "SPK_LN", + "External Speaker", "SPK_RP", + "External Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "Mic Jack", "MICB"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8960>; + }; + + }; }; &flexspi { @@ -344,6 +386,18 @@ &i2c3 { pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + wm8960: codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + SPKVDD1-supply = <®_audio_pwr>; + }; + pca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; @@ -422,6 +476,16 @@ &pwm4 { status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -499,6 +563,12 @@ &wdog1 { }; &iomuxc { + pinctrl_audio_pwr_reg: audiopwrreggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -668,6 +738,16 @@ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 -- GitLab From b405d8d500e59e1edc51d934a766ea6127e1e69d Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 15:51:04 -0500 Subject: [PATCH 118/926] arm64: dts: qcom: sc8280xp: Add ethernet nodes This platform has 2 MACs integrated in it, go ahead and describe them. Reviewed-by: Konrad Dybcio Tested-by: Brian Masney Signed-off-by: Andrew Halaney Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501205105.2518373-2-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 60 ++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 8fa9fbfe5d000..a2320f8807954 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -768,6 +768,36 @@ soc: soc@0 { ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; + ethernet0: ethernet@20000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + iommus = <&apps_smmu 0x4c0 0xf>; + power-domains = <&gcc EMAC_0_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,gcc-sc8280xp"; reg = <0x0 0x00100000 0x0 0x1f0000>; @@ -4706,6 +4736,36 @@ dispcc1: clock-controller@22100000 { status = "disabled"; }; + + ethernet1: ethernet@23000000 { + compatible = "qcom,sc8280xp-ethqos"; + reg = <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + iommus = <&apps_smmu 0x40 0xf>; + power-domains = <&gcc EMAC_1_GDSC>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; }; sound: sound { -- GitLab From 57827e87be5447559cc3495567349ff002a6b33a Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 15:51:05 -0500 Subject: [PATCH 119/926] arm64: dts: qcom: sa8540p-ride: Add ethernet nodes Enable both the MACs found on the board. ethernet0 and ethernet1 both ultimately go to a series of on board switches which aren't managed by this processor. ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to the series of switches via SGMII on the "media" side of the phy. RGMII_SGMII mode is enabled via devicetree register descriptions. The switch on the "media" side has auto-negotiation disabled, so configuration from userspace similar to: ethtool -s eth0 autoneg off speed 1000 duplex full is necessary to get traffic flowing on that interface. ethernet1 is in a mac2mac/fixed-link configuration going to the same series of switches directly via RGMII. Tested-by: Brian Masney Signed-off-by: Andrew Halaney Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501205105.2518373-3-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 238 ++++++++++++++++++++++ 1 file changed, 238 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 24fa449d48a66..21e9eaf914dde 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -151,6 +151,184 @@ vreg_l8g: ldo8 { }; }; +ðernet0 { + snps,mtl-rx-config = <ðernet0_mtl_rx_setup>; + snps,mtl-tx-config = <ðernet0_mtl_tx_setup>; + + max-speed = <1000>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-txid"; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet0_default>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Marvell 88EA1512 */ + rgmii_phy: phy@8 { + reg = <0x8>; + + interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + + device_type = "ethernet-phy"; + + /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation + * from userspace to talk to the switch on the SGMII side of things + */ + marvell,reg-init = + /* Set MODE[2:0] to RGMII_SGMII */ + <0x12 0x14 0xfff8 0x4>, + /* Soft reset required after changing MODE[2:0] */ + <0x12 0x14 0x7fff 0x8000>; + }; + }; + + ethernet0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + ethernet0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + snps,mtl-rx-config = <ðernet1_mtl_rx_setup>; + snps,mtl-tx-config = <ðernet1_mtl_tx_setup>; + + max-speed = <1000>; + phy-mode = "rgmii-txid"; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet1_default>; + + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + ethernet1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + ethernet1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_default>; @@ -316,6 +494,66 @@ &xo_board_clk { /* PINCTRL */ &tlmm { + ethernet0_default: ethernet0-default-state { + mdc-pins { + pins = "gpio175"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio176"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188"; + function = "rgmii_0"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182"; + function = "rgmii_0"; + drive-strength = <16>; + bias-disable; + }; + }; + + ethernet1_default: ethernet1-default-state { + mdc-pins { + pins = "gpio97"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio98"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110"; + function = "rgmii_1"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104"; + function = "rgmii_1"; + drive-strength = <16>; + bias-disable; + }; + }; + i2c0_default: i2c0-default-state { /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ pins = "gpio135", "gpio136"; -- GitLab From 775d08f3954174c030d41bc31a145c027e98b7f7 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sat, 13 May 2023 08:05:04 +0700 Subject: [PATCH 120/926] dt-bindings: arm: qcom: Add Fxtec Pro1X Document F(x)tec Pro1X as a SM6115 device. Signed-off-by: Dang Huynh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230505-fxtec-pro1x-support-v3-1-0c9c7f58b205@riseup.net --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d9dd25695c3dd..767e4c22f7617 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -882,6 +882,11 @@ properties: - const: qcom,qrb4210 - const: qcom,sm4250 + - items: + - enum: + - fxtec,pro1x + - const: qcom,sm6115 + - items: - enum: - lenovo,j606f -- GitLab From 0e59d9e210912e037ec28bd057d06481100f0ba5 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Sat, 13 May 2023 08:05:05 +0700 Subject: [PATCH 121/926] arm64: dts: qcom: Add Fxtec Pro1X (QX1050) DTS The F(x)tec Pro1X is a mobile phone released by FX Technologies Ltd in 2022. The phone is exactly the same as the Pro1 released in 2019 with some changes: - MSM8998 -> SM6115 - Camera button is no longer multistate - Only one 48MP back camera - A new keyboard layout picked by the community. This commit has the following features working: - Display (using simplefb) - UFS - Power and volume buttons - Pinctrl - RPM Regulators - USB (Device Mode) To get a successful boot run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/\ sm6115-fxtec-pro1x.dtb > .Image.gz-dtb mkbootimg --kernel .Image.gz-dtb \ --ramdisk initrd.img \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --second_offset 0xf00000 \ --tags_offset 0x100 \ --pagesize 4096 \ --cmdline "CMDLINE HERE" \ -o qx1050-boot.img fastboot flash boot qx1050-boot.img fastboot erase dtbo fastboot reboot Signed-off-by: Dang Huynh Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230505-fxtec-pro1x-support-v3-2-0c9c7f58b205@riseup.net --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm6115-fxtec-pro1x.dts | 250 ++++++++++++++++++ 2 files changed, 251 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d42c59572ace0..e311ba675f359 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts new file mode 100644 index 0000000000000..3ce9875e932c7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Dang Huynh + */ + +/dts-v1/; + +#include "sm6115.dtsi" +#include "pm6125.dtsi" +#include + +/ { + model = "F(x)tec Pro1X (QX1050)"; + compatible = "fxtec,pro1x", "qcom,sm6115"; + chassis-type = "handset"; + + qcom,msm-id = ; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x5c000000 0x0 (1080 * 2160 * 4)>; + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&dispcc { + /* HACK: disable until a panel driver is ready to retain simplefb */ + status = "disabled"; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s6a: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + pm6125_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + pm6125_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + pm6125_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + pm6125_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + pm6125_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + regulator-allow-set-load; + }; + + pm6125_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + pm6125_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + pm6125_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + pm6125_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + pm6125_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l23a: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + regulator-allow-set-load; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&pm6125_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&pm6125_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&pm6125_l4a>; + vdda-pll-supply = <&pm6125_l12a>; + vddp-ref-clk-supply = <&pm6125_l18a>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + +&usb_hsphy { + vdd-supply = <&pm6125_l4a>; + vdda-pll-supply = <&pm6125_l12a>; + vdda-phy-dpdm-supply = <&pm6125_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; -- GitLab From 86c96823d4b5f0403d0418b89c614682a01ce28e Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Fri, 14 Apr 2023 14:30:16 +0200 Subject: [PATCH 122/926] arm64: dts: qcom: sa8775p: add the PMU node Add the PMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230414123016.176457-1-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2343df7e0ea4f..3f3e584bff062 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -288,6 +288,11 @@ opp-100000000 { }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; -- GitLab From be543efeee17b93edaac61e49c6361d2209bd3d3 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 11 Apr 2023 15:04:45 +0200 Subject: [PATCH 123/926] arm64: dts: qcom: sa8775p: add UFS nodes Add nodes for the UFS and its PHY on sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230411130446.401440-5-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3f3e584bff062..8a0e53fae24e0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -590,6 +590,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + iommus = <&apps_smmu 0x100 0x0>; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sa8775p-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; -- GitLab From 35c45a1125fc0772b95aa41acc25deddcf5492be Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 11 Apr 2023 15:04:46 +0200 Subject: [PATCH 124/926] arm64: dts: qcom: sa8775p-ride: enable UFS Enable the UFS and its PHY on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230411130446.401440-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index f238a02a54480..2bb001a3ea55a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "sa8775p.dtsi" @@ -20,6 +21,7 @@ aliases { serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; + ufshc1 = &ufs_mem_hc; }; chosen { @@ -426,6 +428,23 @@ &uart17 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; -- GitLab From 2dba7a613a6ea4c2f97abd770262f64ce53f7575 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 17 Apr 2023 14:58:41 +0200 Subject: [PATCH 125/926] arm64: dts: qcom: sa8775p: add the pcie smmu node Add the PCIe SMMU node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417125844.400782-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 8a0e53fae24e0..30ef360b38da7 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -872,6 +872,80 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ -- GitLab From 597cfc178829ac2e6f68736ec73417968a0810a5 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 17 Apr 2023 14:58:42 +0200 Subject: [PATCH 126/926] arm64: dts: qcom: sa8775p: add the GPU clock controller node Add the GPUCC node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417125844.400782-4-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 30ef360b38da7..1b2ceb5e43823 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -654,6 +654,20 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- GitLab From 1a1ff00c1626c898feb8ceb93aa7b335a9923980 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 17 Apr 2023 14:58:44 +0200 Subject: [PATCH 127/926] arm64: dts: qcom: sa8775p: add the GPU IOMMU node Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417125844.400782-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 1b2ceb5e43823..badabf79c6efa 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -668,6 +669,42 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- GitLab From 40d5835998705c28b985b1325114114c6007546e Mon Sep 17 00:00:00 2001 From: Parikshit Pareek Date: Mon, 17 Apr 2023 16:55:34 +0200 Subject: [PATCH 128/926] arm64: dts: qcom: sa8775p: pmic: remove the PON modes On this PMIC, the PON peripheral does not provide passing reboot modes over HLOS. They must be passed over SDAM. Remove the reboot-mode properties as we'll provide a proper SDAM node in a later commit. Fixes: d2d9a592746c ("arm64: dts: qcom: sa8775p: add the Power On device node") Signed-off-by: Parikshit Pareek Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417145536.414490-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 7602cca47baec..5abdc239d3a67 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -108,8 +108,6 @@ pmm8654au_0_pon: pon@1200 { compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>; reg-names = "hlos", "pbs"; - mode-recovery = <0x1>; - mode-bootloader = <0x2>; pmm8654au_0_pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; -- GitLab From 6c92689a0a57b40c758a12c1ca668d6a36a805a6 Mon Sep 17 00:00:00 2001 From: Parikshit Pareek Date: Mon, 17 Apr 2023 16:55:36 +0200 Subject: [PATCH 129/926] arm64: dts: qcom: sa8775p: pmic: add the sdam_0 node Introduce sdam_0 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reaons supported via sdam_0 node. Signed-off-by: Parikshit Pareek Signed-off-by: Bartosz Golaszewski Tested-by: Eric Chanudet Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417145536.414490-4-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 5abdc239d3a67..3c3b6287cd274 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -88,6 +88,14 @@ trip1 { }; }; }; + + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; }; &spmi_bus { @@ -133,6 +141,19 @@ pmm8654au_0_gpios: gpio@8800 { interrupt-controller; #interrupt-cells = <2>; }; + + pmm8654au_0_sdam_0: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; }; pmm8654au_1: pmic@2 { -- GitLab From 09b701b89a761e5e9566d65326d5fe0e94eaa48f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 27 Apr 2023 18:12:18 +0200 Subject: [PATCH 130/926] arm64: dts: qcom: sa8775p: add the watchdog node Now that the hypervisor issue is fixed, we can add the watchdog node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230427161218.201828-1-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index badabf79c6efa..0737ba38fefe1 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1008,6 +1008,13 @@ intc: interrupt-controller@17a00000 { redistributor-stride = <0x0 0x20000>; }; + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; + reg = <0x0 0x17c10000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + memtimer: timer@17c20000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; -- GitLab From de1001525c1aa21380349ffbef8154149ef637e8 Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 28 Apr 2023 18:38:23 +0530 Subject: [PATCH 131/926] arm64: dts: qcom: sa8775p: add USB nodes Add nodes for the USB and it's PHY on sa8775p platform. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230428130824.23803-6-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 239 +++++++++++++++++++++++++- 1 file changed, 237 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 0737ba38fefe1..fa3a2a42b8721 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -455,8 +455,8 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, + <&usb_0_qmpphy>, + <&usb_1_qmpphy>, <0>, <0>, <0>, @@ -649,6 +649,241 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + usb_0_hsphy: phy@88e4000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e4000 0 0x120>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0_qmpphy: phy@88e8000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088e8000 0 0x2000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0: usb@a6f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x080 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_1_hsphy: phy@88e6000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e6000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@88ea000 { + compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; + reg = <0 0x088ea000 0 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "pipe"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", "phy_phy"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1: usb@a8f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_EDGE_RISING>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x0a0 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2_hsphy: phy@88e7000 { + compatible = "qcom,sa8775p-usb-hs-phy", + "qcom,usb-snps-hs-5nm-phy"; + reg = <0 0x088e7000 0 0x120>; + clocks = <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref"; + resets = <&gcc GCC_USB3_PHY_TERT_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_2: usb@a4f8800 { + compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xe000>; + interrupts = ; + iommus = <&apps_smmu 0x020 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; -- GitLab From 4eefaf51f716be584bbc4f548d368255c682a3b9 Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 28 Apr 2023 18:38:24 +0530 Subject: [PATCH 132/926] arm64: dts: qcom: sa8775p-ride: enable USB nodes Enable usb0, usb1 and usb2 nodes and their respective phy's. Signed-off-by: Shazad Hussain Reviewed-by: Dmitry Baryshkov Tested-by: Adrien Thierry Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230428130824.23803-7-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 92 +++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 2bb001a3ea55a..4c000a5cb3c4b 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -293,6 +293,13 @@ &pmm8654au_1_gpios { "BT_EN", "USB2_PWR_EN", "USB2_FAULT"; + + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; }; &pmm8654au_2_gpios { @@ -308,6 +315,20 @@ &pmm8654au_2_gpios { "USB1_PWR_ENABLE", "USB1_FAULT", "VMON_SPX8"; + + usb0_en_state: usb0-en-state { + pins = "gpio3"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb1_en_state: usb1-en-state { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; }; &pmm8654au_3_gpios { @@ -445,6 +466,77 @@ &ufs_mem_phy { status = "okay"; }; +&usb_0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_state>; + + status = "okay"; +}; + +&usb_0_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_state>; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; -- GitLab From d3db273c8a11f377d867c49f95c7e7dc6ae26184 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 4 May 2023 18:17:55 +0200 Subject: [PATCH 133/926] arm64: dts: qcom: sa8775p: enable AOSS Enable the always-on subsystem controller on SA8775P platforms for use by upcoming support for other peripherals. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230504161755.197417-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index fa3a2a42b8721..a71b745f7a346 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -987,6 +988,16 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells = <0>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, -- GitLab From e10094bf590696a7f845790485cc3f753b2fd94a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Apr 2023 10:08:15 +0200 Subject: [PATCH 134/926] arm64: dts: qcom: sm8150: drop incorrect serial properties Drop incorrect and unused serial properties - address/size-cells and reg-names: sa8155p-adp.dtb: geniqup@ac0000: serial@a84000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'reg-names' were unexpected) Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417080818.28398-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2273fa5719884..8e550f1043141 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1353,14 +1353,11 @@ spi9: spi@a84000 { uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a84000 0x0 0x4000>; - reg-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart9_default>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; -- GitLab From 83254172fa7f4d4a400f2ff441f111e424dd5ee0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Apr 2023 10:09:37 +0200 Subject: [PATCH 135/926] arm64: dts: qcom: sm8150: add missing qcom,smmu-500 fallback Since commit 6c84bbd103d8 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417080939.28648-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8e550f1043141..7c12db60a22c8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3974,7 +3974,7 @@ spmi_bus: spmi@c440000 { }; apps_smmu: iommu@15000000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; -- GitLab From 7df522338d63c42946eb82f8af7dba8c363bd725 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Apr 2023 10:09:38 +0200 Subject: [PATCH 136/926] arm64: dts: qcom: sm8150: drop snps,dw-pcie fallback compatible Qualcomm PCI express root complex does not use snps,dw-pcie fallback: ['qcom,pcie-sm8150', 'snps,dw-pcie'] is too long Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417080939.28648-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 7c12db60a22c8..2c377d7bb3a26 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1814,7 +1814,7 @@ dma@10a2000 { }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8150"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -1909,7 +1909,7 @@ pcie0_lane: phy@1c06200 { }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + compatible = "qcom,pcie-sm8150"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, -- GitLab From 9230758996c3ff0b5cf8e8506731c956bfb351bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Apr 2023 10:09:39 +0200 Subject: [PATCH 137/926] arm64: dts: qcom: sc8280xp: correct GIC child node name GIC child node is supposed to be named msi-controller: sa8295p-adp.dtb: interrupt-controller@17a00000: gic-its@17a40000: False schema does not allow Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417080939.28648-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a2320f8807954..91a2d3ab3cc1c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3925,7 +3925,7 @@ intc: interrupt-controller@17a00000 { #size-cells = <2>; ranges; - gic-its@17a40000 { + msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; -- GitLab From d2bf7abfd2352dd45cc99b2ce8c7344ac539a656 Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Sat, 13 May 2023 17:01:25 +0530 Subject: [PATCH 138/926] dt-bindings: arm: fsl: Add Emtop SoM & Baseboard Add support for i.MX8MM based Emtop SOM-IMX8MMLPD4 and IMX8MM Mini Baseboard Signed-off-by: Himanshu Bhavani Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ff73a23bbe490..63f8886dc69a5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -925,6 +925,12 @@ properties: - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm + - description: Emtop i.MX8MM based Boards + items: + - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 + - const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module + - const: fsl,imx8mm + - description: Engicam i.Core MX8M Mini SoM based boards items: - enum: -- GitLab From 50552fa6ec91531634f29f9f89e09195ba5bfbbc Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Sat, 13 May 2023 17:01:26 +0530 Subject: [PATCH 139/926] dt-bindings: vendor-prefixes: Add Emtop Add vendor prefix for Emtop Embedded Solutions (https://www.emtop-tech.com/) Signed-off-by: Himanshu Bhavani Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 82d39ab0231b0..5990366bff0c5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -388,6 +388,8 @@ patternProperties: description: EDIMAX Technology Co., Ltd "^edt,.*": description: Emerging Display Technologies + "^ees,.*": + description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc "^einfochips,.*": -- GitLab From 84e29d79be2d5ced59816f458609b7d0c393e89c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 May 2023 16:31:49 +0800 Subject: [PATCH 140/926] arm64: dts: imx93: add watchdog node Add watchdog[1-5] nodes Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index e8d49660ac85b..a04c63d4dc06e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -153,6 +153,24 @@ system_counter: timer@44290000 { nxp,no-divider; }; + wdog1: watchdog@442d0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG1_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog2: watchdog@442e0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG2_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + tpm1: pwm@44310000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44310000 0x1000>; @@ -344,6 +362,33 @@ mu2: mailbox@42440000 { status = "disabled"; }; + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG4_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog5: watchdog@424b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG5_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + tpm3: pwm@424e0000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x424e0000 0x1000>; -- GitLab From 5a866baab1e0254ac8922c7598df48f2c12e86d8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 May 2023 16:31:50 +0800 Subject: [PATCH 141/926] arm64: dts: imx93: add ocotp node Add i.MX93 OCOTP node Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index a04c63d4dc06e..8354d17a6a3f8 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -805,6 +805,13 @@ gpio1: gpio@47400080 { gpio-ranges = <&iomuxc 0 92 16>; }; + ocotp: efuse@47510000 { + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + s4muap: mailbox@47520000 { compatible = "fsl,imx93-mu-s4"; reg = <0x47520000 0x10000>; -- GitLab From f2d03ba997cb5370060874f03e4c61c18bdf6a54 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 May 2023 16:31:51 +0800 Subject: [PATCH 142/926] arm64: dts: imx93: reorder device nodes Reorder device nodes per address - Move eqos node after fec node - Move mediamix node after mlmix node Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 60 ++++++++++++------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 8354d17a6a3f8..5c5652ae4ee07 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -305,14 +305,6 @@ src: system-controller@44460000 { #size-cells = <1>; ranges; - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; reg = <0x44461800 0x400>, <0x44464800 0x400>; @@ -320,6 +312,14 @@ mlmix: power-domain@44461800 { clocks = <&clk IMX93_CLK_ML_APB>, <&clk IMX93_CLK_ML>; }; + + mediamix: power-domain@44462400 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; }; anatop: anatop@44480000 { @@ -685,28 +685,6 @@ usdhc2: mmc@42860000 { status = "disabled"; }; - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <0>; - status = "disabled"; - }; - fec: ethernet@42890000 { compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x42890000 0x10000>; @@ -733,6 +711,28 @@ fec: ethernet@42890000 { status = "disabled"; }; + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + snps,clk-csr = <0>; + status = "disabled"; + }; + usdhc3: mmc@428b0000 { compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; reg = <0x428b0000 0x10000>; -- GitLab From afbd37e878244a3f4d167cb405cd38300592e0b4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 May 2023 16:31:52 +0800 Subject: [PATCH 143/926] arm64: dts: imx93: add cpuidle node Add cpuidle node to support cpu idle. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 5c5652ae4ee07..dc444ca394afd 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -46,12 +46,27 @@ cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A55_1: cpu@100 { @@ -60,6 +75,7 @@ A55_1: cpu@100 { reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; }; -- GitLab From b954d70abe528112aaac31eaf7c65ebd6a982790 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 10 May 2023 16:31:53 +0800 Subject: [PATCH 144/926] arm64: dts: imx93-11x11-evk: enable wdog3 Enable wdog3 to support watchdog feature Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index fefb934872914..c50f46f06f62c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -116,6 +116,10 @@ &usdhc2 { no-mmc; }; +&wdog3 { + status = "okay"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < -- GitLab From cbd3ef64eb9d1be9ec647411547bc7bb8409b11f Mon Sep 17 00:00:00 2001 From: Himanshu Bhavani Date: Sat, 13 May 2023 17:01:24 +0530 Subject: [PATCH 145/926] arm64: dts: Add support for Emtop SoM & Baseboard Add device tree support for the i.MX8MM Based Emtop SOM-IMX8MMLPD4 (V1) and IMX8M Mini Baseboard (V1). Currently supported are serial console, eMMC. Signed-off-by: Himanshu Bhavani Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-emtop-baseboard.dts | 15 + .../boot/dts/freescale/imx8mm-emtop-som.dtsi | 261 ++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0a6a646712a54..eb6279fcdf7be 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-emtop-baseboard.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts new file mode 100644 index 0000000000000..1c4e4d175989e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Emtop Embedded Solutions + */ + +/dts-v1/; + +#include "imx8mm-emtop-som.dtsi" + +/ { + model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1"; + compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som", + "fsl,imx8mm"; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi new file mode 100644 index 0000000000000..67d22d3768aa8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-som.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Emtop Embedded Solutions + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM"; + compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck3: BUCK3 { + regulator-name = "BUCK3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <945000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3600000>; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_led: emtop-gpio-led-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + + pinctrl_i2c1: emtop-i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: emtop-pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: emtop-uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc3: emtop-usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: emtop-wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- GitLab From e5cfa586d5131979feed2820dee18689a4075e64 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 13 May 2023 11:21:24 +0100 Subject: [PATCH 146/926] ARM: dts: armada388-clearfog: add missing phy-modes The DSA framework has got more picky about always having a phy-mode, particularly for the CPU port. Add the missing phy-mode properties for every port which does not have an integrated PHY. Add a phy-mode property to the ethernet interface facing the switch as this was configured using SGMII - as the switch is actually using 1000base-x, let's have some consistency between the two link partners. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-388-clearfog.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 95299167dcf58..32c569df142ff 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -47,6 +47,8 @@ button-0 { ð1 { /* ethernet@30000 */ + phy-mode = "1000base-x"; + fixed-link { speed = <1000>; full-duplex; @@ -129,8 +131,9 @@ port@4 { port@5 { reg = <5>; - label = "cpu"; ethernet = <ð1>; + phy-mode = "1000base-x"; + fixed-link { speed = <1000>; full-duplex; @@ -141,6 +144,8 @@ port@6 { /* 88E1512 external phy */ reg = <6>; label = "lan6"; + phy-mode = "rgmii-id"; + fixed-link { speed = <1000>; full-duplex; -- GitLab From be06fedcec0d5796f3a383f0e4409cf1296e75a9 Mon Sep 17 00:00:00 2001 From: Shubhi Garg Date: Mon, 8 May 2023 10:27:32 +0000 Subject: [PATCH 147/926] dt-bindings: tegra: Document compatible for IGX Document the compatible strings used for Nvidia IGX Orin Development kit which uses P3701 SKU8 and P3740 carrier board. Signed-off-by: Shubhi Garg Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 0df41f5b7e2a3..6970ca1b8bd86 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -167,6 +167,11 @@ properties: - const: nvidia,p3737-0000+p3701-0000 - const: nvidia,p3701-0000 - const: nvidia,tegra234 + - description: NVIDIA IGX Orin Development Kit + items: + - const: nvidia,p3740-0002+p3701-0008 + - const: nvidia,p3701-0008 + - const: nvidia,tegra234 - description: Jetson Orin NX items: - const: nvidia,p3767-0000 -- GitLab From 435ac3fbfbc64a4557862a612058383748a3c7f0 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Tue, 9 May 2023 23:17:22 +0800 Subject: [PATCH 148/926] riscv: dts: starfive: jh7100: Add watchdog node Add watchdog node for the StarFive JH7100 RISC-V SoC. Reviewed-by: Emil Renner Berthing Signed-off-by: Xingyu Wu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482acaa..4218621ea3b92 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -238,5 +238,15 @@ i2c3: i2c@12460000 { #size-cells = <0>; status = "disabled"; }; + + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x0 0x12480000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, + <&clkgen JH7100_CLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, + <&rstgen JH7100_RSTN_WDT>; + }; }; }; -- GitLab From 6361b7de262aca8704abfaade5166a940f7cc571 Mon Sep 17 00:00:00 2001 From: Xingyu Wu Date: Tue, 9 May 2023 23:17:23 +0800 Subject: [PATCH 149/926] riscv: dts: starfive: jh7110: Add watchdog node Add the watchdog node for the Starfive JH7110 SoC. Signed-off-by: Xingyu Wu Reviewed-by: Walker Chen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 30e1f34d5cf8d..03c6cc49fa229 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -469,6 +469,16 @@ sysgpio: pinctrl@13040000 { #gpio-cells = <2>; }; + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; -- GitLab From 3db59e1ca693455d0710dc217455fe81d0d32dce Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 7 Apr 2023 20:31:57 +0200 Subject: [PATCH 150/926] ARM: dts: stm32: add part number for STM32MP15x The STM32MP15x Device Part Number is located in the first 8 bits of OTP4, this patch add its description as the NVMEM cell. Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 63f4c78fcc1dc..664825418c32c 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1620,6 +1620,9 @@ bsec: efuse@5c005000 { reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + part_number_otp: part-number-otp@4 { + reg = <0x4 0x1>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; -- GitLab From b0dae3df0546a5968ef8ea5b396d3de9b3a2295a Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:07 +0530 Subject: [PATCH 151/926] dt-bindings: tegra: Add ICC IDs for dummy memory clients Add ICC IDs for dummy software clients representing CCPLEX clusters. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra234-mc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 347e55e89a2a8..6e60d55491b3b 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -536,4 +536,9 @@ #define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 #define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 +/* ICC ID's for dummy MC clients used to represent CPU Clusters */ +#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 +#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 +#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 + #endif -- GitLab From c95711d7dbc41cc0eb8927313f8482b2b07c8280 Mon Sep 17 00:00:00 2001 From: Shubhi Garg Date: Mon, 8 May 2023 10:27:33 +0000 Subject: [PATCH 152/926] arm64: tegra: Add support for IGX Orin Add support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Signed-off-by: Shubhi Garg Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 2 + .../boot/dts/nvidia/tegra234-p3701-0008.dtsi | 111 +++++++++++++ .../nvidia/tegra234-p3740-0002+p3701-0008.dts | 154 ++++++++++++++++++ .../boot/dts/nvidia/tegra234-p3740-0002.dtsi | 137 ++++++++++++++++ 4 files changed, 404 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 1406d5d40b8f1..2ea0058979d3b 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -9,6 +9,7 @@ DTC_FLAGS_tegra194-p2972-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ +DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@ DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb @@ -25,4 +26,5 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi new file mode 100644 index 0000000000000..e468352b8b7f0 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + compatible = "nvidia,p3701-0008", "nvidia,tegra234"; + + bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "module"; + vcc-supply = <&vdd_1v8_hs>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + + mmc@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + i2c@c240000 { + status = "okay"; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; + + bpmp { + i2c { + status = "okay"; + + thermal-sensor@4c { + status = "okay"; + reg = <0x4c>; + vcc-supply = <&vdd_1v8_ao>; + }; + }; + + thermal { + status = "okay"; + }; + }; + + vdd_1v8_ao: regulator-vdd-1v8-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_hs: regulator-vdd-1v8-hs { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_ls: regulator-vdd-1v8-ls { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3v3_ao: regulator-vdd-3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts new file mode 100644 index 0000000000000..43d797e5544f5 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include "tegra234-p3701-0008.dtsi" +#include "tegra234-p3740-0002.dtsi" + +/ { + model = "NVIDIA IGX Orin Development Kit"; + compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234"; + + aliases { + serial0 = &tcu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bus@0 { + host1x@13e00000 { + nvdec@15480000 { + status = "okay"; + }; + }; + + pcie@140e0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_4>, <&p2u_gbe_5>; + phy-names = "p2u-0", "p2u-1"; + }; + + pcie@14100000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>, + <&p2u_hsio_4>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + + pcie@141e0000 { + status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; + }; + + aconnect@2900000 { + status = "okay"; + }; + + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + status = "okay"; + }; + + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + }; + + i2c@3190000 { + status = "okay"; + }; + + i2c@31b0000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + + }; + + i2c@31e0000 { + status = "okay"; + }; + + spi@3270000 { + status = "okay"; + }; + + hda@3510000 { + nvidia,model = "NVIDIA IGX HDA"; + status = "okay"; + }; + + fuse@3810000 { + status = "okay"; + }; + + i2c@c240000 { + status = "okay"; + }; + + i2c@c250000 { + status = "okay"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi new file mode 100644 index 0000000000000..c95063b193218 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3740-0002"; + + bus@0 { + i2c@31c0000 { + /* carrier board ID EEPROM */ + eeprom@55 { + compatible = "atmel,24c02"; + reg = <0x55>; + + label = "system"; + vcc-supply = <&vdd_1v8_ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + padctl@3520000 { + vclamp-usb-supply = <&vdd_1v8_ao>; + avdd-usb-supply = <&vdd_3v3_ao>; + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + usb-role-switch; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + vbus-supply = <&vdd_5v0_sys>; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-2 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-0"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; + }; +}; -- GitLab From 1582e1d1b244e195c869957e08f06c53aa78c688 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:11 +0530 Subject: [PATCH 153/926] arm64: tegra: Add CPU OPP tables and interconnects property Add OPP table and interconnects property to scale DDR frequency with CPU frequency for better performance. Each operating point entry of the OPP table has CPU freq to per MC channel bandwidth mapping. One table is added for each cluster even though the table data is same because the bandwidth request is per cluster. This is done because OPP framework creates a single icc path and hence single bandwidth request if the table is marked as 'opp-shared' and shared among all clusters. For us, the OPP table data is same but the MC Client ID argument to interconnects property is different for each cluster. So, having per cluster table makes different icc path for each cluster and helps to make per cluster BW requests. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 276 +++++++++++++++++++++++ 1 file changed, 276 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 18b4c2b2c42c8..97ed3e0d892ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3028,6 +3028,9 @@ cpu0_0: cpu@0 { enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3044,6 +3047,9 @@ cpu0_1: cpu@100 { enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3060,6 +3066,9 @@ cpu0_2: cpu@200 { enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3076,6 +3085,9 @@ cpu0_3: cpu@300 { enable-method = "psci"; + operating-points-v2 = <&cl0_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3092,6 +3104,9 @@ cpu1_0: cpu@10000 { enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3108,6 +3123,9 @@ cpu1_1: cpu@10100 { enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3124,6 +3142,9 @@ cpu1_2: cpu@10200 { enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3140,6 +3161,9 @@ cpu1_3: cpu@10300 { enable-method = "psci"; + operating-points-v2 = <&cl1_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3156,6 +3180,9 @@ cpu2_0: cpu@20000 { enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3172,6 +3199,9 @@ cpu2_1: cpu@20100 { enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3188,6 +3218,9 @@ cpu2_2: cpu@20200 { enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3204,6 +3237,9 @@ cpu2_3: cpu@20300 { enable-method = "psci"; + operating-points-v2 = <&cl2_opp_tbl>; + interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; + i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -3478,4 +3514,244 @@ timer { interrupt-parent = <&gic>; always-on; }; + + cl0_opp_tbl: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + cl0_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl0_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl0_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl0_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; + + cl1_opp_tbl: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + cl1_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl1_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl1_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl1_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; + + cl2_opp_tbl: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + cl2_ch1_opp1: opp-115200000 { + opp-hz = /bits/ 64 <115200000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp2: opp-268800000 { + opp-hz = /bits/ 64 <268800000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp3: opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp4: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp5: opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp6: opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp7: opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp8: opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp9: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp10: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp11: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <2660000>; + }; + + cl2_ch1_opp12: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <2660000>; + }; + + cl2_ch1_opp13: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp14: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6400000>; + }; + + cl2_ch1_opp15: opp-2201600000 { + opp-hz = /bits/ 64 <2201600000>; + opp-peak-kBps = <6400000>; + }; + }; }; -- GitLab From 04127a3d30bd7ef7956b894724ca031728154e54 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 16 May 2023 12:31:11 +0200 Subject: [PATCH 154/926] ARM: dts: stm32: remove extra space in stm32mp15xx-dkx.dtsi Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi. Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index cefeeb00fc228..0f1110e42c939 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -379,21 +379,21 @@ vref_ddr: vref_ddr { regulator-always-on; }; - bst_out: boost { + bst_out: boost { regulator-name = "bst_out"; interrupts = ; - }; + }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - }; + }; - vbus_sw: pwr_sw2 { + vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; regulator-active-discharge = <1>; - }; + }; }; onkey { -- GitLab From 9a18fb598162f4626497ace3090e1a2cb40aa7e4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:48 +0200 Subject: [PATCH 155/926] arm64: zynqmp: Rename ams_ps/pl node names Fix child node names to be aligned with commit 39dd2d1e251d ("dt-bindings: iio: adc: Add Xilinx AMS binding documentation") which requires names as ams-ps@ and ams-pl@. Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/373136eccf8d22cdfb499adbc8d5f5510d6c1035.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 1a24029b106ec..d048719862615 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -938,13 +938,13 @@ xilinx_ams: ams@ffa50000 { #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; - ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; -- GitLab From 6ae507f09e29ae2f492b9c4cec97aad1f84aa8ab Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Tue, 2 May 2023 15:35:36 +0200 Subject: [PATCH 156/926] arm64: zynqmp: Add resets property to sdhci nodes Add "resets" property to sdhci nodes. Resets property is used to reset the SD host controller when dynamic configuration support is enabled. Signed-off-by: Sai Krishna Potthuri Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8f8592d6454c024c8f8b92e56c9009c65ad1d54a.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index d048719862615..1aa250d5d9555 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -740,6 +740,7 @@ sdhci0: mmc@ff160000 { #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { @@ -753,6 +754,7 @@ sdhci1: mmc@ff170000 { #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: iommu@fd800000 { -- GitLab From 3effc177f12d5062bf39496aa6db23d29924678b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:34 +0200 Subject: [PATCH 157/926] arm64: zynqmp: Sync node name address with reg (mailbox) Address in node name should match with the first reg property in DT. Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5d8e80383912b8ff75409764efb75f3b85917087.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 1aa250d5d9555..44e0ab8aae53c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -126,7 +126,7 @@ zynqmp_ipi: zynqmp_ipi { #size-cells = <2>; ranges; - ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, -- GitLab From 028d125a30ff5646b3ad22445080d8f2946d67d7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:32 +0200 Subject: [PATCH 158/926] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 The commit 53ba1b2bdaf7 ("arm64: dts: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d117473da3bab39a82fe900cecd8ca78df9adeda.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index c74bc3ff703b8..685f8e4f33e77 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -545,6 +545,7 @@ &usb0 { pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; }; &dwc3_0 { @@ -560,6 +561,7 @@ &usb1 { pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { -- GitLab From e2ff42b4f1caf37ce8fca06f69e4970d6fa5ad69 Mon Sep 17 00:00:00 2001 From: Chirag Parekh Date: Tue, 2 May 2023 15:52:41 +0200 Subject: [PATCH 159/926] ARM: zynq: dts: Add SCL & SDA GPIO entries for recovery Wire i2c pinmuxing gpio recovery for zc702. Signed-off-by: Chirag Parekh Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5eb73d1150648e782795e35c30fccb983b3e0db7.1683035557.git.michal.simek@amd.com --- arch/arm/boot/dts/zynq-zc702.dts | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index d23201ba8cd7d..6efdbca9d3efb 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" +#include / { model = "Xilinx ZC702 board"; @@ -106,8 +107,11 @@ &gpio0 { &i2c0 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; @@ -298,6 +302,19 @@ conf { }; }; + pinctrl_i2c0_gpio: i2c0-gpio { + mux { + groups = "gpio0_50_grp", "gpio0_51_grp"; + function = "gpio0"; + }; + + conf { + groups = "gpio0_50_grp", "gpio0_51_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + }; + pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; -- GitLab From e0040abb8d5bb2215f8ee08e0e2d05052a004288 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 7 Apr 2023 23:01:52 +0200 Subject: [PATCH 160/926] ARM: dts: stm32: Replace deprecated st,hw-flow-ctrl with uart-has-rtscts Replace deprecated st,hw-flow-ctrl with uart-has-rtscts . No functional change. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h750i-art-pi.dts | 2 +- arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 4 ++-- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts index f3e70d3b65ac4..44c307f8b09cf 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -208,7 +208,7 @@ &usart3 { dmas = <&dmamux1 45 0x400 0x05>, <&dmamux1 46 0x400 0x05>; dma-names = "rx", "tx"; - st,hw-flow-ctrl; + uart-has-rtscts; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index 3a36f7fe0a2c3..5f85598cc7c6b 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -287,7 +287,7 @@ &usart2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; @@ -297,7 +297,7 @@ &usart2 { &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 50af4a27d6be4..8232bbbae379c 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -452,7 +452,7 @@ &usart2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; - st,hw-flow-ctrl; + uart-has-rtscts; /delete-property/dmas; /delete-property/dma-names; status = "okay"; -- GitLab From 9660efc2af37f3c12dc6e6a5511ad99e0addc297 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 May 2023 23:37:29 +0200 Subject: [PATCH 161/926] ARM: dts: stm32: Move ethernet MAC EEPROM from SoM to carrier boards The ethernet MAC EEPROM is not populated on the SoM itself, it has to be populated on each carrier board. Move the EEPROM into the correct place in DTs, i.e. the carrier board DTs. Add label to the EEPROM too. Fixes: 7e76f82acd9e1 ("ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 6 ------ arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 8 ++++++++ 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 8232bbbae379c..302efac5d26f0 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -321,6 +321,12 @@ adv7513_i2s0: endpoint { }; }; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; <dc { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index c32c160f97f20..39af79dc654cc 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -192,6 +192,12 @@ eeprom@50 { reg = <0x50>; pagesize = <16>; }; + + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &sdmmc1 { /* MicroSD */ diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index bb40fb46da81d..bba19f21e5277 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -213,12 +213,6 @@ watchdog { status = "disabled"; }; }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; }; &ipcc { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi index 5fdb74b652aca..faed31b6d84a1 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -90,6 +90,14 @@ phy0: ethernet-phy@7 { }; }; +&i2c4 { + dh_mac_eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; -- GitLab From e05d2f969cb558da5c74c1e5c6aaf506806f4563 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:37 +0200 Subject: [PATCH 162/926] arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5d3777fdf91d114effe1921255a7ad71ef30d277.1683034376.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 34412304d09fa..54cf2e8175371 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -288,6 +288,101 @@ &gpio { "", "", "", ""; /* 170 - 173 */ }; +&zynqmp_dpsub { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gpu { status = "okay"; }; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +}; -- GitLab From 4a7f7eadd7f740c69cdc0a041e0e589d25ddfbbe Mon Sep 17 00:00:00 2001 From: Srinivas Neeli Date: Tue, 2 May 2023 15:35:38 +0200 Subject: [PATCH 163/926] arm64: zynqmp: Add linux,code for gpio button BTN_MISC looks like the most reasonable option for this button. Button is used by firmware to indicate (after reset, power up) that user wants to do firmware upgrade via firmware update utility. For bootloader or OS is this just user button which is worth to have it mapped. Also button can be used as a wakeup source and pressing it for more time can generate more chars that's why also adding wakeup-source and autorepeat properties. Signed-off-by: Srinivas Neeli Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4e20661f43b1fb8432fa5fcda5c1cb50d0a27475.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 54cf2e8175371..00c0455635b8b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -55,6 +55,9 @@ gpio-keys { key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + autorepeat; }; }; -- GitLab From 637902f7c407268391434c2bd3455d35d3a74c84 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:39 +0200 Subject: [PATCH 164/926] arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM With limited low level configuration done via psu-init only IPs connected on SOM are initialized and configured. All IPs connected to carrier card are not initialized. There is a need to do proper reset, pin configuration and also clock setting. The patch targets the last part which is setting up proper clock for EMMC on production SOMs and SD on kv260-revB. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/cf5a4e412e1674500a71a0b1eed7fa8393f37ae9.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 5e7e1bf5b8115..681885c9bcbb0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -185,10 +186,12 @@ &sata { &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b610e65e0cdfe..22fe9c4e4d437 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -132,6 +132,7 @@ &sdhci1 { /* on CC with tuned parameters */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; + assigned-clock-rates = <187498123>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a52dafbfd59e7..ca3429f9961ac 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -115,6 +115,7 @@ &sdhci1 { /* on CC with tuned parameters */ clk-phase-sd-hs = <126>, <60>; clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; + assigned-clock-rates = <187498123>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 00c0455635b8b..d8b2c30caf2c9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -178,6 +178,7 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; + assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ -- GitLab From 5ac5794afb3699047a4f58f20627df5ac7ba594c Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Tue, 2 May 2023 15:35:40 +0200 Subject: [PATCH 165/926] arm64: zynqmp: Add mtd partition for secure OS storage area Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage" Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20dd23821118999c6fec2bad52ea446d1a66fefb.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index d8b2c30caf2c9..9778d5655a5a4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -83,7 +83,7 @@ &uart1 { /* MIO36/MIO37 */ &qspi { /* MIO 0-5 - U143 */ status = "okay"; - flash@0 { /* MT25QU512A */ + spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; @@ -161,13 +161,17 @@ partition@2220000 { }; partition@2240000 { label = "SHA256"; - reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; - partition@2250000 { + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { label = "User"; - reg = <0x2250000 0x1db0000>; /* 29.5 MB */ + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; -- GitLab From 56bb4ed4da7c38d1cdc2f11f8a66eb50ecac25a6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:42 +0200 Subject: [PATCH 166/926] arm64: zynqmp: Add gpio labels for modepin gpio Using label helps with better chip identification. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/12b2fcd94e528c8ca7117f6741aae36b5942b430.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 9778d5655a5a4..583a2d533cef9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -77,6 +77,10 @@ ds36-led { }; }; +&modepin_gpio { + label = "modepin"; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; -- GitLab From c506fe31d7220b088abd9312867849bc2ecf3f51 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:43 +0200 Subject: [PATCH 167/926] arm64: zynqmp: Add pinctrl emmc description to SM-K26 Production SOM has emmc on it and make sense to describe pin description to be able use EMMC if it is not configured via psu_init. (Still some regs are not handled but this is one step in that direction) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f61c16e2fd7c91c2be6d6b67c902037580dbd364.1683034376.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 583a2d533cef9..dbc595c2d56b5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "ZynqMP SM-K26 Rev1/B/A"; @@ -85,6 +86,23 @@ &uart1 { /* MIO36/MIO37 */ status = "okay"; }; +&pinctrl0 { + status = "okay"; + pinctrl_sdhci0_default: sdhci0-default { + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + }; +}; + &qspi { /* MIO 0-5 - U143 */ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ @@ -182,6 +200,8 @@ partition@22A0000 { &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; -- GitLab From 60a990542425b5fc71c879e84ca0848730d7aa3b Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Tue, 2 May 2023 15:35:44 +0200 Subject: [PATCH 168/926] arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 The board zynqmp-zc1751-xm016-dc2 support only USB2.0 that's why remove USB3.0 DT configuration. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ad019501a851c5730427af948b636316f10b2e3b.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 938b76bd05274..868ca655a2205 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -485,8 +485,6 @@ &usb1 { &dwc3_1 { status = "okay"; dr_mode = "host"; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; }; &uart0 { -- GitLab From fc57b6c9298f49073fdb6de0532b76b0f98337e4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:45 +0200 Subject: [PATCH 169/926] arm64: zynqmp: Switch to ethernet-phy-id in kv260 Use ethernet-phy-id compatible string to properly describe phy reset on kv260 boards. Previous description wasn't correct because reset was done for mdio bus to operate and it was in this case used for different purpose which was eth phy reset. With ethernet-phy-id phy reset happens only for the phy via phy framework. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4b139e942c2a808eecbb30226b6ea5303348390a.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 22fe9c4e4d437..85bf276fb52dc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -145,16 +145,18 @@ &gem3 { /* required by spec */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index ca3429f9961ac..bf8f2a94be251 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -128,16 +128,18 @@ &gem3 { /* required by spec */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; -- GitLab From 116de80adad7a4f1eddff7aa13d801b3c3596eab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:46 +0200 Subject: [PATCH 170/926] arm64: zynqmp: Setup clock for DP and DPDMA Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 681885c9bcbb0..581221fdadf13 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -248,10 +248,14 @@ &xilinx_ams { &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; + assigned-clocks = <&zynqmp_clk DP_STC_REF>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 85bf276fb52dc..42ff4450d8a10 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -98,10 +98,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index bf8f2a94be251..ed57b4e44c989 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -79,10 +79,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { -- GitLab From 6d1a2bea2410ed046b8422952743be03259f7f2f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:47 +0200 Subject: [PATCH 171/926] arm64: zynqmp: Enable DP driver for SOMs DP DMA is already enabled that's why there is no reason to keep DP disabled. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/15d16b4de933bfae108df6ca368eb2cdf916aa02.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 42ff4450d8a10..5bd2e8c2f7212 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -95,7 +95,7 @@ &sata { }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index ed57b4e44c989..83757fe0219a9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -76,7 +76,7 @@ &psgtr { }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -- GitLab From 255118de7689211b9d2f1e0da2dc63ef63ea3ff6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:49 +0200 Subject: [PATCH 172/926] arm64: zynqmp: Enable AMS on SOM and other zcu10x boards AMS is used for monitoring system. Used for measuring voltages and especially temperatures. Origin interface is IIO but via iio-hwmon it can be moved to hwmon framework too (done for SOM and zcu100). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e1e1621ac1cee7f36ef20606bb3795e130de9609.1683034376.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 26 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 17 ++++++++++++ .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 12 +++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 12 +++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 12 +++++++++ 5 files changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index dbc595c2d56b5..3f8a7a497f3e2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -76,6 +76,20 @@ ds36-led { default-state = "on"; }; }; + + ams { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, + <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, + <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, + <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, + <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, + <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, + <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + }; }; &modepin_gpio { @@ -320,6 +334,18 @@ &gpio { "", "", "", ""; /* 170 - 173 */ }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpsub { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 685f8e4f33e77..70c48079575dd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -58,6 +58,15 @@ switch-4 { }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, + <&xilinx_ams 11>, <&xilinx_ams 12>; + }; + leds { compatible = "gpio-leds"; led-ds2 { @@ -574,6 +583,14 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 13c43324f1d24..d600eeb5b2b70 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -1017,6 +1017,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 485585c491f42..473fae564906d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -501,6 +501,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 44ec9edd24527..c8ba9ed157be9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -513,6 +513,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; -- GitLab From 7b91ccd5d2657a526fcb54a082087921f3997c53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:50 +0200 Subject: [PATCH 173/926] arm64: zynqmp: Describe bus-width for SD card on KV260 SD card is connected with 4 data lines which should be described properly. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b4046d2f593047400c190e438fd9d05128c293d9.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 5bd2e8c2f7212..bd7628a50b042 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -135,6 +135,7 @@ &sdhci1 { /* on CC with tuned parameters */ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 83757fe0219a9..8e66448f35a9d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -118,6 +118,7 @@ &sdhci1 { /* on CC with tuned parameters */ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ -- GitLab From 5be4fbbfbec320dfb08530f0297fa2fe7aa1e836 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:35:51 +0200 Subject: [PATCH 174/926] arm64: zynqmp: Add phase tags marking bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 581221fdadf13..719ea5d5ae88d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -11,30 +11,35 @@ #include / { pss_ref_clk: pss_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk { &zynqmp_firmware { zynqmp_clk: clock-controller { + bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 3f8a7a497f3e2..464e28bf078a4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -236,17 +236,20 @@ tpm@0 { /* slm9670 - U144 */ &i2c1 { status = "okay"; + bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 44e0ab8aae53c..850b497d7a812 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -118,6 +118,7 @@ rproc_1_fw_image: memory@3ef00000 { }; zynqmp_ipi: zynqmp_ipi { + bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -127,6 +128,7 @@ zynqmp_ipi: zynqmp_ipi { ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { + bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, @@ -143,6 +145,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { dcc: dcc { compatible = "arm,dcc"; status = "disabled"; + bootph-all; }; pmu { @@ -164,8 +167,10 @@ zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; + bootph-all; zynqmp_power: zynqmp-power { + bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -245,6 +250,7 @@ r5f-1 { amba: axi { compatible = "simple-bus"; + bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; @@ -684,6 +690,7 @@ pcie_intc: legacy-interrupt-controller { }; qspi: spi@ff0f0000 { + bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -730,6 +737,7 @@ sata: ahci@fd0c0000 { }; sdhci0: mmc@ff160000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -744,6 +752,7 @@ sdhci0: mmc@ff160000 { }; sdhci1: mmc@ff170000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -836,6 +845,7 @@ ttc3: timer@ff140000 { }; uart0: serial@ff000000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -846,6 +856,7 @@ uart0: serial@ff000000 { }; uart1: serial@ff010000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -967,6 +978,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { }; zynqmp_dpsub: display@fd4a0000 { + bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, -- GitLab From 45fe0dc4ea2efff3eff4e54e31e679224c095c2a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 May 2023 15:12:49 +0200 Subject: [PATCH 175/926] arm64: xilinx: Use zynqmp prefix for SOM dt overlays U-Boot is using zynqmp- prefix to compose DT name for board detection that's why also generate DT in this format in the kernel. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/49c1b8c992929610ba17b9c6edf5d40d4b28d2ed.1683033163.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/Makefile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index db0cc5733177e..5e40c0b4fa0a9 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -21,12 +21,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb -sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo -sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo -smk-k26-revA-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo -smk-k26-revA-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo -dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += sm-k26-revA-sck-kv-g-revB.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += smk-k26-revA-sm-k26-revA-sck-kv-g-revB.dtb +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo -- GitLab From 7a5f349e592c254f3c1ac34665b6c3905576efc2 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 16 May 2023 10:52:19 +0200 Subject: [PATCH 176/926] ARM: dts: stm32: use RCC macro for CRC node on stm32f746 The patch replaces the number 12 with the appropriate numerical constant already defined in the file stm32f7-rcc.h. Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index dc868e6da40e0..e3564b74a7791 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -515,7 +515,7 @@ pwrcfg: power-config@40007000 { crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; status = "disabled"; }; -- GitLab From 303f3fe1d88f7e45e0ab63f37c0949953b69fc10 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:49 +0200 Subject: [PATCH 177/926] ARM: dts: stm32: Add alternate pinmux for ethernet for stm32mp15 Add another option for the ethernet0 pins. It is almost identical to ethernet0_rgmii_pins_c apart from TXD0/1. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e86d989dd351d..c20d59919fc9b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -341,6 +341,56 @@ pins1 { }; }; + ethernet0_rgmii_pins_d: rgmii-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ -- GitLab From ab7a5cba8231306fce1125b4aadc9edda076902c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:50 +0200 Subject: [PATCH 178/926] ARM: dts: stm32: Add alternate pinmux for sai2b on stm32mp15 Add another option for the SAI2B pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Reviewed-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index c20d59919fc9b..f6661951258a1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1491,6 +1491,30 @@ pins { }; }; + sai2b_pins_d: sai2b-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + ; /* SAI2_MCLK_B */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_d: sai2b-sleep-3 { + pins1 { + pinmux = , /* SAI2_SCK_B */ + , /* SAI2_FS_B */ + , /* SAI2_MCLK_B */ + ; /* SAI2_SD_B */ + }; + }; + sai4a_pins_a: sai4a-0 { pins { pinmux = ; /* SAI4_SD_A */ -- GitLab From 8b8d017f5334f01646ab04bf4c5c33d9886f0d5c Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:51 +0200 Subject: [PATCH 179/926] ARM: dts: stm32: Add new pinmux for sdmmc1_b4 on stm32mp15 Add another option for the SDMMC_B4 pins. It is almost identical to sdmmc1_b4_pins_a but the SDMMC1_D2 pin. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 54 ++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f6661951258a1..b4f36520f51bb 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1596,6 +1596,60 @@ pins { }; }; + sdmmc1_b4_pins_b: sdmmc1-b4-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = , /* SDMMC1_D0DIR */ -- GitLab From 2f18e152217d9d784e3ca8270547917cfc7d7440 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:52 +0200 Subject: [PATCH 180/926] ARM: dts: stm32: Add new pinmux for sdmmc2_d47 on stm32mp15 Add another option for the SDMMC_D47 pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index b4f36520f51bb..a1a994c9a48e1 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1887,6 +1887,27 @@ pins { }; }; + sdmmc2_d47_pins_e: sdmmc2-d47-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ -- GitLab From 559b33d2a8c546c06a4e398da064e4a787ea4aab Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:53 +0200 Subject: [PATCH 181/926] ARM: dts: stm32: Add pinmux for USART1 pins on stm32mp15 Add a mux option for the USART1 pins. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 57 ++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a1a994c9a48e1..527c76c8be581 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2273,6 +2273,33 @@ pins { }; }; + usart1_pins_a: usart1-0 { + pins1 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_CTS_NSS */ + bias-disable; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_RTS */ + ; /* USART1_CTS_NSS */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -2612,4 +2639,34 @@ pins2 { bias-disable; }; }; + + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; }; -- GitLab From 37f92e6930bd68830f3299f905fa8f208cc7a250 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:54 +0200 Subject: [PATCH 182/926] ARM: dts: stm32: Add idle/sleep pinmux for USART3 on stm32mp15 Add idle and sleep mux option for the USART3 pins_a. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 527c76c8be581..358cbe9ec9961 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2402,6 +2402,23 @@ pins2 { }; }; + usart3_idle_pins_a: usart3-idle-0 { + pins1 { + pinmux = ; /* USART3_TX */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_a: usart3-sleep-0 { + pins { + pinmux = , /* USART3_TX */ + ; /* USART3_RX */ + }; + }; + usart3_pins_b: usart3-1 { pins1 { pinmux = , /* USART3_TX */ -- GitLab From d4b5f1a5a099d28169e05e138c91e69e00e5ab11 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:55 +0200 Subject: [PATCH 183/926] ARM: dts: stm32: Add sleep pinmux for SPI1 pins_a on stm32mp15 Add a sleep mux option for the SPI1 pins_a mux. This is used on the Phycore STM32MP1. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 358cbe9ec9961..06e969aa5fdb9 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2657,6 +2657,14 @@ pins2 { }; }; + spi1_sleep_pins_a: spi1-sleep-0 { + pins { + pinmux = , /* SPI1_SCK */ + , /* SPI1_MISO */ + ; /* SPI1_MOSI */ + }; + }; + usart1_pins_b: usart1-1 { pins1 { pinmux = ; /* USART1_TX */ -- GitLab From e90227f0f3837ae2552196f26cbd48e576690d70 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:56 +0200 Subject: [PATCH 184/926] dt-bindings: arm: stm32: Add Phytec STM32MP1 board The Phytec STM32MP1 based SoMs feature up to 1 GB DDR3LP RAM, up to 1 GB eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. Signed-off-by: Steffen Trumtrar Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 13e34241145b4..4af5b8f4f8032 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -155,6 +155,12 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 + - description: Phytec STM32MP1 SoM based Boards + items: + - const: phytec,phycore-stm32mp1-3 + - const: phytec,phycore-stm32mp157c-som + - const: st,stm32mp157 + additionalProperties: true ... -- GitLab From 27538a18a4fcc7e8e20c9f71f9a622685a9d7c7b Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:57 +0200 Subject: [PATCH 185/926] ARM: dts: stm32: add STM32MP1-based Phytec SoM The Phytec STM32MP1 based SoMs feature up to 1 GB DDR3LP RAM, up to 1 GB eMMC, up to 16 MB QSPI and up to 128 GB NAND flash. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- .../stm32mp157c-phycore-stm32mp15-som.dtsi | 577 ++++++++++++++++++ 1 file changed, 577 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi new file mode 100644 index 0000000000000..4e8b2d2b30c7a --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi @@ -0,0 +1,577 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp15-pinctrl.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP15 SOM"; + compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + rtc0 = &i2c4_rtc; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; + + regulator_vin: regulator { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-0 = <ðernet0_rgmii_pins_d>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + enet-phy-lane-no-swap; + ti,clk-output-sel = ; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <®ulator_vin>; + buck2-supply = <®ulator_vin>; + buck3-supply = <®ulator_vin>; + buck4-supply = <®ulator_vin>; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo4-supply = <®ulator_vin>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + boost-supply = <®ulator_vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + vdd_eth_2v5: ldo2 { + regulator-name = "dd_eth_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + vdd_eth_1v0: ldo6 { + regulator-name = "vdd_eth_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , + ; + interrupt-names = "onkey-falling", + "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + }; + }; + + i2c4_eeprom: eeprom@50 { + compatible = "microchip,24c32", + "atmel,24c32"; + reg = <0x50>; + }; + + i2c4_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + status = "okay"; + + flash0: flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + st,sync = <&sai2b 2>; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + pinctrl-3 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; -- GitLab From b195a9d7f72139fe5c51e81684a698c7a8a5f34f Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 5 May 2023 08:01:58 +0200 Subject: [PATCH 186/926] ARM: dts: stm32: add STM32MP1-based Phytec board Add the Phytec STM32MP1-3 Dev board. The devboard uses a Phytec stm32m157c-som. Signed-off-by: Steffen Trumtrar Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 +- .../dts/stm32mp157c-phycore-stm32mp1-3.dts | 60 +++++++++++++++++++ 2 files changed, 62 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..4c1c96000f3bf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1266,7 +1266,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-ev1.dtb \ stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ - stm32mp157c-odyssey.dtb + stm32mp157c-odyssey.dtb \ + stm32mp157c-phycore-stm32mp1-3.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts new file mode 100644 index 0000000000000..28d7203264cea --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +/dts-v1/; + +#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp157c-phycore-stm32mp15-som.dtsi" + +/ { + model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + compatible = "phytec,phycore-stm32mp1-3", + "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; + + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +&fmc { + status = "disabled"; +}; + +&gpu { + status = "okay"; +}; + +&i2c4_eeprom { + status = "okay"; +}; + +&i2c4_rtc { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&sdmmc2 { + status = "okay"; +}; -- GitLab From 21f475946d89911e31bccd02f8a7ce40b8f52a70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Apr 2023 17:08:24 +0200 Subject: [PATCH 187/926] ARM: dts: en7523: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: en7523-evb.dtb: l2-cache0: 'cache-level' is a required property en7523-evb.dtb: l2-cache0: 'cache-unified' is a required property Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230423150824.118430-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/en7523.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi index 7f839331a7779..b523a868c4ad1 100644 --- a/arch/arm/boot/dts/en7523.dtsi +++ b/arch/arm/boot/dts/en7523.dtsi @@ -81,6 +81,8 @@ cpu1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- GitLab From 0022cec7edecd5ea6796dfe0d75330c55dd07a67 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:39 +0200 Subject: [PATCH 188/926] arm64: dts: apm: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: apm-mustang.dtb: l2-cache-0: 'cache-level' is a required property apm-mustang.dtb: l2-cache-0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223139.115044-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 8 ++++++++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 70a10bcafcffc..377660d705d1a 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -97,15 +97,23 @@ cpu@301 { }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index d73e809fe41a8..efa79209f4b2c 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,15 +81,23 @@ cpu@301 { }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- GitLab From 9f921604a91c637eb57e57668045ca5c21f49f05 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:40 +0200 Subject: [PATCH 189/926] arm64: dts: amazon: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: alpine-v3-evp.dtb: cache@0: 'cache-unified' is a dependency of 'cache-size' Link: https://lore.kernel.org/r/20230421223141.115072-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 73a352ea8fd5c..39481d7fd7d4d 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -250,6 +250,7 @@ cluster0_l2: cache@0 { cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster1_l2: cache@100 { @@ -258,6 +259,7 @@ cluster1_l2: cache@100 { cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster2_l2: cache@200 { @@ -266,6 +268,7 @@ cluster2_l2: cache@200 { cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster3_l2: cache@300 { @@ -274,6 +277,7 @@ cluster3_l2: cache@300 { cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; }; -- GitLab From a0936e9edf16750867b65c8f2017352f1ea3dea8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:14 +0200 Subject: [PATCH 190/926] arm64: dts: hisilicon: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++ 5 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a57f35eb5ef60..7e137a884ae55 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -204,11 +204,13 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; A73_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f6d3202b0d1ad..872e9c73c4221 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -187,11 +187,13 @@ cpu7: cpu@103 { CLUSTER0_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 5b2b1bfd0d2a1..65ddc0698f828 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -212,21 +212,25 @@ cpu15: cpu@20303 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 291c2ee382882..c588848bfdebb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -212,21 +212,25 @@ cpu15: cpu@10303 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 8a9436ca25311..595abe339c5df 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -843,81 +843,97 @@ cpu63: cpu@70303 { cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster4_l2: l2-cache4 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster5_l2: l2-cache5 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster6_l2: l2-cache6 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster7_l2: l2-cache7 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster8_l2: l2-cache8 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster9_l2: l2-cache9 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster10_l2: l2-cache10 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster11_l2: l2-cache11 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster12_l2: l2-cache12 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster13_l2: l2-cache13 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster14_l2: l2-cache14 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster15_l2: l2-cache15 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From 7a242135a44d32a6a8563fc74f11d5a100b7cf0a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:50 +0200 Subject: [PATCH 191/926] arm64: dts: realtek: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: rtd1293-ds418j.dtb: l2-cache: 'cache-level' is a required property rtd1293-ds418j.dtb: l2-cache: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223151.115243-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/realtek/rtd1293.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1295.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1296.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1395.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 4 ++++ 5 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi index 2d92b56ac94d6..d0c9387ac17a6 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -30,6 +30,8 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 1402abe80ea1b..b7f63102f2ddf 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi index fb864a139c97e..4f805f576cef5 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi index 05c9216a87eef..2efe5b25c83c6 100644 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index bf4d9e9179258..34802cc629838 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -88,11 +88,15 @@ cpu5: cpu@500 { l2: l2-cache { compatible = "cache"; next-level-cache = <&l3>; + cache-level = <2>; + cache-unified; }; l3: l3-cache { compatible = "cache"; + cache-level = <3>; + cache-unified; }; }; -- GitLab From 3740a577eaaa224db6e4bd3b6fdaea2fb3729814 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:45 +0200 Subject: [PATCH 192/926] arm64: dts: synaptics: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: berlin4ct-stb.dtb: cache: 'cache-level' is a required property berlin4ct-stb.dtb: cache: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223145.115129-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index dc12350b9fc89..53d616c3cfed7 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,8 @@ cpu3: cpu@3 { l2: cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { -- GitLab From 4c84cced9304303ed1c73e35277891249e3cc2cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:37 +0200 Subject: [PATCH 193/926] arm64: dts: allwinner: a64: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: sun50i-a64-pine64-lts.dtb: l2-cache: 'cache-unified' is a required property Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230421223137.115015-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 62f45f71ec654..a9c7f82c2c662 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -93,6 +93,7 @@ cpu3: cpu@3 { L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From 0a03767e9a73cd919eb9fff40582e7a3d9232c6d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 17 Apr 2023 09:56:59 +0200 Subject: [PATCH 194/926] ARM: dts: ux500: Disable charging on HREF boards The HREF boards are usually used without battery and not using active charging. Disable it. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230417075659.3162603-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-href-ab8500.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 9fa024900d534..e1de9d389a01b 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -418,6 +418,24 @@ default_cfg { }; }; }; + /* + * Charging is not working on the HREF unless an actual battery is + * mounted, most HREFs have a DC cable in to the "battery power" + * which means this will only be cofusing. So do not enable charging + * of the HREFs. + */ + ab8500_fg { + status = "disabled"; + }; + ab8500_btemp { + status = "disabled"; + }; + ab8500_charger { + status = "disabled"; + }; + ab8500_chargalg { + status = "disabled"; + }; }; }; }; -- GitLab From bd0e450371efa69b985b801c5c67d6faac4d05a7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 8 May 2023 09:08:11 +0200 Subject: [PATCH 195/926] ARM: dts: ux500: Fix STMPE device nodes The STMPE device nodes need to be augmented to fit with current naming policies. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230508070811.965762-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-href-stuib.dtsi | 5 ++--- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 16 +++++++--------- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index e32d0c36feb8f..79c2be36acae7 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -30,12 +30,11 @@ button@145 { soc { i2c@80004000 { - stmpe1601: stmpe1601@40 { + stmpe1601: port-expander@40 { compatible = "st,stmpe1601"; reg = <0x40>; interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpio6>; - interrupt-controller; vcc-supply = <&db8500_vsmps2_reg>; vio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; @@ -44,7 +43,7 @@ stmpe1601: stmpe1601@40 { wakeup-source; st,autosleep-timeout = <1024>; - stmpe_keypad { + keyboard-controller { compatible = "st,stmpe-keypad"; debounce-interval = <64>; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 4d741adc16cd9..1cba130dde8f2 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -99,17 +99,16 @@ lis3lv02dl@1d { pinctrl-names = "default"; reg = <0x1d>; }; - stmpe0: stmpe2401@43 { + stmpe0: port-expander@43 { compatible = "st,stmpe2401"; reg = <0x43>; reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 interrupt-parent = <&gpio2>; - interrupt-controller; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&stmpe2401_1_nhk_mode>; - stmpe_gpio43: stmpe_gpio { + stmpe_gpio43: gpio { compatible = "st,stmpe-gpio"; gpio-controller; #gpio-cells = <2>; @@ -118,7 +117,7 @@ stmpe_gpio43: stmpe_gpio { /* Some pins in alternate functions */ st,norequest-mask = <0xf0f002>; }; - stmpe_keypad { + keyboard-controller { compatible = "st,stmpe-keypad"; debounce-interval = <64>; st,scan-count = <8>; @@ -140,22 +139,21 @@ stmpe_keypad { 0x03020067 // Up 0x0303006c>; // Down }; - stmpe0_pwm: stmpe_pwm { + stmpe0_pwm: pwm { compatible = "st,stmpe-pwm"; #pwm-cells = <2>; }; }; - stmpe1: stmpe2401@44 { + stmpe1: port-expander@44 { compatible = "st,stmpe2401"; reg = <0x44>; reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 interrupt-parent = <&gpio2>; - interrupt-controller; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&stmpe2401_2_nhk_mode>; - stmpe_gpio44: stmpe_gpio { + stmpe_gpio44: gpio { compatible = "st,stmpe-gpio"; gpio-controller; #gpio-cells = <2>; @@ -165,7 +163,7 @@ stmpe_gpio44: stmpe_gpio { * This will turn off SATA so that MMC/SD * can thrive */ - mmcsd-gpio { + mmcsd-hog { gpio-hog; gpios = <2 0x0>; output-low; -- GitLab From 56f0440f27b48948122e5a739fc55c11b23bc821 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 27 Apr 2023 14:10:03 +0200 Subject: [PATCH 196/926] ARM: dts: ux500: Add eSRAM nodes The U8500 has 640 KB of eSRAM, split into 5 banks of 128 KB each. Add this to the device tree, with ESRAM 0, 1+2 and 3+4 as separate devices, since these have different power domains. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230417-ux500-dma40-cleanup-v2-8-cdaa68a4b863@linaro.org --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 73 ++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index fead7afd55171..c34ccde046008 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -110,6 +110,74 @@ soc { interrupt-parent = <&intc>; ranges; + /* + * 640KB ESRAM (embedded static random access memory), divided + * into 5 banks of 128 KB each. This is a fast memory usually + * used by different accelerators. We group these according to + * their power domains: ESRAM0 (always on) ESRAM 1+2 and + * ESRAM 3+4. + */ + sram@40000000 { + /* The first (always on) ESRAM 0, 128 KB */ + compatible = "mmio-sram"; + reg = <0x40000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x20000>; + + sram@0 { + compatible = "stericsson,u8500-esram"; + reg = <0x0 0x10000>; + pool; + }; + lcpa: sram@10000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Paramers (LCP), the address + * where these parameters are stored is called "LCPA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCPA"; + reg = <0x10000 0x800>; + }; + sram@10800 { + compatible = "stericsson,u8500-esram"; + reg = <0x10800 0xf800>; + pool; + }; + }; + sram@40020000 { + /* ESRAM 1+2, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x40000>; + }; + sram@40060000 { + /* ESRAM 3+4, 256 KB */ + compatible = "mmio-sram"; + reg = <0x40060000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40060000 0x40000>; + + lcla: sram@20000 { + /* + * This eSRAM is used by the DMA40 DMA controller + * for Logical Channel Logical Addresses (LCLA), the address + * where these parameters are stored is called "LCLA". + * This is addressed directly by the driver so no + * pool is used. + */ + compatible = "stericsson,u8500-esram"; + label = "DMA40-LCLA"; + reg = <0x20000 0x2000>; + }; + }; + ptm@801ae000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x801ae000 0x1000>; @@ -536,9 +604,10 @@ usb_per5@a03e0000 { dma: dma-controller@801C0000 { compatible = "stericsson,db8500-dma40", "stericsson,dma40"; - reg = <0x801C0000 0x1000 0x40010000 0x800>; - reg-names = "base", "lcpa"; + reg = <0x801C0000 0x1000>; + reg-names = "base"; interrupts = ; + sram = <&lcpa>, <&lcla>; #dma-cells = <3>; memcpy-channels = <56 57 58 59 60>; -- GitLab From ae1c0d6eb45a7839396337ea597090542b294c7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:59 +0200 Subject: [PATCH 197/926] arm64: dts: marvell: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ 4 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 8bce640691387..c9ce1010c4156 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -50,6 +50,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 990f70303fe6f..3ed6fba1f4383 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -52,6 +52,7 @@ l2: l2-cache { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index a7b8e001cc9c1..cf6a96ddcf40f 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 7740098fd108b..8848238f9565d 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; cache-level = <2>; + cache-unified; }; }; }; -- GitLab From 7f9f7f9b1e83058e90d5fe885ee5181ddaaa7d45 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 May 2023 10:11:57 -0300 Subject: [PATCH 198/926] ARM: dts: armada-xp: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 0dad95ea26c2a..21b95578fe953 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -167,8 +167,8 @@ scroll-button { spi-3 { compatible = "spi-gpio"; status = "okay"; - gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ + sck-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + mosi-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/ cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; -- GitLab From 9c994fcf52284ac4cdeee1633373d69e05e30b23 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 17 May 2023 09:48:29 +0200 Subject: [PATCH 199/926] ARM: dts: stm32: Update Cortex-M4 reset declarations on stm32mp15 Since the introduction of the SCMI for the management of the MCU hold boot in OP-TEE, management of the hold boot by SMC call is deprecated. - Clean the st,syscfg-tz which allows to determine if the trust zone is enable. - Add reset-names properties to be able to differentiate the MCU reset and the MCU HOLD BOOT. Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 664825418c32c..a98ae58e2c1c8 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1823,8 +1823,8 @@ m4_rproc: m4@10000000 { <0x30000000 0x40000>, <0x38000000 0x10000>; resets = <&rcc MCU_R>; + reset-names = "mcu_rst"; st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; -- GitLab From 3b1583868691b6fb7d5f7452711cba0481e72292 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 17 May 2023 09:48:30 +0200 Subject: [PATCH 200/926] ARM: dts: stm32: fix m4_rproc references to use SCMI for stm32mp15 Fixes stm32mp15*-scmi DTS files introduced in [1]: This patch fixes the node which uses the MCU reset and adds the missing HOLD_BOOT which is also handled by the SCMI reset service. This change cannot be applied as a fix on commit [1], the management of the hold boot impacts also the stm32_rproc driver. [1] 'commit 5b7e58313a77 ("ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)")' Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 7 +++++-- arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 7 +++++-- 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts index e539cc80bef81..afcd6285890cc 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -55,8 +55,11 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts index 97e4f94b0a24e..39358d9020003 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -61,8 +61,11 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts index 9cf0a44d2f47e..07ea765a4553a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -60,8 +60,11 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts index 3b9dd6f4ccc96..813086ec24895 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -66,8 +66,11 @@ &mdma1 { resets = <&scmi_reset RST_SCMI_MDMA>; }; -&mlahb { - resets = <&scmi_reset RST_SCMI_MCU>; +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; }; &rcc { -- GitLab From f217d94fc632fece2a41030c2eebc4ed34a48b2a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:55 +0200 Subject: [PATCH 201/926] arm64: dts: microchip: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b3..6f7651b064780 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ cpu1: cpu@1 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- GitLab From 70be83708c925b3f72c508e4756e48ad2330c830 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 21 Feb 2023 11:50:37 +0100 Subject: [PATCH 202/926] arm64: dts: microchip: sparx5: do not use PSCI on reference boards PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well. I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023. So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used. Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko Acked-by: Steen Hegelund Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 6f7651b064780..ed6f57ce38f7f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -63,7 +63,7 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { + psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 9d1a082de3e29..32bb76b3202a0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -6,6 +6,18 @@ /dts-v1/; #include "sparx5.dtsi" +&psci { + status = "disabled"; +}; + +&cpu0 { + enable-method = "spin-table"; +}; + +&cpu1 { + enable-method = "spin-table"; +}; + &uart0 { status = "okay"; }; -- GitLab From a34ebb17546d209cbb0b9b2c94303f25749557d7 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 21 Feb 2023 11:50:38 +0100 Subject: [PATCH 203/926] arm64: dts: microchip: sparx5: correct CPU address-cells There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index ed6f57ce38f7f..4996499cc738f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ chosen { }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,14 +39,14 @@ core1 { cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; -- GitLab From d5e64404e77c19ec5bd687b34a11eec0263f1aa8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Apr 2022 21:46:00 +0200 Subject: [PATCH 204/926] arm64: dts: sparx5: rename pinctrl nodes The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20220420194600.3416282-1-michael@walle.cc Link: https://lore.kernel.org/r/20220319204628.1759635-5-michael@walle.cc Signed-off-by: Krzysztof Kozlowski --- .../dts/microchip/sparx5_pcb134_board.dtsi | 26 +++++++++---------- .../dts/microchip/sparx5_pcb135_board.dtsi | 10 +++---- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index ed94a80bf05ff..f3e226de5e5e9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -325,69 +325,69 @@ &sgpio2 { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_22"; function = "twi_scl_m"; output-high; }; - i2cmux_6: i2cmux-6 { + i2cmux_6: i2cmux-6-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_7: i2cmux-7 { + i2cmux_7: i2cmux-7-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_8: i2cmux-8 { + i2cmux_8: i2cmux-8-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_9: i2cmux-9 { + i2cmux_9: i2cmux-9-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; }; - i2cmux_10: i2cmux-10 { + i2cmux_10: i2cmux-10-pins { pins = "GPIO_56"; function = "twi_scl_m"; output-high; }; - i2cmux_11: i2cmux-11 { + i2cmux_11: i2cmux-11-pins { pins = "GPIO_57"; function = "twi_scl_m"; output-high; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 0760cf2e48bc5..82ce007d99592 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -59,28 +59,28 @@ led@7 { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_35", "GPIO_36", "GPIO_50", "GPIO_51"; function = "twi_scl_m"; output-low; }; - i2cmux_s29: i2cmux-0 { + i2cmux_s29: i2cmux-0-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_s30: i2cmux-1 { + i2cmux_s30: i2cmux-1-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_s31: i2cmux-2 { + i2cmux_s31: i2cmux-2-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_s32: i2cmux-3 { + i2cmux_s32: i2cmux-3-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; -- GitLab From 2b967894f80aac2c7421eb545c32ed995f8d9877 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 15 May 2023 14:19:08 +0200 Subject: [PATCH 205/926] arm64: dts: qcom: sa8775p: mark the UFS controller as dma-coherent The UFS controller is cache coherent, so mark it as such in the dtsi. Fixes: be543efeee17 ("arm64: dts: qcom: sa8775p: add UFS nodes") Signed-off-by: Bartosz Golaszewski Suggested-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515121908.303432-1-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a71b745f7a346..07aeb8a8e97bb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -605,6 +605,7 @@ ufs_mem_hc: ufs@1d84000 { power-domains = <&gcc UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0x100 0x0>; + dma-coherent; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, -- GitLab From 4755e880b08d963db24a1b3a710ee0e62f36aa49 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 22:12:50 +0200 Subject: [PATCH 206/926] dt-bindings: power: qcom,rpmpd: add missing RPMH levels There are a lot of RPMh levels that we haven't included yet.. some sadly turned out to be necessary, add them! Acked-by: Krzysztof Kozlowski Acked-by: Conor Dooley Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-kailua-rpmhpd-v2-1-3063ce19c491@linaro.org --- include/dt-bindings/power/qcom-rpmpd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 1bf8e87ecd7ee..e34c01e650d65 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -209,18 +209,28 @@ /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 #define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 #define RPMH_REGULATOR_LEVEL_SVS_L2 224 #define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 #define RPMH_REGULATOR_LEVEL_NOM_L1 320 #define RPMH_REGULATOR_LEVEL_NOM_L2 336 #define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 /* MDM9607 Power Domains */ #define MDM9607_VDDCX 0 -- GitLab From 1738600082987ddcf9cfce753ae3c581c8e46933 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 22:12:51 +0200 Subject: [PATCH 207/926] dt-bindings: power: qcom,rpmpd: Format RPMh levels better After adding the missing levels with a nice, easy-to-read diff, reformat the defines to make them nice to look at.. Acked-by: Krzysztof Kozlowski Acked-by: Conor Dooley Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-kailua-rpmhpd-v2-2-3063ce19c491@linaro.org --- include/dt-bindings/power/qcom-rpmpd.h | 46 +++++++++++++------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index e34c01e650d65..4ede277d20e14 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -207,29 +207,29 @@ #define SC8280XP_XO 15 /* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L0 288 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 -#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 -#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 /* MDM9607 Power Domains */ -- GitLab From 99d33ee61cb06e1235dab404b33d4694fe18088f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 22:12:52 +0200 Subject: [PATCH 208/926] arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels We need more granularity for things like the GPU. Add the missing levels. This unfortunately requires some re-indexing, resulting in an ugly diff. Rename the nodes to prevent that in the future. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-kailua-rpmhpd-v2-3-3063ce19c491@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 40 +++++++++++++++++++++------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6e9bad8f6f33e..1c9460dc3d442 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3608,43 +3608,63 @@ rpmhpd: power-controller { rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; - rpmhpd_opp_ret: opp1 { + rpmhpd_opp_ret: opp-16 { opp-level = ; }; - rpmhpd_opp_min_svs: opp2 { + rpmhpd_opp_min_svs: opp-48 { opp-level = ; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_lov_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_lov_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_lov_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { opp-level = ; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { opp-level = ; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp-256 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp-320 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp-336 { opp-level = ; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp-384 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp-416 { opp-level = ; }; }; -- GitLab From 5d8d9330921770fb953e8e749bbd049ac0fae988 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Apitzsch?= Date: Wed, 17 May 2023 08:32:31 +0200 Subject: [PATCH 209/926] arm64: dts: qcom: msm8916-longcheer-l8910: Add front flash LED MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit l8910 uses OCP8110 flash LED driver. Add it to the device tree. Tested-by: Stephan Gerhold Signed-off-by: André Apitzsch Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230514-x5_front_flash-v2-1-845a8bb0483b@apitzsch.eu --- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index b79e80913af9f..6046e2c1f1586 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -20,6 +20,21 @@ chosen { stdout-path = "serial0"; }; + flash-led-controller { + compatible = "ocs,ocp8110"; + enable-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + flash-gpios = <&msmgpio 119 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&camera_front_flash_default>; + pinctrl-names = "default"; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -246,6 +261,13 @@ button_backlight_default: button-backlight-default-state { bias-disable; }; + camera_front_flash_default: camera-front-flash-default-state { + pins = "gpio49", "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; -- GitLab From 6fb45762691d12d9812c41d20b2f5db1412047ae Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 25 Apr 2023 14:10:05 +0530 Subject: [PATCH 210/926] arm64: dts: qcom: ipq9574: Update the size of GICC & GICV regions Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR registers lie in the second 4kB region. Also, add target CPU encoding. Fixes: 97cb36ff52a1 ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support") Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230425084010.15581-2-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index b65d94887e1ab..40a266106c803 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -197,14 +197,14 @@ blsp1_uart2: serial@78b1000 { intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ - <0x0b002000 0x1000>, /* GICC */ + <0x0b002000 0x2000>, /* GICC */ <0x0b001000 0x1000>, /* GICH */ - <0x0b004000 0x1000>; /* GICV */ + <0x0b004000 0x2000>; /* GICV */ #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <3>; - interrupts = ; + interrupts = ; ranges = <0 0x0b00c000 0x3000>; v2m0: v2m@0 { -- GitLab From 4fc6a939aba4c0aa723b9da8363d262d3d60e57e Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 25 Apr 2023 14:10:09 +0530 Subject: [PATCH 211/926] arm64: dts: qcom: ipq9574: Drop bias_pll_ubi_nc_clk input Drop unused bias_pll_ubi_nc_clk input to the clock controller. Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230425084010.15581-6-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 40a266106c803..ccf70bafababc 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -16,12 +16,6 @@ / { #size-cells = <2>; clocks { - bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { - compatible = "fixed-clock"; - clock-frequency = <353000000>; - #clock-cells = <0>; - }; - sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -145,7 +139,7 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&xo_board_clk>, <&sleep_clk>, - <&bias_pll_ubi_nc_clk>, + <0>, <0>, <0>, <0>, -- GitLab From ec4c54584c504f98c77073c6795936e96f278a15 Mon Sep 17 00:00:00 2001 From: Roman Beranek Date: Fri, 5 May 2023 07:21:08 +0200 Subject: [PATCH 212/926] ARM: dts: sunxi: rename tcon's clock output While the rate of TCON0's DCLK matches dotclock for parallel and LVDS outputs, this doesn't hold for DSI. According manuals from Allwinner, DCLK is an abbreviation of Data Clock, not dotclock, so go with that instead. Signed-off-by: Roman Beranek Acked-by: Jernej Skrabec Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/20230505052110.67514-3-me@crly.cz Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 250d6b87ab4d9..2f901a0136763 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -286,7 +286,7 @@ tcon0: lcd-controller@1c0c000 { clock-names = "ahb", "tcon-ch0", "tcon-ch1"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 4aa9d88c9ea3a..cd4bf60dbb3cb 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -190,7 +190,7 @@ tcon0: lcd-controller@1c0c000 { clock-names = "ahb", "tcon-ch0", "lvds-alt"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_LCD>, <&ccu RST_BUS_LVDS>; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 82fdb04122caa..94eb3bfc989e2 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -456,7 +456,7 @@ tcon0: lcd-controller@1c0c000 { interrupts = ; clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b001251644f75..3b9a282c27463 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -191,7 +191,7 @@ tcon0: lcd-controller@1c0c000 { <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>; reset-names = "lcd"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 62f45f71ec654..e3b17575699c8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -407,7 +407,7 @@ tcon0: lcd-controller@1c0c000 { interrupts = ; clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; + clock-output-names = "tcon-data-clock"; #clock-cells = <0>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; -- GitLab From f3781521af7f9de723a95a6236dcd4cc88854533 Mon Sep 17 00:00:00 2001 From: Ludwig Kormann Date: Wed, 10 May 2023 13:15:27 +0200 Subject: [PATCH 213/926] dt-bindings: arm: sunxi: add ICnova A20 ADB4006 binding Document board compatible names for In-Circuit ICnova A20 ADB4006 development board. Reviewed-by: Andre Przywara Acked-by: Krzysztof Kozlowski Signed-off-by: Ludwig Kormann Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230510111528.2155582-2-ludwig.kormann@ict42.de Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 013821f4a7b8d..ee8fdd2da869a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -305,6 +305,12 @@ properties: - const: allwinner,i12-tvbox - const: allwinner,sun7i-a20 + - description: ICnova A20 ADB4006 + items: + - const: incircuit,icnova-a20-adb4006 + - const: incircuit,icnova-a20 + - const: allwinner,sun7i-a20 + - description: ICNova A20 SWAC items: - const: incircuit,icnova-a20-swac -- GitLab From de2bdfb7f79d5c655eb056d459e02be2c7f13c8b Mon Sep 17 00:00:00 2001 From: Ludwig Kormann Date: Wed, 10 May 2023 13:15:28 +0200 Subject: [PATCH 214/926] arm: dts: sunxi: Add ICnova A20 ADB4006 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add board support for ICnova A20 SomPi compute module on ICnova ADB4006 development board. Specification: SoM - Processor: Allwinner A20 Cortex-A7 Dual Core at 1GHz - 512MB DDR3 RAM - Fast Ethernet (Phy: Realtek RTL8201CP) ADB4006 - I2C - 2x USB 2.0 - 1x Fast Ethernet port - 1x SATA - 2x buttons (PWRON, Boot) - 2x LEDS - serial console - HDMI - µSD-Card slot - Audio Line-In / Line-Out - GPIO pinheaders https://wiki.in-circuit.de/index.php5?title=ICnova_ADB4006 https://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM Reviewed-by: Andre Przywara Signed-off-by: Ludwig Kormann Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230510111528.2155582-3-ludwig.kormann@ict42.de Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun7i-a20-icnova-a20-adb4006.dts | 137 ++++++++++++++++++ arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi | 62 ++++++++ 3 files changed, 200 insertions(+) create mode 100644 arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts create mode 100644 arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..b4e10c379edf1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1335,6 +1335,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-hummingbird.dtb \ sun7i-a20-itead-ibox.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ sun7i-a20-icnova-swac.dtb \ sun7i-a20-lamobo-r1.dtb \ sun7i-a20-linutronix-testbox-v2.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts new file mode 100644 index 0000000000000..577ead1d02a0f --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +/dts-v1/; + +#include "sun7i-a20-icnova-a20.dtsi" + +#include +#include + +/ { + model = "In-Circuit ICnova A20 ADB4006"; + compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20", + "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_ahci_5v { + status = "okay"; +}; + +&ac_power_supply { + status = "okay"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi b/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi new file mode 100644 index 0000000000000..46616c6bc8991 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2023 In-Circuit GmbH + +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>; + phy-handle = <&phy1>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +#include "axp209.dtsi" + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; -- GitLab From c1b2093dce23158e758818443e059e3fcd54633e Mon Sep 17 00:00:00 2001 From: Maksim Kiselev Date: Wed, 10 May 2023 11:11:12 +0300 Subject: [PATCH 215/926] riscv: dts: allwinner: d1: Add SPI controllers node Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have an optional SPI flash that connects to the SPI0 controller. This controller is the same for R329/D1/R528/T113s SoCs and should be supported by the sun50i-r329-spi driver. So let's add its DT nodes. Signed-off-by: Maksim Kiselev Acked-by: Conor Dooley Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230510081121.3463710-6-bigunclemax@gmail.com Signed-off-by: Jernej Skrabec --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c099..1bb1e5cae6021 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -108,6 +108,12 @@ rmii_pe_pins: rmii-pe-pins { function = "emac"; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5"; + function = "spi0"; + }; + /omit-if-no-ref/ uart1_pg6_pins: uart1-pg6-pins { pins = "PG6", "PG7"; @@ -447,6 +453,37 @@ mmc2: mmc@4022000 { #size-cells = <0>; }; + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x04025000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x04026000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@4100000 { compatible = "allwinner,sun20i-d1-musb", "allwinner,sun8i-a33-musb"; -- GitLab From 9b12ceb5a80d1fb45d293265de100e33b5843943 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Fri, 20 Jan 2023 10:14:21 +0100 Subject: [PATCH 216/926] media: dt-bindings: media: rockchip-rga: add rockchip,rk3568-rga Add a new compatible for the rk3568 Rockchip SoC, which also features an RGA, which is called RGA2 in the TRM Part2. It is the same core as used on the rk3288, which documents the same RGA2. Specify a new compatible for the rk3568 to be able to handle unknown SoC-specific differences in the driver. Acked-by: Krzysztof Kozlowski Signed-off-by: Michael Tretter Reviewed-by: Ezequiel Garcia Acked-by: Sakari Ailus Acked-by: Nicolas Dufresne Link: https://lore.kernel.org/r/20230119-rk3568-rga-v1-1-43d4d14365e6@pengutronix.de Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/media/rockchip-rga.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml index dd645ddccb075..ea23422224086 100644 --- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml @@ -21,7 +21,9 @@ properties: - const: rockchip,rk3288-rga - const: rockchip,rk3399-rga - items: - - const: rockchip,rk3228-rga + - enum: + - rockchip,rk3228-rga + - rockchip,rk3568-rga - const: rockchip,rk3288-rga reg: -- GitLab From 0c3391f8bb06b744df521651534cd99e3d77e0a8 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Fri, 20 Jan 2023 10:14:22 +0100 Subject: [PATCH 217/926] arm64: dts: rockchip: Add RGA2 support to rk356x The rk3568 also features a RGA2 block. Add the necessary device tree node. Acked-by: Nicolas Frattaroli Signed-off-by: Michael Tretter Acked-by: Nicolas Dufresne Link: https://lore.kernel.org/r/20230119-rk3568-rga-v1-2-43d4d14365e6@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f62e0fd881a95..f74039d9a8790 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -613,6 +613,17 @@ vdpu_mmu: iommu@fdea0800 { #iommu-cells = <0>; }; + rga: rga@fdeb0000 { + compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; + reg = <0x0 0xfdeb0000 0x0 0x180>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3568_PD_RGA>; + }; + vepu: video-codec@fdee0000 { compatible = "rockchip,rk3568-vepu"; reg = <0x0 0xfdee0000 0x0 0x800>; -- GitLab From addc72dc55118a1e80f8c77767a5c94000248d3d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 May 2023 22:04:51 +0530 Subject: [PATCH 218/926] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 6B Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. Edgeble Neural Compute Module 6B(Neu6B) IO board is an industrial form factor evaluation board from Edgeble AI. Neu6B needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. This patch add dt-bindings for Edgeble Neu6 Model B SoM based IO board. Signed-off-by: Jagan Teki Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230516163454.997736-1-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index f34af97b3c1b3..03fa51cf2028b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -107,6 +107,12 @@ properties: - const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM - const: rockchip,rk3588 + - description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards + items: + - const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board + - const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM + - const: rockchip,rk3588 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 -- GitLab From 8274a04ff1dc76bfc412d389123eb2a5f474549d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 May 2023 22:04:52 +0530 Subject: [PATCH 219/926] arm64: dts: rockchip: Add Rockchip RK3588J MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rockchip RK3588J is the industrial-grade version of RK3588 SoC and is operated with -40 °C to +85 °C temparature. Add rk3588j specific dtsi for adding rk3588j specific operating points and other changes to be add in future. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230516163454.997736-2-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588j.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi new file mode 100644 index 0000000000000..38b9dbf38a218 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" -- GitLab From 08e4dd1d12acc02244b119790c8e50bbf3618a89 Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Fri, 28 Apr 2023 10:06:35 +0200 Subject: [PATCH 220/926] ARM: dts: at91: tse850: add properties for gpio-line-names Signal names are one-to-one copies from the schematics, except VBUS which is an unnamed signal there. Signed-off-by: Peter Rosin [claudiu.beznea: add 1 indentation tab before index based comment] Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/32995b53-7f73-936f-a81d-5f1969f64910@axentia.se --- arch/arm/boot/dts/at91-tse850-3.dts | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index b99a4fb44a364..9d58a3931207e 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -300,3 +300,63 @@ &dbgu { dmas = <0>, <0>; /* Do not use DMA for dbgu */ }; + +&pioA { + gpio-line-names = + /* 0 */ "SUP-A", "SUP-B", "SUP-C", "SIGLIN", + /* 28 */ "RXD", "TXD", "BRX", "BTX"; +}; + +&pioC { + gpio-line-names = + /* 0 */ "ETX0", "ETX1", "ERX0", "ERX1", + /* 4 */ "ETXEN", "ECRSDV", "ERXER", "EREFCK", + /* 8 */ "EMDC", "EMDIO", "", "", + /* 12 */ "", "", "", "/ILIM", + /* 16 */ "BCK", "LRCK", "DIN", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "VBUS"; +}; + +&pioD { + gpio-line-names = + /* 0 */ "I1", "I2", "O1", "EXTVEN", + /* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL", + /* 8 */ "STEREO", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", ">LIN", "LIN>", "", + /* 20 */ "VREFEN", "", "", "", + /* 24 */ "", "", "VINOK", "", + /* 28 */ "POEOK", "USBON", "POELOAD", ""; +}; + +&pioE { + gpio-line-names = + /* 0 */ "", "", "", "", + /* 4 */ "", "", "", "", + /* 8 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "ALE", "CLE", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", "/ETHINT"; +}; -- GitLab From d08f92bdfb2dc4a2a14237cfd8a22c568781797c Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 17 May 2023 12:41:15 +0300 Subject: [PATCH 221/926] ARM: dts: at91: use clock-controller name for PMC nodes Use clock-controller generic name for PMC nodes. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230517094119.2894220-2-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91rm9200.dtsi | 2 +- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g20.dtsi | 2 +- arch/arm/boot/dts/at91sam9g25.dtsi | 2 +- arch/arm/boot/dts/at91sam9g35.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x25.dtsi | 2 +- arch/arm/boot/dts/at91sam9x35.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d3_emac.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- arch/arm/boot/dts/sama7g5.dtsi | 2 +- 19 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 6f9004ebf4245..37b500f6f3956 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -102,7 +102,7 @@ ramc0: ramc@ffffff00 { reg = <0xffffff00 0x100>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 789fe356dbf60..16e3b24b4dddb 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -115,7 +115,7 @@ matrix: matrix@ffffee00 { reg = <0xffffee00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9260-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index ee0bd1aceb3f0..fe9ead867e2ab 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -599,7 +599,7 @@ pioC: gpio@fffff800 { }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9261-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 3ce9ea9873129..ee5e6ed44dd40 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -101,7 +101,7 @@ aic: interrupt-controller@fffff000 { atmel,external-irqs = <30 31>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9263-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 708e1646b7f46..738a43ffd2281 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -41,7 +41,7 @@ adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index d2f13afb35eaf..ec3c77221881c 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -26,7 +26,7 @@ pinctrl@fffff400 { >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index 48c2bc4a7753d..c9cfb93092ee6 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -25,7 +25,7 @@ pinctrl@fffff400 { >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 95f5d76234dbb..76afeb31b7f54 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -129,7 +129,7 @@ matrix: matrix@ffffea00 { reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 83114d26f10d0..c2e7460fb7ff6 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -118,7 +118,7 @@ smc: smc@ffffea00 { reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; #clock-cells = <2>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 364a2ff0a763d..a12e6c419fe3d 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -763,7 +763,7 @@ pioD: gpio@fffffa00 { }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9rl-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 0fe8802e1242b..7036f5f045715 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -27,7 +27,7 @@ pinctrl@fffff400 { >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 0bfa21f18f870..eb03b0497e371 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -26,7 +26,7 @@ pinctrl@fffff400 { >; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 0c26c925761b2..af19ef2a875c4 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -126,7 +126,7 @@ smc: smc@ffffea00 { reg = <0xffffea00 0x200>; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,at91sam9x5-pmc", "syscon"; reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index e67ede940071f..89aafb9a8b0fe 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -1282,7 +1282,7 @@ pioD: gpio@fffffa00 { }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "microchip,sam9x60-pmc", "syscon"; reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 14c35c12a115f..86009dd28e623 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -284,7 +284,7 @@ dma1: dma-controller@f0004000 { clock-names = "dma_clk"; }; - pmc: pmc@f0014000 { + pmc: clock-controller@f0014000 { compatible = "atmel,sama5d2-pmc", "syscon"; reg = <0xf0014000 0x160>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index bde8e92d60bb1..4524a16322d16 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1001,7 +1001,7 @@ pioE: gpio@fffffa00 { }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { compatible = "atmel,sama5d3-pmc", "syscon"; reg = <0xfffffc00 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 45226108850d2..5d7ce13de8ccf 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -30,7 +30,7 @@ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with }; }; - pmc: pmc@fffffc00 { + pmc: clock-controller@fffffc00 { }; macb1: ethernet@f802c000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index af62157ae214f..e94f3a661f4bb 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -250,7 +250,7 @@ dma0: dma-controller@f0014000 { clock-names = "dma_clk"; }; - pmc: pmc@f0018000 { + pmc: clock-controller@f0018000 { compatible = "atmel,sama5d4-pmc", "syscon"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 929ba73702e93..b55adb96a06ec 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -241,7 +241,7 @@ pioA: pinctrl@e0014000 { clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; }; - pmc: pmc@e0018000 { + pmc: clock-controller@e0018000 { compatible = "microchip,sama7g5-pmc", "syscon"; reg = <0xe0018000 0x200>; interrupts = ; -- GitLab From f4f15c5cdc289db798ab0bf32fe83a6701946ef9 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 17 May 2023 12:41:17 +0300 Subject: [PATCH 222/926] ARM: dts: at91: at91sam9n12: witch sckc to new clock bindings Switch slow clock controller to new clock bindings. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230517094119.2894220-4-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91sam9n12.dtsi | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index c2e7460fb7ff6..0e28101b26bf0 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -146,28 +146,11 @@ shdwc@fffffe10 { clocks = <&clk32k>; }; - sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; mmc0: mmc@f0008000 { -- GitLab From 3ecb546333089195b6a1508cb58627b0797a26ca Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 17 May 2023 12:41:18 +0300 Subject: [PATCH 223/926] ARM: dts: at91: use clock-controller name for sckc nodes Use clock-controller generic name for slow clock controller nodes. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230517094119.2894220-5-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 76afeb31b7f54..498cb92b29f96 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -923,7 +923,7 @@ usb2: gadget@fff78000 { status = "disabled"; }; - clk32k: sckc@fffffd50 { + clk32k: clock-controller@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index a12e6c419fe3d..d7e8a115c916c 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -799,7 +799,7 @@ watchdog@fffffd40 { status = "disabled"; }; - clk32k: sckc@fffffd50 { + clk32k: clock-controller@fffffd50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffd50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index af19ef2a875c4..0123ee47151cb 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -154,7 +154,7 @@ pit: timer@fffffe30 { clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 89aafb9a8b0fe..c8bedfa987e57 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -1322,7 +1322,7 @@ pit: timer@fffffe40 { clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "microchip,sam9x60-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 86009dd28e623..5f632e3f039e6 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -704,7 +704,7 @@ watchdog: watchdog@f8048040 { status = "disabled"; }; - clk32k: sckc@f8048050 { + clk32k: clock-controller@f8048050 { compatible = "atmel,sama5d4-sckc"; reg = <0xf8048050 0x4>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 4524a16322d16..0eebf6c760b3d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1040,7 +1040,7 @@ watchdog: watchdog@fffffe40 { status = "disabled"; }; - clk32k: sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,sama5d3-sckc"; reg = <0xfffffe50 0x4>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index e94f3a661f4bb..de6c829692327 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -761,7 +761,7 @@ watchdog: watchdog@fc068640 { status = "disabled"; }; - clk32k: sckc@fc068650 { + clk32k: clock-controller@fc068650 { compatible = "atmel,sama5d4-sckc"; reg = <0xfc068650 0x4>; #clock-cells = <0>; -- GitLab From 23b76ba20e8737aca29e91af5b47a16b15fb1999 Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Fri, 21 Apr 2023 13:37:58 +0200 Subject: [PATCH 224/926] ARM: dts: lan966x: Add support for SMA connectors The pcb8309 has 2 SMA connectors which are connected to the lan966x chip. The lan966x can generate 1PPS output on one of them and it can receive 1PPS input on the other one. Signed-off-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230421113758.3465678-1-horatiu.vultur@microchip.com --- arch/arm/boot/dts/lan966x-pcb8309.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/lan966x-pcb8309.dts index c436cd20d4b4c..0cb505f79ba1a 100644 --- a/arch/arm/boot/dts/lan966x-pcb8309.dts +++ b/arch/arm/boot/dts/lan966x-pcb8309.dts @@ -144,6 +144,18 @@ fc4_b_pins: fc4-b-pins { function = "fc4_b"; }; + pps_out_pins: pps-out-pins { + /* 1pps output */ + pins = "GPIO_38"; + function = "ptpsync_3"; + }; + + ptp_ext_pins: ptp-ext-pins { + /* 1pps input */ + pins = "GPIO_39"; + function = "ptpsync_4"; + }; + sgpio_a_pins: sgpio-a-pins { /* SCK, D0, D1, LD */ pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; @@ -212,5 +224,7 @@ gpio@1 { }; &switch { + pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; status = "okay"; }; -- GitLab From 507ceaa5ca9fac0d9fe2521c29d7d6237c1214f4 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 14 May 2023 20:27:42 -0700 Subject: [PATCH 225/926] arm64: dts: qcom: sc8280xp-crd: Add QMP to SuperSpeed graph With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the two USB Type-C connectors, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Tested-by: Abel Vesa Tested-by: Steev Klimaszewski Tested-by: Neil Armstrong # on HDK8450 Tested-by: Johan Hovold # X13s Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515032743.400170-8-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 28 ++++++++++++++++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 34 +++++++++++++++++++++++ 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 5b25d54b95911..e22f9b65b7b6c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -64,7 +64,7 @@ port@1 { reg = <1>; pmic_glink_con0_ss: endpoint { - remote-endpoint = <&mdss0_dp0_out>; + remote-endpoint = <&usb_0_qmpphy_out>; }; }; @@ -99,7 +99,7 @@ port@1 { reg = <1>; pmic_glink_con1_ss: endpoint { - remote-endpoint = <&mdss0_dp1_out>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; @@ -386,7 +386,7 @@ &mdss0_dp0 { &mdss0_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con0_ss>; + remote-endpoint = <&usb_0_qmpphy_dp_in>; }; &mdss0_dp1 { @@ -395,7 +395,7 @@ &mdss0_dp1 { &mdss0_dp1_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con1_ss>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss0_dp3 { @@ -644,9 +644,19 @@ &usb_0_qmpphy { vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + orientation-switch; + status = "okay"; }; +&usb_0_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp0_out>; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + &usb_0_role_switch { remote-endpoint = <&pmic_glink_con0_hs>; }; @@ -671,9 +681,19 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + orientation-switch; + status = "okay"; }; +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp1_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + &usb_1_role_switch { remote-endpoint = <&pmic_glink_con1_hs>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 91a2d3ab3cc1c..84ef3bd6d49a2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2865,6 +2865,23 @@ usb_0_qmpphy: phy@88eb000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_0_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_hsphy: phy@8902000 { @@ -2901,6 +2918,23 @@ usb_1_qmpphy: phy@8903000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint {}; + }; + }; }; mdss1_dp0_phy: phy@8909a00 { -- GitLab From 42b08375498e74f094425fad10d10c338fd29858 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 14 May 2023 20:27:43 -0700 Subject: [PATCH 226/926] arm64: dts: qcom: sc8280xp-x13s: Add QMP to SuperSpeed graph Following the CRD, connect the two QMP phys inbetween the USB Type-C connectors and the DisplayPort controller, to handle orientation switching. Tested-by: Abel Vesa Tested-by: Steev Klimaszewski Tested-by: Neil Armstrong # on HDK8450 Tested-by: Johan Hovold # X13s Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515032743.400170-9-quic_bjorande@quicinc.com --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index bdcba719fc385..5ae057ad64381 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -106,7 +106,7 @@ port@1 { reg = <1>; pmic_glink_con0_ss: endpoint { - remote-endpoint = <&mdss0_dp0_out>; + remote-endpoint = <&usb_0_qmpphy_out>; }; }; @@ -141,7 +141,7 @@ port@1 { reg = <1>; pmic_glink_con1_ss: endpoint { - remote-endpoint = <&mdss0_dp1_out>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; @@ -528,7 +528,7 @@ &mdss0_dp0 { &mdss0_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con0_ss>; + remote-endpoint = <&usb_0_qmpphy_dp_in>; }; &mdss0_dp1 { @@ -537,7 +537,7 @@ &mdss0_dp1 { &mdss0_dp1_out { data-lanes = <0 1>; - remote-endpoint = <&pmic_glink_con1_ss>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss0_dp3 { @@ -1114,9 +1114,19 @@ &usb_0_qmpphy { vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + orientation-switch; + status = "okay"; }; +&usb_0_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp0_out>; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + &usb_0_role_switch { remote-endpoint = <&pmic_glink_con0_hs>; }; @@ -1141,9 +1151,19 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + orientation-switch; + status = "okay"; }; +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss0_dp1_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + &usb_1_role_switch { remote-endpoint = <&pmic_glink_con1_hs>; }; -- GitLab From ef026e592baa01dd7402511e5ced90f4b3ac3d2c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 17 May 2023 16:52:17 -0700 Subject: [PATCH 227/926] arm64: dts: qcom: sc8280xp: Add SDC2 and enable on CRD The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for enabling this. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517235217.1728548-1-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 81 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 43 ++++++++++++ 2 files changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index e22f9b65b7b6c..cd7e0097d8bc5 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -308,6 +308,13 @@ vreg_l1c: ldo1 { regulator-initial-mode = ; }; + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + vreg_l7c: ldo7 { regulator-name = "vreg_l7c"; regulator-min-microvolt = <2504000>; @@ -318,6 +325,13 @@ vreg_l7c: ldo7 { RPMH_REGULATOR_MODE_HPM>; }; + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + vreg_l13c: ldo13 { regulator-name = "vreg_l13c"; regulator-min-microvolt = <3072000>; @@ -600,6 +614,19 @@ &remoteproc_nsp0 { status = "okay"; }; +&sdc2 { + pinctrl-0 = <&sdc2_default_state>; + pinctrl-1 = <&sdc2_sleep_state>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l9c>; + vqmmc-supply = <&vreg_l6c>; + + cd-gpios = <&tlmm 131 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &uart17 { compatible = "qcom,geni-debug-uart"; @@ -862,6 +889,60 @@ wake-n-pins { }; }; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + tpad_default: tpad-default-state { int-n-pins { pins = "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 84ef3bd6d49a2..4f64adadcdb55 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2845,6 +2845,49 @@ data-pins { }; }; + sdc2: mmc@8804000 { + compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4e0 0x0>; + power-domains = <&rpmhpd SC8280XP_CX>; + operating-points-v2 = <&sdc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; + }; + }; + }; + usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088eb000 0 0x4000>; -- GitLab From 1ebc72ceef2613ba39eaad6caa723a4ff0a04473 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 17 May 2023 13:54:06 +0200 Subject: [PATCH 228/926] ARM: dts: at91: Return to boolean properties Returning back to commit 0dc23d1a8e17 ("arm: dts: at91: Fix boolean properties with values") as pinctrl driver no longer expects an integer value and expects a simple boolean property. Signed-off-by: Ryan Wanner Acked-by: Nicolas Ferre Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/6f06be9e393c02563bc877498c8af75daf3b47f8.1684313910.git.Ryan.Wanner@microchip.com --- arch/arm/boot/dts/at91-kizbox3-hs.dts | 2 +- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 7075df6549e99..fec7269088d10 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -225,7 +225,7 @@ pinctrl_pio_zbe_rst: gpio_zbe_rst { pinctrl_pio_io_reset: gpio_io_reset { pinmux = ; bias-disable; - drive-open-drain = <1>; + drive-open-drain; output-low; }; pinctrl_pio_input: gpio_input { diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index abe27adfa4d65..4656646284199 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -211,7 +211,7 @@ pinctrl_flx4_default: flx4_i2c6_default { pinmux = , //DATA ; //CLK bias-disable; - drive-open-drain = <1>; + drive-open-drain; }; pinctrl_pwm0 { -- GitLab From 4ffec92e70ac5097b9f67ec154065305b16a3b46 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 13:32:25 +0300 Subject: [PATCH 229/926] ARM: dts: gta04: Move model property out of pinctrl node The model property should be at the top level, let's move it out of the pinctrl node. Fixes: d2eaf949d2c3 ("ARM: dts: omap3-gta04a5one: define GTA04A5 variant with OneNAND") Cc: Andreas Kemnade Cc: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04a5one.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/omap3-gta04a5one.dts index 9db9fe67cd63b..95df45cc70c09 100644 --- a/arch/arm/boot/dts/omap3-gta04a5one.dts +++ b/arch/arm/boot/dts/omap3-gta04a5one.dts @@ -5,9 +5,11 @@ #include "omap3-gta04a5.dts" -&omap3_pmx_core { +/ { model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; +}; +&omap3_pmx_core { gpmc_pins: pinmux_gpmc_pins { pinctrl-single,pins = < -- GitLab From 46bab63e1dcf5aa683a47d431aeff79106c0794b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:26:19 +0300 Subject: [PATCH 230/926] ARM: dts: Unify pinctrl-single pin group nodes for omap3 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-craneboard.dts | 2 +- arch/arm/boot/dts/am3517-evm-ui.dtsi | 4 +- arch/arm/boot/dts/am3517-evm.dts | 20 +++---- arch/arm/boot/dts/am3517-som.dtsi | 14 ++--- .../boot/dts/logicpd-som-lv-35xx-devkit.dts | 2 +- .../boot/dts/logicpd-som-lv-37xx-devkit.dts | 2 +- .../boot/dts/logicpd-som-lv-baseboard.dtsi | 16 +++--- arch/arm/boot/dts/logicpd-som-lv.dtsi | 24 ++++----- .../boot/dts/logicpd-torpedo-35xx-devkit.dts | 2 +- .../boot/dts/logicpd-torpedo-37xx-devkit.dts | 6 +-- .../boot/dts/logicpd-torpedo-baseboard.dtsi | 26 ++++----- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 14 ++--- arch/arm/boot/dts/omap3-beagle-xm.dts | 14 ++--- arch/arm/boot/dts/omap3-beagle.dts | 14 ++--- arch/arm/boot/dts/omap3-cm-t3517.dts | 14 ++--- arch/arm/boot/dts/omap3-cm-t3530.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3730.dts | 6 +-- arch/arm/boot/dts/omap3-cm-t3x.dtsi | 20 +++---- arch/arm/boot/dts/omap3-cm-t3x30.dtsi | 4 +- .../arm/boot/dts/omap3-devkit8000-common.dtsi | 2 +- arch/arm/boot/dts/omap3-echo.dts | 12 ++--- arch/arm/boot/dts/omap3-evm-37xx.dts | 4 +- arch/arm/boot/dts/omap3-evm-common.dtsi | 2 +- .../boot/dts/omap3-evm-processor-common.dtsi | 18 +++---- arch/arm/boot/dts/omap3-evm.dts | 4 +- arch/arm/boot/dts/omap3-gta04.dtsi | 54 +++++++++---------- arch/arm/boot/dts/omap3-gta04a5.dts | 10 ++-- arch/arm/boot/dts/omap3-gta04a5one.dts | 2 +- arch/arm/boot/dts/omap3-ha-common.dtsi | 16 +++--- arch/arm/boot/dts/omap3-ha-lcd.dts | 10 ++-- arch/arm/boot/dts/omap3-igep.dtsi | 16 +++--- arch/arm/boot/dts/omap3-igep0020-common.dtsi | 14 ++--- arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 2 +- arch/arm/boot/dts/omap3-igep0020.dts | 2 +- arch/arm/boot/dts/omap3-igep0030-common.dtsi | 10 ++-- arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 4 +- arch/arm/boot/dts/omap3-igep0030.dts | 2 +- arch/arm/boot/dts/omap3-ldp.dts | 6 +-- arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 30 +++++------ arch/arm/boot/dts/omap3-lilly-dbb056.dts | 12 ++--- arch/arm/boot/dts/omap3-n900.dts | 34 ++++++------ arch/arm/boot/dts/omap3-n950-n9.dtsi | 18 +++---- arch/arm/boot/dts/omap3-n950.dts | 8 +-- .../boot/dts/omap3-overo-alto35-common.dtsi | 4 +- arch/arm/boot/dts/omap3-overo-base.dtsi | 14 ++--- arch/arm/boot/dts/omap3-overo-chestnut43.dts | 4 +- arch/arm/boot/dts/omap3-overo-common-dvi.dtsi | 2 +- .../boot/dts/omap3-overo-common-lcd35.dtsi | 10 ++-- .../boot/dts/omap3-overo-common-lcd43.dtsi | 10 ++-- .../dts/omap3-overo-common-peripherals.dtsi | 4 +- arch/arm/boot/dts/omap3-overo-gallop43.dts | 4 +- arch/arm/boot/dts/omap3-overo-palo35.dts | 4 +- arch/arm/boot/dts/omap3-overo-palo43.dts | 4 +- .../boot/dts/omap3-overo-storm-chestnut43.dts | 4 +- .../boot/dts/omap3-overo-storm-gallop43.dts | 4 +- .../arm/boot/dts/omap3-overo-storm-palo35.dts | 4 +- .../arm/boot/dts/omap3-overo-storm-palo43.dts | 4 +- .../arm/boot/dts/omap3-overo-storm-summit.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm.dtsi | 4 +- arch/arm/boot/dts/omap3-overo-summit.dts | 2 +- arch/arm/boot/dts/omap3-overo.dtsi | 4 +- arch/arm/boot/dts/omap3-pandora-1ghz.dts | 6 +-- arch/arm/boot/dts/omap3-pandora-600mhz.dts | 6 +-- arch/arm/boot/dts/omap3-pandora-common.dtsi | 16 +++--- arch/arm/boot/dts/omap3-sb-t35.dtsi | 8 +-- arch/arm/boot/dts/omap3-sbc-t3517.dts | 4 +- arch/arm/boot/dts/omap3-sbc-t3530.dts | 2 +- arch/arm/boot/dts/omap3-sbc-t3730.dts | 2 +- arch/arm/boot/dts/omap3-sniper.dts | 20 +++---- arch/arm/boot/dts/omap3-tao3530.dtsi | 20 +++---- arch/arm/boot/dts/omap3-thunder.dts | 6 +-- arch/arm/boot/dts/omap3-zoom3.dts | 18 +++---- arch/arm/boot/dts/twl4030_omap3.dtsi | 4 +- 73 files changed, 349 insertions(+), 349 deletions(-) diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts index 3642cfc801941..afae7a4d232ef 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/am3517-craneboard.dts @@ -72,7 +72,7 @@ &mmc3 { #include "tps65910.dtsi" &omap3_pmx_core { - tps_pins: pinmux_tps_pins { + tps_pins: tps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */ >; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 75ad42179aeeb..16b8968d5be8a 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -197,7 +197,7 @@ &mcbsp2 { }; &omap3_pmx_core { - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ @@ -206,7 +206,7 @@ OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 11618aa501fc5..af9df15274bed 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -242,7 +242,7 @@ &usbhsehci { &omap3_pmx_core { - ethernet_pins: pinmux_ethernet_pins { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ @@ -257,28 +257,28 @@ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -291,19 +291,19 @@ OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 >; }; - pwm_pins: pinmux_pwm_pins { + pwm_pins: pwm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ @@ -329,7 +329,7 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 >; }; - hsusb1_rst_pins: pinmux_hsusb1_rst_pins { + hsusb1_rst_pins: hsusb1-rst-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; @@ -338,7 +338,7 @@ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ &omap3_pmx_core2 { - hsusb1_pins: pinmux_hsusb1_pins { + hsusb1_pins: hsusb1-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/am3517-som.dtsi index f7b680f6c48ad..bd0a6c95afa16 100644 --- a/arch/arm/boot/dts/am3517-som.dtsi +++ b/arch/arm/boot/dts/am3517-som.dtsi @@ -181,20 +181,20 @@ bluetooth { &omap3_pmx_core { - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { + wl12xx_buffer_pins: wl12xx-buffer-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ @@ -210,19 +210,19 @@ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - rtc_pins: pinmux_rtc_pins { + rtc_pins: rtc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ @@ -235,7 +235,7 @@ OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ &omap3_pmx_wkup { - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + wl12xx_wkup_pins: wl12xx-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ >; diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts index 3240c67e0c392..c1705f6f3d108 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts @@ -15,7 +15,7 @@ / { &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts index c757f0d7781c1..9dbbcc7ced7ce 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts @@ -15,7 +15,7 @@ / { &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi index 7d0468a237818..690f2ad50c653 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi @@ -141,25 +141,25 @@ &mmc1 { }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ >; }; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -172,13 +172,13 @@ OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ >; }; - lcd_enable_pin: pinmux_lcd_enable_pin { + lcd_enable_pin: lcd-enable-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins1 { + dss_dpi_pins1: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -206,13 +206,13 @@ OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) }; &omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { + led_pins_wkup: led-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ >; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index 9ba0ea4eb48a8..c0e6b73fa472d 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -157,7 +157,7 @@ &usbhsehci { &omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { + mmc3_pins: mm3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ @@ -167,7 +167,7 @@ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ @@ -175,7 +175,7 @@ OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -184,7 +184,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -193,7 +193,7 @@ OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -204,7 +204,7 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hs >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -221,7 +221,7 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ @@ -229,21 +229,21 @@ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ >; @@ -252,12 +252,12 @@ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ &omap3_pmx_wkup { - hsusb2_reset_pin: pinmux_hsusb1_reset_pin { + hsusb2_reset_pin: hsusb1-reset-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; - wl127x_gpio: pinmux_wl127x_gpio_pin { + wl127x_gpio: wl127x-gpio-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts index cb08aa62d9671..eaa583fdc3d6b 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts @@ -13,7 +13,7 @@ / { }; &omap3_pmx_core { - isp1763_pins: pinmux_isp1763_pins { + isp1763_pins: isp1763-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 07ea822fe4052..533ce7ce387a5 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -65,7 +65,7 @@ &mt9p031_out { }; &omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { + mmc3_pins: mm3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ @@ -78,7 +78,7 @@ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ }; &omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { + mmc3_core2_pins: mmc3-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -88,7 +88,7 @@ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_c /* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ &omap3_pmx_wkup { - isp1763_pins: pinmux_isp1763_pins { + isp1763_pins: isp1763-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index e0cbac500e172..e0caed5398104 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -209,33 +209,33 @@ &mmc1 { }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ >; }; - hdq_pins: hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ >; }; - pwm_pins: pinmux_pwm_pins { + pwm_pins: pwm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -246,19 +246,19 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ >; }; - isp_pins: pinmux_isp_pins { + isp_pins: isp-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ @@ -276,13 +276,13 @@ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ >; }; - panel_pwr_pins: pinmux_panel_pwr_pins { + panel_pwr_pins: panel-pwr-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins1 { + dss_dpi_pins1: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -313,20 +313,20 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) }; &omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { + gpio_key_pins_wkup: gpio-key-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ >; }; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ >; }; - mmc1_cd: pinmux_mmc1_cd { + mmc1_cd: mmc1-cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ >; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 72b5af475d09c..227699890890a 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -111,7 +111,7 @@ at24@50 { }; &omap3_pmx_core { - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ @@ -119,7 +119,7 @@ OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -128,7 +128,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -136,7 +136,7 @@ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_so OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -153,19 +153,19 @@ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 1a085bc013177..08ee0f8ea68fd 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -90,7 +90,7 @@ hsusb2_power: hsusb2_power_reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; @@ -183,13 +183,13 @@ etm_out: endpoint { }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; - dss_dpi_pins2: pinmux_dss_dpi_pins1 { + dss_dpi_pins2: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ @@ -207,14 +207,14 @@ &omap3_pmx_core { &hsusb2_pins >; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -225,7 +225,7 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_d >; }; - dss_dpi_pins1: pinmux_dss_dpi_pins2 { + dss_dpi_pins1: dss-dpi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -261,7 +261,7 @@ &omap3_pmx_core2 { &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 47ff1ffddfc52..4d9a8eab6abf8 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -57,7 +57,7 @@ hsusb2_power: hsusb2_power_reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ vcc-supply = <&hsusb2_power>; @@ -170,7 +170,7 @@ etm_out: endpoint { }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ >; @@ -183,7 +183,7 @@ &omap3_pmx_core { &hsusb2_pins >; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -194,20 +194,20 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_d >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -247,7 +247,7 @@ &omap3_pmx_core2 { &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index f25c0a84a190c..f776e0527049c 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -43,7 +43,7 @@ wl12xx_vaux2: wl12xx_vaux2 { &omap3_pmx_wkup { - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { + wl12xx_wkup_pins: wl12xx-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ @@ -53,25 +53,25 @@ OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */ &omap3_pmx_core { - phy1_reset_pins: pinmux_hsusb1_phy_reset_pins { + phy1_reset_pins: hsusb1-phy-reset-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */ >; }; - phy2_reset_pins: pinmux_hsusb2_phy_reset_pins { + phy2_reset_pins: hsusb2-phy-reset-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ >; }; - otg_drv_vbus: pinmux_otg_drv_vbus { + otg_drv_vbus: otg-drv-vbus-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -82,14 +82,14 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_da >; }; - wl12xx_core_pins: pinmux_wl12xx_core_pins { + wl12xx_core_pins: wl12xx-core-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ OMAP3_CORE1_IOPAD(0x2176, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - usb_hub_pins: pinmux_usb_hub_pins { + usb_hub_pins: usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_clkx.gpio_152 - USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts index bc545ee23e711..0c6f14963e5ea 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts @@ -23,7 +23,7 @@ mmc2_sdio_reset: regulator-mmc2-sdio-reset { }; &omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index e1b1a047f77a0..f1a8f0fd7a831 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -33,7 +33,7 @@ wl12xx_vaux2: wl12xx_vaux2 { }; &omap3_pmx_wkup { - dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { + dss_dpi_pins_cm_t3730: dss-dpi-cm-t3730-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ @@ -47,7 +47,7 @@ OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ &omap3_pmx_core { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -58,7 +58,7 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_da >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE4) /* dss_data3.gpio_73 */ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 */ diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index e61b8a2bfb7de..f6cd7a3aef1f3 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -47,7 +47,7 @@ hsusb1_phy: hsusb1_phy { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb2_power>; #phy-cells = <0>; @@ -74,14 +74,14 @@ tv_connector_in: endpoint { &omap3_pmx_core { - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -92,13 +92,13 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_da >; }; - green_led_pins: pinmux_green_led_pins { + green_led_pins: green-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ >; }; - dss_dpi_pins_common: pinmux_dss_dpi_pins_common { + dss_dpi_pins_common: dss-dpi-common-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -126,7 +126,7 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { + dss_dpi_pins_cm_t35x: dss-dpi-cm-t35x-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ @@ -137,13 +137,13 @@ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ @@ -152,14 +152,14 @@ OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi index 5e8943539fcc2..0e942513560d6 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi @@ -22,14 +22,14 @@ sound { &omap3_pmx_core { - smsc1_pins: pinmux_smsc1_pins { + smsc1_pins: smsc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_163 */ >; }; - hsusb0_pins: pinmux_hsusb0_pins { + hsusb0_pins: hsusb0-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index 38aa1febc33f3..3b9838f1bb6b3 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -312,7 +312,7 @@ ethernet@6,0 { }; &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts index 06d2377d28adb..263e517944dde 100644 --- a/arch/arm/boot/dts/omap3-echo.dts +++ b/arch/arm/boot/dts/omap3-echo.dts @@ -524,13 +524,13 @@ codec0: codec@18 { #include "tps65910.dtsi" &omap3_pmx_core { - tps_pins: pinmux_tps_pins { + tps_pins: tps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */ @@ -540,7 +540,7 @@ OMAP3_CORE1_IOPAD(0x2a1a, PIN_OUTPUT | MUX_MODE0) /* sys_clkout1.sys_clkout1 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -551,7 +551,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_d >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -566,7 +566,7 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_d >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ @@ -577,7 +577,7 @@ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ }; &omap3_pmx_core2 { - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index abd403c228c7a..e0346bf842fcd 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -17,7 +17,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - ehci_phy_pins: pinmux_ehci_phy_pins { + ehci_phy_pins: ehci-phy-pins { pinctrl-single,pins = < /* EHCI PHY reset GPIO etk_d7.gpio_21 */ @@ -29,7 +29,7 @@ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < /* etk_d10.hsusb2_clk */ diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index 17c89df6ce6b1..1b6023c4cdf31 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -25,7 +25,7 @@ hsusb2_power: hsusb2_power_reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ vcc-supply = <&hsusb2_power>; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi index e6ba30a211663..e27837093e43d 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -33,7 +33,7 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; - dss_dpi_pins1: pinmux_dss_dpi_pins2 { + dss_dpi_pins1: dss-dpi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -62,7 +62,7 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -78,7 +78,7 @@ OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_d }; /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -93,7 +93,7 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ @@ -101,14 +101,14 @@ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irt }; /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ - on_board_gpio_61: pinmux_ehci_port_select_pins { + on_board_gpio_61: ehci-port-select-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) >; }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < /* mcspi1_cs3.hsusb2_data2 */ @@ -135,14 +135,14 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) * Note that gpio_150 pulled high with internal pull to prevent wlcore * reset on return from off mode in idle. */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ >; }; - smsc911x_pins: pinmux_smsc911x_pins { + smsc911x_pins: smsc911x-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; @@ -150,7 +150,7 @@ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ }; &omap3_pmx_wkup { - dss_dpi_pins2: pinmux_dss_dpi_pins1 { + dss_dpi_pins2: dss-dpi1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index f95eea63b355f..a2a1613c45c3e 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -17,7 +17,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_2_pins>; - ehci_phy_pins: pinmux_ehci_phy_pins { + ehci_phy_pins: ehci-phy-pins { pinctrl-single,pins = < /* EHCI PHY reset GPIO etk_d7.gpio_21 */ @@ -29,7 +29,7 @@ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) }; /* Used by OHCI and EHCI. OHCI won't work without external phy */ - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < /* etk_d10.hsusb2_clk */ diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 4183fde460596..b6b27e93857f5 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -153,7 +153,7 @@ pwm11: pwm-11 { ti,clock-source = <0x01>; }; - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; #phy-cells = <0>; @@ -200,7 +200,7 @@ wifi_pwrseq: wifi_pwrseq { }; /* devconf0 setup for mcbsp1 clock pins */ - pinmux_mcbsp1@48002274 { + pinmux@48002274 { compatible = "pinctrl-single"; reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ #address-cells = <1>; @@ -211,14 +211,14 @@ pinmux_mcbsp1@48002274 { #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_devconf0_pins>; - mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { + mcbsp1_devconf0_pins: mcbsp1-devconf0-pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ }; }; /* devconf1 setup for tvout pins */ - pinmux_tv_out@480022d8 { + pinmux@480022d8 { compatible = "pinctrl-single"; reg = <0x480022d8 4>; /* CONTROL_DEVCONF1 */ #address-cells = <1>; @@ -229,7 +229,7 @@ pinmux_tv_out@480022d8 { #pinctrl-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&tv_acbias_devconf1_pins>; - tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { + tv_acbias_devconf1_pins: tv-acbias-devconf1-pins { /* offset bits mask */ pinctrl-single,bits = <0x00 0x40800 0x40800>; /* set TVOUTBYPASS and TVOUTACEN */ }; @@ -237,7 +237,7 @@ tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins { }; &omap3_pmx_wkup { - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_clkout.gpio_10 */ @@ -251,7 +251,7 @@ &omap3_pmx_core { &hsusb2_pins >; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -262,28 +262,28 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_d >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -294,13 +294,13 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_d >; }; - backlight_pins: backlight_pins_pinmux { + backlight_pins: backlight-pinmux-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -333,50 +333,50 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - gps_pins: pinmux_gps_pins { + gps_pins: gps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* gpio145 */ >; }; - hdq_pins: hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */ >; }; - bmp085_pins: pinmux_bmp085_pins { + bmp085_pins: bmp085-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */ >; }; - bma180_pins: pinmux_bma180_pins { + bma180_pins: bma180-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */ >; }; - itg3200_pins: pinmux_itg3200_pins { + itg3200_pins: itg3200-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */ >; }; - hmc5843_pins: pinmux_hmc5843_pins { + hmc5843_pins: hmc5843-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */ >; }; - penirq_pins: pinmux_penirq_pins { + penirq_pins: penirq-pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */ >; }; - camera_pins: pinmux_camera_pins { + camera_pins: camera-pins { pinctrl-single,pins = < /* set up parallel camera interface */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */ @@ -402,7 +402,7 @@ OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */ OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_clkr.mcbsp1_fsr */ @@ -415,7 +415,7 @@ OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_clkx */ @@ -424,7 +424,7 @@ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2_dx */ >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dx */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dx.mcbsp3_dr */ @@ -433,7 +433,7 @@ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_clkx.mcbsp3_fsx */ >; }; - mcbsp4_pins: pinmux_mcbsp4_pins { + mcbsp4_pins: mcbsp4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_clkx */ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcbsp4_clkx.mcbsp4_dr */ @@ -448,7 +448,7 @@ &omap3_pmx_core2 { &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -459,7 +459,7 @@ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - spi_gpio_pins: spi_gpio_pinmux { + spi_gpio_pins: spi-gpio-pinmux-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index 425081201fd42..8bd6b4b1f30b8 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -45,31 +45,31 @@ irda-en-hog { }; &omap3_pmx_core { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat5 = mmc3_dat1 = gpio137 */ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* mmc2_dat6 = mmc3_dat2 = gpio138 */ >; }; - wlan_irq_pin: pinmux_wlan_irq_pin { + wlan_irq_pin: wlan-irq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */ >; }; - irda_pins: pinmux_irda { + irda_pins: irda-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4) /* mcspi1_cs1 = gpio175 */ >; }; - pps_pins: pinmux_pps_pins { + pps_pins: pps-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */ >; diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/omap3-gta04a5one.dts index 95df45cc70c09..1e5703d1b02ee 100644 --- a/arch/arm/boot/dts/omap3-gta04a5one.dts +++ b/arch/arm/boot/dts/omap3-gta04a5one.dts @@ -10,7 +10,7 @@ / { }; &omap3_pmx_core { - gpmc_pins: pinmux_gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* address lines */ diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi index a010585d0302a..3a258a692757f 100644 --- a/arch/arm/boot/dts/omap3-ha-common.dtsi +++ b/arch/arm/boot/dts/omap3-ha-common.dtsi @@ -17,43 +17,43 @@ gpio_poweroff { }; &omap3_pmx_core { - sound2_pins: pinmux_sound2_pins { + sound2_pins: sound2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ >; }; - led_blue_pins: pinmux_led_blue_pins { + led_blue_pins: led-blue-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ >; }; - led_green_pins: pinmux_led_green_pins { + led_green_pins: led-green-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ >; }; - led_red_pins: pinmux_led_red_pins { + led_red_pins: led-red-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ >; }; - poweroff_pins: pinmux_poweroff_pins { + poweroff_pins: poweroff-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ >; }; - powerdown_input_pins: pinmux_powerdown_input_pins { + powerdown_input_pins: powerdown-input-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ >; }; - fpga_boot0_pins: fpga_boot0_pins { + fpga_boot0_pins: fpga-boot0-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ @@ -62,7 +62,7 @@ OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ >; }; - fpga_boot1_pins: fpga_boot1_pins { + fpga_boot1_pins: fpga-boot1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts index 643283f0c3dbb..94f6b7931e333 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -24,19 +24,19 @@ &led_red_pins &touchscreen_wake_pins >; - touchscreen_irq_pins: pinmux_touchscreen_irq_pins { + touchscreen_irq_pins: touchscreen-irq-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ >; }; - touchscreen_wake_pins: pinmux_touchscreen_wake_pins { + touchscreen_wake_pins: touchscreen-wake-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -69,13 +69,13 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 2192026104638..e068ecf86b8f8 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -34,28 +34,28 @@ vdd33: regulator-vdd33 { }; &omap3_pmx_core { - gpmc_pins: pinmux_gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* OneNAND seems to require PIN_INPUT on clock. */ OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */ @@ -64,7 +64,7 @@ OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -75,7 +75,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_da >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -86,14 +86,14 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_da >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index 73d8f471b9ec9..13f434625407a 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -107,13 +107,13 @@ &tfp410_pins &dss_dpi_pins >; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -146,7 +146,7 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ @@ -155,7 +155,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ >; }; - smsc9221_pins: pinmux_smsc9221_pins { + smsc9221_pins: smsc9221-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ >; @@ -168,7 +168,7 @@ &omap3_pmx_core2 { &hsusbb1_pins >; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ @@ -185,7 +185,7 @@ OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_da >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ @@ -193,7 +193,7 @@ OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ >; }; - mmc1_wp_pins: pinmux_mmc1_cd_pins { + mmc1_wp_pins: mmc1-cd-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4) /* etk_d15.gpio_29 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index eadb5b857f48b..316e8e6b39cde 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -24,7 +24,7 @@ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { }; &omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + lbep5clwmc_pins: lbep5clwmc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index 3f0197ceae09e..232cf91878223 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -27,7 +27,7 @@ mmc2_pwrseq: mmc2_pwrseq { }; &omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { + lbee1usjyc_pins: lbee1usjyc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi index 742e3e1470633..d434f75aadaca 100644 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -31,7 +31,7 @@ user2 { }; }; - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ #phy-cells = <0>; @@ -42,7 +42,7 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_pins>; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ @@ -53,7 +53,7 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_d >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ @@ -67,7 +67,7 @@ &omap3_pmx_core2 { pinctrl-names = "default"; pinctrl-0 = <&hsusb2_core2_pins>; - hsusb2_core2_pins: pinmux_hsusb2_core2_pins { + hsusb2_core2_pins: hsusb2-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -78,7 +78,7 @@ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - leds_core2_pins: pinmux_leds_core2_pins { + leds_core2_pins: leds-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index bc95a8df2e6a1..fddd7c86fec4b 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -24,7 +24,7 @@ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { }; &omap3_pmx_core { - lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + lbep5clwmc_pins: lbep5clwmc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ @@ -32,7 +32,7 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_E >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ >; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index d36ceecb7328c..e3f99dbef2a10 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -27,7 +27,7 @@ mmc2_pwrseq: mmc2_pwrseq { }; &omap3_pmx_core { - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { + lbee1usjyc_pins: lbee1usjyc-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 85f33bbb566f9..bb6fab9fa47df 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -223,7 +223,7 @@ &mmc3 { }; &omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2.gpio_101 */ OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE4) /* cam_d3.gpio_102 */ @@ -237,7 +237,7 @@ OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ >; }; - musb_pins: pinmux_musb_pins { + musb_pins: musb-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ @@ -254,7 +254,7 @@ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index c595afe4181d7..005a3d67f3ed1 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -54,19 +54,19 @@ hsusb1_phy: hsusb1_phy { &omap3_pmx_wkup { pinctrl-names = "default"; - lan9221_pins: pinmux_lan9221_pins { + lan9221_pins: lan9221-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ >; }; - tsc2048_pins: pinmux_tsc2048_pins { + tsc2048_pins: tsc2048-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */ >; }; - mmc1cd_pins: pinmux_mmc1cd_pins { + mmc1cd_pins: mmc1cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ >; @@ -76,7 +76,7 @@ OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */ &omap3_pmx_core { pinctrl-names = "default"; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ @@ -85,42 +85,42 @@ OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clkx.uart2_tx */ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc ,PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - hsusb1_pins: pinmux_hsusb1_pins { + hsusb1_pins: hsusb1-pins { pinctrl-single,pins = < /* GPIO 182 controls USB-Hub reset. But USB-Phy its @@ -132,7 +132,7 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT_PULLUP | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) >; }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { + hsusb_otg_pins: hsusb-otg-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ @@ -149,7 +149,7 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -160,7 +160,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_ >; }; - spi2_pins: pinmux_spi2_pins { + spi2_pins: spi2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_clk.mcspi2_clk */ OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi2_simo.mcspi2_simo */ @@ -173,7 +173,7 @@ OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0.mcspi2_cs0 */ &omap3_pmx_core2 { pinctrl-names = "default"; - hsusb1_2_pins: pinmux_hsusb1_2_pins { + hsusb1_2_pins: hsusb1-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ @@ -190,7 +190,7 @@ OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ >; }; - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25fa, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d15.gpio_29 */ >; diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts index f6bbea2be54c5..0891c6682a67e 100644 --- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts +++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts @@ -24,25 +24,25 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&lcd_pins>; - lan9117_pins: pinmux_lan9117_pins { + lan9117_pins: lan9117-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */ >; }; - gpio4_pins: pinmux_gpio4_pins { + gpio4_pins: gpio4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */ >; }; - gpio5_pins: pinmux_gpio5_pins { + gpio5_pins: gpio5-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -> enable DSS */ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -69,7 +69,7 @@ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -86,7 +86,7 @@ OMAP3_CORE1_IOPAD(0x219c, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_rts_sd.gpio_1 >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index f9f9eca0c56cc..d334853412517 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -209,7 +209,7 @@ csi_isp: endpoint { &omap3_pmx_core { pinctrl-names = "default"; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ @@ -218,14 +218,14 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx */ >; }; - ethernet_pins: pinmux_ethernet_pins { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ @@ -233,7 +233,7 @@ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ >; }; - gpmc_pins: pinmux_gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < /* address lines */ @@ -260,34 +260,34 @@ OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - debug_leds: pinmux_debug_led_pins { + debug_leds: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ >; }; - mcspi4_pins: pinmux_mcspi4_pins { + mcspi4_pins: mcspi4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ @@ -296,7 +296,7 @@ OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd */ @@ -307,7 +307,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ @@ -322,13 +322,13 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */ >; }; - acx565akm_pins: pinmux_acx565akm_pins { + acx565akm_pins: acx565akm-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ >; }; - dss_sdi_pins: pinmux_dss_sdi_pins { + dss_sdi_pins: dss-sdi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE1) /* dss_data10.sdi_dat1n */ OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE1) /* dss_data11.sdi_dat1p */ @@ -340,14 +340,14 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ >; }; - wl1251_pins: pinmux_wl1251 { + wl1251_pins: wl1251-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ >; }; - ssi_pins: pinmux_ssi { + ssi_pins: ssi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ @@ -360,7 +360,7 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; - modem_pins: pinmux_modem { + modem_pins: modem-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE4) /* gpio 70 => cmt_apeslpx */ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* gpio 72 => ape_rst_rq */ @@ -371,7 +371,7 @@ modem_pins: pinmux_modem { >; }; - camera_pins: pinmux_camera { + camera_pins: camera-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x210c, PIN_OUTPUT | MUX_MODE7) /* cam_hs */ OMAP3_CORE1_IOPAD(0x210e, PIN_OUTPUT | MUX_MODE7) /* cam_vs */ diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index f68da828b0505..aa4fcdbedd8fb 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -57,20 +57,20 @@ vctcxo: vctcxo { }; &omap3_pmx_core { - accelerator_pins: pinmux_accelerator_pins { + accelerator_pins: accelerator-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ >; }; - debug_leds: pinmux_debug_led_pins { + debug_leds: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */ @@ -81,14 +81,14 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ >; }; - ssi_pins: pinmux_ssi_pins { + ssi_pins: ssi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ @@ -101,7 +101,7 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; - ssi_pins_idle: pinmux_ssi_pins_idle { + ssi_pins_idle: ssi-idle-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ @@ -114,7 +114,7 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ >; }; - modem_pins1: pinmux_modem_core1_pins { + modem_pins1: modem-core1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ @@ -122,7 +122,7 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_ape >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts */ @@ -133,7 +133,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ }; &omap3_pmx_core2 { - modem_pins2: pinmux_modem_core2_pins { + modem_pins2: modem-core2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ >; diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index cbaf79c4e8422..b99f97880204d 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -30,7 +30,7 @@ keypad_slide { }; &omap3_pmx_core { - keypad_slide_pins: pinmux_debug_led_pins { + keypad_slide_pins: debug-led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ >; @@ -38,7 +38,7 @@ OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ }; &omap3_pmx_core { - spi4_pins: pinmux_spi4_pins { + spi4_pins: spi4-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ @@ -49,7 +49,7 @@ OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ }; &omap3_pmx_core { - dsi_pins: pinmux_dsi_pins { + dsi_pins: dsi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE1) /* dsi_dx0 - data0+ */ OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE1) /* dsi_dy0 - data0- */ @@ -60,7 +60,7 @@ OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE1) /* dsi_dy2 - data1- */ >; }; - display_pins: pinmux_display_pins { + display_pins: display-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ca, PIN_INPUT | MUX_MODE4) /* gpio 62 - display te */ OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE4) /* gpio 87 - display reset */ diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi index a6dbbba799b2e..7f1671bf3dfac 100644 --- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi @@ -51,7 +51,7 @@ button0 { }; &omap3_pmx_core { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE4) /* uart1_tx.gpio_148 */ OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ @@ -62,7 +62,7 @@ OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ }; &omap3_pmx_wkup { - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a18, PIN_INPUT | MUX_MODE4) /* sys_clkout1.gpio_10 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index adc714c398257..cc57626ea6076 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -44,7 +44,7 @@ hsusb2_power: hsusb2_power_reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */ vcc-supply = <&hsusb2_power>; @@ -80,7 +80,7 @@ &omap3_pmx_core { &hsusb2_pins >; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ @@ -89,14 +89,14 @@ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -107,7 +107,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_d >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -119,14 +119,14 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_d }; /* WiFi/BT combo */ - w3cbw003c_pins: pinmux_w3cbw003c_pins { + w3cbw003c_pins: w3cbw003c-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ >; }; - hsusb2_pins: pinmux_hsusb2_pins { + hsusb2_pins: hsusb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-chestnut43.dts index d147d704b89f1..bb53c76fff6ca 100644 --- a/arch/arm/boot/dts/omap3-overo-chestnut43.dts +++ b/arch/arm/boot/dts/omap3-overo-chestnut43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi index 339a51fa41198..b1a800f2e940d 100644 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index 1d6e88f99eb31..5a8cb309c71a3 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -41,19 +41,19 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - lb035_pins: pinmux_lb035_pins { + lb035_pins: lb035-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -63,7 +63,7 @@ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT | MUX_MODE0) /* mcspi1_cs1.mcspi1_cs1 */ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi index 7e30f9d45790e..c489c06f6cc78 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi @@ -8,7 +8,7 @@ */ &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -41,19 +41,19 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_OUTPUT | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE4) /* uart2_rts.gpio_145 */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -62,7 +62,7 @@ OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT_PULLDOWN | MUX_MODE4) /* csi2_dx1.gpio_114 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi index 8a4a02472c9a3..00369f699e207 100644 --- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi @@ -24,14 +24,14 @@ lis33_1v8: lis33-1v8-reg { }; &omap3_pmx_core { - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/omap3-overo-gallop43.dts index 24b40bdf7ea1d..d882a58028c14 100644 --- a/arch/arm/boot/dts/omap3-overo-gallop43.dts +++ b/arch/arm/boot/dts/omap3-overo-gallop43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo35.dts b/arch/arm/boot/dts/omap3-overo-palo35.dts index 55e08d56b18b3..39c8e9ce57760 100644 --- a/arch/arm/boot/dts/omap3-overo-palo35.dts +++ b/arch/arm/boot/dts/omap3-overo-palo35.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/omap3-overo-palo43.dts index 092c8325a133d..2c0f755ec8cc5 100644 --- a/arch/arm/boot/dts/omap3-overo-palo43.dts +++ b/arch/arm/boot/dts/omap3-overo-palo43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts index 3af8d10d72247..25e82efe4f3b6 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts index 813e3c9fe3b64..0c93ea3f97743 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts index 8405bd9262de6..9468ef9f9742e 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts index b9558d736e795..9feead5844792 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts @@ -18,14 +18,14 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* etk_d8.gpio_22 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE4) /* etk_d9.gpio_23 */ OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE4) /* etk_d0.gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts index fcfc449f2abea..92f56b9d009d1 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts @@ -18,7 +18,7 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/omap3-overo-storm.dtsi index 2af15d5f61f92..da583b47ed8db 100644 --- a/arch/arm/boot/dts/omap3-overo-storm.dtsi +++ b/arch/arm/boot/dts/omap3-overo-storm.dtsi @@ -12,7 +12,7 @@ &omap3_pmx_core2 { &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -23,7 +23,7 @@ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { + w3cbw003c_2_pins: w3cbw003c-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/omap3-overo-summit.dts index a6c9799fe4915..da5ca80430aeb 100644 --- a/arch/arm/boot/dts/omap3-overo-summit.dts +++ b/arch/arm/boot/dts/omap3-overo-summit.dts @@ -18,7 +18,7 @@ / { }; &omap3_pmx_core2 { - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4) /* etk_d7.gpio_21 */ >; diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index cc9263e99254f..7dc044e87226c 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi @@ -12,7 +12,7 @@ &omap3_pmx_core2 { &hsusb2_2_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -23,7 +23,7 @@ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins { + w3cbw003c_2_pins: w3cbw003c-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ >; diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts index c0252f8a798aa..8d8c9085e6ffe 100644 --- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts @@ -27,7 +27,7 @@ &hsusb2_2_pins &control_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -38,7 +38,7 @@ OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -49,7 +49,7 @@ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 >; }; - control_pins: pinmux_control_pins { + control_pins: control-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/omap3-pandora-600mhz.dts index 6bd9041942f2a..2d5eac3ffc6cd 100644 --- a/arch/arm/boot/dts/omap3-pandora-600mhz.dts +++ b/arch/arm/boot/dts/omap3-pandora-600mhz.dts @@ -27,7 +27,7 @@ &hsusb2_2_pins &control_pins >; - hsusb2_2_pins: pinmux_hsusb2_2_pins { + hsusb2_2_pins: hsusb2-2-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -38,7 +38,7 @@ OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_d >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3430_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ @@ -49,7 +49,7 @@ OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 >; }; - control_pins: pinmux_control_pins { + control_pins: control-pins { pinctrl-single,pins = < OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* etk_d0.gpio_14 = HP_SHUTDOWN */ OMAP3430_CORE2_IOPAD(0x25de, PIN_OUTPUT | MUX_MODE4) /* etk_d1.gpio_15 = BT_SHUTDOWN */ diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 559853764487f..e91000f5f304b 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -205,7 +205,7 @@ lid { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */ vcc-supply = <&vaux2>; @@ -251,7 +251,7 @@ wg7210_32k: fixed-regulator-wg7210_32k { &omap3_pmx_core { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -262,7 +262,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_d >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -277,7 +277,7 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_c >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -311,14 +311,14 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - led_pins: pinmux_leds_pins { + led_pins: leds-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2154, PIN_OUTPUT | MUX_MODE4) /* GPIO_128 */ OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* GPIO_129 */ @@ -327,7 +327,7 @@ OMAP3_CORE1_IOPAD(0x2192, PIN_OUTPUT | MUX_MODE4) /* GPIO_159 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE4) /* GPIO_96 */ OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE4) /* GPIO_97 */ @@ -349,7 +349,7 @@ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* GPIO_176 */ >; }; - penirq_pins: pinmux_penirq_pins { + penirq_pins: penirq-pins { pinctrl-single,pins = < /* here we could enable to wakeup the cpu from suspend by a pen touch */ OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE4) /* GPIO_94 */ diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index 5ec0893415e03..6730c749d5eaf 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -56,27 +56,27 @@ audio_amp: audio_amp { }; &omap3_pmx_core { - smsc2_pins: pinmux_smsc2_pins { + smsc2_pins: smsc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b6, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs4.gpmc_ncs4 */ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - sb_t35_audio_amp: pinmux_sb_t35_audio_amp { + sb_t35_audio_amp: sb-t35-audio-amp-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts index a69d328604219..07bec48dc4416 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts @@ -36,14 +36,14 @@ &sb_t35_usb_hub_pins &usb_hub_pins >; - mmc1_aux_pins: pinmux_mmc1_aux_pins { + mmc1_aux_pins: mmc1-aux-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20c0, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_clk.gpio_59 */ OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE4) /* uart2_cts.gpio_144 */ >; }; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ec, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_98 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts index 24bf3fd86641f..1beefc3194224 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts @@ -20,7 +20,7 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts index 4c36bde62491d..aefc1187ebc9e 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts @@ -20,7 +20,7 @@ &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&sb_t35_usb_hub_pins>; - sb_t35_usb_hub_pins: pinmux_sb_t35_usb_hub_pins { + sb_t35_usb_hub_pins: sb-t35-usb-hub-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* ccdc_wen.gpio_167 - SB-T35 USB HUB RST */ >; diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts index 0591af4941847..79e0040574821 100644 --- a/arch/arm/boot/dts/omap3-sniper.dts +++ b/arch/arm/boot/dts/omap3-sniper.dts @@ -26,48 +26,48 @@ memory@80000000 { &omap3_pmx_core { pinctrl-names = "default"; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ >; }; - dp3t_sel_pins: pinmux_dp3t_sel_pins { + dp3t_sel_pins: dp3t-sel-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE4) /* gpio_161 */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* gpio_162 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; - lp8720_en_pin: pinmux_lp8720_en_pin { + lp8720_en_pin: lp8720-en-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2080, PIN_OUTPUT | MUX_MODE4) /* gpio_37 */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT | MUX_MODE0) /* sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd */ @@ -78,7 +78,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT | MUX_MODE0) /* sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT | MUX_MODE0) /* sdmmc2_cmd */ @@ -93,7 +93,7 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7 */ >; }; - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { + usb_otg_hs_pins: usb-otg-hs-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp */ @@ -114,7 +114,7 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7 */ &omap3_pmx_wkup { pinctrl-names = "default"; - mmc1_cd_pin: pinmux_mmc1_cd_pin { + mmc1_cd_pin: mmc1-cd-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT | MUX_MODE4) /* gpio_10 */ >; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 7f440d11f7e75..92a5846048bd7 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -43,7 +43,7 @@ hsusb2_power: hsusb2_power_reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ vcc-supply = <&hsusb2_power>; @@ -70,7 +70,7 @@ mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { }; &omap3_pmx_core { - hsusbb2_pins: pinmux_hsusbb2_pins { + hsusbb2_pins: hsusbb2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ @@ -87,7 +87,7 @@ OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_d >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -102,7 +102,7 @@ OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_da >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -114,27 +114,27 @@ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_da }; /* wlan GPIO output for WLAN_EN */ - wlan_gpio: pinmux_wlan_gpio { + wlan_gpio: wlan-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ @@ -143,7 +143,7 @@ OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - mcspi3_pins: pinmux_mcspi3_pins { + mcspi3_pins: mcspi3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ @@ -152,7 +152,7 @@ OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INP >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts index d82cab8e213a6..c87956c59b083 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -12,7 +12,7 @@ / { }; &omap3_pmx_core { - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ @@ -45,13 +45,13 @@ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; }; - lte430_pins: pinmux_lte430_pins { + lte430_pins: lte430-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ >; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index ab52e8d68f760..9f1e125fd77b6 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -49,7 +49,7 @@ wl12xx_vmmc: wl12xx_vmmc { &omap3_pmx_core { /* REVISIT: twl gpio0 is mmc0_cd */ - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP3_CORE1_IOPAD(0x2146, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -60,7 +60,7 @@ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_da >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ @@ -75,14 +75,14 @@ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */ OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ @@ -91,7 +91,7 @@ OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -100,7 +100,7 @@ OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -110,7 +110,7 @@ OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irt }; /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ >; @@ -118,7 +118,7 @@ OMAP3_CORE1_IOPAD(0x211a, PIN_OUTPUT| MUX_MODE4) /* cam_d2.gpio_101 */ }; &omap3_pmx_core2 { - mmc3_2_pins: pinmux_mmc3_2_pins { + mmc3_2_pins: mmc3-2-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */ @@ -130,7 +130,7 @@ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 }; &omap3_pmx_wkup { - wlan_host_wkup: pinmux_wlan_host_wkup_pins { + wlan_host_wkup: wlan-host-wkup-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a1a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_clkout1.gpio_10 WLAN_HOST_WKUP */ >; diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi index 683419d5c0e5c..89433f251df03 100644 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi @@ -14,7 +14,7 @@ &omap3_pmx_core { * to the SYS_NIRQ line on OMAP. Therefore, configure the * defaults for the SYS_NIRQ pin here. */ - twl4030_pins: pinmux_twl4030_pins { + twl4030_pins: twl4030-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ >; @@ -28,7 +28,7 @@ OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) / * sys_nvmode2 signaling. */ &omap3_pmx_wkup { - twl4030_vpins: pinmux_twl4030_vpins { + twl4030_vpins: twl4030-vpins-pins { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ -- GitLab From c872f0d7780ad31ff791893822593588b71e2209 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:37:00 +0300 Subject: [PATCH 231/926] ARM: dts: Unify pinctrl-single pin group nodes for omap2 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420-n810.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts index 09c1dbc0bb690..3bf8175d85a82 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -23,7 +23,7 @@ v28_aic: v28_aic { }; &omap2420_pmx { - mcbsp2_pins: mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1) /* eac_ac_sclk.mcbsp2_clkx */ OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1) /* eac_ac_fs.mcbsp2_fsx */ @@ -32,7 +32,7 @@ OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ >; }; - aic33_pins: aic33_pins { + aic33_pins: aic33-pins { pinctrl-single,pins = < OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ -- GitLab From 7fff6f6d6e198ad619fea9dbbe9731999af56070 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:52:53 +0300 Subject: [PATCH 232/926] ARM: dts: Unify pinctrl-single pin group nodes for omap4 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- .../boot/dts/motorola-mapphone-common.dtsi | 40 +++++++++---------- arch/arm/boot/dts/omap4-duovero-parlor.dts | 12 +++--- arch/arm/boot/dts/omap4-duovero.dtsi | 18 ++++----- arch/arm/boot/dts/omap4-kc1.dts | 14 +++---- arch/arm/boot/dts/omap4-mcpdm.dtsi | 2 +- arch/arm/boot/dts/omap4-panda-common.dtsi | 30 +++++++------- arch/arm/boot/dts/omap4-panda-es.dts | 8 ++-- arch/arm/boot/dts/omap4-sdp.dts | 36 ++++++++--------- .../boot/dts/omap4-var-om44customboard.dtsi | 24 +++++------ .../arm/boot/dts/omap4-var-som-om44-wlan.dtsi | 6 +-- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 22 +++++----- arch/arm/boot/dts/twl6030_omap4.dtsi | 4 +- 12 files changed, 108 insertions(+), 108 deletions(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index f7cc8fc678fa5..091ba310053eb 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -352,13 +352,13 @@ isl29030@44 { &omap4_pmx_core { /* hdmi_hpd.gpio_63 */ - hdmi_hpd_gpio: pinmux_hdmi_hpd_pins { + hdmi_hpd_gpio: hdmi-hpd-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) >; }; - hdq_pins: pinmux_hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < /* 0x4a100120 hdq_sio.hdq_sio aa27 */ OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) @@ -366,7 +366,7 @@ OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0) }; /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */ - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) @@ -380,7 +380,7 @@ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) * devices. Off mode value should be tested if we have off mode working * later on. */ - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < /* 0x4a10008e gpmc_wait2.gpio_100 d23 */ OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3) @@ -406,40 +406,40 @@ OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1) }; /* gpmc_ncs0.gpio_50 */ - poweroff_gpio: pinmux_poweroff_pins { + poweroff_gpio: poweroff-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3) >; }; /* kpd_row0.gpio_178 */ - tmp105_irq: pinmux_tmp105_irq { + tmp105_irq: tmp105-irq-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins { + usb_gpio_mux_sel1: usb-gpio-mux-sel1-pins { /* gpio_60 */ pinctrl-single,pins = < OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) >; }; - touchscreen_pins: pinmux_touchscreen_pins { + touchscreen_pins: touchscreen-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - als_proximity_pins: pinmux_als_proximity_pins { + als_proximity_pins: als-proximity-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - usb_mdm6600_pins: pinmux_usb_mdm6600_pins { + usb_mdm6600_pins: usb-mdm6600-pins { pinctrl-single,pins = < /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) @@ -476,7 +476,7 @@ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) >; }; - usb_ulpi_pins: pinmux_usb_ulpi_pins { + usb_ulpi_pins: usb-ulpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) OMAP4_IOPAD(0x198, MUX_MODE7) @@ -496,7 +496,7 @@ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0) }; /* usb0_otg_dp and usb0_otg_dm */ - usb_utmi_pins: pinmux_usb_utmi_pins { + usb_utmi_pins: usb-utmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) @@ -521,7 +521,7 @@ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) * when not used. If needed, we can add rts pin remux later based * on power measurements. */ - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) @@ -538,7 +538,7 @@ OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2) }; /* uart3_tx_irtx and uart3_rx_irrx */ - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) OMAP4_IOPAD(0x198, MUX_MODE7) @@ -557,7 +557,7 @@ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7) >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */ @@ -566,7 +566,7 @@ OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ @@ -575,7 +575,7 @@ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ >; }; - mcbsp3_pins: pinmux_mcbsp3_pins { + mcbsp3_pins: mcbsp3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */ OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */ @@ -584,13 +584,13 @@ OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */ >; }; - vibrator_direction_pin: pinmux_vibrator_direction_pin { + vibrator_direction_pin: vibrator-direction-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */ >; }; - vibrator_enable_pin: pinmux_vibrator_enable_pin { + vibrator_enable_pin: vibrator-enable-pins { pinctrl-single,pins = < OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ >; @@ -598,7 +598,7 @@ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */ }; &omap4_pmx_wkup { - usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins { + usb_gpio_mux_sel2: usb-gpio-mux-sel2-pins { /* gpio_wk0 */ pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3) diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index b294c22177cbf..6d1beb453234e 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -62,33 +62,33 @@ &button_pins &smsc_pins >; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - smsc_pins: pinmux_smsc_pins { + smsc_pins: smsc-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */ OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */ @@ -96,7 +96,7 @@ OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48: amdix enab >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3) /* hdmi_hpd.gpio_63 */ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index 805dfd40030dc..b8af455b411a9 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -73,14 +73,14 @@ &twl6040_pins &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_nxt.gpio_160 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -89,7 +89,7 @@ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -106,34 +106,34 @@ OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_u >; }; - hsusb1phy_pins: pinmux_hsusb1phy_pins { + hsusb1phy_pins: hsusb1phy-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3) /* gpmc_wait1.gpio_62 */ >; }; - w2cbw0015_pins: pinmux_w2cbw0015_pins { + w2cbw0015_pins: w2cbw0015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc1_cmd */ @@ -144,7 +144,7 @@ OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3 */ >; }; - mmc5_pins: pinmux_mmc5_pins { + mmc5_pins: mmc5-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk */ OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmcc5_cmd */ diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts index e59d17b25a1d9..c6b79ba8bbc91 100644 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ b/arch/arm/boot/dts/omap4-kc1.dts @@ -35,42 +35,42 @@ led-2 { &omap4_pmx_core { pinctrl-names = "default"; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ @@ -85,7 +85,7 @@ OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ >; }; - usb_otg_hs_pins: pinmux_usb_otg_hs_pins { + usb_otg_hs_pins: usb-otg-hs-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/omap4-mcpdm.dtsi index 915a9b31a33b4..03ade47431fbe 100644 --- a/arch/arm/boot/dts/omap4-mcpdm.dtsi +++ b/arch/arm/boot/dts/omap4-mcpdm.dtsi @@ -7,7 +7,7 @@ */ &omap4_pmx_core { - mcpdm_pins: pinmux_mcpdm_pins { + mcpdm_pins: mcpdm-pins { pinctrl-single,pins = < /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */ OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 0269424350aae..f528511c2537b 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -237,14 +237,14 @@ &tpd12s015_pins &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -253,7 +253,7 @@ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ @@ -288,13 +288,13 @@ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ >; }; - tfp410_pins: pinmux_tfp410_pins { + tfp410_pins: tfp410-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -302,7 +302,7 @@ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ @@ -310,7 +310,7 @@ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -327,28 +327,28 @@ OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_u >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ @@ -359,7 +359,7 @@ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP * REVISIT: Are the pull-ups needed for GPIO 48 and 49? */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ @@ -369,7 +369,7 @@ OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ }; /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { + wl12xx_pins: wl12xx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ @@ -382,7 +382,7 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ >; @@ -390,7 +390,7 @@ OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ }; &omap4_pmx_wkup { - led_wkgpio_pins: pinmux_leds_wkpins { + led_wkgpio_pins: leds-wkpins-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 7631029e4d7a8..fe7b156d10ed0 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -38,26 +38,26 @@ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ }; &omap4_pmx_core { - led_gpio_pins: gpio_led_pmx { + led_gpio_pins: gpio-led-pmx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ >; }; - button_pins: pinmux_button_pins { + button_pins: button-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 9e976140f34a6..b2cb93edbc3a6 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -214,7 +214,7 @@ &dss_hdmi_pins &tpd12s015_pins >; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -223,7 +223,7 @@ OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -232,21 +232,21 @@ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ >; }; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - dmic_pins: pinmux_dmic_pins { + dmic_pins: dmic-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ @@ -255,7 +255,7 @@ OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ @@ -264,7 +264,7 @@ OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ @@ -273,7 +273,7 @@ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ @@ -282,7 +282,7 @@ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -290,7 +290,7 @@ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ @@ -298,28 +298,28 @@ OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ @@ -327,14 +327,14 @@ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ }; /* wl12xx GPIO output for WLAN_EN */ - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */ >; }; /* wl12xx GPIO inputs and SDIO pins */ - wl12xx_pins: pinmux_wl12xx_pins { + wl12xx_pins: wl12xx-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ @@ -347,13 +347,13 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ }; /* gpio_48 for ENET_ENABLE */ - enet_enable_gpio: pinmux_enet_enable_gpio { + enet_enable_gpio: enet-enable-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */ >; }; - ks8851_pins: pinmux_ks8851_pins { + ks8851_pins: ks8851-pins { pinctrl-single,pins = < /* ENET_INT */ OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */ diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi index 458cb53dd3d18..cadc7e02592bf 100644 --- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi +++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi @@ -60,7 +60,7 @@ hdmi_connector_in: endpoint { }; &omap4_pmx_core { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ @@ -69,7 +69,7 @@ OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ @@ -78,13 +78,13 @@ OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; - mcasp_pins: pinmux_mcsasp_pins { + mcasp_pins: mcsasp-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2) /* mcbsp2_dr.abe_mcasp_axr */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */ OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */ @@ -117,7 +117,7 @@ OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ @@ -125,14 +125,14 @@ OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ >; }; - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc5_pins: pinmux_mmc5_pins { + mmc5_pins: mmc5-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3) /* abe_mcbsp2_clkx.gpio_110 */ OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ @@ -144,32 +144,32 @@ OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */ >; }; - gpio_led_pins: pinmux_gpio_led_pins { + gpio_led_pins: gpio-led-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3) /* kpd_col4.gpio_172 */ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3) /* kpd_col5.gpio_173 */ >; }; - gpio_key_pins: pinmux_gpio_key_pins { + gpio_key_pins: gpio-key-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3) /* sys_boot0.gpio_184 */ >; }; - ks8851_irq_pins: pinmux_ks8851_irq_pins { + ks8851_irq_pins: ks8851-irq-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3) /* kpd_col3.gpio_171 */ >; }; - hdmi_hpd_pins: pinmux_hdmi_hpd_pins { + hdmi_hpd_pins: hdmi-hpd-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ >; }; - backlight_pins: pinmux_backlight_pins { + backlight_pins: backlight-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */ >; diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi index d0032213101e6..de779d2d7c3e9 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi @@ -19,7 +19,7 @@ wl12xx_vmmc: wl12xx_vmmc { }; &omap4_pmx_core { - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ @@ -28,7 +28,7 @@ OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; - wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins { + wl12xx_ctrl_pins: wl12xx-ctrl-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a17.gpio_41 (WLAN_IRQ) */ OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3) /* gpmc_a18.gpio_42 (BT_EN) */ @@ -36,7 +36,7 @@ OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 (WLAN_EN) */ >; }; - mmc4_pins: pinmux_mmc4_pins { + mmc4_pins: mmc4-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_clk.sdmmc4_clk */ OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi4_simo.sdmmc4_cmd */ diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 334cbbaa5b8b0..37d56b3010cff 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -65,21 +65,21 @@ &omap4_pmx_core { &hsusbb1_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */ OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ >; }; - tsc2004_pins: pinmux_tsc2004_pins { + tsc2004_pins: tsc2004-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */ OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ @@ -88,7 +88,7 @@ OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; - hsusbb1_pins: pinmux_hsusbb1_pins { + hsusbb1_pins: hsusbb1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ @@ -105,27 +105,27 @@ OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_u >; }; - hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins { + hsusbb1_phy_rst_pins: hsusbb1-phy-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3) /* kpd_row2.gpio_177 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - i2c3_pins: pinmux_i2c3_pins { + i2c3_pins: i2c3-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ @@ -144,19 +144,19 @@ &hsusbb1_hub_rst_pins &lan7500_rst_pins >; - hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins { + hsusbb1_phy_clk_pins: hsusbb1-phy-clk-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0) /* fref_clk3_out */ >; }; - hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins { + hsusbb1_hub_rst_pins: hsusbb1-hub-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3) /* gpio_wk1 */ >; }; - lan7500_rst_pins: pinmux_lan7500_rst_pins { + lan7500_rst_pins: lan7500-rst-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3) /* gpio_wk0 */ >; diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi index 5730e46b00677..64e38c7c8be70 100644 --- a/arch/arm/boot/dts/twl6030_omap4.dtsi +++ b/arch/arm/boot/dts/twl6030_omap4.dtsi @@ -19,7 +19,7 @@ &twl6030_wkup_pins }; &omap4_pmx_wkup { - twl6030_wkup_pins: pinmux_twl6030_wkup_pins { + twl6030_wkup_pins: twl6030-wkup-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ >; @@ -27,7 +27,7 @@ OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ }; &omap4_pmx_core { - twl6030_pins: pinmux_twl6030_pins { + twl6030_pins: twl6030-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ >; -- GitLab From e141d4a73f57f820511e292d72521b0fad8e334f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:53:49 +0300 Subject: [PATCH 233/926] ARM: dts: Unify pinctrl-single pin group nodes for omap5 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 42 +++++++++++------------ arch/arm/boot/dts/omap5-cm-t54.dts | 32 ++++++++--------- arch/arm/boot/dts/omap5-igep0050.dts | 4 +-- arch/arm/boot/dts/omap5-sbc-t54.dts | 4 +-- arch/arm/boot/dts/omap5-uevm.dts | 6 ++-- 5 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 373984c130e01..6f46f1ecf1e57 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -56,7 +56,7 @@ vmmcsdio_fixed: fixedregulator-mmcsdio { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ clocks = <&auxclk1_ck>; @@ -156,13 +156,13 @@ &usbhost_pins &led_gpio_pins >; - twl6040_pins: pinmux_twl6040_pins { + twl6040_pins: twl6040-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ >; }; - mcpdm_pins: pinmux_mcpdm_pins { + mcpdm_pins: mcpdm-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ @@ -172,7 +172,7 @@ OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_l >; }; - mcbsp1_pins: pinmux_mcbsp1_pins { + mcbsp1_pins: mcbsp1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ @@ -181,7 +181,7 @@ OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1 >; }; - mcbsp2_pins: pinmux_mcbsp2_pins { + mcbsp2_pins: mcbsp2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ @@ -190,14 +190,14 @@ OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ >; }; - mcspi2_pins: pinmux_mcspi2_pins { + mcspi2_pins: mcspi2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ @@ -206,7 +206,7 @@ OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ >; }; - mcspi3_pins: pinmux_mcspi3_pins { + mcspi3_pins: mcspi3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ @@ -215,7 +215,7 @@ OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ @@ -226,20 +226,20 @@ OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */ >; }; /* TI trees use GPIO mode; msecure mode does not work reliably? */ - palmas_msecure_pins: palmas_msecure_pins { + palmas_msecure_pins: palmas-msecure-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */ >; }; - usbhost_pins: pinmux_usbhost_pins { + usbhost_pins: usbhost-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ @@ -252,13 +252,13 @@ OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ >; }; - led_gpio_pins: pinmux_led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ @@ -267,14 +267,14 @@ OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ >; }; - uart5_pins: pinmux_uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ @@ -283,7 +283,7 @@ OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */ OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */ @@ -291,7 +291,7 @@ OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { + tpd12s015_pins: tpd12s015-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ >; @@ -304,20 +304,20 @@ &omap5_pmx_wkup { &usbhost_wkup_pins >; - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { + palmas_sys_nirq_pins: palmas-sys-nirq-pins { pinctrl-single,pins = < /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) >; }; - usbhost_wkup_pins: pinmux_usbhost_wkup_pins { + usbhost_wkup_pins: usbhost-wkup-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ >; }; - wlcore_irq_pin: pinmux_wlcore_irq_pin { + wlcore_irq_pin: wlcore-irq-pin-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ >; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 2d87b9fc230ee..abe0b389ad76d 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -60,7 +60,7 @@ ads7846reg: ads7846-reg { }; /* HS USB Host PHY on PORT 2 */ - hsusb2_phy: hsusb2_phy { + hsusb2_phy: hsusb2-phy-pins { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ #phy-cells = <0>; @@ -176,13 +176,13 @@ dvi_connector_in: endpoint { &omap5_pmx_wkup { - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ >; }; - palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { + palmas_sys_nirq_pins: palmas-sys-nirq-pins { pinctrl-single,pins = < /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */ OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) @@ -197,27 +197,27 @@ &led_gpio_pins &usbhost_pins >; - led_gpio_pins: pinmux_led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ @@ -228,7 +228,7 @@ OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ @@ -243,7 +243,7 @@ OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ @@ -254,14 +254,14 @@ OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ >; }; - wlan_gpios_pins: pinmux_wlan_gpios_pins { + wlan_gpios_pins: wlan-gpios-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ >; }; - usbhost_pins: pinmux_usbhost_pins { + usbhost_pins: usbhost-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ @@ -274,7 +274,7 @@ OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ >; }; - dss_hdmi_pins: pinmux_dss_hdmi_pins { + dss_hdmi_pins: dss-hdmi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x013c, PIN_INPUT | MUX_MODE0) /* hdmi_cec */ OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ @@ -282,19 +282,19 @@ OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ >; }; - hdmi_conn_pins: pinmux_hdmi_conn_pins { + hdmi_conn_pins: hdmi-conn-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + dss_dpi_pins: dss-dpi-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ @@ -327,7 +327,7 @@ OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ >; }; - mcspi2_pins: pinmux_mcspi1_pins { + mcspi2_pins: mcspi1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 3851120857d79..d4ca2e3a14dd8 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -85,14 +85,14 @@ &ldo7_reg { }; &omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ >; }; - power_button_pin: pinctrl_power_button_pin { + power_button_pin: power-button-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ >; diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts index 657df46251c2e..02716fb796bda 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -11,14 +11,14 @@ / { }; &omap5_pmx_core { - i2c4_pins: pinmux_i2c4_pins { + i2c4_pins: i2c4-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ >; }; - mmc1_aux_pins: pinmux_mmc1_aux_pins { + mmc1_aux_pins: mmc1-aux-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 453da9f18a997..933de05d3ca19 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -162,20 +162,20 @@ &mmc1 { }; &omap5_pmx_core { - evm_keys_pins: pinmux_evm_keys_gpio_pins { + evm_keys_pins: evm-keys-gpio-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */ >; }; - i2c5_pins: pinmux_i2c5_pins { + i2c5_pins: i2c5-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */ OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */ >; -- GitLab From c99b88740223ce85f050f9a1e023857f70deec4f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 13:35:51 +0300 Subject: [PATCH 234/926] ARM: dts: Unify pinctrl-single pin group nodes for ti81xx We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3874-iceboard.dts | 16 ++++++++-------- arch/arm/boot/dts/dm8148-evm.dts | 6 +++--- arch/arm/boot/dts/dm8148-t410.dts | 6 +++--- arch/arm/boot/dts/dm8168-evm.dts | 10 +++++----- arch/arm/boot/dts/dra62x-j5eco-evm.dts | 4 ++-- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 791478e81c5ad..ac082e83a9a20 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -285,7 +285,7 @@ i2c@6 { }; &pincntl { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -299,19 +299,19 @@ DM814X_IOPAD(0x093C, PIN_INPUT | 0x2) /* SD1_SDCD */ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; }; - gpio1_pins: pinmux_gpio1_pins { + gpio1_pins: gpio1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80) /* PROGRAM_B */ DM814X_IOPAD(0x0820, PIN_INPUT | 0x80) /* INIT_B */ @@ -336,7 +336,7 @@ DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */ >; }; - gpio2_pins: pinmux_gpio2_pins { + gpio2_pins: gpio2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */ DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */ @@ -349,7 +349,7 @@ DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */ >; }; - gpio4_pins: pinmux_gpio4_pins { + gpio4_pins: gpio4-pins { pinctrl-single,pins = < /* The PLL doesn't react well to the SPI controller reset, so * we force the CS lines to pull up as GPIOs until we're ready. @@ -364,14 +364,14 @@ DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */ >; }; - spi2_pins: pinmux_spi2_pins { + spi2_pins: spi2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */ DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */ >; }; - spi4_pins: pinmux_spi4_pins { + spi4_pins: spi4-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0a7c, 0x20) DM814X_IOPAD(0x0b74, 0x20) diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index fe3f9a970b188..ae8d9fa09d16b 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -116,7 +116,7 @@ &mmc3 { }; &pincntl { - sd1_pins: pinmux_sd1_pins { + sd1_pins: sd1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -129,13 +129,13 @@ DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts index 79ccdd4470f4c..f3e2ecf6d7233 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/dm8148-t410.dts @@ -71,7 +71,7 @@ &mmc3 { }; &pincntl { - sd2_pins: pinmux_sd2_pins { + sd2_pins: sd2-pins { pinctrl-single,pins = < DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[7] */ DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1) /* SD2_DAT[6] */ @@ -87,13 +87,13 @@ DM814X_IOPAD(0x0920, PIN_INPUT | 0x40) /* SD2_SDCD */ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80) /* USB1_DRVVBUS */ >; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 244a957f9ba3a..1d80288f6ba5f 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -30,7 +30,7 @@ sata_refclk: fixedclock0 { }; &dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { + mcspi1_pins: mcspi1-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ @@ -39,7 +39,7 @@ DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ >; }; - mmc_pins: pinmux_mmc_pins { + mmc_pins: mmc-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ @@ -53,19 +53,19 @@ DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ >; }; - nandflash_pins: nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/ DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */ diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 577114c4c20a3..2f6ac267fc150 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -108,7 +108,7 @@ &mmc2 { }; &pincntl { - sd1_pins: pinmux_sd1_pins { + sd1_pins: sd1-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0800, PIN_INPUT | 0x1) /* SD1_CLK */ DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1) /* SD1_CMD */ @@ -121,7 +121,7 @@ DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP | 0x80) /* GP1[6] */ >; }; - usb0_pins: pinmux_usb0_pins { + usb0_pins: usb0-pins { pinctrl-single,pins = < DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1) /* USB0_DRVVBUS */ >; -- GitLab From d73ab823ee9c2bba919eaffc8cc6bb7d71222c17 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:25:03 +0300 Subject: [PATCH 235/926] ARM: dts: Unify pinctrl-single pin group nodes for am33xx We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 4 +- arch/arm/boot/dts/am335x-baltos-ir3220.dts | 8 +-- arch/arm/boot/dts/am335x-baltos-ir5221.dts | 10 ++-- arch/arm/boot/dts/am335x-baltos-leds.dtsi | 2 +- arch/arm/boot/dts/am335x-baltos.dtsi | 20 ++++---- arch/arm/boot/dts/am335x-base0033.dts | 6 +-- arch/arm/boot/dts/am335x-bone-common.dtsi | 22 ++++---- arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi | 6 +-- .../boot/dts/am335x-boneblack-wireless.dts | 8 +-- arch/arm/boot/dts/am335x-boneblue.dts | 34 ++++++------- .../arm/boot/dts/am335x-bonegreen-common.dtsi | 2 +- .../boot/dts/am335x-bonegreen-wireless.dts | 8 +-- arch/arm/boot/dts/am335x-chiliboard.dts | 16 +++--- arch/arm/boot/dts/am335x-chilisom.dtsi | 4 +- arch/arm/boot/dts/am335x-cm-t335.dts | 36 ++++++------- arch/arm/boot/dts/am335x-evm.dts | 40 +++++++-------- arch/arm/boot/dts/am335x-evmsk.dts | 34 ++++++------- arch/arm/boot/dts/am335x-guardian.dts | 30 +++++------ arch/arm/boot/dts/am335x-icev2.dts | 18 +++---- arch/arm/boot/dts/am335x-igep0033.dtsi | 8 +-- arch/arm/boot/dts/am335x-lxm.dts | 16 +++--- .../boot/dts/am335x-moxa-uc-2100-common.dtsi | 12 ++--- arch/arm/boot/dts/am335x-moxa-uc-2101.dts | 4 +- .../boot/dts/am335x-moxa-uc-8100-common.dtsi | 24 ++++----- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 20 ++++---- arch/arm/boot/dts/am335x-myirtech-myd.dts | 50 +++++++++---------- arch/arm/boot/dts/am335x-nano.dts | 20 ++++---- arch/arm/boot/dts/am335x-netcan-plus-1xx.dts | 4 +- arch/arm/boot/dts/am335x-netcom-plus-2xx.dts | 4 +- arch/arm/boot/dts/am335x-netcom-plus-8xx.dts | 6 +-- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 18 +++---- arch/arm/boot/dts/am335x-pcm-953.dtsi | 18 +++---- arch/arm/boot/dts/am335x-pdu001.dts | 28 +++++------ arch/arm/boot/dts/am335x-pepper.dts | 34 ++++++------- arch/arm/boot/dts/am335x-phycore-som.dtsi | 10 ++-- arch/arm/boot/dts/am335x-pocketbeagle.dts | 26 +++++----- arch/arm/boot/dts/am335x-regor.dtsi | 14 +++--- .../boot/dts/am335x-sancloud-bbe-common.dtsi | 6 +-- .../dts/am335x-sancloud-bbe-extended-wifi.dts | 6 +-- .../arm/boot/dts/am335x-sancloud-bbe-lite.dts | 2 +- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 4 +- arch/arm/boot/dts/am335x-sbc-t335.dts | 4 +- arch/arm/boot/dts/am335x-shc.dts | 30 +++++------ arch/arm/boot/dts/am335x-sl50.dts | 46 ++++++++--------- arch/arm/boot/dts/am335x-wega.dtsi | 12 ++--- 45 files changed, 367 insertions(+), 367 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 75992eec830f6..ea5882ed70104 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -18,7 +18,7 @@ / { }; &am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -31,7 +31,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 087e084506d25..ea4f8dde64244 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -18,13 +18,13 @@ / { }; &am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -37,7 +37,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ @@ -52,7 +52,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mca >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index faeb39aab60a7..ec914f27d11df 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -18,21 +18,21 @@ / { }; &am33xx_pinmux { - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) @@ -45,7 +45,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ @@ -60,7 +60,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mca >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ >; diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi index 025014657d12a..6a52e42b9e813 100644 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi @@ -37,7 +37,7 @@ led-app { }; &am33xx_pinmux { - user_leds: pinmux_user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 PWR LED */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mii1_txd3.gpio0_16 WLAN LED */ diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 6161c8929a781..c56087048cc10 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -48,7 +48,7 @@ wl12xx_vmmc: fixedregulator2 { }; &am33xx_pinmux { - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ @@ -60,33 +60,33 @@ AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7) /* emu0.gpio3[ >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ >; }; - tps65910_pins: pinmux_tps65910_pins { + tps65910_pins: tps65910-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ben1.gpio1[28] */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -114,7 +114,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.r >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -141,7 +141,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data.mdio_data */ @@ -149,7 +149,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk.mdio_ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -157,7 +157,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - nandflash_pins_s0: nandflash_pins_s0 { + nandflash_pins_s0: nandflash-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts index 89c00ce42c261..eba843e22ea16 100644 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -41,7 +41,7 @@ led1 { }; &am33xx_pinmux { - nxp_hdmi_pins: pinmux_nxp_hdmi_pins { + nxp_hdmi_pins: nxp-hdmi-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) @@ -66,13 +66,13 @@ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { + nxp_hdmi_off_pins: nxp-hdmi-off-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ >; }; - leds_base_pins: pinmux_leds_base_pins { + leds_base_pins: leds-base-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 02e04a12a2703..0b073f290abc7 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -66,7 +66,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -75,34 +75,34 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) @@ -121,7 +121,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -140,7 +140,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -148,7 +148,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -156,7 +156,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -168,7 +168,7 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi index 486f24deb875c..109f08fd174d6 100644 --- a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi @@ -7,7 +7,7 @@ #include &am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) @@ -33,13 +33,13 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; - mcasp0_pins: mcasp0_pins { + mcasp0_pins: mcasp0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 207d2b63e0eb3..b4b4b80df08cd 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -28,13 +28,13 @@ wlan_en_reg: fixedregulator@2 { }; &am33xx_pinmux { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ @@ -45,7 +45,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1 >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ @@ -54,7 +54,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3 >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 34579e98636e6..b78e38f87892d 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -115,7 +115,7 @@ wlan_en_reg: fixedregulator@2 { }; &am33xx_pinmux { - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ @@ -132,7 +132,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.g >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ @@ -140,7 +140,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart }; /* UT0 */ - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -148,7 +148,7 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) }; /* UT1 */ - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -156,7 +156,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) }; /* GPS */ - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ @@ -164,27 +164,27 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0 }; /* DSM2 */ - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ >; }; /* UT5 */ - uart5_pins: pinmux_uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ @@ -199,7 +199,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ @@ -210,13 +210,13 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_ >; }; - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ @@ -225,7 +225,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ @@ -234,7 +234,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gm }; /* DCAN */ - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ @@ -243,7 +243,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0 }; /* E1 */ - eqep0_pins: pinmux_eqep0_pins { + eqep0_pins: eqep0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ @@ -251,7 +251,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr }; /* E2 */ - eqep1_pins: pinmux_eqep1_pins { + eqep1_pins: eqep1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ @@ -259,7 +259,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13. }; /* E3 */ - eqep2_pins: pinmux_eqep2_pins { + eqep2_pins: eqep2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi index 9f7fb63744d01..383beeddf595d 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi +++ b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi @@ -22,7 +22,7 @@ &mmc2 { }; &am33xx_pinmux { - uart2_pins: uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index d388cffa1a4d6..a4f5b52626456 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -27,13 +27,13 @@ wlan_en_reg: fixedregulator@2 { }; &am33xx_pinmux { - bt_pins: pinmux_bt_pins { + bt_pins: bt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ @@ -44,7 +44,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ @@ -53,7 +53,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3 >; }; - wl18xx_pins: pinmux_wl18xx_pins { + wl18xx_pins: wl18xx-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index a223cdd3e30e8..648e97fe1dfd5 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -36,14 +36,14 @@ led1 { }; &am33xx_pinmux { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -57,7 +57,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -72,7 +72,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* mdio_data.mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -81,7 +81,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -89,13 +89,13 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - usb1_drvvbus: usb1_drvvbus { + usb1_drvvbus: usb1-drvvbus-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - sd_pins: pinmux_sd_card { + sd_pins: sd-card-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0) @@ -107,7 +107,7 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - led_gpio_pins: led_gpio_pins { + led_gpio_pins: led-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */ diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index 43b61e43ed1ee..51021d5822140 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -25,14 +25,14 @@ memory@80000000 { &am33xx_pinmux { pinctrl-names = "default"; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - nandflash_pins: nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 993b134206996..72990e7ffe10e 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -88,14 +88,14 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&bluetooth_pins>; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) @@ -104,14 +104,14 @@ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) >; }; - gpio_led_pins: pinmux_gpio_led_pins { + gpio_led_pins: gpio-led-pins { pinctrl-single,pins = < /* gpmc_csn3.gpio2_0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -132,14 +132,14 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -148,7 +148,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < /* uart1_ctsn.dcan0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) @@ -157,7 +157,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < /* uart1_rxd.dcan1_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) @@ -166,13 +166,13 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) >; }; - ecap0_pins: pinmux_ecap0_pins { + ecap0_pins: ecap0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ /* mii1_tx_en.rgmii1_tctl */ @@ -202,7 +202,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -220,14 +220,14 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -235,7 +235,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -246,7 +246,7 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) @@ -257,7 +257,7 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) }; /* wl1271 bluetooth */ - bluetooth_pins: pinmux_bluetooth_pins { + bluetooth_pins: bluetooth-pins { pinctrl-single,pins = < /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) @@ -265,7 +265,7 @@ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) }; /* TLV320AIC23B codec */ - mcasp1_pins: pinmux_mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < /* MII1_CRS.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) @@ -279,7 +279,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) }; /* wl1271 WiFi */ - wifi_pins: pinmux_wifi_pins { + wifi_pins: wifi-pins { pinctrl-single,pins = < /* EMU1.gpio3_8 - WiFi IRQ */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 5beabaa5ff6a1..6560db1dcdbeb 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -163,7 +163,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - matrix_keypad_s0: matrix_keypad_s0 { + matrix_keypad_s0: matrix-keypad-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -173,35 +173,35 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.g >; }; - volume_keys_s0: volume_keys_s0 { + volume_keys_s0: volume-keys-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -210,13 +210,13 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - nandflash_pins_s0: nandflash_pins_s0 { + nandflash_pins_s0: nandflash-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -236,13 +236,13 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -260,7 +260,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0 >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -278,7 +278,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -286,7 +286,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -294,7 +294,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -307,7 +307,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.m >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ @@ -318,7 +318,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc >; }; - wlan_pins: pinmux_wlan_pins { + wlan_pins: wlan-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ @@ -326,7 +326,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcas >; }; - lcd_pins_s0: lcd_pins_s0 { + lcd_pins_s0: lcd-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ @@ -359,7 +359,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -368,7 +368,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1 >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -377,7 +377,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 5b3278c0c46a5..332f6c8ae68b1 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -202,7 +202,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ @@ -235,7 +235,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - lcd_pins_sleep: lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ @@ -269,7 +269,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) }; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ @@ -278,7 +278,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7. >; }; - gpio_keys_s0: gpio_keys_s0 { + gpio_keys_s0: gpio-keys-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ @@ -287,33 +287,33 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - ecap2_pins: backlight_pins { + ecap2_pins: backlight-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -345,7 +345,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.r >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -377,7 +377,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -385,7 +385,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -393,7 +393,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -406,7 +406,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.m >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -415,7 +415,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1 >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -424,7 +424,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ @@ -436,7 +436,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc >; }; - wl12xx_gpio: pinmux_wl12xx_gpio { + wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ >; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index b357364e93f99..3031fc9061a4b 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -481,14 +481,14 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin &guardian_interface_pins>; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; }; - guardian_interface_pins: pinmux_interface_pins { + guardian_interface_pins: interface-pins { pinctrl-single,pins = < /* ADC_BATSENSE_EN */ /* (A14) MCASP0_AHCLKx.gpio3[21] */ @@ -518,13 +518,13 @@ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) >; }; - guardian_beeper_pins: pinmux_dmtimer7_pins { + guardian_beeper_pins: dmtimer7-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) /* (E18) timer7 */ >; }; - guardian_button_pins: pinmux_guardian_button_pins { + guardian_button_pins: guardian-button-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ @@ -532,28 +532,28 @@ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) /* (V9) gpmc_csn2.gpio1[31] */ }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - led_bl_pins: gpio_led_bl_pins { + led_bl_pins: gpio-led-bl-pins { pinctrl-single,pins = < /* P9_14, gpmc_a[2].GPIO1[18] (backlight control) */ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) >; }; - lcd_disen_pins: pinmux_lcd_disen_pins { + lcd_disen_pins: lcd-disen-pins { pinctrl-single,pins = < /* P9_27, mcasp0_fsr.gpio3[19] (lcd_disen) */ AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) >; }; - lcd_pins_default: pinmux_lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < /* (U10) gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) @@ -614,7 +614,7 @@ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) >; }; - lcd_pins_sleep: pinmux_lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) @@ -659,13 +659,13 @@ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) >; }; - guardian_led_pins: pinmux_guardian_led_pins { + guardian_led_pins: guardian-led-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) /* (T16) gpmc_a10.gpio1[26] */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ @@ -677,7 +677,7 @@ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < /* SPI0_CLK - spi0_clk.spi */ AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) @@ -690,7 +690,7 @@ AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < /* uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) @@ -699,7 +699,7 @@ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < /* K18 uart2_rxd.mirx_txd */ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) @@ -708,7 +708,7 @@ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 5835c0cdda50b..7ed2321a8b402 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -152,7 +152,7 @@ gpio-decoder { }; &am33xx_pinmux { - user_leds: user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ @@ -163,7 +163,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txc >; }; - mmc0_pins_default: mmc0_pins_default { + mmc0_pins_default: mmc0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -174,14 +174,14 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c0_pins_default: i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - spi0_pins_default: spi0_pins_default { + spi0_pins_default: spi0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -192,14 +192,14 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* (B12) mc >; }; - uart3_pins_default: uart3_pins_default { + uart3_pins_default: uart3-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1, RMII mode */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -222,7 +222,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rm >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -246,7 +246,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -254,7 +254,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 3fddf80dcf714..4aed736554016 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -52,14 +52,14 @@ vmmc: fixedregulator1 { }; &am33xx_pinmux { - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - nandflash_pins: pinmux_nandflash_pins { + nandflash_pins: nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -79,14 +79,14 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ >; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index 1282dae144ddc..008be696327aa 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -41,7 +41,7 @@ vmmcsd_fixed: fixedregulator1 { }; &am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -52,14 +52,14 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ @@ -85,7 +85,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refc >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ @@ -111,7 +111,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refc >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -119,7 +119,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -127,7 +127,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -142,7 +142,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 49e280b42442f..b8730aa52ce6f 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -31,27 +31,27 @@ buttons: push_button { &am33xx_pinmux { pinctrl-names = "default"; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - push_button_pins: pinmux_push_button { + push_button_pins: push-button-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -59,7 +59,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - mmc1_pins_default: pinmux_mmc1_pins { + mmc1_pins_default: mmc1-pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ @@ -75,7 +75,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.m >; }; - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts index 1cc513ed92ccf..e986945ac1b5f 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts @@ -28,7 +28,7 @@ led1 { &am33xx_pinmux { pinctrl-names = "default"; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ @@ -42,7 +42,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - spi1_pins: pinmux_spi1 { + spi1_pins: spi1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index 7d00e8b20f18a..c16f3cff1e4ba 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -38,7 +38,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins>; - minipcie_pins: pinmux_minipcie { + minipcie_pins: minipcie-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ @@ -46,13 +46,13 @@ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync >; }; - push_button_pins: pinmux_push_button { + push_button_pins: push-button-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) @@ -60,21 +60,21 @@ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -83,7 +83,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ @@ -92,7 +92,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -117,7 +117,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_ref >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -125,7 +125,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - mmc0_pins_default: pinmux_mmc0_pins { + mmc0_pins_default: mmc0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -138,7 +138,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp >; }; - mmc2_pins_default: pinmux_mmc2_pins { + mmc2_pins_default: mmc2-pins { pinctrl-single,pins = < /* eMMC */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ @@ -154,7 +154,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc >; }; - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 6eea18b293557..c721707e1430b 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -159,21 +159,21 @@ &rtc { }; &am33xx_pinmux { - mdio_pins_default: pinmux_mdio_pins_default { + mdio_pins_default: mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */ >; }; - mdio_pins_sleep: pinmux_mdio_pins_sleep { + mdio_pins_sleep: mdio-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - eth_slave1_pins_default: pinmux_eth_slave1_pins_default { + eth_slave1_pins_default: eth-slave1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */ @@ -190,7 +190,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_r >; }; - eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep { + eth_slave1_pins_sleep: eth-slave1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -207,34 +207,34 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - i2c0_pins_default: pinmux_i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */ >; }; - i2c0_pins_gpio: pinmux_i2c0_pins_gpio { + i2c0_pins_gpio: i2c0-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */ >; }; - i2c0_pins_sleep: pinmux_i2c0_pins_sleep { + i2c0_pins_sleep: i2c0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - led_mod_pins: pinmux_led_mod_pins { + led_mod_pins: led-mod-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */ >; }; - nand_pins_default: pinmux_nand_pins_default { + nand_pins_default: nand-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */ @@ -254,7 +254,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_c >; }; - nand_pins_sleep: pinmux_nand_pins_sleep { + nand_pins_sleep: nand-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 425ad9b81a68a..d3bba79b9358c 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -304,47 +304,47 @@ &vdd_mod { }; &am33xx_pinmux { - dcan0_pins_default: pinmux_dcan0_pins_default { + dcan0_pins_default: dcan0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */ >; }; - dcan0_pins_sleep: pinmux_dcan0_pins_sleep { + dcan0_pins_sleep: dcan0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - dcan1_pins_default: pinmux_dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */ >; }; - dcan1_pins_sleep: pinmux_dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default { + ehrpwm0_pins_default: ehrpwm0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */ >; }; - ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep { + ehrpwm0_pins_sleep: ehrpwm0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - eth_slave2_pins_default: pinmux_eth_slave2_pins_default { + eth_slave2_pins_default: eth-slave2-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */ @@ -361,7 +361,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 >; }; - eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep { + eth_slave2_pins_sleep: eth-slave2-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -378,35 +378,35 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - gpio_buttons_pins: pinmux_gpio_buttons_pins { + gpio_buttons_pins: gpio-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */ >; }; - i2c1_pins_default: pinmux_i2c1_pins_default { + i2c1_pins_default: i2c1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */ >; }; - i2c1_pins_gpio: pinmux_i2c1_pins_gpio { + i2c1_pins_gpio: i2c1-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */ >; }; - i2c1_pins_sleep: pinmux_i2c1_pins_sleep { + i2c1_pins_sleep: i2c1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - lcdc_pins_default: pinmux_lcdc_pins_default { + lcdc_pins_default: lcdc-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */ @@ -431,7 +431,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias >; }; - lcdc_pins_sleep: pinmux_lcdc_pins_sleep { + lcdc_pins_sleep: lcdc-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) @@ -456,14 +456,14 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - leds_pins: pinmux_leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */ >; }; - mcasp0_pins_default: pinmux_mcasp0_pins_default { + mcasp0_pins_default: mcasp0-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */ @@ -472,7 +472,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0 >; }; - mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep { + mcasp0_pins_sleep: mcasp0-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -481,7 +481,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */ @@ -493,7 +493,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -505,42 +505,42 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */ >; }; - uart1_pins_default: pinmux_uart1_pins_default { + uart1_pins_default: uart1-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */ >; }; - uart1_pins_sleep: pinmux_uart1_pins_sleep { + uart1_pins_sleep: uart1-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - uart2_pins_default: pinmux_uart2_pins_default { + uart2_pins_default: uart2-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */ >; }; - uart2_pins_sleep: pinmux_uart2_pins_sleep { + uart2_pins_sleep: uart2-sleep-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - usb_pins: pinmux_usb_pins { + usb_pins: usb-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */ AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */ diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index c447aebd8d866..9305ba9d85eff 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -36,13 +36,13 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&misc_pins>; - misc_pins: misc_pins { + misc_pins: misc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ >; }; - gpmc_pins: gpmc_pins { + gpmc_pins: gpmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -86,21 +86,21 @@ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - uart0_pins: uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart1_pins: uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) @@ -109,7 +109,7 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart2_pins: uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ @@ -118,7 +118,7 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd >; }; - uart3_pins: uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ @@ -127,7 +127,7 @@ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in >; }; - uart4_pins: uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ @@ -136,14 +136,14 @@ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart >; }; - uart5_pins: uart5_pins { + uart5_pins: uart5-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ >; }; - mmc1_pins: mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts index 2e049489ac066..f7fad48e36edf 100644 --- a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts +++ b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts @@ -37,14 +37,14 @@ led@2 { }; &am33xx_pinmux { - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */ diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts index 6ed886c3306be..76751a324ad75 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts @@ -18,7 +18,7 @@ / { }; &am33xx_pinmux { - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ @@ -31,7 +31,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI * >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts index ad3adc7679f98..5a9fcec040fae 100644 --- a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts +++ b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts @@ -20,7 +20,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&dip_switches>; - dip_switches: pinmux_dip_switches { + dip_switches: dip-switches-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -29,13 +29,13 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - tca6416_pins: pinmux_tca6416_pins { + tca6416_pins: tca6416-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3) diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index b2846cd220f04..d28d397288476 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -239,25 +239,25 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11. >; }; - flash_enable: flash-enable { + flash_enable: flash-enable-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ >; }; - imu_interrupt: imu-interrupt { + imu_interrupt: imu-interrupt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ >; }; - ethernet_interrupt: ethernet-interrupt{ + ethernet_interrupt: ethernet-interrupt-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ >; }; - user_leds_s0: user-leds-s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -280,13 +280,13 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - clkout2_pin: pinmux-clkout2-pin { + clkout2_pin: pinmux-clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw-default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -304,7 +304,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) >; }; - cpsw_sleep: cpsw-sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -322,7 +322,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci-mdio-default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -330,7 +330,7 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci-mdio-sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 67c7fcc52ce6d..75efe1cf1dd23 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -68,14 +68,14 @@ button-1 { }; &am33xx_pinmux { - user_buttons_pins: pinmux-user-buttons { + user_buttons_pins: pinmux-user-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ >; }; - user_leds_pins: pinmux-user-leds { + user_leds_pins: pinmux-user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ @@ -85,7 +85,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn /* CAN */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ @@ -101,7 +101,7 @@ &dcan1 { /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { + ethernet1_pins: ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ @@ -142,7 +142,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&cb_gpio_pins>; - cb_gpio_pins: pinmux-cb-gpio { + cb_gpio_pins: pinmux-cb-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ @@ -176,14 +176,14 @@ &mmc1 { /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux-uart1 { + uart1_pins: pinmux-uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -192,14 +192,14 @@ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart2_pins: pinmux-uart2 { + uart2_pins: pinmux-uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; - uart3_pins: pinmux-uart3 { + uart3_pins: pinmux-uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts index ce6cc2b96654f..92a1d5fea850c 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/am335x-pdu001.dts @@ -90,28 +90,28 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_clk.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d0.i2c2_scl */ >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -120,7 +120,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3) /* mcasp0_ahclk >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) @@ -128,27 +128,27 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart3_pins: pinmux_uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; }; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Port 1 (emac0) */ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0) @@ -186,14 +186,14 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1) /* mii2_col.gpmc_ben >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { /* eMMC */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) @@ -205,7 +205,7 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - mmc2_pins: pinmux_mmc2_pins { + mmc2_pins: mmc2-pins { /* SD cardcage */ pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ @@ -219,7 +219,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7) /* gpmc_advn_ale >; }; - lcd_pins_s0: lcd_pins_s0 { + lcd_pins_s0: lcd-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -244,7 +244,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart1_rtsn.d_can0_rx */ diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index a4509e9e1056c..5a87b25a983bf 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -26,7 +26,7 @@ buttons: user_buttons { compatible = "gpio-keys"; }; - leds: user_leds { + leds: user-leds-pins { compatible = "gpio-leds"; }; @@ -88,13 +88,13 @@ &i2c1 { }; &am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c1_pins: pinmux_i2c1 { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_crs,i2c1_sda */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE3) /* mii1_rxerr,i2c1_scl */ @@ -125,7 +125,7 @@ &accel { }; &am33xx_pinmux { - accel_pins: pinmux_accel { + accel_pins: accel-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; @@ -172,7 +172,7 @@ &mcasp0 { }; &am33xx_pinmux { - audio_pins: pinmux_audio { + audio_pins: audio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -223,7 +223,7 @@ &lcdc { }; &am33xx_pinmux { - lcd_pins: pinmux_lcd { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -292,7 +292,7 @@ &mac_sw { }; &am33xx_pinmux { - ethernet_pins: pinmux_ethernet { + ethernet_pins: ethernet-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ @@ -313,7 +313,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) /* mii1_col.gp >; }; - mdio_pins: pinmux_mdio { + mdio_pins: mdio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) @@ -357,7 +357,7 @@ &mmc3 { &am33xx_pinmux { - sd_pins: pinmux_sd_card { + sd_pins: sd-card-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -368,7 +368,7 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - emmc_pins: pinmux_emmc { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -384,7 +384,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ >; }; - wireless_pins: pinmux_wireless { + wireless_pins: wireless-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ @@ -491,7 +491,7 @@ &spi0 { }; &am33xx_pinmux { - spi0_pins: pinmux_spi0 { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) @@ -532,13 +532,13 @@ &uart1 { }; &am33xx_pinmux { - uart0_pins: pinmux_uart0 { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1 { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -563,7 +563,7 @@ &usb1 { }; &am33xx_pinmux { - usb_pins: pinmux_usb { + usb_pins: usb-pins { pinctrl-single,pins = < /* USB0 Over-Current (active low) */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7) /* gpmc_a9.gpio1_25 */ @@ -620,14 +620,14 @@ button-2 { }; &am33xx_pinmux { - user_leds_pins: pinmux_user_leds { + user_leds_pins: user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE7) /* gpmc_a4.gpio1_20 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ >; }; - user_buttons_pins: pinmux_user_buttons { + user_buttons_pins: user-buttons-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_a7.gpio1_21 */ diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 034dc51816794..feb3f4c249780 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -76,7 +76,7 @@ &mmc2 { /* Ethernet */ &am33xx_pinmux { - ethernet0_pins: pinmux_ethernet0 { + ethernet0_pins: ethernet0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) @@ -89,7 +89,7 @@ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - mdio_pins: pinmux_mdio { + mdio_pins: mdio-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -125,7 +125,7 @@ &mac_sw { /* I2C Busses */ &am33xx_pinmux { - i2c0_pins: pinmux-i2c0 { + i2c0_pins: pinmux-i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) @@ -165,7 +165,7 @@ i2c_rtc: rtc@68 { /* NAND memory */ &am33xx_pinmux { - nandflash_pins: pinmux-nandflash { + nandflash_pins: pinmux-nandflash-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -316,7 +316,7 @@ vmmc_reg: regulator@12 { /* SPI Busses */ &am33xx_pinmux { - spi0_pins: pinmux-spi0 { + spi0_pins: pinmux-spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts index 0ba4883cd4eff..5dfe4d4bab934 100644 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts @@ -214,7 +214,7 @@ &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio &P2_17_gpio >; /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ - P2_03_gpio: pinmux_P2_03_gpio { + P2_03_gpio: P2-03-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -223,7 +223,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ - P1_34_gpio: pinmux_P1_34_gpio { + P1_34_gpio: P1-34-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -232,7 +232,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ - P2_19_gpio: pinmux_P2_19_gpio { + P2_19_gpio: P2-19-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -241,7 +241,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ - P2_24_gpio: pinmux_P2_24_gpio { + P2_24_gpio: P2-24-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -250,7 +250,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ - P2_33_gpio: pinmux_P2_33_gpio { + P2_33_gpio: P2-33-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -259,7 +259,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ - P2_22_gpio: pinmux_P2_22_gpio { + P2_22_gpio: P2-22-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -268,7 +268,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ - P2_18_gpio: pinmux_P2_18_gpio { + P2_18_gpio: P2-18-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -277,7 +277,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ - P2_10_gpio: pinmux_P2_10_gpio { + P2_10_gpio: P2-10-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -286,7 +286,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ - P2_06_gpio: pinmux_P2_06_gpio { + P2_06_gpio: P2-06-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -295,7 +295,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ - P2_04_gpio: pinmux_P2_04_gpio { + P2_04_gpio: P2-04-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -304,7 +304,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ - P2_02_gpio: pinmux_P2_02_gpio { + P2_02_gpio: P2-02-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) >; @@ -313,7 +313,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) }; /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ - P2_08_gpio: pinmux_P2_08_gpio { + P2_08_gpio: P2-08-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) >; @@ -322,7 +322,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) }; /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ - P2_17_gpio: pinmux_P2_17_gpio { + P2_17_gpio: P2-17-gpio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) >; diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi index 3894f14a914cf..625db3bcd3656 100644 --- a/arch/arm/boot/dts/am335x-regor.dtsi +++ b/arch/arm/boot/dts/am335x-regor.dtsi @@ -39,7 +39,7 @@ error-led { /* User Leds */ &am33xx_pinmux { - user_leds_pins: pinmux-user-leds { + user_leds_pins: pinmux-user-leds-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ @@ -49,7 +49,7 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -65,7 +65,7 @@ &dcan1 { /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1 { + ethernet1_pins: pinmux-ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -108,7 +108,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&user_gpios_pins>; - user_gpios_pins: pinmux-user-gpios { + user_gpios_pins: pinmux-user-gpios-pins { pinctrl-single,pins = < /* DIGIN 1-4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ @@ -126,7 +126,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux-mmc1 { + mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -155,14 +155,14 @@ &i2c_rtc { /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart2_pins: pinmux-uart2 { + uart2_pins: pinmux-uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi index f9b7e774ac48d..a138eb3568744 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi @@ -4,7 +4,7 @@ */ &am33xx_pinmux { - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -22,7 +22,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0 >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -40,7 +40,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - usb_hub_ctrl: usb_hub_ctrl { + usb_hub_ctrl: usb-hub-ctrl-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ >; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts index a2676d10c24af..5522759def266 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -28,7 +28,7 @@ wlan_en_reg: fixedregulator@2 { }; &am33xx_pinmux { - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < /* gpmc_a9.gpio1_25: RADIO_EN */ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) @@ -53,14 +53,14 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) >; }; - bluetooth_pins: pinmux_bluetooth_pins { + bluetooth_pins: bluetooth-pins { pinctrl-single,pins = < /* event_intr0.gpio0_19 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < /* uart1_rxd */ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts index d6ef19311a914..b1b400226d837 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts @@ -19,7 +19,7 @@ / { }; &am33xx_pinmux { - bb_spi0_pins: pinmux_bb_spi0_pins { + bb_spi0_pins: bb-spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts index efbe93135dbe4..32669346cefe8 100644 --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts @@ -17,13 +17,13 @@ / { }; &am33xx_pinmux { - mpu6050_pins: pinmux_mpu6050_pins { + mpu6050_pins: mpu6050-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ >; }; - lps3331ap_pins: pinmux_lps3331ap_pins { + lps3331ap_pins: lps3331ap-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ >; diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts index 81e4453687ba1..596774c847448 100644 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/am335x-sbc-t335.dts @@ -64,7 +64,7 @@ timing1: dvi { /* 1024x768p60 */ &am33xx_pinmux { /* Display */ - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) @@ -105,7 +105,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) >; }; - lcd_pins_sleep: lcd_pins_sleep { + lcd_pins_sleep: lcd-sleep-pins { pinctrl-single,pins = < /* gpmc_ad8.lcd_data23 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index c497200f9cb0b..9297cb1efcd4b 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -366,14 +366,14 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; - clkout2_pin: pinmux_clkout2_pin { + clkout2_pin: clkout2-pins { pinctrl-single,pins = < /* xdma_event_intr1.clkout2 */ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -392,7 +392,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0) >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -411,14 +411,14 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -426,13 +426,13 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - ehrpwm1_pins: pinmux_ehrpwm1 { + ehrpwm1_pins: ehrpwm1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) @@ -447,20 +447,20 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5) >; }; - mmc3_pins: pinmux_mmc3_pins { + mmc3_pins: mmc3-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3) AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3) @@ -471,7 +471,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3) >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0) @@ -480,7 +480,7 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1 { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0) @@ -489,21 +489,21 @@ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6) >; }; - user_leds_s0: user_leds_s0 { + user_leds_s0: user-leds-s0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7) diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 73b5d1a024bd1..d35ed80de0f02 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -213,7 +213,7 @@ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&lwb_pins>; - audio_pins: pinmux_audio_pins { + audio_pins: audio-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -223,31 +223,31 @@ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) >; }; - audio_pa_pins: pinmux_audio_pa_pins { + audio_pa_pins: audio-pa-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7) /* SoundPA_en - mcasp0_aclkr.gpio3_18 */ >; }; - audio_mclk_pins: pinmux_audio_mclk_pins { + audio_mclk_pins: audio-mclk-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ >; }; - backlight0_pins: pinmux_backlight0_pins { + backlight0_pins: backlight0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7) /* gpmc_wen.gpio2_4 */ >; }; - backlight1_pins: pinmux_backlight1_pins { + backlight1_pins: backlight1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */ >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) @@ -272,7 +272,7 @@ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - led_pins: pinmux_led_pins { + led_pins: led-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* gpmc_a5.gpio1_21 */ AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* gpmc_a6.gpio1_22 */ @@ -281,42 +281,42 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart4_pins: pinmux_uart4_pins { + uart4_pins: uart4-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* gpmc_wait0.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* gpmc_wpn.uart4_txd */ >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) @@ -335,7 +335,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -354,7 +354,7 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) @@ -364,7 +364,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) /* Ethernet_nR >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) @@ -372,19 +372,19 @@ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ >; }; - emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { + emmc_pwrseq_pins: emmc-pwrseq-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a4.gpio1_20 */ >; }; - emmc_pins: pinmux_emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -399,20 +399,20 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc >; }; - ehrpwm1_pins: pinmux_ehrpwm1a_pins { + ehrpwm1_pins: ehrpwm1a-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6) /* gpmc_a2.ehrpwm1a */ AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.ehrpwm1b */ >; }; - rtc0_irq_pins: pinmux_rtc0_irq_pins { + rtc0_irq_pins: rtc0-irq-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_ad9.gpio0_23 */ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MOSI */ AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_MISO */ @@ -422,7 +422,7 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0) /* SPI0_CS1 (FP >; }; - lwb_pins: pinmux_lwb_pins { + lwb_pins: lwb-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index 6a103f17585b4..cb27ff464dbeb 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -49,7 +49,7 @@ vcc3v3: fixedregulator1 { /* Audio */ &am33xx_pinmux { - mcasp0_pins: pinmux-mcasp0 { + mcasp0_pins: pinmux-mcasp0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -90,7 +90,7 @@ &mcasp0 { /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux-dcan1 { + dcan1_pins: pinmux-dcan1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -106,7 +106,7 @@ &dcan1 { /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux-ethernet1 { + ethernet1_pins: pinmux-ethernet1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -146,7 +146,7 @@ &mac_sw { /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux-mmc1 { + mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -176,14 +176,14 @@ &vdig1_reg { /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux-uart0 { + uart0_pins: pinmux-uart0-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux-uart1 { + uart1_pins: pinmux-uart1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) -- GitLab From 7a75ed229f35267438eeae6ec42926307185c4ea Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:55:25 +0300 Subject: [PATCH 236/926] ARM: dts: Unify pinctrl-single pin group nodes for am4 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 14 ++--- arch/arm/boot/dts/am437x-gp-evm.dts | 78 ++++++++++++++-------------- arch/arm/boot/dts/am437x-idk-evm.dts | 32 ++++++------ arch/arm/boot/dts/am437x-sbc-t43.dts | 14 ++--- arch/arm/boot/dts/am437x-sk-evm.dts | 54 +++++++++---------- arch/arm/boot/dts/am43x-epos-evm.dts | 72 ++++++++++++------------- 6 files changed, 132 insertions(+), 132 deletions(-) diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 0861e868b75ab..9ec75d03eaff1 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -38,20 +38,20 @@ &am43xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&cm_t43_led_pins>; - cm_t43_led_pins: cm_t43_led_pins { + cm_t43_led_pins: cm-t43-led-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa78, MUX_MODE7) >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - emmc_pins: emmc_pins { + emmc_pins: emmc-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */ AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */ @@ -66,7 +66,7 @@ AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */ AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -75,7 +75,7 @@ AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8: nand-flash-x8-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0) AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0) @@ -95,7 +95,7 @@ AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ @@ -128,7 +128,7 @@ AM4372_IOPAD(0xa38, MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 46d5361fe8764..f7aad0323d191 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -153,45 +153,45 @@ &am43xx_pinmux { pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; pinctrl-1 = <&wlan_pins_sleep>; - ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + ddr3_vtt_toggle_default: ddr-vtt-toggle-default-pins { pinctrl-single,pins = < 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; - pixcir_ts_pins: pixcir_ts_pins { + pixcir_ts_pins: pixcir-ts-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ @@ -209,7 +209,7 @@ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -227,7 +227,7 @@ AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -235,7 +235,7 @@ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -243,7 +243,7 @@ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - nand_flash_x8: nand_flash_x8 { + nand_flash_x8: nand-flash-x8-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ @@ -263,7 +263,7 @@ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) @@ -297,42 +297,42 @@ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ >; }; - display_mux_pins: display_mux_pins { + display_mux_pins: display-mux-pins { pinctrl-single,pins = < /* GPIO 5_8 to select LCD / HDMI */ AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - dcan0_default: dcan0_default_pins { + dcan0_default: dcan0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ >; }; - dcan0_sleep: dcan0_sleep_pins { + dcan0_sleep: dcan0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ >; }; - dcan1_default: dcan1_default_pins { + dcan1_default: dcan1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ >; }; - dcan1_sleep: dcan1_sleep_pins { + dcan1_sleep: dcan1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ >; }; - vpfe0_pins_default: vpfe0_pins_default { + vpfe0_pins_default: vpfe0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ @@ -350,7 +350,7 @@ AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; - vpfe0_pins_sleep: vpfe0_pins_sleep { + vpfe0_pins_sleep: vpfe0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ @@ -368,7 +368,7 @@ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 m >; }; - vpfe1_pins_default: vpfe1_pins_default { + vpfe1_pins_default: vpfe1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ @@ -386,7 +386,7 @@ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ >; }; - vpfe1_pins_sleep: vpfe1_pins_sleep { + vpfe1_pins_sleep: vpfe1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ @@ -404,7 +404,7 @@ AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 m >; }; - mmc3_pins_default: pinmux_mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ @@ -415,7 +415,7 @@ AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ >; }; - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + mmc3_pins_sleep: mmc3-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ @@ -426,7 +426,7 @@ AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ >; }; - wlan_pins_default: pinmux_wlan_pins_default { + wlan_pins_default: wlan-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ @@ -434,7 +434,7 @@ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN* >; }; - wlan_pins_sleep: pinmux_wlan_pins_sleep { + wlan_pins_sleep: wlan-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ @@ -442,7 +442,7 @@ AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ >; }; - uart3_pins: uart3_pins { + uart3_pins: uart3-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ @@ -451,7 +451,7 @@ AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ @@ -460,7 +460,7 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 >; }; - mcasp1_sleep_pins: mcasp1_sleep_pins { + mcasp1_sleep_pins: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -469,13 +469,13 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - gpio0_pins: gpio0_pins { + gpio0_pins: gpio0-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ >; }; - emmc_pins_default: emmc_pins_default { + emmc_pins_default: emmc-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ @@ -490,7 +490,7 @@ AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ >; }; - emmc_pins_sleep: emmc_pins_sleep { + emmc_pins_sleep: emmc-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ @@ -505,19 +505,19 @@ AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ >; }; - beeper_pins_default: beeper_pins_default { + beeper_pins_default: beeper-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; - beeper_pins_sleep: beeper_pins_sleep { + beeper_pins_sleep: beeper-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; - unused_pins: unused_pins { + unused_pins: unused-pins { pinctrl-single,pins = < AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -566,7 +566,7 @@ AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - debugss_pins: pinmux_debugss_pins { + debugss_pins: debugss-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) @@ -578,7 +578,7 @@ AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ @@ -587,7 +587,7 @@ AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_ >; }; - uart0_pins_sleep: uart0_pins_sleep { + uart0_pins_sleep: uart0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ @@ -596,7 +596,7 @@ AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | M >; }; - matrix_keypad_default: matrix_keypad_default { + matrix_keypad_default: matrix-keypad-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) @@ -605,7 +605,7 @@ AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - matrix_keypad_sleep: matrix_keypad_sleep { + matrix_keypad_sleep: matrix-keypad-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index e46cf2a9d075c..863552393c07a 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -171,41 +171,41 @@ led-out7 { }; &am43xx_pinmux { - gpio_keys_pins_default: gpio_keys_pins_default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */ >; }; - i2c0_pins_default: i2c0_pins_default { + i2c0_pins_default: i2c0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c0_pins_sleep: i2c0_pins_sleep { + i2c0_pins_sleep: i2c0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - i2c2_pins_default: i2c2_pins_default { + i2c2_pins_default: i2c2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */ AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */ >; }; - i2c2_pins_sleep: i2c2_pins_sleep { + i2c2_pins_sleep: i2c2-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ @@ -217,7 +217,7 @@ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -229,7 +229,7 @@ AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - spi1_pins_default: spi1_pins_default { + spi1_pins_default: spi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ AM4372_IOPAD(0x910, PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ @@ -238,7 +238,7 @@ AM4372_IOPAD(0x90c, PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ >; }; - spi1_pins_sleep: spi1_pins_sleep { + spi1_pins_sleep: spi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -247,13 +247,13 @@ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - ecap0_pins_default: backlight_pins_default { + ecap0_pins_default: backlight-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ @@ -270,7 +270,7 @@ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -287,7 +287,7 @@ AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -295,7 +295,7 @@ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -303,7 +303,7 @@ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - qspi_pins_default: qspi_pins_default { + qspi_pins_default: qspi-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ @@ -314,7 +314,7 @@ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ >; }; - qspi_pins_sleep: qspi_pins_sleep{ + qspi_pins_sleep: qspi-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts index 8ea3780f939de..34a5407bee151 100644 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/am437x-sbc-t43.dts @@ -16,7 +16,7 @@ aliases { }; &am43xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ @@ -29,7 +29,7 @@ AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ >; }; - dss_pinctrl_default: dss_pinctrl_default { + dss_pinctrl_default: dss-pinctrl-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */ AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2) @@ -64,7 +64,7 @@ AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) @@ -73,27 +73,27 @@ AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */ AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */ >; }; - i2c2_pins: i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; - usb2_phy1_default: usb2_phy1_default { + usb2_phy1_default: usb2-phy1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy2_default: usb2_phy2_default { + usb2_phy2_default: usb2-phy2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0) >; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 511a02e13e2c9..9c97006ffd5b0 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -159,7 +159,7 @@ vmmcwl_fixed: fixedregulator-mmcwl { }; &am43xx_pinmux { - matrix_keypad_pins: matrix_keypad_pins { + matrix_keypad_pins: matrix-keypad-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ @@ -168,7 +168,7 @@ AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ >; }; - leds_pins: leds_pins { + leds_pins: leds-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ @@ -177,21 +177,21 @@ AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ >; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - i2c1_pins: i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ @@ -203,20 +203,20 @@ AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - ecap0_pins: backlight_pins { + ecap0_pins: backlight-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ >; }; - edt_ft5306_ts_pins: edt_ft5306_ts_pins { + edt_ft5306_ts_pins: edt-ft5306-ts-pins { pinctrl-single,pins = < AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ >; }; - vpfe0_pins_default: vpfe0_pins_default { + vpfe0_pins_default: vpfe0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ @@ -236,7 +236,7 @@ AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ >; }; - vpfe0_pins_sleep: vpfe0_pins_sleep { + vpfe0_pins_sleep: vpfe0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -256,13 +256,13 @@ AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; - clkout1_pin: pinmux_clkout1_pin { + clkout1_pin: clkout1-pins { pinctrl-single,pins = < 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ @@ -294,7 +294,7 @@ AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -326,7 +326,7 @@ AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -334,7 +334,7 @@ AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -342,7 +342,7 @@ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) @@ -376,7 +376,7 @@ AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ >; }; - qspi_pins: qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ @@ -387,7 +387,7 @@ AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ @@ -396,7 +396,7 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 >; }; - mcasp1_pins_sleep: mcasp1_pins_sleep { + mcasp1_pins_sleep: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -405,25 +405,25 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - lcd_pins: lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,pins = < AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ >; }; - usb1_pins: usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; - usb2_pins: usb2_pins { + usb2_pins: usb2-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; - mmc3_pins_default: pinmux_mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ @@ -434,7 +434,7 @@ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 >; }; - mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + mmc3_pins_sleep: mmc3-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ @@ -445,21 +445,21 @@ AM4372_IOPAD(0xa04, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_da >; }; - wlan_pins_default: pinmux_wlan_pins_default { + wlan_pins_default: wlan-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; - wlan_pins_sleep: pinmux_wlan_pins_sleep { + wlan_pins_sleep: wlan-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9d0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ AM4372_IOPAD(0x9e4, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ >; }; - uart1_bt_pins_default: pinmux_uart1_bt_pins_default { + uart1_bt_pins_default: uart1-bt-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ @@ -469,7 +469,7 @@ AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN >; }; - uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { + uart1_bt_pins_sleep: uart1-bt-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x980, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ AM4372_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 9fc915a2582e2..9193a4cfba78a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -141,7 +141,7 @@ &am43xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&unused_pins>; - unused_pins: unused_pins { + unused_pins: unused-pins { pinctrl-single,pins = < AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -175,7 +175,7 @@ AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - cpsw_default: cpsw_default { + cpsw_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave 1 */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ @@ -190,7 +190,7 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk >; }; - cpsw_sleep: cpsw_sleep { + cpsw_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 reset value */ AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -205,7 +205,7 @@ AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - davinci_mdio_default: davinci_mdio_default { + davinci_mdio_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ @@ -213,7 +213,7 @@ AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; - davinci_mdio_sleep: davinci_mdio_sleep { + davinci_mdio_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < /* MDIO reset value */ AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) @@ -221,14 +221,14 @@ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; - nand_flash_x8_default: nand_flash_x8_default { + nand_flash_x8_default: nand-flash-x8-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ @@ -249,7 +249,7 @@ AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ >; }; - nand_flash_x8_sleep: nand_flash_x8_sleep { + nand_flash_x8_sleep: nand-flash-x8-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) @@ -270,26 +270,26 @@ AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - ecap0_pins_default: backlight_pins_default { + ecap0_pins_default: backlight-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; - ecap0_pins_sleep: backlight_pins_sleep { + ecap0_pins_sleep: backlight-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - i2c2_pins: pinmux_i2c2_pins { + i2c2_pins: i2c2-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ >; }; - spi0_pins_default: pinmux_spi0_pins_default { + spi0_pins_default: spi0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ @@ -298,7 +298,7 @@ AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ >; }; - spi0_pins_sleep: pinmux_spi0_pins_sleep { + spi0_pins_sleep: spi0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -307,7 +307,7 @@ AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - spi1_pins_default: pinmux_spi1_pins_default { + spi1_pins_default: spi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ @@ -316,7 +316,7 @@ AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 * >; }; - spi1_pins_sleep: pinmux_spi1_pins_sleep { + spi1_pins_sleep: spi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) @@ -325,19 +325,19 @@ AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) >; }; - mmc1_pins_default: pinmux_mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; - mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + mmc1_pins_sleep: mmc1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) >; }; - matrix_keypad_default: matrix_keypad_default { + matrix_keypad_default: matrix-keypad-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ @@ -350,7 +350,7 @@ AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ >; }; - matrix_keypad_sleep: matrix_keypad_sleep { + matrix_keypad_sleep: matrix-keypad-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) @@ -363,7 +363,7 @@ AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - qspi1_pins_default: qspi1_pins_default { + qspi1_pins_default: qspi1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) @@ -374,7 +374,7 @@ AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) >; }; - qspi1_pins_sleep: qspi1_pins_sleep { + qspi1_pins_sleep: qspi1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) @@ -385,25 +385,25 @@ AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - pixcir_ts_pins_default: pixcir_ts_pins_default { + pixcir_ts_pins_default: pixcir-ts-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; - pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { + pixcir_ts_pins_sleep: pixcir-ts-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ >; }; - hdq_pins: pinmux_hdq_pins { + hdq_pins: hdq-pins { pinctrl-single,pins = < AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ >; }; - dss_pins: dss_pins { + dss_pins: dss-pins { pinctrl-single,pins = < AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) @@ -436,14 +436,14 @@ AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ >; }; - display_mux_pins: display_mux_pins { + display_mux_pins: display-mux-pins { pinctrl-single,pins = < /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; - vpfe1_pins_default: vpfe1_pins_default { + vpfe1_pins_default: vpfe1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ @@ -461,7 +461,7 @@ AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ >; }; - vpfe1_pins_sleep: vpfe1_pins_sleep { + vpfe1_pins_sleep: vpfe1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -479,7 +479,7 @@ AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; - uart0_pins_default: uart0_pins_default { + uart0_pins_default: uart0-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ @@ -488,7 +488,7 @@ AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) >; }; - uart0_pins_sleep: uart0_pins_sleep { + uart0_pins_sleep: uart0-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) @@ -497,31 +497,31 @@ AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) >; }; - usb2_phy1_default: usb2_phy1_default { + usb2_phy1_default: usb2-phy1-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy1_sleep: usb2_phy1_sleep { + usb2_phy1_sleep: usb2-phy1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - usb2_phy2_default: usb2_phy2_default { + usb2_phy2_default: usb2-phy2-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) >; }; - usb2_phy2_sleep: usb2_phy2_sleep { + usb2_phy2_sleep: usb2-phy2-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; - mcasp1_pins: mcasp1_pins { + mcasp1_pins: mcasp1-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ @@ -530,7 +530,7 @@ AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 >; }; - mcasp1_sleep_pins: mcasp1_sleep_pins { + mcasp1_sleep_pins: mcasp1-sleep-pins { pinctrl-single,pins = < AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) -- GitLab From 5cb957a188c7c71f6fdae6bc5a730eb7cbb676ca Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 12:54:43 +0300 Subject: [PATCH 237/926] ARM: dts: Unify pinctrl-single pin group nodes for dra7 We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 28 +++++++-------- arch/arm/boot/dts/am57xx-idk-common.dtsi | 4 +-- arch/arm/boot/dts/am57xx-sbc-am57x.dts | 14 ++++---- arch/arm/boot/dts/dra7-evm.dts | 4 +-- arch/arm/boot/dts/dra7-mmc-iodelay.dtsi | 2 +- arch/arm/boot/dts/dra72-evm-common.dtsi | 4 +-- arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi | 28 +++++++-------- arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi | 44 +++++++++++------------ arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 16 ++++----- 9 files changed, 72 insertions(+), 72 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 2fc9a5d5e0c0d..4774aa05f101e 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -77,40 +77,40 @@ simple-audio-card,codec { }; &dra7_pmx_core { - leds_pins_default: leds_pins_default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */ >; }; - i2c1_pins_default: i2c1_pins_default { + i2c1_pins_default: i2c1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ >; }; - i2c3_pins_default: i2c3_pins_default { + i2c3_pins_default: i2c3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ >; }; - i2c4_pins_default: i2c4_pins_default { + i2c4_pins_default: i2c4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */ DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */ >; }; - tps659038_pins_default: tps659038_pins_default { + tps659038_pins_default: tps659038-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -125,7 +125,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - qspi1_pins: pinmux_qspi1_pins { + qspi1_pins: qspi1-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */ @@ -136,7 +136,7 @@ DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ >; }; - cpsw_pins_default: cpsw_pins_default { + cpsw_pins_default: cpsw-default-pins { pinctrl-single,pins = < /* Slave at addr 0x0 */ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */ @@ -168,7 +168,7 @@ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd >; }; - cpsw_pins_sleep: cpsw_pins_sleep { + cpsw_pins_sleep: cpsw-sleep-pins { pinctrl-single,pins = < /* Slave 1 */ DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) @@ -200,7 +200,7 @@ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) >; }; - davinci_mdio_pins_default: davinci_mdio_pins_default { + davinci_mdio_pins_default: davinci-mdio-default-pins { pinctrl-single,pins = < /* MDIO */ DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */ @@ -208,20 +208,20 @@ DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */ >; }; - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { + davinci_mdio_pins_sleep: davinci-mdio-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15) DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15) >; }; - ads7846_pins: pinmux_ads7846_pins { + ads7846_pins: ads7846-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */ >; }; - mcasp3_pins_default: mcasp3_pins_default { + mcasp3_pins_default: mcasp3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ @@ -230,7 +230,7 @@ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_ >; }; - mcasp3_pins_sleep: mcasp3_pins_sleep { + mcasp3_pins_sleep: mcasp3-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 7f092a8811e88..43e3623f079c8 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -158,14 +158,14 @@ src_clk_x1: src_clk_x1 { }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x37d4, PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts index beef63e8a0057..363115afb0a45 100644 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts @@ -20,14 +20,14 @@ aliases { }; &dra7_pmx_core { - uart3_pins_default: uart3_pins_default { + uart3_pins_default: uart3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -40,33 +40,33 @@ DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */ >; }; - usb1_pins: pinmux_usb1_pins { + usb1_pins: usb1-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ >; }; - i2c5_pins_default: i2c5_pins_default { + i2c5_pins_default: i2c5-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ >; }; - lcd_pins_default: lcd_pins_default { + lcd_pins_default: lcd-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */ >; }; - hdmi_pins: pinmux_hdmi_pins { + hdmi_pins: hdmi-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ >; }; - hdmi_conn_pins: pinmux_hdmi_conn_pins { + hdmi_conn_pins: hdmi-conn-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */ >; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 8cbcf55a5a339..46efbaa67a8e2 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -152,14 +152,14 @@ vtt_fixed: fixedregulator-vtt { }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ diff --git a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi index aa09472665269..cb1a682c26cda 100644 --- a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi @@ -6,7 +6,7 @@ */ &dra7_pmx_core { - mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { + mmc1_pins_default_no_clk_pu: mmc1-default-no-clk-pu-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index c79ba671ec2b9..31ab0c60ca75e 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -197,14 +197,14 @@ clk_ov5640_fixed: clock { }; &dra7_pmx_core { - dcan1_pins_default: dcan1_pins_default { + dcan1_pins_default: dcan1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + dcan1_pins_sleep: dcan1-sleep-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi index 34eea3c048bdf..d006f1dfdeb57 100644 --- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi @@ -32,7 +32,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -43,7 +43,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_sdr12: mmc1_pins_sdr12 { + mmc1_pins_sdr12: mmc1-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -54,7 +54,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -65,7 +65,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_sdr25: mmc1_pins_sdr25 { + mmc1_pins_sdr25: mmc1-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -76,7 +76,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -87,7 +87,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* >; }; - mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { + mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ @@ -98,7 +98,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* >; }; - mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { + mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -109,7 +109,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_da >; }; - mmc1_pins_sdr104: mmc1_pins_sdr104 { + mmc1_pins_sdr104: mmc1-sdr104-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -120,7 +120,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_da >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -135,7 +135,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_hs: mmc2_pins_hs { + mmc2_pins_hs: mmc2-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -150,7 +150,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { + mmc2_pins_ddr_rev10: mmc2-ddr-rev10-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ @@ -165,7 +165,7 @@ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ >; }; - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -180,7 +180,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -195,7 +195,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc4_pins_default: mmc4_pins_default { + mmc4_pins_default: mmc4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi index b9d040135c5fa..e2fdb0702f5c9 100644 --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi @@ -30,7 +30,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -41,7 +41,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_sdr12: mmc1_pins_sdr12 { + mmc1_pins_sdr12: mmc1-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -52,7 +52,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -63,7 +63,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* >; }; - mmc1_pins_sdr25: mmc1_pins_sdr25 { + mmc1_pins_sdr25: mmc1-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -74,7 +74,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -85,7 +85,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* >; }; - mmc1_pins_ddr50: mmc1_pins_ddr50 { + mmc1_pins_ddr50: mmc1-ddr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -96,7 +96,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_da >; }; - mmc1_pins_sdr104: mmc1_pins_sdr104 { + mmc1_pins_sdr104: mmc1-sdr104-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -107,7 +107,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_da >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -122,7 +122,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_hs: mmc2_pins_hs { + mmc2_pins_hs: mmc2-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -137,7 +137,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 { + mmc2_pins_ddr_3_3v_rev11: mmc2-ddr-3-3v-rev11-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -152,7 +152,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 { + mmc2_pins_ddr_1_8v_rev11: mmc2-ddr-1-8v-rev11-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -167,7 +167,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { + mmc2_pins_ddr_rev20: mmc2-ddr-rev20-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -182,7 +182,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -197,7 +197,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc4_pins_default: mmc4_pins_default { + mmc4_pins_default: mmc4-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -208,7 +208,7 @@ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_r >; }; - mmc4_pins_hs: mmc4_pins_hs { + mmc4_pins_hs: mmc4-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -219,7 +219,7 @@ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_r >; }; - mmc3_pins_default: mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -230,7 +230,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc3_pins_hs: mmc3_pins_hs { + mmc3_pins_hs: mmc3-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -241,7 +241,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc3_pins_sdr12: mmc3_pins_sdr12 { + mmc3_pins_sdr12: mmc3-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -252,7 +252,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc3_pins_sdr25: mmc3_pins_sdr25 { + mmc3_pins_sdr25: mmc3-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -263,7 +263,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc3_pins_sdr50: mmc3_pins_sdr50 { + mmc3_pins_sdr50: mmc3-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -274,7 +274,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc4_pins_sdr12: mmc4_pins_sdr12 { + mmc4_pins_sdr12: mmc4-sdr12-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ @@ -285,7 +285,7 @@ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_r >; }; - mmc4_pins_sdr25: mmc4_pins_sdr25 { + mmc4_pins_sdr25: mmc4-sdr25-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi index fdca481869160..4690554dfa6e2 100644 --- a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi +++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi @@ -27,7 +27,7 @@ */ &dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { + mmc1_pins_default: mmc1-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -38,7 +38,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mmc1_pins_hs: mmc1_pins_hs { + mmc1_pins_hs: mmc1-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -49,7 +49,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* >; }; - mmc1_pins_sdr50: mmc1_pins_sdr50 { + mmc1_pins_sdr50: mmc1-sdr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -60,7 +60,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* >; }; - mmc1_pins_ddr50: mmc1_pins_ddr50 { + mmc1_pins_ddr50: mmc1-ddr50-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ @@ -71,7 +71,7 @@ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_da >; }; - mmc2_pins_default: mmc2_pins_default { + mmc2_pins_default: mmc2-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -86,7 +86,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - mmc2_pins_hs200: mmc2_pins_hs200 { + mmc2_pins_hs200: mmc2-hs200-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ @@ -101,7 +101,7 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a2 >; }; - mmc3_pins_default: mmc3_pins_default { + mmc3_pins_default: mmc3-default-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ @@ -112,7 +112,7 @@ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_ >; }; - mmc4_pins_hs: mmc4_pins_hs { + mmc4_pins_hs: mmc4-hs-pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ -- GitLab From d831312557e7308cdb59da5b3a228175e8d7738d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 May 2023 09:15:45 +0200 Subject: [PATCH 238/926] arm64: dts: qcom: sm8350: add ports subnodes in usb1 qmpphy node Add the USB3+DP Combo QMP PHY port subnodes in the SM8350 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-1-6c43d293995f@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ebcb481571c28..c057e320c1d0a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2149,6 +2149,32 @@ usb_1_qmpphy: phy@88e9000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_2_qmpphy: phy-wrapper@88eb000 { -- GitLab From e5167da381a71eeeac13d8ec299ac7c597622b23 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 May 2023 09:15:46 +0200 Subject: [PATCH 239/926] arm64: dts: qcom: sm8450: add ports subnodes in usb1 qmpphy node Add the USB3+DP Combo QMP PHY port subnodes in the SM8450 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-2-6c43d293995f@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 595533aeafc40..6de3327d9b32a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2044,6 +2044,32 @@ usb_1_qmpphy: phy@88e8000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; remoteproc_slpi: remoteproc@2400000 { -- GitLab From a3e42da4f712ca7fb3c9b1543f11ad82100e9914 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 May 2023 09:15:47 +0200 Subject: [PATCH 240/926] arm64: dts: qcom: sm8350-hdk: Add QMP & DP to SuperSpeed graph With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-3-6c43d293995f@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 76 ++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 2ee1b121686ae..d3788bd72ac33 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -58,7 +58,15 @@ port@1 { reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -326,6 +334,37 @@ zap-shader { }; }; +&i2c13 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + &i2c15 { clock-frequency = <400000>; status = "okay"; @@ -370,6 +409,21 @@ &mdss { status = "okay"; }; +&mdss_dp { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; +}; + &mdss_mdp { status = "okay"; }; @@ -416,6 +470,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &qupv3_id_2 { status = "okay"; }; @@ -716,7 +774,7 @@ &usb_1_dwc3_hs { }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -732,6 +790,20 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p88>; + + orientation-switch; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; }; &usb_2 { -- GitLab From b002bac7b4847aa11a6a56d14b2d75d4118f9591 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 May 2023 09:15:48 +0200 Subject: [PATCH 241/926] arm64: dts: qcom: sm8450-hdk: Add QMP & DP to SuperSpeed graph With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-4-6c43d293995f@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 73 ++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index e931545a2cac4..d5aeb7319776d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -114,9 +114,18 @@ port@1 { reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_1_qmpphy_out>; }; }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; }; }; @@ -494,6 +503,37 @@ lt9611_out: endpoint { }; }; +&i2c5 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + &mdss { status = "okay"; }; @@ -513,6 +553,21 @@ &mdss_dsi0_phy { status = "okay"; }; +&mdss_dp0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; +}; + &mdss_mdp { status = "okay"; }; @@ -766,7 +821,7 @@ &usb_1_dwc3_hs { }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -782,6 +837,20 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; + + orientation-switch; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; }; &vamacro { -- GitLab From b8ae83eb0c9648a3f9c386cfb191e31139050143 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 15:30:10 +0200 Subject: [PATCH 242/926] arm64: dts: qcom: sm8550-qrd: add PCIe0 Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, thus skip pcie_1_phy_aux_clk input clock to GCC. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516133011.108093-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index d5a645ee2a619..88f27a632a4dd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -359,6 +359,38 @@ vreg_l3g_1p2: ldo3 { }; }; +&gcc { + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; +}; + +&pcie_1_phy_aux_clk { + status = "disabled"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; -- GitLab From d97a6332c5841df4fb03aef996a7139465d68ca8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 15:30:11 +0200 Subject: [PATCH 243/926] arm64: dts: qcom: sm8550-qrd: add USB OTG Add missing parts of USB stack to enable USB OTG mode. The QRD8550 comes with one USB Type-C port. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516133011.108093-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 52 ++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 88f27a632a4dd..82cda2f9fea4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -27,6 +27,40 @@ chosen { stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -391,6 +425,11 @@ &pcie0_phy { status = "okay"; }; +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -449,13 +488,24 @@ &usb_1 { }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&pm8550b_eusb2_repeater>; + status = "okay"; }; -- GitLab From e130889286881e561a2904c5da44c3cbf5d5cd79 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:12 +0200 Subject: [PATCH 244/926] arm64: dts: qcom: qrb4210-rb2: Describe fixed regulators The board hosts a whole lot of fixed regulators. Describe them. Signed-off-by: Konrad Dybcio Reviewed-and-Tested-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-1-a52d154a639d@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 77 +++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index dc80f0bca7676..0fc99d38360c7 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -19,11 +19,86 @@ chosen { stdout-path = "serial0:115200n8"; }; - vph_pwr: vph-pwr-regulator { + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { + compatible = "regulator-fixed"; + regulator-name = "VREG_HDMI_OUT_1P2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_1v2>; + regulator-always-on; + regulator-boot-on; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + /* Main barrel jack input */ + vdc_12v: regulator-vdc-12v { + compatible = "regulator-fixed"; + regulator-name = "DC_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* 1.2V supply stepped down from the barrel jack input */ + vdc_1v2: regulator-vdc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "VDC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 3.3V supply stepped down from the barrel jack input */ + vdc_3v3: regulator-vdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 5V supply stepped down from the barrel jack input */ + vdc_5v: regulator-vdc-5v { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ + vdc_vbat_som: regulator-vdc-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* PMI632 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; + vin-supply = <&vdc_vbat_som>; regulator-always-on; regulator-boot-on; -- GitLab From f7b01e07e89ced85975345b12cb63538ee07e91c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:13 +0200 Subject: [PATCH 245/926] arm64: dts: qcom: qrb4210-rb2: Enable display out The RB2 has a HDMI output via an LT9611UXC bridge. Set it up. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov Reviewed-and-Tested-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-2-a52d154a639d@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 88 +++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 0fc99d38360c7..fc0e05c61b6ac 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -19,6 +19,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { compatible = "regulator-fixed"; regulator-name = "VREG_HDMI_OUT_1P2"; @@ -105,6 +116,68 @@ vph_pwr: regulator-vph-pwr { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_hdmi_out_1p2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l18a_1p232>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -287,10 +360,23 @@ &sleep_clk { }; &tlmm { - gpio-reserved-ranges = <37 5>, <43 2>, <47 1>, + gpio-reserved-ranges = <43 2>, <47 1>, <49 1>, <52 1>, <54 1>, <56 3>, <61 2>, <64 1>, <68 1>, <72 8>, <96 1>; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; + input-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio46"; + function = "gpio"; + bias-disable; + }; }; &uart4 { -- GitLab From fd888ed763415c31cf0ea7f044bd6cf429832f0e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:14 +0200 Subject: [PATCH 246/926] arm64: dts: qcom: qrb4210-rb2: Add GPIO LEDs Add the three LEDs (blue/yellow/green) connected to TLMM GPIOs. Signed-off-by: Konrad Dybcio Reviewed-and-Tested-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-3-a52d154a639d@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 36 ++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index fc0e05c61b6ac..42f16939457f9 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm4250.dtsi" / { @@ -30,6 +31,38 @@ hdmi_con: endpoint { }; }; + leds { + compatible = "gpio-leds"; + + led-bt { + label = "blue:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-user0 { + label = "green:user0"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led-wlan { + label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { compatible = "regulator-fixed"; regulator-name = "VREG_HDMI_OUT_1P2"; @@ -360,8 +393,7 @@ &sleep_clk { }; &tlmm { - gpio-reserved-ranges = <43 2>, <47 1>, - <49 1>, <52 1>, <54 1>, + gpio-reserved-ranges = <43 2>, <49 1>, <54 1>, <56 3>, <61 2>, <64 1>, <68 1>, <72 8>, <96 1>; -- GitLab From 42be4edd8910a5f998a5bd993f42ea7112dd8f80 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:15 +0200 Subject: [PATCH 247/926] arm64: dts: qcom: qrb4210-rb2: Enable load setting on SDHCI VQMMC The MMC core calls regulator_set_load on VQMMC, enable loadsetting to make it effective. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Konrad Dybcio Reviewed-and-Tested-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-4-a52d154a639d@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 42f16939457f9..38297dd259395 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -267,6 +267,7 @@ vreg_l4a_0p9: l4 { vreg_l5a_2p96: l5 { regulator-min-microvolt = <1648000>; regulator-max-microvolt = <3056000>; + regulator-allow-set-load; }; vreg_l6a_0p6: l6 { @@ -297,6 +298,7 @@ vreg_l10a_1p8: l10 { vreg_l11a_1p8: l11 { regulator-min-microvolt = <1704000>; regulator-max-microvolt = <1952000>; + regulator-allow-set-load; }; vreg_l12a_1p8: l12 { -- GitLab From 34a7cdf075410c30ca88c85627520dda74d3bd30 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 15 May 2023 15:04:16 +0200 Subject: [PATCH 248/926] arm64: dts: qcom: qrb4210-rb2: Enable CAN bus controller Enable the Microchip mcp2518fd hosted on the SPI5 bus. Signed-off-by: Konrad Dybcio Reviewed-and-Tested-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-5-a52d154a639d@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 38297dd259395..e8302b00d359d 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -20,6 +20,14 @@ chosen { stdout-path = "serial0:115200n8"; }; + clocks { + clk40M: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -390,6 +398,20 @@ &sdhc_2 { status = "okay"; }; +&spi5 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk40M>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; +}; + &sleep_clk { clock-frequency = <32000>; }; -- GitLab From 10254fb73fdadec81e47a776e149863a13030291 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 16 May 2023 13:29:06 +0530 Subject: [PATCH 249/926] arm64: dts: qcom: qrb4210-rb2: Add SD pinctrl states Add the default and sleep pinctrl states for SDHC1 & 2 controllers on QRB4210 RB2 board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516075908.2323372-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index e8302b00d359d..db7813ff211a6 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -381,6 +381,10 @@ vreg_l24a_2p96: l24 { }; &sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l24a_2p96>; vqmmc-supply = <&vreg_l11a_1p8>; no-sdio; @@ -391,6 +395,11 @@ &sdhc_1 { &sdhc_2 { cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; /* card detect gpio */ + + pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l22a_2p96>; vqmmc-supply = <&vreg_l5a_2p96>; no-sdio; @@ -433,6 +442,13 @@ lt9611_irq_pin: lt9611-irq-state { function = "gpio"; bias-disable; }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart4 { -- GitLab From 14e6c47b628788a8c8634bc59b2dd50d68a74de3 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 16 May 2023 13:29:07 +0530 Subject: [PATCH 250/926] arm64: dts: qcom: qrb4210-rb2: Fix CD gpio for SDHC2 Card-Detect (CD) gpio for SDHC2 is an active GPIO line. Fix the same. This allows the uSD card to be properly detected on the board. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516075908.2323372-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index db7813ff211a6..561ed01380e4b 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -394,7 +394,7 @@ &sdhc_1 { }; &sdhc_2 { - cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; /* card detect gpio */ + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; /* card detect gpio */ pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>; -- GitLab From 50931b44dc751784cdc5721bf30a79093c2c9fe9 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 16 May 2023 13:29:08 +0530 Subject: [PATCH 251/926] arm64: dts: qcom: qrb4210-rb2: Enable aDSP and cDSP remoteproc nodes Enable the aDSP and cDSP remoteproc nodes on Qualcomm QRB4210 RB2 board. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516075908.2323372-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 561ed01380e4b..da3bc307c2f85 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -223,6 +223,18 @@ &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qrb4210/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qrb4210/cdsp.mbn"; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm6125-regulators"; -- GitLab From b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 15 May 2023 17:19:20 +0200 Subject: [PATCH 252/926] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. That syncs more Northstar code to be based on the same licensing schema. Signed-off-by: Rafał Miłecki Cc: Hauke Mehrtens Acked-by: Hauke Mehrtens Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 85 ------------------------------- 2 files changed, 90 insertions(+), 85 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index cc977bbc142b5..58c30e3a142f8 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2013-2014 Hauke Mehrtens + */ #include #include @@ -7,6 +10,81 @@ #include / { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + chipcommon-a-bus@18000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x18000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@300 { + compatible = "ns16550"; + reg = <0x0300 0x100>; + interrupts = ; + clocks = <&iprocslow>; + status = "disabled"; + }; + + uart1: serial@400 { + compatible = "ns16550"; + reg = <0x0400 0x100>; + interrupts = ; + clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; + status = "disabled"; + }; + }; + + mpcore-bus@19000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + + scu@20000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x20000 0x100>; + }; + + timer@20200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20200 0x100>; + interrupts = ; + clocks = <&periph_clk>; + }; + + timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20600 0x20>; + interrupts = ; + clocks = <&periph_clk>; + }; + + gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x21000 0x1000>, + <0x20100 0x100>; + }; + + L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; + reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; + prefetch-instr = <1>; + cache-level = <2>; + }; + }; + axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -216,6 +294,18 @@ thermal: thermal@2c0 { }; }; + nand_controller: nand-controller@18028000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index bc36edc245101..d6c31ead03987 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -11,41 +11,7 @@ #include "bcm-ns.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chipcommon-a-bus@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550"; - reg = <0x0300 0x100>; - interrupts = ; - clocks = <&iprocslow>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550"; - reg = <0x0400 0x100>; - interrupts = ; - clocks = <&iprocslow>; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_uart1>; - status = "disabled"; - }; - }; - mpcore-bus@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; @@ -53,26 +19,6 @@ a9pll: arm_clk@0 { reg = <0x00000 0x1000>; }; - scu@20000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x20000 0x100>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = ; - clocks = <&periph_clk>; - }; - - timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = ; - clocks = <&periph_clk>; - }; - watchdog@20620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0x20620 0x20>; @@ -80,25 +26,6 @@ watchdog@20620 { IRQ_TYPE_EDGE_RISING)>; clocks = <&periph_clk>; }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; - prefetch-instr = <1>; - cache-level = <2>; - }; }; pmu { @@ -301,18 +228,6 @@ genpll: clock-controller@140 { }; }; - nand_controller: nand-controller@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - spi@18029200 { compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; reg = <0x18029200 0x184>, -- GitLab From 3b3e35b279bee5e51580c648399e20323467f58c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 15 May 2023 17:19:21 +0200 Subject: [PATCH 253/926] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Those entries were added by: 1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ numbers for PCIe controller") 2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB interrupts") Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more Northstar code to be based on the same licensing schema. Signed-off-by: Rafał Miłecki Cc: Hauke Mehrtens Cc: Florian Fainelli Acked-by: Hauke Mehrtens Link: https://lore.kernel.org/r/20230515151921.25021-2-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 75 --------------------------------- 2 files changed, 73 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 58c30e3a142f8..3f8220a7a54dd 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -92,6 +92,79 @@ axi@18000000 { #address-cells = <1>; #size-cells = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + chipcommon: chipcommon@0 { reg = <0x00000000 0x1000>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d6c31ead03987..0f40812eb5a40 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -3,8 +3,6 @@ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs * - * Copyright 2013-2014 Hauke Mehrtens - * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -72,79 +70,6 @@ periph_clk: periph_clk { }; axi@18000000 { - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - - /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - - /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - pcie2: pcie@14000 { reg = <0x00014000 0x1000>; }; -- GitLab From 19571b46d8997d20c10b7194a3ee5772500ce725 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Mon, 8 May 2023 15:59:30 +0200 Subject: [PATCH 254/926] dt-bindings: soc: bcm: add missing dt-binding document for bcm23550-cdc Broadcom BCM23550 has a Cluster Dormant Control block that keeps the CPU in idle state. A command needs to be sent to this block to bring the CPU into running state. This has been in use in mainline Linux since ~2016, but was never documented. Add a dt-binding document for it. Signed-off-by: Stanislav Jakubek Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230508135930.GA27583@standask-GA-A55M-S2HP Signed-off-by: Florian Fainelli --- .../bindings/soc/bcm/brcm,bcm23550-cdc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml new file mode 100644 index 0000000000000..1a952f5698032 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm23550-cdc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm23550-cdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM23550 Cluster Dormant Control + +description: + The Cluster Dormant Control block keeps the CPU in idle state. A command + needs to be sent to this block to bring the CPU into running state. + +maintainers: + - Florian Fainelli + +properties: + compatible: + const: brcm,bcm23550-cdc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cdc@3fe0e000 { + compatible = "brcm,bcm23550-cdc"; + reg = <0x3fe0e000 0x78>; + }; +... -- GitLab From dfa6570eb5ce2f24059caadbe2ed70034b5337bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 15 May 2023 10:33:08 +0200 Subject: [PATCH 255/926] ARM: dts: BCM5301X: Specify MAC addresses on Luxul devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use NRAM (NVMEM device) and its "et0macaddr" variable (NVMEM cell) to point Ethernet devices to their MAC addresses. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230515083308.7612-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 11 +++++++++++ arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 11 +++++++++++ arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 11 +++++++++++ arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 11 +++++++++++ arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 5 ++++- 10 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 6de7fe204b0c0..9b98a0179f055 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -20,6 +20,14 @@ memory@0 { reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -53,6 +61,11 @@ button-restart { }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index f5b75ba935124..4ca348c06b51f 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -24,6 +24,14 @@ memory@0 { reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + nand_controller: nand-controller@18028000 { nand@0 { partitions { @@ -60,6 +68,11 @@ button-restart { }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 76c9b30b868d4..edc1940859957 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -20,6 +20,14 @@ memory@0 { reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -53,6 +61,11 @@ button-restart { }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 6ef0c0788e625..97b61d9d4be9e 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -24,6 +24,10 @@ memory@0 { nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -106,6 +110,11 @@ &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -137,6 +146,8 @@ port@3 { port@4 { reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index 41a0722fa64a6..ae55238708542 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -25,6 +25,10 @@ memory@0 { nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -61,6 +65,11 @@ &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -76,6 +85,8 @@ ports { port@0 { reg = <0>; label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@1 { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index c56c7e366848b..9220f193499e7 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -20,6 +20,14 @@ memory@0 { reg = <0x00000000 0x08000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -51,6 +59,11 @@ button-restart { }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 1b5c91a524ac9..2bd64dcd43535 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -25,6 +25,10 @@ memory@0 { nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -61,6 +65,11 @@ &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -76,6 +85,8 @@ ports { port@0 { reg = <0>; label = "wan"; + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@1 { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 739063b77b1f6..8a6d19f985c13 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -22,6 +22,14 @@ memory@0 { <0x88000000 0x18000000>; }; + nvram@1eff0000 { + compatible = "brcm,nvram"; + reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; + }; + leds { compatible = "gpio-leds"; @@ -47,6 +55,11 @@ &uart1 { status = "okay"; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index 7afc68d5d2c20..ebea188bd2d75 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -25,6 +25,10 @@ memory@0 { nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; leds { @@ -101,6 +105,11 @@ &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -136,6 +145,8 @@ port@3 { port@4 { reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 60a2c441d5bda..2dd05f4dce92a 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -27,6 +27,7 @@ nvram@1eff0000 { reg = <0x1eff0000 0x10000>; et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; }; }; @@ -76,7 +77,7 @@ button-restart { }; &gmac0 { - nvmem-cells = <&et0macaddr>; + nvmem-cells = <&et0macaddr 0>; nvmem-cell-names = "mac-address"; }; @@ -119,6 +120,8 @@ port@3 { port@4 { reg = <4>; label = "wan"; + nvmem-cells = <&et0macaddr 5>; + nvmem-cell-names = "mac-address"; }; port@5 { -- GitLab From 4ceb0c70d0dae0f1327c4cfda3826b98a885f735 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 22 May 2023 15:48:12 +0300 Subject: [PATCH 256/926] ARM: dts: at91: sama5d2: remove extra line Remove extra line from the definition of slow clock controller. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230522124812.107227-1-claudiu.beznea@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5f632e3f039e6..7b6471655deec 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -707,7 +707,6 @@ watchdog: watchdog@f8048040 { clk32k: clock-controller@f8048050 { compatible = "atmel,sama5d4-sckc"; reg = <0xf8048050 0x4>; - clocks = <&slow_xtal>; #clock-cells = <0>; }; -- GitLab From 8721e18ca6960f3c5a6a7f58245d9ab084ad09dd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 May 2023 19:04:30 +0300 Subject: [PATCH 257/926] arm64: dts: qcom: enable dual ("bonded") DSI mode for DB845c Now as both lt9611 and drm/msm drivers were updated to handle the 4k modes over DSI, enable "bonded" DSI mode on DB845c. This way the board utilizes both DSI links and thus can support 4k on the HDMI output. Cc: Amit Pundir Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230504160430.4014206-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index e14fe9bbb386a..4dea2c04b22fa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -419,6 +419,9 @@ &dsi0 { status = "okay"; vdda-supply = <&vreg_l26a_1p2>; + qcom,dual-dsi-mode; + qcom,master-dsi; + ports { port@1 { endpoint { @@ -434,6 +437,31 @@ &dsi0_phy { vdds-supply = <&vreg_l1a_0p875>; }; +&dsi1 { + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi1_phy { + vdds-supply = <&vreg_l1a_0p875>; + status = "okay"; +}; + &gcc { protected-clocks = , , @@ -493,6 +521,14 @@ lt9611_a: endpoint { }; }; + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + port@2 { reg = <2>; -- GitLab From 399a3c34b390afda183b7b0bd91afeee3a4cfc0f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 3 May 2023 16:13:28 +0200 Subject: [PATCH 258/926] arm64: dts: qcom: pmk8350: add reboot-mode node using sdam_2 nvmem Introduce sdam_2 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reasons supported via sdam_2 node. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-upstream-reboot-reason-v1-1-c5ac3dd5b49f@linaro.org --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index f26fb7d32faf2..bc6297e7253e2 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -13,6 +13,16 @@ #define PMK8350_SID 0 #endif +/ { + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; +}; + &spmi_bus { pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; @@ -66,6 +76,19 @@ pmk8350_rtc: rtc@6100 { status = "disabled"; }; + pmk8350_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + pmk8350_gpios: gpio@b000 { compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; reg = <0xb000>; -- GitLab From 138c427ade7bad3f4f764b506ce4f1079bfc22ee Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 3 May 2023 16:13:29 +0200 Subject: [PATCH 259/926] arm64: dts: qcom: pmk8550: add reboot-mode node using sdam_2 nvmem Introduce sdam_2 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reasons supported via sdam_2 node. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-upstream-reboot-reason-v1-2-c5ac3dd5b49f@linaro.org --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 201efeda7d2d9..8c897d4fee296 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -8,6 +8,16 @@ #include #include +/ { + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; +}; + &spmi_bus { pmk8550: pmic@0 { compatible = "qcom,pm8550", "qcom,spmi-pmic"; @@ -42,6 +52,19 @@ pmk8550_rtc: rtc@6100 { status = "disabled"; }; + pmk8550_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + pmk8550_gpios: gpio@8800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; -- GitLab From 9ee402ccfeb1638a039f2e0d455300b5f8600a81 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 2 May 2023 15:09:58 +0530 Subject: [PATCH 260/926] arm64: dts: qcom: sc7280: Fix EUD dt node syntax As noted by Konrad while reviewing [1], fix the EUD and DWC3 node syntax in sc7280 dtsi file. While at it also fix the errors reported by '$ make dtbs_check' for the EUD node: arch/arm64/boot/dts/qcom/sc7280-crd-r3.dtb: eud@88e0000: ports: 'oneOf' conditional failed, one must be fixed: 'port' is a required property '#address-cells' is a required property '#size-cells' is a required property From schema: Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml [1]. https://lore.kernel.org/linux-arm-msm/20221231131945.3286639-1-bhupesh.sharma@linaro.org Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230502093959.1258889-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 31728f4614223..e441b1d6cad37 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -640,6 +640,18 @@ cpu7_opp_3014mhz: opp-3014400000 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -3421,6 +3433,7 @@ usb_2_dwc3: usb@8c00000 { phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; + port { usb2_role_switch: endpoint { remote-endpoint = <&eud_ep>; @@ -3596,10 +3609,11 @@ system-cache-controller@9200000 { }; eud: eud@88e0000 { - compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x088e0000 0 0x2000>, - <0 0x088e2000 0 0x1000>; + compatible = "qcom,sc7280-eud", "qcom,eud"; + reg = <0 0x88e0000 0 0x2000>, + <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -3610,6 +3624,7 @@ eud_ep: endpoint { remote-endpoint = <&usb2_role_switch>; }; }; + port@1 { reg = <1>; eud_con: endpoint { @@ -3619,21 +3634,6 @@ eud_con: endpoint { }; }; - eud_typec: connector { - compatible = "usb-c-connector"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - con_eud: endpoint { - remote-endpoint = <&eud_con>; - }; - }; - }; - }; - nsp_noc: interconnect@a0c0000 { reg = <0 0x0a0c0000 0 0x10000>; compatible = "qcom,sc7280-nsp-noc"; -- GitLab From eee7369de0c3cca7aacab3874663d460fb7a5b06 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 16:24:43 -0500 Subject: [PATCH 261/926] arm64: dts: qcom: sa8155p-adp: Make compatible the first property As stated at the below link in another review, compatible is always the first property. Follow suit here to avoid copying incorrectly in the future. Link: https://lore.kernel.org/netdev/20230331215804.783439-1-ahalaney@redhat.com/T/#ma76b4116bbb9e49ee4bcf699e40935d80965b3f3 Reviewed-by: Konrad Dybcio Signed-off-by: Andrew Halaney Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501212446.2570364-2-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 339fea522509f..029b23198b3a2 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -352,19 +352,18 @@ ðernet { max-speed = <1000>; mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <0x1>; #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - /* Micrel KSZ9031RNZ PHY */ rgmii_phy: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x7>; interrupt-parent = <&tlmm>; interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ device_type = "ethernet-phy"; - compatible = "ethernet-phy-ieee802.3-c22"; }; }; }; -- GitLab From 674631c35f8670017d3bbd51a5b52f8b953f6816 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 16:24:44 -0500 Subject: [PATCH 262/926] arm64: dts: qcom: Make -cells decimal The property logically makes sense in decimal, and is the standard used elsewhere. Suggested-by: Konrad Dybcio Signed-off-by: Andrew Halaney Reviewed-by: Krzysztof Kozlowski Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501212446.2570364-3-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 4 ++-- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 4 ++-- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9ff4e9d45065b..ccaf8e57668aa 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -571,7 +571,7 @@ intc: interrupt-controller@b000000 { #address-cells = <2>; #size-cells = <2>; interrupt-controller; - #interrupt-cells = <0x3>; + #interrupt-cells = <3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 84e715aa43103..0bde1303bb9db 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -29,8 +29,8 @@ xo: xo { }; cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; @@ -106,8 +106,8 @@ scm { }; soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <1>; + #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; @@ -321,9 +321,9 @@ tlmm: pinctrl@1000000 { interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 70>; - #gpio-cells = <0x2>; + #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <0x2>; + #interrupt-cells = <2>; serial_4_pins: serial4-state { pins = "gpio23", "gpio24"; @@ -666,7 +666,7 @@ intc: interrupt-controller@b000000 { #address-cells = <1>; #size-cells = <1>; interrupt-controller; - #interrupt-cells = <0x3>; + #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; ranges = <0 0xb00a000 0xffd>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 602cb188a6354..eeebdab58c043 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1505,8 +1505,8 @@ apcs: mailbox@b011000 { timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; - #address-cells = <0x01>; - #size-cells = <0x01>; + #address-cells = <1>; + #size-cells = <1>; ranges; frame@b121000 { diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 59702ba24f351..358827c2fbd31 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -27,8 +27,8 @@ ðernet { phy-handle = <&phy1>; phy-mode = "rgmii"; mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy1: phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 029b23198b3a2..ac52a8dfeba10 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -353,8 +353,8 @@ ðernet { mdio { compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; /* Micrel KSZ9031RNZ PHY */ rgmii_phy: phy@7 { -- GitLab From 0ff4f6a380214fcf85a5b5ad64ff481d9bd1dfc6 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 16:24:45 -0500 Subject: [PATCH 263/926] arm64: dts: qcom: sa8155p-adp: Remove unneeded rgmii_phy information Using interrupts-extended already indicates what the interrupt-parent is, so drop the explicit interrupt-parent. The comment about this being the phy-intr is not helpful either, since this is the only interrupt in the phy node. Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Andrew Halaney Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501212446.2570364-4-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index ac52a8dfeba10..b65e0203d7838 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -361,8 +361,7 @@ rgmii_phy: phy@7 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x7>; - interrupt-parent = <&tlmm>; - interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ + interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; device_type = "ethernet-phy"; }; }; -- GitLab From 93fe463652504bba298a68b56334729cdf92c0c3 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Mon, 1 May 2023 16:24:46 -0500 Subject: [PATCH 264/926] arm64: dts: qcom: sa8155p-adp: Move mtl nodes into ethernet node The mtl nodes aren't evaluated unless they're under the node with the compatible. Move them so they're now evaluated in case future patchsets modify them incorrectly. An example of this can be seen in the link. Link: https://lore.kernel.org/linux-arm-msm/20230414145844.wyg6pt623pzqwh5l@halaney-x13s/ Signed-off-by: Andrew Halaney Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230501212446.2570364-5-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 46 ++++++++++++------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index b65e0203d7838..02d04ce877c9c 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -47,29 +47,6 @@ vreg_s4a_1p8: smps4 { vin-supply = <&vreg_3p3>; }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - snps,tx-sched-wrr; - - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - }; }; &apps_rsc { @@ -365,6 +342,29 @@ rgmii_phy: phy@7 { device_type = "ethernet-phy"; }; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; }; &qupv3_id_1 { -- GitLab From e0a6590d8ceb7d6c4e35b5b5eb368d9fb800487f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 27 Apr 2023 22:34:29 +0200 Subject: [PATCH 265/926] ARM: dts: qcom: msm8974-hammerhead: Add vibrator The Nexus 5 has a vibrator connected to the clock output of GP1_CLK which we can use with the clk-pwm driver, then we can use that pwm with pwm-vibrator to get haptics functionality. This patch is based on Brian Masney's previous patch with clk-vibrator. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Caleb Connolly Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230427-hammerhead-vibra-v1-4-e87eeb94da51@z3ntu.xyz --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index ab35f2d644c0e..fea8a6be9021d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -41,6 +41,25 @@ key-volume-down { }; }; + clk_pwm: pwm { + compatible = "clk-pwm"; + clocks = <&mmcc CAMSS_GP1_CLK>; + + pinctrl-0 = <&vibrator_pin>; + pinctrl-names = "default"; + + #pwm-cells = <2>; + }; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <&pm8941_l19>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + }; + vreg_wlan: wlan-regulator { compatible = "regulator-fixed"; @@ -637,6 +656,22 @@ shutdown-pins { function = "gpio"; }; }; + + vibrator_pin: vibrator-state { + core-pins { + pins = "gpio27"; + function = "gp1_clk"; + drive-strength = <6>; + bias-disable; + }; + + enable-pins { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &usb { -- GitLab From cb0c14dae63fae037db41174fc95a59dea0ecf77 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 26 Apr 2023 20:56:47 +0200 Subject: [PATCH 266/926] arm64: dts: qcom: ipq8074: Add QUP5 SPI node Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230426185647.180166-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 0bde1303bb9db..74ce93e9bd673 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -533,6 +533,20 @@ blsp1_i2c5: i2c@78b9000 { status = "disabled"; }; + blsp1_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; -- GitLab From 311bbc884b2edcf584b67d331be85ce43b27586f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Apr 2023 19:52:32 +0200 Subject: [PATCH 267/926] ARM: dts: qcom: msm8974: do not use underscore in node name (again) Align RPM requests node with DT schema by using hyphen instead of underscore. Fixes: f300826d27be ("ARM: dts: qcom-msm8974: Sort and clean up nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230410175232.22317-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8208012684d4a..38d3ee152dcb4 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -300,7 +300,7 @@ rpm { qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests: rpm_requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; -- GitLab From 1c305ea86bc32b3f38413ef3dbb1f3c288da024e Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:44 +0530 Subject: [PATCH 268/926] dt-bindings: clock: qcom: Add GCC clocks for SDX75 Add support for qcom global clock controller bindings for SDX75 platform. Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com --- .../bindings/clock/qcom,sdx75-gcc.yaml | 65 ++++++ include/dt-bindings/clock/qcom,sdx75-gcc.h | 193 ++++++++++++++++++ 2 files changed, 258 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sdx75-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml new file mode 100644 index 0000000000000..98921fa236b18 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX75 + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX75 + + See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + +properties: + compatible: + const: qcom,sdx75-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC0 sgmiiphy rclk source + - description: EMAC0 sgmiiphy tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy rclk source + - description: EMAC1 sgmiiphy tclk source + - description: PCIE20 phy aux clock source + - description: PCIE_1 Pipe clock source + - description: PCIE_2 Pipe clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x80000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sdx75-gcc.h b/include/dt-bindings/clock/qcom,sdx75-gcc.h new file mode 100644 index 0000000000000..a470e8c4fd413 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sdx75-gcc.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL5 3 +#define GPLL6 4 +#define GPLL8 5 +#define GCC_AHB_PCIE_LINK_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_EEE_EMAC0_CLK 8 +#define GCC_EEE_EMAC0_CLK_SRC 9 +#define GCC_EEE_EMAC1_CLK 10 +#define GCC_EEE_EMAC1_CLK_SRC 11 +#define GCC_EMAC0_AXI_CLK 12 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16 +#define GCC_EMAC0_PHY_AUX_CLK 17 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 18 +#define GCC_EMAC0_PTP_CLK 19 +#define GCC_EMAC0_PTP_CLK_SRC 20 +#define GCC_EMAC0_RGMII_CLK 21 +#define GCC_EMAC0_RGMII_CLK_SRC 22 +#define GCC_EMAC0_RPCS_RX_CLK 23 +#define GCC_EMAC0_RPCS_TX_CLK 24 +#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25 +#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26 +#define GCC_EMAC0_SLV_AHB_CLK 27 +#define GCC_EMAC0_XGXS_RX_CLK 28 +#define GCC_EMAC0_XGXS_TX_CLK 29 +#define GCC_EMAC1_AXI_CLK 30 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34 +#define GCC_EMAC1_PHY_AUX_CLK 35 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 36 +#define GCC_EMAC1_PTP_CLK 37 +#define GCC_EMAC1_PTP_CLK_SRC 38 +#define GCC_EMAC1_RGMII_CLK 39 +#define GCC_EMAC1_RGMII_CLK_SRC 40 +#define GCC_EMAC1_RPCS_RX_CLK 41 +#define GCC_EMAC1_RPCS_TX_CLK 42 +#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43 +#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44 +#define GCC_EMAC1_SLV_AHB_CLK 45 +#define GCC_EMAC1_XGXS_RX_CLK 46 +#define GCC_EMAC1_XGXS_TX_CLK 47 +#define GCC_EMAC_0_CLKREF_EN 48 +#define GCC_EMAC_1_CLKREF_EN 49 +#define GCC_GP1_CLK 50 +#define GCC_GP1_CLK_SRC 51 +#define GCC_GP2_CLK 52 +#define GCC_GP2_CLK_SRC 53 +#define GCC_GP3_CLK 54 +#define GCC_GP3_CLK_SRC 55 +#define GCC_PCIE_0_CLKREF_EN 56 +#define GCC_PCIE_1_AUX_CLK 57 +#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58 +#define GCC_PCIE_1_CFG_AHB_CLK 59 +#define GCC_PCIE_1_CLKREF_EN 60 +#define GCC_PCIE_1_MSTR_AXI_CLK 61 +#define GCC_PCIE_1_PHY_RCHNG_CLK 62 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_1_PIPE_CLK 64 +#define GCC_PCIE_1_PIPE_CLK_SRC 65 +#define GCC_PCIE_1_PIPE_DIV2_CLK 66 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67 +#define GCC_PCIE_1_SLV_AXI_CLK 68 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_2_AUX_CLK 70 +#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71 +#define GCC_PCIE_2_CFG_AHB_CLK 72 +#define GCC_PCIE_2_CLKREF_EN 73 +#define GCC_PCIE_2_MSTR_AXI_CLK 74 +#define GCC_PCIE_2_PHY_RCHNG_CLK 75 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76 +#define GCC_PCIE_2_PIPE_CLK 77 +#define GCC_PCIE_2_PIPE_CLK_SRC 78 +#define GCC_PCIE_2_PIPE_DIV2_CLK 79 +#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80 +#define GCC_PCIE_2_SLV_AXI_CLK 81 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82 +#define GCC_PCIE_AUX_CLK 83 +#define GCC_PCIE_AUX_CLK_SRC 84 +#define GCC_PCIE_AUX_PHY_CLK_SRC 85 +#define GCC_PCIE_CFG_AHB_CLK 86 +#define GCC_PCIE_MSTR_AXI_CLK 87 +#define GCC_PCIE_PIPE_CLK 88 +#define GCC_PCIE_PIPE_CLK_SRC 89 +#define GCC_PCIE_RCHNG_PHY_CLK 90 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91 +#define GCC_PCIE_SLEEP_CLK 92 +#define GCC_PCIE_SLV_AXI_CLK 93 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 94 +#define GCC_PDM2_CLK 95 +#define GCC_PDM2_CLK_SRC 96 +#define GCC_PDM_AHB_CLK 97 +#define GCC_PDM_XO4_CLK 98 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99 +#define GCC_QUPV3_WRAP0_CORE_CLK 100 +#define GCC_QUPV3_WRAP0_S0_CLK 101 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102 +#define GCC_QUPV3_WRAP0_S1_CLK 103 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104 +#define GCC_QUPV3_WRAP0_S2_CLK 105 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S3_CLK 107 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S4_CLK 109 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110 +#define GCC_QUPV3_WRAP0_S5_CLK 111 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S6_CLK 113 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S7_CLK 115 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S8_CLK 117 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120 +#define GCC_SDCC1_AHB_CLK 121 +#define GCC_SDCC1_APPS_CLK 122 +#define GCC_SDCC1_APPS_CLK_SRC 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_SDCC2_APPS_CLK_SRC 126 +#define GCC_USB2_CLKREF_EN 127 +#define GCC_USB30_MASTER_CLK 128 +#define GCC_USB30_MASTER_CLK_SRC 129 +#define GCC_USB30_MOCK_UTMI_CLK 130 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132 +#define GCC_USB30_MSTR_AXI_CLK 133 +#define GCC_USB30_SLEEP_CLK 134 +#define GCC_USB30_SLV_AHB_CLK 135 +#define GCC_USB3_PHY_AUX_CLK 136 +#define GCC_USB3_PHY_AUX_CLK_SRC 137 +#define GCC_USB3_PHY_PIPE_CLK 138 +#define GCC_USB3_PHY_PIPE_CLK_SRC 139 +#define GCC_USB3_PRIM_CLKREF_EN 140 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141 +#define GCC_XO_PCIE_LINK_CLK 142 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_EMAC1_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_PCIE_2_GDSC 4 +#define GCC_PCIE_2_PHY_GDSC 5 +#define GCC_PCIE_GDSC 6 +#define GCC_PCIE_PHY_GDSC 7 +#define GCC_USB30_GDSC 8 +#define GCC_USB3_PHY_GDSC 9 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_EMMC_BCR 2 +#define GCC_PCIE_1_BCR 3 +#define GCC_PCIE_1_LINK_DOWN_BCR 4 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_1_PHY_BCR 6 +#define GCC_PCIE_2_BCR 7 +#define GCC_PCIE_2_LINK_DOWN_BCR 8 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_2_PHY_BCR 10 +#define GCC_PCIE_BCR 11 +#define GCC_PCIE_LINK_DOWN_BCR 12 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_QUSB2PHY_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_EMAC0_RGMII_CLK_ARES 24 + +#endif -- GitLab From 1e910b2ba0edd639cc89b5495a3a832b28f77c7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 24 May 2023 19:36:54 +0530 Subject: [PATCH 269/926] dt-bindings: clock: qcom: Add SM8450 video clock controller Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com --- .../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++ 2 files changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml new file mode 100644 index 0000000000000..fe1fda77b835c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8450 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + +properties: + compatible: + const: qcom,sm8450-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h new file mode 100644 index 0000000000000..9d795adfe4eb2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK 0 +#define VIDEO_CC_MVS0_CLK_SRC 1 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS0C_CLK 3 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS1_CLK 5 +#define VIDEO_CC_MVS1_CLK_SRC 6 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS1C_CLK 8 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 +#define VIDEO_CC_PLL0 10 +#define VIDEO_CC_PLL1 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif -- GitLab From 3c678552b00f90387de14ae965ab6c0bafe8ea12 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 24 May 2023 19:36:56 +0530 Subject: [PATCH 270/926] arm64: dts: qcom: sm8450: Add video clock controller Add device node for video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524140656.7076-4-quic_tdas@quicinc.com --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6de3327d9b32a..174a23bd3e589 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -2598,6 +2599,18 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac15000 { compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; -- GitLab From 22ff170d4551756e3e4ef57253c43e8c3fffefed Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 20:22:03 +0530 Subject: [PATCH 271/926] arm64: dts: qcom: sm8550: Add video clock controller Add device node for video clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524145203.13153-5-quic_jkona@quicinc.com --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1c9460dc3d442..0595190081964 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -2385,6 +2386,18 @@ opp-202000000 { }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8550-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- GitLab From d9ef7a805a709a0b07341857d97a25598a7f92da Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 9 Apr 2023 21:21:45 +0300 Subject: [PATCH 272/926] arm64: dts: qcom: pm8998: don't use GIC_SPI for SPMI interrupts Unlike typical GIC interrupts, first cell for SPMI interrupts is the USID rather than GIC_SPI/GIC_PPI/GIC_LPI qualifier. Fix the resin interrupt to use USID value 0x0 rather than GIC_SPI define. Fixes: f86ae6f23a9e ("arm64: dts: qcom: sagit: add initial device tree for sagit") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230409182145.122895-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 340033ac31860..695d79116cde2 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -55,7 +55,7 @@ pm8998_pwrkey: pwrkey { pm8998_resin: resin { compatible = "qcom,pm8941-resin"; - interrupts = ; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; bias-pull-up; status = "disabled"; -- GitLab From 20fd55b2b0acd496cc6d3cb98832fe2438939ac4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Apr 2023 20:14:41 +0200 Subject: [PATCH 273/926] arm64: dts: qcom: sm8150-kumano: Add GPIO line names for PMIC GPIOs Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Griffin and Bahamut device trees to better document the hardware. They are the same on both devices! Very nice! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kumano_dts0-v2-1-0ca7fa521b86@linaro.org --- .../dts/qcom/sm8150-sony-xperia-kumano.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 47e2430991ca0..6753c65d75bcc 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -456,6 +456,17 @@ &i2c10 { }; &pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "", + "NC", + "NC", + "", + "NC", + "SUPWC_PWR_EN", + "", + "NC", + "NC"; /* GPIO_10 */ + vol_down_n: vol-down-n-state { pins = "gpio1"; function = "normal"; @@ -466,6 +477,19 @@ vol_down_n: vol-down-n-state { }; &pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "TS_VDDH_EN", + "LCD_ID", + "", + "NC", /* GPIO_10 */ + "NC", + "RF_ID"; + snapshot_n: snapshot-n-state { pins = "gpio1"; function = "normal"; @@ -483,6 +507,21 @@ focus_n: focus-n-state { }; }; +&pm8150l_gpios { + gpio-line-names = "TS_VDDIO_EN", /* GPIO_1 */ + "NC", + "MAIN_CAM_PWR_VMDR_EN", + "NC", + "", + "NC", + "NC", + "FP_LDO_EN", + "NC", + "NC", /* GPIO_10 */ + "NC", + "NC"; +}; + &pon_pwrkey { status = "okay"; }; -- GitLab From b949d8032fa287633faf895dc3669a7fd6720071 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Apr 2023 20:14:42 +0200 Subject: [PATCH 274/926] arm64: dts: qcom: sm8150-kumano: Add GPIO line names for TLMM Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the common DTSI to better document the hardware. The pin assignment for TLMM is identical on both devices. Great job! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kumano_dts0-v2-2-0ca7fa521b86@linaro.org --- .../dts/qcom/sm8150-sony-xperia-kumano.dtsi | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 6753c65d75bcc..d1a3ab8360196 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -541,6 +541,181 @@ &qupv3_id_1 { &tlmm { gpio-reserved-ranges = <126 4>; + gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", + "NFC_ESE_SPI_CS_N", + "NC", + "NC", + "DISP_RESET_N", + "DEBUG_GPIO0", + "MDP_VSYNC_P", + "TS_I2C_SDA", + "TS_I2C_SCL", /* GPIO_10 */ + "CAM_SOF", + "CAM2_RST_N", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "NC", + "MAIN_CAM_PWR_EN", + "CAM3_RST_N", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "NC", + "CAM0_RST_N", + "RGBC_IR_PWR_EN", + "CAM1_RST_N", /* GPIO_30 */ + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "NC", + "DEBUG_GPIO1", + "RGBC_IR_INT", + "USB_CC_DIR", + "NC", + "NC", /* GPIO_40 */ + "NFC_EN", + "NFC_ESE_PWR_REQ", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "NFC_IRQ", + "NFC_DWL_REQ", + "UIM2_DETECT_EN", + "WLAN_SW_CTRL", /* GPIO_50 */ + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "NC", + "TS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "HW_ID_0", + "NC", /* GPIO_60 */ + "QLINK_REQUEST", + "QLINK_ENABLE", + "WMSS_RESET_N", + "SDM_GRFC_8", + "WDOG_DISABLE", + "NC", + "NC", + "PA_INDICATOR_OR", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", /* GPIO_70 */ + "SDM_RFFE0_DATA", + "SDM_RFFE0_CLK", + "SDM_RFFE1_DATA", + "SDM_RFFE1_CLK", + "SDM_RFFE2_DATA", + "SDM_RFFE2_CLK", + "SDM_RFFE3_DATA", + "SDM_RFFE3_CLK", + "SUB_CAM_PWR_EN", + "FP_RESET_N", /* GPIO_80 */ + "NC", + "NC", + "NC", + "NC", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "DVDT_WRT_DET_AND", + "NC", + "NC", + "NC", /* GPIO_90 */ + "NC", + "NC", + "NC", + "NC", + "UDON_SWITCH_SEL", + "SD_CARD_DET_N", + "NC", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "USB_AUDIO_EN1", /* GPIO_100 */ + "DISP_ERR_FG", + "NC", + "NC", + "NC", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_DET", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", + "UIM1_PRESENT", + "NFC_CLK_REQ", + "SW_SERVICE", + "NC", + "RF_ID_EXTENSION", + "ALS_PROX_INT_N", + "FP_INT", + "DVDT_WRT_DET_OR", + "BAROMETER_INT", /* GPIO_120 */ + "ACC_COVER_OPEN", + "TS_INT_N", + "CODEC_INT1_N", + "CODEC_INT2_N", + "TX_GTR_THRES_IN", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "NC", /* GPIO_130 */ + "DVDT_ENABLE", + "ACCEL_INT", + "NC", + "MAG_INT_N", + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "HW_ID_1", + "NC", /* GPIO_140 */ + "NC", + "NC", + "CODEC_RST_N", + "CDC_SPI_MISO", + "CDC_SPI_MOSI", + "CDC_SPI_SCLK", + "CDC_SPI_CS_N", + "NC", + "LPASS_SLIMBUS_CLK", + "LPASS_SLIMBUS_DATA0", /* GPIO_150 */ + "LPASS_SLIMBUS_DATA1", + "USB_AUDIO_EN2", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "COMPASS_I2C_SDA", + "COMPASS_I2C_SCL", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", /* GPIO_160 */ + "SSC_SENSOR_I2C_SDA", + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "SSC_UART_1_TX", + "SSC_UART_1_RX", + "WL_CMD_CLK_CHAIN0", + "WL_CMD_DATA_CHAIN0", /* GPIO_170 */ + "WL_CMD_CLK_CHAIN1", + "WL_CMD_DATA_CHAIN1", + "WL_BT_COEX_CLK", + "WL_BT_COEX_DATA"; }; &uart2 { -- GitLab From 7a740ec3045bfa3b476ea94dd2d70bc3ac5d0a0f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Apr 2023 20:14:43 +0200 Subject: [PATCH 275/926] arm64: dts: qcom: sm8150-kumano: Set up camera fixed regulators Sony - as per usual - used a whole bunch of GPIO-gated fixed voltage regulators for camera sensors on Kumano. Describe them and the corresponding pins. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kumano_dts0-v2-3-0ca7fa521b86@linaro.org --- .../dts/qcom/sm8150-sony-xperia-kumano.dtsi | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index d1a3ab8360196..ad402f3a90c3b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "sm8150.dtsi" #include "pm8150.dtsi" @@ -81,6 +82,66 @@ key-vol-down { }; }; + cam0_vdig_vreg: cam0-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera0_vdig_vreg"; + gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&main_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam1_vdig_vreg: cam1-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera1_vdig_vreg"; + gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&sub_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam2_vdig_vreg: cam2-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera2_vdig_vreg"; + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&chat_cam_pwr_en>; + pinctrl-names = "default"; + }; + + cam3_vdig_vreg: cam3-vdig-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera3_vdig_vreg"; + gpio = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&supwc_pwr_en>; + pinctrl-names = "default"; + }; + + cam_vmdr_vreg: cam-vmdr-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vmdr_vreg"; + gpio = <&pm8150l_gpios 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&main_cam_pwr_vmdr_en>; + pinctrl-names = "default"; + }; + + rgbcir_vreg: rgbcir-regulator { + compatible = "regulator-fixed"; + regulator-name = "rgbcir_vreg"; + gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rgbc_ir_pwr_en>; + pinctrl-names = "default"; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -474,6 +535,15 @@ vol_down_n: vol-down-n-state { bias-pull-up; input-enable; }; + + supwc_pwr_en: supwc-pwr-en-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = <1>; + power-source = <1>; + drive-push-pull; + output-low; + }; }; &pm8150b_gpios { @@ -520,6 +590,15 @@ &pm8150l_gpios { "NC", /* GPIO_10 */ "NC", "NC"; + + main_cam_pwr_vmdr_en: main-cam-pwr-vmdr-en-state { + pins = "gpio3"; + function = "normal"; + qcom,drive-strength = ; + power-source = <0>; + drive-push-pull; + output-low; + }; }; &pon_pwrkey { @@ -716,6 +795,37 @@ &tlmm { "WL_CMD_DATA_CHAIN1", "WL_BT_COEX_CLK", "WL_BT_COEX_DATA"; + + main_cam_pwr_en: main-cam-pwr-en-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + chat_cam_pwr_en: chat-cam-pwr-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + rgbc_ir_pwr_en: rgbc-ir-pwr-en-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + sub_cam_pwr_en: sub-cam-pwr-en-state { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart2 { -- GitLab From 644ab8bb42b596f16d01fb140088afb616f67cd8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Apr 2023 20:14:44 +0200 Subject: [PATCH 276/926] arm64: dts: qcom: sm8150-kumano: Enable SDHCI2 Set up and enable SDHCI2 to enable the microSD slot on Kumano devices. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kumano_dts0-v2-4-0ca7fa521b86@linaro.org --- .../boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index ad402f3a90c3b..baafea53770bf 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -618,6 +618,17 @@ &qupv3_id_1 { status = "okay"; }; +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <126 4>; gpio-line-names = "NFC_ESE_SPI_MISO", /* GPIO_0 */ -- GitLab From 6ce42cb4b7dc67fdb670930cc72732fa3fc8df2e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 12 Apr 2023 22:24:51 +0200 Subject: [PATCH 277/926] arm64: dts: qcom: sm8250-edo: Enable Venus Enable Venus on Edo phones. The firmware is signed, as per usual. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230412-edo_venus-v1-1-bcfc82e0efc3@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 2f22d348d45d7..8d4352c8c5431 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -672,3 +672,8 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p9>; }; + +&venus { + firmware-name = "qcom/sm8250/Sony/edo/venus.mbn"; + status = "okay"; +}; -- GitLab From 3e459be2a315dd017cbed6a86c23e636987b493f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 13 Apr 2023 02:37:36 +0200 Subject: [PATCH 278/926] arm64: dts: qcom: msm8996-tone: Enable LPG LEDs Enable the notification LED(s) wired up to the PMI8994(6) LPG. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230413-tone_led-v1-1-bc3c73393bfa@linaro.org --- .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 7f4d493a55ff4..b4b770a9277dc 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -11,6 +11,7 @@ #include "pmi8996.dtsi" #include #include +#include #include #include @@ -605,6 +606,34 @@ pm8994_s11: s11 { }; }; +&pmi8994_lpg { + qcom,power-source = <1>; + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pmi8994_spmi_regulators { vdd_gfx: pmi8994_s2: s2 { -- GitLab From 935e538fd6b8e30151ee822313c01005bd2865ad Mon Sep 17 00:00:00 2001 From: Arnaud Vrac Date: Mon, 17 Apr 2023 18:49:46 +0200 Subject: [PATCH 279/926] arm64: dts: qcom: msm8998: add blsp spi nodes Add pinctrl and qup nodes in msm8998 device tree to support spi. Values were ported from downstream msm-4.4 kernel. Signed-off-by: Arnaud Vrac Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230417-msm8998-spi-v2-1-b314c6d9ea31@freebox.fr --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 309 ++++++++++++++++++++++++++ 1 file changed, 309 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b150437a83558..c53e8dda44a6f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1228,6 +1228,57 @@ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { drive-strength = <2>; bias-pull-up; }; + + blsp1_spi_b_default: blsp1-spi-b-default-state { + pins = "gpio23", "gpio28"; + function = "blsp1_spi_b"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_spi1"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi2_default: blsp1-spi2-default-state { + pins = "gpio31", "gpio34", "gpio32", "gpio33"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi3_default: blsp1-spi3-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_spi2"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi4_default: blsp1-spi4-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "blsp_spi4"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi5_default: blsp1-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "blsp_spi5"; + drive-strength = <6>; + bias-disable; + }; + + blsp1_spi6_default: blsp1-spi6-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "blsp_spi6"; + drive-strength = <6>; + bias-disable; + }; + + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ blsp2_i2c1_default: blsp2-i2c1-default-state { pins = "gpio55", "gpio56"; @@ -1312,6 +1363,48 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { drive-strength = <2>; bias-pull-up; }; + + blsp2_spi1_default: blsp2-spi1-default-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "blsp_spi7"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi2_default: blsp2-spi2-default-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_spi8"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi3_default: blsp2-spi3-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_spi9"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi4_default: blsp2-spi4-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "blsp_spi10"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi5_default: blsp2-spi5-default-state { + pins = "gpio58", "gpio59", "gpio60", "gpio61"; + function = "blsp_spi11"; + drive-strength = <6>; + bias-disable; + }; + + blsp2_spi6_default: blsp2-spi6-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "blsp_spi12"; + drive-strength = <6>; + bias-disable; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -2249,6 +2342,114 @@ blsp1_i2c6: i2c@c17a000 { #size-cells = <0>; }; + blsp1_spi1: spi@c175000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi2: spi@c176000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c176000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi3: spi@c177000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c177000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi4: spi@c178000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c178000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi5: spi@c179000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c179000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp1_spi6: spi@c17a000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c17a000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x25000>; @@ -2392,6 +2593,114 @@ blsp2_i2c6: i2c@c1ba000 { #size-cells = <0>; }; + blsp2_spi1: spi@c1b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b5000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi1_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi2: spi@c1b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b6000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi2_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi3: spi@c1b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi3_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi4: spi@c1b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b8000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi4_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi5: spi@c1b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b9000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi5_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + blsp2_spi6: spi@c1ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1ba000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_spi6_default>; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-msm8998"; #clock-cells = <1>; -- GitLab From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:39 +0200 Subject: [PATCH 280/926] arm64: dts: qcom: ipq6018: correct qrng unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000" Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index ccaf8e57668aa..6dd8995fc690e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -301,7 +301,7 @@ mdio: mdio@90000 { status = "disabled"; }; - prng: qrng@e1000 { + prng: qrng@e3000 { compatible = "qcom,prng-ee"; reg = <0x0 0x000e3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; -- GitLab From 48798d992ce276cf0d57bf75318daf8eabd02aa4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:40 +0200 Subject: [PATCH 281/926] arm64: dts: qcom: msm8916: correct camss unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/camss@1b00000: simple-bus unit address format error, expected "1b0ac00" Fixes: 58f479f90a7c ("arm64: dts: qcom: msm8916: Add CAMSS support") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7e0fa37a3adf8..762647e926608 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1161,7 +1161,7 @@ dsi_phy0: phy@1a98300 { }; }; - camss: camss@1b00000 { + camss: camss@1b0ac00 { compatible = "qcom,msm8916-camss"; reg = <0x01b0ac00 0x200>, <0x01b00030 0x4>, -- GitLab From 72644bc76d5145c098c268829554a0b98fab1de1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:41 +0200 Subject: [PATCH 282/926] arm64: dts: qcom: msm8916: correct MMC unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/mmc@7824000: simple-bus unit address format error, expected "7824900" Warning (simple_bus_reg): /soc@0/mmc@7864000: simple-bus unit address format error, expected "7864900" Fixes: c4da5a561627 ("arm64: dts: qcom: Add msm8916 sdhci configuration nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 762647e926608..556dbf7870f46 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1553,7 +1553,7 @@ lpass_codec: audio-codec@771c000 { #sound-dai-cells = <1>; }; - sdhc_1: mmc@7824000 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc", "core"; @@ -1571,7 +1571,7 @@ sdhc_1: mmc@7824000 { status = "disabled"; }; - sdhc_2: mmc@7864000 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc", "core"; -- GitLab From 1f9a41bb0bba7b373c26a6f2cc8d35cc3159c861 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:42 +0200 Subject: [PATCH 283/926] arm64: dts: qcom: msm8916: correct WCNSS unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/remoteproc@a21b000: simple-bus unit address format error, expected "a204000" Fixes: 88106096cbf8 ("ARM: dts: msm8916: Add and enable wcnss node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 556dbf7870f46..4df55f209a1c9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1870,7 +1870,7 @@ usb_hs_phy: phy { }; }; - wcnss: remoteproc@a21b000 { + wcnss: remoteproc@a204000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; -- GitLab From 1c06b93461ec9df8a5878947db4a9d2d1cb72855 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:43 +0200 Subject: [PATCH 284/926] arm64: dts: qcom: msm8953: correct IOMMU unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/iommu@1e00000: simple-bus unit address format error, expected "1e20000" Fixes: c0b9575a3606 ("arm64: dts: qcom: msm8953: add APPS IOMMU") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index eeebdab58c043..076de7c8bf83c 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1000,7 +1000,7 @@ dsi1_phy: phy@1a96400 { }; }; - apps_iommu: iommu@1e00000 { + apps_iommu: iommu@1e20000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x01e20000 0x20000>; -- GitLab From 751038676e3075a5cb816034f7d5ba6e95f4486d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:44 +0200 Subject: [PATCH 285/926] arm64: dts: qcom: msm8953: correct WCNSS unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/remoteproc@a21b000: simple-bus unit address format error, expected "a204000" Fixes: b12428640ebe ("arm64: dts: MSM8953: Add wcnss nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 076de7c8bf83c..92e15946039ba 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1423,7 +1423,7 @@ i2c_8: i2c@7af8000 { status = "disabled"; }; - wcnss: remoteproc@a21b000 { + wcnss: remoteproc@a204000 { compatible = "qcom,pronto-v3-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; -- GitLab From 80284797a4cb8ceae71e3c403bafc6648263a060 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:45 +0200 Subject: [PATCH 286/926] arm64: dts: qcom: msm8976: correct MMC unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/mmc@7824000: simple-bus unit address format error, expected "7824900" Warning (simple_bus_reg): /soc@0/mmc@7864000: simple-bus unit address format error, expected "7864900" Warning (simple_bus_reg): /soc@0/mmc@7a24000: simple-bus unit address format error, expected "7a24900" Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 1f0bd24a074a6..937bb7fcca266 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -820,7 +820,7 @@ spmi_bus: spmi@200f000 { #interrupt-cells = <4>; }; - sdhc_1: mmc@7824000 { + sdhc_1: mmc@7824900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x500>, <0x07824000 0x800>; reg-names = "hc", "core"; @@ -836,7 +836,7 @@ sdhc_1: mmc@7824000 { status = "disabled"; }; - sdhc_2: mmc@7864000 { + sdhc_2: mmc@7864900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc", "core"; @@ -955,7 +955,7 @@ otg: usb@78db000 { #reset-cells = <1>; }; - sdhc_3: mmc@7a24000 { + sdhc_3: mmc@7a24900 { compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07a24900 0x11c>, <0x07a24000 0x800>; reg-names = "hc", "core"; -- GitLab From 24f0f6a8059c7108d4ee3476c95db1e7ff4feb79 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:46 +0200 Subject: [PATCH 287/926] arm64: dts: qcom: msm8994: correct SPMI unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/spmi@fc4c0000: simple-bus unit address format error, expected "fc4cf000" Fixes: b0ad598f8ec0 ("arm64: dts: qcom: msm8994: Add SPMI PMIC arbiter device") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 2831966be960d..4041f3a690fec 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -745,7 +745,7 @@ restart@fc4ab000 { reg = <0xfc4ab000 0x4>; }; - spmi_bus: spmi@fc4c0000 { + spmi_bus: spmi@fc4cf000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xfc4cf000 0x1000>, <0xfc4cb000 0x1000>, -- GitLab From e959ced1d0e5ef0b1f66a0c2d0e1ae80790e5ca5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:47 +0200 Subject: [PATCH 288/926] arm64: dts: qcom: msm8996: correct camss unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/camss@a00000: simple-bus unit address format error, expected "a34000" Fixes: e0531312e78f ("arm64: dts: qcom: msm8996: Add CAMSS support") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2b35cb3f52921..f0114e4fdd375 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2067,7 +2067,7 @@ ufsphy_lane: phy@627400 { }; }; - camss: camss@a00000 { + camss: camss@a34000 { compatible = "qcom,msm8996-camss"; reg = <0x00a34000 0x1000>, <0x00a00030 0x4>, -- GitLab From c8b7faa7e9913a94444b3f00b6480e53a174fcfd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:48 +0200 Subject: [PATCH 289/926] arm64: dts: qcom: sdm630: correct camss unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/camss@ca00000: simple-bus unit address format error, expected "ca00020" Fixes: f3d5d3cc6971 ("arm64: dts: qcom: sdm630: Configure the camera subsystem") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 37e72b1c56dce..b31424544b196 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1892,7 +1892,7 @@ pil-reloc@94c { }; }; - camss: camss@ca00000 { + camss: camss@ca00020 { compatible = "qcom,sdm660-camss"; reg = <0x0ca00020 0x10>, <0x0ca30000 0x100>, -- GitLab From a05b913a27e46926ba60ba2bcacc7ec7a8403e4c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:49 +0200 Subject: [PATCH 290/926] arm64: dts: qcom: sdm845: correct camss unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/camss@a00000: simple-bus unit address format error, expected "acb3000" Fixes: d48a6698a6b7 ("arm64: dts: qcom: sdm845: Add CAMSS ISP node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 90424442bb4ac..b3d00d805ecc3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4229,7 +4229,7 @@ videocc: clock-controller@ab00000 { #reset-cells = <1>; }; - camss: camss@a00000 { + camss: camss@acb3000 { compatible = "qcom,sdm845-camss"; reg = <0 0x0acb3000 0 0x1000>, -- GitLab From 2358b43256080459fcc5642265ed4fec75558f8c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:50 +0200 Subject: [PATCH 291/926] arm64: dts: qcom: sm6115: correct thermal-sensor unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/thermal-sensor@4410000: simple-bus unit address format error, expected "4411000" Fixes: 7b74cba6b13f ("arm64: dts: qcom: sm6115: Add TSENS node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-12-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 631ca327e064b..94623fba0d56f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -698,7 +698,7 @@ spmi_bus: spmi@1c40000 { #interrupt-cells = <4>; }; - tsens0: thermal-sensor@4410000 { + tsens0: thermal-sensor@4411000 { compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ <0x0 0x04410000 0x0 0x8>; /* SROT */ -- GitLab From 41d6bca799b3f40d4d3c22dd4545aeac7c210e33 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:51 +0200 Subject: [PATCH 292/926] arm64: dts: qcom: sm8350: correct DMA controller unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/dma-controller@900000: simple-bus unit address format error, expected "9800000" Fixes: bc08fbf49bc8 ("arm64: dts: qcom: sm8350: Define GPI DMA engines") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-13-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c057e320c1d0a..b38c921b0f961 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -898,7 +898,7 @@ spi19: spi@894000 { }; }; - gpi_dma0: dma-controller@900000 { + gpi_dma0: dma-controller@9800000 { compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x09800000 0 0x60000>; interrupts = , -- GitLab From ab98c21bc9246f421a6ae70e69f1b73cea6f85e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:52 +0200 Subject: [PATCH 293/926] arm64: dts: qcom: sm8350: correct PCI phy unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/phy@1c0f000: simple-bus unit address format error, expected "1c0e000" Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-14-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b38c921b0f961..94cdc2bf595f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1629,7 +1629,7 @@ pcie1: pci@1c08000 { status = "disabled"; }; - pcie1_phy: phy@1c0f000 { + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, -- GitLab From a560ab70c6e28ba784a824611d3f58969d8fadba Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:53 +0200 Subject: [PATCH 294/926] arm64: dts: qcom: sm8350: correct USB phy unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/phy@88e9000: simple-bus unit address format error, expected "88e8000" Fixes: 2458a305e80e ("arm64: dts: qcom: sm8350: switch to combo usb3/dp phy") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-15-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 94cdc2bf595f7..ae09460462ed8 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2131,7 +2131,7 @@ usb_2_hsphy: phy@88e4000 { resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; - usb_1_qmpphy: phy@88e9000 { + usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm8350-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; -- GitLab From 3cbf49ef16962ab6d99a3659cb34a33c5f147b50 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:54 +0200 Subject: [PATCH 295/926] arm64: dts: qcom: sm8550: correct crypto unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/crypto@1de0000: simple-bus unit address format error, expected "1dfa000" Fixes: 433477c3bf0b ("arm64: dts: qcom: sm8550: add QCrypto nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-16-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 0595190081964..011d101867e95 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1850,7 +1850,7 @@ cryptobam: dma-controller@1dc4000 { <&apps_smmu 0x481 0x0>; }; - crypto: crypto@1de0000 { + crypto: crypto@1dfa000 { compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0x0 0x01dfa000 0x0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; -- GitLab From 950a4fe6ec8498799d1c7bd31a489a718f94a87e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:55 +0200 Subject: [PATCH 296/926] arm64: dts: qcom: sm8550: correct pinctrl unit address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc@0/pinctrl@f000000: simple-bus unit address format error, expected "f100000" Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-17-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 011d101867e95..94201d08b5af1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2887,7 +2887,7 @@ spmi_bus: spmi@c400000 { #interrupt-cells = <4>; }; - tlmm: pinctrl@f000000 { + tlmm: pinctrl@f100000 { compatible = "qcom,sm8550-tlmm"; reg = <0 0x0f100000 0 0x300000>; interrupts = ; -- GitLab From 4a0156b8862665a3e31c8280607388e3001ace3d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:18:56 +0200 Subject: [PATCH 297/926] arm64: dts: qcom: sdm845-polaris: add missing touchscreen child node reg Add missing reg property to touchscreen child node to fix dtbs W=1 warnings: Warning (unit_address_vs_reg): /soc@0/geniqup@ac0000/i2c@a98000/touchscreen@20/rmi4-f12@12: node has a unit name, but no reg or ranges property Fixes: be497abe19bf ("arm64: dts: qcom: Add support for Xiaomi Mi Mix2s") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Molly Sophia Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211856.79332-18-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 8ae0ffccaab22..576f0421824f4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -483,6 +483,7 @@ rmi4-f01@1 { }; rmi4-f12@12 { + reg = <0x12>; syna,rezero-wait-ms = <0xc8>; syna,clip-x-high = <0x438>; syna,clip-y-high = <0x870>; -- GitLab From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:04 +0200 Subject: [PATCH 298/926] arm64: dts: qcom: ipq6018: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 6dd8995fc690e..d3dee4e4f004f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -198,7 +198,7 @@ smem { hwlocks = <&tcsr_mutex 0>; }; - soc: soc { + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x0 0xffffffff>; -- GitLab From da6aa1111a17db11367817ddc10c5a6c188cdc44 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:05 +0200 Subject: [PATCH 299/926] arm64: dts: qcom: ipq8074: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 74ce93e9bd673..6b3fc4ac13205 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -105,7 +105,7 @@ scm { }; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- GitLab From f7fd546dd693f64404bbbdc154b3dac0aee1f3bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:06 +0200 Subject: [PATCH 300/926] arm64: dts: qcom: msm8994: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 4041f3a690fec..184bdde5c78da 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -340,8 +340,7 @@ modem_smp2p_in: slave-kernel { }; }; - soc: soc { - + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- GitLab From b67f5c337f894109a8a9c40f7dbb74de9cf07d57 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:07 +0200 Subject: [PATCH 301/926] arm64: dts: qcom: msm8996: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f0114e4fdd375..8a40c4b0f94c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -604,7 +604,7 @@ slpi_smp2p_in: slave-kernel { }; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- GitLab From 77462beddbfc700d36fe1f24d77b545fe3d6db44 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:08 +0200 Subject: [PATCH 302/926] arm64: dts: qcom: msm8998: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c53e8dda44a6f..9c7568fb49503 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -800,7 +800,7 @@ timer { ; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- GitLab From cefb40777a6c695e754d918cf5a5551169e40965 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:09 +0200 Subject: [PATCH 303/926] arm64: dts: qcom: sdm630: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b31424544b196..a7d475f23beaf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -548,7 +548,7 @@ modem_smp2p_in: slave-kernel { }; }; - soc { + soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- GitLab From 188e26bc67896cb89aca0821b366833e9abf829e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:36:10 +0200 Subject: [PATCH 304/926] arm64: dts: qcom: sm6125: add unit address to soc node "soc" node is supposed to have unit address: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420063610.11068-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 9484752fb8506..745874a82a49d 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -364,7 +364,7 @@ smem: smem { hwlocks = <&tcsr_mutex 3>; }; - soc { + soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00 0xffffffff>; -- GitLab From 5a60e72c3eff0747cc779b8067cd795acf6beecd Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 21 Apr 2023 23:56:22 +0200 Subject: [PATCH 305/926] arm64: dts: qcom: pm8953: add GPIOs Add a node for the GPIOs found on the pm8953. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421-pm8953-gpio-v1-3-3d33e2de47e3@z3ntu.xyz --- arch/arm64/boot/dts/qcom/pm8953.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index a1d36f9ebbd25..2268daf27fa7a 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -79,6 +79,16 @@ rtc@6000 { reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; + + pm8953_gpios: gpio@c000 { + compatible = "qcom,pm8953-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8953_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@1 { -- GitLab From a5317b23fe6f26307f4c821d56d694c893887675 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 22 Apr 2023 13:39:16 +0200 Subject: [PATCH 306/926] arm64: dts: qcom: msm8953: Add BLSP DMAs for I2C MSM8953 has two DMA controllers for the various I2C, SPI and UART busses. Add the nodes and configure all the I2C nodes so that the driver can use the DMA. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230422-msm8953-blsp-dma-v1-1-0024801bb587@z3ntu.xyz --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 92e15946039ba..f42a1e3763407 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1274,6 +1274,19 @@ opp-200000000 { }; }; + blsp1_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + num-channels = <12>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,num-ees = <4>; + qcom,controlled-remotely; + }; + uart_0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; @@ -1292,6 +1305,8 @@ i2c_1: i2c@78b5000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_1_default>; @@ -1310,6 +1325,8 @@ i2c_2: i2c@78b6000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_2_default>; @@ -1328,6 +1345,9 @@ i2c_3: i2c@78b7000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_3_default>; pinctrl-1 = <&i2c_3_sleep>; @@ -1345,6 +1365,9 @@ i2c_4: i2c@78b8000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_4_default>; pinctrl-1 = <&i2c_4_sleep>; @@ -1355,6 +1378,19 @@ i2c_4: i2c@78b8000 { status = "disabled"; }; + blsp2_dma: dma-controller@7ac4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07ac4000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + num-channels = <12>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,num-ees = <4>; + qcom,controlled-remotely; + }; + i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; @@ -1362,6 +1398,9 @@ i2c_5: i2c@7af5000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_5_default>; pinctrl-1 = <&i2c_5_sleep>; @@ -1379,6 +1418,9 @@ i2c_6: i2c@7af6000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_6_default>; pinctrl-1 = <&i2c_6_sleep>; @@ -1396,6 +1438,9 @@ i2c_7: i2c@7af7000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_7_default>; pinctrl-1 = <&i2c_7_sleep>; @@ -1413,6 +1458,9 @@ i2c_8: i2c@7af8000 { clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_8_default>; pinctrl-1 = <&i2c_8_sleep>; -- GitLab From 06a9f50c20b5d5fcec9cb0d44b759c4183c7bbd5 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Sat, 6 May 2023 00:32:51 +0800 Subject: [PATCH 307/926] arm64: dts: qcom: msm8916-ufi: make UDC dual mode It's possible to use this device with a (non-standard) hub to get USB working in host mode, but dr_mode="peripheral" prevents the UDC to do so. Remove dr_mode="peripheral" and add usb-role-switch so that it defaults to otg mode and can be switched to host mode in userspace. Signed-off-by: Yang Xiwen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/TYZPR04MB632102315884225B7343533B96729@TYZPR04MB6321.apcprd04.prod.outlook.com --- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 50bae6f214f1f..08ecd901c1af6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -109,7 +109,7 @@ &sdhc_1 { &usb { extcon = <&pm8916_usbin>; - dr_mode = "peripheral"; + usb-role-switch; status = "okay"; }; -- GitLab From 83fae950c9924112ee08792370934e7ab3acd782 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 12 May 2023 18:04:51 +0200 Subject: [PATCH 308/926] arm64: dts: qcom: sm8550-qrd: add WCD9385 audio-codec Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX and TX. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512160452.206585-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 56 +++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 82cda2f9fea4d..88b7d3ecdbc92 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -23,6 +23,32 @@ aliases { serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -456,8 +482,38 @@ &sleep_clk { clock-frequency = <32000>; }; +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 8>; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart7 { -- GitLab From a541667c86a9a0510d17f01461072a80fd6cfffd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 12 May 2023 18:04:52 +0200 Subject: [PATCH 309/926] arm64: dts: qcom: sm8550-mtp: add WCD9385 audio-codec Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX and TX. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512160452.206585-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 56 +++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index e2b9bb6b1e279..785889450e8a7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -23,6 +23,32 @@ aliases { serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -535,6 +561,28 @@ &sleep_clk { clock-frequency = <32000>; }; +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 8>; @@ -565,6 +613,14 @@ sde_te_suspend: sde-te-suspend-state { drive-strength = <2>; bias-pull-down; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart7 { -- GitLab From 43926a3cb19180b4fc6cd0d72bbefc7e93592f91 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Mon, 15 May 2023 14:37:41 +0500 Subject: [PATCH 310/926] arm64: dts: qcom: sc7180: Don't enable lpass clocks by default lpass clocks are usually blocked from HLOS by the firmware and instead are managed by the ADSP. Mark them as reserved and explicitly enable in the CrOS boards that have special, cooperative firmware. The IDP board gets lpass clocks disabled as it doesn't make use of sound anyway and might use Qualcomm firmware that blocks those clocks. [1] [1] https://lore.kernel.org/all/ZBJhmDd3zK%2FAiwBD@google.com/ Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515093744.289045-2-nikita@trvn.ru --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index ca6920de7ea87..6cf09152fdfd3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -788,6 +788,10 @@ alc5682: codec@1a { }; }; +&lpasscc { + status = "okay"; +}; + &lpass_cpu { status = "okay"; @@ -813,6 +817,10 @@ dai-link@5 { }; }; +&lpass_hm { + status = "okay"; +}; + &mdp { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ea1ffade1aa19..39130596dc7d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3627,6 +3627,8 @@ lpasscc: clock-controller@62d00000 { power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; #clock-cells = <1>; #power-domain-cells = <1>; + + status = "reserved"; /* Controlled by ADSP */ }; lpass_cpu: lpass@62d87000 { @@ -3675,6 +3677,8 @@ lpass_hm: clock-controller@63000000 { #clock-cells = <1>; #power-domain-cells = <1>; + + status = "reserved"; /* Controlled by ADSP */ }; }; -- GitLab From 39238382c4991d7d9442de4aa6636b19355be1e9 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Mon, 15 May 2023 14:37:42 +0500 Subject: [PATCH 311/926] arm64: dts: qcom: sc7180: Drop redundant disable in mdp mdss is useless without a display controller which makes explicitly enabling mdp redundant. Have it enabled by default to drop the extra node for all users. Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515093744.289045-3-nikita@trvn.ru --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 -- 3 files changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 9f052270e0908..bd9ed03159cfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -334,10 +334,6 @@ &dsi_phy { vdds-supply = <&vreg_l4a_0p8>; }; -&mdp { - status = "okay"; -}; - &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 6cf09152fdfd3..51d6c3502f3ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -821,10 +821,6 @@ &lpass_hm { status = "okay"; }; -&mdp { - status = "okay"; -}; - &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 39130596dc7d3..d89aa56191639 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2988,8 +2988,6 @@ mdp: display-controller@ae01000 { interrupt-parent = <&mdss>; interrupts = <0>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; -- GitLab From aaffd364118bbc5b20c0a92f82780ea22e1c3f07 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Mon, 15 May 2023 14:37:43 +0500 Subject: [PATCH 312/926] dt-bindings: arm: qcom: Add Acer Aspire 1 Acer Aspire 1 is a laptop based on sc7180. Document it's compatible. Signed-off-by: Nikita Travkin Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515093744.289045-4-nikita@trvn.ru --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 767e4c22f7617..bf356587765b3 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -380,9 +380,9 @@ properties: - qcom,qru1000-idp - const: qcom,qru1000 - - description: Qualcomm Technologies, Inc. SC7180 IDP - items: + - items: - enum: + - acer,aspire1 - qcom,sc7180-idp - const: qcom,sc7180 -- GitLab From 4a9f8f8f2adaa05abfdec7c588c8dab3281048f0 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Mon, 15 May 2023 14:37:44 +0500 Subject: [PATCH 313/926] arm64: dts: qcom: Add Acer Aspire 1 Acer Aspire 1 is a WoA laptop based on Snapdragon 7c gen1 platform. The laptop design is similar to trogdor in the choice of primary components but the specifics on usage of those differ slightly. Add the devicetree for the laptop with support for most of the hardware present. Signed-off-by: Nikita Travkin Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230515093744.289045-5-nikita@trvn.ru --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc7180-acer-aspire1.dts | 845 ++++++++++++++++++ 2 files changed, 846 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e311ba675f359..063c41a0aebc3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts new file mode 100644 index 0000000000000..2a80f4090085b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include +#include + +#include "sc7180.dtsi" + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &tz_mem; +/delete-node/ &ipa_fw_mem; + +/ { + model = "Acer Aspire 1"; + compatible = "acer,aspire1", "qcom,sc7180"; + chassis-type = "laptop"; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + serial0 = &uart8; + wifi0 = &wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + zap_mem: zap-shader@80840000 { + reg = <0x0 0x80840000 0 0x2000>; + no-map; + }; + + venus_mem: venus@85b00000 { + reg = <0x0 0x85b00000 0 0x500000>; + no-map; + }; + + mpss_mem: mpss@86000000 { + reg = <0x0 0x86000000 0x0 0x2000000>; + no-map; + }; + + adsp_mem: adsp@8e400000 { + reg = <0x0 0x8e400000 0x0 0x2800000>; + no-map; + }; + + wlan_mem: wlan@93900000 { + reg = <0x0 0x93900000 0x0 0x200000>; + no-map; + }; + }; + + max98357a: audio-codec { + compatible = "maxim,max98357a"; + sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&_sd_mode_default>; + pinctrl-names = "default"; + + #sound-dai-cells = <0>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&sn65dsi86_bridge 1000000>; + enable-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&soc_bkoff_default>; + pinctrl-names = "default"; + }; + + reg_brij_1p2: bridge-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "brij_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_edp_1p2_en_default>; + pinctrl-names = "default"; + }; + + reg_brij_1p8: bridge-regulator { + compatible = "regulator-fixed"; + regulator-name = "brij_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l8c_1p8>; + + gpio = <&tlmm 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_edp_1p8_en_default>; + pinctrl-names = "default"; + }; + + reg_codec_3p3: codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "codec_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_audio_en_default>; + pinctrl-names = "default"; + }; + + reg_lcm_3p3: panel-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcm_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_lcm_en_default>; + pinctrl-names = "default"; + }; + + reg_tp_3p3: touchpad-regulator { + compatible = "regulator-fixed"; + regulator-name = "tp_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tp_en_default>; + pinctrl-names = "default"; + }; +}; + +&dsi0 { + vdda-supply = <&vreg_l3c_1p2>; + status = "okay"; +}; + +&dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi_phy { + vdds-supply = <&vreg_l4a_0p8>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + /* embedded-controller@76 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* + * NOTE: DSDT defines two possible touchpads, other one is + * + * reg = <0x15>; + * hid-descr-addr = <0x1>; + */ + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + vdd-supply = <®_tp_3p3>; + + interrupts-extended = <&tlmm 94 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&hid_touchpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 33 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&hid_keyboard_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + alc5682: codec@1a { + compatible = "realtek,rt5682i"; + reg = <0x1a>; + + #sound-dai-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <28 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-0 = <&codec_irq_default>; + pinctrl-names = "default"; + + AVDD-supply = <&vreg_l15a_1p8>; + MICVDD-supply = <®_codec_3p3>; + VBAT-supply = <®_codec_3p3>; + + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <1>; + realtek,jd-src = <1>; + }; +}; + +&i2c10 { + clock-frequency = <400000>; + status = "okay"; + + sn65dsi86_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + suspend-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&bridge_en_default>, + <&edp_bridge_irq_default>, + <&bridge_suspend_default>; + pinctrl-names = "default"; + + vpll-supply = <®_brij_1p8>; + vccio-supply = <®_brij_1p8>; + vcca-supply = <®_brij_1p2>; + vcc-supply = <®_brij_1p2>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK3>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sn65dsi86_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <®_lcm_3p3>; + backlight = <&backlight>; + hpd-absent-delay-ms = <200>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&zap_mem>; + firmware-name = "qcom/sc7180/acer/aspire1/qcdxkmsuc7180.mbn"; + }; +}; + +&mdss { + status = "okay"; +}; + +&pm6150_adc { + thermistor@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + charger-thermistor@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + charger-thermistor@0 { + reg = <0>; + io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm6150_pon { + status = "disabled"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l19a_2p9>; + vqmmc-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + +&uart3 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart3_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3991-bt"; + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vreg_l2c_1p3>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_2_x: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + peer-hub = <&usb_hub_3_x>; + }; + + usb_hub_3_x: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + peer-hub = <&usb_hub_2_x>; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; + qcom,imp-res-offset-value = <8>; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l4a_0p8>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sc7180/acer/aspire1/qcvss7180.mbn"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&qup_i2c2_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c4_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c9_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&qup_i2c10_default { + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; +}; + +&tlmm { + /* + * The TZ seem to protect those because some boards can have + * fingerprint sensor connected to this range. Not connected + * on this board + */ + gpio-reserved-ranges = <58 5>; + + amp_sd_mode_default: amp-sd-mode-deault-state { + pins = "gpio23"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + bridge_en_default: bridge-en-default-state { + pins = "gpio51"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + bridge_suspend_default: bridge-suspend-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + codec_irq_default: codec-irq-deault-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_bridge_irq_default: edp-bridge-irq-default-state { + pins = "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + hid_keyboard_default: hid-keyboard-default-state { + pins = "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hid_touchpad_default: hid-touchpad-default-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; + + reg_edp_1p2_en_default: reg-edp-1p2-en-deault-state { + pins = "gpio19"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_edp_1p8_en_default: reg-edp-1p8-en-deault-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_lcm_en_default: reg-lcm-en-deault-state { + pins = "gpio26"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + reg_audio_en_default: reg-audio-en-deault-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tp_en_default: reg-tp-en-deault-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + soc_bkoff_default: soc-bkoff-deault-state { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <16>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; +}; -- GitLab From ec8bb9c5b1c6963db3ed09e4a9148ae85804b962 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 16 May 2023 02:53:06 +0200 Subject: [PATCH 314/926] arm64: dts: qcom: sm8450: Add missing RPMhPD OPP levels We need more granularity for things like the GPU. Add the missing levels. This unfortunately requires some re-indexing, resulting in an ugly diff. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516005306.952821-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 174a23bd3e589..f853032e89daa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4032,31 +4032,43 @@ rpmhpd_opp_low_svs: opp4 { opp-level = ; }; - rpmhpd_opp_svs: opp5 { + rpmhpd_opp_low_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp6 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp6 { + rpmhpd_opp_svs_l0: opp7 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp8 { opp-level = ; }; - rpmhpd_opp_nom: opp7 { + rpmhpd_opp_svs_l2: opp9 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp10 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp8 { + rpmhpd_opp_nom_l1: opp11 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp9 { + rpmhpd_opp_nom_l2: opp12 { opp-level = ; }; - rpmhpd_opp_turbo: opp10 { + rpmhpd_opp_turbo: opp13 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp11 { + rpmhpd_opp_turbo_l1: opp14 { opp-level = ; }; }; -- GitLab From fbd47f83c5a94f6e3772b4087c97292601857e68 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 16 May 2023 08:56:14 +0200 Subject: [PATCH 315/926] arm64: dts: qcom: sm6350: Move wifi node to correct place Somehow wifi was placed further up in the file than where it should be. Move it down so the nodes are sorted by reg again. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516-sm6350-order-v1-1-5c3b7c4cd761@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++-------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 18c4616848cef..4dffd7974fa39 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1891,28 +1891,6 @@ frame@17c2d000 { }; }; - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_fw_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x20 0x1>; - qcom,msa-fixed-perm; - status = "disabled"; - }; - apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; label = "apps_rsc"; @@ -2010,6 +1988,28 @@ cpufreq_hw: cpufreq@18323000 { #freq-domain-cells = <1>; #clock-cells = <1>; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_fw_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x20 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; }; timer { -- GitLab From cf51d2be057b19f2ef72233788c3211f0781678d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:02:01 +0200 Subject: [PATCH 316/926] arm64: dts: qcom: pm8550: add flash LED controller Add node for PM8550 PMIC flash LED controller. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516150202.188655-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 46396ec1a330a..33f357a806362 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -55,5 +55,11 @@ pm8550_gpios: gpio@8800 { interrupt-controller; #interrupt-cells = <2>; }; + + pm8550_flash: led-controller@ee00 { + compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; }; }; -- GitLab From a158f00cdf68852850df231526ce0df0bb7dc1b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:02:02 +0200 Subject: [PATCH 317/926] arm64: dts: qcom: sm8550-qrd: add flash LEDs Enable PM8550 PMIC flash LED controller and add two flash LEDs using four current outputs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516150202.188655-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 88b7d3ecdbc92..30b36a1491254 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "sm8550.dtsi" #include "pm8010.dtsi" @@ -451,6 +452,30 @@ &pcie0_phy { status = "okay"; }; +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; -- GitLab From 5ef00c06ea5e4e0de1f63d2c620f671750f73f9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:45:37 +0200 Subject: [PATCH 318/926] arm64: dts: qcom: sm8550: enable DISPCC by default Enable the Display Clock Controller by default in SoC DTSI so unused clocks can be turned off. It does not require any external resources, so as core SoC component should be always available to boards. Suggested-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516154539.238655-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - 2 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 785889450e8a7..f27d5c657f444 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -419,10 +419,6 @@ vreg_l3g_1p2: ldo3 { }; }; -&dispcc { - status = "okay"; -}; - &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 94201d08b5af1..473ab1831ab1b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2697,7 +2697,6 @@ dispcc: clock-controller@af00000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; usb_1_hsphy: phy@88e3000 { -- GitLab From fbeffa580e30fe7fb748e4ccc39c2b18a137c055 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:45:38 +0200 Subject: [PATCH 319/926] arm64: dts: qcom: sm8550-mtp: drop redundant MDP status MDP in sm8550.dtsi is not disabled (although its parent MDSS is), so board DTS does not have to enable it. Suggested-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516154539.238655-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index f27d5c657f444..579f65f523709 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -459,10 +459,6 @@ &mdss_dsi0_phy { status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; -- GitLab From fdb0038e96659f08dae575aae6b4b6b22884d17b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 17:45:39 +0200 Subject: [PATCH 320/926] arm64: dts: qcom: sm8550-qrd: add display and panel Enable Display Subsystem with Visionox VTDR6130 Panel (same as on MTP8550). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516154539.238655-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 68 +++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 30b36a1491254..ade6ba53ae6bc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -431,6 +431,46 @@ &gcc { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + pinctrl-names = "default", "sleep"; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + &pcie_1_phy_aux_clk { status = "disabled"; }; @@ -532,6 +572,34 @@ wcd_tx: codec@0,3 { &tlmm { gpio-reserved-ranges = <32 8>; + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio108"; function = "gpio"; -- GitLab From 9ef42640504e09ecc79530b6e532ebf48305516b Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 17 May 2023 12:58:06 +0530 Subject: [PATCH 321/926] arm64: dts: qcom: ipq9574: add few device nodes Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes. While at it, enable the SPI NOR in RDP433 board. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517072806.13170-1-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index ccf70bafababc..fea15f3cf9100 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -116,6 +116,13 @@ soc: soc@0 { #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; @@ -178,6 +185,36 @@ sdhc_1: mmc@7804000 { status = "disabled"; }; + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x2b000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; @@ -188,6 +225,163 @@ blsp1_uart2: serial@78b1000 { status = "disabled"; }; + blsp1_uart3: serial@78b2000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b2000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart4: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b3000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart5: serial@78b4000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b4000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi1: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c3: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 18>, <&blsp_dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi3: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 18>, <&blsp_dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c4: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi4: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ @@ -220,6 +414,14 @@ v2m2: v2m@2000 { }; }; + watchdog: watchdog@b017000 { + compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + timeout-sec = <30>; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; -- GitLab From 05860f678c686afebc781c1fe8233bf997f2435b Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Wed, 17 May 2023 21:33:40 +0800 Subject: [PATCH 322/926] arm64: dts: qcom: sm8250-xiaomi-elish: remove redundant empty line Remove a redundant empty line introduced by commit 51c4c2bd6f31 ("arm64: dts: qcom: sm8250-xiaomi-elish-boe: Add mdss and dsi panel") Signed-off-by: Jianhua Lu Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517133340.21111-1-lujianhua000@gmail.com --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 8af6a0120a500..eaac000858946 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -504,7 +504,6 @@ panel_in_1: endpoint { remote-endpoint = <&dsi1_out>; }; }; - }; }; }; -- GitLab From e27654df20d77ad7549a3cf6739ebaa3aa59a088 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:40 +0200 Subject: [PATCH 323/926] arm64: dts: qcom: apq8016-sbc: Fix regulator constraints For some reason DB410c has completely bogus regulator constraints that actually just correspond to the programmable voltages which are already provided by the regulator driver. Some of them are not just outside the recommended operating conditions of the APQ8016E SoC but even exceed the absolute maximum ratings, potentially risking permanent device damage. In practice it's not quite as dangerous thanks to the RPM firmware: It turns out that it has its own voltage constraints and silently clamps all regulator requests. For example, requesting 3.3V for L5 (allowed by the current regulator constraints!) still results in 1.8V being programmed in the actual regulator hardware. Experimentation with various voltages shows that the internal RPM voltage constraints roughly correspond to the safe "specified range" in the PM8916 Device Specification (rather than the "programmable range" used inside apq8016-sbc.dtsi right now). Combine those together with some fixed voltages used in the old msm-3.10 device tree from Qualcomm to give DB410c some actually valid voltage constraints. Cc: Srinivas Kandagatla Fixes: 4c7d53d16d77 ("arm64: dts: apq8016-sbc: add regulators support") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-1-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 64 ++++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 59860a2223b83..14cb217a13c1e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -447,21 +447,21 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; regulator-always-on; regulator-boot-on; }; l1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; }; l2 { @@ -470,13 +470,13 @@ l2 { }; l4 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; }; l5 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; l6 { @@ -485,45 +485,45 @@ l6 { }; l7 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; }; l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; l10 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; }; l12 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; }; l13 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; }; l14 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; /** @@ -531,14 +531,14 @@ l14 { * for mezzanine boards */ l15 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; }; l16 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; l17 { @@ -547,8 +547,8 @@ l17 { }; l18 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; }; }; -- GitLab From 5500f823db38db073d30557af159b77fb1f2bf26 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:41 +0200 Subject: [PATCH 324/926] arm64: dts: qcom: apq8016-sbc: Fix 1.8V power rail on LS expansion The 96Boards specification expects a 1.8V power rail on the low-speed expansion connector that is able to provide at least 0.18W / 100 mA. According to the DB410c hardware user manual this is done by connecting both L15 and L16 in parallel with up to 55mA each (for 110 mA total) [1]. Unfortunately the current regulator setup in the DB410c device tree does not implement the specification correctly and only provides 5 mA: - Only L15 is marked always-on, so L16 is never enabled. - Without specifying a load the regulator is put into LPM where it can only provide 5 mA. Fix this by: - Adding proper voltage constraints for L16. - Making L16 always-on. - Adding regulator-system-load for both L15 and L16. 100 mA should be available in total, so specify 50 mA for each. (The regulator hardware can only be in normal (55 mA) or low-power mode (5 mA) so this will actually result in the expected 110 mA total...) [1]: https://www.96boards.org/documentation/consumer/dragonboard/dragonboard410c/hardware-docs/hardware-user-manual.md.html#power-supplies Cc: Srinivas Kandagatla Fixes: 828dd5d66f0f ("arm64: dts: apq8016-sbc: make 1.8v available on LS expansion") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-2-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 14cb217a13c1e..3ec449f5cab78 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -526,19 +526,27 @@ l14 { regulator-max-microvolt = <3300000>; }; - /** - * 1.8v required on LS expansion - * for mezzanine boards + /* + * The 96Boards specification expects a 1.8V power rail on the low-speed + * expansion connector that is able to provide at least 0.18W / 100 mA. + * L15/L16 are connected in parallel to provide 55 mA each. A minimum load + * must be specified to ensure the regulators are not put in LPM where they + * would only provide 5 mA. */ l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; regulator-always-on; }; l16 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; }; l17 { -- GitLab From 355750828c5519c88de6ac0d09202d2a7e5892c5 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:42 +0200 Subject: [PATCH 325/926] arm64: dts: qcom: msm8916: Fix regulator constraints The regulator constraints for most MSM8916 devices (except DB410c) were originally taken from Qualcomm's msm-3.10 vendor device tree (for lack of better documentation). Unfortunately it turns out that Qualcomm's voltages are slightly off as well and do not match the voltage constraints applied by the RPM firmware. This means that we sometimes request a specific voltage but the RPM firmware actually applies a much lower or higher voltage. This is particularly critical for pm8916_l11 which is used as SD card VMMC regulator: The SD card can choose a voltage from the current range of 1.8 - 2.95V. If it chooses to run at 1.8V we pretend that this is fine but the RPM firmware will still silently end up configuring 2.95V. This can be easily reproduced with a multimeter or by checking the SPMI hardware registers of the regulator. Fix this by making the voltages match the actual "specified range" in the PM8916 Device Specification which is enforced by the RPM firmware. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-3-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 14 +++++++------- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 12 ++++++------ .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 14 +++++++------- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 14 +++++++------- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 14 +++++++------- .../boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 14 +++++++------- .../boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 14 +++++++------- .../boot/dts/qcom/msm8916-samsung-serranove.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 14 +++++++------- .../boot/dts/qcom/msm8916-wingtech-wt88047.dts | 12 ++++++------ 13 files changed, 89 insertions(+), 89 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 13cd9ad167df7..0d517804e44ed 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -159,13 +159,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -199,7 +199,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -209,12 +209,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index fecb69944cfa3..ddd64cc469983 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -201,13 +201,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -241,7 +241,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -251,12 +251,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 91284a1d0966f..982457503a3cc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -169,13 +169,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -209,7 +209,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -219,12 +219,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 525ec76efeeb7..9584d271c5260 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -159,13 +159,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -199,7 +199,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -209,12 +209,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 5b1bac8f51220..baa7bb86cdd5b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -322,13 +322,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -372,12 +372,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index f1dd625e18227..68d1b76aaf772 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -273,13 +273,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -313,7 +313,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -323,12 +323,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 6046e2c1f1586..1e0c08770371a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -155,13 +155,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -195,7 +195,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -205,12 +205,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 16d67749960e0..b362a76eebc94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -285,13 +285,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -325,7 +325,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -335,12 +335,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 74ffd04db8d84..4464beeeaab12 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -168,13 +168,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -208,7 +208,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -218,12 +218,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index adeee0830e768..6e231e92e6756 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -134,13 +134,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -174,7 +174,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -184,12 +184,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 1a41a4db874da..fa5b330aaeaee 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -326,13 +326,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -366,7 +366,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -376,12 +376,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-allow-set-load; regulator-system-load = <200000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 08ecd901c1af6..259c4660bb0fc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -132,13 +132,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -172,7 +172,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -182,12 +182,12 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index ac56c7595f78a..78020a0db4e48 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -194,13 +194,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; l1 { @@ -234,7 +234,7 @@ l7 { }; l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -244,7 +244,7 @@ l9 { }; l10 { - regulator-min-microvolt = <2700000>; + regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; -- GitLab From a5cf21b14666c42912327c7bece38711f6e0d708 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:43 +0200 Subject: [PATCH 326/926] arm64: dts: qcom: msm8916: Disable audio codecs by default Not every device has something connected to the digital audio codec in MSM8916 and/or the analog audio codec in PM8916. Disable those by default so the hardware is only powered up when necessary. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-4-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 5 +++++ arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 5 +++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + arch/arm64/boot/dts/qcom/pm8916.dtsi | 1 + 4 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 3ec449f5cab78..7d7af6406c393 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -310,6 +310,10 @@ &lpass { status = "okay"; }; +&lpass_codec { + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -399,6 +403,7 @@ &usb_hs_phy { }; &wcd_codec { + status = "okay"; clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "mclk"; qcom,mbhc-vthreshold-low = <75 150 237 450 500>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index baa7bb86cdd5b..8197710372ad1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -218,6 +218,10 @@ &lpass { status = "okay"; }; +&lpass_codec { + status = "okay"; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -302,6 +306,7 @@ &usb_hs_phy { }; &wcd_codec { + status = "okay"; qcom,micbias-lvl = <2800>; qcom,mbhc-vthreshold-low = <75 150 237 450 500>; qcom,mbhc-vthreshold-high = <75 150 237 450 500>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4df55f209a1c9..6444a2e6bb2cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1551,6 +1551,7 @@ lpass_codec: audio-codec@771c000 { <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "ahbix-clk", "mclk"; #sound-dai-cells = <1>; + status = "disabled"; }; sdhc_1: mmc@7824900 { diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f4fb1a92ab55a..33ca1002fb754 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -178,6 +178,7 @@ wcd_codec: audio-codec@f000 { vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; vdd-micbias-supply = <&pm8916_l13>; #sound-dai-cells = <1>; + status = "disabled"; }; }; }; -- GitLab From 38218822a72fd31e89affc7fc457d527f65581aa Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:44 +0200 Subject: [PATCH 327/926] arm64: dts: qcom: pm8916: Move default regulator "-supply"s Some of the power supplies for the analog audio codec in PM8916 are wired externally. While most boards use the regulators currently specified in pm8916.dtsi, in theory it could be connected differently. We already have msm8916-pm8916.dtsi that models that standard setup used by most devices so move the -supply properties there and keep the base pm8916.dtsi independent. Currently all MSM8916 boards in mainline make use of msm8916-pm8916.dtsi, so it is not necessary to adjust any other boards. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-5-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/pm8916.dtsi | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 6eb5e0a395100..5b3ed7137e1f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -35,6 +35,12 @@ &usb_hs_phy { v3p3-supply = <&pm8916_l13>; }; +&wcd_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + &wcnss { vddpx-supply = <&pm8916_l7>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 33ca1002fb754..864bb1cd68dbf 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -174,9 +174,6 @@ wcd_codec: audio-codec@f000 { "cdc_ear_cnp_int", "cdc_hphr_cnp_int", "cdc_hphl_cnp_int"; - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; #sound-dai-cells = <1>; status = "disabled"; }; -- GitLab From f193264986b5944216e574b9962616f2524aac08 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:45 +0200 Subject: [PATCH 328/926] arm64: dts: qcom: msm8916-pm8916: Clarify purpose Goal of the msm8916-pm8916.dtsi is to reduce the boilerplate necessary to create a device tree for a typical board with the MSM8916 SoC combined with the PM8916 PMIC. > 99% of all MSM8916 boards use the same standard setup where many of the PM8916 regulators have a fixed purpose and only some are left up for board-specific use. While MSM8916 (and perhaps MSM8939 soon) is currently the only platform with such an include, it has definitely proven useful. With more than 30 boards using it (not all of them upstream yet) it simplifies the review a lot and reduces the chance of configuring the standard components incorrectly. In preparation of extending its scope slightly, add a comment at the top that clearly explains what the .dtsi represents and when it should (or should not) be used. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-6-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 5b3ed7137e1f1..29ef46c333506 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -1,4 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only +/* + * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections) + * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC. + * Many regulators have a fixed purpose in the original reference design and + * were rarely re-used for different purposes. Devices that deviate from the + * typical reference design should not make use of this include and instead add + * the necessary properties in the board-specific device tree. + */ #include "msm8916.dtsi" #include "pm8916.dtsi" -- GitLab From b0a8f16ae4a0eb423122256691849b3ebc64efc2 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:46 +0200 Subject: [PATCH 329/926] arm64: dts: qcom: msm8916: Define regulator constraints next to usage Right now each MSM8916 device has a huge block of regulator constraints with allowed voltages for each regulator. For lack of better documentation these voltages are often copied as-is from the vendor device tree, without much extra thought. Unfortunately, the voltages in the vendor device trees are often misleading or even wrong, e.g. because: - There is a large voltage range allowed and the actual voltage is only set somewhere hidden in some messy vendor driver. This is often the case for pm8916_{l14,l15,l16} because they have a broad range of 1.8-3.3V by default. - The voltage is actually wrong but thanks to the voltage constraints in the RPM firmware it still ends up applying the correct voltage. To have proper regulator constraints it is important to review them in context of the usage. The current setup in the MSM8916 device trees makes this quite hard because each device duplicates the standard voltages for components of the SoC and mixes those with minor device-specific additions and dummy voltages for completely unused regulators. The actual usage of the regulators for the SoC components is in msm8916-pm8916.dtsi, so it can and should also define the related voltage constraints. These are not board-specific but defined in the APQ8016E/PM8916 Device Specification. The board DT can then focus on describing the actual board-specific regulators, which makes it much easier to review and spot potential mistakes there. Note that this commit does not make any functional change. All used regulators still have the same regulator constraints as before. Unused regulators do not have regulator constraints anymore because most of these were too broad or even entirely wrong. They should be added back with proper voltage constraints when there is an actual usage. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-7-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 153 ++++-------------- .../boot/dts/qcom/msm8916-acer-a1-724.dts | 115 ++----------- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 110 +------------ .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 110 +------------ .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 110 +------------ .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 120 ++------------ .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 110 +------------ .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 110 +------------ arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 102 +++++++++--- .../qcom/msm8916-samsung-a2015-common.dtsi | 110 +------------ .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 110 +------------ .../dts/qcom/msm8916-samsung-j5-common.dtsi | 103 ------------ .../dts/qcom/msm8916-samsung-serranove.dts | 103 ------------ arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 103 ------------ .../dts/qcom/msm8916-wingtech-wt88047.dts | 119 ++------------ 15 files changed, 210 insertions(+), 1478 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 7d7af6406c393..ab8dfd858025c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -329,6 +329,40 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + /* + * The 96Boards specification expects a 1.8V power rail on the low-speed + * expansion connector that is able to provide at least 0.18W / 100 mA. + * L15/L16 are connected in parallel to provide 55 mA each. A minimum load + * must be specified to ensure the regulators are not put in LPM where they + * would only provide 5 mA. + */ + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <50000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pm8916_s4 { + regulator-always-on; + regulator-boot-on; +}; + &sdhc_1 { status = "okay"; @@ -446,125 +480,6 @@ &wcnss_iris { &stm { status = "okay"; }; &tpiu { status = "okay"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - /* - * The 96Boards specification expects a 1.8V power rail on the low-speed - * expansion connector that is able to provide at least 0.18W / 100 mA. - * L15/L16 are connected in parallel to provide 55 mA each. A minimum load - * must be specified to ensure the regulators are not put in LPM where they - * would only provide 5 mA. - */ - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <50000>; - regulator-allow-set-load; - regulator-always-on; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <50000>; - regulator-allow-set-load; - regulator-always-on; - }; - - l17 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - /* * 2mA drive strength is not enough when connecting multiple * I2C devices with different pull up resistors. diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 0d517804e44ed..753413b48751a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -114,6 +114,18 @@ &pm8916_resin { status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -153,109 +165,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_int_default: accel-int-default-state { pins = "gpio115"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index ddd64cc469983..4bfbad669b1ea 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -156,6 +156,13 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -195,109 +202,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_int_default: accel-int-default-state { pins = "gpio31"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 982457503a3cc..37755e8853958 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -128,6 +128,13 @@ &blsp1_uart2 { status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &sdhc_1 { status = "okay"; @@ -163,109 +170,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio117"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 9584d271c5260..4a6bf99c755fd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -114,6 +114,13 @@ &pm8916_resin { status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -153,109 +160,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 8197710372ad1..29aaa35438a36 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -222,11 +222,28 @@ &lpass_codec { status = "okay"; }; +&pm8916_l8 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; +}; + &pm8916_resin { status = "okay"; linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -321,109 +338,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_irq_default: accel-irq-default-state { pins = "gpio115"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 68d1b76aaf772..b7b1f1ceaf1f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -223,6 +223,13 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_usbin { status = "okay"; }; @@ -267,109 +274,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_int_default: accel-int-default-state { pins = "gpio116"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 1e0c08770371a..630727ed1ed5a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -110,6 +110,13 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -149,109 +156,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { button_backlight_default: button-backlight-default-state { pins = "gpio17"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 29ef46c333506..b38eecbd62538 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -61,30 +61,92 @@ &wcnss_iris { }; &rpm_requests { - smd_rpm_regulators: regulators { + pm8916_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; + pm8916_s3: s3 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; + }; + + /* + * Some of the regulators are unused or managed by another + * processor (e.g. the modem). We should still define nodes for + * them to ensure the vote from the application processor can be + * dropped in case the regulators are already on during boot. + * + * The labels for these nodes are omitted on purpose because + * boards should configure a proper voltage before using them. + */ + l1 {}; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; + + l4 {}; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 {}; + + pm8916_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 {}; + l15 {}; + l16 {}; + l17 {}; + l18 {}; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index b362a76eebc94..37a872949851b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -252,6 +252,13 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &sdhc_1 { status = "okay"; @@ -279,109 +286,6 @@ &usb_hs_phy { extcon = <&muic>; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_int_default: accel-int-default-state { pins = "gpio115"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 4464beeeaab12..a49e1641e59b8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -120,6 +120,13 @@ &pm8916_resin { status = "okay"; }; +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + /* FIXME: Replace with MAX77849 MUIC when driver is available */ &pm8916_usbin { status = "okay"; @@ -162,109 +169,6 @@ &wcnss_iris { compatible = "qcom,wcn3660b"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { accel_int_default: accel-int-default-state { pins = "gpio115"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index 6e231e92e6756..6192d04a58ae4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -128,109 +128,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { gpio_hall_sensor_default: gpio-hall-sensor-default-state { pins = "gpio52"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index fa5b330aaeaee..fc4c61c4e1e6c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -320,109 +320,6 @@ &wcnss_iris { compatible = "qcom,wcn3660b"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { fg_alert_default: fg-alert-default-state { pins = "gpio121"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 259c4660bb0fc..6a92190395720 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -126,109 +126,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { /* pins are board-specific */ button_default: button-default-state { diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 78020a0db4e48..323590598113b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -149,6 +149,22 @@ &pm8916_resin { linux,code = ; }; +&pm8916_rpm_regulators { + pm8916_l16: l16 { + /* + * L16 is only used for AW2013 which is fine with 2.5-3.3V. + * Use the recommended typical voltage of 2.8V as minimum. + */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + &pm8916_vib { status = "okay"; }; @@ -188,109 +204,6 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &msmgpio { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; -- GitLab From 8bbd35771f903a9d14fe95bcba8c7b9f07aeb958 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 17 May 2023 20:48:47 +0200 Subject: [PATCH 330/926] arm64: dts: qcom: msm8916-pm8916: Mark always-on regulators Some of the regulators must be always-on to ensure correct operation of the system, e.g. PM8916 L2 for the LPDDR RAM, L5 for most digital I/O and L7 for the CPU PLL (strictly speaking the CPU PLL might only need an active-only vote but this is not supported for regulators in mainline currently). The RPM firmware seems to enforce that internally, these supplies stay on even if we vote for them to power off (and there is no other processor running). This means it's pointless to keep sending enable/disable requests because they will just be ignored. Also, drivers are much more likely to get a wrong impression of the regulator status, because regulator_is_enabled() will return false when there are no users, even though the regulator is always on. Describe this properly by marking the regulators as always-on. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510-msm8916-regulators-v1-8-54d4960a05fc@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 5 ----- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index ab8dfd858025c..1c5d558548932 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -358,11 +358,6 @@ pm8916_l17: l17 { }; }; -&pm8916_s4 { - regulator-always-on; - regulator-boot-on; -}; - &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index b38eecbd62538..64d7228bee07d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -72,11 +72,13 @@ pm8916_rpm_regulators: regulators { pm8916_s3: s3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <1350000>; + regulator-always-on; /* Needed for L2 */ }; pm8916_s4: s4 { regulator-min-microvolt = <1850000>; regulator-max-microvolt = <2150000>; + regulator-always-on; /* Needed for L5/L7 */ }; /* @@ -93,6 +95,7 @@ pm8916_s4: s4 { pm8916_l2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; /* Needed for LPDDR RAM */ }; /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ @@ -102,6 +105,7 @@ pm8916_l2: l2 { pm8916_l5: l5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for most digital I/O */ }; pm8916_l6: l6 { @@ -112,6 +116,7 @@ pm8916_l6: l6 { pm8916_l7: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for CPU PLL */ }; pm8916_l8: l8 { -- GitLab From b5de1a9ff1f2f90c7c1b9b243e754fea6ce1a8e1 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 18 May 2023 13:30:31 +0530 Subject: [PATCH 331/926] arm64: dts: qcom: sm6115: Add CPU idle-states Add CPU idle-state nodes and power-domains in Qualcomm sm6115 SoC dtsi. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230518080031.2509250-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 136 +++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 94623fba0d56f..eec543925d355 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -47,6 +47,8 @@ CPU0: cpu@0 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -63,6 +65,8 @@ CPU1: cpu@1 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -75,6 +79,8 @@ CPU2: cpu@2 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -87,6 +93,8 @@ CPU3: cpu@3 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; CPU4: cpu@100 { @@ -99,6 +107,8 @@ CPU4: cpu@100 { dynamic-power-coefficient = <282>; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -115,6 +125,8 @@ CPU5: cpu@101 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; }; CPU6: cpu@102 { @@ -127,6 +139,8 @@ CPU6: cpu@102 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; }; CPU7: cpu@103 { @@ -139,6 +153,8 @@ CPU7: cpu@103 { enable-method = "psci"; next-level-cache = <&L2_1>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; }; cpu-map { @@ -178,6 +194,68 @@ core3 { }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <297>; + exit-latency-us = <324>; + min-residency-us = <1110>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { + /* GDHS */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40000022>; + entry-latency-us = <360>; + exit-latency-us = <421>; + min-residency-us = <782>; + }; + + CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { + /* Power Collapse */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + + CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { + /* GDHS */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x40000042>; + entry-latency-us = <314>; + exit-latency-us = <345>; + min-residency-us = <660>; + }; + + CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { + /* Power Collapse */ + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <640>; + exit-latency-us = <1654>; + min-residency-us = <8094>; + }; + }; }; firmware { @@ -201,6 +279,64 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_0_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_1_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_0_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; + }; + + CLUSTER_1_PD: power-domain-cpu-cluster1 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; + }; }; reserved_memory: reserved-memory { -- GitLab From 9139bb56734a14c156d3ef736c22a06bd1a9d22c Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 18 May 2023 15:31:12 +0200 Subject: [PATCH 332/926] arm64: dts: qcom: pmi8998: add flash LED controller Qualcomm PMIC PMI8998 has a 3 channel flash LED driver which is used by many phones for 1 or 2 flash LEDs. Each LED can be used in flash mode or torch mode. Add the flash LED controller node to PMI8998 DTS. Signed-off-by: Dylan Van Assche Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230518133113.273880-3-me@dylanvanassche.be --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index ffe587f281d8c..08e00819b39d1 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -60,6 +60,12 @@ pmi8998_lpg: pwm { status = "disabled"; }; + pmi8998_flash: led-controller@d300 { + compatible = "qcom,pmi8998-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pmi8998_wled: leds@d800 { compatible = "qcom,pmi8998-wled"; reg = <0xd800>, <0xd900>; -- GitLab From 8587d217ec3c09268d2023758e5fd6dbc3529c2b Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 18 May 2023 15:31:13 +0200 Subject: [PATCH 333/926] arm64: dts: qcom: sdm845-shift-axolotl: enable flash LEDs The SHIFT6mq (axolotl) is an SDM845-based smartphone with 2 flash LEDs. One LED is white, the other one is yellow. Define both LEDs in the DTS so they can be used as flash or torch and enable the flash LED controller to control them in PMI8998. Signed-off-by: Dylan Van Assche Reviewed-by: Konrad Dybcio Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230518133113.273880-4-me@dylanvanassche.be --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 0ad891348e0c3..1eaff964b202a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -554,6 +554,28 @@ led@5 { }; }; +&pmi8998_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>; + led-max-microamp = <100000>; + flash-max-microamp = <1100000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>; + led-max-microamp = <100000>; + flash-max-microamp = <1100000>; + flash-max-timeout-us = <1280000>; + }; +}; + &qup_uart9_rx { drive-strength = <2>; bias-pull-up; -- GitLab From a1f0f2ebb044c7248c3f30b98de0f151505bd4bd Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 23 May 2023 22:41:28 +0200 Subject: [PATCH 334/926] arm64: dts: qcom: Add PMI632 PMIC The PMI632, commonly found on SoCs with SDM632 has various standard functions like ADC, GPIOs, LPG and more. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230414-pmi632-v3-1-079d2cada699@z3ntu.xyz --- arch/arm64/boot/dts/qcom/pmi632.dtsi | 165 +++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmi632.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi new file mode 100644 index 0000000000000..4eb79e0ce40a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2023 Luca Weiss + */ + +#include +#include +#include + +/ { + thermal-zones { + pmi632-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmi632_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@2 { + compatible = "qcom,pmi632", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmi632_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + channel@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + channel@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + channel@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + + channel@7 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "usb_in_i_uv"; + }; + + channel@8 { + reg = ; + qcom,pre-scaling = <1 16>; + label = "usb_in_v_div_16"; + }; + + channel@9 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "chg_temp"; + }; + + channel@4b { + reg = ; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + label = "bat_id"; + }; + + channel@83 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + + channel@84 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vbat_sns"; + }; + }; + + pmi632_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmi632_sdam_7: nvram@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb600 0x100>; + }; + + pmi632_gpios: gpio@c000 { + compatible = "qcom,pmi632-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pmi632_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@3 { + compatible = "qcom,pmi632", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_lpg: pwm { + compatible = "qcom,pmi632-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; -- GitLab From 0c4f10917d22e6f36080617bfe71de1ae854ee58 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 23 May 2023 22:41:29 +0200 Subject: [PATCH 335/926] arm64: dts: qcom: sdm632-fairphone-fp3: Add notification LED The phone features a notification LED connected to the pmi632. Configure the RGB led found on it. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230414-pmi632-v3-2-079d2cada699@z3ntu.xyz --- .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 70e683b7e4fce..301eca9a4f313 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -4,8 +4,10 @@ */ /dts-v1/; +#include #include "sdm632.dtsi" #include "pm8953.dtsi" +#include "pmi632.dtsi" / { model = "Fairphone 3"; @@ -83,6 +85,33 @@ &pm8953_resin { linux,code = ; }; +&pmi632_lpg { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; -- GitLab From aaa3fc4ce98b7b37531c330f975270d27b1179ea Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Wed, 24 May 2023 19:03:37 -0400 Subject: [PATCH 336/926] dt-bindings: arm: qcom: Add missing msm8960 The list of supported 'SoC's didn't include msm8960 even though qcom,msm8960-cdp exists. Signed-off-by: Rudraksha Gupta Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524230338.120619-1-guptarud@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bf356587765b3..4d5d3ec274f3f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -40,6 +40,7 @@ description: | msm8939 msm8953 msm8956 + msm8960 msm8974 msm8976 msm8992 -- GitLab From 8051c8b83ac076ab7f4fc80cff5e7f8cc3b1eefb Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 7 Apr 2023 20:49:01 +0100 Subject: [PATCH 337/926] dt-bindings: vendor-prefixes: Add Square Add vendor prefix for Square (https://squareup.com). Acked-by: Krzysztof Kozlowski Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407194905.611461-2-bryan.odonoghue@linaro.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 82d39ab0231b0..c40c56d8d8412 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1267,6 +1267,8 @@ patternProperties: description: SpinalHDL "^sprd,.*": description: Spreadtrum Communications Inc. + "^square,.*": + description: Square "^ssi,.*": description: SSI Computer Corp "^sst,.*": -- GitLab From 61550c6c156c3715baf54ab2cdd678c8c35b3803 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 7 Apr 2023 20:49:02 +0100 Subject: [PATCH 338/926] arm64: dts: qcom: Add msm8939 SoC Add msm8939 a derivative SoC of msm8916. This SoC contains a number of key differences to msm8916. - big.LITTLE Octa Core - quad 1.5GHz + quad 1.0GHz - DRAM 1x800 LPDDR3 - Camera 4+4 lane CSI - Venus @ 1080p60 HEVC - DSI x 2 - Adreno A405 - WiFi wcn3660/wcn3680b 802.11ac Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Co-developed-by: Jun Nie Signed-off-by: Jun Nie Co-developed-by: Benjamin Li Signed-off-by: Benjamin Li Co-developed-by: James Willcox Signed-off-by: James Willcox Co-developed-by: Leo Yan Signed-off-by: Leo Yan Co-developed-by: Joseph Gates Signed-off-by: Joseph Gates Co-developed-by: Max Chen Signed-off-by: Max Chen Co-developed-by: Zac Crosby Signed-off-by: Zac Crosby Co-developed-by: Vincent Knecht Signed-off-by: Vincent Knecht Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407194905.611461-3-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2452 +++++++++++++++++++++++++ 1 file changed, 2452 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi new file mode 100644 index 0000000000000..778d24c8aee52 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -0,0 +1,2452 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + /* + * Stock LK wants address-cells/size-cells = 2 + * A number of our drivers want address/size cells = 1 + * hence the disparity between top-level and /soc below. + */ + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x100>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x101>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU2: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x102>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU3: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x103>; + next-level-cache = <&L2_1>; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + CPU4: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x0>; + qcom,acc = <&acc4>; + qcom,saw = <&saw4>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x1>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc5>; + qcom,saw = <&saw5>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + CPU6: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x2>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc6>; + qcom,saw = <&saw6>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + CPU7: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x3>; + next-level-cache = <&L2_0>; + qcom,acc = <&acc7>; + qcom,saw = <&saw7>; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible ="qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + }; + + /* + * MSM8939 has a big.LITTLE heterogeneous computing architecture, + * consisting of two clusters of four ARM Cortex-A53s each. The + * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs + * at 1.5-1.7GHz. + * + * The enable method used here is spin-table which presupposes use + * of a 2nd stage boot shim such as lk2nd to have installed a + * spin-table, the downstream non-psci/non-spin-table method that + * default msm8916/msm8936/msm8939 will not be supported upstream. + */ + cpu-map { + /* LITTLE (efficiency) cluster */ + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + /* big (performance) cluster */ + /* Boot CPU is cluster 1 core 0 */ + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8916", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@86680000 { + reg = <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + + qcom,client-id = <1>; + }; + + rfsa@867e0000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + wcnss_mem: wcnss@8bd00000 { + reg = <0x0 0x8bd00000 0x0 0x600000>; + no-map; + }; + + venus_mem: venus@8c300000 { + reg = <0x0 0x8c300000 0x0 0x800000>; + no-map; + }; + + mba_mem: mba@8cb00000 { + reg = <0x0 0x8cb00000 0x0 0x100000>; + no-map; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs1_mbox 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8936"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8939-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + smp2p-hexagon { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs1_mbox 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + }; + }; + + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = ; + + mboxes = <&apcs1_mbox 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs1_mbox 8 13>; + qcom,ipc-3 = <&apcs1_mbox 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_base1: base1@a0 { + reg = <0xa0 0x1>; + bits = <0 8>; + }; + + tsens_s6_p1: s6-p1@a1 { + reg = <0xa1 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@a1 { + reg = <0xa1 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@a2 { + reg = <0xa2 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@a3 { + reg = <0xa3 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@a4 { + reg = <0xa4 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@a4 { + reg = <0xa4 0x2>; + bits = <6 6>; + }; + + tsens_s9_p1: s9-p1@a5 { + reg = <0xa5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2: s9-p2@a6 { + reg = <0xa6 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@a7 { + reg = <0xa7 0x1>; + bits = <0 8>; + }; + + tsens_mode: mode@d0 { + reg = <0xd0 0x1>; + bits = <0 3>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <3 6>; + }; + + tsens_s0_p2: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@d1 { + reg = <0xd1 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@d4 { + reg = <0xd4 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg = <0xd5 0x2>; + bits = <5 6>; + }; + + tsens_s5_p1: s5-p1@d6 { + reg = <0xd6 0x2>; + bits = <3 6>; + }; + + tsens_s5_p2: s5-p2@d7 { + reg = <0xd7 0x1>; + bits = <1 6>; + }; + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8939-bimc"; + reg = <0x00400000 0x62000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + #interconnect-cells = <1>; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; + #qcom,sensors = <9>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8939-pcnoc"; + reg = <0x00500000 0x11000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + #interconnect-cells = <1>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8939-snoc"; + reg = <0x00580000 0x14080>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + #interconnect-cells = <1>; + + snoc_mm: interconnect-snoc { + compatible = "qcom,msm8939-snoc-mm"; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>, + <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; + #interconnect-cells = <1>; + }; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst-pins { + pins = "gpio28"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + mclk1-pins { + pins = "gpio27"; + function = "cam_mclk1"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins = "gpio34"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + mclk0-pins { + pins = "gpio26"; + function = "cam_mclk0"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + cdc_pdm_lines_default: pdm-lines-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; + + cdc_pdm_lines_sleep: pdm-lines-suspend-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; + }; + + cdc_dmic_lines_act: cdc-dmic-lines-on-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <8>; + }; + + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <8>; + }; + }; + + cdc_dmic_lines_sus: cdc-dmic-lines-off-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <2>; + bias-disable; + }; + + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <2>; + bias-disable; + }; + }; + + ext-mclk-tlmm-lines-state { + ext_mclk_tlmm_lines_act: mclk-lines-on-pins { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + }; + + ext-pri-tlmm-lines-state { + ext_pri_tlmm_lines_act: ext-pa-on-pins { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + ext_pri_tlmm_lines_sus: ext-pa-off-pins { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + }; + + ext-pri-ws-line-state { + ext_pri_ws_act: ext-pa-on-pins { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + + ext_pri_ws_sus: ext-pa-off-pins { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* secondary Mi2S */ + ext-sec-tlmm-lines-state { + ext_sec_tlmm_lines_act: tlmm-lines-on-pins { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c1_default: i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c2_default: i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c3_default: i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c5_default: i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c6_default: i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c6_sleep: i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_default_state: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_sleep_state: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + cd-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + cd-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + spi1_default: spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi1_sleep: spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + spi2_default: spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi2_sleep: spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + spi3_default: spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi3_sleep: spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + spi4_default: spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi4_sleep: spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + spi5_default: spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi5_sleep: spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + spi6_default: spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi6_sleep: spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wcnss_pin_a: wcnss-active-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8939"; + reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi_phy0 1>, + <&dsi_phy0 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + interrupts = ; + interrupt-controller; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + status = "disabled"; + + mdp: display-controller@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 4>; + + interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, + <&dsi_phy0 1>; + + phys = <&dsi_phy0>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + + dsi1: dsi@1aa0000 { + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x01aa0000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks = <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, + <&dsi_phy0 1>; + phys = <&dsi_phy1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi_phy1: phy@1aa0300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01aa0300 0xd4>, + <0x01aa0500 0x280>, + <0x01aa0780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-405.0", "qcom,adreno"; + reg = <0x01c00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + }; + + apps_iommu: iommu@1ef0000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + reg = <0x01ef0000 0x3000>; + ranges = <0 0x01e20000 0x40000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <17>; + + /* mdp_0: */ + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + /* venus_ns: */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GFX_TBU_CLK>; + clock-names = "iface", "bus", "tbu"; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <18>; + + /* gfx3d_user: */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + /* gfx3d_priv: */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil"; + reg = <0x04080000 0x100>, <0x04020000 0x040>; + reg-names = "qdsp6", "rmb"; + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "bus", + "mem", + "xo"; + power-domains = <&rpmpd MSM8939_VDDMDCX>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names = "cx", "mx"; + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + resets = <&scm 0>; + reset-names = "mss_restart"; + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = ; + + qcom,smd-edge = <0>; + mboxes = <&apcs1_mbox 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; + + sound: sound@7702000 { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, + <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + status = "disabled"; + }; + + lpass: audio-controller@7708000 { + compatible = "qcom,apq8016-lpass-cpu"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; + clock-names = "ahbix-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpass_codec: audio-codec@771c000 { + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + }; + + sdhc_1: mmc@7824900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc", "core"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + bus-width = <4>; + status = "disabled"; + }; + + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c3_default>; + pinctrl-1 = <&i2c3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c4_default>; + pinctrl-1 = <&i2c4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-0 = <&spi6_default>; + pinctrl-1 = <&spi6_sleep>; + pinctrl-names = "default", "sleep"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + #reset-cells = <1>; + phy_type = "ulpi"; + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + #phy-cells = <0>; + qcom,init-seq = /bits/ 8 <0x0 0x44>, + <0x1 0x6b>, + <0x2 0x24>, + <0x3 0x13>; + }; + }; + }; + + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_mem>; + + power-domains = <&rpmpd MSM8939_VDDCX>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs1_mbox 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, + <0x0b001000 0x1000>, <0x0b004000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + apcs1_mbox: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + assigned-clocks = <&apcs2>; + assigned-clock-rates = <297600000>; + #mbox-cells = <1>; + }; + + a53pll_c1: clock@b016000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + }; + + acc0: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b088000 0x1000>; + }; + + saw0: power-manager@b089000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b098000 0x1000>; + }; + + saw1: power-manager@b099000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0a8000 0x1000>; + }; + + saw2: power-manager@b0a9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0b8000 0x1000>; + }; + + saw3: power-manager@b0b9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + }; + + apcs0_mbox: mailbox@b111000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b111000 0x1000>; + clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + + a53pll_c0: clock@b116000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b121000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + acc4: clock-controller@b188000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b188000 0x1000>; + }; + + saw4: power-manager@b189000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b189000 0x1000>; + }; + + acc5: clock-controller@b198000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b198000 0x1000>; + }; + + saw5: power-manager@b199000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b199000 0x1000>; + }; + + acc6: clock-controller@b1a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1a8000 0x1000>; + }; + + saw6: power-manager@b1a9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1a9000 0x1000>; + }; + + acc7: clock-controller@b1b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1b8000 0x1000>; + }; + + saw7: power-manager@b1b9000 { + compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1b9000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b1d0000 0x40>; + #clock-cells = <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b1d1000 0x1000>; + clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4567-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + cpu4567_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4567_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4567_alert>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + gpu_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + modem1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + modem2_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + cam_alert0: trip-point0 { + temperature = <75000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- GitLab From 1e6dfe47ba020a192d743c7c820b469fd7253813 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 7 Apr 2023 20:49:03 +0100 Subject: [PATCH 339/926] arm64: dts: qcom: Add msm8939-pm8916.dtsi include The msm8939-pm8916.dtsi include configures the regulator supplies of MSM8939 used together with PM8916, as recommended by Qualcomm. In rare cases where boards deviate from the recommended design they can just avoid using this include. Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407194905.611461-4-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 82 ++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi new file mode 100644 index 0000000000000..24393a1590580 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8939.dtsi" +#include "pm8916.dtsi" + +&dsi0 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&dsi1 { + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; +}; + +&dsi_phy0 { + vddio-supply = <&pm8916_l6>; +}; + +&dsi_phy1 { + vddio-supply = <&pm8916_l6>; +}; + +&mpss { + pll-supply = <&pm8916_l7>; +}; + +&rpm_requests { + smd_rpm_regulators: regulators { + compatible = "qcom,rpm-pm8916-regulators"; + + /* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */ + /* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */ + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */ + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; +}; + +&sdhc_2 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; +}; + +&usb_hs_phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; +}; + +&wcnss { + vddpx-supply = <&pm8916_l7>; +}; + +&wcnss_iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; +}; -- GitLab From 273a3dc13eb746c7b7abe7ea682811a8dacc89d6 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 7 Apr 2023 20:49:04 +0100 Subject: [PATCH 340/926] arm64: dts: qcom: Add Square apq8039-t2 board The apq8039-t2 is an apq8039 based board paired with a wcn3680b WiFi chipset. Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Co-developed-by: Jun Nie Signed-off-by: Jun Nie Co-developed-by: Benjamin Li Signed-off-by: Benjamin Li Co-developed-by: James Willcox Signed-off-by: James Willcox Co-developed-by: Leo Yan Signed-off-by: Leo Yan Co-developed-by: Joseph Gates Signed-off-by: Joseph Gates Co-developed-by: Max Chen Signed-off-by: Max Chen Co-developed-by: Zac Crosby Signed-off-by: Zac Crosby Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407194905.611461-5-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/apq8039-t2.dts | 492 ++++++++++++++++++++++++ 2 files changed, 493 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/apq8039-t2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 063c41a0aebc3..6f3bd9327bf33 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts new file mode 100644 index 0000000000000..e75ee34cb014b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include +#include +#include + +/ { + model = "Square, Inc. T2 Devkit"; + compatible = "square,apq8039-t2", "qcom,msm8939"; + + qcom,board-id = <0x53 0x54>; + qcom,msm-id = ; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp1_uart1; + serial1 = &blsp1_uart2; + }; + + bl: backlight { + compatible = "gpio-backlight"; + pinctrl-0 = <&pinctrl_backlight>; + pinctrl-names = "default"; + gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + vreg_lcd_avdd_reg: lcd-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avdd"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-0 = <&pinctrl_lcd_avdd_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + vreg_lcd_avee_reg: lcd-avee-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avee"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-0 = <&pinctrl_lcd_avee_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + vreg_lcd_iovcc_reg: lcd-iovcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_iovcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-0 = <&pinctrl_lcd_iovcc_reg>; + pinctrl-names = "default"; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; +}; + +&blsp_i2c1 { + status = "okay"; +}; + +&blsp_i2c2 { + status = "okay"; +}; + +&blsp_i2c3 { + status = "okay"; + + typec_pd: usb-pd@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + pinctrl-names = "default"; + pinctrl-0 = <&typec_irq>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + typec_ep: endpoint { + remote-endpoint = <&otg_ep>; + }; + }; + }; + }; +}; + +&blsp_i2c5 { + status = "okay"; +}; + +&blsp1_uart1 { + status = "okay"; +}; + +&blsp1_uart1_default { + pins = "gpio0", "gpio1"; +}; + +&blsp1_uart1_sleep { + pins = "gpio0", "gpio1"; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "PM_GPIO1", /* WIFI_GPIO1_PRE */ + "PM_GPIO2", /* WIFI_GPIO2_PRE */ + "PM_GPIO3", + "PM_GPIO4"; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + /* l1 is fixed to 1225000, but not connected in schematic */ + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_default_state>; + pinctrl-1 = <&sdc1_sleep_state>; + status = "okay"; +}; + +&sound { + model = "apq8039-square-sndcard"; + audio-routing = "AMIC2", "MIC BIAS Internal2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cdc_pdm_lines_default>; + pinctrl-1 = <&cdc_pdm_lines_sleep>; + + internal-codec-playback-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + +/* + * Line names are taken from the schematic of T2, Ver X03. + * July 14, 2018. Page 4 in particular. + */ +&tlmm { + gpio-line-names = + "APQ_UART1_TX", /* GPIO_0 */ + "APQ_UART1_RX", + "APQ_I2C1_SDA", + "APQ_I2C1_SCL", + "APQ_UART2_TX_1V8", + "APQ_UART2_RX_1V8", + "APQ_I2C2_SDA", + "APQ_I2C2_SCL", + "NC", + "APQ_LCD_IOVCC_EN", + "APQ_I2C3_SDA", /* GPIO_10 */ + "APQ_I2C3_SCL", + "TOUCH_RST_1V8_L", + "NC", + "APQ_I2C4_SDA", + "APQ_I2C4_SCL", + "APQ_ID5", + "USB_DISCONNECT", + "APQ_I2C5_SDA", + "APQ_I2C5_SCL", + "APQ_USBC_SPI_MOSI", /* GPIO_20 */ + "APQ_USBC_SPI_MISO", + "APQ_USBC_SPI_SS_L", + "APQ_USBC_SPI_CLK", + "APQ_LCD_TE0", + "APQ_LCD_RST_L", + "NC", + "NC", + "ACCELEROMETER_INT1", + "APQ_CAM_I2C0_SDA", + "APQ_CAM_I2C0_SCL", /* GPIO_30 */ + "ACCELEROMETER_INT2", + "NC", + "NC", + "NC", + "APQ_K21_RST_1V8_L", + "NC", + "APQ_EDL_1V8", + "TP145", + "BT_SSBI", + "NC", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "BT_CTRL", + "BT_DAT", + "PWR_GPIO_IN", + "PWR_GPIO_OUT", /* GPIO_50 */ + "CARD_DET_MLB_L", + "HALL_SENSOR", + "TP63", + "TP64", + "TP65", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "APQ_K21_GPIO0_1V8", + "CDC_PDM_CLK", + "CDC_PDM_SYNC", + "CDC_PDM_TX", + "CDC_PDM_RX0", + "CDC_PDM_RX1", + "CDC_PDM_RX2", + "APQ_K21_GPIO1_1V8", + "NC", /* GPIO_70 */ + "APQ_HUB_SEL_1V8", + "APQ_K21_GPIO2_1V8", + "APQ_K21_GPIO3_1V8", + "APQ_ID0", + "APQ_ID1", + "APQ_ID2", + "APQ_ID3", + "APQ_ID4", + "APQ_HUB_SUSP_IND", + "BOOT_CONFIG_0", /* GPIO_80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "APQ_LCD_AVDD_EN", + "APQ_LCD_AVEE_EN", + "TP70", + "NC", + "APQ_DEBUG0", /* GPIO_90 */ + "APQ_DEBUG1", + "APQ_DEBUG2", + "APQ_DEBUG3", + "TP165", + "NC", + "APQ_LNA_PWR_EN", + "NC", + "APQ_LCD_BL_EN", + "NC", + "APQ_LCD_ID0", /* GPIO_100 */ + "APQ_LCD_ID1", + "USBC_GPIO5_1V8", + "NC", + "NC", + "NC", + "APQ_HUB_RST_1V8_L", + "USBC_I2C_IRQ_1V8_L", + "SPE_PWR_EN", + "NC", + "APQ_USB_ID", /* GPIO_110 */ + "APQ_EXT_BUCK_VSEL", + "APQ_USB_ID_OUT", + "NC", + "PRNT_RST_L", + "APQ_CRQ_I2C_RDY_1V8", + "TYPEC_RST_1V8_H", + "CHG_BACKPWR_EN", + "CHG_PROCHOT_L", + "NC", + "USBC_GPIO7_1V8", /* GPIO_120 */ + "NC"; + + pinctrl_backlight: backlight-state { + pins = "gpio98"; + function = "gpio"; + }; + + pinctrl_lcd_avdd_reg: lcd-avdd-reg-state { + pins = "gpio86"; + function = "gpio"; + }; + + pinctrl_lcd_avee_reg: lcd-avee-reg-state { + pins = "gpio87"; + function = "gpio"; + }; + + pinctrl_lcd_iovcc_reg: lcd-iovcc-reg-state { + pins = "gpio9"; + function = "gpio"; + }; + + pinctrl_lcd_rst: lcd-rst-state { + pins = "gpio25"; + function = "gpio"; + }; + + pinctrl_otg_default: otg-default-state { + function = "gpio"; + pins = "gpio17"; + output-high; + }; + + pinctrl_otg_device: otg-device-state { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + pinctrl_otg_host: otg-host-state { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + typec_irq: typec-irq-state { + function = "gpio"; + pins = "gpio107"; + bias-pull-up; + input-enable; + }; +}; + +&usb { + pinctrl-names = "default", "host", "device"; + pinctrl-0 = <&pinctrl_otg_default>; + pinctrl-1 = <&pinctrl_otg_host>; + pinctrl-2 = <&pinctrl_otg_device>; + pin-switch-delay-us = <100000>; + usb-role-switch; + status = "okay"; + + port { + otg_ep: endpoint { + remote-endpoint = <&typec_ep>; + }; + }; +}; + +&wcd_codec { + qcom,hphl-jack-type-normally-open; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3680"; +}; -- GitLab From f1134f738fad68c51a44216ab0f68a0f086a1a5e Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 7 Apr 2023 20:49:05 +0100 Subject: [PATCH 341/926] arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua Add a basic booting DTS for the Sony Xperia M4 Aqua aka "tulip". Tulip is paired with: - wcn3660 - smb1360 battery charger - 720p Truly NT35521 Panel Reviewed-by: Konrad Dybcio Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407194905.611461-6-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 183 ++++++++++++++++++ 2 files changed, 184 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f3bd9327bf33..f8e8a4a416cbd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts new file mode 100644 index 0000000000000..951d01674b784 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Bryan O'Donoghue. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include +#include + +/ { + model = "Sony Xperia M4 Aqua"; + compatible = "sony,kanuti-tulip", "qcom,msm8939"; + + qcom,board-id = ; + qcom,msm-id = , ; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&tlmm { + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_default_state>; + pinctrl-1 = <&sdc1_sleep_state>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default_state>; + pinctrl-1 = <&sdc2_sleep_state>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660"; +}; -- GitLab From 42d5b302bf1807af46f65b97bb6c8652d0e12782 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sat, 20 May 2023 13:26:00 +0200 Subject: [PATCH 342/926] dt-bindings: arm: bcm: unify version notation of Northstar devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always use a minus/hyphen char to separate model from version. This unifies binding's "compatible" strings. Signed-off-by: Rafał Miłecki Reviewed-by: Linus Walleij Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230520112601.11821-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- .../devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 454b0e93245d8..cc34025fdc787 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -28,10 +28,10 @@ properties: - buffalo,wzr-1750dhp - linksys,ea6300-v1 - linksys,ea6500-v2 - - luxul,xap-1510v1 + - luxul,xap-1510-v1 - luxul,xwc-1000 - - netgear,r6250v1 - - netgear,r6300v2 + - netgear,r6250-v1 + - netgear,r6300-v2 - smartrg,sr400ac - brcm,bcm94708 - const: brcm,bcm4708 @@ -42,8 +42,8 @@ properties: - asus,rt-n18u - buffalo,wzr-600dhp2 - buffalo,wzr-900dhp - - luxul,xap-1410v1 - - luxul,xwr-1200v1 + - luxul,xap-1410-v1 + - luxul,xwr-1200-v1 - tplink,archer-c5-v2 - const: brcm,bcm47081 - const: brcm,bcm4708 @@ -72,7 +72,7 @@ properties: - luxul,xap-1610-v1 - luxul,xbr-4500-v1 - luxul,xwc-2000-v1 - - luxul,xwr-3100v1 + - luxul,xwr-3100-v1 - luxul,xwr-3150-v1 - netgear,r8500 - phicomm,k3 -- GitLab From 9d7121f1d2faa0b50bf5b462adcd2dd91970c45e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sat, 20 May 2023 13:26:01 +0200 Subject: [PATCH 343/926] ARM: dts: BCM5301X: Use updated device "compatible" strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Northstar binding was updated to use minus/hyphen char between model and version for all devices. Signed-off-by: Rafał Miłecki Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20230520112601.11821-2-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 2 +- arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 2 +- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 2 +- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 2 +- arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 9b98a0179f055..5d0549855978d 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -8,7 +8,7 @@ #include "bcm4708.dtsi" / { - compatible = "luxul,xap-1510v1", "brcm,bcm4708"; + compatible = "luxul,xap-1510-v1", "brcm,bcm4708"; model = "Luxul XAP-1510 V1"; chosen { diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 89155caf50bef..8661ec94ca672 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -13,7 +13,7 @@ #include "bcm5301x-nand-cs0-bch8.dtsi" / { - compatible = "netgear,r6250v1", "brcm,bcm4708"; + compatible = "netgear,r6250-v1", "brcm,bcm4708"; model = "Netgear R6250 V1 (BCM4708)"; chosen { diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 57d00a0b4765a..77396730bdd3e 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -12,7 +12,7 @@ #include "bcm5301x-nand-cs0-bch8.dtsi" / { - compatible = "netgear,r6300v2", "brcm,bcm4708"; + compatible = "netgear,r6300-v2", "brcm,bcm4708"; model = "Netgear R6300 V2 (BCM4708)"; chosen { diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index edc1940859957..7e042928fd40e 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -8,7 +8,7 @@ #include "bcm47081.dtsi" / { - compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708"; + compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708"; model = "Luxul XAP-1410 V1"; chosen { diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 97b61d9d4be9e..231d437408d8b 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -9,7 +9,7 @@ #include "bcm5301x-nand-cs0-bch4.dtsi" / { - compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708"; + compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708"; model = "Luxul XWR-1200 V1"; chosen { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index ebea188bd2d75..52783a4b6f999 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -9,7 +9,7 @@ #include "bcm5301x-nand-cs0-bch4.dtsi" / { - compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; + compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708"; model = "Luxul XWR-3100 V1"; chosen { -- GitLab From 47e75a4aaf97e562444eddcbfc77955f3f0e8013 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 23 May 2023 09:52:35 +0300 Subject: [PATCH 344/926] arm64: dts: broadcom: Unify pinctrl-single pin group nodes for stingray We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20230523065236.14524-1-tony@atomide.com Signed-off-by: Florian Fainelli --- .../broadcom/stingray/stingray-pinctrl.dtsi | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 56789ccf94545..46a8275219215 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -44,7 +44,7 @@ pinmux: pinmux@14029c { compatible = "pinctrl-single"; reg = <0x0014029c 0x26c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xf>; pinctrl-single,gpio-range = < @@ -56,14 +56,14 @@ range: gpio-range { }; /* pinctrl functions */ - tsio_pins: pinmux_gpio_14 { + tsio_pins: gpio-14-pins { pinctrl-single,pins = < 0x038 MODE_NITRO /* tsio_0 */ 0x03c MODE_NITRO /* tsio_1 */ >; }; - nor_pins: pinmux_pnor_adv_n { + nor_pins: pnor-adv-n-pins { pinctrl-single,pins = < 0x0ac MODE_PNOR /* nand_ce1_n */ 0x0b0 MODE_PNOR /* nand_ce0_n */ @@ -119,7 +119,7 @@ nor_pins: pinmux_pnor_adv_n { >; }; - nand_pins: pinmux_nand_ce1_n { + nand_pins: nand-ce1-n-pins { pinctrl-single,pins = < 0x0ac MODE_NAND /* nand_ce1_n */ 0x0b0 MODE_NAND /* nand_ce0_n */ @@ -148,59 +148,59 @@ nand_pins: pinmux_nand_ce1_n { >; }; - pwm0_pins: pinmux_pwm_0 { + pwm0_pins: pwm-0-pins { pinctrl-single,pins = < 0x10c MODE_NITRO >; }; - pwm1_pins: pinmux_pwm_1 { + pwm1_pins: pwm-1-pins { pinctrl-single,pins = < 0x110 MODE_NITRO >; }; - pwm2_pins: pinmux_pwm_2 { + pwm2_pins: pwm-2-pins { pinctrl-single,pins = < 0x114 MODE_NITRO >; }; - pwm3_pins: pinmux_pwm_3 { + pwm3_pins: pwm-3-pins { pinctrl-single,pins = < 0x118 MODE_NITRO >; }; - dbu_rxd_pins: pinmux_uart1_sin_nitro { + dbu_rxd_pins: uart1-sin-nitro-pins { pinctrl-single,pins = < 0x11c MODE_NITRO /* dbu_rxd */ 0x120 MODE_NITRO /* dbu_txd */ >; }; - uart1_pins: pinmux_uart1_sin_nand { + uart1_pins: uart1-sin-nand-pins { pinctrl-single,pins = < 0x11c MODE_NAND /* uart1_sin */ 0x120 MODE_NAND /* uart1_out */ >; }; - uart2_pins: pinmux_uart2_sin { + uart2_pins: uart2-sin-pins { pinctrl-single,pins = < 0x124 MODE_NITRO /* uart2_sin */ 0x128 MODE_NITRO /* uart2_out */ >; }; - uart3_pins: pinmux_uart3_sin { + uart3_pins: uart3-sin-pins { pinctrl-single,pins = < 0x12c MODE_NITRO /* uart3_sin */ 0x130 MODE_NITRO /* uart3_out */ >; }; - i2s_pins: pinmux_i2s_bitclk { + i2s_pins: i2s-bitclk-pins { pinctrl-single,pins = < 0x134 MODE_NITRO /* i2s_bitclk */ 0x138 MODE_NITRO /* i2s_sdout */ @@ -211,7 +211,7 @@ i2s_pins: pinmux_i2s_bitclk { >; }; - qspi_pins: pinumx_qspi_hold_n { + qspi_pins: qspi-hold-n-pins { pinctrl-single,pins = < 0x14c MODE_NAND /* qspi_hold_n */ 0x150 MODE_NAND /* qspi_wp_n */ @@ -222,28 +222,28 @@ qspi_pins: pinumx_qspi_hold_n { >; }; - mdio_pins: pinumx_ext_mdio { + mdio_pins: ext-mdio-pins { pinctrl-single,pins = < 0x164 MODE_NITRO /* ext_mdio */ 0x168 MODE_NITRO /* ext_mdc */ >; }; - i2c0_pins: pinmux_i2c0_sda { + i2c0_pins: i2c0-sda-pins { pinctrl-single,pins = < 0x16c MODE_NITRO /* i2c0_sda */ 0x170 MODE_NITRO /* i2c0_scl */ >; }; - i2c1_pins: pinmux_i2c1_sda { + i2c1_pins: i2c1-sda-pins { pinctrl-single,pins = < 0x174 MODE_NITRO /* i2c1_sda */ 0x178 MODE_NITRO /* i2c1_scl */ >; }; - sdio0_pins: pinmux_sdio0_cd_l { + sdio0_pins: sdio0-cd-l-pins { pinctrl-single,pins = < 0x17c MODE_NITRO /* sdio0_cd_l */ 0x180 MODE_NITRO /* sdio0_clk_sdcard */ @@ -262,7 +262,7 @@ sdio0_pins: pinmux_sdio0_cd_l { >; }; - sdio1_pins: pinmux_sdio1_cd_l { + sdio1_pins: sdio1-cd-l-pins { pinctrl-single,pins = < 0x1b4 MODE_NITRO /* sdio1_cd_l */ 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ @@ -281,7 +281,7 @@ sdio1_pins: pinmux_sdio1_cd_l { >; }; - spi0_pins: pinmux_spi0_sck_nand { + spi0_pins: spi0-sck-nand-pins { pinctrl-single,pins = < 0x1ec MODE_NITRO /* spi0_sck */ 0x1f0 MODE_NITRO /* spi0_rxd */ @@ -290,7 +290,7 @@ spi0_pins: pinmux_spi0_sck_nand { >; }; - spi1_pins: pinmux_spi1_sck_nand { + spi1_pins: spi1-sck-nand-pins { pinctrl-single,pins = < 0x1fc MODE_NITRO /* spi1_sck */ 0x200 MODE_NITRO /* spi1_rxd */ @@ -299,14 +299,14 @@ spi1_pins: pinmux_spi1_sck_nand { >; }; - nuart_pins: pinmux_uart0_sin_nitro { + nuart_pins: uart0-sin-nitro-pins { pinctrl-single,pins = < 0x20c MODE_NITRO /* nuart_rxd */ 0x210 MODE_NITRO /* nuart_txd */ >; }; - uart0_pins: pinumux_uart0_sin_nand { + uart0_pins: uart0-sin-nand-pins { pinctrl-single,pins = < 0x20c MODE_NAND /* uart0_sin */ 0x210 MODE_NAND /* uart0_out */ @@ -319,7 +319,7 @@ uart0_pins: pinumux_uart0_sin_nand { >; }; - drdu2_pins: pinmux_drdu2_overcurrent { + drdu2_pins: drdu2-overcurrent-pins { pinctrl-single,pins = < 0x22c MODE_NITRO /* drdu2_overcurrent */ 0x230 MODE_NITRO /* drdu2_vbus_ppc */ @@ -328,7 +328,7 @@ drdu2_pins: pinmux_drdu2_overcurrent { >; }; - drdu3_pins: pinmux_drdu3_overcurrent { + drdu3_pins: drdu3-overcurrent-pins { pinctrl-single,pins = < 0x23c MODE_NITRO /* drdu3_overcurrent */ 0x240 MODE_NITRO /* drdu3_vbus_ppc */ @@ -337,7 +337,7 @@ drdu3_pins: pinmux_drdu3_overcurrent { >; }; - usb3h_pins: pinmux_usb3h_overcurrent { + usb3h_pins: usb3h-overcurrent-pins { pinctrl-single,pins = < 0x24c MODE_NITRO /* usb3h_overcurrent */ 0x250 MODE_NITRO /* usb3h_vbus_ppc */ -- GitLab From 1bd2339df1b545b544283f7b896ef651d93e32cf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 May 2023 15:27:24 +0200 Subject: [PATCH 345/926] dt-bindings: timer: sifive,clint: Clean up compatible value section Replace the sentences in the description listing some supported variants by comments on the individual compatible values, to ease future maintenance. While at it, restore alphabetical sort order. Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../bindings/timer/sifive,clint.yaml | 21 +++++++------------ 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1b..34a8151067813 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -29,11 +29,11 @@ properties: oneOf: - items: - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - starfive,jh7110-clint - - canaan,k210-clint - - const: sifive,clint0 + - canaan,k210-clint # Canaan Kendryte K210 + - sifive,fu540-c000-clint # SiFive FU540 + - starfive,jh7100-clint # StarFive JH7100 + - starfive,jh7110-clint # StarFive JH7110 + - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: - allwinner,sun20i-d1-clint @@ -45,14 +45,9 @@ properties: description: For the QEMU virt machine only description: - Should be ",-clint" and "sifive,clint". - Supported compatible strings are - - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated - onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and - "sifive,clint0" for the SiFive CLINT v0 IP block with no chip - integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details + Should be ",-clint", followed by "sifive,clint" + when compatible with a SiFive CLINT. Please refer to + sifive-blocks-ip-versioning.txt for details regarding the latter. reg: maxItems: 1 -- GitLab From b087f59779b00f73738fdf6a63915aabf77c7d39 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 May 2023 15:26:00 +0200 Subject: [PATCH 346/926] dt-bindings: interrupt-controller: sifive,plic: Sort compatible values Restore alphabetical sort order of the supported SiFive-compatible values. Signed-off-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af7..292556cb367de 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -57,10 +57,10 @@ properties: - const: andestech,nceplic100 - items: - enum: + - canaan,k210-plic - sifive,fu540-c000-plic - starfive,jh7100-plic - starfive,jh7110-plic - - canaan,k210-plic - const: sifive,plic-1.0.0 - items: - enum: -- GitLab From 2a7318b2586684e842f58cb7eeada2d8cb5d8151 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 26 May 2023 12:17:27 +0100 Subject: [PATCH 347/926] arm64: tegra: Fix PCIe regulator for Orin Jetson AGX The PCIe slot on the Jetson Orin AGX is not working and PCIe cards are not detected. The regulator for the 3.3V regulator for the PCIe is using the wrong GPIO for turning on the regulator. Fix this by updating the 3.3V regulator to use the correct GPIO. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 2378da324273c..812499918085e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -126,7 +126,7 @@ vdd_3v3_pcie: regulator-vdd-3v3-pcie { regulator-name = "VDD_3V3_PCIE"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>; regulator-boot-on; enable-active-high; }; -- GitLab From 33f2d12d040059bce36dbd8ab9ecc7a580bd4d77 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 25 May 2023 11:42:37 +0200 Subject: [PATCH 348/926] dt-bindings: usb: tegra-xudc: Remove extraneous PHYs The USB device controller on Tegra210 and later supports one USB 2/3 port, so only a single pair of PHYs is needed. Drop any of the extra PHYs from the bindings. Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index e2270ce0c56b2..c6e661e8915ca 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -91,6 +91,7 @@ properties: phys: minItems: 1 + maxItems: 2 description: Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. @@ -99,13 +100,7 @@ properties: minItems: 1 items: - const: usb2-0 - - const: usb2-1 - - const: usb2-2 - - const: usb2-3 - const: usb3-0 - - const: usb3-1 - - const: usb3-2 - - const: usb3-3 avddio-usb-supply: description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. -- GitLab From 83022f6484b11a60dbf9a95a88c7ef8e59c4b19c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 7 Apr 2023 09:45:44 +0200 Subject: [PATCH 349/926] arm64: dts: qcom: pm7250b: add missing spmi-vadc include This file is using definitions from the spmi-vadc header, so we need to include it. Fixes: 11975b9b8135 ("arm64: dts: qcom: Add pm7250b PMIC") Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407-pm7250b-sid-v1-1-fc648478cc25@fairphone.com --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index d709d955a2f5a..daa6f1d30efa0 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Luca Weiss */ +#include #include #include -- GitLab From d9556c5c6c51aad2c2f760ce953735afa9162f94 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 25 Apr 2023 14:10:10 +0530 Subject: [PATCH 350/926] arm64: dts: qcom: ipq9574: rename al02-c7 dts to rdp433 Rename the dts after Reference Design Platform(RDP) to adopt standard naming convention. Acked-by: Konrad Dybcio Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230425084010.15581-7-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} (97%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f8e8a4a416cbd..cddb90978cc1b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -10,7 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts similarity index 97% rename from arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts rename to arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 2c8430197ec0f..2ce8e09e75656 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * IPQ9574 AL02-C7 board device tree source + * IPQ9574 RDP433 board device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. -- GitLab From 84c4a652db1cf764ebaeea56e6e3372cc52bf708 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 6 Apr 2023 11:43:13 +0530 Subject: [PATCH 351/926] arm64: dts: qcom: ipq9574: Add support for APSS clock controller Add the APCS & A73 PLL nodes to support CPU frequency scaling. Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406061314.10916-5-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index fea15f3cf9100..b751d2a5b5b6e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -422,6 +422,24 @@ watchdog: watchdog@b017000 { timeout-sec = <30>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq9574-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a73pll>, <&xo_board_clk>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a73pll: clock@b116000 { + compatible = "qcom,ipq9574-a73pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board_clk>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; -- GitLab From 8cc864a4375dd62023a2880050bf618a225cb907 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Wed, 17 May 2023 22:55:25 +0530 Subject: [PATCH 352/926] arm64: dts: qcom: ipq9574: Add RPM related nodes Add RPM Glink & RPM message RAM nodes to support frequency scaling on IPQ9574. Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517172527.1968-2-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index b751d2a5b5b6e..917a63f8dd039 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -110,12 +110,29 @@ smem@4aa00000 { }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; -- GitLab From 56ba2b3aeb4b76549a7759e79bd44330cd9b885a Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Wed, 17 May 2023 22:55:26 +0530 Subject: [PATCH 353/926] arm64: dts: qcom: ipq9574: Add SMPA1 regulator node Add support for SMPA1 regulator node in IPQ9574. Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517172527.1968-3-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 2ce8e09e75656..2b3ed8d351f70 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -29,6 +29,25 @@ &blsp1_uart2 { status = "okay"; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; -- GitLab From 8f0ae6bc0098f63a008820f80c08b01ea2167da3 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Wed, 17 May 2023 22:55:27 +0530 Subject: [PATCH 354/926] arm64: dts: qcom: ipq9574: Add cpufreq support Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517172527.1968-4-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 917a63f8dd039..f4aa0fa422877 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,8 +6,9 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ -#include +#include #include +#include #include / { @@ -37,6 +38,10 @@ CPU0: cpu@0 { reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -45,6 +50,10 @@ CPU1: cpu@1 { reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -53,6 +62,10 @@ CPU2: cpu@2 { reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -61,6 +74,10 @@ CPU3: cpu@3 { reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -82,6 +99,47 @@ memory@40000000 { reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupts = ; -- GitLab From e3c98aac28bd8964031ebb057cb6e48fc492d256 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Wed, 10 May 2023 16:13:58 +0530 Subject: [PATCH 355/926] dt-bindings: arm: qcom: document AL02-C2 board based on IPQ9574 family Document AL02-C2 (Reference Design Platform 418) board based on IPQ9574 family of SoCs. Signed-off-by: Devi Priya Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510104359.16678-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4d5d3ec274f3f..b6a9a56c1c214 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -86,6 +86,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-al02-c2 ap-al02-c7 ap-mi01.2 ap-mi01.6 @@ -352,6 +353,7 @@ properties: - items: - enum: + - qcom,ipq9574-ap-al02-c2 - qcom,ipq9574-ap-al02-c7 - const: qcom,ipq9574 -- GitLab From d8a83f8d2e730d4e05e8fc8e1faccbee0f95ca12 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Wed, 10 May 2023 16:13:59 +0530 Subject: [PATCH 356/926] arm64: dts: qcom: ipq9574: add support for RDP418 variant Add the initial device tree support for the Reference Design Platform (RDP) 418 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR, eMMC and SMPA1 regulator node. Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230510104359.16678-3-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 124 ++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cddb90978cc1b..75dce9455c9e8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts new file mode 100644 index 0000000000000..2b093e02637ba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP418 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; + compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; -- GitLab From 2e4cd263b97d0254e6bbd88b2feb4df6c4a9ad0d Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 16 May 2023 19:20:12 +0530 Subject: [PATCH 357/926] dt-bindings: arm: qcom: document AL02-C6 board based on IPQ9574 family Document AL02-C6 (Reference Design Platform 449) board based on IPQ9574 family of SoCs. Signed-off-by: Devi Priya Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516135013.3547-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b6a9a56c1c214..bad064b21b729 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -87,6 +87,7 @@ description: | adp ap-al02-c2 + ap-al02-c6 ap-al02-c7 ap-mi01.2 ap-mi01.6 @@ -354,6 +355,7 @@ properties: - items: - enum: - qcom,ipq9574-ap-al02-c2 + - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 - const: qcom,ipq9574 -- GitLab From aa261f13dae60850be30de95c7eb6ffb6059a6b7 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 16 May 2023 19:20:13 +0530 Subject: [PATCH 358/926] arm64: dts: qcom: ipq9574: add support for RDP449 variant Add the initial device tree support for the Reference Design Platform (RDP) 449 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by: Devi Priya Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516135013.3547-3-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts | 80 +++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 75dce9455c9e8..78dedf9f69fe6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts new file mode 100644 index 0000000000000..c8fa54e1a62cc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP449 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6"; + compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; -- GitLab From b866fba43698479fef5dd301313e8a73e28c789e Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Fri, 26 May 2023 21:01:51 +0530 Subject: [PATCH 359/926] dt-bindings: arm: qcom: document AL02-C8 board based on IPQ9574 family Document AL02-C8 (Reference Design Platform 453) board based on IPQ9574 family of SoCs. Signed-off-by: Devi Priya Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526153152.777-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bad064b21b729..1050ef598c3f9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -89,6 +89,7 @@ description: | ap-al02-c2 ap-al02-c6 ap-al02-c7 + ap-al02-c8 ap-mi01.2 ap-mi01.6 cdp @@ -357,6 +358,7 @@ properties: - qcom,ipq9574-ap-al02-c2 - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c8 - const: qcom,ipq9574 - description: Sierra Wireless MangOH Green with WP8548 Module -- GitLab From 8a465494d62215ca531dfa0cde993779a77e61aa Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Fri, 26 May 2023 21:01:52 +0530 Subject: [PATCH 360/926] arm64: dts: qcom: ipq9574: add support for RDP453 variant Add the initial device tree support for the Reference Design Platform (RDP) 453 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526153152.777-3-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 80 +++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 78dedf9f69fe6..4a2e09ec381da 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts new file mode 100644 index 0000000000000..f01de6628c3b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP453 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; + compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; -- GitLab From 8fa13a6e61a799b102b3314c623d27cb8c078d21 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 26 May 2023 18:23:02 +0530 Subject: [PATCH 361/926] dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs Add the QFPROM compatible for IPQ5332, IPQ6018 and IPQ9574 Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526125305.19626-2-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 8d8503dd934b8..076566ef9cc8e 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -18,8 +18,11 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,ipq5332-qfprom + - qcom,ipq6018-qfprom - qcom,ipq8064-qfprom - qcom,ipq8074-qfprom + - qcom,ipq9574-qfprom - qcom,msm8916-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom -- GitLab From 2f34a2aa4c88f4882e3c5df8c9b78f8bbd3f564f Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 26 May 2023 18:23:03 +0530 Subject: [PATCH 362/926] arm64: dts: qcom: ipq5332: add QFPROM node IPQ5332 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526125305.19626-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 12e0e179e139c..47984037f0a54 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -134,6 +134,13 @@ soc@0 { #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + qfprom: efuse@a4000 { + compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x721>; + #address-cells = <1>; + #size-cells = <1>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; -- GitLab From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 26 May 2023 18:23:04 +0530 Subject: [PATCH 363/926] arm64: dts: qcom: ipq6018: add QFPROM node IPQ6018 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Signed-off-by: Kathiravan T Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index d3dee4e4f004f..a629dd5893b39 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -301,6 +301,13 @@ mdio: mdio@90000 { status = "disabled"; }; + qfprom: efuse@a4000 { + compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a4000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + prng: qrng@e3000 { compatible = "qcom,prng-ee"; reg = <0x0 0x000e3000 0x0 0x1000>; -- GitLab From 05e6b82f395c406333253d6c492d884e7f14ef46 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 26 May 2023 18:23:05 +0530 Subject: [PATCH 364/926] arm64: dts: qcom: ipq9574: add QFPROM node IPQ9574 has efuse region to determine the various HW quirks. Lets add the initial support and the individual fuses will be added as they are required. Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526125305.19626-5-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index f4aa0fa422877..988107a9edc45 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -198,6 +198,13 @@ rng: rng@e3000 { clock-names = "core"; }; + qfprom: efuse@a4000 { + compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x5a1>; + #address-cells = <1>; + #size-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; -- GitLab From 31dfb8014f6bbebf06ca5084a072f755d8dd9797 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:02 +0530 Subject: [PATCH 365/926] arm64: dts: qcom: sdm8550: Fix the BAM DMA engine compatible string As per documentation, Qualcomm SM8550 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Reviewed-by: Konrad Dybcio Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 473ab1831ab1b..29b99003d8a9f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1840,7 +1840,7 @@ pcie1_phy: phy@1c0e000 { }; cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; interrupts = ; #dma-cells = <1>; -- GitLab From 20bf3ac438fd2f6f9a98bc5cbddb5024cd31560f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:03 +0530 Subject: [PATCH 366/926] arm64: dts: qcom: sdm845: Fix the slimbam DMA engine compatible string As per documentation, Qualcomm SDM845 SoC supports SLIMBAM DMA engine v1.7.4, so use the correct compatible strings. Reviewed-by: Konrad Dybcio Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b3d00d805ecc3..e55f826709c3a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5212,7 +5212,7 @@ msi-controller@17a40000 { }; slimbam: dma-controller@17184000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; num-channels = <31>; -- GitLab From 61baef687d81ffda97ac26db8f100b5b27069477 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:06 +0530 Subject: [PATCH 367/926] arm64: dts: qcom: sm6115: Add Crypto Engine support Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm6115.dtsi'. Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-8-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index eec543925d355..6ba9cd33960bd 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -797,6 +797,37 @@ usb_hsphy: phy@1613000 { status = "disabled"; }; + cryptobam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01b04000 0x0 0x24000>; + interrupts = ; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + }; + + crypto: crypto@1b3a000 { + compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0 0x01b3a000 0x0 0x6000>; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x94 0x11>, + <&apps_smmu 0x96 0x11>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + }; + qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; reg = <0x0 0x01b40000 0x0 0x7000>; -- GitLab From f7f485f3dc09d21c58f46756a7e6463c29a0f85b Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:07 +0530 Subject: [PATCH 368/926] arm64: dts: qcom: sm8150: Add Crypto Engine support Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8150.dtsi'. Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-9-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2c377d7bb3a26..2a5b2b99968a4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2085,6 +2085,36 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x502 0x0641>, + <&apps_smmu 0x504 0x0011>, + <&apps_smmu 0x506 0x0011>, + <&apps_smmu 0x508 0x0011>, + <&apps_smmu 0x512 0x0000>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x502 0x0641>, + <&apps_smmu 0x504 0x0011>, + <&apps_smmu 0x506 0x0011>, + <&apps_smmu 0x508 0x0011>, + <&apps_smmu 0x512 0x0000>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; -- GitLab From c58be6c87f482b6bdba804ee0a2d7b588e6a2d6a Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:08 +0530 Subject: [PATCH 369/926] arm64: dts: qcom: sm8250: Add Crypto Engine support Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8250.dtsi'. Co-developed-by and Signed-off-by: Vladimir Zapolskiy Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-10-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7bea916900e29..79fad917d142f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2232,6 +2232,38 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x592 0x0000>, + <&apps_smmu 0x598 0x0000>, + <&apps_smmu 0x599 0x0000>, + <&apps_smmu 0x59f 0x0000>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x596 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x592 0x0000>, + <&apps_smmu 0x598 0x0000>, + <&apps_smmu 0x599 0x0000>, + <&apps_smmu 0x59f 0x0000>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- GitLab From f1040a7fe8f069d2259ab3dab9190210005ceb33 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 27 May 2023 00:52:09 +0530 Subject: [PATCH 370/926] arm64: dts: qcom: sm8350: Add Crypto Engine support Add crypto engine (CE) and CE BAM related nodes and definitions to 'sm8350.dtsi'. Co-developed-by and Signed-off-by: Robert Foss [Bhupesh: Switch to '#interconnect-cells = <2>', available since commit 4f287e31ff5f] Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-11-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ae09460462ed8..d2024ba5a754f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1726,6 +1726,28 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm8350-ipa"; -- GitLab From b92b0d2f75820540182e4edf9b57ead7ef344d45 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sat, 27 May 2023 00:52:10 +0530 Subject: [PATCH 371/926] arm64: dts: qcom: sm8450: add crypto nodes Add crypto engine (CE) and CE BAM related nodes and definitions for the SM8450 SoC. Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Neil Armstrong [Bhupesh: Corrected the compatible list] Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526192210.3146896-12-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f853032e89daa..ca147bad902b2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4189,6 +4189,34 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x584 0x11>, + <&apps_smmu 0x588 0x0>, + <&apps_smmu 0x598 0x5>, + <&apps_smmu 0x59a 0x0>, + <&apps_smmu 0x59f 0x0>; + }; + + crypto: crypto@1de0000 { + compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x584 0x11>, + <&apps_smmu 0x588 0x0>, + <&apps_smmu 0x598 0x5>, + <&apps_smmu 0x59a 0x0>, + <&apps_smmu 0x59f 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; -- GitLab From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Fri, 26 May 2023 16:36:52 +0530 Subject: [PATCH 372/926] arm64: dts: qcom: enable the download mode support Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Add support for the same. Signed-off-by: Vignesh Viswanathan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a629dd5893b39..e21e36e192145 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -90,6 +90,7 @@ L2_0: l2-cache { firmware { scm { compatible = "qcom,scm-ipq6018", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 6b3fc4ac13205..695ad1fece008 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -102,6 +102,7 @@ memory@4ac00000 { firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; @@ -381,6 +382,11 @@ tcsr_mutex: hwlock@1905000 { #hwlock-cells = <1>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq8074", "syscon"; + reg = <0x01937000 0x21000>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, -- GitLab From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Fri, 26 May 2023 16:36:53 +0530 Subject: [PATCH 373/926] arm64: dts: qcom: add few more reserved memory region In IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable. Signed-off-by: Vignesh Viswanathan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++--- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++-- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index e21e36e192145..ee570d22e32b1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -155,18 +155,28 @@ rpm_msg_ram: memory@60000 { no-map; }; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz: memory@4a600000 { - reg = <0x0 0x4a600000 0x0 0x00400000>; + reg = <0x0 0x4a600000 0x0 0x400000>; no-map; }; smem_region: memory@4aa00000 { - reg = <0x0 0x4aa00000 0x0 0x00100000>; + reg = <0x0 0x4aa00000 0x0 0x100000>; no-map; }; q6_region: memory@4ab00000 { - reg = <0x0 0x4ab00000 0x0 0x05500000>; + reg = <0x0 0x4ab00000 0x0 0x5500000>; no-map; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 695ad1fece008..8a053c9486c57 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -85,17 +85,27 @@ reserved-memory { #size-cells = <2>; ranges; + bootloader@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + + sbl@4aa00000 { + reg = <0x0 0x4aa00000 0x0 0x100000>; + no-map; + }; + smem@4ab00000 { compatible = "qcom,smem"; - reg = <0x0 0x4ab00000 0x0 0x00100000>; + reg = <0x0 0x4ab00000 0x0 0x100000>; no-map; hwlocks = <&tcsr_mutex 0>; }; memory@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x400000>; no-map; - reg = <0x0 0x4ac00000 0x0 0x00400000>; }; }; -- GitLab From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:25 +0200 Subject: [PATCH 374/926] arm64: dts: qcom: ipq6018: drop incorrect SPI bus spi-max-frequency The spi-max-frequency property belongs to SPI devices, not SPI controller: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index ee570d22e32b1..1c41169efc65e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -458,7 +458,6 @@ blsp1_spi1: spi@78b5000 { #size-cells = <0>; reg = <0x0 0x078b5000 0x0 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -473,7 +472,6 @@ blsp1_spi2: spi@78b6000 { #size-cells = <0>; reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; -- GitLab From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:26 +0200 Subject: [PATCH 375/926] arm64: dts: qcom: ipq8074: drop incorrect SPI bus spi-max-frequency The spi-max-frequency property belongs to SPI devices, not SPI controller: ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 8a053c9486c57..40565ce635dd9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -491,7 +491,6 @@ blsp1_spi1: spi@78b5000 { #size-cells = <0>; reg = <0x078b5000 0x600>; interrupts = ; - spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; -- GitLab From 395aba1b1912d059a13345531fd4090caf51da38 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:27 +0200 Subject: [PATCH 376/926] arm64: dts: qcom: qdu1000: add missing qcom,smmu-500 fallback Since commit 6c84bbd103d8 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback: ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too short ['qcom,qdu1000-smmu-500', 'arm,mmu-500'] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 734438113bbae..bc16d12432c11 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1103,7 +1103,7 @@ qup_spi15_cs: qup-spi15-cs-state { }; apps_smmu: iommu@15000000 { - compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; + compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; -- GitLab From 2438aba45f65b723763299a7b34eddfc40923680 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:28 +0200 Subject: [PATCH 377/926] arm64: dts: qcom: sm8250: add missing qcom,smmu-500 fallback Since commit 6c84bbd103d8 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback: ['qcom,sm8250-smmu-500', 'qcom,adreno-smmu', 'qcom,smmu-500', 'arm,mmu-500'] is too long 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,msm8998-smmu-v2', 'qcom,sdm630-smmu-v2'] 'qcom,sm8250-smmu-500' is not one of ['qcom,msm8996-smmu-v2', 'qcom,sc7180-smmu-v2', 'qcom,sdm630-smmu-v2', 'qcom,sdm845-smmu-v2' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 79fad917d142f..e5c60a6e40747 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5286,7 +5286,7 @@ wake-pins { }; apps_smmu: iommu@15000000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; -- GitLab From ec888e6cff94af8fc5889824d98b1f1df65f3131 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:29 +0200 Subject: [PATCH 378/926] arm64: dts: qcom: sm8550-qrd: add missing PCIE1 PHY AUX clock frequency The SM8550 DTSI defines a fixed PCIE1 PHY AUX clock and expects boards to define frequency. Use the same as in MTP8550 to fix: sm8550-qrd.dtb: pcie-1-phy-aux-clk: 'clock-frequency' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index ade6ba53ae6bc..8669d29144bb0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -521,6 +521,10 @@ &pm8550b_eusb2_repeater { vdd3-supply = <&vreg_l5b_3p1>; }; +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + &qupv3_id_0 { status = "okay"; }; -- GitLab From a2d8dcd48e132967eb8596a02a06185db8fbcb92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 16 Apr 2023 14:37:30 +0200 Subject: [PATCH 379/926] arm64: dts: qcom: sm6125-sprout: align ADC channel node names with bindings Bindings expect ADC channel node names to follow specific pattern: sm6125-xiaomi-laurel-sprout.dtb: adc@3100: 'adc-chan@4d', 'adc-chan@4e', 'adc-chan@52', 'adc-chan@54' do not match any of the regexes: ... Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230416123730.300863-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index b1038eb8cebc2..a7f4aeae9c1a5 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -138,7 +138,7 @@ &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; - adc-chan@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -146,7 +146,7 @@ adc-chan@4d { label = "rf_pa0_therm"; }; - adc-chan@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -154,7 +154,7 @@ adc-chan@4e { label = "quiet_therm"; }; - adc-chan@52 { + channel@52 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -162,7 +162,7 @@ adc-chan@52 { label = "camera_flash_therm"; }; - adc-chan@54 { + channel@54 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; -- GitLab From 5b85de0d51776cae7c165ec2785d1be06ebc9f21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Apr 2023 23:19:21 +0200 Subject: [PATCH 380/926] arm64: dts: qcom: sdm630-nile: correct duplicated reserved memory node SoC DTSI already comes with 85800000 reserved memory node, so assume the author wanted to update its length. This fixes dtbs W=1 warning: Warning (unique_unit_address_if_enabled): /reserved-memory/qhee-code@85800000: duplicate unit-address (also used in node /reserved-memory/reserved@85800000) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230419211921.79871-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 2ca713a3902a9..3033723fc6ff3 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -138,11 +138,6 @@ debug@ffb00000 { no-map; }; - reserved@85800000 { - reg = <0x00 0x85800000 0x00 0x3700000>; - no-map; - }; - cont_splash_mem: splash@9d400000 { reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; no-map; @@ -256,6 +251,10 @@ &pon_resin { linux,code = ; }; +&qhee_code { + reg = <0x00 0x85800000 0x00 0x3700000>; +}; + &qusb2phy0 { status = "okay"; -- GitLab From 24cf51a2e4519c230fd5cbf281c73043e8bf1eeb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 20:07:44 +0200 Subject: [PATCH 381/926] arm64: dts: qcom: msm8996: correct /soc/bus ranges The bus@0 node should have reg or ranges to fix dtbs W=1 warnings: Warning (unit_address_vs_reg): /soc@0/bus@0: node has a unit name, but no reg or ranges property Warning (simple_bus_reg): /soc@0/bus@0: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Tested-by: Konrad Dybcio # MSM8996 Kagura Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420180746.860934-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8a40c4b0f94c1..751911fea3969 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1830,7 +1830,7 @@ bus@0 { compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x0 0xffffffff>; pcie0: pcie@600000 { compatible = "qcom,pcie-msm8996"; -- GitLab From 8164116023acb6dd600776a3391d5b0cd7699adc Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Mon, 24 Apr 2023 15:02:38 +0530 Subject: [PATCH 382/926] arm64: dts: qcom: sc7180: Add stream-id of qspi to iommus As part of DMA mode support to qspi driver. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1682328761-17517-3-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d89aa56191639..af90052c5a8a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2691,6 +2691,7 @@ opp-202000000 { qspi: spi@88dc000 { compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; + iommus = <&apps_smmu 0x20 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; -- GitLab From cc406006126e89c5330ff5c75da20deb5cafedf8 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Mon, 24 Apr 2023 15:02:39 +0530 Subject: [PATCH 383/926] arm64: dts: qcom: sc7280: Add stream-id of qspi to iommus As part of DMA mode support to qspi driver. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1682328761-17517-4-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e441b1d6cad37..7c5dbac7ef772 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3445,6 +3445,7 @@ usb2_role_switch: endpoint { qspi: spi@88dc000 { compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x1000>; + iommus = <&apps_smmu 0x20 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; -- GitLab From 0aa2811cf5eb2355cd91035b4a76a6120a5c6382 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Mon, 24 Apr 2023 15:02:40 +0530 Subject: [PATCH 384/926] arm64: dts: qcom: sdm845: Add stream-id of qspi to iommus As part of DMA mode support to qspi driver. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1682328761-17517-5-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e55f826709c3a..f1dfdd129eab3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3890,6 +3890,7 @@ opp-201500000 { qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; reg = <0 0x088df000 0 0x600>; + iommus = <&apps_smmu 0x160 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; -- GitLab From 9903258a937b47b78d18c7cb8e342ccbb671d8c2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 7 May 2023 19:45:14 +0200 Subject: [PATCH 385/926] arm64: dts: qcom: msm8916: correct LPASS CPU clocks order Re-order the clocks for LPASS CPU node to match the bindings (Linux driver takes by name): msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:1: 'mi2s-bit-clk0' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:2: 'mi2s-bit-clk1' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:3: 'mi2s-bit-clk2' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:4: 'mi2s-bit-clk3' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:5: 'pcnoc-mport-clk' was expected msm8916-asus-z00l.dtb: audio-controller@7708000: clock-names:6: 'pcnoc-sway-clk' was expected Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507174516.264936-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6444a2e6bb2cb..92552f3641da0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1519,20 +1519,20 @@ lpass: audio-controller@7708000 { * Primary/Secondary MI2S both use the PRI_I2S_CLK. */ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; clock-names = "ahbix-clk", - "pcnoc-mport-clk", - "pcnoc-sway-clk", "mi2s-bit-clk0", "mi2s-bit-clk1", "mi2s-bit-clk2", - "mi2s-bit-clk3"; + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; #sound-dai-cells = <1>; interrupts = ; -- GitLab From 3e8188b4b6c76bfa5c5389384bea2719a1271327 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 7 May 2023 19:45:15 +0200 Subject: [PATCH 386/926] arm64: dts: qcom: msm8996: correct MMCC clocks order Re-order the clocks for MMCC clock controller node to match the bindings (Linux driver takes by name): msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507174516.264936-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 751911fea3969..a3f49f21ec379 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -887,16 +887,16 @@ mmcc: clock-controller@8c0000 { #power-domain-cells = <1>; reg = <0x008c0000 0x40000>; clocks = <&xo_board>, - <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, <&gcc GPLL0>, + <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, <&dsi0_phy 1>, <&dsi0_phy 0>, <&dsi1_phy 1>, <&dsi1_phy 0>, <&hdmi_phy>; clock-names = "xo", - "gcc_mmss_noc_cfg_ahb_clk", "gpll0", + "gcc_mmss_noc_cfg_ahb_clk", "dsi0pll", "dsi0pllbyte", "dsi1pll", -- GitLab From c77612a07d18d4425fd8ddd532a8a9b8e1970c53 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 7 May 2023 19:45:16 +0200 Subject: [PATCH 387/926] arm64: dts: qcom: apq8096: fix fixed regulator name property Correct the typo in 'regulator-name' property. apq8096-ifc6640.dtb: v1p05-regulator: 'regulator-name' is a required property apq8096-ifc6640.dtb: v1p05-regulator: Unevaluated properties are not allowed ('reglator-name' was unexpected) Fixes: 6cbdec2d3ca6 ("arm64: dts: qcom: msm8996: Introduce IFC6640") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507174516.264936-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 71e0a500599c8..ed2e2f6c6775a 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -26,7 +26,7 @@ chosen { v1p05: v1p05-regulator { compatible = "regulator-fixed"; - reglator-name = "v1p05"; + regulator-name = "v1p05"; regulator-always-on; regulator-boot-on; @@ -38,7 +38,7 @@ v1p05: v1p05-regulator { v12_poe: v12-poe-regulator { compatible = "regulator-fixed"; - reglator-name = "v12_poe"; + regulator-name = "v12_poe"; regulator-always-on; regulator-boot-on; -- GitLab From 07e3e17205794c8df6b55c65117ca6a6502a37d7 Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 26 May 2023 19:01:17 +0530 Subject: [PATCH 388/926] arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 07aeb8a8e97bb..74bd5f323d96e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -548,6 +548,19 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, }; }; + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -592,6 +605,19 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + qupv3_id_3: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xbc0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; -- GitLab From ee2f5f906d69d96350c2b59fddef75a76d23e877 Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 26 May 2023 19:01:18 +0530 Subject: [PATCH 389/926] arm64: dts: qcom: sa8775p: add missing i2c nodes Add the missing nodes for the i2c buses present on sa8775p Soc. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 420 ++++++++++++++++++++++++++ 1 file changed, 420 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 74bd5f323d96e..ed8fb37110513 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -490,6 +490,69 @@ qupv3_id_2: geniqup@8c0000 { #size-cells = <2>; status = "disabled"; + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x888000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + spi16: spi@888000 { compatible = "qcom,geni-spi"; reg = <0x0 0x00888000 0x0 0x4000>; @@ -511,6 +574,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart17: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x0088c000 0x0 0x4000>; @@ -546,6 +630,48 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, #size-cells = <0>; status = "disabled"; }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c20: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -559,6 +685,132 @@ qupv3_id_0: geniqup@9c0000 { <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus = <&apps_smmu 0x403 0x0>; status = "disabled"; + + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -573,6 +825,90 @@ qupv3_id_1: geniqup@ac0000 { iommus = <&apps_smmu 0x443 0x0>; status = "disabled"; + i2c7: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c8: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c9: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart10: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a8c000 0x0 0x4000>; @@ -589,6 +925,48 @@ &clk_virt SLAVE_QUP_CORE_1 0>, status = "disabled"; }; + i2c11: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + + i2c12: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart12: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a94000 0x0 0x4000>; @@ -603,6 +981,27 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + i2c13: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_3: geniqup@bc0000 { @@ -616,6 +1015,27 @@ qupv3_id_3: geniqup@bc0000 { <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; iommus = <&apps_smmu 0x43 0x0>; status = "disabled"; + + i2c21: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; ufs_mem_hc: ufs@1d84000 { -- GitLab From 1b2d7ad5ac14df4657e629a0b681fd966d43a74e Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 26 May 2023 19:01:19 +0530 Subject: [PATCH 390/926] arm64: dts: qcom: sa8775p: add missing spi nodes Add the missing nodes of the SPI buses present on sa8775p platform. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526133122.16443-4-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 399 ++++++++++++++++++++++++++ 1 file changed, 399 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index ed8fb37110513..df7e0f8f782c9 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -511,6 +511,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c15: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x884000 0x0 0x4000>; @@ -532,6 +553,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c16: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x888000 0x0 0x4000>; @@ -595,6 +637,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart17: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x0088c000 0x0 0x4000>; @@ -631,6 +694,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c19: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x894000 0x0 0x4000>; @@ -652,6 +736,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c20: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x898000 0x0 0x4000>; @@ -672,6 +777,27 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi20: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -707,6 +833,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x984000 0x0 0x4000>; @@ -728,6 +875,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x988000 0x0 0x4000>; @@ -749,6 +917,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x98c000 0x0 0x4000>; @@ -770,6 +959,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x990000 0x0 0x4000>; @@ -791,6 +1001,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x994000 0x0 0x4000>; @@ -811,6 +1042,27 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -846,6 +1098,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi7: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c8: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa84000 0x0 0x4000>; @@ -867,6 +1140,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi8: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c9: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa88000 0x0 0x4000>; @@ -888,6 +1182,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi9: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c10: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa8c000 0x0 0x4000>; @@ -909,6 +1224,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi10: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart10: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a8c000 0x0 0x4000>; @@ -946,6 +1282,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi11: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c12: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa94000 0x0 0x4000>; @@ -967,6 +1324,27 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + spi12: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart12: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a94000 0x0 0x4000>; @@ -1036,6 +1414,27 @@ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi21: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; ufs_mem_hc: ufs@1d84000 { -- GitLab From 445a523d462432dd9001c899e2c3ced60d23994b Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 26 May 2023 19:01:20 +0530 Subject: [PATCH 391/926] arm64: dts: qcom: sa8775p: add uart5 and uart9 nodes Add remaining uart5 and uart9 nodes for UART bus present on sa8775p SoC. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526133122.16443-5-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index df7e0f8f782c9..0385fc810d4cb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1063,6 +1063,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + uart5: serial@994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x994000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -1203,6 +1218,21 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + uart9: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c10: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa8c000 0x0 0x4000>; -- GitLab From a1f6bef21355da77101eca1a35c30408ad74ef67 Mon Sep 17 00:00:00 2001 From: Shazad Hussain Date: Fri, 26 May 2023 19:01:21 +0530 Subject: [PATCH 392/926] arm64: dts: qcom: sa8775p-ride: enable i2c11 This enables the i2c11 node on sa8775p-ride board for A2B controller and audio port expander. Signed-off-by: Shazad Hussain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526133122.16443-6-quic_shazhuss@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 4c000a5cb3c4b..ab767cfa51ff5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -19,6 +19,7 @@ aliases { serial0 = &uart10; serial1 = &uart12; serial2 = &uart17; + i2c11 = &i2c11; i2c18 = &i2c18; spi16 = &spi16; ufshc1 = &ufs_mem_hc; @@ -260,6 +261,13 @@ vreg_l8e: ldo8 { }; }; +&i2c11 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>; @@ -370,6 +378,13 @@ qup_spi16_default: qup-spi16-state { bias-disable; }; + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4"; -- GitLab From 63f4e4b6f54cdde98ca9c484724d4012989e3454 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 18:40:38 +0200 Subject: [PATCH 393/926] dt-bindings: clock: Add Qcom SM8450 GPUCC Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 73 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm8450-gpucc.h | 48 ++++++++++++ include/dt-bindings/reset/qcom,sm8450-gpucc.h | 20 +++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8450-gpucc.h create mode 100644 include/dt-bindings/reset/qcom,sm8450-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml new file mode 100644 index 0000000000000..ad913b2daf0c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8450 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/reset/qcom,sm8450-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8450-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8450-gpucc.h b/include/dt-bindings/clock/qcom,sm8450-gpucc.h new file mode 100644 index 0000000000000..712b171503d67 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H + +/* Clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_SNOC_DVM_CLK 5 +#define GPU_CC_CXO_AON_CLK 6 +#define GPU_CC_CXO_CLK 7 +#define GPU_CC_DEMET_CLK 8 +#define GPU_CC_DEMET_DIV_CLK_SRC 9 +#define GPU_CC_FF_CLK_SRC 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_FF_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_RDVM_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19 +#define GPU_CC_HUB_AON_CLK 20 +#define GPU_CC_HUB_CLK_SRC 21 +#define GPU_CC_HUB_CX_INT_CLK 22 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23 +#define GPU_CC_MEMNOC_GFX_CLK 24 +#define GPU_CC_MND1X_0_GFX3D_CLK 25 +#define GPU_CC_MND1X_1_GFX3D_CLK 26 +#define GPU_CC_PLL0 27 +#define GPU_CC_PLL1 28 +#define GPU_CC_SLEEP_CLK 29 +#define GPU_CC_XO_CLK_SRC 30 +#define GPU_CC_XO_DIV_CLK_SRC 31 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/reset/qcom,sm8450-gpucc.h b/include/dt-bindings/reset/qcom,sm8450-gpucc.h new file mode 100644 index 0000000000000..58ba8f9871073 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8450-gpucc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 + +#endif -- GitLab From 778af143adc8813d8851be401f71dfb80b9144eb Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 23:47:58 +0530 Subject: [PATCH 394/926] dt-bindings: clock: qcom: Add SM8550 graphics clock controller Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + include/dt-bindings/clock/qcom,sm8550-gpucc.h | 48 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sm8550-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index ad913b2daf0c1..2320be920a5f7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,12 +15,14 @@ description: | See also:: include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h properties: compatible: enum: - qcom,sm8450-gpucc + - qcom,sm8550-gpucc clocks: items: diff --git a/include/dt-bindings/clock/qcom,sm8550-gpucc.h b/include/dt-bindings/clock/qcom,sm8550-gpucc.h new file mode 100644 index 0000000000000..a6760547a3ab5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DEMET_DIV_CLK_SRC 7 +#define GPU_CC_FF_CLK_SRC 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_MEMNOC_GFX_CLK 15 +#define GPU_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_CC_PLL0 18 +#define GPU_CC_PLL1 19 +#define GPU_CC_SLEEP_CLK 20 +#define GPU_CC_XO_CLK_SRC 21 +#define GPU_CC_XO_DIV_CLK_SRC 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif -- GitLab From 9f7579423d2d619064dc84cfa8068e3c83b09e3f Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 23:48:00 +0530 Subject: [PATCH 395/926] arm64: dts: qcom: sm8550: Add graphics clock controller Add device node for graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524181800.28717-4-quic_jkona@quicinc.com --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 29b99003d8a9f..20924d570c07e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1952,6 +1953,17 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8550-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; -- GitLab From 171342e6af06e66a099103f95ede9333aeec28c0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 15 May 2023 07:44:29 +0200 Subject: [PATCH 396/926] ARM: dts: imx6qdl-mba6: add mac address for USB ethernet controller The mac address is stored in mainboard eeprom. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-mba6.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/imx6qdl-mba6a.dtsi | 6 ++++++ arch/arm/boot/dts/imx6qdl-mba6b.dtsi | 6 ++++++ 3 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi index 78555a6188510..c911688e9832b 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -271,6 +271,22 @@ &uart5 { &usbh1 { disable-over-current; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb424,2517"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usb424,9e00"; + reg = <1>; + nvmem-cells = <&mba_mac_address>; + nvmem-cell-names = "mac-address"; + }; + }; }; &usbotg { diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi index df8fa169e9f6d..27fec340c380a 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -21,6 +21,12 @@ m24c64_57: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; rtc0: rtc@68 { diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi index 7d1cd7454c7f5..0a9f076eeb36e 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -31,6 +31,12 @@ m24c64_57: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; rtc0: rtc@68 { -- GitLab From 64d45a1a27159229fd55deab9eb2001add8adc9b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 May 2023 17:51:02 +0200 Subject: [PATCH 397/926] arm64: dts: imx8mp: Describe PCIe clock generator on DH electronics i.MX8M Plus DHCOM on PDK3 The PDK3 carrier board contains a PCIe clock generator which is used to supply the PCIe clock lanes. This generator is always on, unless external CLKREQ signal toggles an output off, but this is handled in hardware. The generator does however have I2C interface, describe it in DT. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index b5e76b992a103..24dc58b3404fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -23,10 +23,10 @@ chosen { stdout-path = &uart1; }; - clk_pcie: clock-pcie { + clk_xtal25: clock-xtal25 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <25000000>; }; connector { @@ -203,6 +203,13 @@ eeprom_board: eeprom@54 { pagesize = <16>; reg = <0x54>; }; + + pcieclk: clock@6b { + compatible = "skyworks,si52144"; + reg = <0x6b>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; i2cmuxed1: i2c@1 { /* HDMI DDC I2C */ @@ -244,7 +251,7 @@ &flexcan1 { }; &pcie_phy { - clocks = <&clk_pcie>; + clocks = <&pcieclk 1>; clock-names = "ref"; fsl,refclk-pad-mode = ; status = "okay"; -- GitLab From b0d051afedad32623fa933ac2c44e77b8174f00a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 16 May 2023 07:50:06 +0200 Subject: [PATCH 398/926] arm64: dts: imx8mp: move noc node to correct position The base address of NOC is bigger than aips5, but smaller than aips4. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 40 +++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 245c560674de7..e781a07cec45c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1154,26 +1154,6 @@ eqos: ethernet@30bf0000 { }; }; - noc: interconnect@32700000 { - compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; - reg = <0x32700000 0x100000>; - clocks = <&clk IMX8MP_CLK_NOC>; - #interconnect-cells = <1>; - operating-points-v2 = <&noc_opp_table>; - - noc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - }; - }; - }; - aips5: bus@30c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30c00000 0x400000>; @@ -1325,6 +1305,26 @@ audio_blk_ctrl: clock-controller@30e20000 { }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MP_CLK_NOC>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; -- GitLab From d8f9d8126582d27c5fe51eb0fa22bb73d5d768b3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 16 May 2023 10:04:20 +0200 Subject: [PATCH 399/926] arm64: dts: imx8mp: Add analog audio output on i.MX8MP TQMa8MPxL/MBa8MPxL Enable SAI3, add the codec and pinctrl nodes to enable audio support on MBa8MPxL. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index d8fb29e7e1484..4240e20d38ac3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -202,6 +202,13 @@ linux,cma { }; }; + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tq-tlv320aic32x"; + audio-cpu = <&sai3>; + audio-codec = <&tlv320aic3x04>; + }; + thermal-zones { soc-thermal { trips { @@ -449,6 +456,18 @@ &i2c2 { sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320aic3x04>; + reg = <0x18>; + clock-names = "mclk"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + iov-supply = <®_vcc_3v3>; + ldoin-supply = <®_vcc_3v3>; + }; + se97_1c: temperature-sensor@1c { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1c>; @@ -528,6 +547,16 @@ &pwm3 { status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -843,6 +872,23 @@ pinctrl_regpwmfan: regpwmfangrp { fsl,pins = ; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 + >; + }; + + pinctrl_tlv320aic3x04: tlv320aic3x04grp { + fsl,pins = < + /* CODEC RST# */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 + >; + }; + /* X61 */ pinctrl_uart1: uart1grp { fsl,pins = , -- GitLab From 0275a471839d461c2009cbf9024844972769b138 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 May 2023 10:13:53 +0200 Subject: [PATCH 400/926] arm64: dts: imx8mp: Sort AIPS4 nodes Sort AIPS4 nodes by node unit-address . No functional change . Suggested-by: Alexander Stein Signed-off-by: Marek Vasut Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 204 +++++++++++----------- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e781a07cec45c..2eb14cdd3e9f4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1332,6 +1332,108 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + + mipi_csi_0: csi@32e40000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e40000 0x10000>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <500000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; + }; + }; + + mipi_csi_1: csi@32e50000 { + compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; + reg = <0x32e50000 0x10000>; + interrupts = ; + clock-frequency = <266000000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <266000000>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; + }; + }; + }; + mipi_dsi: dsi@32e60000 { compatible = "fsl,imx8mp-mipi-dsim"; reg = <0x32e60000 0x400>; @@ -1500,108 +1602,6 @@ ldb_lvds_ch1: endpoint { }; }; - isi_0: isi@32e00000 { - compatible = "fsl,imx8mp-isi"; - reg = <0x32e00000 0x4000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "axi", "apb"; - fsl,blk-ctrl = <&media_blk_ctrl>; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - isi_in_0: endpoint { - remote-endpoint = <&mipi_csi_0_out>; - }; - }; - - port@1 { - reg = <1>; - - isi_in_1: endpoint { - remote-endpoint = <&mipi_csi_1_out>; - }; - }; - }; - }; - - mipi_csi_0: csi@32e40000 { - compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; - reg = <0x32e40000 0x10000>; - interrupts = ; - clock-frequency = <500000000>; - clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, - <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; - clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <500000000>; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - mipi_csi_0_out: endpoint { - remote-endpoint = <&isi_in_0>; - }; - }; - }; - }; - - mipi_csi_1: csi@32e50000 { - compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; - reg = <0x32e50000 0x10000>; - interrupts = ; - clock-frequency = <266000000>; - clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, - <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, - <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; - clock-names = "pclk", "wrap", "phy", "axi"; - assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; - assigned-clock-rates = <266000000>; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - mipi_csi_1_out: endpoint { - remote-endpoint = <&isi_in_1>; - }; - }; - }; - }; - pcie_phy: pcie-phy@32f00000 { compatible = "fsl,imx8mp-pcie-phy"; reg = <0x32f00000 0x10000>; -- GitLab From 0c45fb7faf6f57aeb8b17c77195d113b3fc06cd3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 May 2023 10:13:54 +0200 Subject: [PATCH 401/926] arm64: dts: imx8mp: Add DeWarp Engine DT node Add DT node for the DeWarp Engine of the i.MX8MP. Signed-off-by: Marek Vasut Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 2eb14cdd3e9f4..dbd97a7193381 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1366,6 +1366,16 @@ isi_in_1: endpoint { }; }; + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; + mipi_csi_0: csi@32e40000 { compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; -- GitLab From 06d26d5b52f9d1571b0a52666775074dd93beb46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 16 May 2023 10:57:13 +0200 Subject: [PATCH 402/926] dt-bindings: arm: fsl: Fix syntax error Fix the following error by replacing tab indent with spaces. " Documentation/devicetree/bindings/arm/fsl.yaml:930:46: [error] syntax error: found character '\t' that cannot start any token (syntax) " Fixes: d2bf7abfd235 ("dt-bindings: arm: fsl: Add Emtop SoM & Baseboard") Signed-off-by: Marek Vasut Reviewed-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 63f8886dc69a5..b5fc884cfb668 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -927,8 +927,8 @@ properties: - description: Emtop i.MX8MM based Boards items: - - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 - - const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module + - const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1 + - const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module - const: fsl,imx8mm - description: Engicam i.Core MX8M Mini SoM based boards -- GitLab From 5f06c3f508f73a7c9ae804e1f2a655b4d14d73b3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 May 2023 22:04:53 +0530 Subject: [PATCH 403/926] arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B SoM Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. General features: - Rockchip RK3588J - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC On module WiFi6/BT5 is available in the following Neu6 variants. Neu6B needs to mount on top of associated Edgeble Neu6B IO boards for creating complete platform solutions. Enable eMMC for now to boot Linux successfully. Add support for Edgeble Neu6 Model B SoM. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230516163454.997736-3-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-edgeble-neu6b.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi new file mode 100644 index 0000000000000..1c5bcf1280b48 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; -- GitLab From 3a9181a43b94c119da9f332cfc048d4b42119db3 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 16 May 2023 22:04:54 +0530 Subject: [PATCH 404/926] arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B IO Neural Compute Module 6B(Neu6B) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. IO board offers plenty of peripherals and connectivity options and this patch enables basic eMMC and UART which is enough to successfully boot Linux. General features: - microSD slot - 1x HDMI Out - 1x HDMI In - 2x DP - 1x eDP - 2x MIPI DSI connector - 4x MIPI CSI2 connector - 2x USB Host - 2x USB 3.0 OTG/Host - 1x SATA - 1x 2.5Gbps Ethernet - 1x 4G/5G mini PCIe - 1x M.2 E-Key slot - 1x Onboard PoE - 1x RS485, RS232, CAN - 1x Audio, MIC port - RTC battery slot - 40-pin GPIO expansion Neu6B needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. Add support for Edgeble Neu6 Model B IO Board. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230516163454.997736-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-edgeble-neu6b-io.dts | 27 +++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 50d97ae28b151..41a686cb4b6ac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts new file mode 100644 index 0000000000000..e9d5a8bab581f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588j.dtsi" +#include "rk3588-edgeble-neu6b.dtsi" + +/ { + model = "Edgeble Neu6B IO Board"; + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; -- GitLab From ec5d218e1e443dd6fea7e77983c3f97b9e09a74a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 26 May 2023 19:22:55 +0200 Subject: [PATCH 405/926] arm64: dts: rockchip: add PMIC to rk3588-evb1 This adds PMIC support for the RK3588 EVB. Co-developed-by: shengfei Xu Signed-off-by: shengfei Xu Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230526172255.68236-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-evb1-v10.dts | 637 ++++++++++++++++++ 1 file changed, 637 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index b91af0204dbe8..4b2d857ee2197 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -49,6 +49,38 @@ vcc5v0_sys: vcc5v0-sys-regulator { }; }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + &gmac0 { clock_in_out = "output"; phy-handle = <&rgmii_phy>; @@ -123,6 +155,611 @@ &sdhci { status = "okay"; }; +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; -- GitLab From 50b1e9ece16c5fa680ae1c6fdc660b1f065e9b40 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 16 May 2023 12:00:40 -0700 Subject: [PATCH 406/926] dt-bindings: arm: Add Gateworks i.MX8M GW7905-2x board Add DT compatible string for a Gateworks GW7905-2x board based on the i.MX8MPlus from NXP. Signed-off-by: Tim Harvey Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b5fc884cfb668..2510eaa8906dd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1032,6 +1032,7 @@ properties: - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board + - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board - polyhex,imx8mp-debix # Polyhex Debix boards - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules -- GitLab From a101ba8587fae1dfd7b1bfb13397000a381b0774 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 17 May 2023 12:11:07 +0200 Subject: [PATCH 407/926] ARM: dts: imx6qdl: Add HDMI to TQMa6x/MBa6 This adds support for a COTS monitor connected to X17. 4k monitors can be used, but are limited to 1080p. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-mba6.dtsi | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi index c911688e9832b..34d5cf7cee0b1 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -192,6 +192,13 @@ ethphy: ethernet-phy@3 { }; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -205,6 +212,17 @@ tlv320aic32x4: audio-codec@18 { }; }; +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -411,6 +429,15 @@ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ >; }; + pinctrl_hdmi: hdmigrp { + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 @@ -447,6 +474,20 @@ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b899 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b899 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ -- GitLab From 20d0b83e712b92163ddcfb313288272720272733 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 May 2023 18:24:24 +0200 Subject: [PATCH 408/926] arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOM Add TC9595 DSI-to-DPI and DSI-to-(e)DP bridge to DH electronics i.MX8M Plus DHCOM SoM . The bridge is populated on the SoM, but disabled by default unless used for display output. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 7e804f6507843..599c4334f32b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -232,6 +232,36 @@ &i2c3 { sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + tc_bridge: bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + reg = <0xf>; + clock-names = "ref"; + clocks = <&clk IMX8MP_CLK_CLKOUT2>; + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, + <&clk IMX8MP_CLK_CLKOUT2>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <13000000>, <13000000>, <156000000>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tc_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + pmic: pmic@25 { compatible = "nxp,pca9450c"; reg = <0x25>; @@ -398,6 +428,22 @@ &i2c5 { /* HDMI EDID bus */ status = "okay"; }; +&mipi_dsi { + samsung,burst-clock-frequency = <160000000>; + samsung,esc-clock-frequency = <10000000>; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&tc_bridge_in>; + }; + }; + }; +}; + &pwm1 { pinctrl-0 = <&pinctrl_pwm1>; pinctrl-names = "default"; @@ -863,6 +909,15 @@ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 >; }; + pinctrl_tc9595: dhcom-tc9595-grp { + fsl,pins = < + /* RESET_DSIBRIDGE */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 + /* DSI-CONV_INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 + >; + }; + pinctrl_touch: dhcom-touch-grp { fsl,pins = < /* #TOUCH_INT */ -- GitLab From 0d5b288c2110e8a7c74daf90a5e030c44a08ae1c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 16 May 2023 12:00:41 -0700 Subject: [PATCH 409/926] arm64: dts: freescale: Add imx8mp-venice-gw7905-2x The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - RGMII PHY (eQoS) - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-venice-gw702x.dtsi | 587 ++++++++++++++++++ .../dts/freescale/imx8mp-venice-gw7905-2x.dts | 28 + .../dts/freescale/imx8mp-venice-gw7905.dtsi | 309 +++++++++ 4 files changed, 925 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index eb6279fcdf7be..a750be13ace89 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi new file mode 100644 index 0000000000000..74b0fda235edd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi @@ -0,0 +1,587 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + aliases { + ethernet0 = &eqos; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-tamper { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck3_reg>; +}; + +&A53_1 { + cpu-supply = <&buck3_reg>; +}; + +&A53_2 { + cpu-supply = <&buck3_reg>; +}; + +&A53_3 { + cpu-supply = <&buck3_reg>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0x0>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + tx-fifo-depth = ; + rx-fifo-depth = ; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_1p0"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_1p8"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_2p5"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_soc"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_arm"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + + fan-controller@0 { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; + + pmic@69 { + compatible = "mps,mp5416"; + reg = <0x69>; + + regulators { + /* vdd_soc */ + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_dram */ + buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_arm */ + buck3_reg: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* vdd_1p8 */ + buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT2: nvcc_snvs_1p8 */ + ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT3: vdd_1p0 */ + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT4: vdd_2p5 */ + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + /* OUT5: vdd_3p3 */ + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +/* off-board header */ +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* off-board */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + status = "okay"; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts new file mode 100644 index 0000000000000..4a1bbbbe19e66 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905-2x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&eqos { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi new file mode 100644 index 0000000000000..0d40cb0f05f67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw7905.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include +#include +#include + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "gpiod", "", "", + "gpiob", "gpioc", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "pci_usb_sel", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */ + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; -- GitLab From c5e341aacd3af5f4dbf3b320d0a75cfe56157470 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 19 May 2023 14:27:30 +0800 Subject: [PATCH 410/926] ARM: dts: imx6sll-evk: add eMMC node support On imx6sll-evk board, eMMC is connect on the usdhc2. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 67 +++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 269092ac881c5..ad219a647d9c1 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -109,6 +109,14 @@ reg_sd1_vmmc: regulator-sd1-vmmc { enable-active-high; }; + reg_sd2_vmmc: regulator-sd2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + reg_sd3_vmmc: regulator-sd3-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -343,6 +351,17 @@ &usdhc1 { status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + vqmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; @@ -466,6 +485,54 @@ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x13059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x130f9 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 -- GitLab From eb2a7d92dd9f94c0ec9e7c0620e83a993e35eec8 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 19 May 2023 14:27:31 +0800 Subject: [PATCH 411/926] ARM: dts: imx6sll-evk: avoid underscores in node name usdhc1 and usdhc3 node name contain underscores, so replace the '_' by '-'. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index ad219a647d9c1..e3e9b0ec4f734 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -463,7 +463,7 @@ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 >; }; - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 @@ -474,7 +474,7 @@ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 >; }; - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { fsl,pins = < MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 @@ -551,7 +551,7 @@ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 >; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { fsl,pins = < MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 @@ -563,7 +563,7 @@ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 >; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { fsl,pins = < MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 -- GitLab From b74edf626c4f99b3fc7f426bb47e5e52a3bcc4a8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 23 May 2023 20:52:32 -0300 Subject: [PATCH 412/926] ARM: dts: imx6sx: Add LDB support i.MX6SX has an LVDS controller that is connected to the eLCDIF. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 42 +++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 4233943a1cca8..3a43086665522 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -841,10 +841,40 @@ iomuxc: pinctrl@20e0000 { reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@20e4000 { + gpr: syscon@20e4000 { compatible = "fsl,imx6sx-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; reg = <0x020e4000 0x4000>; + + lvds_bridge: bridge@18 { + compatible = "fsl,imx6sx-ldb"; + reg = <0x18 0x4>; + clocks = <&clks IMX6SX_CLK_LDB_DI0>; + clock-names = "ldb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + }; + }; }; sdma: dma-controller@20ec000 { @@ -1278,6 +1308,14 @@ lcdif1: lcdif@2220000 { clock-names = "pix", "axi", "disp_axi"; power-domains = <&pd_disp>; status = "disabled"; + + ports { + port { + lcdif1_to_ldb: endpoint { + remote-endpoint = <&ldb_from_lcdif1>; + }; + }; + }; }; lcdif2: lcdif@2224000 { -- GitLab From 64719d28a36a6369db64ffd171177a9197f0cb59 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 22 May 2023 12:32:18 -0700 Subject: [PATCH 413/926] ARM: dts: imx6qdl-gw54xx: remove invalid nodes from fan-controller Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 4e20cb97058eb..6c487d40a3b76 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -349,8 +349,6 @@ channel@26 { fan-controller@2c { compatible = "gw,gsc-fan"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x2c>; }; }; -- GitLab From 785167f21d6fb440d14f629a3c44978048ed0be5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 22 May 2023 12:32:19 -0700 Subject: [PATCH 414/926] ARM: dts: imx6qdl-gw5912: remove invalid nodes from fan-controller Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 40e235e315cc4..de5983cf7810d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -243,8 +243,6 @@ channel@23 { fan-controller@a { compatible = "gw,gsc-fan"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x0a>; }; }; -- GitLab From 4d4ed48f9bda5ce9954b5af23548e68f166066ac Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 22 May 2023 12:32:17 -0700 Subject: [PATCH 415/926] arm64: dts: imx8mm-venice-gw700x: remove invalid props from fan-controller Remove the invalid #address-cells and #size-cells nodes from the fan-controller. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 9e7d388721575..72cf250d9b4f9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -234,8 +234,6 @@ channel@a2 { }; fan-controller@0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "gw,gsc-fan"; reg = <0x0a>; }; -- GitLab From 04a0b7b88402caf01fe5ebd0df28c3d956c61a50 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 27 May 2023 12:22:33 +0200 Subject: [PATCH 416/926] arm64: dts: imx8mp: Enable SAI audio on MX8MP DHCOM PDK2 and PDK3 Add SAI I2S and audio bindings on MX8MP DHCOM PDK2 and PDK3. The VDDA is supplied from on-carrier-board regulator, the VDDIO is supplied from always-on on-SoM regulator. Except for different I2C bus used to connect the codec, the implementation is virtually identical on both carrier boards. Align regulator-avdd name to regulator-3p3vdd on PDK3, since this is the VDDA supply and it is the same on both carrier boards. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 54 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 47 +++++++++++++++- .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 17 ++++++ 3 files changed, 116 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 92df6c1277c36..e9fb5f7f39b50 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -23,6 +23,12 @@ chosen { stdout-path = &uart1; }; + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -102,6 +108,43 @@ led-3 { pinctrl-names = "default"; }; }; + + reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3P3VDD"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&i2c5 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3vdd>; + VDDIO-supply = <®_vdd_3p3v_awo>; + }; }; &fec { /* Second ethernet */ @@ -155,6 +198,17 @@ &pcie { status = "okay"; }; +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usb3_1 { fsl,over-current-active-low; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index 24dc58b3404fb..31d85d5871c91 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -23,6 +23,12 @@ chosen { stdout-path = &uart1; }; + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + clk_xtal25: clock-xtal25 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -140,12 +146,30 @@ led-3 { }; }; - reg_avdd: regulator-avdd { /* AUDIO_VDD */ + reg_3p3vdd: regulator-3p3vdd { /* 3.3VDD */ compatible = "regulator-fixed"; regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-name = "AUDIO_VDD"; + regulator-name = "3P3VDD"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; }; }; @@ -161,6 +185,15 @@ i2cmuxed0: i2c@0 { #size-cells = <0>; reg = <0>; + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3vdd>; + VDDIO-supply = <®_vdd_3p3v_awo>; + }; + typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; @@ -263,6 +296,16 @@ &pcie { status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usb_dwc3_0 { usb-role-switch; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 599c4334f32b5..cb1953d14aa90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -49,6 +49,14 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { startup-delay-us = <100>; vin-supply = <&buck4>; }; + + reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VDD_3P3V_AWO"; + }; }; &A53_0 { @@ -918,6 +926,15 @@ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 >; }; + pinctrl_sai3: dhcom-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + >; + }; + pinctrl_touch: dhcom-touch-grp { fsl,pins = < /* #TOUCH_INT */ -- GitLab From 0cf099dfe405c42d4596931cdac1e2f3734a9c27 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 10:10:05 -0300 Subject: [PATCH 417/926] ARM: dts: imx7d-smegw01: Remove unneeded #address-cells/#size-cells Remove the unneeded #address-cells/#size-cells from sram@0 to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: sram@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) From schema: Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-smegw01.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index c0f00f5db11e1..76bbc2ab126ea 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -97,8 +97,6 @@ &ecspi1 { sram@0 { compatible = "microchip,48l640"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <16000000>; }; }; -- GitLab From 1b2b6039bd76f2ece9c0ba82b8116c4eb6ab2445 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 10:10:06 -0300 Subject: [PATCH 418/926] ARM: dts: imx7d-smegw01: Pass 'gpr' to the pinctrl groups Pass 'gpr' to the pinctrl groups to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: pinctrl@30330000: 'rfkillrp', 'usbotg1', 'usbotg1-pwr', 'usbotg1-pwr-gpio' do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-smegw01.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index 76bbc2ab126ea..829a3cbf8ad35 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -327,7 +327,7 @@ MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 >; }; - pinctrl_rfkill: rfkillrp { + pinctrl_rfkill: rfkillgrp { fsl,pins = < MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 >; @@ -353,19 +353,19 @@ MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 >; }; - pinctrl_usbotg1_lpsr: usbotg1 { + pinctrl_usbotg1_lpsr: usbotg1grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 >; }; - pinctrl_usbotg1_pwr: usbotg1-pwr { + pinctrl_usbotg1_pwr: usbotg1-pwrgrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 >; }; - pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio { + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 >; -- GitLab From 353791ce48c8e0683e863493f4c35a6bba94b7d9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 10:10:07 -0300 Subject: [PATCH 419/926] ARM: dts: imx7d-smegw01: Use pinctrl-0 for pinctrl_rfkill Use pinctrl-0 for pinctrl_rfkill to fix the following 'make CHECK_DTBS=y imx7d-smegw01.dtb' warning: regulator-wlan-rfkill: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-smegw01.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index 829a3cbf8ad35..7ec830e4ee05e 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -67,7 +67,7 @@ reg_wifi: regulator-wifi { reg_wlan_rfkill: regulator-wlan-rfkill { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-2 = <&pinctrl_rfkill>; + pinctrl-0 = <&pinctrl_rfkill>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "wlan_rfkill"; -- GitLab From f9acd1a110b577a9adf3f11d0aee973bd792ed29 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 10:10:08 -0300 Subject: [PATCH 420/926] ARM: dts: imx7d-smegw01: Pass Ethernet aliases Pass Ethernet aliases, so that the bootloader can properly pass MAC address to Linux. This fixes the problem of getting a random MAC address for eth1 in Linux. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-smegw01.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index 7ec830e4ee05e..85b97b5f64e72 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -13,6 +13,8 @@ / { compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; mmc0 = &usdhc1; mmc1 = &usdhc3; mmc2 = &usdhc2; -- GitLab From e8b4c363255ac5ead34f731716b83b1744c278ac Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Thu, 25 May 2023 16:08:25 +0800 Subject: [PATCH 421/926] arm64: dts: imx93: add fsl,stop-mode property to support WOL Add fsl,stop-mode property for FEC to support Wake-on-LAN (WOL) feature. Otherwise, the WOL feature of FEC does not work. Signed-off-by: Wei Fang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index dc444ca394afd..3b8043c12856e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -724,6 +724,7 @@ fec: ethernet@42890000 { assigned-clock-rates = <100000000>, <250000000>, <50000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; status = "disabled"; }; -- GitLab From 80ad9b634eff7f4232947a6551b049cc955fb91d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 19:26:11 -0300 Subject: [PATCH 422/926] ARM: dts: imx6ull-phytec-tauri: Remove invalid property The 'rs485-rts-active-high' property is not a valid property and is not documented anywhere. Remove it to fix the following DT schema warning: serial@21f0000: Unevaluated properties are not allowed ('rs485-rts-active-high' was unexpected) Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi index 5464a52a1f944..ea627638e40cf 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -260,7 +260,6 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - rs485-rts-active-high; linux,rs485-enabled-at-boot-time; status = "okay"; }; -- GitLab From b3cea7201551e7f82dd8ea7971e8248e320dd8e7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 19:34:40 -0300 Subject: [PATCH 423/926] ARM: dts: imx7d-flex-concentrator: Remove invalid ecspi property The 'num-chipselects' property is not a valid property for ecspi. Remove it to fix the following DT check warning: spi@30630000: Unevaluated properties are not allowed ('num-chipselects' was unexpected) From schema: Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-flex-concentrator.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/imx7d-flex-concentrator.dts index bd6b5285aa8d2..3a723843d5626 100644 --- a/arch/arm/boot/dts/imx7d-flex-concentrator.dts +++ b/arch/arm/boot/dts/imx7d-flex-concentrator.dts @@ -107,7 +107,6 @@ &adc1 { &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; status = "okay"; @@ -122,7 +121,6 @@ pcf2127: rtc@0 { &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - num-chipselects = <1>; cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; status = "okay"; -- GitLab From a211ff74773f59cc492346a8d203302b100d56c0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 19:46:24 -0300 Subject: [PATCH 424/926] ARM: dts: imx35: Remove invalid wdog property The 'clock-names' property is not a valid property for wdog. Remove it to fix the following DT check warning: watchdog@53fdc000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index d650f54c3fc6b..2d20e5541acc8 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -298,7 +298,6 @@ wdog: watchdog@53fdc000 { compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 74>; - clock-names = ""; interrupts = <55>; }; -- GitLab From 7fe4e51820caee89899e53ef66b4058f3fb28222 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 19:46:25 -0300 Subject: [PATCH 425/926] ARM: dts: vfxxx: Remove invalid wdog property The 'clock-names' property is not a valid property for wdog. Remove it to fix the following DT check warning: vf610-zii-ssmb-dtu.dtb: watchdog@4003e000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: /Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vfxxx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index ff4479994b600..3f7dc787938ee 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -294,7 +294,6 @@ wdoga5: watchdog@4003e000 { reg = <0x4003e000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_WDT>; - clock-names = "wdog"; status = "disabled"; }; -- GitLab From 62c9f9c1d4debaa28ba10b23c1dc7be573602898 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 May 2023 22:12:26 -0300 Subject: [PATCH 426/926] ARM: dts: imx6qdl-icore-rqs: Use the 'vmmc-supply' property 'vmcc-supply' is not a valid property. Use 'vmmc-supply' supply instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index a4217f564a534..ef3f88c3615fd 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -262,7 +262,7 @@ &usdhc3 { pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmcc-supply = <®_sd3_vmmc>; + vmmc-supply = <®_sd3_vmmc>; cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; bus-width = <4>; no-1-8-v; @@ -274,7 +274,7 @@ &usdhc4 { pinctrl-0 = <&pinctrl_usdhc4>; pinctrl-1 = <&pinctrl_usdhc4_100mhz>; pinctrl-2 = <&pinctrl_usdhc4_200mhz>; - vmcc-supply = <®_sd4_vmmc>; + vmmc-supply = <®_sd4_vmmc>; bus-width = <8>; no-1-8-v; non-removable; -- GitLab From 6390213bb5bb06c3babada641c2f679501d1bfba Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Thu, 25 May 2023 20:26:06 +0200 Subject: [PATCH 427/926] ARM: dts: vf610: ZII: Add missing phy-mode and fixed links The DSA framework has got more picky about always having a phy-mode for the CPU port. The Vybrid FEC is a Fast Ethrnet using RMII. Additionally, the cpu label has never actually been used in the binding, so remove it. Lastly, for DSA links between switches, add a fixed-link node indicating the expected speed/duplex of the link. Signed-off-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 2 +- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 +- arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 12 ++++++++- arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 32 ++++++++++++++++++++++- arch/arm/boot/dts/vf610-zii-spb4.dts | 2 +- arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 2 +- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 2 +- 7 files changed, 47 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 96495d9651635..1a19aec8957b7 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -202,7 +202,7 @@ port@5 { port@6 { reg = <6>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 1fafefec77410..16b4e06c4efad 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -75,7 +75,7 @@ fixed-link { port@6 { reg = <6>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index c00d39562a10b..6f9878f124c44 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -44,7 +44,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { @@ -82,6 +82,11 @@ switch0port10: port@10 { label = "dsa"; phy-mode = "xaui"; link = <&switch1port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; @@ -174,6 +179,11 @@ switch1port10: port@10 { label = "dsa"; phy-mode = "xaui"; link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; mdio { diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index 7b3276cd470fb..df1335492a199 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -59,7 +59,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { @@ -115,6 +115,11 @@ switch0port10: port@10 { link = <&switch1port10 &switch3port10 &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; @@ -156,6 +161,11 @@ switch1port9: port@9 { phy-mode = "xgmii"; link = <&switch3port10 &switch2port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; switch1port10: port@10 { @@ -163,6 +173,11 @@ switch1port10: port@10 { label = "dsa"; phy-mode = "xgmii"; link = <&switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; @@ -246,6 +261,11 @@ switch2port10: port@10 { link = <&switch3port9 &switch1port9 &switch0port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; }; }; @@ -295,6 +315,11 @@ switch3port9: port@9 { label = "dsa"; phy-mode = "2500base-x"; link = <&switch2port10>; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; switch3port10: port@10 { @@ -303,6 +328,11 @@ switch3port10: port@10 { phy-mode = "xgmii"; link = <&switch1port9 &switch0port10>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 180acb0795b9e..1461804ecaea3 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -140,7 +140,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 73fdace4cb424..463c2452b9b7f 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -129,7 +129,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 20beaa8433b6c..f5ae0d5de3151 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -154,7 +154,7 @@ ports { port@0 { reg = <0>; - label = "cpu"; + phy-mode = "rmii"; ethernet = <&fec1>; fixed-link { -- GitLab From 68c4c67156ec0e0e1abe11a90e4bb9bfe34ca722 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 9 May 2023 21:31:32 +0530 Subject: [PATCH 428/926] dt-bindings: arm: qcom: document MI01.3 board based on IPQ5332 family Document the MI01.3 (Reference Design Platform 442) board based on IPQ5332 family of SoCs. Signed-off-by: Kathiravan T Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509160133.3794-2-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1050ef598c3f9..8302d1ee280d5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -91,6 +91,7 @@ description: | ap-al02-c7 ap-al02-c8 ap-mi01.2 + ap-mi01.3 ap-mi01.6 cdp cp01-c1 @@ -337,6 +338,7 @@ properties: - items: - enum: - qcom,ipq5332-ap-mi01.2 + - qcom,ipq5332-ap-mi01.3 - qcom,ipq5332-ap-mi01.6 - const: qcom,ipq5332 -- GitLab From a782318023f339213f29372e2ecae696c0ca4a69 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 9 May 2023 21:31:33 +0530 Subject: [PATCH 429/926] arm64: dts: qcom: ipq5332: add support for the RDP442 variant Add the initial device tree support for the Reference Design Platform(RDP) 442 based on IPQ5332 family of SoC. This patch carries the support for Console UART, SPI NOR, eMMC and I2C. Signed-off-by: Kathiravan T Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509160133.3794-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 117 ++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4a2e09ec381da..1ad68b728f50e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts new file mode 100644 index 0000000000000..bcf3b31c20e35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP442 board device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3"; + compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_0_data_clk_pins: spi-0-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-down; + }; + + spi_0_cs_pins: spi-0-cs-state { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-up; + }; +}; -- GitLab From 751ec3da08b431bbffb3425746154cb3af4972ce Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:12 +0200 Subject: [PATCH 430/926] arm64: dts: mediatek: add watchdog support for mt8365 SoC Add watchdog support. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-3-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 1f6b48359115d..bb45aab2e6a9b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -162,6 +162,12 @@ syscfg_pctl: syscfg-pctl@10005000 { reg = <0 0x10005000 0 0x1000>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + pio: pinctrl@1000b000 { compatible = "mediatek,mt8365-pinctrl"; reg = <0 0x1000b000 0 0x1000>; -- GitLab From 56e9f0f4aa30146d2f50ec0d3ebe9294f9c8507e Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:13 +0200 Subject: [PATCH 431/926] arm64: dts: mediatek: add mt6357 PMIC support for mt8365-evk This power management system chip integration helps to manage regulators and keys. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-4-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index ceb48eb1a6e69..6074aa9c1c3e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -12,6 +12,7 @@ #include #include #include "mt8365.dtsi" +#include "mt6357.dtsi" / { model = "MediaTek MT8365 Open Platform EVK"; @@ -94,6 +95,12 @@ &i2c0 { status = "okay"; }; +&mt6357_pmic { + interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; +}; + &pio { gpio_keys: gpio-keys-pins { pins { -- GitLab From 6e8270afad054ec480d4a06c99fa30472a30c793 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:14 +0200 Subject: [PATCH 432/926] arm64: dts: mediatek: add mmc support for mt8365-evk - Add EMMC support on mmc0 (internal memory) - Add SD-UHS support on mmc1 (external memory) Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-5-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 6074aa9c1c3e3..6e2f3601509ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -95,6 +95,42 @@ &i2c0 { status = "okay"; }; +&mmc0 { + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x12012>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&mt6357_vemc_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; + max-frequency = <200000000>; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&mt6357_vmch_reg>; + vqmmc-supply = <&mt6357_vmc_reg>; + status = "okay"; +}; + &mt6357_pmic { interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; @@ -118,6 +154,108 @@ pins { }; }; + mmc0_default_pins: mmc0-default-pins { + clk-pins { + pinmux = ; + bias-pull-down; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + rst-pins { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + ds-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + rst-pins { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + cd-pins { + pinmux = ; + bias-pull-up; + }; + + clk-pins { + pinmux = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = , -- GitLab From 0899813f248aebc21b4f73f7914572b5468de79a Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:15 +0200 Subject: [PATCH 433/926] arm64: dts: mediatek: add usb controller support for mt8365-evk This patch add support for SuperSpeed USB, in OTG mode, on micro connector. It also add support for the Extensible Host Controller Interface USB. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-6-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 22 +++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 6e2f3601509ef..1a5769c397c21 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -309,6 +309,28 @@ &pwm { status = "okay"; }; +&ssusb { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + usb-role-switch; + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>; + type = "micro"; + vbus-supply = <&usb_otg_vbus>; + }; +}; + +&usb_host { + vusb33-supply = <&mt6357_vusb33_reg>; + status = "okay"; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; -- GitLab From 2c3df90c20727e2b76251bc9fe44e70bf22e124b Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:16 +0200 Subject: [PATCH 434/926] arm64: dts: mediatek: add ethernet support for mt8365-evk - Enable "vibr" and "vsim2" regulators to power the ethernet chip. Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-7-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 48 +++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 1a5769c397c21..86524cbf43548 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,29 @@ optee_reserved: optee@43200000 { }; }; +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -138,6 +161,31 @@ &mt6357_pmic { }; &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ; -- GitLab From 27205cec69b0f62223836acf5789f04c9c004275 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:17 +0200 Subject: [PATCH 435/926] arm64: dts: mediatek: add OPP support for mt8365 SoC In order to have cpufreq support, this patch adds generic Operating Performance Points support. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-8-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index bb45aab2e6a9b..cfe0c67ad61f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -20,6 +20,91 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + cpu-map { cluster0 { core0 { @@ -50,6 +135,10 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -65,6 +154,10 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -80,6 +173,10 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -95,6 +192,10 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; l2: l2-cache { -- GitLab From a5fe2dbab90cf5ff007d3b6c6e83b11d19f67684 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:18 +0200 Subject: [PATCH 436/926] arm64: dts: mediatek: add cpufreq support for mt8365-evk In order to have cpufreq support, this patch adds proc-supply and sram-supply for each CPU. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-9-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 86524cbf43548..50cbaefa1a993 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,26 @@ optee_reserved: optee@43200000 { }; }; +&cpu0 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu1 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu2 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + +&cpu3 { + proc-supply = <&mt6357_vproc_reg>; + sram-supply = <&mt6357_vsram_proc_reg>; +}; + ðernet { pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; -- GitLab From e8c6b47f49884950322a46ae9bc7e06e8d3d7e9d Mon Sep 17 00:00:00 2001 From: Amjad Ouled-Ameur Date: Thu, 25 May 2023 10:33:19 +0200 Subject: [PATCH 437/926] arm64: dts: mediatek: Add CPU Idle support MT8365 has 3 CPU Idle states: - MCDI_CPU. (Multi-Core-Deep-Idle) - MCDI_CLUSTER. - DPIDLE. (Deep-Idle) Signed-off-by: Amjad Ouled-Ameur Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-10-7019f3fd0adf@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index cfe0c67ad61f8..413496c920695 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -128,6 +128,7 @@ cpu0: cpu@0 { reg = <0x0>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -147,6 +148,7 @@ cpu1: cpu@1 { reg = <0x1>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -166,6 +168,7 @@ cpu2: cpu@2 { reg = <0x2>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -185,6 +188,7 @@ cpu3: cpu@3 { reg = <0x3>; #cooling-cells = <2>; enable-method = "psci"; + cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -198,6 +202,37 @@ cpu3: cpu@3 { operating-points-v2 = <&cluster0_opp>; }; + idle-states { + entry-method = "psci"; + + CPU_MCDI: cpu-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010001>; + entry-latency-us = <300>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + + CLUSTER_MCDI: cluster-mcdi { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <350>; + exit-latency-us = <250>; + min-residency-us = <1200>; + }; + + CLUSTER_DPIDLE: cluster-dpidle { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010004>; + entry-latency-us = <300>; + exit-latency-us = <800>; + min-residency-us = <3300>; + }; + }; + l2: l2-cache { compatible = "cache"; cache-level = <2>; -- GitLab From f6c3e61c54863247594fe0cf506da590d5415b74 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:53 +0800 Subject: [PATCH 438/926] arm64: dts: mediatek: mt8186: Add MTU3 nodes Add MTU3 nodes for MT8186 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230324021258.15863-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 5e83d4e9efa41..e69e616d5e3b6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -982,6 +982,40 @@ afe: audio-controller@11210000 { status = "disabled"; }; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: usb@11200000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; + wakeup-source; + status = "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -1013,6 +1047,40 @@ mmc1: mmc@11240000 { status = "disabled"; }; + ssusb1: usb@11281000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: usb@11280000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11280000 0 0x1000>; + reg-names = "mac"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; + wakeup-source; + status = "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; -- GitLab From 36cfc08f3dd8b5ac7d33d7e53da7c994be7fd186 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:55 +0800 Subject: [PATCH 439/926] arm64: dts: mediatek: mt8186: Add SPMI node Add SPMI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230324021258.15863-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index e69e616d5e3b6..4ffc8afa1a70d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -603,6 +603,21 @@ pwrap: pwrap@1000d000 { clock-names = "spi", "wrap"; }; + spmi: spmi@10015000 { + compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; + reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts = , + ; + status = "disabled"; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8186-timer", "mediatek,mt6765-timer"; -- GitLab From 4dad4f32bad614e3f0c7491a34a19ee4ec47ff84 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:56 +0800 Subject: [PATCH 440/926] arm64: dts: mediatek: mt8186: Add ADSP node Add ADSP node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230324021258.15863-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 4ffc8afa1a70d..6702c36ee870c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -634,6 +634,22 @@ scp: scp@10500000 { interrupts = ; }; + adsp: adsp@10680000 { + compatible = "mediatek,mt8186-dsp"; + reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; + reg-names = "cfg", "sram", "sec", "bus"; + clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; + clock-names = "audiodsp", "adsp_bus"; + assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; + status = "disabled"; + }; + adsp_mailbox0: mailbox@10686000 { compatible = "mediatek,mt8186-adsp-mbox"; #mbox-cells = <0>; -- GitLab From 4121884773afa0030423f36a81d90c43a686c019 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:57 +0800 Subject: [PATCH 441/926] arm64: dts: mediatek: mt8186: Add GCE node Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230324021258.15863-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 6702c36ee870c..df647004661b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -626,6 +627,15 @@ systimer: timer@10017000 { clocks = <&clk13m>; }; + gce: mailbox@1022c000 { + compatible = "mediatek,mt8186-gce"; + reg = <0 0X1022c000 0 0x4000>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names = "gce"; + interrupts = ; + #mbox-cells = <2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8186-scp"; reg = <0 0x10500000 0 0x40000>, -- GitLab From 7e07d3322de2a683890395688225c76674b94a73 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:58 +0800 Subject: [PATCH 442/926] arm64: dts: mediatek: mt8186: Add display nodes Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230324021258.15863-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 116 +++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index df647004661b7..29dddd8c08f1a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -20,6 +20,13 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -1207,6 +1214,20 @@ mmsys: syscon@14000000 { reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8186-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; smi_common: smi@14002000 { @@ -1240,6 +1261,45 @@ larb1: smi@14004000 { power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible = "mediatek,mt8186-dpi"; reg = <0 0x1400a000 0 0x1000>; @@ -1257,6 +1317,52 @@ port { }; }; + ccorr: ccorr@1400b000 { + compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible = "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible = "mediatek,mt8186-dsi"; reg = <0 0x14013000 0 0x1000>; @@ -1290,6 +1396,16 @@ &larb13 &larb14 &larb16 &larb17 #iommu-cells = <1>; }; + rdma1: rdma@1401f000 { + compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1401f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>; -- GitLab From 1e5b6725199f276b02be8539b7545e1553cfd61e Mon Sep 17 00:00:00 2001 From: Balsam CHIHI Date: Wed, 5 Apr 2023 12:09:07 +0200 Subject: [PATCH 443/926] arm64: dts: mediatek: mt8195: Add AP domain thermal zones Add AP Domain thermal zones for the mt8195 and specify the targeted temperature thresholds. Signed-off-by: Balsam CHIHI Link: https://lore.kernel.org/r/20230405100907.53740-1-bchihi@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 180 +++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a44aae4ab9537..ae3b81dcedc41 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3262,5 +3262,185 @@ map0 { }; }; }; + + vpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; + + trips { + vpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; + + trips { + vpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; + + trips { + gpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; + + trips { + gpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + vdec-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; + + trips { + vdec_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vdec_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + img-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_IMG>; + + trips { + img_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + img_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + infra-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; + + trips { + infra_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + infra_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cam0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; + + trips { + cam0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cam1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; + + trips { + cam1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; }; -- GitLab From fee3d8eeca1a9121fff0436937b606affdbcfe7a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:28 +0200 Subject: [PATCH 444/926] arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 17019fbea0af7..a754355aad8ca 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -401,6 +402,15 @@ fhctl: clock-controller@10209f00 { status = "disabled"; }; + gce: mailbox@10212000 { + compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + #mbox-cells = <2>; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- GitLab From d9acc19bc5beddd255c1a067cf437dbb4e4d67aa Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:29 +0200 Subject: [PATCH 445/926] arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks Add the MultiMedia System node, providing clocks for the multimedia hardware blocks and their IOMMU/SMIs. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index a754355aad8ca..32858bf4645c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -654,6 +654,19 @@ mmc3: mmc@11260000 { status = "disabled"; }; + mmsys: syscon@14000000 { + compatible = "mediatek,mt6795-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6795-vdecsys"; reg = <0 0x16000000 0 0x1000>; -- GitLab From 06254e9f244a656abaf89b87c366f991e5bb9a96 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:30 +0200 Subject: [PATCH 446/926] arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs Add nodes for the multimedia IOMMU and its LARBs: this includes all but the MJC LARB, which cannot currently be used and will be added later. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-19-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 32858bf4645c8..e4389bdd9c9a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -390,6 +391,17 @@ systimer: timer@10200670 { clock-names = "clk13m"; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt6795-m4u"; + reg = <0 0x10205000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + #iommu-cells = <1>; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt6795-apmixedsys", "syscon"; reg = <0 0x10209000 0 0x1000>; @@ -667,16 +679,64 @@ mmsys: syscon@14000000 { mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + larb0: larb@14021000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14022000 { + compatible = "mediatek,mt6795-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6795-vdecsys"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; + }; + vencsys: clock-controller@18000000 { compatible = "mediatek,mt6795-vencsys"; reg = <0 0x18000000 0 0x1000>; #clock-cells = <1>; }; + + larb3: larb@18001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <3>; + power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; + }; }; }; -- GitLab From c01a6cc6fdf805c8992c1d94fddd6486a5a76dd7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:33 +0200 Subject: [PATCH 447/926] arm64: dts: mediatek: mt6795: Add PMIC Wrapper node Add the pwrap node: this is used to communicate with the PMIC(s). Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-22-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index e4389bdd9c9a4..597bce2fed729 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -374,6 +374,17 @@ timer: timer@10008000 { clocks = <&system_clk>, <&clk32k>; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt6795-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; + clock-names = "spi", "wrap"; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; -- GitLab From aef783f3e0cab893371fb5a3701bba41d1fffc94 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:35 +0200 Subject: [PATCH 448/926] arm64: dts: mediatek: Add MT6331 PMIC devicetree MT6331 is the primary PMIC for the MediaTek Helio X10 MT6795 smartphone platforms: add a devicetree describing its regulators, Real Time Clock and PMIC-keys. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-24-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6331.dtsi | 284 +++++++++++++++++++++++ 1 file changed, 284 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6331.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi new file mode 100644 index 0000000000000..d89858c73ab1b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ +#include + +&pwrap { + pmic: mt6331 { + compatible = "mediatek,mt6331"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6331regulator: mt6331regulator { + compatible = "mediatek,mt6331-regulator"; + + mt6331_vdvfs11_reg: buck-vdvfs11 { + regulator-name = "vdvfs11"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs12_reg: buck-vdvfs12 { + regulator-name = "vdvfs12"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs13_reg: buck-vdvfs13 { + regulator-name = "vdvfs13"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vdvfs14_reg: buck-vdvfs14 { + regulator-name = "vdvfs14"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vcore2_reg: buck-vcore2 { + regulator-name = "vcore2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vio18_reg: buck-vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + + mt6331_vtcxo1_reg: ldo-vtcxo1 { + regulator-name = "vtcxo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vtcxo2_reg: ldo-vtcxo2 { + regulator-name = "vtcxo2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_avdd32_aud_reg: ldo-avdd32aud { + regulator-name = "avdd32_aud"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vauxa32_reg: ldo-vauxa32 { + regulator-name = "vauxa32"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vio28_reg: ldo-vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vcamaf_reg: ldo-vcamaf { + regulator-name = "vcam_af"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vemc33_reg: ldo-vemc33 { + regulator-name = "vemc33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vgp1_reg: ldo-vgp1 { + regulator-name = "vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vmipi_reg: ldo-vmipi { + regulator-name = "vmipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vgp4_reg: ldo-vgp4 { + regulator-name = "vgp4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vusb10_reg: ldo-vusb10 { + regulator-name = "vusb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vcamio_reg: ldo-vcamio { + regulator-name = "vcam_io"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + }; + + mt6331_vsram_reg: ldo-vsram { + regulator-name = "vsram"; + regulator-min-microvolt = <1012500>; + regulator-max-microvolt = <1012500>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vgp2_reg: ldo-vgp2 { + regulator-name = "vgp2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6331_vgp3_reg: ldo-vgp3 { + regulator-name = "vgp3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vrtc_reg: ldo-vrtc { + regulator-name = "vrtc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + mt6331_vdig18_reg: ldo-vdig18 { + regulator-name = "dvdd18_dig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + }; + + mt6331rtc: mt6331rtc { + compatible = "mediatek,mt6331-rtc"; + }; + + mt6331keys: mt6331keys { + compatible = "mediatek,mt6331-keys"; + power { + linux,keycodes = ; + wakeup-source; + }; + home { + linux,keycodes = ; + }; + }; + }; +}; -- GitLab From e83a6b4bd66db07ea76b829c21a20c2b3a3aa53f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:36 +0200 Subject: [PATCH 449/926] arm64: dts: mediatek: mt6795-xperia-m5: Add MT6331 Combo PMIC This smartphone uses the Helio X10 standard MT6331+MT6332 combo PMICs: include the mt6331 devicetree and add the required interrupt. Note that despite there being two interrupts, one for MT6331 and one for MT6332, in configurations using the companion PMIC, the interrupt of the latter fires for both events on MT6331 and for ones on MT6332, while the interrupt for the main PMIC fires only for events of the main PMIC. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-25-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 507b5b567a367..7bcdfa06155b6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "mt6795.dtsi" +#include "mt6331.dtsi" / { model = "Sony Xperia M5"; @@ -239,6 +240,15 @@ pins-tx { }; }; +&pmic { + /* + * Smartphones, including the Xperia M5, are equipped with a companion + * MT6332 PMIC: when this is present, the main MT6331 PMIC will fire + * an interrupt on the companion, so we use the MT6332 IRQ GPIO. + */ + interrupts = ; +}; + &uart0 { status = "okay"; -- GitLab From 5a65dcccf483c59bf87beadbf64196b4faa2b993 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:37 +0200 Subject: [PATCH 450/926] arm64: dts: mediatek: mt6795-xperia-m5: Add eMMC, MicroSD slot, SDIO Configure and enable the MMC0/1/2 controllers, used for the eMMC chip, MicroSD card slot and SDIO (WiFi) respectively. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-26-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 7bcdfa06155b6..b5746e6d0b15a 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -17,6 +17,7 @@ / { aliases { mmc0 = &mmc0; mmc1 = &mmc1; + mmc2 = &mmc2; serial0 = &uart0; serial1 = &uart1; }; @@ -133,7 +134,97 @@ proximity@48 { }; }; +&mmc0 { + /* eMMC controller */ + mediatek,latch-ck = <0x14>; /* hs400 */ + mediatek,hs200-cmd-int-delay = <1>; + mediatek,hs400-cmd-int-delay = <1>; + mediatek,hs400-ds-dly3 = <0x1a>; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <&mt6331_vemc33_reg>; + vqmmc-supply = <&mt6331_vio18_reg>; + status = "okay"; +}; + +&mmc1 { + /* MicroSD card slot */ + vmmc-supply = <&mt6331_vmc_reg>; + vqmmc-supply = <&mt6331_vmch_reg>; + status = "okay"; +}; + +&mmc2 { + /* SDIO WiFi on MMC2 */ + vmmc-supply = <&mt6331_vmc_reg>; + vqmmc-supply = <&mt6331_vmch_reg>; + status = "okay"; +}; + &pio { + mmc0_pins_default: emmc-sdr-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up = ; + }; + }; + + mmc0_pins_uhs: emmc-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + nfc_pins: nfc-pins { pins-irq { pinmux = ; -- GitLab From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 19 Apr 2023 20:15:53 +0100 Subject: [PATCH 451/926] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64 The SPI-NOR node in the device tree of the BananaPi R64 has most likely been copied from the reference board's device tree even though the R64 comes with an SPI-NAND chip rather than SPI-NOR. Setup the Serial NAND Flash Interface (SNFI) controller, enable hardware BCH error detection and correction engine and add the SPI-NAND chip including basic partitions, Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 38 ++++++++++++++++--- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index af3fe61e40938..a333590152007 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -248,14 +248,42 @@ &nandc { status = "disabled"; }; -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; +&bch { + status = "okay"; +}; +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; flash@0 { - compatible = "jedec,spi-nor"; + compatible = "spi-nand"; reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "fip"; + reg = <0x80000 0x200000>; + read-only; + }; + + ubi: partition@280000 { + label = "ubi"; + reg = <0x280000 0x7d80000>; + }; + }; }; }; -- GitLab From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 19 Apr 2023 20:16:29 +0100 Subject: [PATCH 452/926] arm64: dts: mt7622: handle interrupts from MT7531 switch on BPI-R64 Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support") the mt7530 driver can act as an interrupt controller. Wire up irq line of the MT7531 switch on the BananaPi BPi-R64 board, so the status of the PHYs of the five 1000Base-T ports doesn't need to be polled any more. Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index a333590152007..12abca8e11a18 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -150,6 +150,10 @@ mdio: mdio-bus { switch@0 { compatible = "mediatek,mt7531"; reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&pio 54 0>; ports { -- GitLab From 04c3140312693a939ae55c8e368b79a0b8475c82 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 24 Apr 2023 18:04:09 +0800 Subject: [PATCH 453/926] arm64: dts: mediatek: mt8192-asurada-hayato: Enable Bluetooth MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hayato's Realtek WiFi/BT module has it's Bluetooth function wired to UART1. Add and enable the relevant device nodes for it. Signed-off-by: Chen-Yu Tsai Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20230424100409.2992418-1-wenst@chromium.org Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt8192-asurada-hayato-r1.dts | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index 43a823990a927..6e23428a3ed23 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -40,9 +40,90 @@ CROS_STD_MAIN_KEYMAP >; }; +&pio { + bt_pins: bt-pins { + pins-bt-kill { + pinmux = ; + output-low; + }; + + pins-bt-wake { + pinmux = ; + bias-pull-up; + }; + + pins-ap-wake-bt { + pinmux = ; + output-low; + }; + }; + + uart1_pins: uart1-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + + pins-rts { + pinmux = ; + }; + }; + + uart1_pins_sleep: uart1-sleep-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + + pins-rts { + pinmux = ; + }; + }; +}; + &touchscreen { compatible = "hid-over-i2c"; post-power-on-delay-ms = <10>; hid-descr-addr = <0x0001>; vdd-supply = <&pp3300_u>; }; + +&uart1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pins>; + pinctrl-1 = <&uart1_pins_sleep>; + /delete-property/ interrupts; + interrupts-extended = <&gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 94 IRQ_TYPE_EDGE_FALLING>; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + + enable-gpios = <&pio 144 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&pio 168 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&pio 22 GPIO_ACTIVE_LOW>; + }; +}; -- GitLab From f8fdf9ed5bfc4ed900d34d5b075a052c84e8145c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 24 Apr 2023 13:25:21 +0200 Subject: [PATCH 454/926] arm64: dts: mediatek: mt8195: Assign dp-intf aliases Assign aliases for the primary and secondary dp-intf IP to properly and reliably enable DisplayPort functionality. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Reviewed-by: Chen-Yu Tsai Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230424112523.1436926-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ae3b81dcedc41..2cef831d952b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -24,6 +24,8 @@ / { #size-cells = <2>; aliases { + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; gce0 = &gce0; gce1 = &gce1; ethdr0 = ðdr0; -- GitLab From 58d7dae894f2ce0118a9e0255ee539cd413860a3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 24 Apr 2023 13:25:23 +0200 Subject: [PATCH 455/926] arm64: dts: mediatek: cherry: Enable PCI-Express ports for WiFi On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports to enable enumerating this chip. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Reviewed-by: Chen-Yu Tsai Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230424112523.1436926-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 8ac80a136c371..d20e0ea92c5f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -464,6 +464,13 @@ flash@0 { }; }; +&pcie1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins_default>; +}; + &pio { mediatek,rsel-resistance-in-si-unit; pinctrl-names = "default"; @@ -852,6 +859,24 @@ pins-cs { }; }; + pcie0_pins_default: pcie0-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie1_pins_default: pcie1-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + pio_default: pio-default-pins { pins-wifi-enable { pinmux = ; -- GitLab From 42127f578ebde652d1373e0233356fbd351675c4 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 15 May 2023 13:13:52 -0700 Subject: [PATCH 456/926] arm64: dts: mediatek: mt8183: Add mediatek,broken-save-restore-fw to kukui Firmware shipped on mt8183 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Reviewed-by: Julius Werner Signed-off-by: Douglas Anderson Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230515131353.v2.3.I525a2ed4260046d43c885ee1275e91707743df1c@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 63952c1251dfd..8892b2f64a0f0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -292,6 +292,10 @@ dsi_out: endpoint { }; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { mali-supply = <&mt6358_vgpu_reg>; }; -- GitLab From d72cfbd6fcf7cd02084991eee47ecc9f4b4c1e69 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 15 May 2023 13:13:53 -0700 Subject: [PATCH 457/926] arm64: dts: mediatek: mt8192: Add mediatek,broken-save-restore-fw to asurada Firmware shipped on mt8192 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: 331fae2fc922 ("arm64: dts: mediatek: Introduce MT8192-based Asurada board family") Reviewed-by: Julius Werner Signed-off-by: Douglas Anderson Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230515131353.v2.4.Ie7e600278ffbed55a1e5a58178203787b1449b35@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 5a440504d4f9b..0e8b341170907 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -275,6 +275,10 @@ &dsi_out { remote-endpoint = <&anx7625_in>; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { mali-supply = <&mt6315_7_vbuck1>; status = "okay"; -- GitLab From ea6c5f21efecbaa3a14cb21c5bc0e23c84473a11 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 15 May 2023 13:13:54 -0700 Subject: [PATCH 458/926] arm64: dts: mediatek: mt8195: Add mediatek,broken-save-restore-fw to cherry Firmware shipped on mt8195 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: 5eb2e303ec6b ("arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato") Reviewed-by: Julius Werner Signed-off-by: Douglas Anderson Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230515131353.v2.5.Ia0b6ebbaa351e3cd67e201355b9ae67783c7d718@changeid Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index d20e0ea92c5f8..37a3e9de90ff7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -255,6 +255,10 @@ dptx_out: endpoint { }; }; +&gic { + mediatek,broken-save-restore-fw; +}; + &gpu { status = "okay"; mali-supply = <&mt6315_7_vbuck1>; -- GitLab From 492061bfc045d815aa5414c1a5eaf373c2fb89fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:57 +0200 Subject: [PATCH 459/926] arm64: dts: mediatek: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8186.dtsi | 2 ++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++ 4 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 006cd639059fa..36ef2dbe8add4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -101,6 +101,7 @@ cpu1: cpu@1 { L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 29dddd8c08f1a..8c02232cac38f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -258,6 +258,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -267,6 +268,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 5c30caf740265..faaff39155dca 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -228,6 +228,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -237,6 +238,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 2cef831d952b4..b53e959911999 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -285,6 +285,7 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l2_1: l2-cache1 { @@ -294,6 +295,7 @@ l2_1: l2-cache1 { cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; + cache-unified; }; l3_0: l3-cache { -- GitLab From 380d18fb2758058bf4bf037aebfafcf7b7ecbca5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 May 2023 12:11:08 +0200 Subject: [PATCH 460/926] arm64: mediatek: Propagate chassis-type where possible The chassis-type string identifies the form-factor of the system: add this property to all device trees of devices for which the form factor is known. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 + arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 + arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 + arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 + arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 + arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 + arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 + arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 + arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 + arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 + 28 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index d31a194124c91..fffdb7bbf889e 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT2712 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts index e079b7932ba34..00b14f85c6a16 100644 --- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6755 EVB"; + chassis-type = "embedded"; compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts index 164f5cbb3821d..56b1bf06e26b5 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -10,6 +10,7 @@ / { model = "MediaTek MT6779 EVB"; + chassis-type = "embedded"; compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts index 1ed2f81edeff0..e0d4d7a631394 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6795 Evaluation Board"; + chassis-type = "embedded"; compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts index 2327e752d1648..c927932afa0d6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT6797 Evaluation Board"; + chassis-type = "embedded"; compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index eff9e8dbd0769..9534cf3a09d01 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -12,6 +12,7 @@ / { model = "Mediatek X20 Development Board"; + chassis-type = "embedded"; compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 12abca8e11a18..e4605d23fdc8e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -15,6 +15,7 @@ / { model = "Bananapi BPI-R64"; + chassis-type = "embedded"; compatible = "bananapi,bpi-r64", "mediatek,mt7622"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index b74e774c6eba9..dad8e683aac5b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -15,6 +15,7 @@ / { model = "MediaTek MT7622 RFB1 board"; + chassis-type = "embedded"; compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 33bd6febc1605..7128f779c1657 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -16,6 +16,7 @@ / { model = "Bananapi BPI-R3"; + chassis-type = "embedded"; compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 4f18b4a9a8c82..3ef371ca254e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT7986a RFB"; + chassis-type = "embedded"; compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 188ce82ae56ce..dde190442e386 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -9,6 +9,7 @@ / { model = "MediaTek MT7986b RFB"; + chassis-type = "embedded"; compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts index 774a2f3fb4b29..ebf1a358f42aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts @@ -11,6 +11,7 @@ / { model = "Pumpkin MT8167"; + chassis-type = "embedded"; compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; memory@40000000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts index 28433b94f7c71..256f245ac01d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts @@ -8,6 +8,7 @@ / { model = "Google Hanawl"; + chassis-type = "laptop"; compatible = "google,hana-rev7", "mediatek,mt8173"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts index c234296755e1a..fcf0cb76a87c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts @@ -8,6 +8,7 @@ / { model = "Google Hana"; + chassis-type = "laptop"; compatible = "google,hana-rev6", "google,hana-rev5", "google,hana-rev4", "google,hana-rev3", "google,hana", "mediatek,mt8173"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts index e9e4ac0b74b2a..2390d04204e83 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts @@ -8,6 +8,7 @@ / { model = "Google Elm"; + chassis-type = "laptop"; compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", "google,elm", "mediatek,mt8173"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 755df56942345..5122963d8743a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -10,6 +10,7 @@ / { model = "MediaTek MT8173 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 3e3f4b1b00f02..d8bd518076832 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -11,6 +11,7 @@ / { model = "MediaTek MT8183 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; aliases { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts index 1a2ec0787d3ca..19c1e2bee494c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -9,6 +9,7 @@ / { model = "Google burnet board"; + chassis-type = "convertible"; compatible = "google,burnet", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts index 0eca3ff8672a7..552bfc7269994 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -9,6 +9,7 @@ / { model = "Google damu board"; + chassis-type = "convertible"; compatible = "google,damu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts index bc2c57f0a827b..8ac6bf5b17f97 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts @@ -9,6 +9,7 @@ / { model = "Google juniper sku16 board"; + chassis-type = "convertible"; compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts index 3a724e6f915cd..fcce8ea1232e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts @@ -9,6 +9,7 @@ / { model = "MediaTek kakadu board sku22"; + chassis-type = "tablet"; compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", "google,kakadu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts index 89a139a0ee444..ebfabba725075 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts @@ -9,6 +9,7 @@ / { model = "MediaTek kakadu board"; + chassis-type = "tablet"; compatible = "google,kakadu-rev3", "google,kakadu-rev2", "google,kakadu", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts index e3dd75bdaea43..7213cdcca612a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku16 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts index d81935ae07bc9..bbf0cd1aa66d1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku272 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts index f4082fbe0517a..a429ffeac3bdf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku288 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts index fb5ee91b6fe0e..4ac75806fa948 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts @@ -14,6 +14,7 @@ / { model = "MediaTek krane sku0 board"; + chassis-type = "tablet"; compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts index 721d16f9c3b4f..095279e55d50c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts @@ -14,6 +14,7 @@ / { model = "MediaTek krane sku176 board"; + chassis-type = "tablet"; compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts index ed74a3617c135..2667a7424200e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -7,6 +7,7 @@ / { model = "MediaTek MT8186 evaluation board"; + chassis-type = "embedded"; compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; aliases { -- GitLab From eabb04df46c6ca47efcb02db3285163ab6d603d2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 21 Apr 2023 15:20:44 +0200 Subject: [PATCH 461/926] arm64: dts: mt7986: add PWM This adds pwm node to mt7986. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 51944690e7901..aa9e679b78e2b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -240,6 +240,20 @@ crypto: crypto@10320000 { status = "disabled"; }; + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #clock-cells = <1>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; -- GitLab From cfde46c6add54280339f256ae1aeb75560911b85 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 21 Apr 2023 15:20:45 +0200 Subject: [PATCH 462/926] arm64: dts: mt7986: add PWM to BPI-R3 Add pwm node and pinctrl to BananaPi R3 devicetree. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 7128f779c1657..ee4127c6ece8b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -275,6 +275,13 @@ mux { }; }; + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function = "spi"; @@ -345,6 +352,12 @@ mux { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; -- GitLab From 42bdf378644b5d0a73bd42c031d4d321ad41047e Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 5 Feb 2023 18:48:33 +0100 Subject: [PATCH 463/926] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 Leds for Wifi are low-active, so add property to devicetree. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ee4127c6ece8b..be96f59e63529 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -460,5 +460,9 @@ &wifi { pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; }; -- GitLab From 9dd5f6dba72928e1f16b259fb1c984f80bfa4120 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 16 May 2023 20:35:10 +0530 Subject: [PATCH 464/926] arm64: dts: qcom: sm6115: Add USB SS qmp phy node Add USB superspeed qmp phy node to dtsi. Make sure that the various board dts files (which include sm4250.dtsi file) continue to work as intended. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516150511.2346357-4-bhupesh.sharma@linaro.org --- .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 3 ++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 29 +++++++++++++++++-- .../boot/dts/qcom/sm6115p-lenovo-j606f.dts | 3 ++ 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index a1f0622db5a0a..75951fd439dfb 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -242,6 +242,9 @@ &usb { &usb_dwc3 { maximum-speed = "high-speed"; dr_mode = "peripheral"; + + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; }; &usb_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 6ba9cd33960bd..ba889cc44cb78 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -828,6 +828,31 @@ crypto: crypto@1b3a000 { <&apps_smmu 0x9F 0>; }; + usb_qmpphy: phy@1615000 { + compatible = "qcom,sm6115-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; reg = <0x0 0x01b40000 0x0 0x7000>; @@ -1278,8 +1303,8 @@ usb_dwc3: usb@4e00000 { compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; - phys = <&usb_hsphy>; - phy-names = "usb2-phy"; + phys = <&usb_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index ea3340d31110c..81fdcaf489266 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -306,6 +306,9 @@ &usb { &usb_dwc3 { maximum-speed = "high-speed"; dr_mode = "peripheral"; + + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; }; &usb_hsphy { -- GitLab From eaa53a85748d58c4398c5c9acaa8d01d92adbb67 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 16 May 2023 20:35:11 +0530 Subject: [PATCH 465/926] arm64: dts: qcom: qrb4210-rb2: Enable USB node Enable the USB controller and HS/SS PHYs on qrb4210-rb2 board. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516150511.2346357-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index da3bc307c2f85..39597277343cf 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -467,6 +467,30 @@ &uart4 { status = "okay"; }; +&usb { + status = "okay"; +}; + +&usb_dwc3 { + maximum-speed = "super-speed"; + dr_mode = "peripheral"; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l4a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l15a_3p128>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l4a_0p9>; + vdda-pll-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + &xo_board { clock-frequency = <19200000>; }; -- GitLab From 41e22c2ff38eaea777f1158071539e659aa7980d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:46:58 +0200 Subject: [PATCH 466/926] arm64: dts: qcom: msm8916: Rename &msmgpio -> &tlmm MSM8916 is the only ARM64 Qualcomm SoC that is still using the old &msmgpio name. Change this to &tlmm to avoid confusion. Note that the node ordering does not change because the MSM8916 device trees have pinctrl separated at the bottom (similar to sc7180). Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-1-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 24 +++++------ .../boot/dts/qcom/msm8916-acer-a1-724.dts | 14 +++---- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 24 +++++------ .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 20 ++++----- .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 20 ++++----- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 34 +++++++-------- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 20 ++++----- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 16 +++---- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 2 +- .../qcom/msm8916-samsung-a2015-common.dtsi | 40 +++++++++--------- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 12 +++--- .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 6 +-- .../qcom/msm8916-samsung-e2015-common.dtsi | 6 +-- .../dts/qcom/msm8916-samsung-grandmax.dts | 6 +-- .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 14 +++---- .../boot/dts/qcom/msm8916-samsung-gt510.dts | 12 +++--- .../boot/dts/qcom/msm8916-samsung-gt58.dts | 8 ++-- .../dts/qcom/msm8916-samsung-j5-common.dtsi | 16 +++---- .../dts/qcom/msm8916-samsung-serranove.dts | 42 +++++++++---------- .../boot/dts/qcom/msm8916-thwc-uf896.dts | 8 ++-- .../boot/dts/qcom/msm8916-thwc-ufi001c.dts | 10 ++--- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 2 +- .../dts/qcom/msm8916-wingtech-wt88047.dts | 16 +++---- .../boot/dts/qcom/msm8916-yiming-uz801v3.dts | 8 ++-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 +- 25 files changed, 192 insertions(+), 192 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 1c5d558548932..82f141b55eb3c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -75,7 +75,7 @@ usb2513 { usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -101,13 +101,13 @@ gpio-keys { button { label = "Volume Up"; linux,code = ; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; }; }; leds { pinctrl-names = "default"; - pinctrl-0 = <&msmgpio_leds>, + pinctrl-0 = <&tlmm_leds>, <&pm8916_gpios_leds>, <&pm8916_mpps_leds>; @@ -117,7 +117,7 @@ led@1 { label = "apq8016-sbc:green:user1"; function = LED_FUNCTION_HEARTBEAT; color = ; - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; @@ -126,7 +126,7 @@ led@2 { label = "apq8016-sbc:green:user2"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; - gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; @@ -186,14 +186,14 @@ adv_bridge: bridge@39 { compatible = "adi,adv7533"; reg = <0x39>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; clocks = <&rpmcc RPM_SMD_BB_CLK2>; clock-names = "cec"; - pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; avdd-supply = <&pm8916_l6>; v1p2-supply = <&pm8916_l6>; @@ -276,8 +276,8 @@ camera_rear@3b { compatible = "ovti,ov5640"; reg = <0x3b>; - enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; - reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&camera_rear_default>; @@ -373,7 +373,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &sound { @@ -515,7 +515,7 @@ &i2c6_default { * ones actually used for GPIO. */ -&msmgpio { +&tlmm { gpio-line-names = "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ @@ -640,7 +640,7 @@ &msmgpio { "USR_LED_2_CTRL", /* GPIO 120 */ "SB_HS_ID"; - msmgpio_leds: msmgpio-leds-state { + tlmm_leds: tlmm-leds-state { pins = "gpio21", "gpio120"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 753413b48751a..7b77a80f049c6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -39,14 +39,14 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -58,7 +58,7 @@ &blsp_i2c2 { accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -89,10 +89,10 @@ touchscreen@38 { compatible = "edt,edt-ft5406"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l16>; iovcc-supply = <&pm8916_l6>; @@ -143,7 +143,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -165,7 +165,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 4bfbad669b1ea..d2abbdec5fe68 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -30,7 +30,7 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -42,7 +42,7 @@ gpio-leds { pinctrl-0 = <&gpio_leds_default>; led-0 { - gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; linux,default-trigger = "torch"; function = LED_FUNCTION_TORCH; }; @@ -50,7 +50,7 @@ led-0 { usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -66,9 +66,9 @@ &blsp_i2c4 { touchscreen@26 { compatible = "mstar,msg2638"; reg = <0x26>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ts_int_reset_default>; vdd-supply = <&pm8916_l17>; @@ -86,7 +86,7 @@ magnetometer@c { reg = <0x0c>; vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 8 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; mount-matrix = "0", "1", "0", @@ -99,7 +99,7 @@ accelerometer@f { reg = <0x0f>; vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <31 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&accel_int_default>; @@ -111,7 +111,7 @@ accelerometer@f { proximity@48 { compatible = "sensortek,stk3310"; reg = <0x48>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&proximity_int_default>; @@ -122,7 +122,7 @@ gyroscope@68 { reg = <0x68>; vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <97 IRQ_TYPE_EDGE_RISING>, <98 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -136,7 +136,7 @@ &blsp_i2c6 { led-controller@68 { compatible = "si-en,sn3190"; reg = <0x68>; - shutdown-gpios = <&msmgpio 89 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&led_enable_default &led_shutdown_default>; #address-cells = <1>; @@ -182,7 +182,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -202,7 +202,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio31"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 37755e8853958..c58a70fdf36fb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -30,14 +30,14 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <15>; }; button-volume-down { label = "Volume Down"; - gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <15>; }; @@ -49,7 +49,7 @@ reg_sd_vmmc: regulator-sdcard-vmmc { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - gpio = <&msmgpio 87 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <200>; @@ -60,7 +60,7 @@ reg_sd_vmmc: regulator-sdcard-vmmc { usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpios = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -76,7 +76,7 @@ magnetometer@c { vdd-supply = <&pm8916_l8>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 112 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 112 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -86,7 +86,7 @@ imu@68 { compatible = "invensense,mpu6515"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <36 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -108,10 +108,10 @@ touchscreen@38 { compatible = "edt,edt-ft5306"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l11>; iovcc-supply = <&pm8916_l6>; @@ -150,7 +150,7 @@ &sdhc_2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -170,7 +170,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio117"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 4a6bf99c755fd..221db7edec5ef 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -24,8 +24,8 @@ chosen { flash-led-controller { /* Actually qcom,leds-gpio-flash */ compatible = "sgmicro,sgm3140"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&camera_flash_default>; pinctrl-names = "default"; @@ -45,7 +45,7 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -59,21 +59,21 @@ gpio-leds { led-red { function = LED_FUNCTION_CHARGING; color = ; - gpios = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; retain-state-suspended; }; led-green { function = LED_FUNCTION_CHARGING; color = ; - gpios = <&msmgpio 118 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 118 GPIO_ACTIVE_HIGH>; retain-state-suspended; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; @@ -87,10 +87,10 @@ touchscreen@38 { compatible = "edt,edt-ft5406"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l17>; iovcc-supply = <&pm8916_l6>; @@ -138,7 +138,7 @@ &sdhc_2 { pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; pinctrl-names = "default", "sleep"; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -160,7 +160,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 29aaa35438a36..b02e8f9a8ca0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -43,7 +43,7 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -55,21 +55,21 @@ leds { pinctrl-0 = <&gpio_leds_default>; led-0 { - gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; }; led-1 { - gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; }; led-2 { - gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_INDICATOR; @@ -78,7 +78,7 @@ led-2 { usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -94,7 +94,7 @@ magnetometer@c { vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -104,7 +104,7 @@ accelerometer@1e { compatible = "kionix,kx023-1025"; reg = <0x1e>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -122,7 +122,7 @@ proximity@39 { compatible = "avago,apds9930"; reg = <0x39>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <113 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8916_l17>; @@ -146,7 +146,7 @@ reg_lcd_pos: outp { regulator-name = "outp"; regulator-min-microvolt = <5400000>; regulator-max-microvolt = <5400000>; - enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>; regulator-active-discharge = <1>; }; @@ -154,7 +154,7 @@ reg_lcd_neg: outn { regulator-name = "outn"; regulator-min-microvolt = <5400000>; regulator-max-microvolt = <5400000>; - enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; regulator-active-discharge = <1>; }; }; @@ -169,7 +169,7 @@ rmi4@70 { #address-cells = <1>; #size-cells = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&pm8916_l17>; @@ -199,11 +199,11 @@ nfc@28 { compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; reg = <0x28>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&nfc_default>; @@ -264,7 +264,7 @@ &sdhc_2 { pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; /* - * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>. + * The Huawei device tree sets cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>. * However, gpio38 does not change its state when inserting/removing the * SD card, it's just low all the time. The Huawei kernel seems to use * polling for SD card detection instead. @@ -276,7 +276,7 @@ &sdhc_2 { * Maybe Huawei decided to replace the second SIM card slot with the * SD card slot and forgot to re-route to gpio38. */ - cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; }; &sound { @@ -338,7 +338,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { accel_irq_default: accel-irq-default-state { pins = "gpio115"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index b7b1f1ceaf1f3..56f74a8927640 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -41,7 +41,7 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -53,7 +53,7 @@ reg_ctp: regulator-ctp { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -62,8 +62,8 @@ reg_ctp: regulator-ctp { flash-led-controller { compatible = "sgmicro,sgm3140"; - flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&camera_flash_default>; @@ -122,7 +122,7 @@ accelerometer@10 { * to the BMC156. However, there are two pads next to the chip * that can be shorted to make it work if needed. * - * interrupt-parent = <&msmgpio>; + * interrupt-parent = <&tlmm>; * interrupts = <116 IRQ_TYPE_EDGE_RISING>; */ @@ -141,7 +141,7 @@ magnetometer@12 { compatible = "bosch,bmc156_magn"; reg = <0x12>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <113 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -156,7 +156,7 @@ light-sensor@23 { reg = <0x23>; proximity-near-level = <75>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -170,7 +170,7 @@ gyroscope@68 { compatible = "bosch,bmg160"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <23 IRQ_TYPE_EDGE_RISING>, <22 IRQ_TYPE_EDGE_RISING>; @@ -191,7 +191,7 @@ rmi4@20 { #address-cells = <1>; #size-cells = <0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <®_ctp>; @@ -274,7 +274,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio116"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 630727ed1ed5a..a1208c8e06203 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -22,8 +22,8 @@ chosen { flash-led-controller { compatible = "ocs,ocp8110"; - enable-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; - flash-gpios = <&msmgpio 119 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&camera_front_flash_default>; pinctrl-names = "default"; @@ -45,7 +45,7 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -54,7 +54,7 @@ leds { compatible = "gpio-leds"; led-0 { - gpios = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; color = ; default-state = "off"; function = LED_FUNCTION_KBD_BACKLIGHT; @@ -66,7 +66,7 @@ led-0 { usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -82,7 +82,7 @@ magnetometer@d { vdd-supply = <&pm8916_l17>; vid-supply = <&pm8916_l6>; - reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mag_reset_default>; @@ -136,7 +136,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -156,7 +156,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { button_backlight_default: button-backlight-default-state { pins = "gpio17"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 33dfcf318a81b..1e07f70768f41 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -3,7 +3,7 @@ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. */ -&msmgpio { +&tlmm { blsp1_uart1_default: blsp1-uart1-default-state { /* TX, RX, CTS_N, RTS_N */ diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 37a872949851b..550ba6b9d4cd8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -44,13 +44,13 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -65,7 +65,7 @@ gpio-hall-sensor { event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -83,7 +83,7 @@ reg_motor_vdd: regulator-motor-vdd { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -96,7 +96,7 @@ reg_vdd_tsp_a: regulator-vdd-tsp-a { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -105,8 +105,8 @@ reg_vdd_tsp_a: regulator-vdd-tsp-a { i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -118,7 +118,7 @@ muic: extcon@25 { compatible = "siliconmitus,sm5502-muic"; reg = <0x25>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -128,8 +128,8 @@ muic: extcon@25 { i2c-tkey { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&tkey_i2c_default>; @@ -142,7 +142,7 @@ touchkey: touchkey@20 { compatible = "coreriver,tc360-touchkey"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <98 IRQ_TYPE_EDGE_FALLING>; /* vcc/vdd-supply are board-specific */ @@ -157,8 +157,8 @@ touchkey: touchkey@20 { i2c-nfc { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&nfc_i2c_default>; @@ -170,11 +170,11 @@ nfc@27 { compatible = "samsung,s3fwrn5-i2c"; reg = <0x27>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - en-gpios = <&msmgpio 20 GPIO_ACTIVE_LOW>; - wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + en-gpios = <&tlmm 20 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; @@ -200,7 +200,7 @@ &blsp_i2c2 { accelerometer: accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -225,7 +225,7 @@ &blsp_i2c4 { battery@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_BOTH>; pinctrl-names = "default"; @@ -274,7 +274,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -286,7 +286,7 @@ &usb_hs_phy { extcon = <&muic>; }; -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index a1ca4d8834201..9068aa6f7b293 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -15,7 +15,7 @@ reg_panel_vdd3: regulator-panel-vdd3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -28,7 +28,7 @@ reg_touch_key: regulator-touch-key { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -41,7 +41,7 @@ reg_key_led: regulator-key-led { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -67,7 +67,7 @@ touchscreen@20 { compatible = "zinitix,bt541"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <540>; @@ -93,7 +93,7 @@ panel@0 { vdd3-supply = <®_panel_vdd3>; vci-supply = <&pm8916_l17>; - reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>; port { panel_in: endpoint { @@ -120,7 +120,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { panel_vdd3_default: panel-vdd3-default-state { pins = "gpio9"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 4e10b8a5e9f9c..388482a1e3d9f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -15,7 +15,7 @@ reg_touch_key: regulator-touch-key { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -36,7 +36,7 @@ touchscreen@48 { compatible = "melfas,mms345l"; reg = <0x48>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <720>; @@ -71,7 +71,7 @@ &wcnss_iris { compatible = "qcom,wcn3660b"; }; -&msmgpio { +&tlmm { tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index f6c4a011fdfd2..0cdd6af7817f4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -18,7 +18,7 @@ muic: extcon@14 { compatible = "siliconmitus,sm5504-muic"; reg = <0x14>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -32,7 +32,7 @@ reg_touch_key: regulator-touch-key { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -66,7 +66,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index 4cbd68b894481..3f145dde4059f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -33,7 +33,7 @@ led-keyled { function = LED_FUNCTION_KBD_BACKLIGHT; color = ; - gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&gpio_leds_default>; @@ -42,14 +42,14 @@ led-keyled { }; ®_motor_vdd { - gpio = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; }; ®_touch_key { status = "disabled"; }; -&msmgpio { +&tlmm { gpio_leds_default: gpio-led-default-state { pins = "gpio60"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index a49e1641e59b8..cb1b6318a246d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -34,13 +34,13 @@ gpio-keys { volume-up-button { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; home-button { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -55,7 +55,7 @@ gpio-hall-sensor { hall-sensor-switch { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -74,7 +74,7 @@ fuelgauge@36 { maxim,over-heat-temp = <600>; maxim,over-volt = <4400>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&fuelgauge_int_default>; @@ -97,7 +97,7 @@ accelerometer@1d { vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l5>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "INT1"; @@ -145,7 +145,7 @@ &sdhc_2 { pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; pinctrl-names = "default", "sleep"; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -169,7 +169,7 @@ &wcnss_iris { compatible = "qcom,wcn3660b"; }; -&msmgpio { +&tlmm { accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts index 607a5dc8a5341..48111c6a2c78f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts @@ -25,7 +25,7 @@ reg_motor_vdd: regulator-motor-vdd { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <&motor_en_default>; @@ -38,7 +38,7 @@ reg_tsp_1p8v: regulator-tsp-1p8v { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <&tsp_en_default>; @@ -51,7 +51,7 @@ reg_tsp_3p3v: regulator-tsp-3p3v { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -71,20 +71,20 @@ &blsp_i2c5 { touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <®_tsp_1p8v>; vdda-supply = <®_tsp_3p3v>; - reset-gpios = <&msmgpio 114 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; pinctrl-0 = <&tsp_int_rst_default>; pinctrl-names = "default"; }; }; -&msmgpio { +&tlmm { motor_en_default: motor-en-default-state { pins = "gpio76"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts index 5d6f8383306bb..98ceaad7fcea9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts @@ -15,7 +15,7 @@ reg_vdd_tsp: regulator-vdd-tsp { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-0 = <®_tsp_en_default>; @@ -24,7 +24,7 @@ reg_vdd_tsp: regulator-vdd-tsp { vibrator { compatible = "gpio-vibrator"; - enable-gpios = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&vibrator_en_default>; pinctrl-names = "default"; @@ -37,7 +37,7 @@ &blsp_i2c5 { touchscreen@20 { compatible = "zinitix,bt532"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <768>; @@ -51,7 +51,7 @@ touchscreen@20 { }; }; -&msmgpio { +&tlmm { reg_tsp_en_default: reg-tsp-en-default-state { pins = "gpio73"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index 6192d04a58ae4..b2d2bc205ef27 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -32,7 +32,7 @@ gpio_hall_sensor: gpio-hall-sensor { event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -49,21 +49,21 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home Key"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; i2c_muic: i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -75,7 +75,7 @@ muic: extcon@25 { compatible = "siliconmitus,sm5703-muic"; reg = <0x25>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -108,7 +108,7 @@ &sdhc_2 { pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; &usb { @@ -128,7 +128,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { gpio_hall_sensor_default: gpio-hall-sensor-default-state { pins = "gpio52"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index fc4c61c4e1e6c..13a1d8828447b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -53,13 +53,13 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; button-home { label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; linux,code = ; }; }; @@ -74,7 +74,7 @@ gpio-hall-sensor { event-hall-sensor { label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; linux,can-disable; @@ -87,7 +87,7 @@ reg_vdd_tsp: regulator-vdd-tsp { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -100,7 +100,7 @@ reg_touch_key: regulator-touch-key { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -113,7 +113,7 @@ reg_key_led: regulator-key-led { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -122,8 +122,8 @@ reg_key_led: regulator-key-led { i2c-muic { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&muic_i2c_default>; @@ -135,7 +135,7 @@ muic: extcon@14 { compatible = "siliconmitus,sm5504-muic"; reg = <0x14>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -145,8 +145,8 @@ muic: extcon@14 { i2c-tkey { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&tkey_i2c_default>; @@ -158,7 +158,7 @@ touchkey@20 { compatible = "coreriver,tc360-touchkey"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <98 IRQ_TYPE_EDGE_FALLING>; vcc-supply = <®_touch_key>; @@ -174,8 +174,8 @@ touchkey@20 { i2c-nfc { compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; pinctrl-0 = <&nfc_i2c_default>; @@ -187,11 +187,11 @@ nfc@2b { compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; reg = <0x2b>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&nfc_default>; @@ -206,7 +206,7 @@ imu@6b { compatible = "st,lsm6ds3"; reg = <0x6b>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; @@ -230,7 +230,7 @@ battery@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <121 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -245,7 +245,7 @@ touchscreen@20 { compatible = "zinitix,bt541"; reg = <0x20>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; touchscreen-size-x = <540>; @@ -320,7 +320,7 @@ &wcnss_iris { compatible = "qcom,wcn3660b"; }; -&msmgpio { +&tlmm { fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts index 82e260375174d..6fe1850ba20e9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts @@ -10,19 +10,19 @@ / { }; &button_restart { - gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; &led_r { - gpios = <&msmgpio 82 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 83 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 81 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; }; &button_default { diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts index 978f0abcdf8ff..16d4a91022be6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -10,19 +10,19 @@ / { }; &button_restart { - gpios = <&msmgpio 37 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; }; &led_r { - gpios = <&msmgpio 22 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; }; &mpss { @@ -40,7 +40,7 @@ &gpio_leds_default { }; /* This selects the external SIM card slot by default */ -&msmgpio { +&tlmm { sim_ctrl_default: sim-ctrl-default-state { esim-sel-pins { pins = "gpio0", "gpio3"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 6a92190395720..f5613107ad1fe 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -126,7 +126,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { /* pins are board-specific */ button_default: button-default-state { function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 323590598113b..12ce4dc236c63 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -25,8 +25,8 @@ chosen { flash-led-controller { compatible = "ocs,ocp8110"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; - flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&camera_flash_default>; @@ -47,14 +47,14 @@ gpio-keys { button-volume-up { label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; linux,code = ; }; }; usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -67,7 +67,7 @@ imu@68 { compatible = "invensense,mpu6880"; reg = <0x68>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&pm8916_l17>; @@ -90,10 +90,10 @@ touchscreen@38 { compatible = "edt,edt-ft5506"; reg = <0x38>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; vcc-supply = <&pm8916_l17>; iovcc-supply = <&pm8916_l6>; @@ -204,7 +204,7 @@ &wcnss_iris { compatible = "qcom,wcn3620"; }; -&msmgpio { +&tlmm { camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts index 74ce6563be183..5e6ba8c58bb57 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts @@ -10,19 +10,19 @@ / { }; &button_restart { - gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>; + gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; }; &led_r { - gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; }; &led_g { - gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>; }; &led_b { - gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; }; &button_default { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 92552f3641da0..a363be2d48e92 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -992,12 +992,12 @@ etm3_out: endpoint { }; }; - msmgpio: pinctrl@1000000 { + tlmm: pinctrl@1000000 { compatible = "qcom,msm8916-pinctrl"; reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; - gpio-ranges = <&msmgpio 0 0 122>; + gpio-ranges = <&tlmm 0 0 122>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; -- GitLab From c310ca82e229124e7b373125d82ea8fdbf2f9f81 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:46:59 +0200 Subject: [PATCH 467/926] arm64: dts: qcom: msm8916/39: Rename &blsp1_uartN -> &blsp_uartN For some reason the BLSP UART controllers have a label with a number behind blsp (&blsp1_uartN) while I2C/SPI are named without (&blsp_i2cN). This is confusing, especially for proper node ordering in board DTs. Right now all board DTs are ordered as if the number behind blsp does not exist (&blsp_i2cN comes before &blsp1_uartN). Strictly speaking correct ordering would be the other way around ('1' comes before '_'). End this confusion by giving the UART controllers consistent labels. There is just one BLSP on MSM8916/39 so the number is redundant. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-2-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 8 ++++---- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 12 +++++------ .../boot/dts/qcom/msm8916-acer-a1-724.dts | 4 ++-- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 4 ++-- .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 4 ++-- .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 4 ++-- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 4 ++-- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ++-- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 8 ++++---- .../qcom/msm8916-samsung-a2015-common.dtsi | 4 ++-- .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 4 ++-- .../dts/qcom/msm8916-samsung-j5-common.dtsi | 4 ++-- .../dts/qcom/msm8916-samsung-serranove.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 4 ++-- .../dts/qcom/msm8916-wingtech-wt88047.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 +++++------ .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 2 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 20 +++++++++---------- 20 files changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 82f141b55eb3c..19bf429a973ef 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -18,8 +18,8 @@ / { compatible = "qcom,apq8016-sbc", "qcom,apq8016"; aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart1; + serial0 = &blsp_uart2; + serial1 = &blsp_uart1; usid0 = &pm8916_0; i2c0 = &blsp_i2c2; i2c1 = &blsp_i2c6; @@ -243,12 +243,12 @@ &blsp_spi5 { label = "LS-SPI0"; }; -&blsp1_uart1 { +&blsp_uart1 { status = "okay"; label = "LS-UART0"; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; label = "LS-UART1"; }; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index e75ee34cb014b..07f4c6398b41b 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -24,8 +24,8 @@ / { aliases { mmc0 = &sdhc_1; mmc1 = &sdhc_2; - serial0 = &blsp1_uart1; - serial1 = &blsp1_uart2; + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; }; bl: backlight { @@ -115,19 +115,19 @@ &blsp_i2c5 { status = "okay"; }; -&blsp1_uart1 { +&blsp_uart1 { status = "okay"; }; -&blsp1_uart1_default { +&blsp_uart1_default { pins = "gpio0", "gpio1"; }; -&blsp1_uart1_sleep { +&blsp_uart1_sleep { pins = "gpio0", "gpio1"; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 7b77a80f049c6..c864ce12c1f14 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -22,7 +22,7 @@ / { chassis-type = "tablet"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -105,7 +105,7 @@ touchscreen@38 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index d2abbdec5fe68..47580bd243eb5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -13,7 +13,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -56,7 +56,7 @@ usb_id: usb-id { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index c58a70fdf36fb..ad71695652c20 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -13,7 +13,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -124,7 +124,7 @@ touchscreen@38 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 221db7edec5ef..a2be985052a57 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -14,7 +14,7 @@ / { chassis-type = "tablet"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -105,7 +105,7 @@ touchscreen@38 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index b02e8f9a8ca0d..cbf53de44ef32 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -26,7 +26,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -210,7 +210,7 @@ nfc@28 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 56f74a8927640..facb44892dd50 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -14,7 +14,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -214,7 +214,7 @@ rmi4-f12@12 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index a1208c8e06203..707288b7eca84 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -13,7 +13,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -101,7 +101,7 @@ imu@68 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index 7c0ceb3cff45e..438eb1faee1d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -12,7 +12,7 @@ / { compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; usid0 = &pm8916_0; }; @@ -21,6 +21,6 @@ chosen { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 1e07f70768f41..3539d9029bed7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -5,7 +5,7 @@ &tlmm { - blsp1_uart1_default: blsp1-uart1-default-state { + blsp_uart1_default: blsp-uart1-default-state { /* TX, RX, CTS_N, RTS_N */ pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; @@ -14,7 +14,7 @@ blsp1_uart1_default: blsp1-uart1-default-state { bias-disable; }; - blsp1_uart1_sleep: blsp1-uart1-sleep-state { + blsp_uart1_sleep: blsp-uart1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; @@ -22,7 +22,7 @@ blsp1_uart1_sleep: blsp1-uart1-sleep-state { bias-pull-down; }; - blsp1_uart2_default: blsp1-uart2-default-state { + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -30,7 +30,7 @@ blsp1_uart2_default: blsp1-uart2-default-state { bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep-state { + blsp_uart2_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 550ba6b9d4cd8..497fc83803ef0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -8,7 +8,7 @@ / { aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -233,7 +233,7 @@ battery@35 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index cb1b6318a246d..82d94d62fbe69 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -9,7 +9,7 @@ / { aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -111,7 +111,7 @@ accelerometer@1d { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index b2d2bc205ef27..78935205ea9d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -7,7 +7,7 @@ / { aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -84,7 +84,7 @@ muic: extcon@25 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 13a1d8828447b..bd1e1e1153c00 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -28,7 +28,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -259,7 +259,7 @@ touchscreen@20 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index f5613107ad1fe..898722ee86a51 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -9,7 +9,7 @@ / { chassis-type = "embedded"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -82,7 +82,7 @@ &bam_dmux_dma { status = "okay"; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 12ce4dc236c63..930318a443a84 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -16,7 +16,7 @@ / { chassis-type = "handset"; aliases { - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { @@ -140,7 +140,7 @@ led@2 { }; }; -&blsp1_uart2 { +&blsp_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a363be2d48e92..10670cfd2a6ec 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1598,7 +1598,7 @@ blsp_dma: dma-controller@7884000 { qcom,ee = <0>; }; - blsp1_uart1: serial@78af000 { + blsp_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; interrupts = ; @@ -1607,12 +1607,12 @@ blsp1_uart1: serial@78af000 { dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; status = "disabled"; }; - blsp1_uart2: serial@78b0000 { + blsp_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b0000 0x200>; interrupts = ; @@ -1621,8 +1621,8 @@ blsp1_uart2: serial@78b0000 { dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 951d01674b784..85a8d8fe212ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -23,7 +23,7 @@ / { aliases { mmc0 = &sdhc_1; /* SDC1 eMMC slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ - serial0 = &blsp1_uart2; + serial0 = &blsp_uart2; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 778d24c8aee52..a44f7e8295133 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -660,28 +660,28 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_uart1_default: blsp1-uart1-default-state { + blsp_uart1_default: blsp-uart1-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; drive-strength = <16>; bias-disable; }; - blsp1_uart1_sleep: blsp1-uart1-sleep-state { + blsp_uart1_sleep: blsp-uart1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp1_uart2_default: blsp1-uart2-default-state { + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <16>; bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep-state { + blsp_uart2_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; @@ -1679,7 +1679,7 @@ blsp_dma: dma-controller@7884000 { qcom,ee = <0>; }; - blsp1_uart1: serial@78af000 { + blsp_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; interrupts = ; @@ -1687,13 +1687,13 @@ blsp1_uart1: serial@78af000 { clock-names = "core", "iface"; dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; pinctrl-names = "default", "sleep"; status = "disabled"; }; - blsp1_uart2: serial@78b0000 { + blsp_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b0000 0x200>; interrupts = ; @@ -1701,8 +1701,8 @@ blsp1_uart2: serial@78b0000 { clock-names = "core", "iface"; dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; pinctrl-names = "default", "sleep"; status = "disabled"; }; -- GitLab From fdfc21f65023dbbfe11dcd8f106230668ba8d9e5 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:47:00 +0200 Subject: [PATCH 468/926] arm64: dts: qcom: msm8916/39: Use consistent name for I2C/SPI pinctrl Make the labels for the BLSP I2C/SPI pinctrl consistent with the one used for UART by adding the missing blsp_ prefix. This allows having them properly grouped together. The nodes are only reordered in msm8939.dtsi for now since the pinctrl definitions in msm8916-pins.dtsi are currently still unordered anyway. (I will try fixing this in a future patch.) Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-3-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 6 +- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 48 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 48 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 504 ++++++++++----------- 4 files changed, 303 insertions(+), 303 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 19bf429a973ef..4f3d837578fd0 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -479,15 +479,15 @@ &wcnss_iris { * 2mA drive strength is not enough when connecting multiple * I2C devices with different pull up resistors. */ -&i2c2_default { +&blsp_i2c2_default { drive-strength = <16>; }; -&i2c4_default { +&blsp_i2c4_default { drive-strength = <16>; }; -&i2c6_default { +&blsp_i2c6_default { drive-strength = <16>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 3539d9029bed7..1b60d42a13c7d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -38,7 +38,7 @@ blsp_uart2_sleep: blsp-uart2-sleep-state { bias-pull-down; }; - spi1_default: spi1-default-state { + blsp_spi1_default: blsp-spi1-default-state { spi-pins { pins = "gpio0", "gpio1", "gpio3"; function = "blsp_spi1"; @@ -56,7 +56,7 @@ cs-pins { }; }; - spi1_sleep: spi1-sleep-state { + blsp_spi1_sleep: blsp-spi1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; @@ -64,7 +64,7 @@ spi1_sleep: spi1-sleep-state { bias-pull-down; }; - spi2_default: spi2-default-state { + blsp_spi2_default: blsp-spi2-default-state { spi-pins { pins = "gpio4", "gpio5", "gpio7"; function = "blsp_spi2"; @@ -82,7 +82,7 @@ cs-pins { }; }; - spi2_sleep: spi2-sleep-state { + blsp_spi2_sleep: blsp-spi2-sleep-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; @@ -90,7 +90,7 @@ spi2_sleep: spi2-sleep-state { bias-pull-down; }; - spi3_default: spi3-default-state { + blsp_spi3_default: blsp-spi3-default-state { spi-pins { pins = "gpio8", "gpio9", "gpio11"; function = "blsp_spi3"; @@ -108,7 +108,7 @@ cs-pins { }; }; - spi3_sleep: spi3-sleep-state { + blsp_spi3_sleep: blsp-spi3-sleep-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; @@ -116,7 +116,7 @@ spi3_sleep: spi3-sleep-state { bias-pull-down; }; - spi4_default: spi4-default-state { + blsp_spi4_default: blsp-spi4-default-state { spi-pins { pins = "gpio12", "gpio13", "gpio15"; function = "blsp_spi4"; @@ -134,7 +134,7 @@ cs-pins { }; }; - spi4_sleep: spi4-sleep-state { + blsp_spi4_sleep: blsp-spi4-sleep-state { pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; @@ -142,7 +142,7 @@ spi4_sleep: spi4-sleep-state { bias-pull-down; }; - spi5_default: spi5-default-state { + blsp_spi5_default: blsp-spi5-default-state { spi-pins { pins = "gpio16", "gpio17", "gpio19"; function = "blsp_spi5"; @@ -160,7 +160,7 @@ cs-pins { }; }; - spi5_sleep: spi5-sleep-state { + blsp_spi5_sleep: blsp-spi5-sleep-state { pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; @@ -168,7 +168,7 @@ spi5_sleep: spi5-sleep-state { bias-pull-down; }; - spi6_default: spi6-default-state { + blsp_spi6_default: blsp-spi6-default-state { spi-pins { pins = "gpio20", "gpio21", "gpio23"; function = "blsp_spi6"; @@ -186,7 +186,7 @@ cs-pins { }; }; - spi6_sleep: spi6-sleep-state { + blsp_spi6_sleep: blsp-spi6-sleep-state { pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; @@ -194,7 +194,7 @@ spi6_sleep: spi6-sleep-state { bias-pull-down; }; - i2c1_default: i2c1-default-state { + blsp_i2c1_default: blsp-i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; @@ -202,7 +202,7 @@ i2c1_default: i2c1-default-state { bias-disable; }; - i2c1_sleep: i2c1-sleep-state { + blsp_i2c1_sleep: blsp-i2c1-sleep-state { pins = "gpio2", "gpio3"; function = "gpio"; @@ -210,7 +210,7 @@ i2c1_sleep: i2c1-sleep-state { bias-disable; }; - i2c2_default: i2c2-default-state { + blsp_i2c2_default: blsp-i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; @@ -218,7 +218,7 @@ i2c2_default: i2c2-default-state { bias-disable; }; - i2c2_sleep: i2c2-sleep-state { + blsp_i2c2_sleep: blsp-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; @@ -226,7 +226,7 @@ i2c2_sleep: i2c2-sleep-state { bias-disable; }; - i2c3_default: i2c3-default-state { + blsp_i2c3_default: blsp-i2c3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; @@ -234,7 +234,7 @@ i2c3_default: i2c3-default-state { bias-disable; }; - i2c3_sleep: i2c3-sleep-state { + blsp_i2c3_sleep: blsp-i2c3-sleep-state { pins = "gpio10", "gpio11"; function = "gpio"; @@ -242,7 +242,7 @@ i2c3_sleep: i2c3-sleep-state { bias-disable; }; - i2c4_default: i2c4-default-state { + blsp_i2c4_default: blsp-i2c4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; @@ -250,7 +250,7 @@ i2c4_default: i2c4-default-state { bias-disable; }; - i2c4_sleep: i2c4-sleep-state { + blsp_i2c4_sleep: blsp-i2c4-sleep-state { pins = "gpio14", "gpio15"; function = "gpio"; @@ -258,7 +258,7 @@ i2c4_sleep: i2c4-sleep-state { bias-disable; }; - i2c5_default: i2c5-default-state { + blsp_i2c5_default: blsp-i2c5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; @@ -266,7 +266,7 @@ i2c5_default: i2c5-default-state { bias-disable; }; - i2c5_sleep: i2c5-sleep-state { + blsp_i2c5_sleep: blsp-i2c5-sleep-state { pins = "gpio18", "gpio19"; function = "gpio"; @@ -274,7 +274,7 @@ i2c5_sleep: i2c5-sleep-state { bias-disable; }; - i2c6_default: i2c6-default-state { + blsp_i2c6_default: blsp-i2c6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; @@ -282,7 +282,7 @@ i2c6_default: i2c6-default-state { bias-disable; }; - i2c6_sleep: i2c6-sleep-state { + blsp_i2c6_sleep: blsp-i2c6-sleep-state { pins = "gpio22", "gpio23"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 10670cfd2a6ec..b7736a07bca37 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1636,8 +1636,8 @@ blsp_i2c1: i2c@78b5000 { dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; + pinctrl-0 = <&blsp_i2c1_default>; + pinctrl-1 = <&blsp_i2c1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1653,8 +1653,8 @@ blsp_spi1: spi@78b5000 { dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; + pinctrl-0 = <&blsp_spi1_default>; + pinctrl-1 = <&blsp_spi1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1670,8 +1670,8 @@ blsp_i2c2: i2c@78b6000 { dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; + pinctrl-0 = <&blsp_i2c2_default>; + pinctrl-1 = <&blsp_i2c2_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1687,8 +1687,8 @@ blsp_spi2: spi@78b6000 { dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; + pinctrl-0 = <&blsp_spi2_default>; + pinctrl-1 = <&blsp_spi2_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1704,8 +1704,8 @@ blsp_i2c3: i2c@78b7000 { dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_default>; - pinctrl-1 = <&i2c3_sleep>; + pinctrl-0 = <&blsp_i2c3_default>; + pinctrl-1 = <&blsp_i2c3_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1721,8 +1721,8 @@ blsp_spi3: spi@78b7000 { dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; + pinctrl-0 = <&blsp_spi3_default>; + pinctrl-1 = <&blsp_spi3_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1738,8 +1738,8 @@ blsp_i2c4: i2c@78b8000 { dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; + pinctrl-0 = <&blsp_i2c4_default>; + pinctrl-1 = <&blsp_i2c4_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1755,8 +1755,8 @@ blsp_spi4: spi@78b8000 { dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; + pinctrl-0 = <&blsp_spi4_default>; + pinctrl-1 = <&blsp_spi4_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1772,8 +1772,8 @@ blsp_i2c5: i2c@78b9000 { dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; + pinctrl-0 = <&blsp_i2c5_default>; + pinctrl-1 = <&blsp_i2c5_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1789,8 +1789,8 @@ blsp_spi5: spi@78b9000 { dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; + pinctrl-0 = <&blsp_spi5_default>; + pinctrl-1 = <&blsp_spi5_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1806,8 +1806,8 @@ blsp_i2c6: i2c@78ba000 { dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; + pinctrl-0 = <&blsp_i2c6_default>; + pinctrl-1 = <&blsp_i2c6_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1823,8 +1823,8 @@ blsp_spi6: spi@78ba000 { dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; + pinctrl-0 = <&blsp_spi6_default>; + pinctrl-1 = <&blsp_spi6_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index a44f7e8295133..1196a962897f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -660,6 +660,234 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; + blsp_i2c1_default: blsp-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c1_sleep: blsp-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_default: blsp-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_sleep: blsp-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_default: blsp-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_sleep: blsp-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_default: blsp-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_sleep: blsp-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_default: blsp-i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_sleep: blsp-i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_default: blsp-i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_sleep: blsp-i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_spi1_default: blsp-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi1_sleep: blsp-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi2_default: blsp-spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi2_sleep: blsp-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi3_default: blsp-spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi3_sleep: blsp-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi4_default: blsp-spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi4_sleep: blsp-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi5_default: blsp-spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi5_sleep: blsp-spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi6_default: blsp-spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi6_sleep: blsp-spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + blsp_uart1_default: blsp-uart1-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; @@ -852,90 +1080,6 @@ ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { }; }; - i2c1_default: i2c1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_default: i2c2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c3_default: i2c3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - i2c3_sleep: i2c3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c4_default: i2c4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - i2c4_sleep: i2c4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_default: i2c5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - sdc1_default_state: sdc1-default-state { clk-pins { pins = "sdc1_clk"; @@ -1030,150 +1174,6 @@ cd-pins { }; }; - spi1_default: spi1-default-state { - spi-pins { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi1_sleep: spi1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - spi2_default: spi2-default-state { - spi-pins { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio6"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi2_sleep: spi2-sleep-state { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - spi3_default: spi3-default-state { - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio10"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi3_sleep: spi3-sleep-state { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - spi4_default: spi4-default-state { - spi-pins { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio14"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi4_sleep: spi4-sleep-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - spi5_default: spi5-default-state { - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio18"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - spi6_default: spi6-default-state { - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - drive-strength = <12>; - bias-disable; - }; - - cs-pins { - pins = "gpio22"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi6_sleep: spi6-sleep-state { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - wcnss_pin_a: wcnss-active-state { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; @@ -1716,8 +1716,8 @@ blsp_i2c1: i2c@78b5000 { clock-names = "core", "iface"; dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; + pinctrl-0 = <&blsp_i2c1_default>; + pinctrl-1 = <&blsp_i2c1_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1733,8 +1733,8 @@ blsp_spi1: spi@78b5000 { clock-names = "core", "iface"; dmas = <&blsp_dma 4>, <&blsp_dma 5>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; + pinctrl-0 = <&blsp_spi1_default>; + pinctrl-1 = <&blsp_spi1_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1750,8 +1750,8 @@ blsp_i2c2: i2c@78b6000 { clock-names = "core", "iface"; dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; + pinctrl-0 = <&blsp_i2c2_default>; + pinctrl-1 = <&blsp_i2c2_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1767,8 +1767,8 @@ blsp_spi2: spi@78b6000 { clock-names = "core", "iface"; dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; + pinctrl-0 = <&blsp_spi2_default>; + pinctrl-1 = <&blsp_spi2_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1784,8 +1784,8 @@ blsp_i2c3: i2c@78b7000 { clock-names = "core", "iface"; dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c3_default>; - pinctrl-1 = <&i2c3_sleep>; + pinctrl-0 = <&blsp_i2c3_default>; + pinctrl-1 = <&blsp_i2c3_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1801,8 +1801,8 @@ blsp_spi3: spi@78b7000 { clock-names = "core", "iface"; dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; + pinctrl-0 = <&blsp_spi3_default>; + pinctrl-1 = <&blsp_spi3_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1818,8 +1818,8 @@ blsp_i2c4: i2c@78b8000 { clock-names = "core", "iface"; dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; + pinctrl-0 = <&blsp_i2c4_default>; + pinctrl-1 = <&blsp_i2c4_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1835,8 +1835,8 @@ blsp_spi4: spi@78b8000 { clock-names = "core", "iface"; dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; + pinctrl-0 = <&blsp_spi4_default>; + pinctrl-1 = <&blsp_spi4_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1852,8 +1852,8 @@ blsp_i2c5: i2c@78b9000 { clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; + pinctrl-0 = <&blsp_i2c5_default>; + pinctrl-1 = <&blsp_i2c5_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1869,8 +1869,8 @@ blsp_spi5: spi@78b9000 { clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; + pinctrl-0 = <&blsp_spi5_default>; + pinctrl-1 = <&blsp_spi5_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1886,8 +1886,8 @@ blsp_i2c6: i2c@78ba000 { clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; + pinctrl-0 = <&blsp_i2c6_default>; + pinctrl-1 = <&blsp_i2c6_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; @@ -1903,8 +1903,8 @@ blsp_spi6: spi@78ba000 { clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; + pinctrl-0 = <&blsp_spi6_default>; + pinctrl-1 = <&blsp_spi6_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; -- GitLab From 835f939501769253eb7eb2dc5389b8592a63a3ed Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:47:01 +0200 Subject: [PATCH 469/926] arm64: dts: qcom: msm8916/39: Clean up MDSS labels Right now MDSS related definitions cannot be properly grouped together in board DTs because the labels do not use consistent prefixes. The DSI PHY label is particularly weird because the DSI number is at the end (&dsi_phy0) while DSI itself is called &dsi0. Follow the example of more recent SoCs and give all the MDSS related nodes a consistent label that allows proper grouping. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-4-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 12 ++--- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 4 +- .../qcom/msm8916-samsung-a2015-common.dtsi | 10 ++-- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 6 +-- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 +++++------ arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/msm8939.dtsi | 46 +++++++++---------- 8 files changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 4f3d837578fd0..9081825c95746 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -211,7 +211,7 @@ ports { port@0 { reg = <0>; adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -301,11 +301,6 @@ ov5640_ep: endpoint { }; }; -&dsi0_out { - data-lanes = <0 1 2 3>; - remote-endpoint = <&adv7533_in>; -}; - &lpass { status = "okay"; }; @@ -318,6 +313,11 @@ &mdss { status = "okay"; }; +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + &mpss { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 64d7228bee07d..4e7289e6d22da 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -15,12 +15,12 @@ &camss { vdda-supply = <&pm8916_l2>; }; -&dsi0 { +&mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; }; -&dsi_phy0 { +&mdss_dsi0_phy { vddio-supply = <&pm8916_l6>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 497fc83803ef0..b1af9c5d07b25 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -237,16 +237,16 @@ &blsp_uart2 { status = "okay"; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_default>; pinctrl-1 = <&mdss_sleep>; }; -&mdss { - status = "okay"; -}; - &pm8916_resin { status = "okay"; linux,code = ; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 9068aa6f7b293..e5a569698c4f2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -85,7 +85,7 @@ &clk_pwm { status = "okay"; }; -&dsi0 { +&mdss_dsi0 { panel@0 { reg = <0>; @@ -97,13 +97,13 @@ panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { data-lanes = <0 1>; remote-endpoint = <&panel_in>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 898722ee86a51..ac39ac6a21c16 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -86,7 +86,7 @@ &blsp_uart2 { status = "okay"; }; -/* Remove &dsi_phy0 from clocks to make sure that gcc probes with display disabled */ +/* Remove &mdss_dsi0_phy from clocks to make sure that gcc probes with display disabled */ &gcc { clocks = <&xo_board>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index b7736a07bca37..ff1834a624eb0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1011,8 +1011,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&xo_board>, <&sleep_clk>, - <&dsi_phy0 1>, - <&dsi_phy0 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, <0>, <0>, <0>; @@ -1061,7 +1061,7 @@ mdss: display-subsystem@1a00000 { #size-cells = <1>; ranges; - mdp: display-controller@1a01000 { + mdss_mdp: display-controller@1a01000 { compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; @@ -1086,14 +1086,14 @@ ports { port@0 { reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; }; }; }; }; - dsi0: dsi@1a98000 { + mdss_dsi0: dsi@1a98000 { compatible = "qcom,msm8916-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a98000 0x25c>; @@ -1104,8 +1104,8 @@ dsi0: dsi@1a98000 { assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -1119,7 +1119,7 @@ dsi0: dsi@1a98000 { "byte", "pixel", "core"; - phys = <&dsi_phy0>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -1130,20 +1130,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi_phy0: phy@1a98300 { + mdss_dsi0_phy: phy@1a98300 { compatible = "qcom,dsi-phy-28nm-lp"; reg = <0x01a98300 0xd4>, <0x01a98500 0x280>, diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index 24393a1590580..33e02f42f5e4e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -3,21 +3,21 @@ #include "msm8939.dtsi" #include "pm8916.dtsi" -&dsi0 { +&mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; }; -&dsi1 { - vdda-supply = <&pm8916_l2>; +&mdss_dsi0_phy { vddio-supply = <&pm8916_l6>; }; -&dsi_phy0 { +&mdss_dsi1 { + vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; }; -&dsi_phy1 { +&mdss_dsi1_phy { vddio-supply = <&pm8916_l6>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 1196a962897f5..0d9f8b951b66e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1187,8 +1187,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&dsi_phy0 1>, - <&dsi_phy0 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, <0>, <0>, <0>; @@ -1240,7 +1240,7 @@ mdss: display-subsystem@1a00000 { status = "disabled"; - mdp: display-controller@1a01000 { + mdss_mdp: display-controller@1a01000 { compatible = "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; @@ -1269,21 +1269,21 @@ ports { port@0 { reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; - mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + mdss_mdp_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@1a98000 { + mdss_dsi0: dsi@1a98000 { compatible = "qcom,msm8916-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a98000 0x25c>; @@ -1306,10 +1306,10 @@ dsi0: dsi@1a98000 { "core"; assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; - phys = <&dsi_phy0>; + phys = <&mdss_dsi0_phy>; status = "disabled"; #address-cells = <1>; @@ -1321,20 +1321,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi_phy0: phy@1a98300 { + mdss_dsi0_phy: phy@1a98300 { compatible = "qcom,dsi-phy-28nm-lp"; reg = <0x01a98300 0xd4>, <0x01a98500 0x280>, @@ -1352,7 +1352,7 @@ dsi_phy0: phy@1a98300 { status = "disabled"; }; - dsi1: dsi@1aa0000 { + mdss_dsi1: dsi@1aa0000 { compatible = "qcom,msm8916-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01aa0000 0x25c>; @@ -1375,9 +1375,9 @@ dsi1: dsi@1aa0000 { "core"; assigned-clocks = <&gcc BYTE1_CLK_SRC>, <&gcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; - phys = <&dsi_phy1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + phys = <&mdss_dsi1_phy>; status = "disabled"; ports { @@ -1386,20 +1386,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&mdp5_intf2_out>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi_phy1: phy@1aa0300 { + mdss_dsi1_phy: phy@1aa0300 { compatible = "qcom,dsi-phy-28nm-lp"; reg = <0x01aa0300 0xd4>, <0x01aa0500 0x280>, -- GitLab From 274cf2bdd6c94da2bf293f5a6c9a5f712dd4b01e Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:47:02 +0200 Subject: [PATCH 470/926] arm64: dts: qcom: pm8916: Rename &wcd_codec -> &pm8916_codec All definitions in pm8916.dtsi use the &pm8916_ label prefix, only the codec uses the &wcd_codec label. &wcd_codec is confusing because the codec on MSM8916 is split into a "wcd-digital" and "wcd-analog" part and both could be described with &wcd_codec. Let's just name it &pm8916_codec so it's consistent with all other PMIC device nodes. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-5-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 20 +++++++++---------- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 18 ++++++++--------- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 20 +++++++++---------- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 12 +++++------ arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- 5 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9081825c95746..923646766ef1c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -324,6 +324,14 @@ &mpss { firmware-name = "qcom/apq8016/mba.mbn", "qcom/apq8016/modem.mbn"; }; +&pm8916_codec { + status = "okay"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -403,7 +411,7 @@ cpu { sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; }; }; @@ -413,7 +421,7 @@ cpu { sound-dai = <&lpass MI2S_TERTIARY>; }; codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; }; }; }; @@ -431,14 +439,6 @@ &usb_hs_phy { extcon = <&usb_id>; }; -&wcd_codec { - status = "okay"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; -}; - &wcnss { status = "okay"; firmware-name = "qcom/apq8016/wcnss.mbn"; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 07f4c6398b41b..e783b0af355e1 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -139,6 +139,13 @@ &mdss { status = "okay"; }; +&pm8916_codec { + qcom,hphl-jack-type-normally-open; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + &pm8916_gpios { gpio-line-names = "PM_GPIO1", /* WIFI_GPIO1_PRE */ @@ -265,7 +272,7 @@ cpu { sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; }; }; @@ -275,7 +282,7 @@ cpu { sound-dai = <&lpass MI2S_TERTIARY>; }; codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; }; }; }; @@ -476,13 +483,6 @@ otg_ep: endpoint { }; }; -&wcd_codec { - qcom,hphl-jack-type-normally-open; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; - status = "okay"; -}; - &wcnss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index cbf53de44ef32..1334bfcf3ceeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -222,6 +222,14 @@ &lpass_codec { status = "okay"; }; +&pm8916_codec { + status = "okay"; + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + &pm8916_l8 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; @@ -298,7 +306,7 @@ cpu { sound-dai = <&lpass MI2S_PRIMARY>; }; codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; }; }; @@ -308,7 +316,7 @@ cpu { sound-dai = <&lpass MI2S_TERTIARY>; }; codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; }; }; }; @@ -322,14 +330,6 @@ &usb_hs_phy { extcon = <&usb_id>; }; -&wcd_codec { - status = "okay"; - qcom,micbias-lvl = <2800>; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; - qcom,hphl-jack-type-normally-open; -}; - &wcnss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 4e7289e6d22da..b1a7eafbee31f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -28,6 +28,12 @@ &mpss { pll-supply = <&pm8916_l7>; }; +&pm8916_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + &sdhc_1 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -43,12 +49,6 @@ &usb_hs_phy { v3p3-supply = <&pm8916_l13>; }; -&wcd_codec { - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; -}; - &wcnss { vddpx-supply = <&pm8916_l7>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 864bb1cd68dbf..1ea8920ff3694 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -139,7 +139,7 @@ pm8916_vib: vibrator@c000 { status = "disabled"; }; - wcd_codec: audio-codec@f000 { + pm8916_codec: audio-codec@f000 { compatible = "qcom,pm8916-wcd-analog-codec"; reg = <0xf000>; reg-names = "pmic-codec-core"; -- GitLab From 154f23a8d70cd39158cfdcfb71c112f687352da4 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 29 May 2023 14:47:03 +0200 Subject: [PATCH 471/926] arm64: dts: qcom: msm8916: Move aliases to boards MSM8939 has the aliases defined separately for each board (because there could be (theoretically) a board where the slots are numbered differently. To make MSM8916 and MSM8939 more consistent do the same for all MSM8916 boards and move aliases there. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-msm8916-labels-v1-6-bec0f5fb46fb@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts | 2 ++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 ----- 15 files changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 923646766ef1c..56dfca61253e6 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -18,6 +18,8 @@ / { compatible = "qcom,apq8016-sbc", "qcom,apq8016"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; serial1 = &blsp_uart1; usid0 = &pm8916_0; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index c864ce12c1f14..5025c08e48173 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -22,6 +22,8 @@ / { chassis-type = "tablet"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 47580bd243eb5..7b629243ef0d7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -13,6 +13,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index ad71695652c20..b8c217b04a3b9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -13,6 +13,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index a2be985052a57..56c42b0c97336 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -14,6 +14,8 @@ / { chassis-type = "tablet"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 1334bfcf3ceeb..175ca011998c6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -26,6 +26,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index facb44892dd50..9560ba632c6fb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -14,6 +14,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 707288b7eca84..f23cfb2bf7934 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -13,6 +13,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index b1af9c5d07b25..895036fb6eb89 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -8,6 +8,8 @@ / { aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 82d94d62fbe69..94cfb3200496c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -9,6 +9,8 @@ / { aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index 78935205ea9d3..f2a5800f1605b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -7,6 +7,8 @@ / { aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index bd1e1e1153c00..3637e7d80d0a0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -28,6 +28,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index ac39ac6a21c16..dafa5bd823289 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -9,6 +9,7 @@ / { chassis-type = "embedded"; aliases { + mmc0 = &sdhc_1; /* eMMC */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 930318a443a84..733917531218c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -16,6 +16,8 @@ / { chassis-type = "handset"; aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ serial0 = &blsp_uart2; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index ff1834a624eb0..cc5d3cf647213 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -18,11 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - }; - chosen { }; memory@80000000 { -- GitLab From 0cf765e598712addec34d0208cc1418c151fefb2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 02:42:32 +0200 Subject: [PATCH 472/926] ARM: dts: stm32: Shorten the AV96 HDMI sound card name Fix the following error in kernel log due to too long sound card name: " asoc-audio-graph-card sound: ASoC: driver name too long 'STM32MP1-AV96-HDMI' -> 'STM32MP1-AV96-H' " Fixes: e027da342772 ("ARM: dts: stm32: Add bindings for audio on AV96") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 302efac5d26f0..2b52515457e4b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -87,7 +87,7 @@ sd_switch: regulator-sd_switch { sound { compatible = "audio-graph-card"; - label = "STM32MP1-AV96-HDMI"; + label = "STM32-AV96-HDMI"; dais = <&sai2a_port>; status = "okay"; }; -- GitLab From 0c211488ef36db3d52c8b8ae9931e508272f5a11 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:56 +0200 Subject: [PATCH 473/926] ARM: dts: stm32: fix warnings on stm32f469-disco board Several warnings appear when building and checking stm32f429 device-tree: arch/arm/boot/dts/stm32f469-disco.dts:182.28-184.5: Warning (unit_address_vs_reg): /soc/display-controller@40016800/port/endpoint@0: node has a unit name, but no reg or ranges property .../arch/arm/boot/dts/stm32f469-disco.dtb: dsi@40016c00: Unevaluated properties are not allowed ('panel-dsi@0' was unexpected) From schema: .../Documentation/devicetree/bindings/display/st,stm32-dsi.yaml Fix those. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f469-disco.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 5a0daf8e8b118..cbbd521bf0108 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -160,7 +160,7 @@ dsi_out: endpoint { }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; @@ -179,7 +179,7 @@ <dc { status = "okay"; port { - ltdc_out_dsi: endpoint@0 { + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in>; }; }; -- GitLab From 45e418bd528f5c1ed6b8de7596cf523f10f74b7b Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:57 +0200 Subject: [PATCH 474/926] dt-bindings: display: st,stm32-dsi: Remove unnecessary fields "#address-cells" and "#size-cells" are two properties that are not mandatory. For instance, the DSI could refer to a bridge outside the scope of the node rather than include a 'panel@0' subnode. By doing so, address and size fields become then unnecessary, creating a warning at build time. Signed-off-by: Raphael Gallais-Pou Acked-by: Conor Dooley Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml index c488308d7be13..53560052aaf00 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml @@ -74,8 +74,6 @@ properties: - const: 2 required: - - "#address-cells" - - "#size-cells" - compatible - reg - clocks -- GitLab From f7164b346a9009e5b70671bb72e32e1cc22a90b4 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:58 +0200 Subject: [PATCH 475/926] ARM: dts: stm32: fix dsi warnings on stm32mp15 boards Fixes DSI related warnings: * "#size-cells" and "#address-cells" wrongly used * Changed 'panel-dsi@0' to 'panel@0' according to dsi-controller.yaml Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157.dtsi | 7 ------- .../boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 3 +++ arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 3 +++ arch/arm/boot/dts/stm32mp157c-dk2.dts | 5 +++++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 7 ++++++- 5 files changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 54e73ccea4464..5e733cd16ff9e 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -24,14 +24,7 @@ dsi: dsi@5a000000 { clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 9a2a4bc7d0793..47d03bd9ef0b7 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -49,6 +49,9 @@ &dsi { phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index 390ee8c057547..d2f68997a471b 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -49,6 +49,9 @@ &dsi { phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in_ltdc: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index ab13e340f4ef5..0067c6248cd18 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -31,10 +31,15 @@ &cryp1 { }; &dsi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index ba8e9d9a42faf..67c6b9440878e 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -101,9 +101,14 @@ dcmi_0: endpoint { &dsi { phy-dsi-supply = <®18>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { reg = <0>; dsi_in: endpoint { @@ -119,7 +124,7 @@ dsi_out: endpoint { }; }; - panel-dsi@0 { + panel@0 { compatible = "raydium,rm68200"; reg = <0>; reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; -- GitLab From 5364e37799c83d405175b2e1e1065c7c247949b3 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 29 May 2023 11:13:59 +0200 Subject: [PATCH 476/926] ARM: dts: stm32: fix ltdc warnings in stm32mp15 boards Those concern: * "#size-cells" and "#address-cells" wrongly used * residual "reg" property appearing on endpoints where it could be avoided Signed-off-by: Raphael Gallais-Pou Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 ----- .../boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 3 +-- arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 3 +-- .../dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 3 +-- arch/arm/boot/dts/stm32mp157c-dk2.dts | 3 +++ arch/arm/boot/dts/stm32mp157c-ev1.dts | 3 +-- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 3 +-- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 +----- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 3 +-- 9 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index a98ae58e2c1c8..bf3830dca7428 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1529,11 +1529,6 @@ ltdc: display-controller@5a001000 { clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - }; }; iwdg2: watchdog@5a002000 { diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 47d03bd9ef0b7..4279b26547dfd 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -107,8 +107,7 @@ <dc { status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index d2f68997a471b..efba542898207 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -107,8 +107,7 @@ <dc { status = "okay"; port { - ltdc_out_dsi: endpoint@0 { - reg = <0>; + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in_ltdc>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 0d7560ba2950f..5116a77852013 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -81,8 +81,7 @@ <dc { status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 0067c6248cd18..4bef2300ed7ca 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -87,6 +87,9 @@ <dc { status = "okay"; port { + #address-cells = <1>; + #size-cells = <0>; + ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 67c6b9440878e..49ca94c19b02b 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -244,8 +244,7 @@ <dc { status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&dsi_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 407ed3952f75d..eada9cf257be9 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -161,8 +161,7 @@ <dc { status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&panel_input>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 2b52515457e4b..cdd4902b59a97 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -336,11 +336,7 @@ <dc { status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&adv7513_in>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 0f1110e42c939..a6e2e20f12fa0 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -457,8 +457,7 @@ <dc { status = "okay"; port { - ltdc_ep0_out: endpoint@0 { - reg = <0>; + ltdc_ep0_out: endpoint { remote-endpoint = <&sii9022_in>; }; }; -- GitLab From 2f6905307a7bb998e819c03097f3cc54a51b015a Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Fri, 19 May 2023 21:06:23 +0200 Subject: [PATCH 477/926] ARM: dts: exynos: Fix some typos in comments Change 'specfic' to 'specific', 'optiosn' to 'options' and remove duplicated 'are listed' in DTSI heading comments. Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230519190625.7844-2-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 4 ++-- arch/arm/boot/dts/exynos3250.dtsi | 2 +- arch/arm/boot/dts/exynos4.dtsi | 2 +- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 4 ++-- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 4 ++-- arch/arm/boot/dts/exynos5.dtsi | 2 +- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 2 +- arch/arm/boot/dts/exynos5410.dtsi | 2 +- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 2 +- arch/arm/boot/dts/exynos5800.dtsi | 2 +- 14 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index 011ba2eff29eb..07828551d4b3a 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2014 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index bd37f1b587f03..3f1015edab436 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 4340253310415..f775b9377a38b 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -9,7 +9,7 @@ * * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular * SoCs from Exynos4 series can include this file and provide values for SoCs - * specfic bindings. + * specific bindings. * * Note: This file does not include device nodes for all the controllers in * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 76f44ae0de469..70d268f9fcb19 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -7,8 +7,8 @@ * Copyright (c) 2011-2012 Linaro Ltd. * www.linaro.org * - * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 8660c4c76e3a6..dcbe0ce6180fe 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 9f7ea5f2a91ff..04935fbe2f2a4 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 48e43b6b3213a..4a17a19586bb1 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -7,7 +7,7 @@ * * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular * SoCs from Exynos5 series can include this file and provide values for SoCs - * specfic bindings. + * specific bindings. */ #include diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 48732edadff15..d956540a2d88a 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -5,8 +5,8 @@ * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device - * tree nodes are listed in this file. + * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 1a4c6c028d038..99c84bebf25a4 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5250 SoC device nodes are listed in this file. * Exynos5250 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. * * Note: This file does not include device nodes for all the controllers in * Exynos5250 SoC. As device tree coverage for Exynos5250 increases, diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 43e4a541f4798..d15494b4bda9a 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 350b8afa0a3a0..546035e78f404 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5410 SoC device nodes are listed in this file. * Exynos5410 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos54xx.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 14cf9c4ca0ed7..93b9873fa84fd 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -6,7 +6,7 @@ * http://www.samsung.com * * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. + * tree nodes in this file. */ #include "exynos-pinctrl.h" diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index dd291f1199f28..25ed90374679a 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5420 SoC device nodes are listed in this file. * Exynos5420 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos54xx.dtsi" diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 8328ddb3b02f9..72d3a3535a7ae 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -7,7 +7,7 @@ * * Samsung Exynos5800 SoC device nodes are listed in this file. * Exynos5800 based board files can include this file and provide - * values for board specfic bindings. + * values for board specific bindings. */ #include "exynos5420.dtsi" -- GitLab From 316c31fba6eda4543d5e234b13d0c0605a83a643 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Fri, 19 May 2023 21:06:24 +0200 Subject: [PATCH 478/926] ARM: dts: s3c64xx: Fix some typos in comments Change 'specfic' to 'specific'. Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230519190625.7844-3-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s3c6400.dtsi | 2 +- arch/arm/boot/dts/s3c6410.dtsi | 2 +- arch/arm/boot/dts/s3c64xx.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi index 8c28e8a0c8244..7cc785a638668 100644 --- a/arch/arm/boot/dts/s3c6400.dtsi +++ b/arch/arm/boot/dts/s3c6400.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Tomasz Figa * * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi index a766d6de696c5..13e9cc69b8a80 100644 --- a/arch/arm/boot/dts/s3c6410.dtsi +++ b/arch/arm/boot/dts/s3c6410.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Tomasz Figa * * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index c03df63555000..0b59135ffe880 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -6,7 +6,7 @@ * * Samsung's S3C64xx SoC series device nodes are listed in this file. * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. + * values for SoCs specific bindings. * * Note: This file does not include device nodes for all the controllers in * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional -- GitLab From 6a988251c4e53da33107c1975f578904c0635b43 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Fri, 19 May 2023 21:06:25 +0200 Subject: [PATCH 479/926] ARM: dts: s5pv210: Fix typo in comments, fix pinctrl header Change 'specfic' to 'specific' and make the pinctrl DTSI header more like the s3c64xx pinctrl DTSI (previously it was copied from the main s5pv210 DTSI, and not changed to match the new contents). Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230519190625.7844-4-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 12 ++++-------- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index ae0b4a4237465..af740abd9e0f4 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -1,19 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Samsung's S5PV210 SoC device tree source + * Samsung's S5PV210 SoC device tree source - pin control-related + * definitions * * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd. * * Mateusz Krawczuk * Tomasz Figa * - * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S5PV210 SoC. As device tree coverage for S5PV210 increases, additional - * nodes can be added to this file. + * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are + * listed as device tree nodes in this file. */ #include "s5pv210-pinctrl.h" diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index faa3682ab5dde..f7de5b5f2f383 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -8,7 +8,7 @@ * Tomasz Figa * * Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210 - * based board files can include this file and provide values for board specfic + * based board files can include this file and provide values for board specific * bindings. * * Note: This file does not include device nodes for all the controllers in -- GitLab From a0f19091d4f5bbe97485592257b88007eb5b1998 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 14 Apr 2023 15:57:47 +0200 Subject: [PATCH 480/926] ARM: dts: qcom: msm8660: Fix regulator node names commit 04715461abf7 altered the node names in a DTSI file used by qcom-apq8060-dragonboard.dts breaking the board. Align the node names in the DTS file and the board boots again. Cc: stable@vger.kernel.org Fixes: 85055a1eecc1 ("ARM: dts: qcom-msm8660: align RPM regulators node name with bindings") Signed-off-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230414135747.34994-1-linus.walleij@linaro.org --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 8e4b61e4d4b17..e8fe321f3d89b 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -451,7 +451,7 @@ &rpm { * PM8901 supplies "preliminary regulators" whatever * that means */ - pm8901-regulators { + regulators-0 { vdd_l0-supply = <&pm8901_s4>; vdd_l1-supply = <&vph>; vdd_l2-supply = <&vph>; @@ -537,7 +537,7 @@ lvs0 { }; - pm8058-regulators { + regulators-1 { vdd_l0_l1_lvs-supply = <&pm8058_s3>; vdd_l2_l11_l12-supply = <&vph>; vdd_l3_l4_l5-supply = <&vph>; -- GitLab From 392a1aab14542a9e393f89c985679cf3ac161156 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 08:53:18 +0200 Subject: [PATCH 481/926] ARM: dts: qcom: msm8974: drop unit addresses from USB phys The ulpi node does not allow children to have unit address: Warning (unit_address_vs_reg): /soc/usb@f9a55000/ulpi/phy@a: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420065318.23503-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 38d3ee152dcb4..9f0a6d7a38677 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -675,7 +675,7 @@ usb: usb@f9a55000 { #reset-cells = <1>; ulpi { - usb_hs1_phy: phy@a { + usb_hs1_phy: phy-0 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; @@ -686,7 +686,7 @@ usb_hs1_phy: phy@a { status = "disabled"; }; - usb_hs2_phy: phy@b { + usb_hs2_phy: phy-1 { compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; #phy-cells = <0>; -- GitLab From edcbdd57de499305e2a3737d4a73fe387f71d84c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:28:11 +0200 Subject: [PATCH 482/926] ARM: dts: qcom: ipq4019: fix broken NAND controller properties override After renaming NAND controller node name from "qpic-nand" to "nand-controller", the board DTS/DTSI also have to be updated: Warning (unit_address_vs_reg): /soc/qpic-nand@79b0000: node has a unit name, but no reg or ranges property Cc: Fixes: 9e1e00f18afc ("ARM: dts: qcom: Fix node name for NAND controller node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420072811.36947-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8 ++++---- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 10 +++++----- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 12 ++++++------ 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts index 79b0c6318e527..0993f840d1fc7 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts @@ -11,9 +11,9 @@ soc { dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - status = "okay"; - }; }; }; + +&nand { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index a63b3778636d4..468ebc40d2ad3 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -102,10 +102,10 @@ pci@40000000 { status = "okay"; perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi index 0107f552f5204..7ef635997efa4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi @@ -65,11 +65,11 @@ i2c@78b7000 { /* BLSP1 QUP2 */ dma-controller@7984000 { status = "okay"; }; - - qpic-nand@79b0000 { - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - status = "okay"; - }; }; }; + +&nand { + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- GitLab From e054c9c38f439613a2c4dd81db46909ba532b1b9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:44 +0200 Subject: [PATCH 483/926] ARM: dts: qcom: ipq4019: correct syscon unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/syscon@1fcb000: simple-bus unit address format error, expected "1fc0000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 342c3d14001eb..72d82a9a6cc5d 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -515,7 +515,7 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; - tcsr: syscon@1fcb000 { + tcsr: syscon@1fc0000 { compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; -- GitLab From fd9936dfe45765bd74c8100b8e228675482cd3ca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:45 +0200 Subject: [PATCH 484/926] ARM: dts: qcom: sdx55: correct rsc unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/rsc@17840000: simple-bus unit address format error, expected "17830000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 72d82a9a6cc5d..06c2646dd673d 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -792,7 +792,7 @@ frame@17829000 { }; }; - apps_rsc: rsc@17840000 { + apps_rsc: rsc@17830000 { compatible = "qcom,rpmh-rsc"; reg = <0x17830000 0x10000>, <0x17840000 0x10000>; reg-names = "drv-0", "drv-1"; -- GitLab From dcbd24008bfa9b2fc63ea34092b036f3f76b35db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:46 +0200 Subject: [PATCH 485/926] ARM: dts: qcom: msm8974: correct pronto unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/remoteproc@fb21b000: simple-bus unit address format error, expected "fb204000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9f0a6d7a38677..b30d598441365 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -706,7 +706,7 @@ rng@f9bff000 { clock-names = "core"; }; - pronto: remoteproc@fb21b000 { + pronto: remoteproc@fb204000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; -- GitLab From 1c7d01ba0f36ad7f7c5f6f7fd7b69375d97350e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:47 +0200 Subject: [PATCH 486/926] ARM: dts: qcom: ipq8064: drop leading 0 from unit-address Unit-address should not start with 0: Warning (simple_bus_reg): /soc/syscon@03000000: simple-bus unit address format error, expected "3000000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index af6764770fd15..5a42d920e4f9a 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -606,7 +606,7 @@ saw1: regulator@2099000 { regulator; }; - nss_common: syscon@03000000 { + nss_common: syscon@3000000 { compatible = "syscon"; reg = <0x03000000 0x0000FFFF>; }; -- GitLab From 24643b229c3d93cc4c7368e00dad89d300dd5e8a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:48 +0200 Subject: [PATCH 487/926] ARM: dts: qcom: ipq8064: drop invalid GCC thermal-sensor unit-address GCC comes with syscon compatible so the thermal-sensor child node should not have unit-address (bindings also do not expect it): Warning (unit_address_vs_reg): /soc/clock-controller@900000/thermal-sensor@900000: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 5a42d920e4f9a..2ca20a2765e79 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -520,7 +520,7 @@ gcc: clock-controller@900000 { #reset-cells = <1>; #power-domain-cells = <1>; - tsens: thermal-sensor@900000 { + tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; -- GitLab From 51500b3aac5d2fc102d607c3517f7a1ee2f29dca Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:49 +0200 Subject: [PATCH 488/926] ARM: dts: qcom: ipq8064: correct LED node names GPIO LEDs is not a bus, so drop unit-address and also start suffix numbering from 0: Warning (unit_address_vs_reg): /soc/leds/led@7: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-6-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 2 +- arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 4d509876294be..104eb729c2d6c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -323,7 +323,7 @@ leds { pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "rb3011:green:user"; color = ; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 411c8d63c38e1..c5abe7151f142 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -92,34 +92,34 @@ leds { pinctrl-0 = <&leds_pins>; pinctrl-names = "default"; - led@7 { + led-0 { label = "led_usb1"; gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@8 { + led-1 { label = "led_usb3"; gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "usbdev"; default-state = "off"; }; - led@9 { + led-2 { label = "status_led_fail"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@26 { + led-3 { label = "sata_led"; gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@53 { + led-4 { label = "status_led_pass"; function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; -- GitLab From 8b96065dd257f74ed03645978d2e076894d864b2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:50 +0200 Subject: [PATCH 489/926] ARM: dts: qcom: ipq8064: align USB node names with bindings Bindings expect USB controller node names to be named "usb". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-7-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 2ca20a2765e79..5ef5026fb7bc0 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -611,7 +611,7 @@ nss_common: syscon@3000000 { reg = <0x03000000 0x0000FFFF>; }; - usb3_0: usb3@100f8800 { + usb3_0: usb@100f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -626,7 +626,7 @@ usb3_0: usb3@100f8800 { status = "disabled"; - dwc3_0: dwc3@10000000 { + dwc3_0: usb@10000000 { compatible = "snps,dwc3"; reg = <0x10000000 0xcd00>; interrupts = ; @@ -657,7 +657,7 @@ ss_phy_0: phy@100f8830 { status = "disabled"; }; - usb3_1: usb3@110f8800 { + usb3_1: usb@110f8800 { compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -672,7 +672,7 @@ usb3_1: usb3@110f8800 { status = "disabled"; - dwc3_1: dwc3@11000000 { + dwc3_1: usb@11000000 { compatible = "snps,dwc3"; reg = <0x11000000 0xcd00>; interrupts = ; -- GitLab From 600efc01c98d3369d1fc5caee531159c43bc3939 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:51 +0200 Subject: [PATCH 490/926] ARM: dts: qcom: apq8060-dragonboard: move regulators out of simple-bus Regulators is not a bus, so drop incomplete simple-bus usage to fix dtbs W=1 warnings: Warning (simple_bus_reg): /regulators/regulator-fixed: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/xc622a331mrg: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/nds332p: missing or empty reg/ranges property Warning (simple_bus_reg): /regulators/txb0104rgyr: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-8-krzysztof.kozlowski@linaro.org --- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 80 +++++++++---------- 1 file changed, 38 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index e8fe321f3d89b..db4c791b2e2fb 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -18,50 +18,46 @@ chosen { stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; - - /* Main power of the board: 3.7V */ - vph: regulator-fixed { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-always-on; - regulator-boot-on; - }; - - /* GPIO controlled ethernet power regulator */ - dragon_veth: xc622a331mrg { - compatible = "regulator-fixed"; - regulator-name = "XC6222A331MR-G"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vph>; - gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&dragon_veth_gpios>; - regulator-always-on; - }; + /* Main power of the board: 3.7V */ + vph: regulator-fixed { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-always-on; + regulator-boot-on; + }; + + /* GPIO controlled ethernet power regulator */ + dragon_veth: xc622a331mrg { + compatible = "regulator-fixed"; + regulator-name = "XC6222A331MR-G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vph>; + gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&dragon_veth_gpios>; + regulator-always-on; + }; - /* VDDvario fixed regulator */ - dragon_vario: nds332p { - compatible = "regulator-fixed"; - regulator-name = "NDS332P"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&pm8058_s3>; - }; + /* VDDvario fixed regulator */ + dragon_vario: nds332p { + compatible = "regulator-fixed"; + regulator-name = "NDS332P"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8058_s3>; + }; - /* This is a levelshifter for SDCC5 */ - dragon_vio_txb: txb0104rgyr { - compatible = "regulator-fixed"; - regulator-name = "Dragon SDCC levelshifter"; - vin-supply = <&pm8058_l14>; - regulator-always-on; - }; + /* This is a levelshifter for SDCC5 */ + dragon_vio_txb: txb0104rgyr { + compatible = "regulator-fixed"; + regulator-name = "Dragon SDCC levelshifter"; + vin-supply = <&pm8058_l14>; + regulator-always-on; }; /* -- GitLab From 26fe8ec355328c35e2768cb9758341c0256dc953 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:52 +0200 Subject: [PATCH 491/926] ARM: dts: qcom: msm8960-cdp: move regulator out of simple-bus Regulators is not a bus, so drop incomplete simple-bus usage to fix dtbs W=1 warning: Warning (simple_bus_reg): /regulators/gpio-regulator: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-9-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8960-cdp.dts | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 8fa2befa629ae..6c1bc3818883c 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -15,16 +15,12 @@ chosen { stdout-path = "serial0:115200n8"; }; - regulators { - compatible = "simple-bus"; - - ext_l2: gpio-regulator { - compatible = "regulator-fixed"; - regulator-name = "ext_l2"; - gpio = <&msmgpio 91 0>; - startup-delay-us = <10000>; - enable-active-high; - }; + ext_l2: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ext_l2"; + gpio = <&msmgpio 91 0>; + startup-delay-us = <10000>; + enable-active-high; }; }; -- GitLab From 05e916f1db2fff88f316b6f94929b4b3b8414498 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Apr 2023 09:50:53 +0200 Subject: [PATCH 492/926] ARM: dts: qcom: apq8084: correct thermal sensor unit-address Match unit-address to reg entry to fix dtbs W=1 warnings: Warning (simple_bus_reg): /soc/thermal-sensor@fc4a8000: simple-bus unit address format error, expected "fc4a9000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230420075053.41976-10-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index b653ea40c441c..207124d68128d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -506,7 +506,7 @@ tsens_s4_p2_backup: s4-p2_backup@44e { }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ -- GitLab From d2f1bd8f0b91ce77951d983a094c157b2efd789c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 21:54:37 +0200 Subject: [PATCH 493/926] ARM: dts: qcom: msm8974: align WCNSS Bluetooth node name with bindings Bindings expect WCNSS Bluetooth child to be named "bluetooth": remoteproc@fb204000: smd-edge:wcnss: 'bt' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421195437.31513-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index b30d598441365..7dcbe0810e346 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -745,7 +745,7 @@ wcnss { qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; -- GitLab From 57b60d03d5a682d366a4850b1f69c53fc13beb22 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:50 +0530 Subject: [PATCH 494/926] ARM: dts: qcom: sdx65: Add support for PCIe PHY Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-3-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 525dd8a1f6649..2fe61c296e392 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -295,6 +295,37 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; -- GitLab From 9c0bb38414a45a03d1100f033ab6f96bedffe43a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:51 +0530 Subject: [PATCH 495/926] ARM: dts: qcom: sdx65: Add support for PCIe EP Add support for PCIe Endpoint controller on the Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 2fe61c296e392..1a3583029a649 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -295,6 +296,56 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie_phy: phy@1c06000 { compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; reg = <0x01c06000 0x2000>; @@ -332,6 +383,11 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + ipa: ipa@3f40000 { compatible = "qcom,sdx65-ipa"; -- GitLab From 2e69f6882b69ea98e785469481bf9a4d111e3b96 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:52 +0530 Subject: [PATCH 496/926] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY Enable PCIe PHY on SDX65 MTP for PCIe EP. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 57bc3b03d3aac..29ccb158f8fc4 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -250,6 +250,13 @@ &ipa { status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; -- GitLab From fd817375091b35c4368244a9872158eb719534b0 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 18 May 2023 23:17:53 +0530 Subject: [PATCH 497/926] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1684432073-28490-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 29ccb158f8fc4..02d8d6e241ae1 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -250,6 +250,18 @@ &ipa { status = "okay"; }; +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l1b_1p2>; vdda-pll-supply = <&vreg_l4b_0p88>; @@ -281,6 +293,29 @@ &remoteproc_mpss { status = "okay"; }; +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb { status = "okay"; }; -- GitLab From 38cd0f2d86f1dbfef2bef4e2b0a8b19d32a82760 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:31 +0300 Subject: [PATCH 498/926] ARM: dts: qcom: msm8226: Add PMU node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable perf events on MSM8226 devices by adding the PMU node. Signed-off-by: Matti Lehtimäki Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-3-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 42acb9ddb8ccb..185a8fff62bef 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -47,6 +47,12 @@ scm { }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; -- GitLab From a22a576af30d4366ff13662c8b57c951374c7674 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:32 +0300 Subject: [PATCH 499/926] ARM: dts: qcom: msm8226: Add rpm-stats device node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device node for the rpm-stats pseudo device. Signed-off-by: Matti Lehtimäki Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-4-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 185a8fff62bef..dc706d5b185cc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -598,6 +598,11 @@ frame@f9028000 { }; }; + sram@fc190000 { + compatible = "qcom,msm8226-rpm-stats"; + reg = <0xfc190000 0x10000>; + }; + rpm_msg_ram: sram@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; -- GitLab From 9cf9832d4f5f7659159a036ccae2e10f6eeadf5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sat, 20 May 2023 15:19:33 +0300 Subject: [PATCH 500/926] ARM: dts: qcom: msm8226: Add IMEM node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This enables userspace to signal the bootloader to go into the bootloader or recovery mode. The magic values can be found in both the downstream kernel and the LK kernel (bootloader). Signed-off-by: Matti Lehtimäki Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-5-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index dc706d5b185cc..a3a9162e9c28e 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -647,6 +647,20 @@ smd-edge { label = "lpass"; }; }; + + sram@fe805000 { + compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; + reg = <0xfe805000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-bootloader = <0x77665500>; + mode-normal = <0x77665501>; + mode-recovery = <0x77665502>; + }; + }; }; timer { -- GitLab From b41fb001bebff28dd05a7c74e728ce7f024856ac Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 30 Apr 2023 20:20:57 +0200 Subject: [PATCH 501/926] ARM: dts: qcom: apq8026-huawei-sturgeon: Add vibrator The watch has a DRV2605 for haptics. Add a node for it based on the values found in the downstream board file. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230430-drv260x-improvements-v1-5-1fb28b4cc698@z3ntu.xyz --- .../boot/dts/qcom-apq8026-huawei-sturgeon.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts index d64096028ab13..eb73b992a6964 100644 --- a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts +++ b/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts @@ -7,6 +7,7 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +#include /delete-node/ &adsp_region; @@ -68,6 +69,26 @@ &adsp { status = "okay"; }; +&blsp1_i2c2 { + clock-frequency = <384000>; + + status = "okay"; + + vibrator@5a { + compatible = "ti,drv2605"; + reg = <0x5a>; + enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + mode = ; + library-sel = ; + vib-rated-mv = <2765>; + vib-overdrive-mv = <3525>; + + pinctrl-0 = <&vibrator_default_state>; + pinctrl-names = "default"; + }; +}; + &blsp1_i2c5 { clock-frequency = <384000>; @@ -347,6 +368,13 @@ reset-pins { }; }; + vibrator_default_state: vibrator-default-state { + pins = "gpio59", "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + wlan_hostwake_default_state: wlan-hostwake-default-state { pins = "gpio66"; function = "gpio"; -- GitLab From e60c230588d88036f974cec7e93361e2c4f62226 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:33 +0300 Subject: [PATCH 502/926] ARM: dts: qcom: apq8074-dragonboard: Set DMA as remotely controlled Add the qcom,controlled-remotely property for the blsp2_bam controller node. This board requires this, otherwise the board stalls during the boot for some reason (most probably because TZ mishandles the protection error and keeps on looping somewhere inside). Fixes: 62bc81792223 dts: msm8974: Add blsp2_bam dma node Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-3-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 1345df7cbd002..6b047c6793707 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -23,6 +23,10 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_dma { + qcom,controlled-remotely; +}; + &blsp2_i2c5 { status = "okay"; clock-frequency = <200000>; -- GitLab From 1ca793c3714a754488c782eb0d68b279d811b977 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:34 +0300 Subject: [PATCH 503/926] ARM: dts: qcom: apq8074-dragonboard: enable adsp and MSS Enable ADSP and Modem DSPs on APQ8074 dragonboard. The MSS region differs from the one defined in the msm8974, so it overriden locally. The modem is specified use mba.mbn instead of mbn.b00 (for the sake of similarity with other platforms). This requires a patch for remoteproc to be applied [1]. [1] https://lore.kernel.org/all/20230507172041.2320279-1-dmitry.baryshkov@linaro.org/ Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-4-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 6b047c6793707..c893afc00eb40 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -4,6 +4,8 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" +/delete-node/ &mpss_region; + / { model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; @@ -17,6 +19,13 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + mpss_region: mpss@ac00000 { + reg = <0x0ac00000 0x2500000>; + no-map; + }; + }; }; &blsp1_uart2 { @@ -39,6 +48,25 @@ eeprom: eeprom@52 { }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + + firmware-name = "qcom/apq8074/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + firmware-name = "qcom/apq8074/mba.mbn", "qcom/apq8074/modem.mbn"; + + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; -- GitLab From 925bac3caa46c5790d21ee236869b017090aad2d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 7 May 2023 22:07:35 +0300 Subject: [PATCH 504/926] ARM: dts: qcom: apq8074-dragonboard: enable DSI panel Enable MDSS, GPU and DSI panel output on the APQ8074 dragonboard. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507190735.2333145-5-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index c893afc00eb40..72f7e09a5bbf1 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -48,6 +48,57 @@ eeprom: eeprom@52 { }; }; +&dsi0 { + vdda-supply = <&pm8941_l2>; + vdd-supply = <&pm8941_l22>; + vddio-supply = <&pm8941_l12>; + + status = "okay"; + + panel: panel@0 { + compatible = "sharp,ls043t1le01-qhd"; + reg = <0>; + + avdd-supply = <&pm8941_l22>; + backlight = <&pm8941_wled>; + reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vddio-supply = <&pm8941_l12>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm8941_wled { + qcom,cs-out; + qcom,switching-freq = <3200>; + qcom,ovp = <32>; + qcom,num-strings = <1>; + + status = "okay"; +}; + &remoteproc_adsp { cx-supply = <&pm8841_s2>; -- GitLab From 8575f197b077001591ef3ff709cdee48785daf0d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 May 2023 21:54:45 +0530 Subject: [PATCH 505/926] arm64: dts: qcom: Introduce the SC8180x platform Introduce a base dtsi for the Qualcomm SC8180x platform, with CPUs, global clock controller, SMMU, rpmh clocks, rpmh power-domains, CPUfreq etc Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-7-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1188 +++++++++++++++++++++++++ 1 file changed, 1188 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi new file mode 100644 index 0000000000000..e38ea25456547 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -0,0 +1,1188 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <602>; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; + + L2_300: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_400: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_500: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_600: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; + + L2_700: l2-cache { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <241>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-peak-kBps = <800000 9600000>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-peak-kBps = <800000 12902400>; + }; + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <800000 12902400>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <800000 15974400>; + }; + + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-peak-kBps = <1804000 19660800>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <1804000 19660800>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <1804000 22732800>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <1804000 22732800>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <2188000 31948800>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <3072000 31948800>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1804000 15974400>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 19660800>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <2188000 22732800>; + }; + + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <3072000 25804800>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <3072000 31948800>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <4068000 31948800>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <4068000 31948800>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <4068000 40550400>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <4068000 40550400>; + }; + + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <4068000 43008000>; + }; + + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <6220000 49152000>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <7216000 49152000>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <8368000 49152000>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2649600000 { + opp-hz = /bits/ 64 <2649600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2918400000 { + opp-hz = /bits/ 64 <2918400000>; + opp-peak-kBps = <8368000 51609600>; + }; + + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <8368000 51609600>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sc8180x", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@85700000 { + reg = <0x0 0x85700000 0x0 0x600000>; + no-map; + }; + + xbl_mem: xbl@85d00000 { + reg = <0x0 0x85d00000 0x0 0x140000>; + no-map; + }; + + aop_mem: aop@85f00000 { + reg = <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db: cmd-db@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + reserved@85f40000 { + reg = <0x0 0x85f40000 0x0 0x10000>; + no-map; + }; + + smem_mem: smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + reserved@86200000 { + reg = <0x0 0x86200000 0x0 0x3900000>; + no-map; + }; + + reserved@89b00000 { + reg = <0x0 0x89b00000 0x0 0x1c00000>; + no-map; + }; + + reserved@9d400000 { + reg = <0x0 0x9d400000 0x0 0x1000000>; + no-map; + }; + + reserved@9e400000 { + reg = <0x0 0x9e400000 0x0 0x1400000>; + no-map; + }; + + reserved@9f800000 { + reg = <0x0 0x9f800000 0x0 0x800000>; + no-map; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apss_shared 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lpass { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apss_shared 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apss_shared 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + modem_smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + modem_smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + + interrupts = ; + + mboxes = <&apss_shared 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc8180x"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x2500>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x300 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy-wrapper@1d87000 { + compatible = "qcom,sc8180x-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + adreno_smmu: iommu@2ca0000 { + compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; + reg = <0 0x02ca0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + tlmm: pinctrl@3100000 { + compatible = "qcom,sc8180x-tlmm"; + reg = <0 0x03100000 0 0x300000>, + <0 0x03500000 0 0x700000>, + <0 0x03d00000 0 0x300000>; + reg-names = "west", "east", "south"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 191>; + wakeup-parent = <&pdc>; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sc8180x-llcc"; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc8180x-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + apss_shared: mailbox@17c00000 { + compatible = "qcom,sc8180x-apss-shared"; + reg = <0x0 0x17c00000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17c21000{ + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c26000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sc8180x-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sc8180x-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- GitLab From f3be8a111d7eaf4e291b6c2d51dd0adb39934b32 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:46 +0530 Subject: [PATCH 506/926] arm64: dts: qcom: sc8180x: Add interconnects and lmh This add interconnect nodes and add LMH to sc8180x SoC dtsi Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-8-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 126 ++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e38ea25456547..08f5ad65efd50 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include #include @@ -44,6 +46,8 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -70,6 +74,8 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -93,6 +99,8 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -115,6 +123,8 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -137,6 +147,8 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -159,6 +171,8 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -181,6 +195,8 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -203,6 +219,8 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -476,6 +494,24 @@ scm: scm { }; }; + camnoc_virt: interconnect-camnoc-virt { + compatible = "qcom,sc8180x-camnoc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sc8180x-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qup_virt: interconnect-qup-virt { + compatible = "qcom,sc8180x-qup-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -743,6 +779,48 @@ gcc: clock-controller@100000 { "sleep_clk"; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sc8180x-config-noc"; + reg = <0 0x01500000 0 0x7400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sc8180x-system-noc"; + reg = <0 0x01620000 0 0x19400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sc8180x-aggre1-noc"; + reg = <0 0x016e0000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sc8180x-aggre2-noc"; + reg = <0 0x01700000 0 0x20000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1720000 { + compatible = "qcom,sc8180x-compute-noc"; + reg = <0 0x01720000 0 0x7000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sc8180x-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -810,6 +888,13 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + ipa_virt: interconnect@1e00000 { + compatible = "qcom,sc8180x-ipa-virt"; + reg = <0 0x01e00000 0 0x1000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -860,6 +945,13 @@ system-cache-controller@9200000 { interrupts = ; }; + gem_noc: interconnect@9680000 { + compatible = "qcom,sc8180x-gem-noc"; + reg = <0 0x09680000 0 0x58200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -1166,6 +1258,40 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sc8180x-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + lmh@18350800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18350800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh@18358800 { + compatible = "qcom,sc8180x-lmh"; + reg = <0 0x18358800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; -- GitLab From d1d3ca03554e51be44546638f83169bb05b20ef8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:47 +0530 Subject: [PATCH 507/926] arm64: dts: qcom: sc8180x: Add thermal zones This patch adds tsens nodes and thermal zones for sc8180x SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-9-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 415 ++++++++++++++++++++++++++ 1 file changed, 415 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 08f5ad65efd50..da7c08e70540e 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -961,6 +962,28 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <9>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; @@ -1304,6 +1327,398 @@ cpufreq_hw: cpufreq@18323000 { #clock-cells = <1>; }; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 13>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 14>; + + trips { + cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + compute-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + mdm-dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- GitLab From 0018761d1564f64d567e119fd9156c473b4592d7 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:48 +0530 Subject: [PATCH 508/926] arm64: dts: qcom: sc8180x: Add QUPs This patch adds qup instances and i2c, spi, serial ports Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-10-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 859 ++++++++++++++++++++++++++ 1 file changed, 859 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index da7c08e70540e..b50673b7c1474 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -780,6 +780,865 @@ gcc: clock-controller@100000 { "sleep_clk"; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x4c3 0>; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart2: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart5: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart6: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart7: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x603 0>; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c16: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi16: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart16: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + qupv3_id_2: geniqup@cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00cc0000 0x0 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x7a3 0>; + status = "disabled"; + + i2c17: i2c@c80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi17: spi@c80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart17: serial@c80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c18: i2c@c84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi18: spi@c84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart18: serial@c84000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c19: i2c@c88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi19: spi@c88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart19: serial@c88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c13: i2c@c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@c8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@c8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c14: i2c@c90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@c90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart14: serial@c90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c15: i2c@c94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@c94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart15: serial@c94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sc8180x-config-noc"; reg = <0 0x01500000 0 0x7400>; -- GitLab From d20b6c84f56ae3a9823cc0fa5cfad330536ba0d1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:49 +0530 Subject: [PATCH 509/926] arm64: dts: qcom: sc8180x: Add PCIe instances This patch adds PCIe instances found on this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-11-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 429 ++++++++++++++++++++++++++ 1 file changed, 429 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b50673b7c1474..2639f5fb6e39c 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1681,6 +1681,435 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy-wrapper@1c06000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx0 */ + <0 0x1c06400 0 0x200>, /* rx0 */ + <0 0x1c06a00 0 0x1f0>, /* pcs */ + <0 0x1c06600 0 0x170>, /* tx1 */ + <0 0x1c06800 0 0x200>, /* rx1 */ + <0 0x1c06e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie3: pci@1c08000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1e00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets = <&gcc GCC_PCIE_3_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_3_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie3_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie3_phy: phy-wrapper@1c0c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c0c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_3_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie3_lane: phy@1c0c200 { + reg = <0 0x1c0c200 0 0x170>, /* tx0 */ + <0 0x1c0c400 0 0x200>, /* rx0 */ + <0 0x1c0ca00 0 0x1f0>, /* pcs */ + <0 0x1c0c600 0 0x170>, /* tx1 */ + <0 0x1c0c800 0 0x200>, /* rx1 */ + <0 0x1c0ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_3_pipe_clk"; + #phy-cells = <0>; + }; + }; + + pcie1: pci@1c10000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c10000 0 0x3000>, + <0 0x68000000 0 0xf1d>, + <0 0x68000f20 0 0xa8>, + <0 0x68001000 0 0x1000>, + <0 0x68100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy-wrapper@1c16000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c16000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: phy@1c0e200 { + reg = <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ + <0 0x1c16600 0 0x170>, /* tx1 */ + <0 0x1c16800 0 0x200>, /* rx1 */ + <0 0x1c16e00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + }; + }; + + pcie2: pci@1c18000 { + compatible = "qcom,pcie-sc8180x"; + reg = <0 0x01c18000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>; + + resets = <&gcc GCC_PCIE_2_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2_GDSC>; + + interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + phys = <&pcie2_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2_phy: phy-wrapper@1c1c000 { + compatible = "qcom,sc8180x-qmp-pcie-phy"; + reg = <0 0x1c1c000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie2_lane: phy@1c0e200 { + reg = <0 0x1c1c200 0 0x170>, /* tx0 */ + <0 0x1c1c400 0 0x200>, /* rx0 */ + <0 0x1c1ca00 0 0x1f0>, /* pcs */ + <0 0x1c1c600 0 0x170>, /* tx1 */ + <0 0x1c1c800 0 0x200>, /* rx1 */ + <0 0x1c1ce00 0 0xf4>; /* pcs_com */ + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk"; + + #phy-cells = <0>; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; -- GitLab From b080f53a8f44eeaa9db9628d8d339ab5a2afb5bd Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:50 +0530 Subject: [PATCH 510/926] arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes This patch adds remoteprocs, wifi and usb and usb phy nodes for this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-12-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 355 ++++++++++++++++++++++++++ 1 file changed, 355 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 2639f5fb6e39c..c73fb25f5af06 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2227,6 +2227,198 @@ tlmm: pinctrl@3100000 { wakeup-parent = <&pdc>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc8180x-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>, + <&rpmhpd SC8180X_MSS>; + power-domain-names = "cx", "mss"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible = "qcom,sc8180x-cdsp-pas"; + reg = <0x0 0x08300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apss_shared 4>; + }; + }; + + usb_prim_hsphy: phy@88e2000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e2000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_sec_hsphy: phy@88e3000 { + compatible = "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_prim_qmpphy: phy@88e9000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_prim_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_prim_phy_pipe_clk_src"; + }; + + usb_prim_dpphy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; + + usb_sec_qmpphy: phy@88ee000 { + compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; + reg = <0 0x088ee000 0 0x18c>, + <0 0x088ed000 0 0x10>, + <0 0x088ef000 0 0x40>; + reg-names = "reg-base", "dp_com"; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", + "ref_clk_src", + "ref", + "com_aux"; + resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_sec_ssphy: usb3-phy@88e9200 { + reg = <0 0x088ee200 0 0x200>, + <0 0x088ee400 0 0x200>, + <0 0x088eec00 0 0x218>, + <0 0x088ee600 0 0x200>, + <0 0x088ee800 0 0x200>, + <0 0x088eea00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_sec_phy_pipe_clk_src"; + }; + + usb_sec_dpphy: dp-phy@88ef200 { + reg = <0 0x088ef200 0 0x200>, + <0 0x088ef400 0 0x200>, + <0 0x088efa00 0 0x200>, + <0 0x088ef600 0 0x200>, + <0 0x088ef800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + clock-output-names = "qmp_dptx1_phy_pll_link_clk", + "qmp_dptx1_phy_pll_vco_div_clk"; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sc8180x-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; @@ -2241,6 +2433,112 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_prim: usb@a6f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc USB30_PRIM_GDSC>; + + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_prim_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x140 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_sec: usb@a8f8800 { + compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "mock_utmi", + "sleep", + "xo"; + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc USB30_SEC_GDSC>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + status = "disabled"; + + usb_sec_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -2416,6 +2714,39 @@ apps_smmu: iommu@15000000 { }; + remoteproc_adsp: remoteproc@17300000 { + compatible = "qcom,sc8180x-adsp-pas"; + reg = <0x0 0x17300000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC8180X_CX>; + power-domain-names = "cx"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -2615,6 +2946,30 @@ cpufreq_hw: cpufreq@18323000 { #clock-cells = <1>; }; + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + clock-names = "cxo_ref_clk_pin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x0640 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; -- GitLab From 494dec9b6f541451b2e82905b0eebd9a4ac9848b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:51 +0530 Subject: [PATCH 511/926] arm64: dts: qcom: sc8180x: Add display and gpu nodes This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with dsi0/1, dp0/1 and edp subnodes as found in this SoC Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-13-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 658 ++++++++++++++++++++++++++ 1 file changed, 658 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index c73fb25f5af06..e8613a00fcab7 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -4,7 +4,9 @@ * Copyright (c) 2020-2023, Linaro Limited */ +#include #include +#include #include #include #include @@ -2190,6 +2192,123 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpu: gpu@2c00000 { + compatible = "qcom,adreno-680.1", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0 0x02c00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0xc01>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "gfx-mem"; + + qcom,gmu = <&gmu>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-level = ; + }; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = ; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + opp-level = ; + }; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + + reg = <0 0x02c6a000 0 0x30000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0xc00>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sc8180x-gpucc"; + reg = <0 0x02c90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + adreno_smmu: iommu@2ca0000 { compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; @@ -2539,6 +2658,545 @@ usb_sec_dwc3: usb@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sc8180x-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "nrt_bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + + port@4 { + reg = <4>; + dpu_intf4_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@5 { + reg = <5>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae90a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + + phys = <&usb_prim_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,sc8180x-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae98a00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <13>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + + phys = <&usb_sec_dpphy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp0_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp: displayport-controller@ae9a000 { + compatible = "qcom,sc8180x-edp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9aa00 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <14>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; + + phys = <&edp_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC8180X_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + edp_phy: phy@aec2a00 { + compatible = "qcom,sc8180x-edp-phy"; + reg = <0 0x0aec2a00 0 0x1c0>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x19c>; + + clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&dispcc MDSS_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc8180x-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_prim_dpphy 0>, + <&usb_prim_dpphy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + clock-names = "bi_tcxo", + "sleep_clk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SC8180X_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- GitLab From d3302290f59e8533a56a8fa2455357f843d8dcf6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 30 May 2023 21:54:52 +0530 Subject: [PATCH 512/926] arm64: dts: qcom: sc8180x: Add pmics SC8180X based platforms have PM8150, PM8150C, PMC8180 and SMB2351 PMICs, so add these as well Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-14-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 326 ++++++++++++++++++++ 1 file changed, 326 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi new file mode 100644 index 0000000000000..8247af01c84a5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + thermal-zones { + pmc8180-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmc8180c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmc8180c_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmc8180_0: pmic@0 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon: power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + + status = "disabled"; + }; + }; + + pmc8180_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pmc8180_gpios: gpio@c000 { + compatible = "qcom,pmc8180-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmc8180", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@2 { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin2"; + }; + }; + }; + + pmic@6 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@8 { + compatible = "qcom,pm8150", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@a { + compatible = "qcom,smb2351", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + vcoin@85 { + reg = <0x85>; + qcom,pre-scaling = <1 1>; + label = "vcoin"; + }; + }; + }; + + pmic@4 { + compatible = "qcom,pm8150c", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmc8180c_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmc8180c_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmc8180c_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmc8180c_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmc8180c_gpios: gpio@c000 { + compatible = "qcom,pmc8180c-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmc8180c", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + + pmc8180c_lpg: lpg { + compatible = "qcom,pmc8180c-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; -- GitLab From 2ce38cc1e8fea4e251e4563e436104369bf3b322 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 May 2023 21:54:53 +0530 Subject: [PATCH 513/926] arm64: dts: qcom: sc8180x: Introduce Primus Introduce support for the SC8180X reference device, aka Primus, with debug UART, regulators, UFS and USB support. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-15-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 706 ++++++++++++++++++++ 2 files changed, 707 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-primus.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1ad68b728f50e..c004849a095c3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts new file mode 100644 index 0000000000000..cca663bcb92d4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -0,0 +1,706 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model = "Qualcomm SC8180x Primus"; + compatible = "qcom,sc8180x-primus", "qcom,sc8180x"; + + aliases { + serial0 = &uart12; + serial1 = &uart13; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8180c_lpg 4 1000000>; + enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwm_default>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&hall_int_active_state>; + + lid-switch { + gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + adsp_mem: adsp-region@96e00000 { + reg = <0x0 0x96e00000 0x0 0x1c00000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg = <0x0 0x8d800000 0x0 0x9600000>; + no-map; + }; + + gpu_mem: gpu-region@98a00000 { + reg = <0x0 0x98a00000 0x0 0x2000>; + no-map; + }; + + reserved-region@9a500000 { + reg = <0x0 0x9a500000 0x0 0x600000>; + no-map; + }; + }; + + vreg_nvme_0p9: nvme-0p9-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_nvme_0p9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-always-on; + }; + + vreg_nvme_3p3: nvme-3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_nvme_3p3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8180c_gpios 11 0>; + enable-active-high; + + regulator-always-on; + }; + + vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_kb_tp_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-always-on; + + pinctrl-names = "default"; + pinctrl-0 = <&kb_tp_3v3_en_active_state>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s5-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt = <1296000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s6-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l2-l3-supply = <&vreg_s6c_1p35>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p8: smps8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l4c_3p3: ldo4 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt = <992000>; + regulator-max-microvolt = <992000>; + regulator-initial-mode = ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l12e: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_i2c_active_state>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + + vdd-supply = <&vreg_l4c_3p3>; + vddl-supply = <&vreg_l12e>; + + post-power-on-delay-ms = <20>; + + interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_active_state>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&aux_i2c_active_state>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_active_state>; + + vdd-supply = <&vdd_kb_tp_3v3>; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&kb_int_active_state>; + + vdd-supply = <&vdd_kb_tp_3v3>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_edp { + data-lanes = <0 1 2 3>; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd_active>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + ports { + port { + auo_b133han05_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_edp_out: endpoint { + remote-endpoint = <&auo_b133han05_in>; + }; + }; + }; +}; + +&pcie1 { + perst-gpio = <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 177 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&pmc8180c_lpg { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc8180x/qcadsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; + firmware-name = "qcom/sc8180x/qcmpss8180.mbn"; + + status = "okay"; +}; + +&uart12 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart13 { + pinctrl-names = "default"; + pinctrl-0 = <&uart13_state>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l9a_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10e_2p9>; + vcc-max-microamp = <155000>; + + vccq2-supply = <&vreg_l7e_1p8>; + vccq2-max-microamp = <425000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_prim { + status = "okay"; +}; + +&usb_prim_dwc3 { + dr_mode = "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_sec { + status = "okay"; +}; + +&usb_sec_dwc3 { + dr_mode = "host"; +}; + +&wifi { + memory-region = <&wlan_mem>; + + vdd-0.8-cx-mx-supply = <&vreg_l1e_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l10c_3p3>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default: bl-pwm-default-state { + en-pins { + pins = "gpio8"; + function = "normal"; + }; + + pwm-pins { + pins = "gpio10"; + function = "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <47 4>, <126 4>; + + aux_i2c_active_state: aux-i2c-active-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + + bias-disable; + drive-strength = <16>; + }; + + edp_hpd_active: epd-hpd-active-state { + pins = "gpio10"; + function = "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins = "gpio121"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + kb_int_active_state: kb-int-active-state { + int-n-pins { + pins = "gpio37"; + function = "gpio"; + + bias-pull-up; + intput-enable; + }; + + kp-disable-pins { + pins = "gpio135"; + function = "gpio"; + + output-high; + }; + }; + + kb_tp_3v3_en_active_state: kb-tp-3v3-en-active-state { + pins = "gpio4"; + function = "gpio"; + + bias-disable; + }; + + pcie2_default_state: pcie2-default-state { + clkreq-pins { + pins = "gpio176"; + function = "pci_e2"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio175"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio177"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + tp_int_active_state: tp-int-active-state { + tp-int-pins { + pins = "gpio24"; + function = "gpio"; + + bias-disable; + input-enable; + }; + + tp-close-n-pins { + pins = "gpio116"; + function = "gpio"; + + bias-disable; + input-enable; + }; + }; + + ts_active_state: ts-active-state { + int-n-pins { + pins = "gpio122"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + reset-n-pins { + pins = "gpio54"; + function = "gpio"; + + output-high; + }; + }; + + ts_i2c_active_state: ts-i2c-active-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + + /* External pull up */ + bias-disable; + drive-strength = <2>; + }; + + uart13_state: uart13-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio44", "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + bias-pull-up; + }; + }; +}; -- GitLab From 20dea72a393c6d5572088b8ad01dbb9e9aca64ce Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 May 2023 21:54:54 +0530 Subject: [PATCH 514/926] arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G Introduce support for the Lenovo Flex 5G laptop, built on the Qualcomm SC8180X platform. Supported peripherals includes keyboard, touchpad, UFS storage, external USB and WiFi. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530162454.51708-16-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 583 ++++++++++++++++++ 2 files changed, 584 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c004849a095c3..4f9e81253e18a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -147,6 +147,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts new file mode 100644 index 0000000000000..fe3b366e1435d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model = "Lenovo Flex 5G"; + compatible = "lenovo,flex-5g", "qcom,sc8180x"; + + aliases { + serial0 = &uart13; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8180c_lpg 4 1000000>; + enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bl_pwm_default>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_active_state>; + pinctrl-names = "default"; + + lid { + gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg = <0x0 0x8d800000 0x0 0x3000000>; + no-map; + }; + + adsp_mem: adsp-region@90800000 { + reg = <0x0 0x90800000 0x0 0x1c00000>; + no-map; + }; + + gpu_mem: gpu-region@98715000 { + reg = <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + + cdsp_mem: cdsp-region@98900000 { + reg = <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s5-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt = <1296000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s6-supply = <&vph_pwr>; + vdd-l2-l3-supply = <&vreg_s6c_1p35>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt = <992000>; + regulator-max-microvolt = <992000>; + regulator-initial-mode = ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x1>; + + interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + + pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-names = "default"; + + status = "okay"; + + hid@5 { + compatible = "hid-over-i2c"; + reg = <0x5>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + }; + + hid@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_edp { + data-lanes = <0 1 2 3>; + + pinctrl-0 = <&edp_hpd_active>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + no-hpd; + + backlight = <&backlight>; + + ports { + port { + auo_b140han06_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_edp_out: endpoint { + remote-endpoint = <&auo_b140han06_in>; + }; + }; + }; +}; + +&pcie3 { + perst-gpio = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 180 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie3_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&pmc8180c_lpg { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcadsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + memory-region = <&cdsp_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qccdsp8180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + memory-region = <&mpss_mem>; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcmpss8180_nm.mbn"; + + status = "okay"; +}; + +&uart13 { + pinctrl-0 = <&uart13_state>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l9a_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10e_2p9>; + vcc-max-microamp = <155000>; + + vccq2-supply = <&vreg_l7e_1p8>; + vccq2-max-microamp = <425000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; + + status = "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_prim { + status = "okay"; +}; + +&usb_prim_dwc3 { + dr_mode = "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply = <&vreg_l5e_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l16e_3p0>; + + status = "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l5e_0p88>; + + status = "okay"; +}; + +&usb_sec { + status = "okay"; +}; + +&usb_sec_dwc3 { + dr_mode = "host"; +}; + +&wifi { + memory-region = <&wlan_mem>; + + vdd-0.8-cx-mx-supply = <&vreg_l1e_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l10c_3p3>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default: bl-pwm-default-state { + en-pins { + pins = "gpio8"; + function = "normal"; + }; + + pwm-pins { + pins = "gpio10"; + function = "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <47 4>, <126 4>; + + edp_hpd_active: epd-hpd-active-state { + pins = "gpio10"; + function = "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins = "gpio121"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + i2c1_active: i2c1-active-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + + bias-pull-up = <1>; + drive-strength = <2>; + }; + + i2c1_hid_active: i2c1-hid-active-state { + pins = "gpio122"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_active: i2c7-active-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + + bias-pull-up; + drive-strength = <2>; + }; + + i2c7_hid_active: i2c7-hid-active-state { + pins = "gpio37", "gpio24"; + function = "gpio"; + + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + pcie3_default_state: pcie3-default-state { + clkreq-pins { + pins = "gpio179"; + function = "pci_e3"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio178"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio180"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart13_state: uart13-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio44", "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + bias-pull-up; + }; + }; +}; -- GitLab From 17ff149eee01110e5d545ad7b936d48aff43407f Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 24 May 2023 12:11:56 +0300 Subject: [PATCH 515/926] ARM: dts: am335x-myirtech: Add missing NAND wait pin definition The NAND wait pin is connected to the GPMC, but this is not mentioned in the DT bindings. Let's fix this. Signed-off-by: Alexander Shiyan Message-Id: <20230524091157.775960-1-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 6eea18b293557..38bc7d41baa73 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -127,6 +127,7 @@ nand0: nand@0,0 { gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; + gpmc,wait-pin = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; -- GitLab From 445d5be64be82c11505c41d75a4bde3af41d619b Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Mon, 13 Mar 2023 12:04:09 +0100 Subject: [PATCH 516/926] ARM: dts: omap4: add initial support for Epson Moverio BT-200 Add the devices working with current drivers for the Epson Moverio BT-200 AR glasses consisting of a control unit and the glasses itself. Signed-off-by: Andreas Kemnade Message-Id: <20230313110409.2294154-1-andreas@kemnade.info> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/omap4-epson-embt2ws.dts | 450 ++++++++++++++++++++++ 2 files changed, 451 insertions(+) create mode 100644 arch/arm/boot/dts/omap4-epson-embt2ws.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..cbc177ce50fdc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -983,6 +983,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-droid-bionic-xt875.dtb \ omap4-droid4-xt894.dtb \ omap4-duovero-parlor.dtb \ + omap4-epson-embt2ws.dtb \ omap4-kc1.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ diff --git a/arch/arm/boot/dts/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/omap4-epson-embt2ws.dts new file mode 100644 index 0000000000000..e119e2cccc4e1 --- /dev/null +++ b/arch/arm/boot/dts/omap4-epson-embt2ws.dts @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Andreas Kemnade + */ +/dts-v1/; + +#include +#include "omap4460.dtsi" + +/ { + model = "Epson Moverio BT-200"; + compatible = "epson,embt2ws", "ti,omap4460", "ti,omap4"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1024M */ + }; + + backlight-left { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 1 7812500>; + power-supply = <&unknown_supply>; + }; + + backlight-right { + compatible = "pwm-backlight"; + pwms = <&twl_pwm 0 7812500>; + power-supply = <&unknown_supply>; + }; + + chosen { + stdout-path = &uart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-lock { + label = "Lock"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; /* SW_TOUCHPAD_LOCK */ + linux,input-type = ; + }; + }; + + unknown_supply: unknown-supply { + compatible = "regulator-fixed"; + regulator-name = "unknown"; + }; + + /* regulator for wl12xx on sdio2 */ + wl12xx_vmmc: wl12xx-vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: pmic@48 { + compatible = "ti,twl6032"; + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + ldo2: regulator-ldo2 { + compatible = "ti,twl6032-ldo2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo4: regulator-ldo4 { + compatible = "ti,twl6032-ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + }; + + ldo3: regulator-ldo3 { + compatible = "ti,twl6032-ldo3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo5: regulator-ldo5 { + compatible = "ti,twl6032-ldo5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + ti,retain-on-reset; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,twl6032-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2500000>; + }; + + ldo7: regulator-ldo7 { + compatible = "ti,twl6032-ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2900000>; + }; + + ldoln: regulator-ldoln { + compatible = "ti,twl6032-ldoln"; + regulator-always-on; + }; + + ldo6: regulator-ldo6 { + compatible = "ti,twl6032-ldo6"; + regulator-always-on; + }; + + ldousb: regulator-ldousb { + compatible = "ti,twl6032-ldousb"; + regulator-always-on; + }; + + vio: regulator-vio { + compatible = "ti,twl6032-vio"; + regulator-always-on; + }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; + + twl_pwm: pwm { + /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */ + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + /* provides one PWM (id 0 for Charging indicator LED) */ + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; + + gpadc { + compatible = "ti,twl6032-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; + + }; +}; + +#include "twl6030_omap4.dtsi" + +&twl_usb_comparator { + usb-supply = <&ldousb>; +}; + + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <200000>; + + /* at head/glasses */ + mpu9150h: imu@68 { + compatible = "invensense,mpu9150"; + reg = <0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu9150h_pins>; + interrupt-parent = <&gpio2>; + interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <100000>; + + /* TODO: BD2606MVV at 0x66 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <360000>; + + /* TODO: KXTI9 at 0xf */ + + tlv320aic3x: codec@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&tlv320aic3x_pins>; + #sound-dai-cells = <0>; + + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + /* TODO: mpu9150 at control unit, seems to require quirks */ +}; + +&keypad { + pinctrl-names = "default"; + pinctrl-0 = <&keypad_pins>; + keypad,num-rows = <2>; + keypad,num-columns = <3>; + linux,keymap = ; + linux,input-no-autorepeat; +}; + +&mcbsp2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; + status = "okay"; +}; + + +&mmc1 { + /* sdcard */ + vmmc-supply = <&ldo5>; + broken-cd; + bus-width = <4>; +}; + +&mmc2 { + /* emmc */ + vmmc-supply = <&ldo2>; + bus-width = <8>; +}; + +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_pins>; + vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x12e>; + non-removable; + bus-width = <4>; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1283"; + reg = <2>; + interrupts-extended = <&gpio1 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq"; + ref-clock-frequency = <26000000>; + tcxo-clock-frequency = <26000000>; + }; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&omap4_pmx_core { + bt_pins: pinmux-bt-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE3) /* gpio25 */ + >; + }; + + gpio_keys_pins: pinmux-gpio-key-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x56, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio35 */ + >; + }; + + i2c1_pins: pinmux-i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux-i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: pinmux-i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ + >; + }; + + keypad_pins: pinmux-keypad-pins { + pinctrl-single,pins = < + /* kpd_row0 */ + OMAP4_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row1 */ + OMAP4_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_row2 */ + OMAP4_IOPAD(0x0054, PIN_INPUT_PULLUP | MUX_MODE1) + /* kpd_col0 */ + OMAP4_IOPAD(0x0058, PIN_OUTPUT | MUX_MODE1) + /* kpd_col1 */ + OMAP4_IOPAD(0x005a, PIN_OUTPUT | MUX_MODE1) + /* kpd_col2 */ + OMAP4_IOPAD(0x005c, PIN_OUTPUT | MUX_MODE1) + >; + }; + + mcbsp2_pins: pinmux-mcbsp2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */ + OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */ + OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */ + OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */ + >; + }; + + mpu9150h_pins: pinmux-mpu9150h-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x76, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + + tlv320aic3x_pins: pinmux-tlv320aic3x-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x7e, PIN_OUTPUT | MUX_MODE3) + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux-uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + usb_otg_hs_pins: pinmux-usb-otg-hs-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ + >; + }; + + wl12xx_pins: pinmux-wl12xx-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c6, PIN_INPUT | MUX_MODE3) /* gpio_23 / IRQ */ + OMAP4_IOPAD(0x16c, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat2 */ + OMAP4_IOPAD(0x16e, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat1 */ + OMAP4_IOPAD(0x170, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat0 */ + OMAP4_IOPAD(0x172, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_dat3 */ + OMAP4_IOPAD(0x174, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_cmd */ + OMAP4_IOPAD(0x176, PIN_INPUT_PULLUP | MUX_MODE2) /* sdmmc3_clk */ + >; + }; + + wl12xx_gpio: pinmux-wl12xx-gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE3) /* gpio_24 / WLAN_EN */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; + + /* + * BT + GPS in WL1283 in WG7500 requiring CLK32KAUDIO of pmic + * which does not have a driver + */ +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&usbhshost { + status = "disabled"; +}; -- GitLab From 98b503c7fb13a17a47d8ebf15fa8f7c10118e75c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 16 May 2023 22:30:29 +0200 Subject: [PATCH 517/926] ARM: dts: meson8: correct uart_B and uart_C clock references On Meson8 uart_B and uart_C do not work, because they are relying on incorrect clocks. Change the references of pclk to the correct CLKID (UART1 for uart_B and UART2 for uart_C), to allow use of the two uarts. This was originally reported by Hans-Frieder Vogt for Meson8b [0], but the same bug is also present in meson8.dtsi [0] https://lore.kernel.org/linux-amlogic/trinity-bf20bcb9-790b-4ab9-99e3-0831ef8257f4-1680878185420@3c-app-gmx-bap55/ Fixes: 57007bfb5469 ("ARM: dts: meson8: Fix the UART device-tree schema validation") Reported-by: Hans-Frieder Vogt # for meson8b.dtsi Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230516203029.1031174-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f22ab451aae2..59932fbfd5d5f 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -769,13 +769,13 @@ &uart_A { &uart_B { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; &uart_C { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; -- GitLab From efb09e4ea81a7d513e3c4c81b8108c2b8066bc66 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Wed, 10 May 2023 13:01:43 +0100 Subject: [PATCH 518/926] ARM: dts: sun5i: chip: Enable bluetooth The C.H.I.P has an rtl8723bs device with the bluetooth interface hooked up on UART3. Support for this didn't exist in mainline when the DTS was initially added, but it does now, so enable it. Signed-off-by: Jonathan McDowell Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/49ff7f3cc79838a55a89baae09a4ba12c88573fb.1683719613.git.noodles@earth.li Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun5i-r8-chip.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index fd37bd1f39208..4192c23848c31 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -255,6 +255,12 @@ &uart3 { pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + }; }; &usb_otg { -- GitLab From c7ea52ed614227a3e3eaafdbd7b477d0129ab6ed Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Wed, 10 May 2023 13:02:02 +0100 Subject: [PATCH 519/926] ARM: dts: sun5i: Add port E pinmux settings for mmc2 These alternate pins for mmc2 are brought out to the 40 pin U14 header on the C.H.I.P and can be used to add an external MMC device with a 4 bit interface. See https://byteporter.com/ntc-chip-micro-sd-slot/ for further details on how. Signed-off-by: Jonathan McDowell Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/7949169f581cab37175602188f44bc26e79a45c0.1683719613.git.noodles@earth.li Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun5i.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 2f901a0136763..d7c7b454a11a3 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -517,6 +517,15 @@ mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { bias-pull-up; }; + /omit-if-no-ref/ + mmc2_4bit_pe_pins: mmc2-4bit-pe-pins { + pins = "PE4", "PE5", "PE6", "PE7", + "PE8", "PE9"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", -- GitLab From 09d199b6dcb6bd94a1f00cfbfa1ee7d3841444b0 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Wed, 10 May 2023 13:02:28 +0100 Subject: [PATCH 520/926] ARM: dts: axp209: Add iio-hwmon node for internal temperature This adds a DT node to hook up the internal temperature ADC to the iio-hwmon driver. The various voltage + current ADCs are consumed and exposed by their respective drivers, but this is not and is always available. Naming chosen to match the axp20x_ prefix the power sensors use. Signed-off-by: Jonathan McDowell Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/2a9bd53a65c4a154cccba622c60cbffcdceaeb95.1683719613.git.noodles@earth.li Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/axp209.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index ca240cd6f6c35..469d0f7d5185c 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -48,6 +48,13 @@ * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf */ +/ { + pmic-temp { + compatible = "iio-hwmon"; + io-channels = <&axp_adc 4>; /* Internal temperature */ + }; +}; + &axp209 { compatible = "x-powers,axp209"; interrupt-controller; -- GitLab From 1798db0e623643dca5218056d419a7fa0f96bfd2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:52 +0200 Subject: [PATCH 521/926] arm64: tegra: Add missing cache properties on Tegra210 As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: tegra210-p2371-0000.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0e463b3cbe010..617583ff27366 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2000,6 +2000,7 @@ CPU_SLEEP: cpu-sleep { L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- GitLab From 3cdba279c5e9209fc1ffd6e56db1e79421555984 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 30 May 2023 19:56:23 +0200 Subject: [PATCH 522/926] arm64: dts: broadcom: Enable device-tree overlay support for RPi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the '-@' DTC option for the Raspberry Pi devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The Rasbperry Pi devices are well known for their GPIO header, that allow various "HATs" or other modules do be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~40%. For example, with v6.4-rc1 increase in size is as follows: bcm2711-rpi-400.dtb 27556 -> 38141 bytes bcm2711-rpi-4-b.dtb 27484 -> 38069 bytes bcm2711-rpi-cm4-io.dtb 27373 -> 38076 bytes bcm2837-rpi-3-a-plus.dtb 14930 -> 20713 bytes bcm2837-rpi-3-b.dtb 15107 -> 20979 bytes bcm2837-rpi-3-b-plus.dtb 15463 -> 21443 bytes bcm2837-rpi-cm3-io3.dtb 14429 -> 20098 bytes bcm2837-rpi-zero-2-w.dtb 14781 -> 20524 bytes Signed-off-by: Aurelien Jarno Link: https://lore.kernel.org/r/20220410225940.135744-2-aurelien@aurel32.net [ukleinek: rebased to v6.4, replaced by a single assignment to DTC_FLAGS] Signed-off-by: Uwe Kleine-König Acked-by: Conor Dooley Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 05d8c5ecf3b0f..8b4591ddd27cc 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 + +# Enables support for device-tree overlays +DTC_FLAGS := -@ + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ -- GitLab From e925743edc0d86fb846d952190d005bac8a6e373 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 30 May 2023 19:56:24 +0200 Subject: [PATCH 523/926] arm: dts: bcm: Enable device-tree overlay support for RPi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the '-@' DTC option for the Raspberry Pi devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The Rasbperry Pi devices are well known for their GPIO header, that allow various "HATs" or other modules do be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~40%. For example, with v6.4-rc1 increase in size is as follows: bcm2711-rpi-400.dtb 27556 -> 38141 bytes bcm2711-rpi-4-b.dtb 27484 -> 38069 bytes bcm2711-rpi-cm4-io.dtb 27373 -> 38076 bytes bcm2835-rpi-a.dtb 12879 -> 18235 bytes bcm2835-rpi-a-plus.dtb 13015 -> 18371 bytes bcm2835-rpi-b.dtb 12997 -> 18377 bytes bcm2835-rpi-b-plus.dtb 13237 -> 18666 bytes bcm2835-rpi-b-rev2.dtb 13085 -> 18514 bytes bcm2835-rpi-cm1-io1.dtb 13109 -> 18528 bytes bcm2835-rpi-zero.dtb 12923 -> 18311 bytes bcm2835-rpi-zero-w.dtb 13449 -> 18889 bytes bcm2836-rpi-2-b.dtb 14500 -> 20252 bytes bcm2837-rpi-3-a-plus.dtb 14930 -> 20713 bytes bcm2837-rpi-3-b.dtb 15107 -> 20979 bytes bcm2837-rpi-3-b-plus.dtb 15463 -> 21443 bytes bcm2837-rpi-cm3-io3.dtb 14429 -> 20098 bytes bcm2837-rpi-zero-2-w.dtb 14781 -> 20524 bytes Signed-off-by: Aurelien Jarno Link: https://lore.kernel.org/r/20220410225940.135744-3-aurelien@aurel32.net [ukleinek: rebased to v6.4-rc1] Signed-off-by: Uwe Kleine-König Acked-by: Conor Dooley Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..68e89f9289ef0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -85,6 +85,24 @@ dtb-$(CONFIG_SOC_SP7021) += \ sunplus-sp7021-demo-v3.dtb dtb-$(CONFIG_ARCH_AXXIA) += \ axm5516-amarillo.dtb +# Enables support for device-tree overlays +DTC_FLAGS_bcm2835-rpi-b := -@ +DTC_FLAGS_bcm2835-rpi-a := -@ +DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ +DTC_FLAGS_bcm2835-rpi-b-plus := -@ +DTC_FLAGS_bcm2835-rpi-a-plus := -@ +DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ +DTC_FLAGS_bcm2836-rpi-2-b := -@ +DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ +DTC_FLAGS_bcm2837-rpi-3-b := -@ +DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ +DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ +DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ +DTC_FLAGS_bcm2711-rpi-400 := -@ +DTC_FLAGS_bcm2711-rpi-4-b := -@ +DTC_FLAGS_bcm2711-rpi-cm4-io := -@ +DTC_FLAGS_bcm2835-rpi-zero := -@ +DTC_FLAGS_bcm2835-rpi-zero-w := -@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-b.dtb \ bcm2835-rpi-a.dtb \ -- GitLab From 86d904b6ef9f5e67a28e0a0bb58df898c08ae0b8 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 10 May 2023 18:03:58 +0900 Subject: [PATCH 524/926] arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes Add iommu-map and iommu-map-mask properties to the PCIe host nodes. Note that iommu-map-mask should be zero because the IPMMU assigns one micro TLB ID only, to the PCIe host. Also change the dma-ranges arguments for IOMMU. Note that dma-ranges can be used if the IOMMU is disabled. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230510090358.261266-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 6 ++++-- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 12 ++++++++---- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 ++++- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 6 ++++-- 10 files changed, 68 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c21b786851234..9065dc243428f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2359,8 +2359,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2371,6 +2371,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2386,8 +2388,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2398,6 +2400,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 82216ce7a92a9..75776decd2186 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2238,8 +2238,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2250,6 +2250,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2265,8 +2267,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2277,6 +2279,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 10abfde329d00..ad2e87b039acd 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1704,8 +1704,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1716,6 +1716,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 2828e05b40b34..2acf4067ab2f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2471,8 +2471,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2483,6 +2483,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2498,8 +2500,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2510,6 +2512,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 10b91e9733bf6..6d15229d25ab1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2778,8 +2778,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2790,6 +2790,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2805,8 +2807,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2817,6 +2819,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 3ea8572e917f8..17062ec506bea 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2565,8 +2565,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2577,6 +2577,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2592,8 +2594,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2604,6 +2606,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d52cb0b67d80c..d3f47da1b6267 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2445,8 +2445,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2457,6 +2457,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2472,8 +2474,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2484,6 +2486,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9584115c6b177..c758200384913 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2423,8 +2423,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2435,6 +2435,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; @@ -2450,8 +2452,8 @@ pciec1: pcie@ee800000 { <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -2462,6 +2464,8 @@ pciec1: pcie@ee800000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 318>; + iommu-map = <0 &ipmmu_hc 1 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index c4ac28a0f7161..5ed2daaca1f00 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1386,7 +1386,8 @@ pciec: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1399,6 +1400,8 @@ pciec: pcie@fe000000 { resets = <&cpg 319>; phys = <&pcie_phy>; phy-names = "pcie"; + iommu-map = <0 &ipmmu_vi0 5 1>; + iommu-map-mask = <0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 4529e9b57c331..1be0b99c15ed6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1870,8 +1870,8 @@ pciec0: pcie@fe000000 { <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + /* Map all possible DDR/IOMMU as inbound ranges */ + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; interrupts = , , ; @@ -1882,6 +1882,8 @@ pciec0: pcie@fe000000 { clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 319>; + iommu-map = <0 &ipmmu_hc 0 1>; + iommu-map-mask = <0>; status = "disabled"; }; -- GitLab From 0501fdec106a291c43b3c1b525cf22ab4c24b2d8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 23 May 2023 17:35:16 +0200 Subject: [PATCH 525/926] ARM: dts: iwg20d-q7-common: Fix backlight pwm specifier make dtbs_check: arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dtb: backlight: pwms: [[58, 0, 5000000], [0]] is too long From schema: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dtb: backlight: pwms: [[67, 0, 5000000], [0]] is too long From schema: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dtb: backlight: pwms: [[67, 0, 5000000], [0]] is too long From schema: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dtb: backlight: pwms: [[58, 0, 5000000], [0]] is too long From schema: Documentation/devicetree/bindings/leds/backlight/pwm-backlight.yaml PWM specifiers referring to R-Car PWM Timer Controllers should contain only two cells. Fix this by dropping the bogus third cell. Fixes: 6f89dd9e9325d05b ("ARM: dts: iwg20d-q7-common: Add LCD support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6e5c3167424a43faf8c1fa68d9667b3d87dc86d8.1684855911.git.geert+renesas@glider.be --- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 03caea6fc6ffa..4351c5a02fa59 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -49,7 +49,7 @@ audio_clock: audio_clock { lcd_backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; + pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; -- GitLab From 1a2c4e5635177939a088d22fa35c6a7032725663 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 May 2023 10:48:22 +0200 Subject: [PATCH 526/926] arm64: dts: renesas: ulcb-kf: Remove flow control for SCIF1 The schematics are misleading, the flow control is for HSCIF1. We need SCIF1 for GNSS/GPS which does not use flow control. Fixes: c6c816e22bc8 ("arm64: dts: ulcb-kf: enable SCIF1") Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230525084823.4195-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index efc80960380f4..c78b7a5c2e2aa 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -367,7 +367,7 @@ hscif0_pins: hscif0 { }; scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; + groups = "scif1_data_b"; function = "scif1"; }; @@ -397,7 +397,6 @@ &sound_clk_pins &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; - uart-has-rtscts; status = "okay"; }; -- GitLab From c776a2128dee50a9f10eace4a14ff894e1432a31 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 May 2023 10:48:23 +0200 Subject: [PATCH 527/926] arm64: dts: renesas: ulcb-kf: Add HSCIF1 node Exposed on CN4. Tested by connecting it to a Renesas Ebisu board. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230525084823.4195-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index c78b7a5c2e2aa..3885ef3454ff6 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -10,6 +10,7 @@ / { aliases { serial1 = &hscif0; serial2 = &scif1; + serial3 = &hscif1; mmc2 = &sdhi3; }; @@ -114,6 +115,14 @@ &hscif0 { status = "okay"; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -366,6 +375,11 @@ hscif0_pins: hscif0 { function = "hscif0"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + scif1_pins: scif1 { groups = "scif1_data_b"; function = "scif1"; -- GitLab From 04d28eb48ff30c059069e27689c4638c8a17134e Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:29 +0200 Subject: [PATCH 528/926] ARM: dts: stm32: add adc internal channels to stm32mp15 Add STM32 ADC2 internal channels VREFINT and VDDCORE to STM32MP15x SoCs. VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. The internal channels are defined in STM32MP15 SoC DT according to the generic IIO channel bindings. The STM32 driver does not support a mixed use of legacy and generic channels. When generic channels are defined, legacy channels are ignored. This involves that the board device trees using legacy bindings for ADC2, have to be reworked. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bf3830dca7428..7b360ee1ba2b4 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1093,6 +1093,8 @@ adc: adc@48003000 { adc1: adc@0 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0>; interrupt-parent = <&adc>; interrupts = <0>; @@ -1104,12 +1106,22 @@ adc1: adc@0 { adc2: adc@100 { compatible = "st,stm32mp1-adc"; #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x100>; interrupt-parent = <&adc>; interrupts = <1>; dmas = <&dmamux1 10 0x400 0x01>; dma-names = "rx"; status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; }; }; -- GitLab From 5988bd535975486a0a550fa8fe8a4ca2fd9231c9 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:30 +0200 Subject: [PATCH 529/926] ARM: dts: stm32: add vrefint calibration on stm32mp15 Describe vrefint calibration cell to be retrieved through bsec. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7b360ee1ba2b4..3d0c39d847b5f 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1630,6 +1630,9 @@ bsec: efuse@5c005000 { part_number_otp: part-number-otp@4 { reg = <0x4 0x1>; }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; -- GitLab From 95ee314b387d1eb30cb75022f6098845ae59a5b0 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:31 +0200 Subject: [PATCH 530/926] ARM: dts: stm32: add vrefint support to adc2 on stm32mp15 Set STM32 ADC2 as a consumer of BSEC on STM32MP15, to retrieve vrefint calibration data saved in OTP. During the calibration process vrefp is set to 3.3V and the data acquired is saved to the OTP. This data is used by the ADC driver to calculated the actual value of vrefp according to the formula: vrefp = 3.3 x vrefint_cal / vrefint_data The vrefint channel provides the actual value of vrefp, which can be used to correct ADC acquisition data. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3d0c39d847b5f..61508917521c3 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1113,6 +1113,8 @@ adc2: adc@100 { interrupts = <1>; dmas = <&dmamux1 10 0x400 0x01>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@13 { reg = <13>; -- GitLab From 7ea81ea58d61aed271afb83fef5935232ee43cd4 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:32 +0200 Subject: [PATCH 531/926] ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards U-Boot enables ADC1&2 to support USB power measurement and ADC calibration on STM32MP15x Disco boards. When leaving U-boot the ADCs do not return to power down state to keep ADC linear calibration available for kernel. Enable ADC1&2 by default on STM32MP15xx-DKx boards to align kernel DT with Uboot. This avoids to shutdown the ADCs VDDA, while the ADCs are not in power down. Use STM32 ADC generic bindings instead of legacy bindings on STM32MP15xx-DKx boards. The ADC pins on Arduino connector are not set by default. These pins are added in A7 Disco example DTs only. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index a6e2e20f12fa0..e78ba956b9d0f 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -93,28 +93,39 @@ vin: vin { &adc { pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; + pinctrl-0 = <&adc12_usb_cc_pins_a>; vdd-supply = <&vdd>; vdda-supply = <&vdd>; vref-supply = <&vrefbuf>; - status = "disabled"; + status = "okay"; adc1: adc@0 { + status = "okay"; /* * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: * 5 * (56 + 47kOhms) * 5pF => 2.5us. * Use arbitrary margin here (e.g. 5us). */ - st,min-sample-time-nsecs = <5000>; - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 6 13 18 19>; - status = "okay"; + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - /* AIN connector, USB Type-C CC1 & CC2 */ - st,adc-channels = <0 1 2 6 18 19>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + /* USB Type-C CC1 & CC2 */ + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + }; + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + }; }; }; -- GitLab From 765ce359d67fc089281bc5317230c310122f7a32 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:33 +0200 Subject: [PATCH 532/926] ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1 Use STM32 ADC generic bindings instead of legacy bindings on STM32MP157c-ed1 board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 8beb901be5065..66ed5f9921ba1 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -103,10 +103,20 @@ &adc { vref-supply = <&vdda>; status = "disabled"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - /* 16.5 ck_cycles sampling time */ - st,min-sample-time-nsecs = <400>; status = "okay"; + channel@0 { + reg = <0>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <400>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <400>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <400>; + }; }; }; -- GitLab From c46e9b6cc98245f7264a8d15394d1f95d433abec Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:34 +0200 Subject: [PATCH 533/926] ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon Use STM32 ADC generic bindings instead of legacy bindings on emtrion GmbH Argon boards. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index b01470a9a3d53..94e38141af672 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -97,9 +97,11 @@ &adc { adc1: adc@0 { pinctrl-names = "default"; pinctrl-0 = <&adc1_in6_pins_a>; - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <6>; status = "disabled"; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { -- GitLab From 1866e1f96cda9237d21e3028f036eb62e1e36d6e Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:35 +0200 Subject: [PATCH 534/926] ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc Use STM32 ADC generic bindings instead of legacy bindings on DHCOR DRC Compact board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- .../dts/stm32mp15xx-dhcor-drc-compact.dtsi | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index 39af79dc654cc..92d906bfd5d7d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -57,15 +57,35 @@ &adc { /* X11 ADC inputs */ status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; -- GitLab From 84cb6d8a0aafabe484203fc5fd63984a5aea8747 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 30 May 2023 14:45:36 +0200 Subject: [PATCH 535/926] ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench Use STM32 ADC generic bindings instead of legacy bindings on DHCOR Testbench board. The STM32 ADC specific binding to declare channels has been deprecated, hence adopt the generic IIO channels bindings, instead. The STM32MP151 device tree now exposes internal channels using the generic binding. This makes the change mandatory here to avoid a mixed use of legacy and generic binding, which is not supported by the driver. Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- .../boot/dts/stm32mp15xx-dhcor-testbench.dtsi | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi index faed31b6d84a1..ab7f0ba496396 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -41,15 +41,35 @@ &adc { status = "okay"; adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; }; adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; status = "okay"; + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; }; }; -- GitLab From 9bcfc3cdc903485a52c6f471f4ae96a41fa51803 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 May 2023 14:45:37 +0200 Subject: [PATCH 536/926] ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems The generic ADC channel binding is recommended over legacy one, update the DT to the modern binding. No functional change. For further details, see commit which adds the generic binding to STM32 ADC binding document: '664b9879f56e ("dt-bindings: iio: stm32-adc: add generic channel binding")' Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 18 +++++---- .../boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 38 +++++++++++++++---- 2 files changed, 40 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index c06edd2eacb0c..e61df23d361a7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -80,17 +80,19 @@ &adc { vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <0>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; +}; - adc2: adc@100 { - st,adc-channels = <1>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc2 { + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index cdd4902b59a97..0069ad75d55e5 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -111,17 +111,39 @@ &adc { vdda-supply = <&vdda>; vref-supply = <&vdda>; status = "okay"; +}; - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; +&adc1 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; }; - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; +}; + +&adc2 { + channel@0 { + reg = <0>; + st,min-sample-time-ns = <5000>; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + }; + + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; }; }; -- GitLab From 9da2bf3bcd8bbc0b700b44886a8e2a0036216748 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 1 Jun 2023 08:52:21 +0200 Subject: [PATCH 537/926] ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1 Correct the following warnings by adding the required supplies (AVDD, DVDD) for the ov5640 node. arch/arm/boot/dts/stm32mp157c-ev1.dtb: camera@3c: 'AVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml arch/arm/boot/dts/stm32mp157c-ev1.dtb: camera@3c: 'DVDD-supply' is a required property From schema: Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 49ca94c19b02b..af3800501875c 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -190,7 +190,9 @@ ov5640: camera@3c { reg = <0x3c>; clocks = <&clk_ext_camera>; clock-names = "xclk"; + AVDD-supply = <&v2v8>; DOVDD-supply = <&v2v8>; + DVDD-supply = <&v2v8>; powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; rotation = <180>; -- GitLab From dda66e99db331c19d7e9e6fe9422d479e27257ae Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2023 13:06:33 -0300 Subject: [PATCH 538/926] ARM: dts: imx7d-sdb: Describe the SD card regulator Improve the devicetree description by adding the SD card regulator that is controlled via GPIO5_2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 25681c430393d..c898d66e27adb 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -60,6 +60,17 @@ extended_io: gpio-expander@0 { }; }; + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <200000>; + off-on-delay-us = <20000>; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -477,6 +488,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; wakeup-source; keep-power-in-suspend; status = "okay"; -- GitLab From ba5e46f762f18d1759769cbcda714a6685bf1e4f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2023 13:06:34 -0300 Subject: [PATCH 539/926] ARM: dts: imx7d-sdb: Allow UHS modes Describe the SD1_VSELECT pad, which is necessary to allow UHS modes. Also, to support higher SD card speed modes, describe the 100MHz and 200MHz SD card pinctrl entries. Suggested-by: Ye Li Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 40 ++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index c898d66e27adb..c9f6137e73e73 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -484,8 +484,10 @@ &usbotg2 { }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; vmmc-supply = <®_sd1_vmmc>; @@ -743,6 +745,15 @@ MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -751,9 +762,28 @@ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; -- GitLab From 6266a0198f281198a3c49c68979d7b1959bd0dfc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2023 13:10:46 -0300 Subject: [PATCH 540/926] ARM: dts: imx6: Use the mux- prefix According to Documentation/devicetree/bindings/sound/imx-audmux.yaml, there must be a "mux-" prefix in the audmux port nodes. Add the "mux-" prefix to avoid devicetree schema warnings. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-qmx6.dtsi | 4 ++-- arch/arm/boot/dts/imx6q-cm-fx6.dts | 4 ++-- arch/arm/boot/dts/imx6q-display5.dtsi | 4 ++-- arch/arm/boot/dts/imx6q-kp.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-icore.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-mba6.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-var-dart.dtsi | 4 ++-- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 8 ++++---- 15 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi index 150d69858255d..05fd8ff4da1ee 100644 --- a/arch/arm/boot/dts/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi @@ -48,7 +48,7 @@ &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -60,7 +60,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) >; }; - audmux_aud6 { + mux-aud6 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 1ad41c944b4b9..ffb3b8eeae5db 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -141,7 +141,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_RCLKDIR | @@ -152,7 +152,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(3) >; }; - audmux4 { + mux-audmux4 { fsl,audmux-port = <3>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi index fef5d72545365..b88b8aa730d76 100644 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -147,7 +147,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -159,7 +159,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(5) >; }; - aud6 { + mux-aud6 { fsl,audmux-port = <5>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_RFSEL(8) | diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi index 5e0ed55600405..091903f53a560 100644 --- a/arch/arm/boot/dts/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/imx6q-kp.dtsi @@ -135,7 +135,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -147,7 +147,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(2) >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 6c487d40a3b76..f7ab7bbcc5607 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -187,7 +187,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -199,7 +199,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 0fa4b8eeddee7..29960d1cf6a03 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -171,7 +171,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -183,7 +183,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 2ffb21dd89f2a..bfade71490807 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -147,7 +147,7 @@ sound-spdif { &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -159,7 +159,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi index eb1ad28946d36..0883ef99cded0 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -179,7 +179,7 @@ sound_codec: simple-audio-card,codec { &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -191,7 +191,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index ef3f88c3615fd..d339957cc0973 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -118,7 +118,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -130,7 +130,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) >; }; - audmux_aud4 { + mux-aud4 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 23c318d9636fc..efe11524b885d 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -109,7 +109,7 @@ &audmux { status = "okay"; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSDIR | @@ -121,7 +121,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) >; }; - audmux_aud4 { + mux-aud4 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi index 34d5cf7cee0b1..212c623418fc4 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -129,7 +129,7 @@ sound { &audmux { status = "okay"; - ssi0 { + mux-ssi0 { fsl,audmux-port = ; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -141,7 +141,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) >; }; - aud3 { + mux-aud3 { fsl,audmux-port = ; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index 51d28e275aa64..a41e47c06ef40 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -75,7 +75,7 @@ dailink_master: simple-audio-card,codec { &audmux { status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -87,7 +87,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index a197bac95cbac..e2fe337f7d9ed 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -216,7 +216,7 @@ codec_dai: simple-audio-card,codec { &audmux { status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -228,7 +228,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - pins5 { + mux-pins5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi index c41cac502bacc..200559d7158dc 100644 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi @@ -39,7 +39,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -51,7 +51,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(2) >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index abd72d72ae996..9ff183e4e069a 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -848,7 +848,7 @@ &audmux { pinctrl-0 = <&pinctrl_audmux>; status = "okay"; - ssi1 { + mux-ssi1 { fsl,audmux-port = <0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -860,7 +860,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(2) >; }; - aud3 { + mux-aud3 { fsl,audmux-port = <2>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -868,7 +868,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(0) >; }; - ssi2 { + mux-ssi2 { fsl,audmux-port = <1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_SYN | @@ -880,7 +880,7 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(4) >; }; - aud5 { + mux-aud5 { fsl,audmux-port = <4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN -- GitLab From 106924746955cfd1f37f6dbb97f94f5cf7db1d7c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2023 17:50:47 -0300 Subject: [PATCH 541/926] ARM: dts: imx: Use 'pmic' as node name Devicetree node names should be generic. Use 'pmic' as node name to avoid devicetree check warning from pfuze100.yaml. Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-novena.dts | 2 +- arch/arm/boot/dts/imx6q-pistachio.dts | 2 +- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi | 2 +- arch/arm/boot/dts/imx6sl-evk.dts | 2 +- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 2 +- arch/arm/boot/dts/imx6sx-sdb.dts | 2 +- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 2 +- arch/arm/boot/dts/imx6ul-pico.dtsi | 2 +- arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +- arch/arm/boot/dts/imx7d-pico.dtsi | 2 +- arch/arm/boot/dts/imx7d-sdb.dts | 2 +- arch/arm/boot/dts/imx7s-warp.dts | 2 +- 18 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 24c7f535f63bd..0366d1037ef4a 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -177,7 +177,7 @@ codec: sgtl5000@a { VDDIO-supply = <®_3p3v>; }; - pmic: pf0100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 9591848cbd37c..3815cb660ff79 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -134,7 +134,7 @@ &pinctrl_stmpe2 &pinctrl_pfuze>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; interrupt-parent = <&gpio3>; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 522a51042965a..0ba802b891b5b 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -206,7 +206,7 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index ee8c0bd3ecfd5..a7d5a68110fcf 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -308,7 +308,7 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2_novena>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts index bad8d831e64e6..109b46a22b5e8 100644 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -208,7 +208,7 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index f7ab7bbcc5607..a642be45ffe2e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -398,7 +398,7 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index f79caa36f3d25..68e97180d33e3 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -336,7 +336,7 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 53b080c97f2d9..4fe58764b929a 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -338,7 +338,7 @@ ov5640_to_mipi_csi2: endpoint { }; }; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi index bf86b639fdac3..9b8c9c23ab547 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -27,7 +27,7 @@ &i2c3 { pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index dc5d596c18db4..239bc6dfc5846 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -160,7 +160,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 7dda42553f4bc..48f19dede467f 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -15,7 +15,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 969cfe920d252..e05a1be5553c8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -14,7 +14,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index b9a1401e6c6d2..bfcd8f7d86dde 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -171,7 +171,7 @@ proximity: sx9500@28 { reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; }; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze200"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi index 357ffb2f5ad61..4ffe99ed55ca2 100644 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/imx6ul-pico.dtsi @@ -131,7 +131,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index a31de900139d6..9c6476bda4a02 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -159,7 +159,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index e0bff39e8d3e1..73d90845e85c2 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -170,7 +170,7 @@ &i2c4 { pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index c9f6137e73e73..cc9b8570ed4db 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -275,7 +275,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index e8734d218b9de..ba7231b364bb8 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -94,7 +94,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic: pfuze3000@8 { + pmic: pmic@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; -- GitLab From 3c52e3e454079a74fd9c997d94c886fe47bc936e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 27 May 2023 17:50:48 -0300 Subject: [PATCH 542/926] ARM: dts: imx6ul-ccimx6ulsom: Fix the "coin" regulator name As documented in pfuze100.yaml, the correct name for the regulator is "coin", so change it to fix the following DT check warning: imx6ul-ccimx6ulsbcexpress.dtb: pmic@8: regulators: 'vcoin' does not match any of the regexes: Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi index b5781c3656d1a..7d1a391431bd9 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -158,7 +158,7 @@ ldo4_ext: vldo4 { regulator-max-microvolt = <3300000>; }; - vcoin_chg: vcoin { + vcoin_chg: coin { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; -- GitLab From 69e2f37a6ddc2d1cd964c8d3af2581ea21be764d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 06:01:19 -0500 Subject: [PATCH 543/926] arm64: dts: imx8mp-beacon-kit: Enable WM8962 Audio CODEC The baseboard has an WM8962 Audio CODEC connected to the SAI3 peripheral. The CODEC supports stereo in and out and a microphone input connected to the headphone jack. Route this CODEC through the simple-audio-card driver. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-beacon-kit.dts | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index cdae45a48c2cb..06e91297fb163 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -118,6 +118,15 @@ pcie0_refclk: clock-pcie { clock-frequency = <100000000>; }; + reg_audio: regulator-wm8962 { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -137,6 +146,32 @@ reg_usb1_host_vbus: regulator-usb1-vbus { gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + frame-master; + bitclock-master; + }; + }; }; &ecspi2 { @@ -239,6 +274,34 @@ &i2c4 { clock-frequency = <384000>; status = "okay"; + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wm8962>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22576000>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + #sound-dai-cells = <0>; + }; + pca6416: gpio@20 { compatible = "nxp,pcal6416"; reg = <0x20>; @@ -315,6 +378,16 @@ &pcie_phy { status = "okay"; }; +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -477,6 +550,16 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ @@ -547,4 +630,10 @@ pinctrl_usdhc2_gpio: usdhc2gpiogrp { MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; }; + + pinctrl_wm8962: wm8962grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 + >; + }; }; -- GitLab From f5402fff11b00466b664ad75d951a06fe8e4a20d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 28 May 2023 06:22:53 -0500 Subject: [PATCH 544/926] arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card Instead of using a custom glue layer connecting the wm8962 CODEC to the SAI3 sound-dai, migrate the sound card to simple-audio-card. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../freescale/imx8mn-beacon-baseboard.dtsi | 37 +++++++++++++------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 6dce77a6114c2..038ef8a3e6043 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -74,18 +74,30 @@ reg_usb_otg_vbus: regulator-usb { enable-active-high; }; - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + frame-master; + bitclock-master; + }; }; }; @@ -183,6 +195,7 @@ wm8962: audio-codec@1a { 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; + #sound-dai-cells = <0>; }; }; -- GitLab From d874b9f7f28335809df27d6e0def4103e34c534a Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Mon, 29 May 2023 11:57:28 +0200 Subject: [PATCH 545/926] arm64: dts: imx8mp-msc-sm2s: Add sound card The MSC SM2-MB-EP1 carrier board for the SM2S-IMX8PLUS SMARC module has an NXP SGTL5000 audio codec connected to I2S-0 (sai2). This requires to: * add the power supplies (always on) * enable sai2 with pinmuxes * reparent the CLKOUT1 clock that feeds the codec SYS_MCLK to IMX8MP_CLK_24M in order it to generate an accurate 24 MHz rate Signed-off-by: Luca Ceresoli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-msc-sm2s-ep1.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts index 470ff8e31e327..64d522c71a448 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -14,6 +14,67 @@ / { compatible = "avnet,sm2s-imx8mp-14N0600E-ep1", "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp", "fsl,imx8mp"; + + reg_vcc_3v3_audio: 3v3-audio-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_AUD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vcc_1v8_audio: 1v8-audio-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_AUD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sgtl5000-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,bitclock-master = <&codec_dai>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + + assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + clocks = <&clk IMX8MP_CLK_CLKOUT1>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + VDDA-supply = <®_vcc_3v3_audio>; + VDDD-supply = <®_vcc_1v8_audio>; + VDDIO-supply = <®_vcc_1v8_audio>; + }; +}; + +/* I2S-0 = sai2 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + + fsl,sai-mclk-direction-output; + status = "okay"; }; &flexcan1 { @@ -32,6 +93,15 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_smarc_gpio>; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + >; + }; + pinctrl_smarc_gpio: smarcgpiosgrp { fsl,pins = , /* GPIO0 */ -- GitLab From 26ca44bdbd13edbe6cbe0dc63327c3316ce01bae Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 29 May 2023 15:33:12 -0400 Subject: [PATCH 546/926] arm64: dts: imx8mn-var-som: add 20ms delay to ethernet regulator enable This commit is taken from Variscite linux kernel public git repository. Original patch author: Nate Drude See: https://github.com/varigit/linux-imx/blob/5.15-2.0.x-imx_var01/drivers/net/ethernet/freescale/fec_main.c#L3993-L4050 The ethernet phy reset was moved from the fec controller to the mdio bus, see for example: 0e825b32c033e1998d0ebaf247f5dab3c340e3bf When the fec driver managed the reset, the regulator had time to settle during the fec phy reset before calling of_mdiobus_register, which probes the mii bus for the phy id to match the correct driver. Now that the mdio bus controls the reset, the fec driver no longer has any delay between enabling the regulator and calling of_mdiobus_register. If the regulator voltage has not settled, the phy id will not be read correctly and the generic phy driver will be used. The following call tree explains in more detail: fec_probe fec_reset_phy <- no longer introduces delay after migration to mdio reset fec_enet_mii_init of_mdiobus_register of_mdiobus_register_phy fwnode_mdiobus_register_phy get_phy_device <- mii probe for phy id to match driver happens here ... fwnode_mdiobus_phy_device_register phy_device_register mdiobus_register_device mdio_device_reset <- mdio reset assert / deassert delay happens here Add a 20ms enable delay to the regulator to fix the issue. Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 682b8e08adcd8..7e5bbd5109eb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -27,6 +27,7 @@ reg_eth_phy: regulator-eth-phy { regulator-name = "eth_phy_pwr"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; -- GitLab From 37d61885acdec51bb062cf33e0ad6fdc40114ff1 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 29 May 2023 15:35:26 -0400 Subject: [PATCH 547/926] arm64: dts: imx8mn-var-som-symphony: adapt FEC pinctrl for SOMs with onboard PHY The VAR SOM symphony carrier board can be used with SOMs which have a soldered ethernet PHY onboard and with SOMs which don't have one. For SOMs with an onboard PHY, the PHY on the cartrier board is not used, and GPIO1_IO9 is used as a reset line to the onboard PHY. For SOMs without an onboard PHY, the PHY on the carrier board is used. For this configuration, pca9534 GPIO 5 (located on the carrier board) is used as a reset line to the PHY, and GPIO1_IO9 is not used. GPIO1_IO9 is not connected to any user-accessible pins or functions, and leaving it enabled in the mux pinctrl for both configurations is safe. Signed-off-by: Hugo Villeneuve Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mn-var-som-symphony.dts | 40 ------------------- 1 file changed, 40 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 3ed7021a487cf..406a711486da5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -152,46 +152,6 @@ &usbotg1 { extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; }; -&pinctrl_fec1 { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - -&pinctrl_fec1_sleep { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 - MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 - MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 - MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 - MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 - MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 - MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 - MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 - MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 - MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 - MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = < -- GitLab From 17afe1a31b993bf0d6cdc4a1455f9f9f2caaa964 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 May 2023 17:06:45 -0300 Subject: [PATCH 548/926] ARM: dts: imx: Use 'eeprom' as node name Devicetree node names should be generic. Use 'eeprom' as node name to avoid devicetree check warning from at24.yaml. Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-tqma53.dtsi | 2 +- arch/arm/boot/dts/imx6q-display5.dtsi | 2 +- arch/arm/boot/dts/imx6q-h100.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 7e7f9f3b3906e..d930739674a19 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -274,7 +274,7 @@ sensor1: lm75@48 { reg = <0x48>; }; - eeprom: 24c64@50 { + eeprom: eeprom@50 { compatible = "atmel,24c64"; pagesize = <32>; reg = <0x50>; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi index b88b8aa730d76..4ab31f2217cdb 100644 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -276,7 +276,7 @@ &i2c3 { pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - at24@50 { + eeprom@50 { compatible = "atmel,24c256"; pagesize = <64>; reg = <0x50>; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 6406ade14f57b..3fe4591e21f57 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -166,7 +166,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_h100_i2c1>; status = "okay"; - eeprom: 24c02@51 { + eeprom: eeprom@51 { compatible = "microchip,24c02", "atmel,24c02"; reg = <0x51>; }; -- GitLab From 49daa70b4f726e0de632e11e98ae8bfea3efd27d Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 30 May 2023 14:03:31 +0200 Subject: [PATCH 549/926] ARM: dts: imx6qdl: vicut1: The sgtl5000 uses i2s not ac97 According to Documentation/devicetree/bindings/sound/fsl,ssi.txt 'fsl,mode' should be specified for AC97 mode only. The 'fsl,ssi' documentation doesn't say anything about specifying 'sound-dai-cells' so we'll remove that as well. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c4e6cf0527ba4..74017ae5a67a0 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -393,8 +393,6 @@ &pwm3 { }; &ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; status = "okay"; }; -- GitLab From b007934665132e387275438e91e2151464bb88a5 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 30 May 2023 14:03:32 +0200 Subject: [PATCH 550/926] ARM: dts: imx6dl: prtvt7: Adjust default backlight brightness to 65 This commit changes the default brightness level of the backlight on the prtvt7 device from 20 to 65, roughly equivalent to 75% of the maximum brightness level defined in the "brightness-levels" property. The adjustment provides a more optimal default brightness for the device, improving the overall user experience. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index a1eb53851794a..5e68802fee6d6 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -24,7 +24,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm1 0 500000 0>; brightness-levels = <0 20 81 248 1000>; - default-brightness-level = <20>; + default-brightness-level = <65>; num-interpolated-steps = <21>; power-supply = <®_bl_12v0>; }; -- GitLab From e76194fc6e5e0d22e1ae6b7c19e010718bd61ca2 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 30 May 2023 14:03:33 +0200 Subject: [PATCH 551/926] ARM: dts: imx6dl: prtvt7: Remove touchscreen inversion This touchscreen does not seem to be inverted in any axis, so remove these DT properties. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtvt7.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 5e68802fee6d6..45bc6e3245f6a 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -267,8 +267,6 @@ touchscreen { <&adc_ts 5>; io-channel-names = "y", "z1", "z2", "x"; touchscreen-min-pressure = <64687>; - touchscreen-inverted-x; - touchscreen-inverted-y; touchscreen-x-plate-ohms = <300>; touchscreen-y-plate-ohms = <800>; }; -- GitLab From fb9e67f279058a9fb9c7e3044479419dcef00d8b Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Tue, 30 May 2023 14:03:34 +0200 Subject: [PATCH 552/926] ARM: dts: imx6q: prtwd2: Correct iomux configuration for ENET MDIO and MDC This commit addresses a misconfiguration in the prtwd2 device tree source. Specifically, the ENET MDIO and MDC pins were mistakenly assigned to the Ethernet block, while they are actually used by the I2C4 interface. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-prtwd2.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts index 54a57a4548e24..792b8903d3451 100644 --- a/arch/arm/boot/dts/imx6q-prtwd2.dts +++ b/arch/arm/boot/dts/imx6q-prtwd2.dts @@ -156,9 +156,6 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 /* nINTRP */ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 - - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 >; }; -- GitLab From bcadb701689a6569fbec7e60e21a73c586d0ed3b Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:35 +0200 Subject: [PATCH 553/926] ARM: dts: imx6dl: lanmcu: Disable unused USB PHY nodes In the imx6dl-lanmcu system, the usbh2 and usbh3 interfaces are not in use. However, the related USB PHY nodes (usbphynop1 and usbphynop2) are enabled by default in the imx6qdl.dtsi file, which can lead to confusion and potential resource mismanagement. This commit explicitly disables these unused USB PHY nodes in the imx6dl-lanmcu device tree, aligning the configuration more accurately with the actual hardware setup. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-lanmcu.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts index fa823988312d6..bbfa921e657d6 100644 --- a/arch/arm/boot/dts/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -260,6 +260,14 @@ &usbotg { status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; -- GitLab From 5e7487d08d5cf3a39aeb98c064c4a4f3bf5dadd0 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:36 +0200 Subject: [PATCH 554/926] ARM: dts: imx6dl: lanmcu: Configure over-current polarity for USB OTG node This commit adds the 'over-current-active-low' flag to the USB OTG node in the imx6dl-lanmcu device tree. This flag is necessary because the hardware signals over-current conditions by pulling the line low. Without this flag, the kernel could misinterpret an over-current condition, leading to unexpected behavior. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-lanmcu.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts index bbfa921e657d6..7c62db91173b7 100644 --- a/arch/arm/boot/dts/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -257,6 +257,7 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; -- GitLab From 543b2064b2f994bdc5d8de82c95f29a1417ee81c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:37 +0200 Subject: [PATCH 555/926] ARM: dts: imx6dl: Add trip points to thermal zones on several devices Kernel v6.3-rc1 prints errors due to missing trip points in thermal zones. These errors indicate a lack of critical temperature threshold settings, causing warnings at boot. To silence these errors, this patch introduces trip points into the thermal zones of several imx6dl based devices. The following devices are updated: - plym2m - prtvt7 - victgo - vicut1 These devices are automotive grade and expected to operate up to 105C. An exception is the plym2m, an industrial grade device, which is certified to work up to 85C. The added trip points act as alert thresholds but do not trigger any actions except warnings. This behavior is by design, as these devices should maintain their performance until the end, without any thermal throttling. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plym2m.dts | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/imx6dl-prtvt7.dts | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/imx6dl-victgo.dts | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 8 ++++++++ 4 files changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index e3c10483f33bd..dfa8110b1d97b 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -113,18 +113,42 @@ chassis-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 45bc6e3245f6a..568e98cb62aaf 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -246,18 +246,42 @@ chassis-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 23274be08e61f..4875afadb6300 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -74,18 +74,42 @@ chassis-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal0 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; touch-thermal1 { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&touch_temp1>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 74017ae5a67a0..ca9c20e90bcf3 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -169,6 +169,14 @@ chassis-thermal { polling-delay = <20000>; polling-delay-passive = <0>; thermal-sensors = <&tsens0>; + + trips { + alert { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + }; }; }; }; -- GitLab From d5a17fb69f909a97fffe3fd7eb3cdde526a7b4d7 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:38 +0200 Subject: [PATCH 556/926] ARM: dts: imx6dl: vicut1: Address USB related warnings This patch addresses several USB-related warnings in the device tree for the imx6dl vicut1 system. Specifically, it disables the unused usbphynop1 and usbphynop2 USB PHYs, and disables unsupported over-current detection. This action mitigates the following kernel warnings: usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests imx_usb 2184200.usb: No over-current polarity defined Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index ca9c20e90bcf3..96e4f4b0b248f 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -432,6 +432,7 @@ &usbh1 { pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -445,6 +446,14 @@ &usbotg { status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; -- GitLab From 768b95f963b804dbaf559c61899abaae48bc9512 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:39 +0200 Subject: [PATCH 557/926] ARM: dts: imx6dl: alti6p: fix different USB related warnings Fix USB-related warnings in imx6dl alti6p device tree by disabling unused usbphynop1 and usbphynop2 USB PHYs and properly configuring over-current detection on related ports. This fixes the following warnings with the current kernel: usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests imx_usb 2184200.usb: No over-current polarity defined Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-alti6p.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts index e6a4e27706400..4989e8d069a1c 100644 --- a/arch/arm/boot/dts/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -361,6 +361,7 @@ &usbh1 { pinctrl-0 = <&pinctrl_usbh1>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; @@ -370,9 +371,18 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; -- GitLab From 5fdc9d1e9a8cd1d8143b54a9f1bddc6b0483d67f Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:40 +0200 Subject: [PATCH 558/926] ARM: dts: imx6dl: prtmvt: fix different USB related warnings Fix USB-related warnings in imx6dl prtmvt device tree by disabling unused usbphynop1 and usbphynop2 USB PHYs and over-current detection which is not supported on USB h1 port. This fixes the following warnings with the current kernel: usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests imx_usb 2184200.usb: No over current polarity defined By the way, fix over-current detection on usbotg port. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtmvt.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts index 5f4fa796ca18f..773a84a5739df 100644 --- a/arch/arm/boot/dts/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtmvt.dts @@ -560,6 +560,7 @@ &usbh1 { pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -569,10 +570,18 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; -- GitLab From 18ee5b92ed5e27b667a3a464cbf7e9e7191765fa Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:41 +0200 Subject: [PATCH 559/926] ARM: dts: imx6qp: prtwd3: Enable USB over current detection on USB OTG port The imx6qp-prtwd3 board supports USB over current detection on the USB OTG port, however, it was previously disabled in the device tree. This commit enables the over current detection by changing the device tree setting from 'disable-over-current' to 'over-current-active-low'. This could potentially protect the USB port from damage due to over current situations. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qp-prtwd3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts index cf6571cc4682e..ae00d538a4dfc 100644 --- a/arch/arm/boot/dts/imx6qp-prtwd3.dts +++ b/arch/arm/boot/dts/imx6qp-prtwd3.dts @@ -350,7 +350,7 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; -- GitLab From 84bd06535980595db95255c2c894845902dfb241 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:42 +0200 Subject: [PATCH 560/926] ARM: dts: imx6ul: prti6g: fix USB over-current detection on USB OTG port USB over-current detection is supported on this board. So, activate it and fixes the following kernel warnings: imx_usb 2184200.usb: No over current polarity defined Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-prti6g.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts index b7c96fbe7a919..c3c50f51a5a86 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/imx6ul-prti6g.dts @@ -177,6 +177,7 @@ &uart1 { &usbotg1 { dr_mode = "host"; + over-current-active-low; status = "okay"; }; -- GitLab From 31d682f1186c3c85eb8e7416a0b1d929b283ad43 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:43 +0200 Subject: [PATCH 561/926] ARM: dts: imx6dl: plybas: fix USB over-current detection on USB OTG port USB over-current detection is supported on this board. So, activate it. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plybas.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index e98046eea7a41..84f34da06267e 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -235,7 +235,7 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; -- GitLab From 1d14bd943fa2bbdfda1efbcc080b298fed5f1803 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:44 +0200 Subject: [PATCH 562/926] ARM: dts: imx6dl: prtrvt, prtvt7, prti6q, prtwd2: fix USB related warnings Fix USB-related warnings in prtrvt, prtvt7, prti6q and prtwd2 device trees by disabling unused usbphynop1 and usbphynop2 USB PHYs and providing proper configuration for the over-current detection. This fixes the following warnings with the current kernel: usb_phy_generic usbphynop1: dummy supplies not allowed for exclusive requests usb_phy_generic usbphynop2: dummy supplies not allowed for exclusive requests imx_usb 2184200.usb: No over current polarity defined By the way, fix over-current detection on usbotg port for prtvt7, prti6q and prtwd2 boards. Only prtrvt do not have OC on USB OTG port. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtrvt.dts | 4 ++++ arch/arm/boot/dts/imx6qdl-prti6q.dtsi | 11 ++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts index 56bb1ca56a2df..36b031236e475 100644 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts @@ -124,6 +124,10 @@ &usbh1 { status = "disabled"; }; +&usbotg { + disable-over-current; +}; + &vpu { status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi index f0db0d4471f40..36f84f4da6b0d 100644 --- a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi +++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi @@ -69,6 +69,7 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; phy_type = "utmi"; dr_mode = "host"; + disable-over-current; status = "okay"; }; @@ -78,10 +79,18 @@ &usbotg { pinctrl-0 = <&pinctrl_usbotg>; phy_type = "utmi"; dr_mode = "host"; - disable-over-current; + over-current-active-low; status = "okay"; }; +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; -- GitLab From 5ef0f31fb9285d72bbe3bfd80be34284d4b9c7dd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 30 May 2023 14:03:45 +0200 Subject: [PATCH 563/926] ARM: dts: imx6qdl: vicut1: rename power to power-button In order to address the warnings about the naming convention for keys, this commit renames the 'power' key to 'power-button' in the vicut1-12inch device tree source file. The warning in question is as follows: arch/arm/boot/dts/imx6q-vicut1.dtb: gpio-keys: 'power' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+' The referenced warning originates from the following schema: Documentation/devicetree/bindings/input/gpio-keys.yaml Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi index f505f27045305..73f381e144672 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi @@ -10,7 +10,7 @@ gpio-keys { pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; - power { + power-button { label = "Power Button"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; linux,code = ; -- GitLab From a27335b3f1e03fb3d0cdd28066b4d7d28e71e3a9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 30 May 2023 10:11:12 -0300 Subject: [PATCH 564/926] arm64: dts: imx8mm-evk: Add HDMI support imx8mm-evk has a MIPI DSI port that can be used with a ADV7535 MIPI DSI to HDMI bridge. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 3f9dfd4d38848..df8e808ac4739 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -19,6 +19,18 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x80000000>; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -303,6 +315,41 @@ &i2c2 { pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -348,6 +395,26 @@ pca6416: gpio@20 { }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + &pcie_phy { fsl,refclk-pad-mode = ; fsl,tx-deemph-gen1 = <0x2d>; -- GitLab From 0dc9d469c2bda63dcf8c9afd956fc39db6f2afca Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 30 May 2023 16:12:34 +0200 Subject: [PATCH 565/926] arm64: dts: tqma8mqml: Add vcc supply to i2c eeproms Fixes the warnings: at24 0-0053: supply vcc not found, using dummy regulator at24 0-0057: supply vcc not found, using dummy regulator Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 12260290c109e..b4466a26d838a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -219,12 +219,14 @@ eeprom1: eeprom@53 { read-only; reg = <0x53>; pagesize = <16>; + vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + vcc-supply = <®_vcc3v3>; }; }; -- GitLab From 3f89845698b7deecb3ea1e25a21d92b376796873 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 30 May 2023 16:19:21 -0300 Subject: [PATCH 566/926] arm64: dts: imx8mm-phg: Add display support The imx8mm-phg has a SN65DSI83 MIPI-DSI to LVDS bridge. Add suppor for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phg.dts | 87 ++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts index e9447738b104f..606a4f4d5f150 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts @@ -80,6 +80,35 @@ reg_usdhc2_vmmc: regulator-vmmc { startup-delay-us = <100>; off-on-delay-us = <12000>; }; + + panel { + compatible = "panel-lvds"; + width-mm = <170>; + height-mm = <28>; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <49500000>; + hactive = <800>; + hback-porch = <48>; + hfront-porch = <312>; + hsync-len = <40>; + vactive = <600>; + vback-porch = <19>; + vfront-porch = <61>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; }; &ecspi1 { @@ -113,8 +142,60 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bridge>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + data-lanes = <1 2>; + lane-polarities = <1 0 0 0 0>; + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; +}; + + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -166,6 +247,12 @@ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 >; }; + pinctrl_dsi_bridge: dsibridgeggrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x19 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 -- GitLab From d5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 May 2023 15:51:08 +0200 Subject: [PATCH 567/926] dt-bindings: xilinx: Switch xilinx.com emails to amd.com @xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Sebastian Reichel Acked-by: Wolfram Sang # for I2C Acked-by: Mark Brown Acked-by: Jassi Brar Acked-by: Damien Le Moal Acked-by: Krzysztof Kozlowski Acked-by: Guenter Roeck Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com --- Documentation/devicetree/bindings/arm/xilinx.yaml | 2 +- Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 2 +- .../devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 2 +- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml | 4 ++-- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 2 +- .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml | 2 +- Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml | 2 +- .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml | 2 +- Documentation/devicetree/bindings/gpio/gpio-zynq.yaml | 2 +- Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml | 2 +- .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 2 +- Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 2 +- .../devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 2 +- .../devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml | 2 +- .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 2 +- .../bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 2 +- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +- .../devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 2 +- .../devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml | 2 +- Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml | 2 +- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 2 +- Documentation/devicetree/bindings/spi/spi-cadence.yaml | 2 +- Documentation/devicetree/bindings/spi/spi-xilinx.yaml | 2 +- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 2 +- Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml | 2 +- Documentation/devicetree/bindings/timer/cdns,ttc.yaml | 2 +- .../devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml | 4 ++-- 29 files changed, 31 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml index b3071d10ea654..f57ed0347894b 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Platforms maintainers: - - Michal Simek + - Michal Simek description: | Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 9b31f864e071e..82e15df5cd12a 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ceva AHCI SATA Controller maintainers: - - Piyush Mehta + - Piyush Mehta description: | The Ceva SATA controller mostly conforms to the AHCI interface with some diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index c1f04830a8329..02bd556bd91a6 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx clocking wizard maintainers: - - Shubhrajyoti Datta + - Shubhrajyoti Datta description: The clocking wizard is a soft ip clocking block of Xilinx versal. It diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 229af98b1d305..93ae349cf9e9e 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Versal clock controller maintainers: - - Michal Simek + - Michal Simek - Jolly Shah - Rajan Vaja diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml index 9e8fbd02b150e..8aead97a585b1 100644 --- a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx ZynqMP AES-GCM Hardware Accelerator maintainers: - - Kalyani Akula - - Michal Simek + - Kalyani Akula + - Michal Simek description: | The ZynqMP AES-GCM hardened cryptographic accelerator is used to diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index f14f7b454f07c..910bebe6cfa80 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx firmware driver maintainers: - - Nava kishore Manne + - Nava kishore Manne description: The zynqmp-firmware node describes the interface to platform firmware. ZynqMP has an interface to communicate with secure firmware. diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml index f47b6140a7429..04dcadc2c20e9 100644 --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq FPGA Manager maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml index ac6a207278d59..26f18834caa3a 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Versal FPGA driver. maintainers: - - Nava kishore Manne + - Nava kishore Manne description: | Device Tree Versal FPGA bindings for the Versal SoC, controlled diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml index 00a8d92ff7368..1390ae103b0b2 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Ultrascale MPSoC FPGA Manager maintainers: - - Nava kishore Manne + - Nava kishore Manne description: | Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 572e1718f5015..5e2496379a3c8 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq GPIO controller maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml index f333ee2288e76..c1060e5fcef3a 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx AXI GPIO controller maintainers: - - Neeli Srinivas + - Neeli Srinivas description: The AXI GPIO design provides a general purpose input/output interface diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml index 31c0fc3459035..18e61aff21857 100644 --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -12,7 +12,7 @@ description: PS_MODE). Every pin can be configured as input/output. maintainers: - - Piyush Mehta + - Piyush Mehta properties: compatible: diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml index cb24d7b3221c8..ff57c5416ebcb 100644 --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence I2C controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: /schemas/i2c/i2c-controller.yaml# diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml index 374ffe64016f3..aeaddbf574b0b 100644 --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml @@ -33,7 +33,7 @@ description: | +------------------------------------------+ maintainers: - - Shubhrajyoti Datta + - Shubhrajyoti Datta properties: compatible: diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml index 7d77823dbb7a1..43daf837fc9f0 100644 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx MIPI CSI-2 Receiver Subsystem maintainers: - - Vishal Sagar + - Vishal Sagar description: | The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index e68c4306025a1..6b62d5d834769 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -9,7 +9,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski - Manish Narani - - Michal Simek + - Michal Simek description: | Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 8f72e2f8588ab..7864a1c994eb0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -9,7 +9,7 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski - Manish Narani - - Michal Simek + - Michal Simek description: The Zynq DDR ECC controller has an optional ECC support in half-bus width diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 24ddc2855b946..4734be456bde6 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CPM Host Controller device tree for Xilinx Versal SoCs maintainers: - - Bharat Kumar Gogada + - Bharat Kumar Gogada allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml index 598a042850b89..b85f9e36ce4b7 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Pinctrl maintainers: - - Sai Krishna Potthuri + - Sai Krishna Potthuri description: | Please refer to pinctrl-bindings.txt in this directory for details of the diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 2722dc7bb03da..cdebfa991e066 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx ZynqMP Pinctrl maintainers: - - Sai Krishna Potthuri + - Sai Krishna Potthuri - Rajan Vaja description: | diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml index 11f1f98c1cdc1..45792e216981a 100644 --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq MPSoC Power Management maintainers: - - Michal Simek + - Michal Simek description: | The zynqmp-power node describes the power management configurations. diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml index 7ed0230f6c677..d1f5eb996dba0 100644 --- a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml @@ -11,7 +11,7 @@ description: The RTC controller has separate IRQ lines for seconds and alarm. maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: rtc.yaml# diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index a8b323d7bf945..e35ad1109efc8 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence UART Controller maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index b0f83b5c2cdd8..b7552739b5545 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence SPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml index 6bd83836edede..4beb3af0416de 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 20f77246d3658..2c864776bc552 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - - Michal Simek + - Michal Simek allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml index 83e8fb4a548df..7ea8fb42ce2c0 100644 --- a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml @@ -14,7 +14,7 @@ allOf: - $ref: spi-controller.yaml# maintainers: - - Michal Simek + - Michal Simek # Everything else is described in the common file properties: diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml index bc5e6f2262957..dbba780c9b021 100644 --- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence TTC - Triple Timer Counter maintainers: - - Michal Simek + - Michal Simek properties: compatible: diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml index 8444c56dd6023..dc1ff39d05a0c 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx AXI/PLB softcore and window Watchdog Timer maintainers: - - Shubhrajyoti Datta - - Srinivas Neeli + - Shubhrajyoti Datta + - Srinivas Neeli description: The Timebase watchdog timer(WDT) is a free-running 32 bit counter. -- GitLab From f5c8855de148f8a911842e8b9c81d2d2a5f3d37f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 May 2023 15:40:27 +0200 Subject: [PATCH 568/926] arm64: zynqmp: Convert kv260-revA overlay to ASCII text File was in UTF-8 format but there is no reason for it. Convert it to ASCII/plain text. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9161f4e1d449edd86e642b6769575b8e201fccf0.1684244418.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index bd7628a50b042..bebbe955eec12 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -5,9 +5,9 @@ * (C) Copyright 2020 - 2021, Xilinx, Inc. * * SD level shifter: - * "A" – A01 board un-modified (NXP) - * "Y" – A01 board modified with legacy interposer (Nexperia) - * "Z" – A01 board modified with Diode interposer + * "A" - A01 board un-modified (NXP) + * "Y" - A01 board modified with legacy interposer (Nexperia) + * "Z" - A01 board modified with Diode interposer * * Michal Simek */ -- GitLab From 4e4ddd3d1dee009a26a8a74822d4761287768a95 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 30 May 2023 12:42:41 +0200 Subject: [PATCH 569/926] arm64: zynqmp: Switch to amd.com emails Update my and DPs email address to match current setup. Reviewed-by: Laurent Pinchart Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 24 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts index 88aa06fa78a8c..4c1bd69e7553e 100644 --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts +++ b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2018, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 719ea5d5ae88d..f04716841a0c0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -5,7 +5,7 @@ * (C) Copyright 2017 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index bebbe955eec12..669fe6084f3ff 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -9,7 +9,7 @@ * "Y" - A01 board modified with legacy interposer (Nexperia) * "Z" - A01 board modified with Diode interposer * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 8e66448f35a9d..7886a19139eeb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 464e28bf078a4..c1ab1ab690df4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts index c70966c1f3449..85b0d16772406 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2020 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-sm-k26-revA.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index f1598527e5ecc..48d6a72024065 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 04efa1683eaa9..e80484f9b1379 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index f89ef2afcd9e5..1a7995ee62ce0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 868ca655a2205..869b733a06348 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index 381cc682cef9a..38b0a312171b7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6e0106bf12942..05be71eab722f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index ae2d03d98322c..b1e933b8a2cdb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Siva Durga Prasad - * Michal Simek + * Siva Durga Prasad Paladugu + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 70c48079575dd..544801814bd5d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek * Nathalie Chan King Choy */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts index 6647e97edba36..c8f71a1aec895 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2018, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts index b6798394fcf4b..705369766a550 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2020, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-rev1.0.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index d600eeb5b2b70..230ef94d5dcb1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2015 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index f7d718ff116b6..63419deb5b336 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ #include "zynqmp-zcu102-revA.dts" diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 473fae564906d..d178a4f898c94 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index c8ba9ed157be9..38b11594c0742 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 09773b7200f83..8af0879806cf0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2016 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index e0305dcbb010d..f76687914e309 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -4,7 +4,7 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index 4874e0ad914e5..e615286b8effc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -4,8 +4,8 @@ * * (C) Copyright 2017 - 2021, Xilinx, Inc. * - * Michal Simek - * Siva Durga Prasad Paladugu + * Michal Simek + * Siva Durga Prasad Paladugu */ /dts-v1/; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 850b497d7a812..a961bb6f31ffc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -4,7 +4,7 @@ * * (C) Copyright 2014 - 2021, Xilinx, Inc. * - * Michal Simek + * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as -- GitLab From c720a1f5e6ee8cb39c28435efc0819cec84d6ee2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 22 May 2023 16:59:48 +0200 Subject: [PATCH 570/926] arm64: zynqmp: Describe TI phy as ethernet-phy-id TI DP83867 is using strapping based on MIO pins. Tristate setup can influence PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------ .../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++-------- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------ 6 files changed, 90 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 230ef94d5dcb1..f36353a518633 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -200,13 +201,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index 63419deb5b336..3c28130909bc6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -16,16 +17,20 @@ / { &gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index d178a4f898c94..3fd47725c2c84 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -109,12 +110,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 38b11594c0742..4f6429caecff2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -114,12 +115,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 8af0879806cf0..8c3fa3fe28d5e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -212,12 +213,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index f76687914e309..0d9b6081dff69 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -172,12 +173,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; }; -- GitLab From f8673fd5700257576b23e0f6de71c153bac23978 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 22 May 2023 16:59:49 +0200 Subject: [PATCH 571/926] arm64: zynqmp: Fix usb node drive strength and slew rate As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com --- .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 8 ++++++-- .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 8 ++++++-- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 8 ++++++-- .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 13 ++++++++++--- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 5 ++++- 10 files changed, 54 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 669fe6084f3ff..603839c825991 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) @@ -265,19 +266,22 @@ mux { pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 7886a19139eeb..a91d09e7da4bc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -248,19 +249,22 @@ mux { pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 1a7995ee62ce0..af3331c133ad4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -187,19 +188,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 869b733a06348..6503f4985f8d6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -281,19 +282,22 @@ mux { conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 544801814bd5d..44d1f351bb757 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek * Nathalie Chan King Choy @@ -432,19 +433,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -456,19 +460,22 @@ mux { conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index f36353a518633..a074d8e2b86d2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -783,19 +783,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 3fd47725c2c84..91c9b77f6b1ff 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -410,20 +410,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4f6429caecff2..954044d9899f6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -422,20 +422,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 8c3fa3fe28d5e..ab5e34b436429 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -794,19 +794,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 0d9b6081dff69..f31365a14f732 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -660,19 +660,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; -- GitLab From 1d831cade71883d0578e9f41d19d09b67f8263ac Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Mon, 22 May 2023 16:59:50 +0200 Subject: [PATCH 572/926] arm64: zynqmp: Set qspi tx-buswidth to 4 All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index c1ab1ab690df4..84e18fdce7752 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -124,7 +124,7 @@ spi_flash: flash@0 { /* MT25QU512A */ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 48d6a72024065..04079d1704f1f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -44,7 +44,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index e80484f9b1379..3dec57cf18be0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -45,7 +45,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index af3331c133ad4..d9d1de5f313c1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -355,7 +355,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 05be71eab722f..6636e76545a5d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -173,7 +173,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index a074d8e2b86d2..8767f147cbe33 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -957,7 +957,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 91c9b77f6b1ff..e185709c0d842 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -444,7 +444,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 954044d9899f6..7fceebd1815cf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -456,7 +456,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index ab5e34b436429..27b2416cb6d8b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -964,7 +964,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index f31365a14f732..6224365826d8c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -794,7 +794,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index e615286b8effc..c406017b0348f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -47,7 +47,7 @@ &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; -- GitLab From f1d48a128a2a016cda9049355cd5db35a9644012 Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 22 May 2023 16:59:52 +0200 Subject: [PATCH 573/926] arm64: zynqmp: Add pmu interrupt-affinity Based on dt-binding "This property should present when there is more than a single SPI" that's also case that's why explicitly specify interrupt affinity to avoid incorrect usage. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/dde2e4b5ac6018adb9bfae05bb3800af6b7c0f0e.1684767562.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a961bb6f31ffc..02cfcc7169368 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -155,6 +155,10 @@ pmu { <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci { -- GitLab From 153fc203f68453d9c28e7347420e68fa3665613a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 22 May 2023 16:59:53 +0200 Subject: [PATCH 574/926] arm64: zynqmp: Used fixed-partitions for QSPI in k26 Using fixed partitions is recommended way how to describe QSPI. Also add label for qspi flash memory to be able to reference it in future. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7368dc772d8dc29477a880ac2065e2ecb98cf3f5.1684767562.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 169 +++++++++--------- 1 file changed, 88 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 84e18fdce7752..dfd1a18f5a10b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -127,87 +127,94 @@ spi_flash: flash@0 { /* MT25QU512A */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xC0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xD00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xF00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xF80000 0xD00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1C80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1D00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1E00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ - read-only; - lock; - }; - partition@2280000 { - label = "Secure OS Storage"; - reg = <0x2280000 0x20000>; /* 128KB */ - }; - partition@22A0000 { - label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xC0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xD00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xF00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xF80000 0xD00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1C80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1D00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1E00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { + label = "User"; + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; -- GitLab From a5e0a69dc34b2acf211785e9ad9642c5aaea098b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 May 2023 09:56:57 +0200 Subject: [PATCH 575/926] dt-bindings: xilinx: Remove Rajan, Jolly and Manish Rajan, Jolly and Manish are no longer work for AMD/Xilinx and there is no activity from them to continue to maintain bindings that's why remove them. Acked-by: Conor Dooley Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9b252dd71c82593fa6b137eca2174d9ab6e57f7a.1684828606.git.michal.simek@amd.com --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 -- .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 1 - .../bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 1 - .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 1 - 4 files changed, 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 93ae349cf9e9e..5cbb34d0b61b3 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -8,8 +8,6 @@ title: Xilinx Versal clock controller maintainers: - Michal Simek - - Jolly Shah - - Rajan Vaja description: | The clock controller is a hardware block of Xilinx versal clock tree. It diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index 6b62d5d834769..87ff9ee098f5e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -8,7 +8,6 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - Michal Simek description: | diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 7864a1c994eb0..75143db514119 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -8,7 +8,6 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - Michal Simek description: diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index cdebfa991e066..24ad0614e61b6 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -8,7 +8,6 @@ title: Xilinx ZynqMP Pinctrl maintainers: - Sai Krishna Potthuri - - Rajan Vaja description: | Please refer to pinctrl-bindings.txt in this directory for details of the -- GitLab From 067bf44de11ceae0d2787c86127a39a67b2d60a6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 May 2023 10:00:09 +0200 Subject: [PATCH 576/926] dt-bindings: usb: xilinx: Replace Manish by Piyush Manish no longer works for AMD/Xilinx and there is also no activity from him. That's why proposing Piyush as the best candidate instead. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/504444f5c2f4e725ac39cba1d72032d5a00c7cda.1684828805.git.michal.simek@amd.com --- Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 2 +- Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 098b73134a1b9..bb373eb025a5f 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - - Manish Narani + - Piyush Mehta properties: compatible: diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml index 04c123c7252a1..868dffe314bcb 100644 --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx udc controller maintainers: - - Manish Narani + - Piyush Mehta properties: compatible: -- GitLab From 04afb51c1dce90051487d3c7b70a1b1b246ce29a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 17:10:23 +0200 Subject: [PATCH 577/926] ARM: dts: BCM5301X: Use updated "spi-gpio" binding properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch away from deprecated properties. This fixes: arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-sck: False schema does not allow [[6, 7, 0]] From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-mosi: False schema does not allow [[6, 4, 0]] From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: 'sck-gpios' is a required property From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: Unevaluated properties are not allowed ('gpio-mosi', 'gpio-sck' were unexpected) From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230602151023.8607-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 4 ++-- arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ++-- arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ++-- arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi index e583b9cbf07c0..0846887ba144d 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -16,8 +16,8 @@ / { spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index 43c698a0a7c39..95ef6ca7210b3 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -28,8 +28,8 @@ memory@0 { spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 407319cb5c0dd..a2b7644eaf393 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -28,8 +28,8 @@ memory@0 { spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index f8622ecce6a2b..7655e4ff2d1cc 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -28,8 +28,8 @@ memory@0 { spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 7 0>; - gpio-mosi = <&chipcommon 4 0>; + sck-gpios = <&chipcommon 7 0>; + mosi-gpios = <&chipcommon 4 0>; cs-gpios = <&chipcommon 6 0>; #address-cells = <1>; #size-cells = <0>; -- GitLab From 58e058f73ce3ac58ae744c783547caaa80807996 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 17:36:57 +0200 Subject: [PATCH 578/926] dt-bindings: arm: bcm: Add bindings for Buffalo WZR-1166DHP(2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add two more Northstar devices based on the BCM4708 SoC. Linux already contains DTS files for both. Signed-off-by: Rafał Miłecki Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230602153657.11362-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index cc34025fdc787..5c3ac97e87286 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -25,6 +25,8 @@ properties: - enum: - asus,rt-ac56u - asus,rt-ac68u + - buffalo,wzr-1166dhp + - buffalo,wzr-1166dhp2 - buffalo,wzr-1750dhp - linksys,ea6300-v1 - linksys,ea6500-v2 -- GitLab From c3acdd4901192bc69dc577012663d5abae21661e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 15:34:54 +0200 Subject: [PATCH 579/926] ARM: dts: BCM5301X: Drop invalid #usb-cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Such property simply doesn't exist (is not documented or used anywhere). This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@21000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@22000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@23000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) From schema: Documentation/devicetree/bindings/usb/generic-xhci.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230602133455.7441-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 3f8220a7a54dd..793891f1f2609 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -192,8 +192,6 @@ usb2: usb2@21000 { interrupt-parent = <&gic>; ehci: usb@21000 { - #usb-cells = <0>; - compatible = "generic-ehci"; reg = <0x00021000 0x1000>; interrupts = ; @@ -214,8 +212,6 @@ ehci_port2: port@2 { }; ohci: usb@22000 { - #usb-cells = <0>; - compatible = "generic-ohci"; reg = <0x00022000 0x1000>; interrupts = ; @@ -245,8 +241,6 @@ usb3: usb3@23000 { interrupt-parent = <&gic>; xhci: usb@23000 { - #usb-cells = <0>; - compatible = "generic-xhci"; reg = <0x00023000 0x1000>; interrupts = ; -- GitLab From 676bf7d062c14191c3fc12f1e36e1f3809041483 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 15:34:55 +0200 Subject: [PATCH 580/926] ARM: dts: BCM5301X: Drop invalid properties from Meraki MR32 keys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/boot/dts/bcm53015-meraki-mr26.dtb: keys: '#address-cells', '#size-cells' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/input/gpio-keys.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230602133455.7441-2-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts index 14f58033efeb9..071f2cb97251a 100644 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -39,8 +39,6 @@ led-1 { keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; key-restart { label = "Reset"; -- GitLab From 2378341504de476acd880833a0e5481555b9aa5c Mon Sep 17 00:00:00 2001 From: Mason Huo Date: Tue, 6 Jun 2023 18:56:54 +0800 Subject: [PATCH 581/926] riscv: dts: starfive: Enable axp15060 pmic for cpufreq The VisionFive 2 board has an embedded pmic axp15060, which supports the cpu DVFS through the dcdc2 regulator. This patch enables axp15060 pmic and configs the dcdc2. Signed-off-by: Mason Huo Signed-off-by: Conor Dooley --- .../starfive/jh7110-starfive-visionfive-2.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 2a6d81609284c..9714da5550d70 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -114,6 +114,23 @@ &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; status = "okay"; + + axp15060: pmic@36 { + compatible = "x-powers,axp15060"; + reg = <0x36>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-name = "vdd-cpu"; + }; + }; + }; }; &i2c6 { -- GitLab From e2c510d6d630fe6593a0cf87531913b4b08ebeb1 Mon Sep 17 00:00:00 2001 From: Mason Huo Date: Tue, 6 Jun 2023 18:56:56 +0800 Subject: [PATCH 582/926] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo Signed-off-by: Conor Dooley --- .../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 9714da5550d70..fa0061eb33a75 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -230,3 +230,19 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 03c6cc49fa229..ec2e70011a736 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; -- GitLab From 12382ad05110b569d95d29c637e16bbeb115acca Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Tue, 30 May 2023 12:51:08 +0200 Subject: [PATCH 583/926] dt-bindings: gpio: Remove FSI domain ports on Tegra234 Ports S, T, U and V are in a separate controller that is part of the FSI domain. Remove their definitions from the MAIN controller definitions to get rid of the confusion. This technically breaks ABI compatibility with old device trees. However it doesn't cause issues in practice. The GPIO pins impacted by this are used for non-critical functionality. Fixes: a8b10f3d12cfc ("dt-bindings: gpio: Add Tegra234 support") Signed-off-by: Prathamesh Shete [treding@nvidia.com: rewrite commit message] Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- include/dt-bindings/gpio/tegra234-gpio.h | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/include/dt-bindings/gpio/tegra234-gpio.h b/include/dt-bindings/gpio/tegra234-gpio.h index d7a1f2e298e82..784673c2c7528 100644 --- a/include/dt-bindings/gpio/tegra234-gpio.h +++ b/include/dt-bindings/gpio/tegra234-gpio.h @@ -33,18 +33,14 @@ #define TEGRA234_MAIN_GPIO_PORT_P 14 #define TEGRA234_MAIN_GPIO_PORT_Q 15 #define TEGRA234_MAIN_GPIO_PORT_R 16 -#define TEGRA234_MAIN_GPIO_PORT_S 17 -#define TEGRA234_MAIN_GPIO_PORT_T 18 -#define TEGRA234_MAIN_GPIO_PORT_U 19 -#define TEGRA234_MAIN_GPIO_PORT_V 20 -#define TEGRA234_MAIN_GPIO_PORT_X 21 -#define TEGRA234_MAIN_GPIO_PORT_Y 22 -#define TEGRA234_MAIN_GPIO_PORT_Z 23 -#define TEGRA234_MAIN_GPIO_PORT_AC 24 -#define TEGRA234_MAIN_GPIO_PORT_AD 25 -#define TEGRA234_MAIN_GPIO_PORT_AE 26 -#define TEGRA234_MAIN_GPIO_PORT_AF 27 -#define TEGRA234_MAIN_GPIO_PORT_AG 28 +#define TEGRA234_MAIN_GPIO_PORT_X 17 +#define TEGRA234_MAIN_GPIO_PORT_Y 18 +#define TEGRA234_MAIN_GPIO_PORT_Z 19 +#define TEGRA234_MAIN_GPIO_PORT_AC 20 +#define TEGRA234_MAIN_GPIO_PORT_AD 21 +#define TEGRA234_MAIN_GPIO_PORT_AE 22 +#define TEGRA234_MAIN_GPIO_PORT_AF 23 +#define TEGRA234_MAIN_GPIO_PORT_AG 24 #define TEGRA234_MAIN_GPIO(port, offset) \ ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) -- GitLab From b4032e1726648cb156f45ae756c8730d6d39a5de Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 16 May 2023 11:58:48 +0200 Subject: [PATCH 584/926] dt-bindings: tegra: Document Jetson Orin Nano The Jetson Orin Nano is the little sibling of the Jetson Orin NX. Document the corresponding compatible strings for these devices. Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 6970ca1b8bd86..7938cc0929b16 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -181,5 +181,9 @@ properties: - const: nvidia,p3768-0000+p3767-0000 - const: nvidia,p3767-0000 - const: nvidia,tegra234 + - description: Jetson Orin Nano + items: + - const: nvidia,p3767-0005 + - const: nvidia,tegra234 additionalProperties: true -- GitLab From 5f027147e4796e9fc11083b2ad50a91c1ac36ede Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 16 May 2023 11:58:49 +0200 Subject: [PATCH 585/926] dt-bindings: tegra: Document Jetson Orin Nano Developer Kit The Jetson Orin Nano Developer Kit pairs the Jetson Orin Nano devkit module with the P3768 carrier board. Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 7938cc0929b16..fcf956406168e 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -185,5 +185,10 @@ properties: items: - const: nvidia,p3767-0005 - const: nvidia,tegra234 + - description: Jetson Orin Nano Developer Kit + items: + - const: nvidia,p3768-0000+p3767-0005 + - const: nvidia,p3767-0005 + - const: nvidia,tegra234 additionalProperties: true -- GitLab From 4d92116266485bc05a7d8cde41fba8845074d152 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 16 May 2023 11:58:50 +0200 Subject: [PATCH 586/926] arm64: tegra: Support Jetson Orin Nano Developer Kit The NVIDIA Jetson Orin Nano Developer Kit is the combination of the NVIDIA Jetson Orin Nano (P3767, SKU 5) module and the P3768 carrier board. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 2 ++ .../arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi | 14 ++++++++++++++ .../dts/nvidia/tegra234-p3768-0000+p3767-0005.dts | 13 +++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 2ea0058979d3b..c38c809fe5771 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -11,6 +11,7 @@ DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@ DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@ +DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb @@ -28,3 +29,4 @@ dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi new file mode 100644 index 0000000000000..232fa95ef4ae5 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234-p3767.dtsi" + +/ { + compatible = "nvidia,p3767-0005", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin Nano"; + + bus@0 { + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin Nano HDA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts new file mode 100644 index 0000000000000..ba66c1845f759 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include + +#include "tegra234-p3767-0005.dtsi" +#include "tegra234-p3768-0000.dtsi" + +/ { + compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin Nano Developer Kit"; +}; -- GitLab From 282fde002760d3a006128c1d70b329e68a6ef844 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 5 Jun 2023 17:42:30 +0200 Subject: [PATCH 587/926] arm64: tegra: Add Tegra234 pin controllers Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra234 family of SoCs. Signed-off-by: Prathamesh Shete Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 97ed3e0d892ac..f5146ce7363d2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -108,6 +108,12 @@ gpio: gpio@2200000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 164>; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra234-pinmux"; + reg = <0x0 0x2430000 0x0 0x19100>; }; gpcdma: dma-controller@2600000 { @@ -1749,6 +1755,12 @@ gpio_aon: gpio@c2f0000 { interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux_aon 0 0 32>; + }; + + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra234-pinmux-aon"; + reg = <0x0 0xc300000 0x0 0x4000>; }; pwm4: pwm@c340000 { -- GitLab From 620405856d591ef95b01ee3e275af3a636c05010 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 30 May 2023 15:02:31 +0100 Subject: [PATCH 588/926] arm64: tegra: Enable USB device for Jetson AGX Orin Enable USB device support for the Jetson AGX Orin platform and update the mode for the usb2-0 port to be on-the-go. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index caa9e952a149c..ac64dac287def 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2096,7 +2096,8 @@ usb3-2 { ports { usb2-0 { - mode = "host"; + mode = "otg"; + usb-role-switch; status = "okay"; port { hs_typec_p1: endpoint { @@ -2152,6 +2153,14 @@ usb3-2 { }; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-0"; + }; + usb@3610000 { status = "okay"; -- GitLab From 86d24f98b75d3a58503554e8d1dd277ae7386966 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 30 May 2023 15:02:32 +0100 Subject: [PATCH 589/926] arm64: tegra: Update USB phy-name for Jetson Orin NX Running 'make dtbs_check' reports the following warning for the Jetson Orin NX platform ... arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dtb: usb@3550000: phy-names:1: 'usb3-0' was expected Fix this by updating the phy-names:1 to be 'usb3-0' as expected. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi index aee21428e1a52..bbd68ef93d979 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi @@ -119,7 +119,7 @@ usb@3550000 { phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; - phy-names = "usb2-0", "usb3-1"; + phy-names = "usb2-0", "usb3-0"; }; usb@3610000 { -- GitLab From ec084cbddbbe3a778ee06ccc0c59cee23b5cbaf4 Mon Sep 17 00:00:00 2001 From: Shreeya Patel Date: Sun, 4 Jun 2023 00:23:39 +0530 Subject: [PATCH 590/926] arm64: dts: rockchip: Add DT node for ADC support in RK3588 Add DT node for ADC support in RK3588. Signed-off-by: Shreeya Patel Link: https://lore.kernel.org/r/20230603185340.13838-8-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index afcd4e806cf72..d3f98788bb1c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1784,6 +1784,18 @@ tsadc: tsadc@fec00000 { status = "disabled"; }; + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; -- GitLab From 47ecb3905715a73b336103cc8d225877ab50143e Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 31 May 2023 11:12:16 -0500 Subject: [PATCH 591/926] arm64: dts: rockchip: add default pinctrl for rk3588 emmc Add a default pinctrl definition for the rk3588 emmc. Signed-off-by: Chris Morgan Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230531161220.280744-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index d3f98788bb1c6..74a06231a17e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1187,6 +1187,9 @@ sdhci: mmc@fe2e0000 { <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; -- GitLab From 725c47d78ddefd04a94391fafa5f99414c7f88db Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 31 May 2023 11:12:17 -0500 Subject: [PATCH 592/926] arm64: dts: rockchip: Add sdio node to rk3588 Add SDIO node for rk3588/rk3588s. Signed-off-by: Chris Morgan Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230531161220.280744-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 74a06231a17e9..3229c2a80bd86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1176,6 +1176,21 @@ sdmmc: mmc@fe2c0000 { status = "disabled"; }; + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; -- GitLab From e78a863151ede8725fcb360c627e90f76fa584f3 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 31 May 2023 11:12:18 -0500 Subject: [PATCH 593/926] dt-bindings: vendor-prefixes: add Indiedroid Indiedroid is a sub-brand of Ameridroid for their line of single board computers. https://indiedroid.us/ Signed-off-by: Chris Morgan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230531161220.280744-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c3d426509e7e8..b209fe6e7a5cf 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -617,6 +617,8 @@ patternProperties: description: Integrated Micro-Electronics Inc. "^incircuit,.*": description: In-Circuit GmbH + "^indiedroid,.*": + description: Indiedroid "^inet-tek,.*": description: Shenzhen iNet Mobile Internet Technology Co., Ltd "^infineon,.*": -- GitLab From 81154abafbe88ca7a723e34d67748a6a514ac882 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 31 May 2023 11:12:19 -0500 Subject: [PATCH 594/926] dt-bindings: arm: rockchip: Add Indiedroid Nova Add Indiedroid Nova, an rk3588s based single board computer. Signed-off-by: Chris Morgan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230531161220.280744-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 03fa51cf2028b..ecdb72a519cbb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -546,6 +546,11 @@ properties: - const: hugsun,x99 - const: rockchip,rk3399 + - description: Indiedroid Nova SBC + items: + - const: indiedroid,nova + - const: rockchip,rk3588s + - description: Khadas Edge series boards items: - enum: -- GitLab From 3900160e164bcba23a111a3ba80f06aff7764c34 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 31 May 2023 11:12:20 -0500 Subject: [PATCH 595/926] arm64: dts: rockchip: Add Indiedroid Nova board The Indiedroid Nova is an SBC from a sub-brand of Ameridroid that includes the following hardware: - A 40-pin GPIO header - 2 USB-A 3.0 ports - 2 USB-A 2.0 ports - A USB-C 2.0 OTG port (used for USB power delivery) - A USB-C 3.0 port that can do display port output. - A Micro HDMI 2.1 port. - A 1GB ethernet port. - An RT8821CS based WiFi/Bluetooth module. - A user replaceable eMMC module. - An SDMMC card slot. - A MIPI DSI connector. - A MIPI CSI connector. - A 3.5mm TRRS audio jack with microphone input. - An 2 pin socket for an RTC battery. - A 4 pin socket for a debug port. - A power button (connected to PMIC), a reset button (connected to SoC reset), a boot button, and a recovery button (both connected to the ADC). - 4GB, 8GB, or 16GB of system RAM. This initial devicetree includes support for the WiFi, bluetooth, analog audio out/in, SDMMC, eMMC, RTC, UART debugging, and has the regulator values from the schematics. ADC, graphics output, GPU, USB, and wired ethernet are still pending additional upstream changes. Analog audio will require changes to handle a difference between the requested clock frequency of 12288000 and the actual clock freqency of 12287999 before it will work properly. This will be done in a subsequent patch series. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20230531161220.280744-6-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588s-indiedroid-nova.dts | 763 ++++++++++++++++++ 2 files changed, 764 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 41a686cb4b6ac..b7fb908eb92db 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -99,5 +99,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts new file mode 100644 index 0000000000000..4d9ed2a027363 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -0,0 +1,763 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "Indiedroid Nova"; + compatible = "indiedroid,nova", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&rtc_hym8563>; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,es8388-codec"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + routing = "LINPUT2", "Mic Jack", + "Headphones", "LOUT1", + "Headphones", "ROUT1"; + dais = <&i2s0_8ch_p0>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&typec5v_pwren>; + pinctrl-names = "default"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + /* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */ + vcc_3v3_s0: vcc-3v3-s0-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usbdcin"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +/* + * Add labels for each GPIO pin exposed on the 40 pin header. Note that + * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by + * label). + */ +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 D0-D7 */ + "HEADER_12_1v8", "", "", "HEADER_24_1v8", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27_3v3", "HEADER_28_3v3", "", "", + "HEADER_29_1v8", "", "HEADER_7_1v8", "", + /* GPIO1 B0-B7 */ + "", "HEADER_31_1v8", "HEADER_33_1v8", "", + "HEADER_11_1v8", "HEADER_13_1v8", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_5_3v3", "HEADER_3_3v3"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "HEADER_16_1v8", "HEADER_18_1v8", "", "", + "", "", "", "HEADER_19_1v8", + /* GPIO3 C0-C7 */ + "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8", + "HEADER_15_1v8", "HEADER_22_1v8", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "", "", "HEADER_37_3v3", "HEADER_32_3v3", + "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3", + /* GPIO4 B0-B7 */ + "", "", "", "HEADER_40_3v3", + "HEADER_8_3v3", "HEADER_10_3v3", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + }; + }; + + rtc_hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&hym8563_int>; + pinctrl-names = "default"; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s3>; + clock-names = "mclk"; + clocks = <&cru I2S0_8CH_MCLKOUT>; + DVDD-supply = <&vcc_1v8_s3>; + HPVDD-supply = <&vcc_3v3_s3>; + PVDD-supply = <&vcc_1v8_s3>; + #sound-dai-cells = <0>; + + port { + es8388_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8388_p0_0>; + }; + }; +}; + +&pinctrl { + bluetooth-pins { + bt_reset: bt-reset { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hym8563 { + + hym8563_int: hym8563-int { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* HS400 modes seemed to cause io errors. */ +&sdhci { + bus-width = <8>; + no-mmc-hs400; + no-sd; + no-sdio; + non-removable; + max-frequency = <200000000>; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>; + pinctrl-names = "default"; + #size-cells = <0>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <675000>; + regulator-name = "vdd_logic_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_vdenc_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <600000>; + regulator-min-microvolt = <600000>; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3_pldo6: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3_pldo6"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Schematics show not in use */ + nldo-reg5 { + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* DMA seems to interfere with bluetooth device normal operation. */ +&uart9 { + pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; + pinctrl-names = "default"; + /delete-property/ dma-names; + /delete-property/ dmas; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", + "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>; + pinctrl-names = "default"; + }; +}; -- GitLab From 28ee08cef4f838c343013330a3cd12674c4dd113 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 30 May 2023 21:11:40 +0300 Subject: [PATCH 596/926] arm64: dts: rockchip: Assign ES8316 MCLK rate on rk3588-rock-5b The I2S0_8CH_MCLKOUT clock rate on Rock 5B board defaults to 12 MHz and it is used to provide the master clock (MCLK) for the ES8316 audio codec. On sound card initialization, this limits the allowed sample rates according to the MCLK/LRCK ratios supported by the codec, which results in the following non-standard rates: 15625, 30000, 31250, 46875. Hence, the very first access of the sound card fails: Broken configuration for playback: no configurations available: Invalid argument Setting of hwparams failed: Invalid argument However, all subsequent attempts will succeed, as the audio graph card will request a correct clock frequency, based on the stream sample rate and the multiplication factor. Assign MCLK to 12.288 MHz, which allows the codec to advertise most of the standard sample rates. Fixes: 55529fe3f32d ("arm64: dts: rockchip: Add rk3588-rock-5b analog audio") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230530181140.483936-4-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 3e4aee8f70c1b..30cdd366813fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -133,6 +133,8 @@ es8316: audio-codec@11 { reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; #sound-dai-cells = <0>; port { -- GitLab From db242e8240b5dc8bd3709dceb194bd49cd3aac2e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 29 May 2023 19:05:31 +0200 Subject: [PATCH 597/926] arm64: dts: rockchip: add PMIC to rock-5b This adds PMIC support for the Radxa ROCK 5B Signed-off-by: shengfei Xu Co-developed-by: shengfei Xu Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230529170532.59804-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 350 ++++++++++++++++++ 1 file changed, 350 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 30cdd366813fb..e8607bc91311c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -51,6 +51,16 @@ vcc5v0_sys: vcc5v0-sys-regulator { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu_b0 { @@ -69,6 +79,22 @@ &cpu_b3 { cpu-supply = <&vdd_cpu_big1_s0>; }; +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -192,6 +218,330 @@ &sdhci { status = "okay"; }; +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; -- GitLab From 2a6d4af5f157b1540e7a49f7fdbbf517b0d0d5b7 Mon Sep 17 00:00:00 2001 From: Lucas Tanure Date: Mon, 29 May 2023 19:05:32 +0200 Subject: [PATCH 598/926] arm64: dts: rockchip: Add SD card support to rock-5b Add sdmmc support for Rock Pi 5B board. Signed-off-by: Lucas Tanure Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230529170532.59804-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index e8607bc91311c..154b1089db770 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -218,6 +218,20 @@ &sdhci { status = "okay"; }; +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; -- GitLab From 1d5682ccc7d6088179b6cfd50a3e3bb6d2b0527e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 5 Jun 2023 08:10:49 +0200 Subject: [PATCH 599/926] ARM: dts: BCM5301X: Relicense Christian's code to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move code added by Christian to the bcm-ns.dtsi which uses dual licensing. That syncs more Northstar code to be based on the same licensing schema. Cc: Christian Lamparter Signed-off-by: Rafał Miłecki Acked-by: Christian Lamparter Link: https://lore.kernel.org/r/20230605061049.16136-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 793891f1f2609..d9455b33adeea 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -182,6 +182,10 @@ pcie1: pcie@13000 { reg = <0x00013000 0x1000>; }; + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + usb2: usb2@21000 { reg = <0x00021000 0x1000>; @@ -274,6 +278,14 @@ gmac3: ethernet@27000 { }; }; + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + mdio: mdio@18003000 { compatible = "brcm,iproc-mdio"; reg = <0x18003000 0x8>; @@ -299,6 +311,15 @@ ports { }; }; + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + dmu-bus@1800c000 { compatible = "simple-bus"; ranges = <0 0x1800c000 0x1000>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 0f40812eb5a40..600a1b54f2ae5 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -69,20 +69,6 @@ periph_clk: periph_clk { }; }; - axi@18000000 { - pcie2: pcie@14000 { - reg = <0x00014000 0x1000>; - }; - }; - - pwm: pwm@18002000 { - compatible = "brcm,iproc-pwm"; - reg = <0x18002000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - mdio-mux@18003000 { compatible = "mdio-mux-mmioreg", "mdio-mux"; mdio-parent-bus = <&mdio>; @@ -110,15 +96,6 @@ usb3_dmp: syscon@18105000 { reg = <0x18105000 0x1000>; }; - uart2: serial@18008000 { - compatible = "ns16550a"; - reg = <0x18008000 0x20>; - clocks = <&iprocslow>; - interrupts = ; - reg-shift = <2>; - status = "disabled"; - }; - i2c0: i2c@18009000 { compatible = "brcm,iproc-i2c"; reg = <0x18009000 0x50>; -- GitLab From cf39ff15cc01adea0ec46d1571d5ae849bb02d43 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 25 Apr 2023 17:17:08 -0500 Subject: [PATCH 600/926] arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uart wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by: Nishanth Menon [bb@ti.com: updated pinmux and commit subject] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230425221708.549675-1-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 40 +++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f6a67f072dca6..65caa5611d6d5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -17,7 +17,9 @@ / { model = "Texas Instruments AM62A7 SK"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; + serial3 = &main_uart1; mmc1 = &sdhci1; }; @@ -114,11 +116,38 @@ led-0 { }; }; +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; +}; + &main_pmx0 { main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ + AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ + AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ + AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ >; }; @@ -254,6 +283,13 @@ &main_uart0 { pinctrl-0 = <&main_uart0_pins_default>; }; +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "reserved"; +}; + &usbss1 { status = "okay"; }; -- GitLab From 3d011933000ed9054c649952d83162d24f020a93 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 19 Apr 2023 09:30:06 +0530 Subject: [PATCH 601/926] arm64: dts: ti: k3-j7200: Fix physical address of pin wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac445e9 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by: Keerthy Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20230419040007.3022780-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j7200-common-proc-board.dts | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 5506341aae21b..0cc0e1dc40c54 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -82,25 +82,25 @@ vdd_sd_dv: gpio-regulator-TLV71033 { &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; }; -- GitLab From 2f932d4151599bc647607ae841cf57273279168c Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 19 Apr 2023 09:30:07 +0530 Subject: [PATCH 602/926] arm64: dts: ti: k3-j7200-som: Enable I2C This patch enables wkup_i2c0 node in board dts file along with pin mux and speed. Also enables underneath eeprom CAV24C256WE. J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf J7200 User Guide (Section 4.3, Table 4-2) : https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index fa44ed4c17d50..269424154771a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -118,6 +118,15 @@ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -214,6 +223,18 @@ exp_som: gpio@21 { }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- GitLab From 709f6754fa357d82f497dac9bc5c5a1538713f97 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 23 May 2023 10:50:34 +0300 Subject: [PATCH 603/926] ARM: dts: hisilicon: Unify pinctrl-single pin group nodes We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it and drop unnecessary ranges property. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620-hi4511.dts | 130 ++++++++++++++-------------- arch/arm/boot/dts/hi3620.dtsi | 6 +- 2 files changed, 67 insertions(+), 69 deletions(-) diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index d7f5daecc9dc8..f1c816a1d7cf7 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -66,119 +66,119 @@ pmx0: pinmux@803000 { pinctrl-names = "default"; pinctrl-0 = <&board_pmx_pins>; - board_pmx_pins: board_pmx_pins { + board_pmx_pins: board-pins { pinctrl-single,pins = < 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x0f0 0x0 0x0f4 0x0 /* UART0_RX & UART0_TX */ >; }; - uart0_pmx_idle: uart0_pmx_idle { + uart0_pmx_idle: uart0-idle-pins { pinctrl-single,pins = < /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ 0x0f4 0x1 /* UART0_RX & UART0_TX */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ >; }; - uart1_pmx_idle: uart1_pmx_idle { + uart1_pmx_idle: uart1-idle-pins { pinctrl-single,pins = < 0x0f8 0x1 /* GPIO (IOMG61) */ 0x0fc 0x1 /* GPIO (IOMG62) */ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x104 0x2 /* UART2_RXD (IOMG96) */ 0x108 0x2 /* UART2_TXD (IOMG64) */ >; }; - uart2_pmx_idle: uart2_pmx_idle { + uart2_pmx_idle: uart2-idle-pins { pinctrl-single,pins = < 0x104 0x1 /* GPIO (IOMG96) */ 0x108 0x1 /* GPIO (IOMG64) */ >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ >; }; - uart3_pmx_idle: uart3_pmx_idle { + uart3_pmx_idle: uart3-idle-pins { pinctrl-single,pins = < 0x160 0x1 /* GPIO (IOMG85) */ 0x164 0x1 /* GPIO (IOMG86) */ >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ 0x16c 0x0 /* UART4_RXD (IOMG88) */ 0x170 0x0 /* UART4_TXD (IOMG93) */ >; }; - uart4_pmx_idle: uart4_pmx_idle { + uart4_pmx_idle: uart4-idle-pins { pinctrl-single,pins = < 0x168 0x1 /* GPIO (IOMG87) */ 0x16c 0x1 /* GPIO (IOMG88) */ 0x170 0x1 /* GPIO (IOMG93) */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ >; }; - i2c0_pmx_idle: i2c0_pmx_idle { + i2c0_pmx_idle: i2c0-idle-pins { pinctrl-single,pins = < 0x0b4 0x1 /* GPIO (IOMG45) */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ >; }; - i2c1_pmx_idle: i2c1_pmx_idle { + i2c1_pmx_idle: i2c1-idle-pins { pinctrl-single,pins = < 0x0b8 0x1 /* GPIO (IOMG46) */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0x068 0x0 /* I2C2_SCL (IOMG26) */ 0x06c 0x0 /* I2C2_SDA (IOMG27) */ >; }; - i2c2_pmx_idle: i2c2_pmx_idle { + i2c2_pmx_idle: i2c2-idle-pins { pinctrl-single,pins = < 0x068 0x1 /* GPIO (IOMG26) */ 0x06c 0x1 /* GPIO (IOMG27) */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x050 0x2 /* I2C3_SCL (IOMG20) */ 0x054 0x2 /* I2C3_SDA (IOMG21) */ >; }; - i2c3_pmx_idle: i2c3_pmx_idle { + i2c3_pmx_idle: i2c3-idle-pins { pinctrl-single,pins = < 0x050 0x1 /* GPIO (IOMG20) */ 0x054 0x1 /* GPIO (IOMG21) */ >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ @@ -187,7 +187,7 @@ spi0_pmx_func: spi0_pmx_func { 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ >; }; - spi0_pmx_idle: spi0_pmx_idle { + spi0_pmx_idle: spi0-idle-pins { pinctrl-single,pins = < 0x0d4 0x1 /* GPIO (IOMG53) */ 0x0d8 0x1 /* GPIO (IOMG54) */ @@ -196,21 +196,21 @@ spi0_pmx_idle: spi0_pmx_idle { 0x0e4 0x1 /* GPIO (IOMG57) */ >; }; - spi1_pmx_func: spi1_pmx_func { + spi1_pmx_func: spi1-pins { pinctrl-single,pins = < 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ 0x0e8 0x0 /* SPI1_DO (IOMG58) */ 0x0ec 0x0 /* SPI1_CS (IOMG95) */ >; }; - spi1_pmx_idle: spi1_pmx_idle { + spi1_pmx_idle: spi1-idle-pins { pinctrl-single,pins = < 0x184 0x1 /* GPIO (IOMG98) */ 0x0e8 0x1 /* GPIO (IOMG58) */ 0x0ec 0x1 /* GPIO (IOMG95) */ >; }; - kpc_pmx_func: kpc_pmx_func { + kpc_pmx_func: kpc-pins { pinctrl-single,pins = < 0x12c 0x0 /* KEY_IN0 (IOMG73) */ 0x130 0x0 /* KEY_IN1 (IOMG74) */ @@ -220,7 +220,7 @@ kpc_pmx_func: kpc_pmx_func { 0x114 0x0 /* KEY_OUT2 (IOMG67) */ >; }; - kpc_pmx_idle: kpc_pmx_idle { + kpc_pmx_idle: kpc-idle-pins { pinctrl-single,pins = < 0x12c 0x1 /* GPIO (IOMG73) */ 0x130 0x1 /* GPIO (IOMG74) */ @@ -230,13 +230,13 @@ kpc_pmx_idle: kpc_pmx_idle { 0x114 0x1 /* GPIO (IOMG67) */ >; }; - gpio_key_func: gpio_key_func { + gpio_key_func: gpio-key-pins { pinctrl-single,pins = < 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ >; }; - emmc_pmx_func: emmc_pmx_func { + emmc_pmx_func: emmc-pins { pinctrl-single,pins = < 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ 0x018 0x0 /* NAND_CS3_N (IOMG6) */ @@ -245,7 +245,7 @@ emmc_pmx_func: emmc_pmx_func { 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ >; }; - emmc_pmx_idle: emmc_pmx_idle { + emmc_pmx_idle: emmc-idle-pins { pinctrl-single,pins = < 0x030 0x0 /* GPIO (IOMG12) */ 0x018 0x1 /* GPIO (IOMG6) */ @@ -254,19 +254,19 @@ emmc_pmx_idle: emmc_pmx_idle { 0x02c 0x1 /* GPIO (IOMG10) */ >; }; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ >; }; - sd_pmx_idle: sd_pmx_idle { + sd_pmx_idle: sd-idle-pins { pinctrl-single,pins = < 0x0bc 0x1 /* GPIO (IOMG47) */ 0x0c0 0x1 /* GPIO (IOMG48) */ >; }; - nand_pmx_func: nand_pmx_func { + nand_pmx_func: nand-pins { pinctrl-single,pins = < 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ 0x010 0x0 /* NAND_CS1_N (IOMG4) */ @@ -279,7 +279,7 @@ nand_pmx_func: nand_pmx_func { 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ >; }; - nand_pmx_idle: nand_pmx_idle { + nand_pmx_idle: nand-idle-pins { pinctrl-single,pins = < 0x00c 0x1 /* GPIO (IOMG3) */ 0x010 0x1 /* GPIO (IOMG4) */ @@ -292,17 +292,17 @@ nand_pmx_idle: nand_pmx_idle { 0x02c 0x1 /* GPIO (IOMG10) */ >; }; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ >; }; - sdio_pmx_idle: sdio_pmx_idle { + sdio_pmx_idle: sdio-idle-pins { pinctrl-single,pins = < 0x0c4 0x1 /* GPIO (IOMG49) */ >; }; - audio_out_pmx_func: audio_out_pmx_func { + audio_out_pmx_func: audio-out-pins { pinctrl-single,pins = < 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ >; @@ -314,7 +314,7 @@ pmx1: pinmux@803800 { pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins &board_np_pins &board_ps_pins &kpc_cfg_func &audio_out_cfg_func>; - board_pu_pins: board_pu_pins { + board_pu_pins: board-pu-pins { pinctrl-single,pins = < 0x014 0 /* GPIO_158 (IOCFG2) */ 0x018 0 /* GPIO_159 (IOCFG3) */ @@ -324,7 +324,7 @@ board_pu_pins: board_pu_pins { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <1 1 0 1>; }; - board_pd_pins: board_pd_pins { + board_pd_pins: board-pd-pins { pinctrl-single,pins = < 0x038 0 /* eFUSE_DOUT (IOCFG11) */ 0x150 0 /* ISP_GPIO8 (IOCFG93) */ @@ -333,7 +333,7 @@ board_pd_pins: board_pd_pins { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - board_pd_ps_pins: board_pd_ps_pins { + board_pd_ps_pins: board-pd-ps-pins { pinctrl-single,pins = < 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ @@ -342,21 +342,21 @@ board_pd_ps_pins: board_pd_ps_pins { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - board_np_pins: board_np_pins { + board_np_pins: board-np-pins { pinctrl-single,pins = < 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ >; pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - board_ps_pins: board_ps_pins { + board_ps_pins: board-ps-pins { pinctrl-single,pins = < 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ >; pinctrl-single,drive-strength = <0x30 0xf0>; }; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x208 0 /* UART0_RXD (IOCFG138) */ 0x20c 0 /* UART0_TXD (IOCFG139) */ @@ -364,7 +364,7 @@ uart0_cfg_func: uart0_cfg_func { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart0_cfg_idle: uart0_cfg_idle { + uart0_cfg_idle: uart0-cfg-idle-pins { pinctrl-single,pins = < 0x208 0 /* UART0_RXD (IOCFG138) */ 0x20c 0 /* UART0_TXD (IOCFG139) */ @@ -372,7 +372,7 @@ uart0_cfg_idle: uart0_cfg_idle { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart1_cfg_func: uart1_cfg_func { + uart1_cfg_func: uart1-cfg-pins { pinctrl-single,pins = < 0x210 0 /* UART1_CTS (IOCFG140) */ 0x214 0 /* UART1_RTS (IOCFG141) */ @@ -382,7 +382,7 @@ uart1_cfg_func: uart1_cfg_func { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart1_cfg_idle: uart1_cfg_idle { + uart1_cfg_idle: uart1-cfg-idle-pins { pinctrl-single,pins = < 0x210 0 /* UART1_CTS (IOCFG140) */ 0x214 0 /* UART1_RTS (IOCFG141) */ @@ -392,7 +392,7 @@ uart1_cfg_idle: uart1_cfg_idle { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x220 0 /* UART2_CTS (IOCFG144) */ 0x224 0 /* UART2_RTS (IOCFG145) */ @@ -402,7 +402,7 @@ uart2_cfg_func: uart2_cfg_func { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart2_cfg_idle: uart2_cfg_idle { + uart2_cfg_idle: uart2-cfg-idle-pins { pinctrl-single,pins = < 0x220 0 /* GPIO (IOCFG144) */ 0x224 0 /* GPIO (IOCFG145) */ @@ -412,7 +412,7 @@ uart2_cfg_idle: uart2_cfg_idle { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x294 0 /* UART3_CTS (IOCFG173) */ 0x298 0 /* UART3_RTS (IOCFG174) */ @@ -422,7 +422,7 @@ uart3_cfg_func: uart3_cfg_func { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart3_cfg_idle: uart3_cfg_idle { + uart3_cfg_idle: uart3-cfg-idle-pins { pinctrl-single,pins = < 0x294 0 /* UART3_CTS (IOCFG173) */ 0x298 0 /* UART3_RTS (IOCFG174) */ @@ -432,7 +432,7 @@ uart3_cfg_idle: uart3_cfg_idle { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x2a4 0 /* UART4_CTS (IOCFG177) */ 0x2a8 0 /* UART4_RTS (IOCFG178) */ @@ -442,7 +442,7 @@ uart4_cfg_func: uart4_cfg_func { pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x17c 0 /* I2C0_SCL (IOCFG103) */ 0x180 0 /* I2C0_SDA (IOCFG104) */ @@ -451,7 +451,7 @@ i2c0_cfg_func: i2c0_cfg_func { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x184 0 /* I2C1_SCL (IOCFG105) */ 0x188 0 /* I2C1_SDA (IOCFG106) */ @@ -460,7 +460,7 @@ i2c1_cfg_func: i2c1_cfg_func { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0x118 0 /* I2C2_SCL (IOCFG79) */ 0x11c 0 /* I2C2_SDA (IOCFG80) */ @@ -469,7 +469,7 @@ i2c2_cfg_func: i2c2_cfg_func { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x100 0 /* I2C3_SCL (IOCFG73) */ 0x104 0 /* I2C3_SDA (IOCFG74) */ @@ -478,7 +478,7 @@ i2c3_cfg_func: i2c3_cfg_func { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi0_cfg_func1: spi0_cfg_func1 { + spi0_cfg_func1: spi0-cfg-func1-pins { pinctrl-single,pins = < 0x1d4 0 /* SPI0_CLK (IOCFG125) */ 0x1d8 0 /* SPI0_DI (IOCFG126) */ @@ -488,7 +488,7 @@ spi0_cfg_func1: spi0_cfg_func1 { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi0_cfg_func2: spi0_cfg_func2 { + spi0_cfg_func2: spi0-cfg-func2-pins { pinctrl-single,pins = < 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ @@ -499,7 +499,7 @@ spi0_cfg_func2: spi0_cfg_func2 { pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi1_cfg_func1: spi1_cfg_func1 { + spi1_cfg_func1: spi1-cfg-func1-pins { pinctrl-single,pins = < 0x1f0 0 /* SPI1_CLK (IOCFG132) */ 0x1f4 0 /* SPI1_DI (IOCFG133) */ @@ -509,7 +509,7 @@ spi1_cfg_func1: spi1_cfg_func1 { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - spi1_cfg_func2: spi1_cfg_func2 { + spi1_cfg_func2: spi1-cfg-func2-pins { pinctrl-single,pins = < 0x1fc 0 /* SPI1_CS (IOCFG135) */ >; @@ -517,7 +517,7 @@ spi1_cfg_func2: spi1_cfg_func2 { pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - kpc_cfg_func: kpc_cfg_func { + kpc_cfg_func: kpc-cfg-pins { pinctrl-single,pins = < 0x250 0 /* KEY_IN0 (IOCFG156) */ 0x254 0 /* KEY_IN1 (IOCFG157) */ @@ -529,7 +529,7 @@ kpc_cfg_func: kpc_cfg_func { pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; }; - emmc_cfg_func: emmc_cfg_func { + emmc_cfg_func: emmc-cfg-pins { pinctrl-single,pins = < 0x0ac 0 /* eMMC_CMD (IOCFG40) */ 0x0b0 0 /* eMMC_CLK (IOCFG41) */ @@ -549,7 +549,7 @@ emmc_cfg_func: emmc_cfg_func { pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sd_cfg_func1: sd_cfg_func1 { + sd_cfg_func1: sd-cfg-func1-pins { pinctrl-single,pins = < 0x18c 0 /* SD_CLK (IOCFG107) */ 0x190 0 /* SD_CMD (IOCFG108) */ @@ -558,7 +558,7 @@ sd_cfg_func1: sd_cfg_func1 { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sd_cfg_func2: sd_cfg_func2 { + sd_cfg_func2: sd-cfg-func2-pins { pinctrl-single,pins = < 0x194 0 /* SD_DATA0 (IOCFG109) */ 0x198 0 /* SD_DATA1 (IOCFG110) */ @@ -569,7 +569,7 @@ sd_cfg_func2: sd_cfg_func2 { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x70 0xf0>; }; - nand_cfg_func1: nand_cfg_func1 { + nand_cfg_func1: nand-cfg-func1-pins { pinctrl-single,pins = < 0x03c 0 /* NAND_ALE (IOCFG12) */ 0x040 0 /* NAND_CLE (IOCFG13) */ @@ -594,7 +594,7 @@ nand_cfg_func1: nand_cfg_func1 { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - nand_cfg_func2: nand_cfg_func2 { + nand_cfg_func2: nand-cfg-func2-pins { pinctrl-single,pins = < 0x044 0 /* NAND_RE_N (IOCFG14) */ 0x048 0 /* NAND_WE_N (IOCFG15) */ @@ -611,7 +611,7 @@ nand_cfg_func2: nand_cfg_func2 { pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x1a4 0 /* SDIO0_CLK (IOCG113) */ 0x1a8 0 /* SDIO0_CMD (IOCG114) */ @@ -624,7 +624,7 @@ sdio_cfg_func: sdio_cfg_func { pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; - audio_out_cfg_func: audio_out_cfg_func { + audio_out_cfg_func: audio-out-cfg-pins { pinctrl-single,pins = < 0x200 0 /* GPIO (IOCFG136) */ 0x204 0 /* GPIO (IOCFG137) */ diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index cf48ec14af434..a254ec0092960 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -545,10 +545,9 @@ pmx0: pinmux@803000 { compatible = "pinctrl-single"; reg = <0x803000 0x188>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; #gpio-range-cells = <3>; - ranges; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <7>; @@ -567,9 +566,8 @@ pmx1: pinmux@803800 { compatible = "pinconf-single"; reg = <0x803800 0x2dc>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; - ranges; pinctrl-single,register-width = <32>; }; -- GitLab From 35e6bcd138bc7ae85b193186207371d77749afcf Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 23 May 2023 09:55:18 +0300 Subject: [PATCH 604/926] arm64: dts: hisilicon: Unify pinctrl-single pin group nodes We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 +- .../boot/dts/hisilicon/hikey-pinctrl.dtsi | 134 +++++++++--------- .../boot/dts/hisilicon/hikey960-pinctrl.dtsi | 124 ++++++++-------- .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 118 +++++++-------- 4 files changed, 191 insertions(+), 191 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f6d3202b0d1ad..663866922781b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -407,7 +407,7 @@ pmx0: pinmux@f7010000 { compatible = "pinctrl-single"; reg = <0x0 0xf7010000 0x0 0x27c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; #gpio-range-cells = <3>; pinctrl-single,register-width = <32>; @@ -446,7 +446,7 @@ pmx1: pinmux@f7010800 { compatible = "pinconf-single"; reg = <0x0 0xf7010800 0x0 0x28c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; @@ -455,7 +455,7 @@ pmx2: pinmux@f8001800 { compatible = "pinconf-single"; reg = <0x0 0xf8001800 0x0 0x78>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi index e7d22619a4c0b..3e27624c31def 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi @@ -17,13 +17,13 @@ &pwm_in_pmx_func &bl_pwm_pmx_func >; - boot_sel_pmx_func: boot_sel_pmx_func { + boot_sel_pmx_func: boot-sel-pins { pinctrl-single,pins = < 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ >; }; - emmc_pmx_func: emmc_pmx_func { + emmc_pmx_func: emmc-pins { pinctrl-single,pins = < 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ @@ -38,7 +38,7 @@ emmc_pmx_func: emmc_pmx_func { >; }; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0xc MUX_M0 /* SD_CLK (IOMG003) */ 0x10 MUX_M0 /* SD_CMD (IOMG004) */ @@ -48,7 +48,7 @@ sd_pmx_func: sd_pmx_func { 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ >; }; - sd_pmx_idle: sd_pmx_idle { + sd_pmx_idle: sd-idle-pins { pinctrl-single,pins = < 0xc MUX_M1 /* SD_CLK (IOMG003) */ 0x10 MUX_M1 /* SD_CMD (IOMG004) */ @@ -59,7 +59,7 @@ sd_pmx_idle: sd_pmx_idle { >; }; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ @@ -69,7 +69,7 @@ sdio_pmx_func: sdio_pmx_func { 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ >; }; - sdio_pmx_idle: sdio_pmx_idle { + sdio_pmx_idle: sdio-idle-pins { pinctrl-single,pins = < 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ @@ -80,7 +80,7 @@ sdio_pmx_idle: sdio_pmx_idle { >; }; - isp_pmx_func: isp_pmx_func { + isp_pmx_func: isp-pins { pinctrl-single,pins = < 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ @@ -101,19 +101,19 @@ isp_pmx_func: isp_pmx_func { >; }; - hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { + hkadc_ssi_pmx_func: hkadc-ssi-pins { pinctrl-single,pins = < 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ >; }; - codec_clk_pmx_func: codec_clk_pmx_func { + codec_clk_pmx_func: codec-clk-pins { pinctrl-single,pins = < 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ >; }; - codec_pmx_func: codec_pmx_func { + codec_pmx_func: codec-pins { pinctrl-single,pins = < 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ @@ -122,7 +122,7 @@ codec_pmx_func: codec_pmx_func { >; }; - fm_pmx_func: fm_pmx_func { + fm_pmx_func: fm-pins { pinctrl-single,pins = < 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ 0x84 MUX_M1 /* FM_XFS (IOMG033) */ @@ -131,7 +131,7 @@ fm_pmx_func: fm_pmx_func { >; }; - bt_pmx_func: bt_pmx_func { + bt_pmx_func: bt-pins { pinctrl-single,pins = < 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ 0x94 MUX_M0 /* BT_XFS (IOMG037) */ @@ -140,26 +140,26 @@ bt_pmx_func: bt_pmx_func { >; }; - pwm_in_pmx_func: pwm_in_pmx_func { + pwm_in_pmx_func: pwm-in-pins { pinctrl-single,pins = < 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ >; }; - bl_pwm_pmx_func: bl_pwm_pmx_func { + bl_pwm_pmx_func: bl-pwm-pins { pinctrl-single,pins = < 0xbc MUX_M1 /* BL_PWM (IOMG047) */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ @@ -168,7 +168,7 @@ uart1_pmx_func: uart1_pmx_func { >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ @@ -177,7 +177,7 @@ uart2_pmx_func: uart2_pmx_func { >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ @@ -186,7 +186,7 @@ uart3_pmx_func: uart3_pmx_func { >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ @@ -195,35 +195,35 @@ uart4_pmx_func: uart4_pmx_func { >; }; - uart5_pmx_func: uart5_pmx_func { + uart5_pmx_func: uart5-pins { pinctrl-single,pins = < 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ @@ -244,7 +244,7 @@ &pwm_in_cfg_func &bl_pwm_cfg_func >; - boot_sel_cfg_func: boot_sel_cfg_func { + boot_sel_cfg_func: boot-sel-cfg-pins { pinctrl-single,pins = < 0x0 0x0 /* BOOT_SEL (IOCFG000) */ >; @@ -253,7 +253,7 @@ boot_sel_cfg_func: boot_sel_cfg_func { pinctrl-single,drive-strength = ; }; - hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { + hkadc_ssi_cfg_func: hkadc-ssi-cfg-pins { pinctrl-single,pins = < 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ >; @@ -262,7 +262,7 @@ hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { pinctrl-single,drive-strength = ; }; - emmc_clk_cfg_func: emmc_clk_cfg_func { + emmc_clk_cfg_func: emmc-clk-cfg-pins { pinctrl-single,pins = < 0x104 0x0 /* EMMC_CLK (IOCFG065) */ >; @@ -271,7 +271,7 @@ emmc_clk_cfg_func: emmc_clk_cfg_func { pinctrl-single,drive-strength = ; }; - emmc_cfg_func: emmc_cfg_func { + emmc_cfg_func: emmc-cfg-pins { pinctrl-single,pins = < 0x108 0x0 /* EMMC_CMD (IOCFG066) */ 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ @@ -288,7 +288,7 @@ emmc_cfg_func: emmc_cfg_func { pinctrl-single,drive-strength = ; }; - emmc_rst_cfg_func: emmc_rst_cfg_func { + emmc_rst_cfg_func: emmc-rst-cfg-pins { pinctrl-single,pins = < 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ >; @@ -297,7 +297,7 @@ emmc_rst_cfg_func: emmc_rst_cfg_func { pinctrl-single,drive-strength = ; }; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0xc 0x0 /* SD_CLK (IOCFG003) */ >; @@ -305,7 +305,7 @@ sd_clk_cfg_func: sd_clk_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sd_clk_cfg_idle: sd_clk_cfg_idle { + sd_clk_cfg_idle: sd-clk-cfg-idle-pins { pinctrl-single,pins = < 0xc 0x0 /* SD_CLK (IOCFG003) */ >; @@ -314,7 +314,7 @@ sd_clk_cfg_idle: sd_clk_cfg_idle { pinctrl-single,drive-strength = ; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x10 0x0 /* SD_CMD (IOCFG004) */ 0x14 0x0 /* SD_DATA0 (IOCFG005) */ @@ -326,7 +326,7 @@ sd_cfg_func: sd_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sd_cfg_idle: sd_cfg_idle { + sd_cfg_idle: sd-cfg-idle-pins { pinctrl-single,pins = < 0x10 0x0 /* SD_CMD (IOCFG004) */ 0x14 0x0 /* SD_DATA0 (IOCFG005) */ @@ -339,7 +339,7 @@ sd_cfg_idle: sd_cfg_idle { pinctrl-single,drive-strength = ; }; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x134 0x0 /* SDIO_CLK (IOCFG077) */ >; @@ -347,7 +347,7 @@ sdio_clk_cfg_func: sdio_clk_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sdio_clk_cfg_idle: sdio_clk_cfg_idle { + sdio_clk_cfg_idle: sdio-clk-cfg-idle-pins { pinctrl-single,pins = < 0x134 0x0 /* SDIO_CLK (IOCFG077) */ >; @@ -356,7 +356,7 @@ sdio_clk_cfg_idle: sdio_clk_cfg_idle { pinctrl-single,drive-strength = ; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ @@ -368,7 +368,7 @@ sdio_cfg_func: sdio_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - sdio_cfg_idle: sdio_cfg_idle { + sdio_cfg_idle: sdio-cfg-idle-pins { pinctrl-single,pins = < 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ @@ -381,7 +381,7 @@ sdio_cfg_idle: sdio_cfg_idle { pinctrl-single,drive-strength = ; }; - isp_cfg_func1: isp_cfg_func1 { + isp_cfg_func1: isp-cfg-func1-pins { pinctrl-single,pins = < 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ @@ -403,7 +403,7 @@ isp_cfg_func1: isp_cfg_func1 { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - isp_cfg_idle1: isp_cfg_idle1 { + isp_cfg_idle1: isp-cfg-idle1-pins { pinctrl-single,pins = < 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ @@ -413,7 +413,7 @@ isp_cfg_idle1: isp_cfg_idle1 { pinctrl-single,drive-strength = ; }; - isp_cfg_func2: isp_cfg_func2 { + isp_cfg_func2: isp-cfg-func2-pins { pinctrl-single,pins = < 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ >; @@ -422,7 +422,7 @@ isp_cfg_func2: isp_cfg_func2 { pinctrl-single,drive-strength = ; }; - codec_clk_cfg_func: codec_clk_cfg_func { + codec_clk_cfg_func: codec-clk-cfg-pins { pinctrl-single,pins = < 0x70 0x0 /* CODEC_CLK (IOCFG028) */ >; @@ -430,7 +430,7 @@ codec_clk_cfg_func: codec_clk_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - codec_clk_cfg_idle: codec_clk_cfg_idle { + codec_clk_cfg_idle: codec-clk-cfg-idle-pins { pinctrl-single,pins = < 0x70 0x0 /* CODEC_CLK (IOCFG028) */ >; @@ -439,7 +439,7 @@ codec_clk_cfg_idle: codec_clk_cfg_idle { pinctrl-single,drive-strength = ; }; - codec_cfg_func1: codec_cfg_func1 { + codec_cfg_func1: codec-cfg-func1-pins { pinctrl-single,pins = < 0x74 0x0 /* DMIC_CLK (IOCFG029) */ >; @@ -448,7 +448,7 @@ codec_cfg_func1: codec_cfg_func1 { pinctrl-single,drive-strength = ; }; - codec_cfg_func2: codec_cfg_func2 { + codec_cfg_func2: codec-cfg-func2-pins { pinctrl-single,pins = < 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 0x7c 0x0 /* CODEC_DI (IOCFG031) */ @@ -458,7 +458,7 @@ codec_cfg_func2: codec_cfg_func2 { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - codec_cfg_idle2: codec_cfg_idle2 { + codec_cfg_idle2: codec-cfg-idle2-pins { pinctrl-single,pins = < 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 0x7c 0x0 /* CODEC_DI (IOCFG031) */ @@ -469,7 +469,7 @@ codec_cfg_idle2: codec_cfg_idle2 { pinctrl-single,drive-strength = ; }; - fm_cfg_func: fm_cfg_func { + fm_cfg_func: fm-cfg-pins { pinctrl-single,pins = < 0x84 0x0 /* FM_XCLK (IOCFG033) */ 0x88 0x0 /* FM_XFS (IOCFG034) */ @@ -481,7 +481,7 @@ fm_cfg_func: fm_cfg_func { pinctrl-single,drive-strength = ; }; - bt_cfg_func: bt_cfg_func { + bt_cfg_func: bt-cfg-pins { pinctrl-single,pins = < 0x94 0x0 /* BT_XCLK (IOCFG037) */ 0x98 0x0 /* BT_XFS (IOCFG038) */ @@ -492,7 +492,7 @@ bt_cfg_func: bt_cfg_func { pinctrl-single,bias-pullup = ; pinctrl-single,drive-strength = ; }; - bt_cfg_idle: bt_cfg_idle { + bt_cfg_idle: bt-cfg-idle-pins { pinctrl-single,pins = < 0x94 0x0 /* BT_XCLK (IOCFG037) */ 0x98 0x0 /* BT_XFS (IOCFG038) */ @@ -504,7 +504,7 @@ bt_cfg_idle: bt_cfg_idle { pinctrl-single,drive-strength = ; }; - pwm_in_cfg_func: pwm_in_cfg_func { + pwm_in_cfg_func: pwm-in-cfg-pins { pinctrl-single,pins = < 0xbc 0x0 /* PWM_IN (IOCFG047) */ >; @@ -513,7 +513,7 @@ pwm_in_cfg_func: pwm_in_cfg_func { pinctrl-single,drive-strength = ; }; - bl_pwm_cfg_func: bl_pwm_cfg_func { + bl_pwm_cfg_func: bl-pwm-cfg-pins { pinctrl-single,pins = < 0xc0 0x0 /* BL_PWM (IOCFG048) */ >; @@ -522,7 +522,7 @@ bl_pwm_cfg_func: bl_pwm_cfg_func { pinctrl-single,drive-strength = ; }; - uart0_cfg_func1: uart0_cfg_func1 { + uart0_cfg_func1: uart0-cfg-func1-pins { pinctrl-single,pins = < 0xc4 0x0 /* UART0_RXD (IOCFG049) */ >; @@ -531,7 +531,7 @@ uart0_cfg_func1: uart0_cfg_func1 { pinctrl-single,drive-strength = ; }; - uart0_cfg_func2: uart0_cfg_func2 { + uart0_cfg_func2: uart0-cfg-func2-pins { pinctrl-single,pins = < 0xc8 0x0 /* UART0_TXD (IOCFG050) */ >; @@ -540,7 +540,7 @@ uart0_cfg_func2: uart0_cfg_func2 { pinctrl-single,drive-strength = ; }; - uart1_cfg_func1: uart1_cfg_func1 { + uart1_cfg_func1: uart1-cfg-func1-pins { pinctrl-single,pins = < 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ 0xd4 0x0 /* UART1_RXD (IOCFG053) */ @@ -550,7 +550,7 @@ uart1_cfg_func1: uart1_cfg_func1 { pinctrl-single,drive-strength = ; }; - uart1_cfg_func2: uart1_cfg_func2 { + uart1_cfg_func2: uart1-cfg-func2-pins { pinctrl-single,pins = < 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ 0xd8 0x0 /* UART1_TXD (IOCFG054) */ @@ -560,7 +560,7 @@ uart1_cfg_func2: uart1_cfg_func2 { pinctrl-single,drive-strength = ; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ @@ -572,7 +572,7 @@ uart2_cfg_func: uart2_cfg_func { pinctrl-single,drive-strength = ; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ @@ -584,7 +584,7 @@ uart3_cfg_func: uart3_cfg_func { pinctrl-single,drive-strength = ; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ @@ -596,7 +596,7 @@ uart4_cfg_func: uart4_cfg_func { pinctrl-single,drive-strength = ; }; - uart5_cfg_func: uart5_cfg_func { + uart5_cfg_func: uart5-cfg-pins { pinctrl-single,pins = < 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ @@ -606,7 +606,7 @@ uart5_cfg_func: uart5_cfg_func { pinctrl-single,drive-strength = ; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0xec 0x0 /* I2C0_SCL (IOCFG059) */ 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ @@ -616,7 +616,7 @@ i2c0_cfg_func: i2c0_cfg_func { pinctrl-single,drive-strength = ; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ @@ -626,7 +626,7 @@ i2c1_cfg_func: i2c1_cfg_func { pinctrl-single,drive-strength = ; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ 0x100 0x0 /* I2C2_SDA (IOCFG064) */ @@ -636,7 +636,7 @@ i2c2_cfg_func: i2c2_cfg_func { pinctrl-single,drive-strength = ; }; - spi0_cfg_func: spi0_cfg_func { + spi0_cfg_func: spi0-cfg-pins { pinctrl-single,pins = < 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ @@ -656,7 +656,7 @@ pmx2: pinmux@f8001800 { &rstout_n_cfg_func >; - rstout_n_cfg_func: rstout_n_cfg_func { + rstout_n_cfg_func: rstout-n-cfg-pins { pinctrl-single,pins = < 0x0 0x0 /* RSTOUT_N (IOCFG000) */ >; @@ -665,7 +665,7 @@ rstout_n_cfg_func: rstout_n_cfg_func { pinctrl-single,drive-strength = ; }; - pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { + pmu_peri_en_cfg_func: pmu-peri-en-cfg-pins { pinctrl-single,pins = < 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ >; @@ -674,7 +674,7 @@ pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { pinctrl-single,drive-strength = ; }; - sysclk0_en_cfg_func: sysclk0_en_cfg_func { + sysclk0_en_cfg_func: sysclk0-en-cfg-pins { pinctrl-single,pins = < 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ >; @@ -683,7 +683,7 @@ sysclk0_en_cfg_func: sysclk0_en_cfg_func { pinctrl-single,drive-strength = ; }; - jtag_tdo_cfg_func: jtag_tdo_cfg_func { + jtag_tdo_cfg_func: jtag-tdo-cfg-pins { pinctrl-single,pins = < 0xc 0x0 /* JTAG_TDO (IOCFG003) */ >; @@ -692,7 +692,7 @@ jtag_tdo_cfg_func: jtag_tdo_cfg_func { pinctrl-single,drive-strength = ; }; - rf_reset_cfg_func: rf_reset_cfg_func { + rf_reset_cfg_func: rf-reset-cfg-pins { pinctrl-single,pins = < 0x70 0x0 /* RF_RESET0 (IOCFG028) */ 0x74 0x0 /* RF_RESET1 (IOCFG029) */ diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 920a3111c66dd..b801a48041f9c 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -25,7 +25,7 @@ pmx0: pinmux@e896c000 { &range 0 7 0 &range 8 116 0>; - pmu_pmx_func: pmu_pmx_func { + pmu_pmx_func: pmu-pins { pinctrl-single,pins = < 0x008 MUX_M1 /* PMU1_SSI */ 0x00c MUX_M1 /* PMU2_SSI */ @@ -34,19 +34,19 @@ pmu_pmx_func: pmu_pmx_func { >; }; - csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + csi0_pwd_n_pmx_func: csi0-pwd-n-pins { pinctrl-single,pins = < 0x044 MUX_M0 /* CSI0_PWD_N */ >; }; - csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + csi1_pwd_n_pmx_func: csi1-pwd-n-pins { pinctrl-single,pins = < 0x04c MUX_M0 /* CSI1_PWD_N */ >; }; - isp0_pmx_func: isp0_pmx_func { + isp0_pmx_func: isp0-pins { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ 0x064 MUX_M1 /* ISP_SCL0 */ @@ -54,7 +54,7 @@ isp0_pmx_func: isp0_pmx_func { >; }; - isp1_pmx_func: isp1_pmx_func { + isp1_pmx_func: isp1-pins { pinctrl-single,pins = < 0x05c MUX_M1 /* ISP_CLK1 */ 0x06c MUX_M1 /* ISP_SCL1 */ @@ -62,47 +62,47 @@ isp1_pmx_func: isp1_pmx_func { >; }; - pwr_key_pmx_func: pwr_key_pmx_func { + pwr_key_pmx_func: pwr-key-pins { pinctrl-single,pins = < 0x080 MUX_M0 /* GPIO_034 */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ 0x030 MUX_M1 /* I2C3_SDA */ >; }; - i2c4_pmx_func: i2c4_pmx_func { + i2c4_pmx_func: i2c4-pins { pinctrl-single,pins = < 0x090 MUX_M1 /* I2C4_SCL */ 0x094 MUX_M1 /* I2C4_SDA */ >; }; - pcie_perstn_pmx_func: pcie_perstn_pmx_func { + pcie_perstn_pmx_func: pcie-perstn-pins { pinctrl-single,pins = < 0x15c MUX_M1 /* PCIE_PERST_N */ >; }; - usbhub5734_pmx_func: usbhub5734_pmx_func { + usbhub5734_pmx_func: usbhub5734-pins { pinctrl-single,pins = < 0x11c MUX_M0 /* GPIO_073 */ 0x120 MUX_M0 /* GPIO_074 */ >; }; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ >; }; - uart1_pmx_func: uart1_pmx_func { + uart1_pmx_func: uart1-pins { pinctrl-single,pins = < 0x0b0 MUX_M2 /* UART1_CTS_N */ 0x0b4 MUX_M2 /* UART1_RTS_N */ @@ -111,7 +111,7 @@ uart1_pmx_func: uart1_pmx_func { >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x0bc MUX_M2 /* UART2_CTS_N */ 0x0c0 MUX_M2 /* UART2_RTS_N */ @@ -120,7 +120,7 @@ uart2_pmx_func: uart2_pmx_func { >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x0dc MUX_M1 /* UART3_CTS_N */ 0x0e0 MUX_M1 /* UART3_RTS_N */ @@ -129,7 +129,7 @@ uart3_pmx_func: uart3_pmx_func { >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x0ec MUX_M1 /* UART4_CTS_N */ 0x0f0 MUX_M1 /* UART4_RTS_N */ @@ -138,7 +138,7 @@ uart4_pmx_func: uart4_pmx_func { >; }; - uart5_pmx_func: uart5_pmx_func { + uart5_pmx_func: uart5-pins { pinctrl-single,pins = < 0x0c4 MUX_M3 /* UART5_CTS_N */ 0x0c8 MUX_M3 /* UART5_RTS_N */ @@ -147,7 +147,7 @@ uart5_pmx_func: uart5_pmx_func { >; }; - uart6_pmx_func: uart6_pmx_func { + uart6_pmx_func: uart6-pins { pinctrl-single,pins = < 0x0cc MUX_M1 /* UART6_CTS_N */ 0x0d0 MUX_M1 /* UART6_RTS_N */ @@ -156,13 +156,13 @@ uart6_pmx_func: uart6_pmx_func { >; }; - cam0_rst_pmx_func: cam0_rst_pmx_func { + cam0_rst_pmx_func: cam0-rst-pins { pinctrl-single,pins = < 0x0c8 MUX_M0 /* CAM0_RST */ >; }; - cam1_rst_pmx_func: cam1_rst_pmx_func { + cam1_rst_pmx_func: cam1-rst-pins { pinctrl-single,pins = < 0x124 MUX_M0 /* CAM1_RST */ >; @@ -180,7 +180,7 @@ pmx1: pinmux@ff37e000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 6 0>; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SD_CLK */ 0x004 MUX_M1 /* SD_CMD */ @@ -203,14 +203,14 @@ pmx2: pinmux@ff3b6000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; - ufs_pmx_func: ufs_pmx_func { + ufs_pmx_func: ufs-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* UFS_REF_CLK */ 0x004 MUX_M1 /* UFS_RST_N */ >; }; - spi3_pmx_func: spi3_pmx_func { + spi3_pmx_func: spi3-pins { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ 0x00c MUX_M1 /* SPI3_DI */ @@ -231,7 +231,7 @@ pmx3: pinmux@ff3fd000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 6 0>; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SDIO_CLK */ 0x004 MUX_M1 /* SDIO_CMD */ @@ -254,7 +254,7 @@ pmx4: pinmux@fff11000 { /* pin base in node, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 42 0>; - i2s2_pmx_func: i2s2_pmx_func { + i2s2_pmx_func: i2s2-pins { pinctrl-single,pins = < 0x044 MUX_M1 /* I2S2_DI */ 0x048 MUX_M1 /* I2S2_DO */ @@ -263,42 +263,42 @@ i2s2_pmx_func: i2s2_pmx_func { >; }; - slimbus_pmx_func: slimbus_pmx_func { + slimbus_pmx_func: slimbus-pins { pinctrl-single,pins = < 0x02c MUX_M1 /* SLIMBUS_CLK */ 0x030 MUX_M1 /* SLIMBUS_DATA */ >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x014 MUX_M1 /* I2C0_SCL */ 0x018 MUX_M1 /* I2C0_SDA */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x01c MUX_M1 /* I2C1_SCL */ 0x020 MUX_M1 /* I2C1_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + i2c7_pmx_func: i2c7-pins { pinctrl-single,pins = < 0x024 MUX_M3 /* I2C7_SCL */ 0x028 MUX_M3 /* I2C7_SDA */ >; }; - pcie_pmx_func: pcie_pmx_func { + pcie_pmx_func: pcie-pins { pinctrl-single,pins = < 0x084 MUX_M1 /* PCIE_CLKREQ_N */ 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; - spi2_pmx_func: spi2_pmx_func { + spi2_pmx_func: spi2-pins { pinctrl-single,pins = < 0x08c MUX_M1 /* SPI2_CLK */ 0x090 MUX_M1 /* SPI2_DI */ @@ -307,7 +307,7 @@ spi2_pmx_func: spi2_pmx_func { >; }; - i2s0_pmx_func: i2s0_pmx_func { + i2s0_pmx_func: i2s0-pins { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ 0x038 MUX_M1 /* I2S0_DO */ @@ -323,7 +323,7 @@ pmx5: pinmux@e896c800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - pmu_cfg_func: pmu_cfg_func { + pmu_cfg_func: pmu-cfg-pins { pinctrl-single,pins = < 0x010 0x0 /* PMU1_SSI */ 0x014 0x0 /* PMU2_SSI */ @@ -347,7 +347,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x038 0x0 /* I2C3_SCL */ 0x03c 0x0 /* I2C3_SDA */ @@ -369,7 +369,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + csi0_pwd_n_cfg_func: csi0-pwd-n-cfg-pins { pinctrl-single,pins = < 0x050 0x0 /* CSI0_PWD_N */ >; @@ -390,7 +390,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + csi1_pwd_n_cfg_func: csi1-pwd-n-cfg-pins { pinctrl-single,pins = < 0x058 0x0 /* CSI1_PWD_N */ >; @@ -411,7 +411,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - isp0_cfg_func: isp0_cfg_func { + isp0_cfg_func: isp0-cfg-pins { pinctrl-single,pins = < 0x064 0x0 /* ISP_CLK0 */ 0x070 0x0 /* ISP_SCL0 */ @@ -433,7 +433,7 @@ PULL_UP DRIVE7_04MA DRIVE6_MASK>; }; - isp1_cfg_func: isp1_cfg_func { + isp1_cfg_func: isp1-cfg-pins { pinctrl-single,pins = < 0x068 0x0 /* ISP_CLK1 */ 0x078 0x0 /* ISP_SCL1 */ @@ -456,7 +456,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - pwr_key_cfg_func: pwr_key_cfg_func { + pwr_key_cfg_func: pwr-key-cfg-pins { pinctrl-single,pins = < 0x08c 0x0 /* GPIO_034 */ >; @@ -477,7 +477,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart1_cfg_func: uart1_cfg_func { + uart1_cfg_func: uart1-cfg-pins { pinctrl-single,pins = < 0x0b4 0x0 /* UART1_RXD */ 0x0b8 0x0 /* UART1_TXD */ @@ -501,7 +501,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* UART2_CTS_N */ 0x0cc 0x0 /* UART2_RTS_N */ @@ -525,7 +525,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart5_cfg_func: uart5_cfg_func { + uart5_cfg_func: uart5-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* UART5_RXD */ 0x0cc 0x0 /* UART5_TXD */ @@ -549,7 +549,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - cam0_rst_cfg_func: cam0_rst_cfg_func { + cam0_rst_cfg_func: cam0-rst-cfg-pins { pinctrl-single,pins = < 0x0d4 0x0 /* CAM0_RST */ >; @@ -570,7 +570,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x0d8 0x0 /* UART0_RXD */ 0x0dc 0x0 /* UART0_TXD */ @@ -592,7 +592,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart6_cfg_func: uart6_cfg_func { + uart6_cfg_func: uart6-cfg-pins { pinctrl-single,pins = < 0x0d8 0x0 /* UART6_CTS_N */ 0x0dc 0x0 /* UART6_RTS_N */ @@ -616,7 +616,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x0e8 0x0 /* UART3_CTS_N */ 0x0ec 0x0 /* UART3_RTS_N */ @@ -640,7 +640,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x0f8 0x0 /* UART4_CTS_N */ 0x0fc 0x0 /* UART4_RTS_N */ @@ -664,7 +664,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - cam1_rst_cfg_func: cam1_rst_cfg_func { + cam1_rst_cfg_func: cam1-rst-cfg-pins { pinctrl-single,pins = < 0x130 0x0 /* CAM1_RST */ >; @@ -692,7 +692,7 @@ pmx6: pinmux@ff3b6800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - ufs_cfg_func: ufs_cfg_func { + ufs_cfg_func: ufs-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* UFS_REF_CLK */ 0x004 0x0 /* UFS_RST_N */ @@ -714,7 +714,7 @@ DRIVE7_08MA DRIVE6_MASK >; }; - spi3_cfg_func: spi3_cfg_func { + spi3_cfg_func: spi3-cfg-pins { pinctrl-single,pins = < 0x008 0x0 /* SPI3_CLK */ 0x00c 0x0 /* SPI3_DI */ @@ -745,7 +745,7 @@ pmx7: pinmux@ff3fd800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SDIO_CLK */ >; @@ -766,7 +766,7 @@ DRIVE6_32MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SDIO_CMD */ 0x008 0x0 /* SDIO_DATA0 */ @@ -798,7 +798,7 @@ pmx8: pinmux@ff37e800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SD_CLK */ >; @@ -820,7 +820,7 @@ DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SD_CMD */ 0x008 0x0 /* SD_DATA0 */ @@ -853,7 +853,7 @@ pmx9: pinmux@fff11800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x01c 0x0 /* I2C0_SCL */ 0x020 0x0 /* I2C0_SDA */ @@ -875,7 +875,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x024 0x0 /* I2C1_SCL */ 0x028 0x0 /* I2C1_SDA */ @@ -897,7 +897,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - i2c7_cfg_func: i2c7_cfg_func { + i2c7_cfg_func: i2c7-cfg-pins { pinctrl-single,pins = < 0x02c 0x0 /* I2C7_SCL */ 0x030 0x0 /* I2C7_SDA */ @@ -919,7 +919,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - slimbus_cfg_func: slimbus_cfg_func { + slimbus_cfg_func: slimbus-cfg-pins { pinctrl-single,pins = < 0x034 0x0 /* SLIMBUS_CLK */ 0x038 0x0 /* SLIMBUS_DATA */ @@ -941,7 +941,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - i2s0_cfg_func: i2s0_cfg_func { + i2s0_cfg_func: i2s0-cfg-pins { pinctrl-single,pins = < 0x040 0x0 /* I2S0_DI */ 0x044 0x0 /* I2S0_DO */ @@ -965,7 +965,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - i2s2_cfg_func: i2s2_cfg_func { + i2s2_cfg_func: i2s2-cfg-pins { pinctrl-single,pins = < 0x050 0x0 /* I2S2_DI */ 0x054 0x0 /* I2S2_DO */ @@ -989,7 +989,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - pcie_cfg_func: pcie_cfg_func { + pcie_cfg_func: pcie-cfg-pins { pinctrl-single,pins = < 0x094 0x0 /* PCIE_CLKREQ_N */ 0x098 0x0 /* PCIE_WAKE_N */ @@ -1011,7 +1011,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - spi2_cfg_func: spi2_cfg_func { + spi2_cfg_func: spi2-cfg-pins { pinctrl-single,pins = < 0x09c 0x0 /* SPI2_CLK */ 0x0a0 0x0 /* SPI2_DI */ @@ -1035,7 +1035,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - usb_cfg_func: usb_cfg_func { + usb_cfg_func: usb-cfg-pins { pinctrl-single,pins = < 0x0ac 0x0 /* GPIO_219 */ >; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index 77bd8c3a83145..8f7bf80e6ece7 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -21,14 +21,14 @@ pmx0: pinmux@e896c000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 82 0>; - uart0_pmx_func: uart0_pmx_func { + uart0_pmx_func: uart0-pins { pinctrl-single,pins = < 0x054 MUX_M2 /* UART0_RXD */ 0x058 MUX_M2 /* UART0_TXD */ >; }; - uart2_pmx_func: uart2_pmx_func { + uart2_pmx_func: uart2-pins { pinctrl-single,pins = < 0x700 MUX_M2 /* UART2_CTS_N */ 0x704 MUX_M2 /* UART2_RTS_N */ @@ -37,7 +37,7 @@ uart2_pmx_func: uart2_pmx_func { >; }; - uart3_pmx_func: uart3_pmx_func { + uart3_pmx_func: uart3-pins { pinctrl-single,pins = < 0x064 MUX_M1 /* UART3_CTS_N */ 0x068 MUX_M1 /* UART3_RTS_N */ @@ -46,7 +46,7 @@ uart3_pmx_func: uart3_pmx_func { >; }; - uart4_pmx_func: uart4_pmx_func { + uart4_pmx_func: uart4-pins { pinctrl-single,pins = < 0x074 MUX_M1 /* UART4_CTS_N */ 0x078 MUX_M1 /* UART4_RTS_N */ @@ -55,52 +55,52 @@ uart4_pmx_func: uart4_pmx_func { >; }; - uart6_pmx_func: uart6_pmx_func { + uart6_pmx_func: uart6-pins { pinctrl-single,pins = < 0x05c MUX_M1 /* UART6_RXD */ 0x060 MUX_M1 /* UART6_TXD */ >; }; - i2c3_pmx_func: i2c3_pmx_func { + i2c3_pmx_func: i2c3-pins { pinctrl-single,pins = < 0x010 MUX_M1 /* I2C3_SCL */ 0x014 MUX_M1 /* I2C3_SDA */ >; }; - i2c4_pmx_func: i2c4_pmx_func { + i2c4_pmx_func: i2c4-pins { pinctrl-single,pins = < 0x03c MUX_M1 /* I2C4_SCL */ 0x040 MUX_M1 /* I2C4_SDA */ >; }; - cam0_rst_pmx_func: cam0_rst_pmx_func { + cam0_rst_pmx_func: cam0-rst-pins { pinctrl-single,pins = < 0x714 MUX_M0 /* CAM0_RST */ >; }; - cam1_rst_pmx_func: cam1_rst_pmx_func { + cam1_rst_pmx_func: cam1-rst-pins { pinctrl-single,pins = < 0x048 MUX_M0 /* CAM1_RST */ >; }; - cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func { + cam0_pwd_n_pmx_func: cam0-pwd-n-pins { pinctrl-single,pins = < 0x098 MUX_M0 /* CAM0_PWD_N */ >; }; - cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func { + cam1_pwd_n_pmx_func: cam1-pwd-n-pins { pinctrl-single,pins = < 0x044 MUX_M0 /* CAM1_PWD_N */ >; }; - isp0_pmx_func: isp0_pmx_func { + isp0_pmx_func: isp0-pins { pinctrl-single,pins = < 0x018 MUX_M1 /* ISP_CLK0 */ 0x024 MUX_M1 /* ISP_SCL0 */ @@ -108,7 +108,7 @@ isp0_pmx_func: isp0_pmx_func { >; }; - isp1_pmx_func: isp1_pmx_func { + isp1_pmx_func: isp1-pins { pinctrl-single,pins = < 0x01c MUX_M1 /* ISP_CLK1 */ 0x02c MUX_M1 /* ISP_SCL1 */ @@ -127,19 +127,19 @@ pmx1: pinmux@fff11000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 46 0>; - pwr_key_pmx_func: pwr_key_pmx_func { + pwr_key_pmx_func: pwr-key-pins { pinctrl-single,pins = < 0x064 MUX_M0 /* GPIO_203 */ >; }; - pd_pmx_func: pd_pmx_func{ + pd_pmx_func: pd-pins { pinctrl-single,pins = < 0x080 MUX_M0 /* GPIO_221 */ >; }; - i2s2_pmx_func: i2s2_pmx_func { + i2s2_pmx_func: i2s2-pins { pinctrl-single,pins = < 0x050 MUX_M1 /* I2S2_DI */ 0x054 MUX_M1 /* I2S2_DO */ @@ -148,7 +148,7 @@ i2s2_pmx_func: i2s2_pmx_func { >; }; - spi0_pmx_func: spi0_pmx_func { + spi0_pmx_func: spi0-pins { pinctrl-single,pins = < 0x094 MUX_M1 /* SPI0_CLK */ 0x098 MUX_M1 /* SPI0_DI */ @@ -157,7 +157,7 @@ spi0_pmx_func: spi0_pmx_func { >; }; - spi2_pmx_func: spi2_pmx_func { + spi2_pmx_func: spi2-pins { pinctrl-single,pins = < 0x710 MUX_M1 /* SPI2_CLK */ 0x714 MUX_M1 /* SPI2_DI */ @@ -166,7 +166,7 @@ spi2_pmx_func: spi2_pmx_func { >; }; - spi3_pmx_func: spi3_pmx_func { + spi3_pmx_func: spi3-pins { pinctrl-single,pins = < 0x72c MUX_M1 /* SPI3_CLK */ 0x730 MUX_M1 /* SPI3_DI */ @@ -175,37 +175,37 @@ spi3_pmx_func: spi3_pmx_func { >; }; - i2c0_pmx_func: i2c0_pmx_func { + i2c0_pmx_func: i2c0-pins { pinctrl-single,pins = < 0x020 MUX_M1 /* I2C0_SCL */ 0x024 MUX_M1 /* I2C0_SDA */ >; }; - i2c1_pmx_func: i2c1_pmx_func { + i2c1_pmx_func: i2c1-pins { pinctrl-single,pins = < 0x028 MUX_M1 /* I2C1_SCL */ 0x02c MUX_M1 /* I2C1_SDA */ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c2_pmx_func: i2c2-pins { pinctrl-single,pins = < 0x030 MUX_M1 /* I2C2_SCL */ 0x034 MUX_M1 /* I2C2_SDA */ >; }; - pcie_clkreq_pmx_func: pcie_clkreq_pmx_func { + pcie_clkreq_pmx_func: pcie-clkreq-pins { pinctrl-single,pins = < 0x084 MUX_M1 /* PCIE0_CLKREQ_N */ >; }; - gpio185_pmx_func: gpio185_pmx_func { + gpio185_pmx_func: gpio185-pins { pinctrl-single,pins = <0x01C 0x1>; }; - gpio185_pmx_idle: gpio185_pmx_idle { + gpio185_pmx_idle: gpio185-idle-pins { pinctrl-single,pins = <0x01C 0x0>; }; }; @@ -216,7 +216,7 @@ pmx2: pinmux@e896c800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - uart0_cfg_func: uart0_cfg_func { + uart0_cfg_func: uart0-cfg-pins { pinctrl-single,pins = < 0x058 0x0 /* UART0_RXD */ 0x05c 0x0 /* UART0_TXD */ @@ -238,7 +238,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - uart2_cfg_func: uart2_cfg_func { + uart2_cfg_func: uart2-cfg-pins { pinctrl-single,pins = < 0x700 0x0 /* UART2_CTS_N */ 0x704 0x0 /* UART2_RTS_N */ @@ -262,7 +262,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - uart3_cfg_func: uart3_cfg_func { + uart3_cfg_func: uart3-cfg-pins { pinctrl-single,pins = < 0x068 0x0 /* UART3_CTS_N */ 0x06c 0x0 /* UART3_RTS_N */ @@ -286,7 +286,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - uart4_cfg_func: uart4_cfg_func { + uart4_cfg_func: uart4-cfg-pins { pinctrl-single,pins = < 0x078 0x0 /* UART4_CTS_N */ 0x07c 0x0 /* UART4_RTS_N */ @@ -310,7 +310,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - uart6_cfg_func: uart6_cfg_func { + uart6_cfg_func: uart6-cfg-pins { pinctrl-single,pins = < 0x060 0x0 /* UART6_RXD */ 0x064 0x0 /* UART6_TXD */ @@ -332,7 +332,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - i2c3_cfg_func: i2c3_cfg_func { + i2c3_cfg_func: i2c3-cfg-pins { pinctrl-single,pins = < 0x014 0x0 /* I2C3_SCL */ 0x018 0x0 /* I2C3_SDA */ @@ -354,7 +354,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - i2c4_cfg_func: i2c4_cfg_func { + i2c4_cfg_func: i2c4-cfg-pins { pinctrl-single,pins = < 0x040 0x0 /* I2C4_SCL */ 0x044 0x0 /* I2C4_SDA */ @@ -376,7 +376,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - cam0_rst_cfg_func: cam0_rst_cfg_func { + cam0_rst_cfg_func: cam0-rst-cfg-pins { pinctrl-single,pins = < 0x714 0x0 /* CAM0_RST */ >; @@ -397,7 +397,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - cam1_rst_cfg_func: cam1_rst_cfg_func { + cam1_rst_cfg_func: cam1-rst-cfg-pins { pinctrl-single,pins = < 0x04C 0x0 /* CAM1_RST */ >; @@ -418,7 +418,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func { + cam0_pwd_n_cfg_func: cam0-pwd-n-cfg-pins { pinctrl-single,pins = < 0x09C 0x0 /* CAM0_PWD_N */ >; @@ -439,7 +439,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func { + cam1_pwd_n_cfg_func: cam1-pwd-n-cfg-pins { pinctrl-single,pins = < 0x048 0x0 /* CAM1_PWD_N */ >; @@ -460,7 +460,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - isp0_cfg_func: isp0_cfg_func { + isp0_cfg_func: isp0-cfg-pins { pinctrl-single,pins = < 0x01C 0x0 /* ISP_CLK0 */ 0x028 0x0 /* ISP_SCL0 */ @@ -483,7 +483,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - isp1_cfg_func: isp1_cfg_func { + isp1_cfg_func: isp1-cfg-pins { pinctrl-single,pins = < 0x020 0x0 /* ISP_CLK1 */ 0x030 0x0 /* ISP_SCL1 */ @@ -517,7 +517,7 @@ pmx5: pinmux@fc182000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 10 0>; - sdio_pmx_func: sdio_pmx_func { + sdio_pmx_func: sdio-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SDIO_CLK */ 0x004 MUX_M1 /* SDIO_CMD */ @@ -535,7 +535,7 @@ pmx6: pinmux@fc182800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + sdio_clk_cfg_func: sdio-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SDIO_CLK */ >; @@ -556,7 +556,7 @@ DRIVE6_32MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + sdio_cfg_func: sdio-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SDIO_CMD */ 0x008 0x0 /* SDIO_DATA0 */ @@ -592,7 +592,7 @@ pmx7: pinmux@ff37e000 { /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; - sd_pmx_func: sd_pmx_func { + sd_pmx_func: sd-pins { pinctrl-single,pins = < 0x000 MUX_M1 /* SD_CLK */ 0x004 MUX_M1 /* SD_CMD */ @@ -610,7 +610,7 @@ pmx8: pinmux@ff37e800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - sd_clk_cfg_func: sd_clk_cfg_func { + sd_clk_cfg_func: sd-clk-cfg-pins { pinctrl-single,pins = < 0x000 0x0 /* SD_CLK */ >; @@ -632,7 +632,7 @@ DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + sd_cfg_func: sd-cfg-pins { pinctrl-single,pins = < 0x004 0x0 /* SD_CMD */ 0x008 0x0 /* SD_DATA0 */ @@ -665,7 +665,7 @@ pmx16: pinmux@fff11800 { #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; - pwr_key_cfg_func: pwr_key_cfg_func { + pwr_key_cfg_func: pwr-key-cfg-pins { pinctrl-single,pins = < 0x090 0x0 /* GPIO_203 */ >; @@ -686,7 +686,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - usb_cfg_func: usb_cfg_func { + usb_cfg_func: usb-cfg-pins { pinctrl-single,pins = < 0x0AC 0x0 /* GPIO_221 */ >; @@ -707,7 +707,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - spi0_cfg_func: spi0_cfg_func { + spi0_cfg_func: spi0-cfg-pins { pinctrl-single,pins = < 0x0c8 0x0 /* SPI0_DI */ 0x0cc 0x0 /* SPI0_DO */ @@ -730,7 +730,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - spi2_cfg_func: spi2_cfg_func { + spi2_cfg_func: spi2-cfg-pins { pinctrl-single,pins = < 0x714 0x0 /* SPI2_DI */ 0x718 0x0 /* SPI2_DO */ @@ -753,7 +753,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - spi3_cfg_func: spi3_cfg_func { + spi3_cfg_func: spi3-cfg-pins { pinctrl-single,pins = < 0x730 0x0 /* SPI3_DI */ 0x734 0x0 /* SPI3_DO */ @@ -776,7 +776,7 @@ DRIVE7_06MA DRIVE6_MASK >; }; - spi0_clk_cfg_func: spi0_clk_cfg_func { + spi0_clk_cfg_func: spi0-clk-cfg-pins { pinctrl-single,pins = < 0x0c4 0x0 /* SPI0_CLK */ >; @@ -797,7 +797,7 @@ DRIVE7_10MA DRIVE6_MASK >; }; - spi2_clk_cfg_func: spi2_clk_cfg_func { + spi2_clk_cfg_func: spi2-clk-cfg-pins { pinctrl-single,pins = < 0x710 0x0 /* SPI2_CLK */ >; @@ -818,7 +818,7 @@ DRIVE7_10MA DRIVE6_MASK >; }; - spi3_clk_cfg_func: spi3_clk_cfg_func { + spi3_clk_cfg_func: spi3-clk-cfg-pins { pinctrl-single,pins = < 0x72c 0x0 /* SPI3_CLK */ >; @@ -839,7 +839,7 @@ DRIVE7_10MA DRIVE6_MASK >; }; - i2c0_cfg_func: i2c0_cfg_func { + i2c0_cfg_func: i2c0-cfg-pins { pinctrl-single,pins = < 0x04c 0x0 /* I2C0_SCL */ 0x050 0x0 /* I2C0_SDA */ @@ -861,7 +861,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - i2c1_cfg_func: i2c1_cfg_func { + i2c1_cfg_func: i2c1-cfg-pins { pinctrl-single,pins = < 0x054 0x0 /* I2C1_SCL */ 0x058 0x0 /* I2C1_SDA */ @@ -883,7 +883,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - i2c2_cfg_func: i2c2_cfg_func { + i2c2_cfg_func: i2c2-cfg-pins { pinctrl-single,pins = < 0x05c 0x0 /* I2C2_SCL */ 0x060 0x0 /* I2C2_SDA */ @@ -905,7 +905,7 @@ DRIVE7_04MA DRIVE6_MASK >; }; - pcie_clkreq_cfg_func: pcie_clkreq_cfg_func { + pcie_clkreq_cfg_func: pcie-clkreq-cfg-pins { pinctrl-single,pins = < 0x0b0 0x0 >; @@ -925,7 +925,7 @@ PULL_UP DRIVE7_06MA DRIVE6_MASK >; }; - i2s2_cfg_func: i2s2_cfg_func { + i2s2_cfg_func: i2s2-cfg-pins { pinctrl-single,pins = < 0x07c 0x0 /* I2S2_DI */ 0x080 0x0 /* I2S2_DO */ @@ -949,7 +949,7 @@ DRIVE7_02MA DRIVE6_MASK >; }; - gpio185_cfg_func: gpio185_cfg_func { + gpio185_cfg_func: gpio185-cfg-pins { pinctrl-single,pins = <0x048 0>; pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; @@ -957,7 +957,7 @@ gpio185_cfg_func: gpio185_cfg_func { pinctrl-single,slew-rate = <0x0 0x80>; }; - gpio185_cfg_idle: gpio185_cfg_idle { + gpio185_cfg_idle: gpio185-cfg-idle-pins { pinctrl-single,pins = <0x048 0>; pinctrl-single,bias-pulldown = <2 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; -- GitLab From 98788f7914af3fcb41101d76f02e1daed5e450a0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 23 May 2023 10:48:43 +0300 Subject: [PATCH 605/926] ARM: dts: Unify pinctrl-single pin group nodes for keystone We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley Cc: Krzysztof Kozlowski Cc: Rob Herring Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20230523074845.59433-1-tony@atomide.com Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/keystone-k2g-evm.dts | 30 +++++++++++++------------- arch/arm/boot/dts/keystone-k2g-ice.dts | 16 +++++++------- arch/arm/boot/dts/keystone-k2l.dtsi | 20 ++++++++--------- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 3a87b7943c706..7527dacb5e012 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -120,14 +120,14 @@ codec { }; &k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; - mmc0_pins: pinmux_mmc0_pins { + mmc0_pins: mmc0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ @@ -139,7 +139,7 @@ K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gp >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ @@ -154,27 +154,27 @@ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - ecap0_pins: ecap0_pins { + ecap0_pins: ecap0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ @@ -183,7 +183,7 @@ K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi. >; }; - qspi_pins: pinmux_qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ @@ -195,28 +195,28 @@ K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0. >; }; - uart2_pins: pinmux_uart2_pins { + uart2_pins: uart2-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ >; }; - dcan0_pins: pinmux_dcan0_pins { + dcan0_pins: dcan0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ >; }; - dcan1_pins: pinmux_dcan1_pins { + dcan1_pins: dcan1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ >; }; - emac_pins: pinmux_emac_pins { + emac_pins: emac-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ @@ -233,14 +233,14 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R >; }; - mdio_pins: pinmux_mdio_pins { + mdio_pins: mdio-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; - vout_pins: pinmux_vout_pins { + vout_pins: vout-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ @@ -274,7 +274,7 @@ K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dss >; }; - mcasp2_pins: pinmux_mcasp2_pins { + mcasp2_pins: mcasp2-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index bd84d7f0f2fe2..97be8691faf5e 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -218,14 +218,14 @@ led12 { }; &k2g_pinctrl { - uart0_pins: pinmux_uart0_pins { + uart0_pins: uart0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; - qspi_pins: pinmux_qspi_pins { + qspi_pins: qspi-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */ K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */ @@ -237,7 +237,7 @@ K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0. >; }; - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: mmc1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ @@ -251,21 +251,21 @@ K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ >; }; - user_leds: pinmux_user_leds { + user_leds: user-leds-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad11.gpio0_11 */ K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* gpmc_ad12.gpio0_12 */ @@ -283,7 +283,7 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.g >; }; - emac_pins: pinmux_emac_pins { + emac_pins: emac-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ @@ -300,7 +300,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R >; }; - mdio_pins: pinmux_mdio_pins { + mdio_pins: mdio-pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 421a02bbc9d30..87318ca008b4e 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -116,42 +116,42 @@ k2l_pmx: pinmux@2620690 { pinctrl-single,function-mask = <0x1>; status = "disabled"; - uart3_emifa_pins: pinmux_uart3_emifa_pins { + uart3_emifa_pins: uart3-emifa-pins { pinctrl-single,bits = < /* UART3_EMIFA_SEL */ 0x0 0x0 0xc0 >; }; - uart2_emifa_pins: pinmux_uart2_emifa_pins { + uart2_emifa_pins: uart2-emifa-pins { pinctrl-single,bits = < /* UART2_EMIFA_SEL */ 0x0 0x0 0x30 >; }; - uart01_spi2_pins: pinmux_uart01_spi2_pins { + uart01_spi2_pins: uart01-spi2-pins { pinctrl-single,bits = < /* UART01_SPI2_SEL */ 0x0 0x0 0x4 >; }; - dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ + dfesync_rp1_pins: dfesync-rp1-pins{ pinctrl-single,bits = < /* DFESYNC_RP1_SEL */ 0x0 0x0 0x2 >; }; - avsif_pins: pinmux_avsif_pins { + avsif_pins: avsif-pins { pinctrl-single,bits = < /* AVSIF_SEL */ 0x0 0x0 0x1 >; }; - gpio_emu_pins: pinmux_gpio_emu_pins { + gpio_emu_pins: gpio-emu-pins { pinctrl-single,bits = < /* * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 @@ -174,7 +174,7 @@ gpio_emu_pins: pinmux_gpio_emu_pins { >; }; - gpio_timio_pins: pinmux_gpio_timio_pins { + gpio_timio_pins: gpio-timio-pins { pinctrl-single,bits = < /* * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 @@ -194,7 +194,7 @@ gpio_timio_pins: pinmux_gpio_timio_pins { >; }; - gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { + gpio_spi2cs_pins: gpio-spi2cs-pins { pinctrl-single,bits = < /* * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 @@ -206,7 +206,7 @@ gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { >; }; - gpio_dfeio_pins: pinmux_gpio_dfeio_pins { + gpio_dfeio_pins: gpio-dfeio-pins { pinctrl-single,bits = < /* * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 @@ -230,7 +230,7 @@ gpio_dfeio_pins: pinmux_gpio_dfeio_pins { >; }; - gpio_emifa_pins: pinmux_gpio_emifa_pins { + gpio_emifa_pins: gpio-emifa-pins { pinctrl-single,bits = < /* * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 -- GitLab From 5ae8afd41ea5a1767d0b683ffa8f9ff3d9c7e68c Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 13:35:13 -0500 Subject: [PATCH 606/926] ARM: dts: keystone: Fix EEPROM node names These should follow the standard EEPROM node naming convention. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515183515.509371-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/keystone-k2e-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2hk-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2l-evm.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index abd5aef8b87dc..04e0759a25271 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -78,7 +78,7 @@ &usb1 { }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 1f762af6f5022..206df8a8d9dd7 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -154,7 +154,7 @@ partition@180000 { }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 3a69f65de81ec..8e15a26a3a7e6 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -51,7 +51,7 @@ &usb0 { }; &i2c0 { - dtt@50 { + eeprom@50 { compatible = "atmel,24c1024"; reg = <0x50>; }; -- GitLab From 4b3498372664efe3755255402537e243bc83eb82 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 13:35:14 -0500 Subject: [PATCH 607/926] ARM: dts: keystone: Remove ti,keystone from soc node compatible This is just a "simple-bus" node, there is no need for the extra compatible "ti,keystone" which is unused and undocumented. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515183515.509371-4-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/keystone.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 50789f9e2215f..552ecd546cfdd 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -69,9 +69,9 @@ psci { }; soc0: soc@0 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; interrupt-parent = <&gic>; ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; -- GitLab From 2d62aab57d2ace03d840c08fb323ed1b9bd83a94 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 13:35:15 -0500 Subject: [PATCH 608/926] ARM: dts: keystone: Do not capitalize hex digits Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515183515.509371-5-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/keystone-k2e-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2e-netcp.dtsi | 2 +- arch/arm/boot/dts/keystone-k2g-evm.dts | 12 ++++++------ arch/arm/boot/dts/keystone-k2g-ice.dts | 14 +++++++------- arch/arm/boot/dts/keystone-k2g.dtsi | 6 +++--- arch/arm/boot/dts/keystone-k2l-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2l.dtsi | 10 +++++----- arch/arm/boot/dts/keystone.dtsi | 6 +++--- 8 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 04e0759a25271..6978d6a362f3f 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -130,7 +130,7 @@ partition@100000 { partition@180000 { label = "ubifs"; - reg = <0x180000 0x1FE80000>; + reg = <0x180000 0x1fe80000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index 42cf74db673cc..bff73a0ed10bf 100644 --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi @@ -167,7 +167,7 @@ cpts_refclk_mux: cpts-refclk-mux { <&tsipclka>, <&tsrefclk>, <&tsipclkb>; ti,mux-tbl = <0x0>, <0x1>, <0x2>, - <0x3>, <0x4>, <0x8>, <0xC>; + <0x3>, <0x4>, <0x8>, <0xc>; assigned-clocks = <&cpts_refclk_mux>; assigned-clock-parents = <&chipclk12>; }; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 7527dacb5e012..7bfc80f1af26b 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -218,16 +218,16 @@ K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3. emac_pins: emac-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ >; @@ -235,7 +235,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R mdio_pins: mdio-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; @@ -424,11 +424,11 @@ partition@3 { }; partition@4 { label = "QSPI.kernel"; - reg = <0x001C0000 0x0800000>; + reg = <0x001c0000 0x0800000>; }; partition@5 { label = "QSPI.file-system"; - reg = <0x009C0000 0x3640000>; + reg = <0x009c0000 0x3640000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/keystone-k2g-ice.dts index 97be8691faf5e..6ceb0d5c6388b 100644 --- a/arch/arm/boot/dts/keystone-k2g-ice.dts +++ b/arch/arm/boot/dts/keystone-k2g-ice.dts @@ -239,15 +239,15 @@ K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0. mmc1_pins: mmc1-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ - K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc1_sdcd.gpio0_69 */ K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_sdwp.mmc1_sdwp */ - K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ + K2G_CORE_IOPAD(0x111c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_pow.mmc1_pow */ >; }; @@ -285,16 +285,16 @@ K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* spi2_scsn1.g emac_pins: emac-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ + K2G_CORE_IOPAD(0x113c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */ K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */ K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */ K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */ K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */ K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */ K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */ - K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ + K2G_CORE_IOPAD(0x116c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */ K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */ - K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ + K2G_CORE_IOPAD(0x117c) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */ K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */ >; @@ -302,7 +302,7 @@ K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.R mdio_pins: mdio-pins { pinctrl-single,pins = < - K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ + K2G_CORE_IOPAD(0x118c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 380dd9d637eef..102d59694d903 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -177,7 +177,7 @@ uart2: serial@2531400 { dcan0: can@260b200 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B200 0x200>; + reg = <0x0260b200 0x200>; interrupts = ; status = "disabled"; power-domains = <&k2g_pds 0x0008>; @@ -186,7 +186,7 @@ dcan0: can@260b200 { dcan1: can@260b400 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - reg = <0x0260B400 0x200>; + reg = <0x0260b400 0x200>; interrupts = ; status = "disabled"; power-domains = <&k2g_pds 0x0009>; @@ -593,7 +593,7 @@ spi1: spi@21805800 { spi2: spi@21805c00 { compatible = "ti,keystone-spi"; - reg = <0x21805C00 0x200>; + reg = <0x21805c00 0x200>; num-cs = <4>; ti,davinci-spi-intr-line = <0>; interrupts = ; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 8e15a26a3a7e6..be619e39a16f3 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -103,7 +103,7 @@ partition@100000 { partition@180000 { label = "ubifs"; - reg = <0x180000 0x7FE80000>; + reg = <0x180000 0x7fe80000>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 87318ca008b4e..8949578e62e84 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -170,7 +170,7 @@ gpio_emu_pins: gpio-emu-pins { * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 */ - 0x4 0x0000 0xFFFE0000 + 0x4 0x0000 0xfffe0000 >; }; @@ -190,7 +190,7 @@ gpio_timio_pins: gpio-timio-pins { * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 */ - 0x4 0x0 0xFFF0 + 0x4 0x0 0xfff0 >; }; @@ -202,7 +202,7 @@ gpio_spi2cs_pins: gpio-spi2cs-pins { * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 */ - 0x4 0x0 0xF + 0x4 0x0 0xf >; }; @@ -226,7 +226,7 @@ gpio_dfeio_pins: gpio-dfeio-pins { * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 */ - 0x8 0x0 0xFFFF0000 + 0x8 0x0 0xffff0000 >; }; @@ -250,7 +250,7 @@ gpio_emifa_pins: gpio-emifa-pins { * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 */ - 0x8 0x0 0xFFFF + 0x8 0x0 0xffff >; }; }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 552ecd546cfdd..1fd04bb37a153 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -282,7 +282,7 @@ gpio0: gpio@260bf00 { ti,davinci-gpio-unbanked = <32>; }; - aemif: aemif@21000A00 { + aemif: aemif@21000a00 { compatible = "ti,keystone-aemif", "ti,davinci-aemif"; #address-cells = <2>; #size-cells = <1>; @@ -290,9 +290,9 @@ aemif: aemif@21000A00 { clock-names = "aemif"; clock-ranges; - reg = <0x21000A00 0x00000100>; + reg = <0x21000a00 0x00000100>; ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000A00 0x00000100>; + 1 0 0x21000a00 0x00000100>; }; pcie0: pcie@21800000 { -- GitLab From a325956fa7048906e26a4535ac2e87e111788fe8 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 8 May 2023 11:08:11 -0500 Subject: [PATCH 609/926] arm64: dts: rockchip: Fix compatible for Bluetooth on rk3566-anbernic The realtek Bluetooth module uses the same driver as the realtek,rtl8822cs-bt and the realtek,rtl8723bs-bt, however by selecting the 8723bs advanced power saving features are disabled that appear to interfere with normal operation of the bluetooth module. This change switches the compatible string to disable power saving. Without this patch evtest of a paired bluetooth controller fails, with this patch the controller operates as expected. Fixes: b6986b7920bb ("arm64: dts: rockchip: Update compatible for bluetooth") Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20230508160811.3568213-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index 69f332738d247..a2c31d53b45bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -721,7 +721,7 @@ &uart1 { status = "okay"; bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8822cs-bt"; + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; -- GitLab From e3f2778b1b6ced649bffdc7cbb05b80bb92f2108 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jun 2023 20:01:12 +0200 Subject: [PATCH 610/926] ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2 The audio routing flow is not correct, the flow should be from source (second element in the pair) to sink (first element in the pair). The flow now is from "HP_OUT" to "Playback", where "Playback" is source and "HP_OUT" is sink, i.e. the direction is swapped and there is no direct link between the two either. Fill in the correct routing, where "HP_OUT" supplies the "Headphone Jack", "Line In Jack" supplies "LINE_IN" input, "Microphone Jack" supplies "MIC_IN" input and "Mic Bias" supplies "Microphone Jack". Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 4709677151aac..46b87a27d8b37 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -137,10 +137,13 @@ reg_panel_supply: regulator-panel-supply { sound { compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; + widgets = "Headphone", "Headphone Jack", + "Line", "Line In Jack", + "Microphone", "Microphone Jack"; + routing = "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; dais = <&sai2a_port &sai2b_port>; status = "okay"; }; -- GitLab From 076c74c592cabe4a47537fe5205b5b678bed010d Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Tue, 6 Jun 2023 13:56:04 +0200 Subject: [PATCH 611/926] ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx Use "dai-format" to configure DAI audio format as specified in audio-graph-port.yaml bindings. Fixes: 144d1ba70548 ("ARM: dts: stm32: Adapt STM32MP157 DK boards to stm32 DT diversity") Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index e78ba956b9d0f..511113f2e3992 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -446,7 +446,7 @@ &i2s2 { i2s2_port: port { i2s2_endpoint: endpoint { remote-endpoint = <&sii9022_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; }; }; -- GitLab From ba4aebce23b2affb810b8a60eae853674d2cded2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 5 Jun 2023 15:21:09 +0200 Subject: [PATCH 612/926] ARM: dts: BCM5301X: Describe switch ports in the main DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All Northstar SoCs have BCM5301x switches (BCM53011, BCM53012) with 8 ports (0-8 without 6). By design 3 switch ports (5, 7 and 8) are hardwired to 3 on-SoC Ethernet interfaces. Switch port 8 requires forcing link state. It seems that global Northstar .dtsi file is the best place to describe those hw details. Only device specific bits (like labels) should go to device .dts files. This seems to fit well with a tiny exception of Asus RT-AC88U which somehow was designed to have switch 5 connected to an extra switch. This case was simply handled with a /delete-property/. Signed-off-by: Rafał Miłecki Reviewed-by: Christian Lamparter (MR32+MR26) Link: https://lore.kernel.org/r/20230605132109.7933-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 41 ++++++++++++++++++- .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 7 ---- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 -- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 -- arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 7 ---- arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 7 ---- .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 7 ---- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 -- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 7 ---- arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 12 ------ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 17 +------- arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 12 ------ arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 12 ------ .../boot/dts/bcm47094-linksys-panamera.dts | 34 ++++----------- arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 7 ---- arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 4 -- arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 7 ---- arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 -- arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 7 ---- .../boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 7 ---- arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 3 -- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 3 -- 22 files changed, 51 insertions(+), 163 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index d9455b33adeea..53472d376a2c0 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -304,10 +304,49 @@ srab: ethernet-switch@18007000 { status = "disabled"; - /* ports are defined in board DTS */ ports { #address-cells = <1>; #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + ethernet = <&gmac0>; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi index 0846887ba144d..42bcbf10957c4 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -159,34 +159,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 5d0549855978d..e04d2e5ea51aa 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -75,19 +75,15 @@ &srab { ports { port@0 { - reg = <0>; label = "poe"; }; port@4 { - reg = <4>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 4ca348c06b51f..a399800139d9c 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -82,14 +82,11 @@ &srab { ports { port@4 { - reg = <4>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 8661ec94ca672..fad3473810a2e 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -100,34 +100,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 26cdeb5cc3377..5b2b7b8b3b123 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -123,34 +123,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index a2b7644eaf393..d0a26b643b82f 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -123,34 +123,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 7e042928fd40e..9f21d6d6d35b7 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -75,14 +75,11 @@ &srab { ports { port@4 { - reg = <4>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 231d437408d8b..2561072917021 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -124,36 +124,29 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; nvmem-cells = <&et0macaddr 5>; nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index 14303ab521ea4..dae3c7d2f0466 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -191,39 +191,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index a50ff686b557e..4d5747aa5dc82 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -181,32 +181,28 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; sw0_p5: port@5 { - reg = <5>; + /delete-property/ethernet; + label = "extsw"; phy-mode = "rgmii"; @@ -218,8 +214,6 @@ fixed-link { }; port@7 { - reg = <7>; - ethernet = <&gmac1>; label = "cpu"; fixed-link { @@ -229,14 +223,7 @@ fixed-link { }; port@8 { - reg = <8>; - ethernet = <&gmac2>; label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 555fbe41dd8fe..51ce510b3e3a0 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -124,39 +124,27 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts index d945a20b06e07..60744f82c2b71 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts @@ -172,40 +172,28 @@ &srab { ports { port@0 { - reg = <0>; label = "lan1"; }; port@1 { - reg = <1>; label = "lan2"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan4"; }; port@4 { - reg = <4>; label = "wan"; }; port@8 { - reg = <8>; label = "cpu"; - ethernet = <&gmac2>; phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index d9a16a820e7f9..8036c04d81cbf 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -207,29 +207,32 @@ &srab { dsa,member = <0 0>; ports { + sw0_p0: port@0 { + label = "extsw"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@1 { - reg = <1>; label = "lan7"; }; port@2 { - reg = <2>; label = "lan4"; }; port@3 { - reg = <3>; label = "lan8"; }; port@4 { - reg = <4>; label = "wan"; }; port@5 { - reg = <5>; - ethernet = <&gmac0>; label = "cpu"; status = "disabled"; @@ -240,8 +243,6 @@ fixed-link { }; port@7 { - reg = <7>; - ethernet = <&gmac1>; label = "cpu"; status = "disabled"; @@ -252,24 +253,7 @@ fixed-link { }; port@8 { - reg = <8>; - ethernet = <&gmac2>; label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sw0_p0: port@0 { - reg = <0>; - label = "extsw"; - - fixed-link { - speed = <1000>; - full-duplex; - }; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index ae55238708542..e8991d4e248ce 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -83,36 +83,29 @@ &srab { ports { port@0 { - reg = <0>; label = "wan"; nvmem-cells = <&et0macaddr 1>; nvmem-cell-names = "mac-address"; }; port@1 { - reg = <1>; label = "lan4"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan2"; }; port@4 { - reg = <4>; label = "lan1"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 9220f193499e7..6875625869d9c 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -73,19 +73,15 @@ &srab { ports { port@0 { - reg = <0>; label = "poe"; }; port@1 { - reg = <1>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 2bd64dcd43535..7cfa4607ef311 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -83,36 +83,29 @@ &srab { ports { port@0 { - reg = <0>; label = "wan"; nvmem-cells = <&et0macaddr 1>; nvmem-cell-names = "mac-address"; }; port@1 { - reg = <1>; label = "lan4"; }; port@2 { - reg = <2>; label = "lan3"; }; port@3 { - reg = <3>; label = "lan2"; }; port@4 { - reg = <4>; label = "lan1"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 8a6d19f985c13..d55e10095eae7 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -69,14 +69,11 @@ &srab { ports { port@0 { - reg = <0>; label = "lan"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index 52783a4b6f999..ccf031c0e276d 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -123,36 +123,29 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; nvmem-cells = <&et0macaddr 5>; nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 2dd05f4dce92a..789dd2a3d2263 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -98,36 +98,29 @@ &srab { ports { port@0 { - reg = <0>; label = "lan4"; }; port@1 { - reg = <1>; label = "lan3"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan1"; }; port@4 { - reg = <4>; label = "wan"; nvmem-cells = <&et0macaddr 5>; nvmem-cell-names = "mac-address"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts index 071f2cb97251a..24ba467c67b91 100644 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -115,14 +115,11 @@ &srab { ports { port@0 { - reg = <0>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; fixed-link { speed = <1000>; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 46c2c93b01d88..559d6c371d67a 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -176,14 +176,11 @@ &srab { ports { port@0 { - reg = <0>; label = "poe"; }; port@5 { - reg = <5>; label = "cpu"; - ethernet = <&gmac0>; fixed-link { speed = <1000>; -- GitLab From 9038af901654a9e31e3bcbc4ebcec5d109b87059 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Fri, 26 May 2023 21:28:45 +0200 Subject: [PATCH 613/926] ARM: dts: bcm-mobile: change "" includes to <> where applicable While at it, also sort the includes alphabetically. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/04aa10d644eb183f6c0c5b944e527e36d56e2110.1685127525.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm11351.dtsi | 3 +-- arch/arm/boot/dts/bcm21664.dtsi | 3 +-- arch/arm/boot/dts/bcm23550.dtsi | 5 ++--- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index c30ff1b02e037..f395e95e0177e 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -1,11 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2012-2013 Broadcom Corporation +#include #include #include -#include "dt-bindings/clock/bcm281xx.h" - / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 4e96656dc36a9..2a426125f9fee 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -1,11 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2014 Broadcom Corporation +#include #include #include -#include "dt-bindings/clock/bcm21664.h" - / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index e1a5f1b40ef5e..424c818d7a1b4 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -30,12 +30,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* BCM23550 and BCM21664 have almost identical clocks */ +#include #include #include -/* BCM23550 and BCM21664 have almost identical clocks */ -#include "dt-bindings/clock/bcm21664.h" - / { #address-cells = <1>; #size-cells = <1>; -- GitLab From 2e167b34c0b5e7fba5ee531fa190be427adc1aa5 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Fri, 26 May 2023 21:29:21 +0200 Subject: [PATCH 614/926] ARM: dts: bcm21664/23550: use CCU compatibles directly BCM21664 and BCM23550 DTs for some reason use constants from a header file for their CCU node compatibles. Change these to use the strings directly. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/65c54bd4076d646623d2a2f518631435522dc628.1685127525.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm21664.dtsi | 8 ++++---- arch/arm/boot/dts/bcm23550.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 2a426125f9fee..19ade84e42c14 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -285,21 +285,21 @@ var_156m_clk: var_156m { }; root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; + compatible = "brcm,bcm21664-root-ccu"; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; + compatible = "brcm,bcm21664-aon-ccu"; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; + compatible = "brcm,bcm21664-master-ccu"; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; clock-output-names = "sdio1", @@ -313,7 +313,7 @@ master_ccu: master_ccu@3f001000 { }; slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + compatible = "brcm,bcm21664-slave-ccu"; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; clock-output-names = "uartb", diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index 424c818d7a1b4..ed3ce2fabca60 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -371,21 +371,21 @@ var_156m_clk: var_156m { }; root_ccu: root_ccu@35001000 { - compatible = BCM21664_DT_ROOT_CCU_COMPAT; + compatible = "brcm,bcm21664-root-ccu"; reg = <0x35001000 0x0f00>; #clock-cells = <1>; clock-output-names = "frac_1m"; }; aon_ccu: aon_ccu@35002000 { - compatible = BCM21664_DT_AON_CCU_COMPAT; + compatible = "brcm,bcm21664-aon-ccu"; reg = <0x35002000 0x0f00>; #clock-cells = <1>; clock-output-names = "hub_timer"; }; slave_ccu: slave_ccu@3e011000 { - compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + compatible = "brcm,bcm21664-slave-ccu"; reg = <0x3e011000 0x0f00>; #clock-cells = <1>; clock-output-names = "uartb", @@ -398,7 +398,7 @@ slave_ccu: slave_ccu@3e011000 { }; master_ccu: master_ccu@3f001000 { - compatible = BCM21664_DT_MASTER_CCU_COMPAT; + compatible = "brcm,bcm21664-master-ccu"; reg = <0x3f001000 0x0f00>; #clock-cells = <1>; clock-output-names = "sdio1", -- GitLab From 517025689e1b79e0a476c1dbf91a4e9637d235a8 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Fri, 26 May 2023 21:29:47 +0200 Subject: [PATCH 615/926] ARM: dts: bcm-mobile: move status properties to the end of nodes Move some DT "status" properties so that they're the last specified property (before sub-nodes). Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/d7060071cb1f4b36b06b6507a09b32c7751ca7f0.1685127525.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm11351.dtsi | 8 ++++---- arch/arm/boot/dts/bcm21664.dtsi | 6 +++--- arch/arm/boot/dts/bcm23550.dtsi | 6 +++--- arch/arm/boot/dts/bcm28155-ap.dts | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index f395e95e0177e..773d717de7f0c 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -51,42 +51,42 @@ smc@3404c000 { serial@3e000000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e000000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; serial@3e001000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e001000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; serial@3e002000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e002000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; serial@3e003000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e003000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; L2: l2-cache@3ff20000 { diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 19ade84e42c14..9e3835a0a7efd 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -51,32 +51,32 @@ smc@3404e000 { serial@3e000000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e000000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; serial@3e001000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e001000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; serial@3e002000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; - status = "disabled"; reg = <0x3e002000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; L2: cache-controller@3ff20000 { diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi index ed3ce2fabca60..445eadb8d871f 100644 --- a/arch/arm/boot/dts/bcm23550.dtsi +++ b/arch/arm/boot/dts/bcm23550.dtsi @@ -129,32 +129,32 @@ slaves@3e000000 { uartb: serial@0 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00000000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uartb2: serial@1000 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00001000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; uartb3: serial@2000 { compatible = "snps,dw-apb-uart"; - status = "disabled"; reg = <0x00002000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; + status = "disabled"; }; bsc1: i2c@16000 { diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index c496e33a71a61..0a8ad1d673d85 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -21,23 +21,23 @@ serial@3e000000 { }; i2c@3e016000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3e017000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3e018000 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; }; i2c@3500d000 { - status = "okay"; clock-frequency = <100000>; + status = "okay"; pmu: pmu@8 { reg = <0x08>; -- GitLab From f13e52ae0f1071c34e9cc24f9c0b0218f95f8aad Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Fri, 26 May 2023 21:30:08 +0200 Subject: [PATCH 616/926] ARM: dts: bcm11351/21664: add UART, I2C node labels Add node labels to serial (UART) and I2C nodes for BCM11351 and BCM21664. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/4c8bb3a725dad9048665d39d0ca728b52152e59e.1685127525.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm11351.dtsi | 16 ++++++++-------- arch/arm/boot/dts/bcm21664.dtsi | 14 +++++++------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 773d717de7f0c..b271a9bf06a9a 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -49,7 +49,7 @@ smc@3404c000 { reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; - serial@3e000000 { + uartb: serial@3e000000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e000000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; @@ -59,7 +59,7 @@ serial@3e000000 { status = "disabled"; }; - serial@3e001000 { + uartb2: serial@3e001000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e001000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; @@ -69,7 +69,7 @@ serial@3e001000 { status = "disabled"; }; - serial@3e002000 { + uartb3: serial@3e002000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e002000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; @@ -79,7 +79,7 @@ serial@3e002000 { status = "disabled"; }; - serial@3e003000 { + uartb4: serial@3e003000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e003000 0x1000>; clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; @@ -161,7 +161,7 @@ pinctrl@35004800 { reg = <0x35004800 0x430>; }; - i2c@3e016000 { + bsc1: i2c@3e016000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e016000 0x80>; interrupts = ; @@ -171,7 +171,7 @@ i2c@3e016000 { status = "disabled"; }; - i2c@3e017000 { + bsc2: i2c@3e017000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e017000 0x80>; interrupts = ; @@ -181,7 +181,7 @@ i2c@3e017000 { status = "disabled"; }; - i2c@3e018000 { + bsc3: i2c@3e018000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3e018000 0x80>; interrupts = ; @@ -191,7 +191,7 @@ i2c@3e018000 { status = "disabled"; }; - i2c@3500d000 { + pmu_bsc: i2c@3500d000 { compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; reg = <0x3500d000 0x80>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 9e3835a0a7efd..2eb7f5b0c1dc5 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -49,7 +49,7 @@ smc@3404e000 { reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ }; - serial@3e000000 { + uartb: serial@3e000000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e000000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; @@ -59,7 +59,7 @@ serial@3e000000 { status = "disabled"; }; - serial@3e001000 { + uartb2: serial@3e001000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e001000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; @@ -69,7 +69,7 @@ serial@3e001000 { status = "disabled"; }; - serial@3e002000 { + uartb3: serial@3e002000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; reg = <0x3e002000 0x118>; clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; @@ -144,7 +144,7 @@ sdio4: mmc@3f1b0000 { status = "disabled"; }; - i2c@3e016000 { + bsc1: i2c@3e016000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e016000 0x70>; interrupts = ; @@ -154,7 +154,7 @@ i2c@3e016000 { status = "disabled"; }; - i2c@3e017000 { + bsc2: i2c@3e017000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e017000 0x70>; interrupts = ; @@ -164,7 +164,7 @@ i2c@3e017000 { status = "disabled"; }; - i2c@3e018000 { + bsc3: i2c@3e018000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e018000 0x70>; interrupts = ; @@ -174,7 +174,7 @@ i2c@3e018000 { status = "disabled"; }; - i2c@3e01c000 { + bsc4: i2c@3e01c000 { compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; reg = <0x3e01c000 0x70>; interrupts = ; -- GitLab From 9ad7f375e9dc7efdb8d9803cd01a78fbe70968b3 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Fri, 26 May 2023 21:30:30 +0200 Subject: [PATCH 617/926] ARM: dts: bcm21664-garnet: use node labels Use node labels instead of nodename@address for BCM21664 Garnet to simplify its DTS file. Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/e9f1ac2e9aa0ef7e880b1c152cbd56ff6b151955.1685127525.git.stano.jakubek@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm21664-garnet.dts | 46 +++++++++++++-------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index dead91d97b632..8789fae178bf8 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -15,33 +15,33 @@ memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; +}; - serial@3e000000 { - status = "okay"; - }; +&sdio1 { + max-frequency = <48000000>; + status = "okay"; +}; - sdio1: mmc@3f180000 { - max-frequency = <48000000>; - status = "okay"; - }; +&sdio2 { + non-removable; + max-frequency = <48000000>; + status = "okay"; +}; - sdio2: mmc@3f190000 { - non-removable; - max-frequency = <48000000>; - status = "okay"; - }; +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; - sdio4: mmc@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>; - status = "okay"; - }; +&uartb { + status = "okay"; +}; - usbotg: usb@3f120000 { - status = "okay"; - }; +&usbotg { + status = "okay"; +}; - usbphy: usb-phy@3f130000 { - status = "okay"; - }; +&usbphy { + status = "okay"; }; -- GitLab From 7121458ec0e140feb95e9e65a9a4971cbd063c00 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sat, 27 May 2023 16:12:22 +0200 Subject: [PATCH 618/926] dt-bindings: power: reset: bcm21664-resetmgr: convert to YAML Convert Broadcom Kona family reset manager bindings to DT schema. Signed-off-by: Stanislav Jakubek Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230527141222.GA5048@standask-GA-A55M-S2HP Signed-off-by: Florian Fainelli --- .../power/reset/brcm,bcm21664-resetmgr.txt | 14 --------- .../power/reset/brcm,bcm21664-resetmgr.yaml | 31 +++++++++++++++++++ 2 files changed, 31 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt create mode 100644 Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt deleted file mode 100644 index 93f31ca1ef4b3..0000000000000 --- a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.txt +++ /dev/null @@ -1,14 +0,0 @@ -Broadcom Kona Family Reset Manager ----------------------------------- - -The reset manager is used on the Broadcom BCM21664 SoC. - -Required properties: - - compatible: brcm,bcm21664-resetmgr - - reg: memory address & range - -Example: - brcm,resetmgr@35001f00 { - compatible = "brcm,bcm21664-resetmgr"; - reg = <0x35001f00 0x24>; - }; diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml new file mode 100644 index 0000000000000..3e28a59d718fc --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/brcm,bcm21664-resetmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona family reset manager + +maintainers: + - Florian Fainelli + +properties: + compatible: + const: brcm,bcm21664-resetmgr + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + reset-controller@35001f00 { + compatible = "brcm,bcm21664-resetmgr"; + reg = <0x35001f00 0x24>; + }; +... -- GitLab From a6a1a156f5debaebf9f61850d111b966e9be9ee9 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 8 Jun 2023 17:36:27 +0200 Subject: [PATCH 619/926] ARM: dts: BCM5301X: MR26: MR32: remove bogus nand-ecc-algo property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit | bcm53015-meraki-mr26.dtb: nand-controller@18028000: | nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs'] | From schema: Documentation/[...]/nand-controller.yaml | bcm53016-meraki-mr32.dtb: nand-controller@18028000: | nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs'] | From schema: Documentation/[...]/nand-controller.yaml original ECC values for these old Merakis are sadly not provided by the vendor. It looks like Meraki just stuck with what Broadcom's SDK was doing... which left this up to the proprietary nand driver. Note: The invalid setting was and is handled by brcmnand. It falls back to "bch" in brcmnand_setup_dev() when ecc.algo is set to NAND_ECC_ALGO_UNKNOWN (since "hw" is not in the list above). A correct nand-ecc-algo = "bch"; is already specified in the included "bcm5301x-nand-cs0-bch8.dtsi". So this line can be dropped. Reported-by: Rafał Miłecki (per Mail) Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26") Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32") Signed-off-by: Christian Lamparter Link: https://lore.kernel.org/r/2c4d00dd40124c2ddc0b139cbce7531b108f9052.1686238550.git.chunkeey@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 -- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts index 24ba467c67b91..c36d3231183bd 100644 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -72,8 +72,6 @@ &gmac3 { }; &nandcs { - nand-ecc-algo = "hw"; - partitions { compatible = "fixed-partitions"; #address-cells = <0x1>; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 559d6c371d67a..e6156fa5cb3db 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -125,8 +125,6 @@ &pwm { }; &nandcs { - nand-ecc-algo = "hw"; - partitions { /* * The partition autodetection does not work for this device. -- GitLab From d68b2f7d7d06872450d4f39d84d5926d7e7ae88c Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 8 Jun 2023 17:36:28 +0200 Subject: [PATCH 620/926] ARM: dts: BCM5301X: MR32: remove partition index numbers removes the partition indexes in the node names under. This brings the device tree source in line with others. Signed-off-by: Christian Lamparter Link: https://lore.kernel.org/r/627f57d568030a56499361790524b4d4f3381619.1686238550.git.chunkeey@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index e6156fa5cb3db..258f6dc4f5dc2 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -138,31 +138,31 @@ partitions { #address-cells = <0x1>; #size-cells = <0x1>; - partition0@0 { + partition@0 { label = "u-boot"; reg = <0x0 0x100000>; read-only; }; - partition1@100000 { + partition@100000 { label = "bootkernel1"; reg = <0x100000 0x300000>; read-only; }; - partition2@400000 { + partition@400000 { label = "nvram"; reg = <0x400000 0x100000>; read-only; }; - partition3@500000 { + partition@500000 { label = "bootkernel2"; reg = <0x500000 0x300000>; read-only; }; - partition4@800000 { + partition@800000 { label = "ubi"; reg = <0x800000 0x7780000>; }; -- GitLab From fd274b733bfdde3ca72f0fa2a37f032f3a8c402c Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Thu, 8 Jun 2023 17:36:29 +0200 Subject: [PATCH 621/926] ARM: dts: BCM5301X: fix duplex-full => full-duplex this typo was found by the dtbs_check | ports:port@5:fixed-link: 'oneOf' conditional failed, | {'speed': [[1000]], 'duplex-full': True} is not of type 'array' | 'duplex-full' does not match any of the regexes: 'pinctrl-[0-]..." this should have been full-duplex; Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26") Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32") Signed-off-by: Christian Lamparter Link: https://lore.kernel.org/r/50522f45566951a9eabd22820647924cc6b4a264.1686238550.git.chunkeey@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 +- arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts index c36d3231183bd..03ad614e6b721 100644 --- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts @@ -121,7 +121,7 @@ port@5 { fixed-link { speed = <1000>; - duplex-full; + full-duplex; }; }; }; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index 258f6dc4f5dc2..26c12bfb0bdd4 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -182,7 +182,7 @@ port@5 { fixed-link { speed = <1000>; - duplex-full; + full-duplex; }; }; }; -- GitLab From 3efb0f179e7f935bcba61f8a71292b12332da9c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 15:59:23 +0200 Subject: [PATCH 622/926] dt-bindings: net: wireless: brcm,bcm4329-fmac: add BCM4366 binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's an 802.11ac chipset that can be found hardwired in a lot of Northstar based routers. Signed-off-by: Rafał Miłecki Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230602135925.14143-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- .../devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index fec1cc9b9a085..527f055a66830 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -38,6 +38,7 @@ properties: - brcm,bcm4354-fmac - brcm,bcm4356-fmac - brcm,bcm4359-fmac + - brcm,bcm4366-fmac - cypress,cyw4373-fmac - cypress,cyw43012-fmac - const: brcm,bcm4329-fmac -- GitLab From 156d2a64e0176863cb2b0df1f014cda1ab0393d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 15:59:24 +0200 Subject: [PATCH 623/926] dt-bindings: net: wireless: brcm,bcm4329-fmac: allow generic properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include ieee80211.yaml to allow using generic 802.11 properties for bindings of Broadcom FullMAC devices. That allows specifying frequencies ranges. Signed-off-by: Rafał Miłecki Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230602135925.14143-2-zajec5@gmail.com Signed-off-by: Florian Fainelli --- .../devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index 527f055a66830..4aa521f1be8cd 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -15,6 +15,9 @@ description: These chips also have a Bluetooth portion described in a separate binding. +allOf: + - $ref: ieee80211.yaml# + properties: compatible: oneOf: @@ -121,7 +124,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | -- GitLab From 752a63b8dbe6cc6900efd1035bea427a778a4b55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Jun 2023 15:59:25 +0200 Subject: [PATCH 624/926] ARM: dts: BCM5301X: Add Netgear R8000 WiFi regulator mappings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows setting FullMAC firmware regulatory domain. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230602135925.14143-3-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index dae3c7d2f0466..707c561703ed8 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -137,8 +137,10 @@ bridge@0,0,0 { #size-cells = <2>; wifi@0,1,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5735000 5835000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; }; @@ -159,6 +161,19 @@ bridge@1,1,0 { #address-cells = <3>; #size-cells = <2>; + bridge@1,0 { + reg = <0x800 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; + }; + }; + bridge@1,2,2 { reg = <0x1000 0 0 0 0>; @@ -166,8 +181,10 @@ bridge@1,2,2 { #size-cells = <2>; wifi@1,4,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5170000 5730000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; }; -- GitLab From 02310be6f080071e1b9e2021fd6dd655bd842aad Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Mon, 15 May 2023 17:32:37 +0800 Subject: [PATCH 625/926] arm64: dts: add support for C3 based Amlogic AW409 Amlogic C3 is an advanced edge AI processor designed for smart IP camera applications. Add basic support for the C3 based Amlogic AW409 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20230515093237.2203171-1-xianwei.zhao@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/amlogic-c3-c302x-aw409.dts | 29 +++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 87 +++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index cd1c5b04890a3..6f61798a109f4 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts new file mode 100644 index 0000000000000..edce8850b3386 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model = "Amlogic C302 aw409 Development Board"; + compatible = "amlogic,aw409", "amlogic,c3"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x10000000>; + }; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 0000000000000..60ad4f3eef9d7 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + }; + }; +}; -- GitLab From a6af62dd0ddfcc366f371762fa9dca9d8dbb4993 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 18 Apr 2023 18:29:10 +0800 Subject: [PATCH 626/926] arm64: dts: imx93: add ddr performance monitor node Add performance monitor. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 3b8043c12856e..8643612ace8c7 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -857,5 +857,11 @@ media_blk_ctrl: system-controller@4ac10000 { #power-domain-cells = <1>; status = "disabled"; }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = ; + }; }; }; -- GitLab From 71c2ac9a2a3da9ba986d3f9e6aa1ffdb04bc5b25 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 15 May 2023 11:01:49 -0400 Subject: [PATCH 627/926] arm64: dts: imx8mp: Add coresight trace components MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add coresight trace components (ETM, ETF, ETB and Funnel). ┌───────┐ ┌───────┐ ┌───────┐ │ CPU0 ├─►│ ETM0 ├─►│ │ └───────┘ └───────┘ │ │ │ │ ┌───────┐ ┌───────┐ │ ATP │ │ CPU1 ├─►│ ETM1 ├─►│ │ └───────┘ └───────┘ │ │ │ FUNNEL│ ┌───────┐ ┌───────┐ │ │ │ CPU2 ├─►│ ETM2 ├─►│ │ └───────┘ └───────┘ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ ┌───────┐ ┌───────┐ │ │ │ M7 │ │ DSP │ │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ │ │ └───────┘ └───────┘ └───┬───┘ └──┬──┘ └──┬──┘ AXI │ │ │ ▲ ▼ ▼ ▼ │ ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐ │ ATP FUNNEL ├──►│ETF ├─► │ETR │ └───────────────────────────┘ └─────┘ └────┘ Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 204 ++++++++++++++++++++++ 1 file changed, 204 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index dbd97a7193381..f645a09fd3615 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -304,6 +304,210 @@ soc: soc@0 { nvmem-cells = <&imx8mp_uid>; nvmem-cell-names = "soc_unique_id"; + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28440000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_0>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28540000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_1>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28640000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_2>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28740000 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A53_3>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x28c03000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + + hugo_funnel_in_port1: endpoint { + /* M7 input */ + }; + }; + + port@2 { + reg = <2>; + + hugo_funnel_in_port2: endpoint { + /* DSP input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c04000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c06000 0x1000>; + clocks = <&clk IMX8MP_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; -- GitLab From c79d80960349c4ec5918f581168a263e88e6190a Mon Sep 17 00:00:00 2001 From: Nicolas Cavallari Date: Mon, 5 Jun 2023 11:04:42 +0200 Subject: [PATCH 628/926] arm64: dts: imx8mm-venice: Fix GSC vdd_bat data size. On these boards, vdd_bat is 16bit, not 24bit. Reading them as 24bit values yield garbage values because of the additional byte, which is a configurable fan trippoint[1]. So set their mode to mode_voltage_16bit = 3 instead of mode_voltage_24bit = 1. [1]: http://trac.gateworks.com/wiki/gsc#SystemTemperatureandVoltageMonitor Only tested on GW7100. Signed-off-by: Nicolas Cavallari Acked-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 72cf250d9b4f9..de7f67a4ff2a7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -149,7 +149,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index df3b2c93d2d58..0ec2ce3dd7218 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -354,7 +354,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index c33ec6826d324..03cd29063312f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -327,7 +327,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 363020a08c9b8..6f26914602c88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -293,7 +293,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 7c12518dbc963..2ddba4213001b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -325,7 +325,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index eb51d648359be..92514b71b5f4a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -281,7 +281,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; -- GitLab From 16c984524862d57c456d090ab835e0085c47d579 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 2 Jun 2023 21:10:13 +0200 Subject: [PATCH 629/926] arm64: dts: imx8mp: don't initialize audio clocks from CCM node The audio clocks should be intitialized to the correct rate by the subsystem using them. There is no need to always initialize them from the CCM node assigned-clocks property. This way boards using the audio clocks in a non- standard way can change them without first duplicating the CCM clock setup. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f645a09fd3615..274c088db9810 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -738,26 +738,16 @@ clk: clock-controller@30380000 { <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, <&clk IMX8MP_CLK_NOC_IO>, - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_CLK_GIC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL2_500M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; + <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <0>, <0>, <1000000000>, <800000000>, - <500000000>, - <400000000>, - <800000000>, - <393216000>, - <361267200>; + <500000000>; }; src: reset-controller@30390000 { -- GitLab From 02208f0e600a6555254133fd7ca8a863ecfa7bcd Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 6 Jun 2023 17:09:17 +0200 Subject: [PATCH 630/926] arm64: dts: imx8mq: Fix lcdif compatible "fsl,imx8mq-lcdif" is compatible to "fsl,imx6sx-lcdif", adjust the list accordingly. Fixes the dtbs_check warning: imx8mq-tqma8mq-mba8mx.dtb: lcd-controller@30320000: compatible: 'oneOf' conditional failed, one must be fixed: ['fsl,imx8mq-lcdif', 'fsl,imx28-lcdif'] is too long 'fsl,imx8mq-lcdif' is not one of ['fsl,imx23-lcdif', 'fsl,imx28-lcdif', 'fsl,imx6sx-lcdif', 'fsl,imx8mp-lcdif', 'fsl,imx93-lcdif'] 'fsl,imx6sx-lcdif' was expected Signed-off-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0492556a10dbc..ad5aa4155d23f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -547,7 +547,7 @@ sdma2: dma-controller@302c0000 { }; lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; reg = <0x30320000 0x10000>; interrupts = ; clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; -- GitLab From edcaf194db96eda0db59cf813be07d619fb9596d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 6 Jun 2023 17:09:18 +0200 Subject: [PATCH 631/926] arm64: dts: imx8mq: Fix lcdif clocks Add display APB and AXI clocks as required by bindings. This fixes the warnings: lcd-controller@30320000: clocks: [[2, 128]] is too short From schema: Documentation/devicetree/bindings/display/fsl,lcdif.yaml lcd-controller@30320000: clock-names: ['pix'] is too short From schema: Documentation/devicetree/bindings/display/fsl,lcdif.yaml Signed-off-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index ad5aa4155d23f..7e17a474198da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -550,8 +550,10 @@ lcdif: lcd-controller@30320000 { compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; reg = <0x30320000 0x10000>; interrupts = ; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; + clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, + <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>, -- GitLab From 940587e7737d56173321926d4d3d9daf332e0a6a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 6 Jun 2023 17:09:19 +0200 Subject: [PATCH 632/926] arm64: dts: imx8mq: Add missing pci property Add the required bus-range property to PCI RC node. Fixes the warning: pcie@33c00000: 'bus-range' is a required property From schema: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml Signed-off-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 7e17a474198da..1bf40c0c77071 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1579,6 +1579,7 @@ pcie1: pcie@33c00000 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; -- GitLab From 6c0160aa6ecdbad091c6ef9da507511b3d06eaaa Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 6 Jun 2023 17:10:48 +0200 Subject: [PATCH 633/926] arm64: dts: imx8mq-tqma8mq-mba8mx: Remove invalid properties They originated from the downstream kernel and slipped into mainline. Remove them to silence also dtbs_check warnings: pcie@33800000: Unevaluated properties are not allowed ('epdev_on-supply', 'hard-wired' were unexpected) pcie@33c00000: Unevaluated properties are not allowed ('epdev_on-supply', 'hard-wired' were unexpected) Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index c5244b608524d..afb3ceb067517 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -108,8 +108,6 @@ &pcie0 { <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; - epdev_on-supply = <®_vcc_3v3>; - hard-wired = <1>; status = "okay"; }; @@ -122,8 +120,6 @@ &pcie1 { <&pcie1_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; - epdev_on-supply = <®_vcc_3v3>; - hard-wired = <1>; status = "okay"; }; -- GitLab From 2e21f19fc510412b20665a7797e0fb918ff3cd13 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 7 Jun 2023 08:36:02 -0700 Subject: [PATCH 634/926] arm64: dts: imx8mp-venice-gw702x: fix GSC vdd_bat data size On this board, vdd_bat is 16bit, not 24bit. Set the mode to mode_voltage_16bit (3) instead of mode_voltage_24bit (1). Fixes: 0d5b288c2110 ("arm64: dts: freescale: Add imx8mp-venice-gw7905-2x") Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi index 74b0fda235edd..560c68e4da6dc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi @@ -138,7 +138,7 @@ channel@6 { }; channel@8 { - gw,mode = <1>; + gw,mode = <3>; reg = <0x08>; label = "vdd_bat"; }; -- GitLab From f847a3a8c68fe048d77485690af8c2a86d32763e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 10 Feb 2023 21:25:01 +0300 Subject: [PATCH 635/926] arm: dts: mt7623: add gmacs to mt7623.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are two gigabit MACs on the MT7623AI and MT7623NI SoCs. Add them to mt7623.dtsi and adjust the DTs that call mt7623.dtsi. Now that there are labels for the MACs, remove them from under ð on the DTs that call mt7623.dtsi. Remove the unnecessary mdio label from Bananapi BPI-R2. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230210182505.24597-2-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 12 +++++++ arch/arm/boot/dts/mt7623a-rfb-emmc.dts | 21 ++++++------ arch/arm/boot/dts/mt7623a-rfb-nand.dts | 21 ++++++------ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 23 +++++++------ arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 32 +++++++++---------- 5 files changed, 58 insertions(+), 51 deletions(-) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 11379c3e6b4ca..f0b4a09004b31 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -980,6 +980,18 @@ eth: ethernet@1b100000 { #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + status = "disabled"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; }; crypto: crypto@1b240000 { diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts index e8b4b6d30d197..a64d68b6e1659 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts @@ -112,20 +112,19 @@ &crypto { status = "okay"; }; -ð { +&gmac0 { status = "okay"; + phy-mode = "trgmii"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; + fixed-link { + speed = <1000>; + full-duplex; + pause; }; +}; + +ð { + status = "okay"; mdio-bus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts index 61f5da68d4b0c..fac3ca0322c8d 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts @@ -116,20 +116,19 @@ &crypto { status = "okay"; }; -ð { +&gmac0 { status = "okay"; + phy-mode = "trgmii"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; + fixed-link { + speed = <1000>; + full-duplex; + pause; }; +}; + +ð { + status = "okay"; mdio-bus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index ece61a6a7a897..8ae9a99f9e6d5 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -171,22 +171,21 @@ dpi0_out: endpoint { }; }; -ð { +&gmac0 { status = "okay"; + phy-mode = "trgmii"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; + fixed-link { + speed = <1000>; + full-duplex; + pause; }; +}; + +ð { + status = "okay"; - mdio: mdio-bus { + mdio-bus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index bf67a8e9be59c..5e328c2a6a6e3 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -156,27 +156,25 @@ dpi0_out: endpoint { }; }; -ð { +&gmac0 { status = "okay"; + phy-mode = "trgmii"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; + fixed-link { + speed = <1000>; + full-duplex; + pause; }; +}; - mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy5>; +}; + +ð { + status = "okay"; mdio-bus { #address-cells = <1>; -- GitLab From e5240c35fa75c44d36b3a361a6f8d5685fde269e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 10 Feb 2023 21:25:02 +0300 Subject: [PATCH 636/926] arm: dts: mt7623: add mt7530 switch to mt7623a.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MT7530 switch is included as a part of the multi-chip module on the MT7623AI SoC. Add it to mt7623a.dtsi and adjust DTs that call mt7623a.dtsi. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230210182505.24597-3-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623a-rfb-emmc.dts | 87 +++++++------------------- arch/arm/boot/dts/mt7623a-rfb-nand.dts | 87 +++++++------------------- arch/arm/boot/dts/mt7623a.dtsi | 74 ++++++++++++++++++++++ 3 files changed, 118 insertions(+), 130 deletions(-) diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts index a64d68b6e1659..5654284bab018 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts @@ -112,74 +112,31 @@ &crypto { status = "okay"; }; -&gmac0 { - status = "okay"; - phy-mode = "trgmii"; +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; + }; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; + port@1 { + status = "okay"; + label = "lan1"; + }; -ð { - status = "okay"; + port@2 { + status = "okay"; + label = "lan2"; + }; + + port@3 { + status = "okay"; + label = "lan3"; + }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; + port@4 { + status = "okay"; + label = "wan"; }; }; }; diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mt7623a-rfb-nand.dts index fac3ca0322c8d..afd177b3b5165 100644 --- a/arch/arm/boot/dts/mt7623a-rfb-nand.dts +++ b/arch/arm/boot/dts/mt7623a-rfb-nand.dts @@ -116,74 +116,31 @@ &crypto { status = "okay"; }; -&gmac0 { - status = "okay"; - phy-mode = "trgmii"; +&switch0 { + ports { + port@0 { + status = "okay"; + label = "lan0"; + }; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; + port@1 { + status = "okay"; + label = "lan1"; + }; -ð { - status = "okay"; + port@2 { + status = "okay"; + label = "lan2"; + }; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7530"; - reg = <0>; - mediatek,mcm; - resets = <ðsys MT2701_ETHSYS_MCM_RST>; - reset-names = "mcm"; - core-supply = <&mt6323_vpa_reg>; - io-supply = <&mt6323_vemc3v3_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; + port@3 { + status = "okay"; + label = "lan3"; + }; + + port@4 { + status = "okay"; + label = "wan"; }; }; }; diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi index d304b62d24b58..fbb5731a3a535 100644 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ b/arch/arm/boot/dts/mt7623a.dtsi @@ -17,8 +17,82 @@ &crypto { power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; }; +&gmac0 { + status = "okay"; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + ð { + status = "okay"; power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@0 { + compatible = "mediatek,mt7530"; + reg = <0>; + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "swp0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "swp1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "swp2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "swp3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "swp4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; }; &nandc { -- GitLab From cf8f3a7a044d57f3a0c5e14e97b8926c212f31f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 10 Feb 2023 21:25:03 +0300 Subject: [PATCH 637/926] arm: dts: mt7623: change mt7530 switch address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the case of muxing phy0 of the MT7530 switch, the switch and the phy will have the same address on the mdio bus, 0. This causes the ethernet driver to fail since devices on the mdio bus cannot share an address. Any address can be used for the switch, therefore, change the switch address to 0x1f. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230210182505.24597-4-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623a.dtsi | 4 ++-- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 4 ++-- arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi index fbb5731a3a535..dd522e508eb30 100644 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ b/arch/arm/boot/dts/mt7623a.dtsi @@ -36,9 +36,9 @@ mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; - switch0: switch@0 { + switch0: switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <ðsys MT2701_ETHSYS_MCM_RST>; reset-names = "mcm"; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 8ae9a99f9e6d5..b05479e055d49 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -189,9 +189,9 @@ mdio-bus { #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 5e328c2a6a6e3..6b0c3d1006abe 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -185,9 +185,9 @@ phy5: ethernet-phy@5 { phy-mode = "rgmii-rxid"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; -- GitLab From 031bf30966721c28489b9a52942dcaa4ef67b63e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 10 Feb 2023 21:25:04 +0300 Subject: [PATCH 638/926] arm: dts: mt7623: enable flow control on port@6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Flow control needs to be enabled on both sides to work. It is already enabled on gmac0, enable it on port@6 too. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230210182505.24597-5-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623a.dtsi | 1 + arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi index dd522e508eb30..2a50b5c0c9335 100644 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ b/arch/arm/boot/dts/mt7623a.dtsi @@ -88,6 +88,7 @@ port@6 { fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 6b0c3d1006abe..34994f3f5a4b2 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -230,6 +230,7 @@ port@6 { fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; -- GitLab From 115ee470e5d2438f9c36802fc47bcb2297ec33be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Fri, 10 Feb 2023 21:25:05 +0300 Subject: [PATCH 639/926] arm: dts: mt7623: add port@5 as CPU port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the MT7623AI SoC and Bananapi BPI-R2, port 5 of the MT7530 switch is connected to the second MAC of the SoC as a CPU port. Add the port and set up the second MAC on the bindings. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230210182505.24597-6-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623a.dtsi | 24 +++++++++++++++++++ arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 24 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi index 2a50b5c0c9335..bcf909d58a1cc 100644 --- a/arch/arm/boot/dts/mt7623a.dtsi +++ b/arch/arm/boot/dts/mt7623a.dtsi @@ -28,6 +28,17 @@ fixed-link { }; }; +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + ð { status = "okay"; power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>; @@ -79,6 +90,19 @@ port@4 { label = "swp4"; }; + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index b05479e055d49..a37f3fa223c72 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -182,6 +182,17 @@ fixed-link { }; }; +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; +}; + ð { status = "okay"; @@ -225,6 +236,19 @@ port@4 { label = "lan3"; }; + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + port@6 { reg = <6>; label = "cpu"; -- GitLab From 91c167b9fea03acd8d0e36e11ed2ab92127f7220 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Jun 2023 16:03:21 -0300 Subject: [PATCH 640/926] arm64: dts: imx8mq: Use 'dsi' as node name Use 'dsi' as node name to avoid the following schema warning: imx8mq-evk.dtb: mipi-dsi@30a00000: $nodename:0: 'mipi-dsi@30a00000' does not match '^dsi(@.*)?$' From schema: Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml Signed-off-by: Fabio Estevam Acked-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1bf40c0c77071..b53592df94b59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1056,7 +1056,7 @@ sec_jr2: jr@3000 { }; }; - mipi_dsi: mipi-dsi@30a00000 { + mipi_dsi: dsi@30a00000 { compatible = "fsl,imx8mq-nwl-dsi"; reg = <0x30a00000 0x300>; clocks = <&clk IMX8MQ_CLK_DSI_CORE>, -- GitLab From 8e2facfe904a20e306536aeadd737dfaeab5cb38 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Jun 2023 16:03:22 -0300 Subject: [PATCH 641/926] arm64: dts: imx8mq: Pass address-cells/size-cells to mipi_dsi mipi_dsi node requires #address-cells and #size-cells. Pass them to fix the following schema warnings: imx8mq-mnt-reform2.dtb: mipi-dsi@30a00000: '#address-cells' is a required property From schema: Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml imx8mq-mnt-reform2.dtb: mipi-dsi@30a00000: '#size-cells' is a required property From schema: Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml Signed-off-by: Fabio Estevam Acked-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index b53592df94b59..1a2d2c04db329 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1059,6 +1059,8 @@ sec_jr2: jr@3000 { mipi_dsi: dsi@30a00000 { compatible = "fsl,imx8mq-nwl-dsi"; reg = <0x30a00000 0x300>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, -- GitLab From aa8ca24cc8e7c105b93b1bf35598f402ca8afd6c Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Tue, 16 May 2023 09:28:28 +0100 Subject: [PATCH 642/926] arm64: tegra: Add GPU power rail regulator on Smaug Add the GPU power rail regulator node for the Pixel C. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index d7d7c63e62e25..8d1ed1e8d0ed5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1370,11 +1370,27 @@ max77621_cpu: max77621@1b { maxim,dvs-default-state = <1>; maxim,enable-active-discharge; maxim,enable-bias-control; - maxim,enable-etr; maxim,enable-gpio = <&pmic 5 0>; maxim,externally-enable; }; + max77621_gpu: regulator@1c { + compatible = "maxim,max77621"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <1150000>; + regulator-name = "PPVAR_GPU"; + regulator-ramp-delay = <12500>; + maxim,dvs-default-state = <1>; + maxim,enable-active-discharge; + maxim,enable-bias-control; + maxim,disable-etr; + maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + maxim,externally-enable; + }; + pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; -- GitLab From e2dbd577c51b999d25c3cc990149d98d97f3a152 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Tue, 16 May 2023 09:28:29 +0100 Subject: [PATCH 643/926] arm64: tegra: Enable GPU on Smaug Enable the GPU on the Pixel C. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 8d1ed1e8d0ed5..5a1ce432c1fbb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -36,6 +36,11 @@ dpaux: dpaux@545c0000 { }; }; + gpu@57000000 { + vdd-supply = <&max77621_gpu>; + status = "okay"; + }; + pinmux: pinmux@700008d4 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; -- GitLab From 679899fbc2592e1edecd77d31e89c3ad92ba9e5a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 12:55:42 +0200 Subject: [PATCH 644/926] arm64: tegra: Sort properties more logically We typically sort the "compatible" property first because it defines what the remainder of the properties can be. For the sound node on the Jetson AGX Orin this wasn't done, so fix that up. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index ac64dac287def..e499010fc673b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2345,9 +2345,8 @@ serial { }; sound { - status = "okay"; - compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; dais = /* ADMAIF (FE) Ports */ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, -- GitLab From bd9681c00612a6830ecf74403584054e74646dd0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 12:55:43 +0200 Subject: [PATCH 645/926] arm64: tegra: Add a few blank lines for better readability Surround device tree nodes with blank lines for increased readability. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index e499010fc673b..5f3d6dcf10a2b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2247,6 +2247,7 @@ TEGRA234_AON_GPIO(AA, 4) i2c@c240000 { status = "okay"; + typec@8 { compatible = "cypress,cypd4226"; reg = <0x08>; @@ -2254,22 +2255,27 @@ typec@8 { interrupts = ; firmware-name = "nvidia,jetson-agx-xavier"; status = "okay"; + #address-cells = <1>; #size-cells = <0>; + ccg_typec_con0: connector@0 { compatible = "usb-c-connector"; reg = <0>; label = "USB-C"; data-role = "host"; + ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; hs_ucsi_ccg_p0: endpoint { remote-endpoint = <&hs_typec_p0>; }; }; + port@1 { reg = <1>; ss_ucsi_ccg_p0: endpoint { @@ -2278,20 +2284,24 @@ ss_ucsi_ccg_p0: endpoint { }; }; }; + ccg_typec_con1: connector@1 { compatible = "usb-c-connector"; reg = <1>; label = "USB-C"; data-role = "dual"; + ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; hs_ucsi_ccg_p1: endpoint { remote-endpoint = <&hs_typec_p1>; }; }; + port@1 { reg = <1>; ss_ucsi_ccg_p1: endpoint { -- GitLab From 09d990782a243b97eb566717a2155a306a2f42af Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Nov 2022 14:02:30 +0100 Subject: [PATCH 646/926] arm64: tegra: Add Tegra234 thermal support Add device tree node for the BPMP thermal node on Tegra234 and add thermal zone definitions. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 53 +++++++++++++++++++ .../thermal/tegra234-bpmp-thermal.h | 19 +++++++ 2 files changed, 72 insertions(+) create mode 100644 include/dt-bindings/thermal/tegra234-bpmp-thermal.h diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f5146ce7363d2..f4974e81dd4b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra234"; @@ -3027,6 +3028,11 @@ bpmp_i2c: i2c { #address-cells = <1>; #size-cells = <0>; }; + + bpmp_thermal: thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; }; cpus { @@ -3517,6 +3523,53 @@ sound { <&bpmp TEGRA234_CLK_PLLA_OUT0>; }; + thermal-zones { + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; + status = "disabled"; + }; + + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; + status = "disabled"; + }; + + cv0-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; + status = "disabled"; + }; + + cv1-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; + status = "disabled"; + }; + + cv2-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; + status = "disabled"; + }; + + soc0-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; + status = "disabled"; + }; + + soc1-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; + status = "disabled"; + }; + + soc2-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; + status = "disabled"; + }; + + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; + status = "disabled"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , diff --git a/include/dt-bindings/thermal/tegra234-bpmp-thermal.h b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h new file mode 100644 index 0000000000000..9347879509321 --- /dev/null +++ b/include/dt-bindings/thermal/tegra234-bpmp-thermal.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding nvidia,tegra234-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H + +#define TEGRA234_BPMP_THERMAL_ZONE_CPU 0 +#define TEGRA234_BPMP_THERMAL_ZONE_GPU 1 +#define TEGRA234_BPMP_THERMAL_ZONE_CV0 2 +#define TEGRA234_BPMP_THERMAL_ZONE_CV1 3 +#define TEGRA234_BPMP_THERMAL_ZONE_CV2 4 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC0 5 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC1 6 +#define TEGRA234_BPMP_THERMAL_ZONE_SOC2 7 +#define TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX 8 + +#endif -- GitLab From 1d3fbd3d41a6c7552126ce39b81591de942a4207 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 26 Jan 2023 14:34:02 +0100 Subject: [PATCH 647/926] arm64: tegra: Enable thermal support on Jetson AGX Orin Add thermal zone details and enable the PWM fan as cooling device. Note that this also changes the cooling levels for the PWM fan, which should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 22 +++++++++++++++++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 22 ++++++++++++++----- .../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 6 +++++ 3 files changed, 45 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 812499918085e..319b3a9cff244 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -139,4 +139,26 @@ vdd_12v_pcie: regulator-vdd-12v-pcie { gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; regulator-boot-on; }; + + thermal-zones { + tj-thermal { + polling-delay = <1000>; + polling-delay-passive = <1000>; + status = "okay"; + + trips { + tj_trip_active0: active-0 { + temperature = <75000>; + hysteresis = <4000>; + type = "active"; + }; + + tj_trip_active1: active-1 { + temperature = <95000>; + hysteresis = <4000>; + type = "active"; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 5f3d6dcf10a2b..cd13cf2381dde 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2343,11 +2343,7 @@ key-suspend { }; pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; + cooling-levels = <66 215 255>; }; serial { @@ -2433,4 +2429,20 @@ sound { "CVB-RT DMIC1", "CVB-RT MIC", "CVB-RT DMIC2", "CVB-RT MIC"; }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index 022a5408d8693..d94147f22ebf7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -33,6 +33,12 @@ pwm@32f0000 { }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + #cooling-cells = <2>; + }; + vdd_1v8_sys: regulator-vdd-1v8-sys { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_SYS"; -- GitLab From a6fb90f0eefb13e2cf18f39f1a84a9ef6054153b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 13:45:53 +0200 Subject: [PATCH 648/926] arm64: tegra: Enable thermal support on Jetson Orin NX Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. This also removes a duplicate definition of the PWM fan and changes its cooling levels. This should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 60 ++----------------- .../nvidia/tegra234-p3768-0000+p3767-0000.dts | 23 +++++-- .../boot/dts/nvidia/tegra234-p3768-0000.dtsi | 1 - 3 files changed, 23 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index bd60478fa75e7..a8aa6e7d8fbc5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -99,74 +99,24 @@ vdd_3v3_ao: regulator-vdd-3v3-ao { }; thermal-zones { - /* - * This monitoring is far from optimal, but it's good enough - * at this stage. - */ - cpu-thermal { + tj-thermal { polling-delay = <1000>; polling-delay-passive = <1000>; status = "okay"; trips { - critical { - temperature = <104500>; - hysteresis = <0>; - type = "critical"; - }; - - hot { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - - board_trip_passive: passive { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - board_trip_active2: active-2 { - temperature = <80000>; + tj_trip_active0: active-0 { + temperature = <74000>; hysteresis = <4000>; type = "active"; }; - board_trip_active1: active-1 { - temperature = <65000>; - hysteresis = <4000>; - type = "active"; - }; - - board_trip_active0: active-0 { - temperature = <50000>; + tj_trip_active1: active-1 { + temperature = <95000>; hysteresis = <4000>; type = "active"; }; }; - - cooling-maps { - passive { - cooling-device = <&fan 3 3>; - trip = <&board_trip_passive>; - }; - - active2 { - cooling-device = <&fan 2 3>; - trip = <&board_trip_active2>; - }; - - active1 { - cooling-device = <&fan 1 2>; - trip = <&board_trip_active1>; - }; - - active0 { - cooling-device = <&fan 0 1>; - trip = <&board_trip_active0>; - }; - }; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts index 7dfbc38eb3c45..65e4b51b79c1b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -112,11 +112,8 @@ key-suspend { }; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; + pwm-fan { + cooling-levels = <0 187 255>; }; vdd_3v3_pcie: regulator-vdd-3v3-pcie { @@ -131,4 +128,20 @@ vdd_3v3_pcie: regulator-vdd-3v3-pcie { serial { status = "okay"; }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi index bbd68ef93d979..c7291ba27cfa7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi @@ -209,7 +209,6 @@ key-suspend { fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm3 0 45334>; - cooling-levels = <0 95 178 255>; #cooling-cells = <2>; }; -- GitLab From 6312e57b3250085b196d9630d2eeea6a583b97ef Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 13:48:38 +0200 Subject: [PATCH 649/926] arm64: tegra: Enable thermal support on Jetson Orin Nano Enable the TJ thermal zone and hook up cooling maps for the PWM- controlled fan and two trip points. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../nvidia/tegra234-p3768-0000+p3767-0005.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts index ba66c1845f759..9b86aa6f7dbe1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -10,4 +10,24 @@ / { compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234"; model = "NVIDIA Jetson Orin Nano Developer Kit"; + + pwm-fan { + cooling-levels = <0 187 255>; + }; + + thermal-zones { + tj-thermal { + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + }; + }; + }; }; -- GitLab From a68e1aec587a75a51496f1b207272b6034cca190 Mon Sep 17 00:00:00 2001 From: Shreeya Patel Date: Sat, 10 Jun 2023 19:18:41 +0530 Subject: [PATCH 650/926] arm64: dts: rockchip: Add saradc node to rock5b Add ADC support for ROCK 5B. Signed-off-by: Shreeya Patel Link: https://lore.kernel.org/r/20230610134841.172313-1-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 154b1089db770..afda976680bca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -207,6 +207,11 @@ &pwm1 { status = "okay"; }; +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; -- GitLab From e280427384269fba93c7ec0373afe87bc39d7945 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 9 May 2023 23:16:35 +0200 Subject: [PATCH 651/926] ARM: dts: qcom: msm8226: Use XO from rpmcc where possible The xo clock being used everywhere actually goes via the RPM. Since the rpmcc driver recently got support for this clock we can use this now. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-1-83a2dfc986ab@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8226.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index a3a9162e9c28e..dd67c881c378a 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -182,7 +182,7 @@ sdhc_1: mmc@f9824900 { interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc1_default_state>; @@ -198,7 +198,7 @@ sdhc_2: mmc@f98a4900 { interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc2_default_state>; @@ -214,7 +214,7 @@ sdhc_3: mmc@f9864900 { interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC3_AHB_CLK>, <&gcc GCC_SDCC3_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-names = "default"; pinctrl-0 = <&sdhc3_default_state>; @@ -368,7 +368,8 @@ usb_hs_phy: phy { compatible = "qcom,usb-hs-phy-msm8226", "qcom,usb-hs-phy"; #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; clock-names = "ref", "sleep"; resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; reset-names = "phy", "por"; @@ -628,7 +629,7 @@ adsp: remoteproc@fe200000 { power-domains = <&rpmpd MSM8226_VDDCX>; power-domain-names = "cx"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; memory-region = <&adsp_region>; -- GitLab From 3f502e372b4d41db1642c0a1285b2cb52ab5f796 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 9 May 2023 23:16:37 +0200 Subject: [PATCH 652/926] ARM: dts: qcom: msm8226: Provide clocks to mmcc node The mmcc needs several clocks that are being used as parents. Provide them in dt. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-3-83a2dfc986ab@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8226.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index dd67c881c378a..ec1b72af80aac 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -398,6 +398,21 @@ mmcc: clock-controller@fd8c0000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte"; }; tlmm: pinctrl@fd510000 { -- GitLab From f04325e4d4d66e63fc4e474ff54835a28b3ff29e Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Thu, 8 Jun 2023 15:15:13 -0500 Subject: [PATCH 653/926] arm64: dts: qcom: sa8540p-ride: Specify ethernet phy OUI With wider usage on more boards, there have been reports of the following: [ 315.016174] qcom-ethqos 20000.ethernet eth0: no phy at addr -1 [ 315.016179] qcom-ethqos 20000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) which has been fairly random and isolated to specific boards. Early reports were written off as a hardware issue, but it has been prevalent enough on boards that theory seems unlikely. In bring up of a newer piece of hardware, similar was seen, but this time _consistently_. Moving the reset to the mdio bus level (which isn't exactly a lie, it is the only device on the bus so one could model it as such) fixed things on that platform. Analysis on sa8540p-ride shows that the phy's reset is not being handled during the OUI scan if the reset lives in the phy node: # gpio 752 is the reset, and is active low, first mdio reads are the OUI modprobe-420 [006] ..... 154.738544: mdio_access: stmmac-0 read phy:0x08 reg:0x02 val:0x0141 modprobe-420 [007] ..... 154.738665: mdio_access: stmmac-0 read phy:0x08 reg:0x03 val:0x0dd4 modprobe-420 [004] ..... 154.741357: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.741358: gpio_direction: 752 out (0) modprobe-420 [004] ..... 154.741360: gpio_value: 752 set 0 modprobe-420 [006] ..... 154.762751: gpio_value: 752 set 1 modprobe-420 [007] ..... 154.846857: gpio_value: 752 set 1 modprobe-420 [004] ..... 154.937824: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-420 [004] ..... 154.937932: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 Moving it to the bus level, or specifying the OUI in the phy's compatible ensures the reset is handled before any mdio access Here is tracing with the OUI approach (which skips scanning the OUI): modprobe-549 [007] ..... 63.860295: gpio_value: 752 set 1 modprobe-549 [007] ..... 63.860297: gpio_direction: 752 out (0) modprobe-549 [007] ..... 63.860299: gpio_value: 752 set 0 modprobe-549 [004] ..... 63.882599: gpio_value: 752 set 1 modprobe-549 [005] ..... 63.962132: gpio_value: 752 set 1 modprobe-549 [006] ..... 64.049379: mdio_access: stmmac-0 write phy:0x08 reg:0x0d val:0x0003 modprobe-549 [006] ..... 64.049490: mdio_access: stmmac-0 write phy:0x08 reg:0x0e val:0x0014 The OUI approach is taken given the description matches the situation perfectly (taken from ethernet-phy.yaml): - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: If the PHY reports an incorrect ID (or none at all) then the compatible list may contain an entry with the correct PHY ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, this is the chip vendor OUI bits 19:24, followed by 10 bits of a vendor specific ID. With this in place the sa8540p-ride's phy is probing consistently, so it seems the floating reset during mdio access was the issue. In either case, it shouldn't be floating so this improves the situation. The below link discusses some of the relationship of mdio, its phys, and points to this OUI compatible as a way to opt out of the OUI scan pre-reset handling which influenced this decision. Link: https://lore.kernel.org/all/dca54c57-a3bd-1147-63b2-4631194963f0@gmail.com/ Fixes: 57827e87be54 ("arm64: dts: qcom: sa8540p-ride: Add ethernet nodes") Signed-off-by: Andrew Halaney Reviewed-by: Konrad Dybcio Reviewed-by: Brian Masney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608201513.882950-1-ahalaney@redhat.com --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 21e9eaf914dde..5a26974dcf8f9 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -171,6 +171,7 @@ mdio { /* Marvell 88EA1512 */ rgmii_phy: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; reg = <0x8>; interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; -- GitLab From bbde65f9da9291a77636e1467b28f27ced1b4ece Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 13 Jun 2023 09:30:12 +0200 Subject: [PATCH 654/926] arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels "low" was written "lov", fix this. Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels") Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v4-1-ac2c6899d22c@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 20924d570c07e..981d439dc95c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3640,15 +3640,15 @@ rpmhpd_opp_min_svs: opp-48 { opp-level = ; }; - rpmhpd_opp_lov_svs_d2: opp-52 { + rpmhpd_opp_low_svs_d2: opp-52 { opp-level = ; }; - rpmhpd_opp_lov_svs_d1: opp-56 { + rpmhpd_opp_low_svs_d1: opp-56 { opp-level = ; }; - rpmhpd_opp_lov_svs_d0: opp-60 { + rpmhpd_opp_low_svs_d0: opp-60 { opp-level = ; }; -- GitLab From 66adfbc4d33993865a180016db73520a15e754c9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 13 Jun 2023 09:30:13 +0200 Subject: [PATCH 655/926] arm64: dts: qcom: sm8550: add display port nodes Add the Display Port controller subnode to the MDSS node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v4-2-ac2c6899d22c@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 981d439dc95c6..f00721fe4208f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2486,6 +2486,13 @@ dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2513,6 +2520,84 @@ opp-514000000 { }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -2696,8 +2781,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ -- GitLab From a277430b3836cdfb994f45cc87d1bd56c4d490aa Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:04:20 -0700 Subject: [PATCH 656/926] arm64: dts: qcom: sc8180x-primus: dispcc is already okay &dispcc status was changed to okay by default in the platform, no need to do it again in the board. Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612220420.1884631-1-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index cca663bcb92d4..fc038474cb71b 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -291,10 +291,6 @@ vreg_l16e_3p0: ldo16 { }; }; -&dispcc { - status = "okay"; -}; - &gpu { status = "okay"; -- GitLab From e537d5ef47097360d8df524c748f3df451383dcd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:05:32 -0700 Subject: [PATCH 657/926] arm64: dts: qcom: sc8180x: Fix adreno smmu compatible The adreno smmu should be compatible with qcom,adreno-smmu as well for per-process page tables to work. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612220532.1884860-1-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index e8613a00fcab7..88015742315be 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2310,7 +2310,8 @@ gpucc: clock-controller@2c90000 { }; adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; + compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; -- GitLab From 2d7b1a31ffb865d1f8e95e985cdbd0df72f671cf Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:07:39 -0700 Subject: [PATCH 658/926] arm64: dts: qcom: sc8180x: Move DisplayPort for MMCX The DisplayPort blocks are powered by MMCX and should be described as such to ensure that power votes are done on the right resource. This also solves the problem that sync_state is unaware of the DP controllers needing MMCX to be kept alive during boot. As such this change also fixes occasionally seen crashes during boot due to undervoltage of MMCX. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612220739.1886155-1-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 88015742315be..5276d4bfdf4e6 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2966,7 +2966,7 @@ mdss_dp0: displayport-controller@ae90000 { #sound-dai-cells = <0>; operating-points-v2 = <&dp0_opp_table>; - power-domains = <&rpmhpd SC8180X_CX>; + power-domains = <&rpmhpd SC8180X_MMCX>; status = "disabled"; @@ -3040,7 +3040,7 @@ mdss_dp1: displayport-controller@ae98000 { #sound-dai-cells = <0>; operating-points-v2 = <&dp0_opp_table>; - power-domains = <&rpmhpd SC8180X_CX>; + power-domains = <&rpmhpd SC8180X_MMCX>; status = "disabled"; @@ -3114,7 +3114,7 @@ mdss_edp: displayport-controller@ae9a000 { #sound-dai-cells = <0>; operating-points-v2 = <&edp_opp_table>; - power-domains = <&rpmhpd SC8180X_CX>; + power-domains = <&rpmhpd SC8180X_MMCX>; status = "disabled"; -- GitLab From 8889d13c2e758cff33fc85139c6d9288553e0e30 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 17:22:49 +0200 Subject: [PATCH 659/926] arm64: dts: qcom: pm8550: add PWM controller Add the PWM function to the pm8550 dtsi, this is usually used to drive RGB leds on platforms using this PMIC. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-1-a288f24af81b@linaro.org --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 33f357a806362..db3d5c17a77df 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -61,5 +61,15 @@ pm8550_flash: led-controller@ee00 { reg = <0xee00>; status = "disabled"; }; + + pm8550_pwm: pwm { + compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; -- GitLab From 3818165476d70b13cf3193e1b5e60b1af6689772 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 17:22:50 +0200 Subject: [PATCH 660/926] arm64: dts: qcom: sm8550-qrd: add notification RGB LED The QRD features a notification LED connected to the pm8550. Configure the RGB led controlled by the PMIC PWM controller. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-2-a288f24af81b@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 8669d29144bb0..efff15225e674 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -516,6 +516,33 @@ led-1 { }; }; +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; -- GitLab From a791fc19965e52918bb70e2b764965083eaadbed Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 17:22:51 +0200 Subject: [PATCH 661/926] arm64: dts: qcom: pmk8550: always enable RTC PMIC device There's no reason to keep the RTC disabled, it has been tested and is functional on the SM8550 QRD and MTP boards. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-3-a288f24af81b@linaro.org --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 8c897d4fee296..c7ac9b2eaacfe 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -49,7 +49,6 @@ pmk8550_rtc: rtc@6100 { reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; }; pmk8550_sdam_2: nvram@7100 { -- GitLab From bb47bfbd5aa89368c348d9828484f7201cef6cea Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Jun 2023 17:22:52 +0200 Subject: [PATCH 662/926] arm64: dts: qcom: sm8550-qrd: enable PMIC Volume and Power buttons The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230525-topic-sm8550-upstream-pm8550-lpg-dt-v4-4-a288f24af81b@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index efff15225e674..cde2ab8b18a48 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -54,6 +54,22 @@ chosen { stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + pmic-glink { compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; @@ -516,6 +532,16 @@ led-1 { }; }; +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + &pm8550_pwm { status = "okay"; @@ -548,6 +574,16 @@ &pm8550b_eusb2_repeater { vdd3-supply = <&vreg_l5b_3p1>; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; -- GitLab From f9a97656ace80c617df2d6003c815877c026a9e3 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:34 +0530 Subject: [PATCH 663/926] dt-bindings: arm: qcom: Document SDX75 platform and boards Document the SDX75 platform binding and also the boards using it. Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-2-git-send-email-quic_rohiagar@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 8302d1ee280d5..834ad577ccfcf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -70,6 +70,7 @@ description: | sdm845 sdx55 sdx65 + sdx75 sm4250 sm6115 sm6115p @@ -828,6 +829,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + - items: - enum: - qcom,ipq6018-cp01 @@ -1056,6 +1062,7 @@ allOf: - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sdx75 - qcom,sm4250 - qcom,sm6115 - qcom,sm6125 -- GitLab From 9181bb939984f1ad4f958c2be3ea10fd67344165 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:38 +0530 Subject: [PATCH 664/926] arm64: dts: qcom: Add SDX75 platform and IDP board support Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdx75-idp.dts | 33 ++ arch/arm64/boot/dts/qcom/sdx75.dtsi | 670 +++++++++++++++++++++++++ 3 files changed, 704 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f9e81253e18a..70478e584e3d4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts new file mode 100644 index 0000000000000..cbe5cdf5a2282 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdx75.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX75 IDP"; + compatible = "qcom,sdx75-idp", "qcom,sdx75"; + + aliases { + serial0 = &uart1; + }; +}; + +&chosen { + stdout-path = "serial0:115200n8"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <110 6>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi new file mode 100644 index 0000000000000..21d5d55da5ebf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX75 SoC device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_100>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_200>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_300>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <235>; + exit-latency-us = <428>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + CPU_RAIL_OFF: cpu-rail-sleep-1 { + compatible = "arm,idle-state"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001344>; + entry-latency-us = <2761>; + exit-latency-us = <3964>; + min-residency-us = <8467>; + }; + + CLUSTER_SLEEP_2: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <2793>; + exit-latency-us = <4023>; + min-residency-us = <9826>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sdx75", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + hyp_elf_package_mem: hyp-elf-package@80800000 { + reg = <0x0 0x80800000 0x0 0x200000>; + no-map; + }; + + access_control_db_mem: access-control-db@81380000 { + reg = <0x0 0x81380000 0x0 0x80000>; + no-map; + }; + + qteetz_mem: qteetz@814e0000 { + reg = <0x0 0x814e0000 0x0 0x2a0000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@81780000 { + reg = <0x0 0x81780000 0x0 0xa00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@87a00000 { + reg = <0x0 0x87a00000 0x0 0x1c0000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@87c00000 { + reg = <0x0 0x87c00000 0x0 0x100000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@87d00000 { + reg = <0x0 0x87d00000 0x0 0x40000>; + no-map; + }; + + xbl_sc_mem: xbl-sc@87d40000 { + reg = <0x0 0x87d40000 0x0 0x40000>; + no-map; + }; + + modem_efs_shared_mem: modem-efs-shared@87d80000 { + reg = <0x0 0x87d80000 0x0 0x10000>; + no-map; + }; + + aop_image_mem: aop-image@87e00000 { + reg = <0x0 0x87e00000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@87e20000 { + reg = <0x0 0x87e20000 0x0 0xc0000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@87ee0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87ee0000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@87f00000 { + reg = <0x0 0x87f00000 0x0 0x20000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@87f20000 { + reg = <0x0 0x87f20000 0x0 0x10000>; + no-map; + }; + + secdata_mem: secdata@87f30000 { + reg = <0x0 0x87f30000 0x0 0x1000>; + no-map; + }; + + tme_crashdump_mem: tme-crashdump@87f31000 { + reg = <0x0 0x87f31000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@87f71000 { + reg = <0x0 0x87f71000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@87f75000 { + reg = <0x0 0x87f75000 0x0 0x10000>; + no-map; + }; + + qdss_mem: qdss@88800000 { + reg = <0x0 0x88800000 0x0 0x300000>; + no-map; + }; + + audio_heap_mem: audio-heap@88b00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88b00000 0x0 0x400000>; + no-map; + }; + + mpss_dsmharq_mem: mpss-dsmharq@88f00000 { + reg = <0x0 0x88f00000 0x0 0x5080000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { + reg = <0x0 0x8df80000 0x0 0x80000>; + no-map; + }; + + mpssadsp_mem: mpssadsp@8e000000 { + reg = <0x0 0x8e000000 0x0 0xf400000>; + no-map; + }; + + gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { + reg = <0x0 0xbdb00000 0x0 0x2000000>; + no-map; + }; + + smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { + reg = <0x0 0xbfb00000 0x0 0x100000>; + no-map; + }; + + hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x0 0x0080000 0x0 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart1: serial@984000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qupv3_se1_2uart_active>; + pinctrl-1 = <&qupv3_se1_2uart_sleep>; + pinctrl-names = "default", + "sleep"; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdx75-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 147 52>, + <52 266 32>, + <84 500 59>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0 0x0f000000 0x0 0x400000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { + tx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + drive-strength= <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + drive-strength= <2>; + bias-disable; + }; + }; + + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, + <0x0 0x17260000 0x0 0x80000>; + interrupts = ; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + power-domains = <&CLUSTER_PD>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + clock-names = "xo", + "alternate"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- GitLab From a2422d51069d682a2172981fa6e7ba84b2dc93c8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2023 11:43:22 +0200 Subject: [PATCH 665/926] arm64: dts: qcom: sm8550-qrd: add WSA8845 speakers Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608094323.267278-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index cde2ab8b18a48..c08230e840450 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -447,6 +447,24 @@ &gcc { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -614,6 +632,36 @@ &sleep_clk { clock-frequency = <32000>; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; +}; + &swr1 { status = "okay"; -- GitLab From edb92fae57e7b3292e92bc3fe7dfd0e21875befe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Jun 2023 11:43:23 +0200 Subject: [PATCH 666/926] arm64: dts: qcom: sm8550-mtp: add WSA8845 speakers Add Qualcomm WSA8845 Soundwire smart speaker amplifiers. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608094323.267278-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 579f65f523709..7961dc6067e80 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -419,6 +419,24 @@ vreg_l3g_1p2: ldo3 { }; }; +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -553,6 +571,36 @@ &sleep_clk { clock-frequency = <32000>; }; +&swr0 { + status = "okay"; + + /* WSA8845 */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; + + /* WSA8845 */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_active>; + powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3g_1p2>; + }; +}; + &swr1 { status = "okay"; -- GitLab From 9f5ebcd61009de388af6f66509f2a1169f90dbbe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 12 Jun 2023 19:37:57 +0200 Subject: [PATCH 667/926] arm64: dts: qcom: sm8550-qrd: add sound card Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612173758.286411-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 81 +++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index c08230e840450..ec4feee6837d6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -104,6 +104,87 @@ pmic_glink_ss_in: endpoint { }; }; + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-QRD"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; -- GitLab From 3f01d016cf4b80382f1c1b8ab6bef7aa76dece01 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 12 Jun 2023 19:37:58 +0200 Subject: [PATCH 668/926] arm64: dts: qcom: sm8550-mtp: add sound card Add the sound card node with tested playback over WSA8845 speakers and WCD9385 headset over USB Type-C. The recording links were not tested, but should be similar to previous platforms. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612173758.286411-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 81 +++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 7961dc6067e80..ec86c5f380450 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -87,6 +87,87 @@ pmic_glink_ss_in: endpoint { }; }; + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "SM8550-MTP"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; -- GitLab From bfc43a9c0ce5f3fcf98c972d7b7f21a742b7c957 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:10 +0100 Subject: [PATCH 669/926] dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-2-srinivas.kandagatla@linaro.org --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 50 +++++++++++++++++++ .../dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 12 +++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 0000000000000..047cae91f4437 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h new file mode 100644 index 0000000000000..df800ea2741c8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif -- GitLab From 83da70da40c93f3515aebcd5f2b8ff6283f64ee3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:11 +0100 Subject: [PATCH 670/926] dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-3-srinivas.kandagatla@linaro.org --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++ include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 047cae91f4437..3326dcd6766c3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -19,6 +19,7 @@ description: | properties: compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc reg: @@ -39,6 +40,15 @@ required: additionalProperties: false examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | #include lpasscc: clock-controller@33e0000 { diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h index df800ea2741c8..d190d57fc81aa 100644 --- a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 -- GitLab From 532bbadcb511e8477b83b4152a199bf7ffc4350c Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:14 +0100 Subject: [PATCH 671/926] arm64: dts: qcom: sc8280xp: add resets for soundwire controllers Soundwire controllers on sc8280xp needs an explicit reset, add support for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-6-srinivas.kandagatla@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 4f64adadcdb55..2f7ead41021cf 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -2551,6 +2552,8 @@ swr1: soundwire-controller@3210000 { interrupts = ; clocks = <&rxmacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "RX"; qcom,din-ports = <0>; @@ -2625,6 +2628,8 @@ swr0: soundwire-controller@3250000 { interrupts = ; clocks = <&wsamacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; label = "WSA"; qcom,din-ports = <2>; @@ -2647,6 +2652,13 @@ swr0: soundwire-controller@3250000 { status = "disabled"; }; + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x032a9000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; @@ -2656,6 +2668,8 @@ swr2: soundwire-controller@3330000 { clocks = <&txmacro>; clock-names = "iface"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "TX"; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2845,6 +2859,13 @@ data-pins { }; }; + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0 0x033e0000 0 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + sdc2: mmc@8804000 { compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; -- GitLab From f2f644d85c4495474bf7d598023f550f0669306a Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 5 Jun 2023 13:35:30 +0530 Subject: [PATCH 672/926] dt-bindings: arm: qcom: document MI01.9 board based on IPQ5332 family Document the MI01.9 (Reference Design Platform 474) board based on IPQ5332 family of SoCs. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230605080531.3879-4-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 834ad577ccfcf..e6193be733297 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -94,6 +94,7 @@ description: | ap-mi01.2 ap-mi01.3 ap-mi01.6 + ap-mi01.9 cdp cp01-c1 dragonboard @@ -341,6 +342,7 @@ properties: - qcom,ipq5332-ap-mi01.2 - qcom,ipq5332-ap-mi01.3 - qcom,ipq5332-ap-mi01.6 + - qcom,ipq5332-ap-mi01.9 - const: qcom,ipq5332 - items: -- GitLab From 5aa5dbc254be19b7011cb1f9d3cb7e241d5fc986 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 5 Jun 2023 13:35:31 +0530 Subject: [PATCH 673/926] arm64: dts: qcom: ipq5332: add support for the RDP474 variant Add the initial device tree support for the Reference Design Platform(RDP) 474 based on IPQ5332 family of SoC. This patch carries the support for Console UART, eMMC, I2C and GPIO based buttons. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230605080531.3879-5-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts | 112 ++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 70478e584e3d4..354a9734c04bd 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts new file mode 100644 index 0000000000000..53c68d8c5e5d2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP474 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; + compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default_state>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + gpio_keys_default_state: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; -- GitLab From f684391e3d323bbdc832569dc685d1289c58d081 Mon Sep 17 00:00:00 2001 From: Anusha Rao Date: Fri, 2 Jun 2023 14:14:31 +0530 Subject: [PATCH 674/926] arm64: dts: qcom: ipq9574: add few more reserved memory region In IPQ SoCs, bootloader will collect the system RAM contents upon crash for post-morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loss of some data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the reserved memory region, wherever applicable Signed-off-by: Anusha Rao Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602084431.19134-1-quic_anusha@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 988107a9edc45..dbf3057d936fb 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -155,6 +155,16 @@ reserved-memory { #size-cells = <2>; ranges; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz_region: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x400000>; no-map; @@ -162,7 +172,7 @@ tz_region: tz@4a600000 { smem@4aa00000 { compatible = "qcom,smem"; - reg = <0x0 0x4aa00000 0x0 0x00100000>; + reg = <0x0 0x4aa00000 0x0 0x100000>; hwlocks = <&tcsr_mutex 0>; no-map; }; -- GitLab From ade89bc08c8e7f52ee8a70d0c6ea55c2defdf1d3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:36 +0200 Subject: [PATCH 675/926] arm64: dts: qcom: sm6350: Add PSCI idle states Add the PSCI idle states so that the CPU (among other things) can reach lower power states. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-2-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 141 +++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 4dffd7974fa39..a0e64f888de6f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -56,6 +56,8 @@ CPU0: cpu@0 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -82,6 +84,8 @@ CPU1: cpu@100 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -104,6 +108,8 @@ CPU2: cpu@200 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -126,6 +132,8 @@ CPU3: cpu@300 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -148,6 +156,8 @@ CPU4: cpu@400 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -170,6 +180,8 @@ CPU5: cpu@500 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -192,6 +204,8 @@ CPU6: cpu@600 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -214,6 +228,8 @@ CPU7: cpu@700 { interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -257,6 +273,76 @@ core7 { }; }; }; + + domain-idle-states { + CLUSTER_SLEEP_PC: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + }; + }; + + cpu_idle_states: idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; }; firmware { @@ -386,6 +472,61 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_PC + &CLUSTER_SLEEP_CX_RET + &CLUSTER_AOSS_SLEEP>; + }; }; reserved_memory: reserved-memory { -- GitLab From ab033e7846f91953244d0626b28ce66412b813b3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:37 +0200 Subject: [PATCH 676/926] arm64: dts: qcom: qdu1000: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 6bd20c54b589 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-3-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index bc16d12432c11..471a5741396c2 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1242,6 +1242,7 @@ apps_rsc: rsc@17a00000 { qcom,tcs-config = , , , ; label = "apps_rsc"; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- GitLab From 442d55d099ed72d96aee996e56f802b5cf885f39 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:38 +0200 Subject: [PATCH 677/926] arm64: dts: qcom: sc8180x: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-4-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 5276d4bfdf4e6..33493032b6e5e 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3496,6 +3496,7 @@ apps_rsc: rsc@18200000 { , ; label = "apps_rsc"; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- GitLab From 7b04cbd81b0e60c5151a310e7b730dc4a951a211 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:39 +0200 Subject: [PATCH 678/926] arm64: dts: qcom: sdm670: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-5-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c5f839dd1c6e3..624aef6a4a608 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1264,6 +1264,7 @@ apps_rsc: rsc@179c0000 { , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- GitLab From 91e83140b5dd5598fbcfada3ee1f8b2b410c3731 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:40 +0200 Subject: [PATCH 679/926] arm64: dts: qcom: sdm845: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: c83545d95376 ("arm64: dts: sdm845: Add rpmh-rsc node") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-6-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f1dfdd129eab3..cf5898b0c17f1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5129,6 +5129,7 @@ apps_rsc: rsc@179c0000 { , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- GitLab From 255c53df8ec3ea9f00765eb3dac02ccb705704dd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:41 +0200 Subject: [PATCH 680/926] arm64: dts: qcom: sm6350: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-7-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index a0e64f888de6f..68e07025aab59 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2046,6 +2046,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm6350-rpmh-clk"; -- GitLab From 4b2c7ac8e469ab7f92e50c34ad4012a77e79d078 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:42 +0200 Subject: [PATCH 681/926] arm64: dts: qcom: sm8550: Flush RSC sleep & wake votes The rpmh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being commited. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-8-b4a985f57b8b@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index f00721fe4208f..a6be0b54ba00c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3697,6 +3697,7 @@ apps_rsc: rsc@17a00000 { qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; -- GitLab From b179f35b887b2d17e93f1827550290669bc6b110 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 12 May 2023 15:58:25 +0200 Subject: [PATCH 682/926] arm64: dts: qcom: sm6350: add uart1 node Add the node describing uart1 incl. opp table and pinctrl. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421-fp4-bluetooth-v2-3-3de840d5483e@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 68e07025aab59..6a77fd068ec0f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -464,6 +464,25 @@ opp-2073600000 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -882,6 +901,22 @@ i2c0: i2c@880000 { status = "disabled"; }; + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; + interrupts = ; + power-domains = <&rpmhpd SM6350_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; @@ -1867,6 +1902,34 @@ qup_i2c10_default: qup-i2c10-default-state { drive-strength = <2>; bias-pull-up; }; + + qup_uart1_cts: qup-uart1-cts-default-state { + pins = "gpio61"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_rts: qup-uart1-rts-default-state { + pins = "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart1_rx: qup-uart1-rx-default-state { + pins = "gpio64"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_tx: qup-uart1-tx-default-state { + pins = "gpio63"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; }; apps_smmu: iommu@15000000 { -- GitLab From c4ef464b24c5aefb7e23eb8fcc08250a783a529b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 12 May 2023 15:58:26 +0200 Subject: [PATCH 683/926] arm64: dts: qcom: sm7225-fairphone-fp4: Add Bluetooth The device has a WCN3988 chip for WiFi and Bluetooth. Configure the Bluetooth node and enable the UART it is connected to, plus the necessary pinctrl that has been borrowed with comments from sc7280-idp.dtsi. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421-fp4-bluetooth-v2-4-3de840d5483e@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 7ae6aba5d2ec7..e3dc499515238 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -31,6 +31,7 @@ / { aliases { serial0 = &uart9; + serial1 = &uart1; }; chosen { @@ -524,6 +525,39 @@ adc-chan@644 { }; }; +&qup_uart1_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart1_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart1_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart1_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -561,6 +595,75 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; + + qup_uart1_sleep_cts: qup-uart1-sleep-cts-state { + pins = "gpio61"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart1_sleep_rts: qup-uart1-sleep-rts-state { + pins = "gpio62"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart1_sleep_rx: qup-uart1-sleep-rx-state { + pins = "gpio64"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart1_sleep_tx: qup-uart1-sleep-tx-state { + pins = "gpio63"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; +}; + +&uart1 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 64 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart1_sleep_cts>, <&qup_uart1_sleep_rts>, <&qup_uart1_sleep_tx>, <&qup_uart1_sleep_rx>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + vddio-supply = <&vreg_l11a>; + vddxo-supply = <&vreg_l7a>; + vddrf-supply = <&vreg_l2e>; + vddch0-supply = <&vreg_l10e>; + swctrl-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + + max-speed = <3200000>; + }; }; &uart9 { -- GitLab From b59cd2902c58969230a8aca67a10ac3fbde0af15 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 19 May 2023 19:08:42 +0530 Subject: [PATCH 684/926] arm64: dts: qcom: ipq5332: rename mi01.2 dts to rdp441 To align with ipq5332-rdp468.dts, lets rename the mi01.2 dts as well to ipq5332-rdp441.dts. Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519133844.23512-2-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../boot/dts/qcom/{ipq5332-mi01.2.dts => ipq5332-rdp441.dts} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm64/boot/dts/qcom/{ipq5332-mi01.2.dts => ipq5332-rdp441.dts} (100%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 354a9734c04bd..c1573bba67292 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,7 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts similarity index 100% rename from arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts rename to arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts -- GitLab From 66d141a15c19f89e7e259e57a007550a253e03d2 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 19 May 2023 19:08:43 +0530 Subject: [PATCH 685/926] arm64: dts: qcom: ipq5332: define UART1 Add the definition for the UART1 found on IPQ5332 SoC. Reviewed-by: Bhupesh Sharma Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519133844.23512-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 47984037f0a54..e7d3ec7a57505 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -225,6 +225,18 @@ blsp1_uart0: serial@78af000 { status = "disabled"; }; + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; -- GitLab From 0196b041aeec788e1bc516b6d24d9c59ea59b1a6 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 19 May 2023 19:08:44 +0530 Subject: [PATCH 686/926] arm64: dts: qcom: ipq5332: add few more reserved memory region In IPQ SoCs, bootloader will collect the system RAM contents upon crash for the post morterm analysis. If we don't reserve the memory region used by bootloader, obviously linux will consume it and upon next boot on crash, bootloader will be loaded in the same region, which will lead to loose some of the data, sometimes we may miss out critical information. So lets reserve the region used by the bootloader. Similarly SBL copies some data into the reserved region and it will be used in the crash scenario. So reserve 1MB for SBL as well. While at it, drop the size padding in the smem memory region. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519133844.23512-4-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index e7d3ec7a57505..b4558871ed215 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -114,6 +114,16 @@ reserved-memory { #size-cells = <2>; ranges; + bootloader@4a100000 { + reg = <0x0 0x4a100000 0x0 0x400000>; + no-map; + }; + + sbl@4a500000 { + reg = <0x0 0x4a500000 0x0 0x100000>; + no-map; + }; + tz_mem: tz@4a600000 { reg = <0x0 0x4a600000 0x0 0x200000>; no-map; @@ -121,7 +131,7 @@ tz_mem: tz@4a600000 { smem@4a800000 { compatible = "qcom,smem"; - reg = <0x0 0x4a800000 0x0 0x00100000>; + reg = <0x0 0x4a800000 0x0 0x100000>; no-map; hwlocks = <&tcsr_mutex 0>; -- GitLab From ebdcfc8c42c2b9d5ca1b27d8ee558eefb3e904d8 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Fri, 19 May 2023 20:07:28 +0200 Subject: [PATCH 687/926] arm64: dts: adapt to LP855X bindings changes Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber Reviewed-by: Daniel Thompson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519180728.2281-5-aweber.kernel@gmail.com --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 38f4ff229beff..a6a58e51822d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -58,19 +58,17 @@ backlight: backlight@2c { dev-ctrl = /bits/ 8 <0x80>; init-brt = /bits/ 8 <0xff>; - pwm-period = <29334>; - pwms = <&pwm 0 29334>; pwm-names = "lp8557"; /* boost frequency 1 MHz */ - rom_13h { + rom-13h { rom-addr = /bits/ 8 <0x13>; rom-val = /bits/ 8 <0x01>; }; /* 3 LED string */ - rom_14h { + rom-14h { rom-addr = /bits/ 8 <0x14>; rom-val = /bits/ 8 <0x87>; }; -- GitLab From 21c9c7af1b37f3b38960f6abaf1b0b43f9db2467 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 22 May 2023 20:42:06 +0530 Subject: [PATCH 688/926] arm64: dts: qcom: qdu1000: Add IMEM and PIL info region Add a simple-mfd representing IMEM on QDU1000 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230522151206.22654-3-quic_kbajaj@quicinc.com --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 471a5741396c2..2914bbc25e41c 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1102,6 +1102,19 @@ qup_spi15_cs: qup-spi15-cs-state { }; }; + sram@14680000 { + compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x1000>; + ranges = <0 0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; -- GitLab From 35e237b3d59941cff839de2d4089db60fac4679f Mon Sep 17 00:00:00 2001 From: Anusha Rao Date: Fri, 26 May 2023 21:41:26 +0530 Subject: [PATCH 689/926] dt-bindings: clock: Add crypto clock and reset definitions Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma Signed-off-by: Anusha Rao Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526161129.1454-2-quic_anusha@quicinc.com --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 + 2 files changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 5a2961bfe8934..b32a7aa65349d 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -210,4 +210,8 @@ #define GCC_SNOC_PCIE1_1LANE_S_CLK 201 #define GCC_SNOC_PCIE2_2LANE_S_CLK 202 #define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#define GCC_CRYPTO_CLK_SRC 204 +#define GCC_CRYPTO_CLK 205 +#define GCC_CRYPTO_AXI_CLK 206 +#define GCC_CRYPTO_AHB_CLK 207 #endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h index d01dc6a24cf1b..c709d103673d8 100644 --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -160,5 +160,6 @@ #define GCC_WCSS_Q6_BCR 151 #define GCC_WCSS_Q6_TBU_BCR 152 #define GCC_TCSR_BCR 153 +#define GCC_CRYPTO_BCR 154 #endif -- GitLab From ffadc79ed99f0f69e4cb74a4d158a18619ccd8ff Mon Sep 17 00:00:00 2001 From: Anusha Rao Date: Fri, 26 May 2023 21:41:29 +0530 Subject: [PATCH 690/926] arm64: dts: qcom: ipq9574: Enable crypto nodes Enable crypto support for ipq9574. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Anusha Rao Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526161129.1454-5-quic_anusha@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index dbf3057d936fb..57e1ecdc93d79 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -215,6 +215,26 @@ qfprom: efuse@a4000 { #size-cells = <1>; }; + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0073a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; -- GitLab From 4e6b053768020f2117caf27b5e062d1e0a06de0c Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 26 May 2023 22:50:20 +0100 Subject: [PATCH 691/926] arm64: dts: qcom: pmi8998: enable rradc by default There is no need for the RRADC to be disabled by default, lets just enable it by default and not clutter up DT. Acked-by: Konrad Dybcio Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524-pmi8998-charger-dts-v2-1-2a5c77d2ff0c@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ---- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 4 ---- 5 files changed, 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 062d56c42385e..68e634f8212cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -279,10 +279,6 @@ vol_keys_default: vol-keys-state { }; }; -&pmi8998_rradc { - status = "okay"; -}; - &qusb2phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 08e00819b39d1..71631bbb13c8f 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -23,8 +23,6 @@ pmi8998_rradc: adc@4500 { compatible = "qcom,pmi8998-rradc"; reg = <0x4500>; #io-channel-cells = <1>; - - status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 4dea2c04b22fa..0d79dbf60f468 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -685,10 +685,6 @@ led@5 { }; }; -&pmi8998_rradc { - status = "okay"; -}; - /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { dai@22 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 5c384345c05d2..55ee8dcf27c39 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -480,10 +480,6 @@ pinconf { }; }; -&pmi8998_rradc { - status = "okay"; -}; - &q6afedai { qi2s@22 { reg = <22>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 5ed975cc6ecba..1915643f1c49a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -346,10 +346,6 @@ &pm8998_resin { status = "okay"; }; -&pmi8998_rradc { - status = "okay"; -}; - /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { dai@22 { -- GitLab From 7711c35fd67c762d65fa802d06411e7bdbd3f748 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 26 May 2023 22:50:21 +0100 Subject: [PATCH 692/926] arm64: dts: qcom: pmi8998: add charger node Add a node for the smb2 charger hardware found on the pmi8998 pmic following the DT bindings. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524-pmi8998-charger-dts-v2-2-2a5c77d2ff0c@linaro.org --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 71631bbb13c8f..cd3f0790fd420 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -9,6 +9,26 @@ pmi8998_lsid0: pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmi8998_charger: charger@1000 { + compatible = "qcom,pmi8998-charger"; + reg = <0x1000>; + + interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usb-plugin", + "bat-ov", + "wdog-bark", + "usbin-icl-change"; + + io-channels = <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; + io-channel-names = "usbin_i", "usbin_v"; + + status = "disabled"; + }; + pmi8998_gpios: gpio@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; -- GitLab From 23cf50b13e0686cd9929f54f89580d7b22cbeb71 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 26 May 2023 22:50:22 +0100 Subject: [PATCH 693/926] arm64: dts: qcom: sdm845-oneplus: enable pmi8998 charger Enable the pmi8998 charger on both devices, enabling charging speeds above the default 500mA limit the bootloader sets. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524-pmi8998-charger-dts-v2-3-2a5c77d2ff0c@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 4 ++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 55ee8dcf27c39..364adf416c4f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -480,6 +480,10 @@ pinconf { }; }; +&pmi8998_charger { + status = "okay"; +}; + &q6afedai { qi2s@22 { reg = <22>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 6cdda971bb4bf..623a826b18a3e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -51,6 +51,10 @@ max98927_codec: max98927@3a { }; }; +&pmi8998_charger { + monitored-battery = <&battery>; +}; + &sound { model = "OnePlus 6"; audio-routing = "RX_BIAS", "MCLK", diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index d82c0d4407f06..9471ada0d6ad8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -47,6 +47,10 @@ &sound { "AMIC5", "MIC BIAS3"; }; +&pmi8998_charger { + monitored-battery = <&battery>; +}; + /* * The TFA9894 codec is currently unsupported. * We need to delete the node to allow the soundcard -- GitLab From e5d83d4d5cb9e00befb497fe8a64001ac1cce157 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Fri, 26 May 2023 22:50:23 +0100 Subject: [PATCH 694/926] arm64: dts: qcom: sdm845-shift-axolotl: enable pmi8998 charger Enable the PMI8998/smb2 charger, and denote the secondary SMB1355 charger which is used for parallel charging. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524-pmi8998-charger-dts-v2-4-2a5c77d2ff0c@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 1eaff964b202a..f1cfe5a1d172d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -494,6 +494,10 @@ touchscreen@38 { }; }; +&i2c10 { + /* SMB1355@0x0C */ +}; + &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; @@ -522,6 +526,12 @@ pinconf { }; }; +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; +}; + &pm8998_resin { linux,code = ; status = "okay"; -- GitLab From e58cf964157bb2f875155a2dcf68f3a8db0da2e3 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 26 May 2023 22:50:24 +0100 Subject: [PATCH 695/926] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable pmi8998 charger Enable the pmi8998 charger and define some basic battery properties. Signed-off-by: Joel Selvaraj Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524-pmi8998-charger-dts-v2-5-2a5c77d2ff0c@linaro.org --- .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 1915643f1c49a..f7fd897afe1e4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -115,6 +115,14 @@ rmtfs_mem: memory@f6301000 { }; }; + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; + vreg_s4a_1p8: vreg-s4a-1p8 { compatible = "regulator-fixed"; regulator-name = "vreg_s4a_1p8"; @@ -341,6 +349,12 @@ &pmi8998_wled { qcom,cabc; }; +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; +}; + &pm8998_resin { linux,code = ; status = "okay"; -- GitLab From 34354cc946abe6b6e4b71883dddfdd368e856d65 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sat, 27 May 2023 12:39:33 +0300 Subject: [PATCH 696/926] arm64: dts: qcom: msm8996pro: Add CBF scaling support Add opp-peak-kBps to CPU OPPs to allow for CBF scaling, and change the CBF compatible to reflect the difference between it and the one on MSM8996. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230527093934.101335-3-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi index a679a9c0cf99d..b74cff06f300d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -24,101 +24,121 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-supported-hw = <0x20>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2188800000 { opp-hz = /bits/ 64 <2188800000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; @@ -131,136 +151,163 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-748800000 { opp-hz = /bits/ 64 <748800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1286400>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1363200>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1440000>; }; opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2246400000 { opp-hz = /bits/ 64 <2246400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2342400000 { opp-hz = /bits/ 64 <2342400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; }; @@ -289,3 +336,7 @@ opp-560000000 { }; /* The rest is inherited from msm8996 */ }; + +&cbf { + compatible = "qcom,msm8996pro-cbf"; +}; -- GitLab From 7b8f119a24f40f4765b8318fb5f6c3feb7d1c713 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Fri, 19 May 2023 20:07:27 +0200 Subject: [PATCH 697/926] ARM: dts: qcom: adapt to LP855X bindings changes Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber Reviewed-by: Luca Weiss Reviewed-by: Daniel Thompson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519180728.2281-4-aweber.kernel@gmail.com --- .../dts/qcom-apq8026-samsung-matisse-wifi.dts | 1 - ...-msm8974pro-sony-xperia-shinano-castor.dts | 23 ++++++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts index 91b860e24681f..884d99297d4cf 100644 --- a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts @@ -99,7 +99,6 @@ backlight@2c { dev-ctrl = /bits/ 8 <0x80>; init-brt = /bits/ 8 <0x3f>; - pwm-period = <100000>; pwms = <&backlight_pwm 0 100000>; pwm-names = "lp8556"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 04bc58d87abf9..2396253f953af 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -150,47 +150,48 @@ lp8566_wled: backlight@2c { bl-name = "backlight"; dev-ctrl = /bits/ 8 <0x05>; init-brt = /bits/ 8 <0x3f>; - rom_a0h { + + rom-a0h { rom-addr = /bits/ 8 <0xa0>; rom-val = /bits/ 8 <0xff>; }; - rom_a1h { + rom-a1h { rom-addr = /bits/ 8 <0xa1>; rom-val = /bits/ 8 <0x3f>; }; - rom_a2h { + rom-a2h { rom-addr = /bits/ 8 <0xa2>; rom-val = /bits/ 8 <0x20>; }; - rom_a3h { + rom-a3h { rom-addr = /bits/ 8 <0xa3>; rom-val = /bits/ 8 <0x5e>; }; - rom_a4h { + rom-a4h { rom-addr = /bits/ 8 <0xa4>; rom-val = /bits/ 8 <0x02>; }; - rom_a5h { + rom-a5h { rom-addr = /bits/ 8 <0xa5>; rom-val = /bits/ 8 <0x04>; }; - rom_a6h { + rom-a6h { rom-addr = /bits/ 8 <0xa6>; rom-val = /bits/ 8 <0x80>; }; - rom_a7h { + rom-a7h { rom-addr = /bits/ 8 <0xa7>; rom-val = /bits/ 8 <0xf7>; }; - rom_a9h { + rom-a9h { rom-addr = /bits/ 8 <0xa9>; rom-val = /bits/ 8 <0x80>; }; - rom_aah { + rom-aah { rom-addr = /bits/ 8 <0xaa>; rom-val = /bits/ 8 <0x0f>; }; - rom_aeh { + rom-aeh { rom-addr = /bits/ 8 <0xae>; rom-val = /bits/ 8 <0x0f>; }; -- GitLab From 56d3067cb694ba60d654e7f5ef231b6fabc4697f Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 7 Jun 2023 20:44:48 +0200 Subject: [PATCH 698/926] arm64: dts: qcom: ipq8074: add critical thermal trips According to bindings, thermal zones must have associated trips as well. Since we currently dont have CPUFreq support and thus no passive cooling lets start by defining critical trips to protect the devices against severe overheating. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 40565ce635dd9..2723a7a50e2be 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -932,6 +932,14 @@ nss-top-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 4>; + + trips { + nss-top-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; nss0-thermal { @@ -939,6 +947,14 @@ nss0-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 5>; + + trips { + nss-0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; nss1-thermal { @@ -946,6 +962,14 @@ nss1-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 6>; + + trips { + nss-1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phya0-thermal { @@ -953,6 +977,14 @@ wcss-phya0-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 7>; + + trips { + wcss-phya0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phya1-thermal { @@ -960,6 +992,14 @@ wcss-phya1-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 8>; + + trips { + wcss-phya1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu0_thermal: cpu0-thermal { @@ -967,6 +1007,14 @@ cpu0_thermal: cpu0-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 9>; + + trips { + cpu0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu1_thermal: cpu1-thermal { @@ -974,6 +1022,14 @@ cpu1_thermal: cpu1-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 10>; + + trips { + cpu1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu2_thermal: cpu2-thermal { @@ -981,6 +1037,14 @@ cpu2_thermal: cpu2-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 11>; + + trips { + cpu2-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cpu3_thermal: cpu3-thermal { @@ -988,6 +1052,14 @@ cpu3_thermal: cpu3-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 12>; + + trips { + cpu3-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; cluster_thermal: cluster-thermal { @@ -995,6 +1067,14 @@ cluster_thermal: cluster-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 13>; + + trips { + cluster-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phyb0-thermal { @@ -1002,6 +1082,14 @@ wcss-phyb0-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 14>; + + trips { + wcss-phyb0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; wcss-phyb1-thermal { @@ -1009,6 +1097,14 @@ wcss-phyb1-thermal { polling-delay = <1000>; thermal-sensors = <&tsens 15>; + + trips { + wcss-phyb1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; }; }; -- GitLab From 2e0580e10e919b544d7be1b2b8fc48fc7dff1322 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Wed, 7 Jun 2023 14:23:09 +0530 Subject: [PATCH 699/926] arm64: dts: qcom: ipq9574: add tsens node IPQ9574 has a tsens v2.3.1 peripheral which monitors temperatures around the various subsystems on the die. Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/00fa16039db78dcb919bd15444bbf86ff3a340d6.1686125196.git.quic_varada@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 57e1ecdc93d79..5ae22aa4e1e1e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -235,6 +235,16 @@ crypto: crypto@73a000 { dma-names = "rx", "tx"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>; -- GitLab From 581dcbe60b6390c633f318a29db41d1df642e6d8 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Wed, 7 Jun 2023 14:23:10 +0530 Subject: [PATCH 700/926] arm64: dts: qcom: ipq9574: add thermal zone nodes This patch adds thermal zone nodes for the various sensors present in IPQ9574 Reviewed-by: Dmitry Baryshkov Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/404c88e9746b3f25585aef078861ec2c273232d5.1686125196.git.quic_varada@quicinc.com --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 208 ++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5ae22aa4e1e1e..bb71e599fbe41 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -621,6 +621,214 @@ frame@b128000 { }; }; + thermal-zones { + nss-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + ubi_0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + ubi_1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + ubi_2-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + ubi_3-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wcss-phyb-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + wcss_phyb-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top_glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- GitLab From abc49a7c6035c57ece0642811f70a7a3892badb6 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Wed, 7 Jun 2023 01:00:20 -0400 Subject: [PATCH 701/926] dt-bindings: arm: qcom: Add Samsung Galaxy Express Add a compatible for Samsung Galaxy Express SGH-I437. Signed-off-by: Rudraksha Gupta Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230607050025.86636-2-guptarud@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index e6193be733297..ffe3c881fa683 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -198,6 +198,7 @@ properties: - items: - enum: - qcom,msm8960-cdp + - samsung,expressatt - const: qcom,msm8960 - items: -- GitLab From 80ce22e5cbe705ff2e113890828d44aa0b3ad96f Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Wed, 7 Jun 2023 01:00:22 -0400 Subject: [PATCH 702/926] ARM: dts: qcom: msm8960: Add USB node Add the required nodes to support USB on the MSM8960 SoC. As it's very similar to the APQ8064 SoC, the nodes are almost identical Add a label to sleep_clk for the USB node to reference Signed-off-by: Rudraksha Gupta Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230607050025.86636-4-guptarud@gmail.com --- arch/arm/boot/dts/qcom-msm8960.dtsi | 34 ++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 2a668cd535cce..581b3ab5c4ca2 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -71,7 +72,7 @@ pxo_board: pxo_board { clock-output-names = "pxo_board"; }; - sleep_clk { + sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -370,5 +371,36 @@ gsbi1_spi: spi@16080000 { status = "disabled"; }; }; + + usb1: usb@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x200>, + <0x12500200 0x200>; + interrupts = ; + clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; + assigned-clock-rates = <60000000>; + resets = <&gcc USB_HS1_RESET>; + reset-names = "core"; + phy_type = "ulpi"; + ahb-burst-config = <0>; + phys = <&usb_hs1_phy>; + phy-names = "usb-phy"; + #reset-cells = <1>; + status = "disabled"; + + ulpi { + usb_hs1_phy: phy { + compatible = "qcom,usb-hs-phy-msm8960", + "qcom,usb-hs-phy"; + clocks = <&sleep_clk>, <&cxo_board>; + clock-names = "sleep", "ref"; + resets = <&usb1 0>; + reset-names = "por"; + #phy-cells = <0>; + }; + }; + }; }; }; -- GitLab From 2b01dda16124696c4b64edcd31e8c2d37c559998 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Wed, 7 Jun 2023 01:00:23 -0400 Subject: [PATCH 703/926] ARM: dts: qcom: Add Samsung Galaxy Express support Add a very basic device tree file for the Samsung Galaxy Express SGH-I437. Currently, the following things work: UART, eMMC, SD Card, and USB. Signed-off-by: Rudraksha Gupta Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230607050025.86636-5-guptarud@gmail.com --- arch/arm/boot/dts/Makefile | 1 + .../dts/qcom-msm8960-samsung-expressatt.dts | 331 ++++++++++++++++++ 2 files changed, 332 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..12c90f2631429 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1081,6 +1081,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8916-samsung-grandmax.dtb \ qcom-msm8916-samsung-serranove.dtb \ qcom-msm8960-cdp.dtb \ + qcom-msm8960-samsung-expressatt.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts new file mode 100644 index 0000000000000..13e85c2874987 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +#include "qcom-msm8960.dtsi" +#include + +/ { + model = "Samsung Galaxy Express SGH-I437"; + compatible = "samsung,expressatt", "qcom,msm8960"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi5_serial; + mmc0 = &sdcc1; /* SDCC1 eMMC slot */ + mmc1 = &sdcc3; /* SDCC3 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi5_serial { + status = "okay"; +}; + +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + status = "okay"; +}; + +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + vqmmc-supply = <&pm8921_l7>; + status = "okay"; +}; + +&gsbi1 { + qcom,mode = ; + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gsbi1_spi { + status = "okay"; +}; + +&msmgpio { + spi1_default: spi1-default-state { + mosi-pins { + pins = "gpio6"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + miso-pins { + pins = "gpio7"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk-pins { + pins = "gpio9"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; -- GitLab From 4acf7eceed31c56cf4baf11d43ee91255685f89a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 7 Jun 2023 01:04:19 +0200 Subject: [PATCH 704/926] arm64: dts: qcom: qcm2290: Add CPU idle states Add the (scarce) idle states for the individual CPUs, as well as the whole cluster. This enables deeper-than-WFI cpuidle Signed-off-by: Konrad Dybcio Reviewed-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230606-topic-qcm2290_idlestates-v2-1-580a5a2d28c9@linaro.org --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index ae5abc76bcc78..82de2f8a6180a 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -48,6 +48,8 @@ CPU0: cpu@0 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -64,6 +66,8 @@ CPU1: cpu@1 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -76,6 +80,8 @@ CPU2: cpu@2 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -88,6 +94,8 @@ CPU3: cpu@3 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu-map { @@ -109,6 +117,30 @@ core3 { }; }; }; + + domain-idle-states { + CLUSTER_SLEEP: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000043>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + }; }; firmware { @@ -134,6 +166,35 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; reserved_memory: reserved-memory { -- GitLab From 223ce29c8b7e5b00f01a68387aabeefd77d97f06 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Tue, 6 Jun 2023 23:14:18 +0200 Subject: [PATCH 705/926] arm64: dts: qcom: sm8250-edo: Panel framebuffer is 2.5k instead of 4k The framebuffer configuration for edo pdx203, written in edo dtsi (which is overwritten in pdx206 dts for its smaller panel) has to use a 1096x2560 configuration as this is what the panel (and framebuffer area) has been initialized to. Downstream userspace also has access to (and uses) this 2.5k mode by default, and only switches the panel to 4k when requested. This is similar to commit be8de06dc397 ("arm64: dts: qcom: sm8150-kumano: Panel framebuffer is 2.5k instead of 4k") which fixed the same for the previous generation Sony platform. Fixes: 69cdb97ef652 ("arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform)") Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230606211418.587676-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 8d4352c8c5431..8ab82bacba81f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -26,9 +26,10 @@ chosen { framebuffer: framebuffer@9c000000 { compatible = "simple-framebuffer"; reg = <0 0x9c000000 0 0x2300000>; - width = <1644>; - height = <3840>; - stride = <(1644 * 4)>; + /* pdx203 BL initializes in 2.5k mode, not 4k */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; format = "a8r8g8b8"; /* * That's a lot of clocks, but it's necessary due -- GitLab From 97c289026c62f80933b44353904b919572175f61 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:11 +0300 Subject: [PATCH 706/926] arm64: dts: qcom: sm8150: Use 2 interconnect cells Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-1-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 60 ++++++++++++++-------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2a5b2b99968a4..768c0f1f66aa9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -55,8 +55,8 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -82,8 +82,8 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -105,8 +105,8 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -128,8 +128,8 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -151,8 +151,8 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -174,8 +174,8 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -197,8 +197,8 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -220,8 +220,8 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -1751,49 +1751,49 @@ spi15: spi@c94000 { config_noc: interconnect@1500000 { compatible = "qcom,sm8150-config-noc"; reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8150-system-noc"; reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163a000 { compatible = "qcom,sm8150-mc-virt"; reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8150-aggre1-noc"; reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8150-aggre2-noc"; reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1720000 { compatible = "qcom,sm8150-compute-noc"; reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8150-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2111,7 +2111,7 @@ crypto: crypto@1dfa000 { <&apps_smmu 0x506 0x0011>, <&apps_smmu 0x508 0x0011>, <&apps_smmu 0x512 0x0000>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "memory"; }; @@ -3538,14 +3538,14 @@ opp-202000000 { dc_noc: interconnect@9160000 { compatible = "qcom,sm8150-dc-noc"; reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9680000 { compatible = "qcom,sm8150-gem-noc"; reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3650,7 +3650,7 @@ usb_2_dwc3: usb@a800000 { camnoc_virt: interconnect@ac00000 { compatible = "qcom,sm8150-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3659,8 +3659,8 @@ mdss: display-subsystem@ae00000 { reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; @@ -4325,7 +4325,7 @@ osm_l3: interconnect@18321000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - #interconnect-cells = <1>; + #interconnect-cells = <2>; }; cpufreq_hw: cpufreq@18323000 { -- GitLab From c2998e9a42637cdab699a21aa75a8cb5a7cbce72 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:12 +0300 Subject: [PATCH 707/926] arm64: dts: qcom: sm8150: Add missing interconnect paths to USB HCs The USB HCs nodes are missing the interconnect paths, so add them. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-2-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 768c0f1f66aa9..3a98995c0f18f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3586,6 +3586,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3635,6 +3639,10 @@ usb_2: usb@a8f8800 { resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; -- GitLab From b5a12438325b9c0207ae4374a797368070cfb945 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:13 +0300 Subject: [PATCH 708/926] arm64: dts: qcom: sm8250: Use 2 interconnect cells Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-3-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 72 ++++++++++++++-------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e5c60a6e40747..c5787489b05ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -106,8 +106,8 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -137,8 +137,8 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -162,8 +162,8 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -187,8 +187,8 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -212,8 +212,8 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -237,8 +237,8 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -262,8 +262,8 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -287,8 +287,8 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, - <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -1789,49 +1789,49 @@ spi13: spi@a94000 { config_noc: interconnect@1500000 { compatible = "qcom,sm8250-config-noc"; reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8250-system-noc"; reg = <0 0x01620000 0 0x1c200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163d000 { compatible = "qcom,sm8250-mc-virt"; reg = <0 0x0163d000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8250-aggre1-noc"; reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8250-aggre2-noc"; reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1733000 { compatible = "qcom,sm8250-compute-noc"; reg = <0 0x01733000 0 0xa180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8250-mmss-noc"; reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -2260,7 +2260,7 @@ crypto: crypto@1dfa000 { <&apps_smmu 0x59f 0x0000>, <&apps_smmu 0x586 0x0011>, <&apps_smmu 0x596 0x0011>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "memory"; }; @@ -3693,21 +3693,21 @@ opp-202000000 { dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { compatible = "qcom,sm8250-gem-noc"; reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sm8250-npu-noc"; reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3837,8 +3837,8 @@ venus: video-codec@aa00000 { <&videocc VIDEO_CC_MVS0_CLK>; clock-names = "iface", "core", "vcodec0_core"; - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, - <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, + <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "cpu-cfg", "video-mem"; iommus = <&apps_smmu 0x2100 0x0400>; @@ -4122,10 +4122,10 @@ camss: camss@ac6a000 { <&apps_smmu 0xc40 0x400>, <&apps_smmu 0xc41 0x400>; - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, - <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; + interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "cam_ahb", "cam_hf_0_mnoc", "cam_sf_0_mnoc", @@ -4182,8 +4182,8 @@ mdss: display-subsystem@ae00000 { reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, - <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; @@ -5671,7 +5671,7 @@ epss_l3: interconnect@18590000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - #interconnect-cells = <1>; + #interconnect-cells = <2>; }; cpufreq_hw: cpufreq@18591000 { -- GitLab From fd62fd1cf9e7fb7ef761e411d37cb5d06769954b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:14 +0300 Subject: [PATCH 709/926] arm64: dts: qcom: sm8250: Add missing interconnect paths to USB HCs The USB HCs nodes are missing the interconnect paths, so add them. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-4-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c5787489b05ca..08ea6396d364f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3750,6 +3750,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3810,6 +3814,10 @@ usb_2: usb@a8f8800 { resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; -- GitLab From 8b51dc863baf1447e9ab52411c5bed7ef9a56d80 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:15 +0300 Subject: [PATCH 710/926] arm64: dts: qcom: sm8350: Add missing interconnect paths to USB HCs The USB HCs nodes are missing the interconnect paths, so add them. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-5-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d2024ba5a754f..39d0b347cbf76 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2295,6 +2295,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -2364,6 +2368,10 @@ usb_2: usb@a8f8800 { resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; -- GitLab From b5b0649d5be4c82d09489492c121a7823323fc4a Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 2 Jun 2023 09:20:16 +0300 Subject: [PATCH 711/926] arm64: dts: qcom: sm8450: Add missing interconnect paths to USB HC The USB HC node is missing the interconnect paths, so add them. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230602062016.1883171-6-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index ca147bad902b2..79174e0d20a2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4297,6 +4297,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; -- GitLab From 90c8c4eb4bbb5e2e241fd5286bd43dd30a850b9d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 1 Jun 2023 16:41:27 +0530 Subject: [PATCH 712/926] arm64: dts: qcom: qdu1000: Add SDHCI node Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs. Also add required pins for SDHCI, so that the interface can work reliably. Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230601111128.19562-3-quic_kbajaj@quicinc.com --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 97 +++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 2914bbc25e41c..7153461d62d76 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -842,6 +842,53 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + sdhc: mmc@8804000 { + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>, + <0x0 0x08805000 0x0 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC5_AHB_CLK>, + <&gcc GCC_SDCC5_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC5_BCR>; + + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + power-domains = <&rpmhpd QDU1000_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + iommus = <&apps_smmu 0x80 0x0>; + dma-coherent; + + bus-width = <8>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <6528000 1652800>; + opp-avg-kBps = <400000 0>; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qdu1000-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; @@ -1100,6 +1147,56 @@ qup_spi15_cs: qup-spi15-cs-state { pins = "gpio31"; function = "gpio"; }; + + sdc_on_state: sdc-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc_off_state: sdc-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; }; sram@14680000 { -- GitLab From 6901ff9987469fa33d06990463adc8a63f8be5d0 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 1 Jun 2023 16:41:28 +0530 Subject: [PATCH 713/926] arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc Add sdhci node for emmc in qdu1000-idp. Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230601111128.19562-4-quic_kbajaj@quicinc.com --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 9e9fd4b8023e6..1d22f87fd238d 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -448,6 +448,29 @@ &qupv3_id_0 { status = "okay"; }; +&sdhc { + pinctrl-0 = <&sdc_on_state>; + pinctrl-1 = <&sdc_off_state>; + pinctrl-names = "default", "sleep"; + + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + non-removable; + no-sd; + no-sdio; + + supports-cqe; + + vmmc-supply = <&vreg_l10a_2p95>; + vqmmc-supply = <&vreg_l7a_1p8>; + + status = "okay"; +}; + &uart7 { status = "okay"; }; -- GitLab From 11a1397bbf69e408223bb691858a0fcd295a8f76 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 1 Jun 2023 13:38:17 +0300 Subject: [PATCH 714/926] arm64: dts: qcom: sm8550: Add missing interconnect path to USB HC The USB HC node is missing the interconnect paths, so add them. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230601103817.4066446-1-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a6be0b54ba00c..ccf21d99cb8ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2869,6 +2869,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnect-names = "usb-ddr", "apps-usb"; + status = "disabled"; usb_1_dwc3: usb@a600000 { -- GitLab From 852865530a21d139196106543cdf3e76c389659b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 17:04:24 +0200 Subject: [PATCH 715/926] arm64: dts: qcom: sm6375: Add GPUCC and Adreno SMMU Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU itself. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-sm6375_gpusmmu-v1-2-860943894c71@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index ae9b6bc446cbc..47f0499e6fa8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1258,6 +1259,42 @@ usb_1_dwc3: usb@4e00000 { }; }; + adreno_smmu: iommu@5940000 { + compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05940000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "bus"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + remoteproc_mss: remoteproc@6000000 { compatible = "qcom,sm6375-mpss-pas"; reg = <0 0x06000000 0 0x4040>; -- GitLab From add687cbfc3482ca74949b91b251e76792d25652 Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Wed, 31 May 2023 08:56:47 +0530 Subject: [PATCH 716/926] dt-bindings: arm: qcom: document AL02-C9 board based on IPQ9574 family Document AL02-C9 (Reference Design Platform 454) board based on IPQ9574 family of SoCs. Acked-by: Conor Dooley Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531032648.23816-2-quic_poovendh@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ffe3c881fa683..450f616774e09 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -91,6 +91,7 @@ description: | ap-al02-c6 ap-al02-c7 ap-al02-c8 + ap-al02-c9 ap-mi01.2 ap-mi01.3 ap-mi01.6 @@ -365,6 +366,7 @@ properties: - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 - qcom,ipq9574-ap-al02-c8 + - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 - description: Sierra Wireless MangOH Green with WP8548 Module -- GitLab From 2435d79033f5e7400195ed3b31585c0c053de553 Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Wed, 31 May 2023 08:56:48 +0530 Subject: [PATCH 717/926] arm64: dts: qcom: ipq9574: add support for RDP454 variant Add the initial device tree support for the Reference Design Platform (RDP) 454 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR and SMPA1 regulator node. Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531032648.23816-3-quic_poovendh@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 80 +++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c1573bba67292..337abc4ceb177 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts new file mode 100644 index 0000000000000..6efae3426cb84 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP454 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; -- GitLab From b9a0de7d5719aa54199da2932c1b1fdb948ff753 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:26:26 +0300 Subject: [PATCH 718/926] ARM: dts: qcom: apq8074-dragonboard: add onboard leds The dragonboard as three LEDs: red, green and blue. Add corresponding description. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531012627.3813060-2-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 72f7e09a5bbf1..baa372acbeb16 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" @@ -90,6 +91,29 @@ &mdss { status = "okay"; }; +&pm8941_lpg { + qcom,power-source = <1>; + status = "okay"; + + led@5 { + reg = <5>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@6 { + reg = <6>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + + led@7 { + reg = <7>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; +}; + &pm8941_wled { qcom,cs-out; qcom,switching-freq = <3200>; -- GitLab From 6198772ec4d9dcd2fea63b4020cef117a786d738 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:26:27 +0300 Subject: [PATCH 719/926] ARM: dts: qcom: apq8074-dragonboard: add gpio keys Add device nodes for gpio-keys (volume-up, general key) device nodes. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531012627.3813060-3-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index baa372acbeb16..d021cf7ae1c23 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include +#include #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" @@ -21,6 +23,26 @@ chosen { stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-0 = <&msm_keys_default>; + pinctrl-names = "default"; + + button-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + }; + + button-general { + label = "General"; + linux,code = ; + gpios = <&pm8941_gpios 23 GPIO_ACTIVE_LOW>; + }; + }; + reserved-memory { mpss_region: mpss@ac00000 { reg = <0x0ac00000 0x2500000>; @@ -91,6 +113,18 @@ &mdss { status = "okay"; }; +&pm8941_gpios { + msm_keys_default: pm8941-gpio-keys-state { + pins = "gpio5", "gpio23"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; +}; + &pm8941_lpg { qcom,power-source = <1>; status = "okay"; -- GitLab From 650c09daca4cac35ffd264ee1ca92521bdd9a5a9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:10 +0300 Subject: [PATCH 720/926] arm64: dts: qcom: sc7280: Don't disable MDP explicitly MDSS and all its subdevices are useless without DPU/MDP, so disabling MDP doesn't make any sense. Remove explicit disabling of the DPU device. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 2 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5b1c175c47f10..9ea6636125ad9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -467,10 +467,6 @@ &mdss_dp_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; -&mdss_mdp { - status = "okay"; -}; - /* NVMe drive, enabled on a per-board basis */ &pcie1 { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7c5dbac7ef772..f836b45de5083 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3872,8 +3872,6 @@ mdss_mdp: display-controller@ae01000 { interrupt-parent = <&mdss>; interrupts = <0>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; -- GitLab From 7116603bdb60b63f108662a5b36f99136e25c4d5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:11 +0300 Subject: [PATCH 721/926] arm64: dts: qcom: sm8350-hdk: remove useless enablement of mdss_mdp The MDP/DPU device is not disabled by default, so there is not point in enabling it in the board DTS file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index d3788bd72ac33..61dd9663fabe0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -424,10 +424,6 @@ mdss_dp0_out: endpoint { }; }; -&mdss_mdp { - status = "okay"; -}; - &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; -- GitLab From 6670bd9e42b43317b3f14dc4e97c3356d7602d63 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:12 +0300 Subject: [PATCH 722/926] arm64: dts: qcom: sm8450-hdk: remove useless enablement of mdss_mdp The MDP/DPU device is not disabled by default, so there is not point in enabling it in the board DTS file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index d5aeb7319776d..bc4c125d1832e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -568,10 +568,6 @@ mdss_dp0_out: endpoint { }; }; -&mdss_mdp { - status = "okay"; -}; - &pcie0 { status = "okay"; max-link-speed = <2>; -- GitLab From f82c8d2f00f6e04a1bc3ad6f0b971a83b02d0bfe Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:13 +0300 Subject: [PATCH 723/926] arm64: dts: qcom: qrb5165-rb5: remove useless enablement of mdss_mdp The MDP/DPU device is not disabled by default since the commit 0c25dad9f2a7 ("arm64: dts: qcom: sm8250: Don't disable MDP explicitly"), so there is not point in enabling it in the board DTS file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index dd924331b0eea..dfcaac2664567 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -639,10 +639,6 @@ &mdss { status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pm8150_adc { xo-therm@4c { reg = ; -- GitLab From 8b87d0585ca6ca0c646d685f29c9a25ade3cb95c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:14 +0300 Subject: [PATCH 724/926] arm64: dts: qcom: msm8953: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 40 +++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index f42a1e3763407..ddde5f2baeb81 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -764,10 +764,10 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "sleep", "dsi0pll", @@ -849,20 +849,20 @@ ports { port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@1a94000 { + mdss_dsi0: dsi@1a94000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a94000 0x400>; reg-names = "dsi_ctrl"; @@ -872,8 +872,8 @@ dsi0: dsi@1a94000 { assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -888,7 +888,7 @@ dsi0: dsi@1a94000 { "pixel", "core"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -901,20 +901,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@1a94400 { + mdss_dsi0_phy: phy@1a94400 { compatible = "qcom,dsi-phy-14nm-8953"; reg = <0x01a94400 0x100>, <0x01a94500 0x300>, @@ -932,7 +932,7 @@ dsi0_phy: phy@1a94400 { status = "disabled"; }; - dsi1: dsi@1a96000 { + mdss_dsi1: dsi@1a96000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x01a96000 0x400>; reg-names = "dsi_ctrl"; @@ -942,8 +942,8 @@ dsi1: dsi@1a96000 { assigned-clocks = <&gcc BYTE1_CLK_SRC>, <&gcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -958,7 +958,7 @@ dsi1: dsi@1a96000 { "pixel", "core"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -968,20 +968,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@1a96400 { + mdss_dsi1_phy: phy@1a96400 { compatible = "qcom,dsi-phy-14nm-8953"; reg = <0x01a96400 0x100>, <0x01a96500 0x300>, -- GitLab From 8b764ed0d04621cd3859a351c7d5cc14e87f6c4a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:15 +0300 Subject: [PATCH 725/926] arm64: dts: qcom: msm8996: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-7-dmitry.baryshkov@linaro.org --- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 30 ++++++++-------- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 22 ++++++------ .../boot/dts/qcom/msm8996-xiaomi-gemini.dts | 18 +++++----- arch/arm64/boot/dts/qcom/msm8996.dtsi | 36 +++++++++---------- .../dts/qcom/msm8996pro-xiaomi-natrium.dts | 18 +++++----- 5 files changed, 62 insertions(+), 62 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 2adadc1e5b7ca..ec5457508fe63 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -164,21 +164,6 @@ &camss { vdda-supply = <&vreg_l2a_1p25>; }; -&dsi0 { - vdda-supply = <&vreg_l2a_1p25>; - vcca-supply = <&vreg_l22a_3p0>; - status = "okay"; -}; - -&dsi0_out { - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vcca-supply = <&vreg_l28a_0p925>; - status = "okay"; -}; - &hsusb_phy1 { vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; @@ -201,6 +186,21 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l22a_3p0>; + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l28a_0p925>; + status = "okay"; +}; + &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 1ce5df0a34054..47f55c7311e92 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -235,7 +235,15 @@ bluetooth: bluetooth { }; }; -&dsi0 { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdd-supply = <&vreg_l2a_1p25>; @@ -246,26 +254,18 @@ &dsi0 { pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; }; -&dsi0_out { +&mdss_dsi0_out { status = "okay"; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vcca-supply = <&vreg_l28a_0p925>; }; -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 100123d514944..bdedcf9dff032 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -93,7 +93,13 @@ synaptics@20 { }; -&dsi0 { +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; + }; +}; + +&mdss_dsi0 { status = "okay"; vdd-supply = <&vreg_l2a_1p25>; @@ -112,22 +118,16 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; - }; -}; - &pmi8994_wled { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a3f49f21ec379..4772b53b80ad4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -889,10 +889,10 @@ mmcc: clock-controller@8c0000 { clocks = <&xo_board>, <&gcc GPLL0>, <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <&hdmi_phy>; clock-names = "xo", "gpll0", @@ -985,20 +985,20 @@ mdp5_intf3_out: endpoint { port@1 { reg = <1>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@994000 { + mdss_dsi0: dsi@994000 { compatible = "qcom,msm8996-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x00994000 0x400>; @@ -1022,9 +1022,9 @@ dsi0: dsi@994000 { "pixel", "core"; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; #address-cells = <1>; @@ -1036,20 +1036,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@994400 { + mdss_dsi0_phy: phy@994400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00994400 0x100>, <0x00994500 0x300>, @@ -1066,7 +1066,7 @@ dsi0_phy: phy@994400 { status = "disabled"; }; - dsi1: dsi@996000 { + mdss_dsi1: dsi@996000 { compatible = "qcom,msm8996-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x00996000 0x400>; @@ -1090,9 +1090,9 @@ dsi1: dsi@996000 { "pixel", "core"; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; #address-cells = <1>; @@ -1104,20 +1104,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@996400 { + mdss_dsi1_phy: phy@996400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00996400 0x100>, <0x00996500 0x300>, diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index d18d0b0eda95e..7957c8823f0d5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -39,7 +39,13 @@ touchscreen@20 { }; }; -&dsi0 { +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; + }; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l2a_1p25>; @@ -57,22 +63,16 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; }; -&gpu { - zap-shader { - firmware-name = "qcom/msm8996/natrium/a530_zap.mbn"; - }; -}; - &mss_pil { firmware-name = "qcom/msm8996/natrium/mba.mbn", "qcom/msm8996/natrium/modem.mbn"; -- GitLab From 2b616f86d51ba534ba41b175846e7f9b3afb6e15 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:16 +0300 Subject: [PATCH 726/926] arm64: dts: qcom: sc7180: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-8-dmitry.baryshkov@linaro.org --- .../boot/dts/qcom/sc7180-acer-aspire1.dts | 32 ++++++------ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 14 ++--- .../qcom/sc7180-trogdor-parade-ps8640.dtsi | 10 ++-- .../qcom/sc7180-trogdor-quackingstick-r0.dts | 2 +- .../qcom/sc7180-trogdor-quackingstick.dtsi | 52 +++++++++---------- .../dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 10 ++-- .../sc7180-trogdor-wormdingler-rev1-boe.dts | 2 +- .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 46 ++++++++-------- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 28 +++++----- arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++---- 10 files changed, 109 insertions(+), 109 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 2a80f4090085b..b637b4270f889 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -143,21 +143,6 @@ reg_tp_3p3: touchpad-regulator { }; }; -&dsi0 { - vdda-supply = <&vreg_l3c_1p2>; - status = "okay"; -}; - -&dsi0_out { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi_phy { - vdds-supply = <&vreg_l4a_0p8>; - status = "okay"; -}; - &i2c2 { clock-frequency = <400000>; status = "okay"; @@ -269,7 +254,7 @@ port@0 { reg = <0>; sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -313,6 +298,21 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l3c_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a_0p8>; + status = "okay"; +}; + &pm6150_adc { thermistor@4e { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index bd9ed03159cfb..546db0d906308 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -295,7 +295,11 @@ vreg_bob: bob { }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l3c_1p2>; @@ -314,7 +318,7 @@ panel@0 { port { panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; @@ -329,15 +333,11 @@ endpoint { }; }; -&dsi_phy { +&mdss_dsi0_phy { status = "okay"; vdds-supply = <&vreg_l4a_0p8>; }; -&mdss { - status = "okay"; -}; - &qfprom { vcc-supply = <&vreg_l11a_1p8>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index 5aa7949b53280..bede23369fede 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -46,10 +46,6 @@ &pp3300_dx_edp { /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&dsi0_out { - remote-endpoint = <&ps8640_in>; -}; - edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; @@ -74,7 +70,7 @@ ports { port@0 { reg = <0>; ps8640_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -102,6 +98,10 @@ panel_in_edp: endpoint { }; }; +&mdss_dsi0_out { + remote-endpoint = <&ps8640_in>; +}; + &tlmm { edp_brij_ps8640_rst: edp-brij-ps8640-rst-state { pins = "gpio11"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts index 5c81e44ed4a5a..0a7f2286b5418 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick-r0.dts @@ -15,7 +15,7 @@ / { compatible = "google,quackingstick-sku1537", "qcom,sc7180"; }; -&dsi_phy { +&mdss_dsi0_phy { qcom,phy-rescode-offset-top = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; qcom,phy-rescode-offset-bot = /bits/ 8 <(-13) (-13) (-13) (-13) (-13)>; qcom,phy-drive-ldo-level = <375>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 8e7b42f843d45..62ab6427dd65d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -52,7 +52,31 @@ keyboard-controller { }; }; -&dsi0 { +&gpio_keys { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&mdss_dsi0 { panel: panel@0 { /* Compatible will be filled in per-board */ reg = <0>; @@ -67,7 +91,7 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; @@ -82,30 +106,6 @@ endpoint { }; }; -&gpio_keys { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - &sdhc_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index e52b8776755db..b0c3be4c3bb48 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -27,10 +27,6 @@ &pp3300_dx_edp { /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&dsi0_out { - remote-endpoint = <&sn65dsi86_in>; -}; - edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; @@ -65,7 +61,7 @@ ports { port@0 { reg = <0>; sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -95,6 +91,10 @@ panel_in_edp: endpoint { }; }; +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in>; +}; + &tlmm { edp_brij_irq: edp-brij-irq-state { pins = "gpio11"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts index c5b0658bd6323..6eeead70d3eb3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev1-boe.dts @@ -17,7 +17,7 @@ / { compatible = "google,wormdingler-sku1024", "qcom,sc7180"; }; -&dsi_phy { +&mdss_dsi0_phy { qcom,phy-rescode-offset-top = /bits/ 8 <31 31 31 31 (-32)>; qcom,phy-rescode-offset-bot = /bits/ 8 <31 31 31 31 (-32)>; qcom,phy-drive-ldo-level = <450>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 262d6691abd95..2efa8a4bcda60 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -110,7 +110,28 @@ keyboard-controller { }; }; -&dsi0 { +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@1 { + compatible = "hid-over-i2c"; + reg = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + vddl-supply = <&pp1800_ts>; + }; +}; + +&mdss_dsi0 { panel: panel@0 { reg = <0>; @@ -126,7 +147,7 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; @@ -141,27 +162,6 @@ endpoint { }; }; -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@1 { - compatible = "hid-over-i2c"; - reg = <0x01>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - - post-power-on-delay-ms = <70>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - vddl-supply = <&pp1800_ts>; - }; -}; - &pm6150_adc { skin-temp-thermistor@4d { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 51d6c3502f3ff..805fe1275e970 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -705,20 +705,6 @@ &camcc { status = "disabled"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; -}; - -&dsi0_out { - data-lanes = <0 1 2 3>; -}; - -&dsi_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - ap_sar_sensor_i2c: &i2c5 { clock-frequency = <400000>; @@ -836,6 +822,20 @@ &mdss_dp_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + &pm6150_adc { charger-thermistor@4f { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index af90052c5a8a1..f1e949b3c1bef 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2996,7 +2996,7 @@ ports { port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; @@ -3033,7 +3033,7 @@ opp-460000000 { }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -3056,12 +3056,12 @@ dsi0: dsi@ae94000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; - phys = <&dsi_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -3074,14 +3074,14 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -3106,13 +3106,13 @@ opp-358000000 { }; }; - dsi_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", + reg-names = "dsi0_phy", + "dsi0_phy_lane", "dsi_pll"; #clock-cells = <1>; @@ -3203,8 +3203,8 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x200000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&dsi_phy 0>, - <&dsi_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", -- GitLab From 71c97412f1d77314434c4097b0ed12646a0403b0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:17 +0300 Subject: [PATCH 727/926] arm64: dts: qcom: sc7280: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-9-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f836b45de5083..4a7bf9704af14 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3879,7 +3879,7 @@ ports { port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; @@ -3964,14 +3964,14 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; -- GitLab From c3c466d9f305291366f0af0650e62bf8a6c31501 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:18 +0300 Subject: [PATCH 728/926] arm64: dts: qcom: sc8180x: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-10-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 33493032b6e5e..d3ae185356365 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2733,14 +2733,14 @@ dpu_intf0_out: endpoint { port@1 { reg = <1>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; @@ -2784,7 +2784,7 @@ opp-460000000 { }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -2808,7 +2808,7 @@ dsi0: dsi@ae94000 { operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC8180X_MMCX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; phy-names = "dsi"; status = "disabled"; @@ -2819,14 +2819,14 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -2851,7 +2851,7 @@ opp-358000000 { }; }; - dsi0_phy: dsi-phy@ae94400 { + mdss_dsi0_phy: dsi-phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -2870,7 +2870,7 @@ dsi0_phy: dsi-phy@ae94400 { status = "disabled"; }; - dsi1: dsi@ae96000 { + mdss_dsi1: dsi@ae96000 { compatible = "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -2894,7 +2894,7 @@ dsi1: dsi@ae96000 { operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC8180X_MMCX>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; phy-names = "dsi"; status = "disabled"; @@ -2905,20 +2905,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: dsi-phy@ae96400 { + mdss_dsi1_phy: dsi-phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, -- GitLab From 8e61d532370eb6946d97e39d270129e9442fb326 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:19 +0300 Subject: [PATCH 729/926] arm64: dts: qcom: sdm630: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-11-dmitry.baryshkov@linaro.org --- .../boot/dts/qcom/sda660-inforce-ifc6560.dts | 16 ++++++------- arch/arm64/boot/dts/qcom/sdm630.dtsi | 20 ++++++++-------- arch/arm64/boot/dts/qcom/sdm660.dtsi | 24 +++++++++---------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 7459525d99828..0b23d5bb3f26c 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -134,7 +134,7 @@ port@0 { reg = <0>; adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -183,25 +183,25 @@ bluetooth { }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l1a_1p225>; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&adv7533_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vcca-supply = <&vreg_l1b_0p925>; }; -&mdss { - status = "okay"; -}; - &mmss_smmu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index a7d475f23beaf..df944f2160e95 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1461,8 +1461,8 @@ mmcc: clock-controller@c8c0000 { <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, <0>, <0>, <0>, @@ -1534,7 +1534,7 @@ ports { port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; }; @@ -1570,7 +1570,7 @@ opp-412500000 { }; }; - dsi0: dsi@c994000 { + mdss_dsi0: dsi@c994000 { compatible = "qcom,sdm660-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c994000 0x400>; @@ -1584,8 +1584,8 @@ dsi0: dsi@c994000 { assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, - <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE0_CLK>, @@ -1606,7 +1606,7 @@ dsi0: dsi@c994000 { "pixel", "core"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1616,20 +1616,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@c994400 { + mdss_dsi0_phy: phy@c994400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c994400 0x100>, <0x0c994500 0x300>, diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index f0f27fc12c18e..f89b27c99f40c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -148,14 +148,14 @@ ports { port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; &mdss { - dsi1: dsi@c996000 { + mdss_dsi1: dsi@c996000 { compatible = "qcom,sdm660-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0c996000 0x400>; @@ -170,8 +170,8 @@ dsi1: dsi@c996000 { assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, - <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE1_CLK>, @@ -192,7 +192,7 @@ dsi1: dsi@c996000 { "pixel", "core"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -202,20 +202,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@c996400 { + mdss_dsi1_phy: phy@c996400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c996400 0x100>, <0x0c996500 0x300>, @@ -239,10 +239,10 @@ &mmcc { <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>; }; -- GitLab From 8fe25ba3ffec7e8e2345d0163990b77a4092e456 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:20 +0300 Subject: [PATCH 730/926] arm64: dts: qcom: sdm845: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-12-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 40 ++++---- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 98 +++++++++---------- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 86 ++++++++-------- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 76 +++++++------- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 76 +++++++------- .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 74 +++++++------- .../qcom/sdm845-xiaomi-beryllium-common.dtsi | 66 ++++++------- .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 76 +++++++------- arch/arm64/boot/dts/qcom/sdm845.dtsi | 36 +++---- 9 files changed, 314 insertions(+), 314 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index d05c511718df8..1ce413263b7f9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -636,25 +636,6 @@ src_pp600_s3c: smps3 { }; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - edp_brij_i2c: &i2c3 { status = "okay"; clock-frequency = <400000>; @@ -687,7 +668,7 @@ ports { port@0 { reg = <0>; sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -767,6 +748,25 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + /* * Cheza fw does not properly program the GPU aperture to allow the * GPU to update the SMMU pagetables for context switches. Work diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 0d79dbf60f468..d6b464cb61d6f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -415,53 +415,6 @@ &cdsp_pas { firmware-name = "qcom/sdm845/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - qcom,dual-dsi-mode; - qcom,master-dsi; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - -&dsi1 { - vdda-supply = <&vreg_l26a_1p2>; - - qcom,dual-dsi-mode; - - /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - - status = "okay"; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi1_phy { - vdds-supply = <&vreg_l1a_0p875>; - status = "okay"; -}; - &gcc { protected-clocks = , , @@ -517,7 +470,7 @@ port@0 { reg = <0>; lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -525,7 +478,7 @@ port@1 { reg = <1>; lt9611_b: endpoint { - remote-endpoint = <&dsi1_out>; + remote-endpoint = <&mdss_dsi1_out>; }; }; @@ -556,6 +509,53 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + qcom,master-dsi; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l26a_1p2>; + + qcom,dual-dsi-mode; + + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l1a_0p875>; + status = "okay"; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index d1440b790fa6d..b2d4336e764bf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -417,7 +417,43 @@ &cdsp_pas { firmware-name = "qcom/sdm845/cdsp.mdt"; }; -&dsi0 { +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/a630_zap.mbn"; + }; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&vdda_mipi_dsi0_1p2>; @@ -448,33 +484,33 @@ ports { port@0 { reg = <0>; truly_in_0: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; port@1 { reg = <1>; truly_in_1: endpoint { - remote-endpoint = <&dsi1_out>; + remote-endpoint = <&mdss_dsi1_out>; }; }; }; }; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi0_pll>; }; -&dsi1 { +&mdss_dsi1 { status = "okay"; vdda-supply = <&vdda_mipi_dsi1_1p2>; qcom,dual-dsi-mode; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; ports { port@1 { @@ -486,47 +522,11 @@ endpoint { }; }; -&dsi1_phy { +&mdss_dsi1_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi1_pll>; }; -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gmu { - status = "okay"; -}; - -&gpu { - status = "okay"; - - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&i2c10 { - status = "okay"; - clock-frequency = <400000>; -}; - -&ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 364adf416c4f0..122c7128dea9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -336,44 +336,6 @@ &cdsp_pas { firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - /* - * Both devices use different panels but all other properties - * are common. Compatible line is declared in device dts. - */ - display_panel: panel@0 { - status = "disabled"; - - reg = <0>; - - vddio-supply = <&vreg_l14a_1p88>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - &gcc { protected-clocks = , , @@ -452,6 +414,44 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + /* + * Both devices use different panels but all other properties + * are common. Compatible line is declared in device dts. + */ + display_panel: panel@0 { + status = "disabled"; + + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + /* Modem/wifi */ &mss_pil { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index f1cfe5a1d172d..dce0141f37190 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -411,44 +411,6 @@ &cdsp_pas { firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - panel@0 { - compatible = "visionox,rm69299-shift"; - status = "okay"; - reg = <0>; - vdda-supply = <&vreg_l14a_1p88>; - vdd3p3-supply = <&vreg_l28a_3p0>; - - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - port { - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in_0>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - &gcc { protected-clocks = , , @@ -509,6 +471,44 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + panel@0 { + compatible = "visionox,rm69299-shift"; + status = "okay"; + reg = <0>; + vdda-supply = <&vreg_l14a_1p88>; + vdd3p3-supply = <&vreg_l28a_3p0>; + + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 420ffede3e804..3bc187a066aeb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -368,43 +368,6 @@ &cdsp_pas { status = "okay"; }; -&dsi0 { - vdda-supply = <&vreg_l26a_1p2>; - status = "okay"; - - panel: panel@0 { - /* The compatible is assigned in device DTs. */ - reg = <0>; - - backlight = <&pmi8998_wled>; - vddio-supply = <&vreg_l14a_1p8>; - vsp-supply = <&lab>; - vsn-supply = <&ibb>; - panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; - pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; - pinctrl-names = "default", "sleep"; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vdds-supply = <&vreg_l1a_0p9>; - status = "okay"; -}; - &gcc { protected-clocks = , , @@ -515,6 +478,43 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l26a_1p2>; + status = "okay"; + + panel: panel@0 { + /* The compatible is assigned in device DTs. */ + reg = <0>; + + backlight = <&pmi8998_wled>; + vddio-supply = <&vreg_l14a_1p8>; + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1a_0p9>; + status = "okay"; +}; + &pm8998_gpios { focus_n: focus-n-state { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index f7fd897afe1e4..9d6faeb656244 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -231,39 +231,6 @@ &cdsp_pas { firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - display_panel: panel@0 { - reg = <0>; - vddio-supply = <&vreg_l14a_1p8>; - vddpos-supply = <&lab>; - vddneg-supply = <&ibb>; - - backlight = <&pmi8998_wled>; - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - status = "disabled"; - - port { - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in_0>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - &gcc { protected-clocks = , , @@ -306,6 +273,39 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + display_panel: panel@0 { + reg = <0>; + vddio-supply = <&vreg_l14a_1p8>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + backlight = <&pmi8998_wled>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + status = "disabled"; + + port { + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 576f0421824f4..6db12abaa88d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -373,44 +373,6 @@ &cdsp_pas { status = "okay"; }; -&dsi0 { - vdda-supply = <&vdda_mipi_dsi0_1p2>; - status = "okay"; - - display_panel: panel@0 { - compatible = "jdi,fhd-nt35596s"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - vddio-supply = <&vreg_l14a_1p8>; - backlight = <&pmi8998_wled>; - vddpos-supply = <&lab>; - vddneg-supply = <&ibb>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active>; - pinctrl-1 = <&sde_dsi_suspend>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&dsi0_phy { - vdds-supply = <&vdda_mipi_dsi0_pll>; - status = "okay"; -}; - &gcc { protected-clocks = , , @@ -505,6 +467,44 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + status = "okay"; + + display_panel: panel@0 { + compatible = "jdi,fhd-nt35596s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + vddio-supply = <&vreg_l14a_1p8>; + backlight = <&pmi8998_wled>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>; + pinctrl-1 = <&sde_dsi_suspend>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + status = "okay"; +}; + &mss_pil { firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cf5898b0c17f1..723c876666800 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4501,14 +4501,14 @@ dpu_intf0_out: endpoint { port@1 { reg = <1>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; @@ -4608,7 +4608,7 @@ opp-810000000 { }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -4630,12 +4630,12 @@ dsi0: dsi@ae94000 { "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -4648,20 +4648,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -4680,7 +4680,7 @@ dsi0_phy: phy@ae94400 { status = "disabled"; }; - dsi1: dsi@ae96000 { + mdss_dsi1: dsi@ae96000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; @@ -4702,12 +4702,12 @@ dsi1: dsi@ae96000 { "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -4720,20 +4720,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, @@ -4895,10 +4895,10 @@ dispcc: clock-controller@af00000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", -- GitLab From e47a7f571d57d383f345e85c47a05ef1801b278c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:21 +0300 Subject: [PATCH 731/926] arm64: dts: qcom: sm8250: rename labels for DSI nodes Currently in board files MDSS and DSI nodes stay apart, because labels for DSI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node labels from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-13-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 52 +++---- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 40 ++--- .../dts/qcom/sm8250-xiaomi-elish-common.dtsi | 138 +++++++++--------- arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++--- 4 files changed, 133 insertions(+), 133 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index dfcaac2664567..9022ad726741c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -535,30 +535,6 @@ &cdsp { firmware-name = "qcom/sm8250/cdsp.mbn"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l9a_1p2>; - -#if 0 - qcom,dual-dsi-mode; - qcom,master-dsi; -#endif - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l5a_0p88>; -}; - &gmu { status = "okay"; }; @@ -604,7 +580,7 @@ port@0 { reg = <0>; lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -613,7 +589,7 @@ port@1 { reg = <1>; lt9611_b: endpoint { - remote-endpoint = <&dsi1_out>; + remote-endpoint = <&mdss_dsi1_out>; }; }; #endif @@ -639,6 +615,30 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + +#if 0 + qcom,dual-dsi-mode; + qcom,master-dsi; +#endif + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; +}; + &pm8150_adc { xo-therm@4c { reg = ; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 1326c171fe728..cfbc4fc1eba92 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -311,25 +311,6 @@ &cdsp_pas { status = "okay"; }; -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - &gcc { protected-clocks = , , @@ -422,7 +403,7 @@ ports { port@0 { reg = <0>; sn65dsi86_in_a: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -475,6 +456,25 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index eaac000858946..b841ea9192aea 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -470,75 +470,6 @@ &cdsp { status = "okay"; }; -&dsi0 { - vdda-supply = <&vreg_l9a_1p2>; - qcom,dual-dsi-mode; - qcom,sync-dual-dsi; - qcom,master-dsi; - status = "okay"; - - display_panel: panel@0 { - reg = <0>; - vddio-supply = <&vreg_l14a_1p88>; - reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; - backlight = <&backlight>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - panel_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1{ - reg = <1>; - - panel_in_1: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; - }; -}; - -&dsi0_out { - data-lanes = <0 1 2>; - remote-endpoint = <&panel_in_0>; -}; - -&dsi0_phy { - vdds-supply = <&vreg_l5a_0p88>; - phy-type = ; - status = "okay"; -}; - -&dsi1 { - vdda-supply = <&vreg_l9a_1p2>; - qcom,dual-dsi-mode; - qcom,sync-dual-dsi; - /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; - status = "okay"; -}; - -&dsi1_out { - data-lanes = <0 1 2>; - remote-endpoint = <&panel_in_1>; -}; - -&dsi1_phy { - vdds-supply = <&vreg_l5a_0p88>; - phy-type = ; - status = "okay"; -}; - &gmu { status = "okay"; }; @@ -607,6 +538,75 @@ &mdss { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + qcom,master-dsi; + status = "okay"; + + display_panel: panel@0 { + reg = <0>; + vddio-supply = <&vreg_l14a_1p88>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_0: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + + panel_in_1: endpoint { + remote-endpoint = <&mdss_dsi1_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_0>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + +&mdss_dsi1 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + status = "okay"; +}; + +&mdss_dsi1_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_1>; +}; + +&mdss_dsi1_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + &pcie0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 08ea6396d364f..83ab6de459bc4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4242,14 +4242,14 @@ ports { port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; @@ -4279,7 +4279,7 @@ opp-460000000 { }; }; - dsi0: dsi@ae94000 { + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -4302,12 +4302,12 @@ dsi0: dsi@ae94000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -4320,14 +4320,14 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -4352,7 +4352,7 @@ opp-358000000 { }; }; - dsi0_phy: phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -4371,7 +4371,7 @@ dsi0_phy: phy@ae94400 { status = "disabled"; }; - dsi1: dsi@ae96000 { + mdss_dsi1: dsi@ae96000 { compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; @@ -4394,12 +4394,12 @@ dsi1: dsi@ae96000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8250_MMCX>; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -4412,20 +4412,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, @@ -4451,10 +4451,10 @@ dispcc: clock-controller@af00000 { power-domains = <&rpmhpd SM8250_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", -- GitLab From f43b6dc7d56ecbd96d8dfb3c3225c46e18f1b842 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:22 +0300 Subject: [PATCH 732/926] arm64: dts: qcom: msm8996: rename labels for HDMI nodes Currently in board files MDSS and HDMI nodes stay apart, because labels for HDMI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change HDMI node labels from hdmi_* to mdss_hdmi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-14-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 50 ++++++++++---------- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 6 +-- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 4 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 16 +++---- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index b599909c44639..537547b97459b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -208,25 +208,6 @@ &gpu { status = "okay"; }; -&hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - &hsusb_phy1 { status = "okay"; @@ -251,6 +232,25 @@ &mdss { status = "okay"; }; +&mdss_hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>; + pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&mdss_hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; @@ -433,28 +433,28 @@ sdc2_cd_off: sdc2-cd-off-state { drive-strength = <2>; }; - hdmi_hpd_active: hdmi-hpd-active-state { + mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <16>; }; - hdmi_hpd_suspend: hdmi-hpd-suspend-state { + mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <2>; }; - hdmi_ddc_active: hdmi-ddc-active-state { + mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; bias-pull-up; }; - hdmi_ddc_suspend: hdmi-ddc-suspend-state { + mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; @@ -1043,7 +1043,7 @@ cpu { }; }; - hdmi-dai-link { + mdss_hdmi-dai-link { link-name = "HDMI"; cpu { sound-dai = <&q6afedai HDMI_RX>; @@ -1054,7 +1054,7 @@ platform { }; codec { - sound-dai = <&hdmi 0>; + sound-dai = <&mdss_hdmi 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index ed2e2f6c6775a..ac6471d1db1f7 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -92,15 +92,15 @@ &gpu { status = "okay"; }; -&hdmi { +&mdss { status = "okay"; }; -&hdmi_phy { +&mdss_hdmi { status = "okay"; }; -&mdss { +&mdss_hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 596ad4c896f55..495d45a16e63a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -24,10 +24,10 @@ &blsp2_uart2 { status = "okay"; }; -&hdmi { +&mdss_hdmi { status = "okay"; }; -&hdmi_phy { +&mdss_hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4772b53b80ad4..e8152fa29d62a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -893,7 +893,7 @@ mmcc: clock-controller@8c0000 { <&mdss_dsi0_phy 0>, <&mdss_dsi1_phy 1>, <&mdss_dsi1_phy 0>, - <&hdmi_phy>; + <&mdss_hdmi_phy>; clock-names = "xo", "gpll0", "gcc_mmss_noc_cfg_ahb_clk", @@ -978,7 +978,7 @@ ports { port@0 { reg = <0>; mdp5_intf3_out: endpoint { - remote-endpoint = <&hdmi_in>; + remote-endpoint = <&mdss_hdmi_in>; }; }; @@ -1134,8 +1134,8 @@ mdss_dsi1_phy: phy@996400 { status = "disabled"; }; - hdmi: hdmi-tx@9a0000 { - compatible = "qcom,hdmi-tx-8996"; + mdss_hdmi: mdss_hdmi-tx@9a0000 { + compatible = "qcom,mdss_hdmi-tx-8996"; reg = <0x009a0000 0x50c>, <0x00070000 0x6158>, <0x009e0000 0xfff>; @@ -1158,7 +1158,7 @@ hdmi: hdmi-tx@9a0000 { "alt_iface", "extp"; - phys = <&hdmi_phy>; + phys = <&mdss_hdmi_phy>; #sound-dai-cells = <1>; status = "disabled"; @@ -1169,16 +1169,16 @@ ports { port@0 { reg = <0>; - hdmi_in: endpoint { + mdss_hdmi_in: endpoint { remote-endpoint = <&mdp5_intf3_out>; }; }; }; }; - hdmi_phy: phy@9a0600 { + mdss_hdmi_phy: phy@9a0600 { #phy-cells = <0>; - compatible = "qcom,hdmi-phy-8996"; + compatible = "qcom,mdss_hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, <0x009a0a00 0x124>, <0x009a0c00 0x124>, -- GitLab From d59b294874c7f51317dc7edfc12ff950260ed2b9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 31 May 2023 04:16:23 +0300 Subject: [PATCH 733/926] ARM: dts: qcom: msm8974: rename labels for DSI nodes Currently in board files MDSS and HDMI nodes stay apart, because labels for HDMI nodes do not have the mdss_ prefix. It was found that grouping all display-related notes is more useful. To keep all display-related nodes close in the board files, change DSI node aliases from dsi_* to mdss_dsi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531011623.3808538-15-dmitry.baryshkov@linaro.org --- .../arm/boot/dts/qcom-apq8074-dragonboard.dts | 16 ++++++--- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 16 ++++----- arch/arm/boot/dts/qcom-msm8974.dtsi | 36 +++++++++---------- .../boot/dts/qcom-msm8974pro-samsung-klte.dts | 24 ++++++------- 4 files changed, 50 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index d021cf7ae1c23..e0679436000bf 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -71,7 +71,15 @@ eeprom: eeprom@52 { }; }; -&dsi0 { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { vdda-supply = <&pm8941_l2>; vdd-supply = <&pm8941_l22>; vddio-supply = <&pm8941_l12>; @@ -88,18 +96,18 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vddio-supply = <&pm8941_l12>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index fea8a6be9021d..e2a7ab7de89b2 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -230,7 +230,11 @@ bluetooth { }; }; -&dsi0 { +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&pm8941_l2>; @@ -246,27 +250,23 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vddio-supply = <&pm8941_l12>; }; -&mdss { - status = "okay"; -}; - &pm8941_gpios { gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 7dcbe0810e346..21fae1f8966f9 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1836,10 +1836,10 @@ mmcc: clock-controller@fd8c0000 { <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&dsi0_phy 1>, - <&dsi0_phy 0>, - <&dsi1_phy 1>, - <&dsi1_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>; @@ -1904,20 +1904,20 @@ ports { port@0 { reg = <0>; mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; mdp5_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; + remote-endpoint = <&mdss_dsi1_in>; }; }; }; }; - dsi0: dsi@fd922800 { + mdss_dsi0: dsi@fd922800 { compatible = "qcom,msm8974-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; @@ -1927,7 +1927,7 @@ dsi0: dsi@fd922800 { interrupts = <4>; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -1944,7 +1944,7 @@ dsi0: dsi@fd922800 { "core", "core_mmss"; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1957,20 +1957,20 @@ ports { port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&mdp5_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; }; - dsi0_phy: phy@fd922a00 { + mdss_dsi0_phy: phy@fd922a00 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd922a00 0xd4>, <0xfd922b00 0x280>, @@ -1988,7 +1988,7 @@ dsi0_phy: phy@fd922a00 { status = "disabled"; }; - dsi1: dsi@fd922e00 { + mdss_dsi1: dsi@fd922e00 { compatible = "qcom,msm8974-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0xfd922e00 0x1f8>; @@ -1998,7 +1998,7 @@ dsi1: dsi@fd922e00 { interrupts = <4>; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2015,7 +2015,7 @@ dsi1: dsi@fd922e00 { "core", "core_mmss"; - phys = <&dsi1_phy>; + phys = <&mdss_dsi1_phy>; status = "disabled"; @@ -2028,20 +2028,20 @@ ports { port@0 { reg = <0>; - dsi1_in: endpoint { + mdss_dsi1_in: endpoint { remote-endpoint = <&mdp5_intf2_out>; }; }; port@1 { reg = <1>; - dsi1_out: endpoint { + mdss_dsi1_out: endpoint { }; }; }; }; - dsi1_phy: phy@fd923000 { + mdss_dsi1_phy: phy@fd923000 { compatible = "qcom,dsi-phy-28nm-hpm"; reg = <0xfd923000 0xd4>, <0xfd923100 0x280>, diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index b9698ffb66ca8..cfbcd521f74d5 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -329,7 +329,15 @@ bluetooth { }; }; -&dsi0 { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { status = "okay"; vdda-supply = <&pma8084_l2>; @@ -351,31 +359,23 @@ panel: panel@0 { port { panel_in: endpoint { - remote-endpoint = <&dsi0_out>; + remote-endpoint = <&mdss_dsi0_out>; }; }; }; }; -&dsi0_out { +&mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; }; -&dsi0_phy { +&mdss_dsi0_phy { status = "okay"; vddio-supply = <&pma8084_l12>; }; -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - &pma8084_gpios { gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio5"; -- GitLab From dfbda20dabaa1f284abd550035db5887384c8e4c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:22 +0200 Subject: [PATCH 734/926] arm64: dts: qcom: msm8916/39: Fix SD card detect pinctrl The current SD card detect pinctrl setup configures bias-pull-up for the "default" (active) case and bias-disable for the "sleep" case. Before commit b5c833b703cc ("mmc: sdhci-msm: Set IO pins in low power state during suspend") the pull up was permanently active. Since then it is only active when a valid SD card is inserted. This does not really make sense: For an active-low CD, the pull up is needed to pull the GPIO high when the card is not inserted. When the card gets inserted CD is shorted to ground (low). This means right now the pull-up is removed exactly when it is needed to detect the next card insertion. Generally, applying different bias for CD does not really make sense. It should always stay the same so card removals and insertions can be detected properly. The reason why card detection still works fine in practice is that most boards seem to have external pull up on the CD pin. However, this means that there is no need to configure an internal pull-up at all and we can keep bias-disable permanently. There are also some boards with different CD polarity (acer-a1-724) and with different GPIO number (huawei-g7). All in all this makes it obvious that the CD pin is board-specific and the pinctrl for it should be defined in the board DT. Move it to the boards that need it and use bias-disable permanently for the boards that seem to have external pull-up. The vendor device tree for msm8939-sony-xperia-kanuti-tulip suggests that it needs the internal pull-up permanently [1] so it gets bias-pull-up to be sure. [1]: https://github.com/sonyxperiadev/kernel/blob/57b5050e340f40a88e1ddb8d16fd9adb44418923/arch/arm/boot/dts/qcom/msm8939-kanuti_tulip.dtsi#L634-L636 Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-1-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 11 +++++++++-- .../arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 11 +++++++++-- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 11 +++++++++-- arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 11 +++++++++-- .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 11 +++++++++-- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 6 +++--- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 11 +++++++++-- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 17 ----------------- .../dts/qcom/msm8916-samsung-a2015-common.dtsi | 11 +++++++++-- .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 11 +++++++++-- .../dts/qcom/msm8916-samsung-j5-common.dtsi | 11 +++++++++-- .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 11 +++++++++-- arch/arm64/boot/dts/qcom/msm8939.dtsi | 14 -------------- 13 files changed, 93 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 56dfca61253e6..b8537fe576a8b 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -380,8 +380,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -642,6 +642,13 @@ &tlmm { "USR_LED_2_CTRL", /* GPIO 120 */ "SB_HS_ID"; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + tlmm_leds: tlmm-leds-state { pins = "gpio21", "gpio120"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 5025c08e48173..9846584daf647 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -142,8 +142,8 @@ &sdhc_1 { &sdhc_2 { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; @@ -184,6 +184,13 @@ gpio_keys_default: gpio-keys-default-state { bias-pull-up; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { reset-pins { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 7b629243ef0d7..4ad7d36cf3506 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -181,8 +181,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -276,6 +276,13 @@ proximity_int_default: proximity-int-default-state { bias-pull-up; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + ts_int_reset_default: ts-int-reset-default-state { pins = "gpio13", "gpio100"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index b8c217b04a3b9..33ca4e157cd59 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -150,8 +150,8 @@ &sdhc_2 { vmmc-supply = <®_sd_vmmc>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -205,6 +205,13 @@ sd_vmmc_en_default: sd-vmmc-en-default-state { bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { touch-pins { pins = "gpio13"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 56c42b0c97336..0d387d9507c33 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -136,8 +136,8 @@ &sdhc_1 { }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; @@ -184,6 +184,13 @@ gpio_leds_default: gpio-led-default-state { bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touchscreen_default: touchscreen-default-state { reset-pins { pins = "gpio12"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 175ca011998c6..39be7b6b1695c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -270,8 +270,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; /* * The Huawei device tree sets cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>. @@ -397,7 +397,7 @@ reg_lcd_en_default: reg-lcd-en-default-state { bias-disable; }; - sdhc2_cd_default: sdhc2-cd-default-state { + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio56"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index f23cfb2bf7934..04e598a436cb3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -135,8 +135,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -190,6 +190,13 @@ mag_reset_default: mag-reset-default-state { bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 1b60d42a13c7d..c2149bcf53c42 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -380,23 +380,6 @@ sdc2_data_off: data-off-pins { }; }; - pmx-sdc2-cd-pin-state { - sdc2_cd_on: cd-on-pins { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - sdc2_cd_off: cd-off-pins { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - cdc-pdm-lines-state { cdc_pdm_lines_act: pdm-lines-on-pins { pins = "gpio63", "gpio64", "gpio65", "gpio66", diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 895036fb6eb89..3c145a0aac99b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -273,8 +273,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -391,6 +391,13 @@ nfc_i2c_default: nfc-i2c-default-state { bias-disable; }; + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 94cfb3200496c..057ce62c03055 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -143,8 +143,8 @@ &sdhc_1 { }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; @@ -199,4 +199,11 @@ gpio_hall_sensor_default: gpio-hall-sensor-default-state { drive-strength = <2>; bias-disable; }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index f2a5800f1605b..36233a31b98be 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -107,8 +107,8 @@ &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; @@ -162,4 +162,11 @@ muic_int_default: muic-int-default-state { drive-strength = <2>; bias-disable; }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 85a8d8fe212ff..80e4f0a6eea1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -43,6 +43,13 @@ &mdss { }; &tlmm { + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; @@ -158,8 +165,8 @@ &sdhc_1 { }; &sdhc_2 { - pinctrl-0 = <&sdc2_default_state>; - pinctrl-1 = <&sdc2_sleep_state>; + pinctrl-0 = <&sdc2_default_state &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 0d9f8b951b66e..2cbd4baa9b959 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1138,13 +1138,6 @@ data-pins { bias-pull-up; drive-strength = <10>; }; - - cd-pins { - pins = "gpio38"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; }; sdc2_sleep_state: sdc2-sleep-state { @@ -1165,13 +1158,6 @@ data-pins { bias-pull-up; drive-strength = <2>; }; - - cd-pins { - pins = "gpio38"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; }; wcnss_pin_a: wcnss-active-state { -- GitLab From c943e4c58b2ffb0dcd497f8b12f284f5e8fc477e Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:23 +0200 Subject: [PATCH 735/926] arm64: dts: qcom: msm8916/39: Consolidate SDC pinctrl MSM8939 has the SDC pinctrl consolidated in two &sdcN_default and &sdcN_sleep states, while MSM8916 has all pins separated. Make this consistent by consolidating them for MSM8916 well. Use this as a chance to define default pinctrl in the SoC.dtsi and only let boards that add additional definitions (such as cd-gpios) override it. For MSM8939 just make the label consistent with the other pinctrl definitions (they do not have a _state suffix). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-2-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 8 +- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 3 - .../boot/dts/qcom/msm8916-acer-a1-724.dts | 8 +- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 8 +- .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 8 +- .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 8 +- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 8 +- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 9 --- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 8 +- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 74 +++++++++---------- .../qcom/msm8916-samsung-a2015-common.dtsi | 8 +- .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 8 +- .../dts/qcom/msm8916-samsung-j5-common.dtsi | 8 +- .../dts/qcom/msm8916-samsung-serranove.dts | 9 --- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 4 - .../dts/qcom/msm8916-wingtech-wt88047.dts | 9 --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++ .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 7 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 14 +++- 19 files changed, 72 insertions(+), 143 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index b8537fe576a8b..23e3b86186acd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -370,18 +370,14 @@ pm8916_l17: l17 { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index e783b0af355e1..107795bf7e5c2 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -253,9 +253,6 @@ pm8916_l18: l18 { }; &sdhc_1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_default_state>; - pinctrl-1 = <&sdc1_sleep_state>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 9846584daf647..5ad49fe999dba 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -133,17 +133,13 @@ &pm8916_vib { }; &sdhc_1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - status = "okay"; }; &sdhc_2 { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 4ad7d36cf3506..1c43f3d6a0b4b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -171,18 +171,14 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 33ca4e157cd59..92f6954817692 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -139,10 +139,6 @@ pm8916_l17: l17 { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { @@ -150,8 +146,8 @@ &sdhc_2 { vmmc-supply = <®_sd_vmmc>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index 0d387d9507c33..f4dbc515c47ad 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -128,16 +128,12 @@ &pm8916_vib { }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 39be7b6b1695c..abd409f10cfed 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -260,18 +260,14 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; /* * The Huawei device tree sets cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>. diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 9560ba632c6fb..97262b8519b36 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -242,19 +242,10 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 04e598a436cb3..9757182fba3e6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -125,18 +125,14 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index c2149bcf53c42..cbf0f3d311af0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -290,44 +290,41 @@ blsp_i2c6_sleep: blsp-i2c6-sleep-state { bias-disable; }; - pmx-sdc1-clk-state { - sdc1_clk_on: clk-on-pins { + sdc1_default: sdc1-default-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: clk-off-pins { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc1-cmd-state { - sdc1_cmd_on: cmd-on-pins { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc1_cmd_off: cmd-off-pins { - pins = "sdc1_cmd"; + data-pins { + pins = "sdc1_data"; bias-pull-up; - drive-strength = <2>; + drive-strength = <10>; }; }; - pmx-sdc1-data-state { - sdc1_data_on: data-on-pins { - pins = "sdc1_data"; + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc1_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <2>; }; - sdc1_data_off: data-off-pins { + data-pins { pins = "sdc1_data"; bias-pull-up; @@ -335,44 +332,41 @@ sdc1_data_off: data-off-pins { }; }; - pmx-sdc2-clk-state { - sdc2_clk_on: clk-on-pins { + sdc2_default: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - sdc2_clk_off: clk-off-pins { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc2-cmd-state { - sdc2_cmd_on: cmd-on-pins { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: cmd-off-pins { - pins = "sdc2_cmd"; + data-pins { + pins = "sdc2_data"; bias-pull-up; - drive-strength = <2>; + drive-strength = <10>; }; }; - pmx-sdc2-data-state { - sdc2_data_on: data-on-pins { - pins = "sdc2_data"; + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc2_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <2>; }; - sdc2_data_off: data-off-pins { + data-pins { pins = "sdc2_data"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 3c145a0aac99b..019bf73178fa6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -263,18 +263,14 @@ pm8916_l17: l17 { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 057ce62c03055..7943bb6191163 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -135,16 +135,12 @@ &pm8916_usbin { }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; &sdhc_2 { - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index 36233a31b98be..f4fd5d72b28bc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -97,18 +97,14 @@ &pm8916_resin { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_default>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 3637e7d80d0a0..15dc246e84e2b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -276,19 +276,10 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; /* diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index dafa5bd823289..004a129a2ee2b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -101,10 +101,6 @@ &pm8916_usbin { }; &sdhc_1 { - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; - pinctrl-names = "default", "sleep"; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 733917531218c..c94d36b386517 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -173,19 +173,10 @@ &pm8916_vib { &sdhc_1 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; }; &sdhc_2 { status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - non-removable; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index cc5d3cf647213..d777a4559d1db 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1561,6 +1561,9 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; mmc-ddr-1_8v; bus-width = <8>; non-removable; @@ -1579,6 +1582,9 @@ sdhc_2: mmc@7864900 { <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; bus-width = <4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 80e4f0a6eea1c..a9df8dab5481f 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -158,15 +158,12 @@ pm8916_l18: l18 { }; &sdhc_1 { - pinctrl-0 = <&sdc1_default_state>; - pinctrl-1 = <&sdc1_sleep_state>; - pinctrl-names = "default", "sleep"; status = "okay"; }; &sdhc_2 { - pinctrl-0 = <&sdc2_default_state &sdc2_cd_default>; - pinctrl-1 = <&sdc2_sleep_state &sdc2_cd_default>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; pinctrl-names = "default", "sleep"; cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 2cbd4baa9b959..1f79444bc250c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1080,7 +1080,7 @@ ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { }; }; - sdc1_default_state: sdc1-default-state { + sdc1_default: sdc1-default-state { clk-pins { pins = "sdc1_clk"; bias-disable; @@ -1100,7 +1100,7 @@ data-pins { }; }; - sdc1_sleep_state: sdc1-sleep-state { + sdc1_sleep: sdc1-sleep-state { clk-pins { pins = "sdc1_clk"; bias-disable; @@ -1120,7 +1120,7 @@ data-pins { }; }; - sdc2_default_state: sdc2-default-state { + sdc2_default: sdc2-default-state { clk-pins { pins = "sdc2_clk"; bias-disable; @@ -1140,7 +1140,7 @@ data-pins { }; }; - sdc2_sleep_state: sdc2-sleep-state { + sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; bias-disable; @@ -1632,6 +1632,9 @@ sdhc_1: mmc@7824900 { <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC1_BCR>; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; mmc-ddr-1_8v; bus-width = <8>; non-removable; @@ -1651,6 +1654,9 @@ sdhc_2: mmc@7864900 { <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; bus-width = <4>; status = "disabled"; }; -- GitLab From 6528e4a90b5105643fe4e748ae90e37dcb3a3502 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:24 +0200 Subject: [PATCH 736/926] arm64: dts: qcom: apq8016-sbc: Drop unneeded MCLK pinctrl GPIO116 is not connected (NC) on DB410c so there is no need to route MCLK there. The MSM8916 digital codec receives the MCLK internally without leaving the SoC through a GPIO. Cc: Srinivas Kandagatla Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-3-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 23e3b86186acd..dad7586712da6 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -385,8 +385,8 @@ &sdhc_2 { &sound { status = "okay"; - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; + pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus>; pinctrl-names = "default", "sleep"; model = "DB410c"; audio-routing = -- GitLab From 0d3a93b102829b22d104c4108ffc9d50f19a556d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:25 +0200 Subject: [PATCH 737/926] arm64: dts: qcom: msm8916/39: Cleanup audio pinctrl The audio pinctrl in MSM8916/MSM8939 is very similar but still has subtle differences, e.g. &cdc_pdm_lines_act on MSM8916 vs &cdc_pdm_lines_default on MSM8939. Make this consistent and use the chance to cleanup all of the audio pinctrl: Drop unneeded outer nodes and replace the names taken over from the vendor kernel with more clear ones that are similar to the actual pinctrl function. Cc: Srinivas Kandagatla Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-4-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 4 +- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 4 +- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 4 +- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 135 +++++++++--------- arch/arm64/boot/dts/qcom/msm8939.dtsi | 133 ++++++++--------- 5 files changed, 133 insertions(+), 147 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index dad7586712da6..f3d65a6061949 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -385,8 +385,8 @@ &sdhc_2 { &sound { status = "okay"; - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus>; + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; pinctrl-names = "default", "sleep"; model = "DB410c"; audio-routing = diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 107795bf7e5c2..2a39216ceef59 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -260,8 +260,8 @@ &sound { model = "apq8039-square-sndcard"; audio-routing = "AMIC2", "MIC BIAS Internal2"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cdc_pdm_lines_default>; - pinctrl-1 = <&cdc_pdm_lines_sleep>; + pinctrl-0 = <&cdc_pdm_default>; + pinctrl-1 = <&cdc_pdm_sleep>; internal-codec-playback-dai-link { link-name = "WCD"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index abd409f10cfed..4239c8fda11b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -295,8 +295,8 @@ &sound { "AMIC3", "MIC BIAS External1"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cdc_pdm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus>; + pinctrl-0 = <&cdc_pdm_default>; + pinctrl-1 = <&cdc_pdm_sleep>; primary-dai-link { link-name = "WCD"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index cbf0f3d311af0..2cfaed37cb59e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -374,95 +374,89 @@ data-pins { }; }; - cdc-pdm-lines-state { - cdc_pdm_lines_act: pdm-lines-on-pins { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; - drive-strength = <8>; - bias-disable; - }; - cdc_pdm_lines_sus: pdm-lines-off-pins { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; - drive-strength = <2>; - bias-pull-down; - }; + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + + drive-strength = <2>; + bias-pull-down; }; - ext-pri-tlmm-lines-state { - ext_pri_tlmm_lines_act: ext-pa-on-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; - ext_pri_tlmm_lines_sus: ext-pa-off-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + + drive-strength = <2>; + bias-disable; }; - ext-pri-ws-line-state { - ext_pri_ws_act: ext-pa-on-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; - drive-strength = <8>; - bias-disable; - }; - ext_pri_ws_sus: ext-pa-off-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + + drive-strength = <2>; + bias-disable; }; - ext-mclk-tlmm-lines-state { - ext_mclk_tlmm_lines_act: mclk-lines-on-pins { - pins = "gpio116"; - function = "pri_mi2s"; + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; - ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { - pins = "gpio116"; - function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + + drive-strength = <2>; + bias-disable; }; - /* secondary Mi2S */ - ext-sec-tlmm-lines-state { - ext_sec_tlmm_lines_act: tlmm-lines-on-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; - drive-strength = <8>; - bias-disable; - }; - ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; - drive-strength = <2>; - bias-disable; - }; + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + + drive-strength = <2>; + bias-disable; }; - cdc_dmic_lines_act: cdc-dmic-lines-on-state { + cdc_dmic_default: cdc-dmic-default-state { clk-pins { pins = "gpio0"; function = "dmic0_clk"; @@ -476,7 +470,8 @@ data-pins { drive-strength = <8>; }; }; - cdc_dmic_lines_sus: cdc-dmic-lines-off-state { + + cdc_dmic_sleep: cdc-dmic-sleep-state { clk-pins { pins = "gpio0"; function = "dmic0_clk"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 1f79444bc250c..de5f8681d18d1 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -969,23 +969,7 @@ cci0_default: cci0-default-state { bias-disable; }; - cdc_pdm_lines_default: pdm-lines-default-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - drive-strength = <8>; - bias-disable; - }; - - cdc_pdm_lines_sleep: pdm-lines-suspend-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - drive-strength = <2>; - bias-pull-down; - }; - - cdc_dmic_lines_act: cdc-dmic-lines-on-state { + cdc_dmic_default: cdc-dmic-default-state { clk-pins { pins = "gpio0"; function = "dmic0_clk"; @@ -999,7 +983,7 @@ data-pins { }; }; - cdc_dmic_lines_sus: cdc-dmic-lines-off-state { + cdc_dmic_sleep: cdc-dmic-sleep-state { clk-pins { pins = "gpio0"; function = "dmic0_clk"; @@ -1015,69 +999,76 @@ data-pins { }; }; - ext-mclk-tlmm-lines-state { - ext_mclk_tlmm_lines_act: mclk-lines-on-pins { - pins = "gpio116"; - function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; - ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { - pins = "gpio116"; - function = "pri_mi2s"; - drive-strength = <2>; - bias-disable; - }; + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; }; - ext-pri-tlmm-lines-state { - ext_pri_tlmm_lines_act: ext-pa-on-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - drive-strength = <8>; - bias-disable; - }; + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; - ext_pri_tlmm_lines_sus: ext-pa-off-pins { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; }; - ext-pri-ws-line-state { - ext_pri_ws_act: ext-pa-on-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; - drive-strength = <8>; - bias-disable; - }; + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; - ext_pri_ws_sus: ext-pa-off-pins { - pins = "gpio110"; - function = "pri_mi2s_ws"; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; }; - /* secondary Mi2S */ - ext-sec-tlmm-lines-state { - ext_sec_tlmm_lines_act: tlmm-lines-on-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - drive-strength = <8>; - bias-disable; - }; + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; - ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - drive-strength = <2>; - bias-disable; - }; + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; }; sdc1_default: sdc1-default-state { -- GitLab From b40de51e3b6737a7bd41045e0cd3f78b75c35b24 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:26 +0200 Subject: [PATCH 738/926] arm64: dts: qcom: msm8916/39: Rename wcnss pinctrl All the pinctrl now uses consistent _default/_sleep suffix so rename the WCNSS pinctrl to be named consistently. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-5-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 2cfaed37cb59e..bf7e664c8350c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -488,7 +488,7 @@ data-pins { }; }; - wcnss_pin_a: wcnss-active-state { + wcss_wlan_default: wcss-wlan-default-state { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d777a4559d1db..8d4a58551291d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1894,7 +1894,7 @@ wcnss: remoteproc@a204000 { qcom,smem-state-names = "stop"; pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; + pinctrl-0 = <&wcss_wlan_default>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index de5f8681d18d1..3c1505b69a6ba 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1151,7 +1151,7 @@ data-pins { }; }; - wcnss_pin_a: wcnss-active-state { + wcss_wlan_default: wcss-wlan-default-state { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; drive-strength = <6>; @@ -1963,7 +1963,7 @@ wcnss: remoteproc@a204000 { qcom,smem-state-names = "stop"; pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; + pinctrl-0 = <&wcss_wlan_default>; status = "disabled"; -- GitLab From 8734d3355079152dc3fdf628a3724f55603c796d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 30 May 2023 09:15:27 +0200 Subject: [PATCH 739/926] arm64: dts: qcom: msm8916: Drop msm8916-pins.dtsi MSM8916 and MSM8939 are pin-compatible and should have exactly the same pinctrl definitions. Still, having pinctrl separated to a -pins.dtsi is not typical anymore for Qualcomm platforms upstream. Since Bjorn specifically requested having the MSM8939 pinctrl inside msm8939.dtsi lets move the MSM8916 definitions to msm8916.dtsi as well to have a consistent location. While at it sort the nodes and drop unnecessary empty lines. Note that in almost all cases changes to MSM8916 pinctrl should also be applied to MSM8939 pinctrl (and vice versa). Right now they are back in sync again and completely identical. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-msm8916-pinctrl-v1-6-11f540b51c93@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 554 --------------------- arch/arm64/boot/dts/qcom/msm8916.dtsi | 481 +++++++++++++++++- 2 files changed, 479 insertions(+), 556 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8916-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi deleted file mode 100644 index bf7e664c8350c..0000000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ /dev/null @@ -1,554 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&tlmm { - - blsp_uart1_default: blsp-uart1-default-state { - /* TX, RX, CTS_N, RTS_N */ - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - - drive-strength = <16>; - bias-disable; - }; - - blsp_uart1_sleep: blsp-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_uart2_default: blsp-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - - drive-strength = <16>; - bias-disable; - }; - - blsp_uart2_sleep: blsp-uart2-sleep-state { - pins = "gpio4", "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi1_default: blsp-spi1-default-state { - spi-pins { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio2"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi1_sleep: blsp-spi1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi2_default: blsp-spi2-default-state { - spi-pins { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio6"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi2_sleep: blsp-spi2-sleep-state { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi3_default: blsp-spi3-default-state { - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio10"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi3_sleep: blsp-spi3-sleep-state { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi4_default: blsp-spi4-default-state { - spi-pins { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio14"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi4_sleep: blsp-spi4-sleep-state { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi5_default: blsp-spi5-default-state { - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio18"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi5_sleep: blsp-spi5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_spi6_default: blsp-spi6-default-state { - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - - drive-strength = <12>; - bias-disable; - }; - cs-pins { - pins = "gpio22"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp_spi6_sleep: blsp-spi6-sleep-state { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp_i2c1_default: blsp-i2c1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c1_sleep: blsp-i2c1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c2_default: blsp-i2c2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c2_sleep: blsp-i2c2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c3_default: blsp-i2c3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c3_sleep: blsp-i2c3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c4_default: blsp-i2c4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c4_sleep: blsp-i2c4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c5_default: blsp-i2c5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c5_sleep: blsp-i2c5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c6_default: blsp-i2c6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - - blsp_i2c6_sleep: blsp-i2c6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdc1_default: sdc1-default-state { - clk-pins { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <16>; - }; - cmd-pins { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - data-pins { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc1_sleep: sdc1-sleep-state { - clk-pins { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <2>; - }; - cmd-pins { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - data-pins { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_default: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <16>; - }; - cmd-pins { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - data-pins { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_sleep: sdc2-sleep-state { - clk-pins { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <2>; - }; - cmd-pins { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - data-pins { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - cdc_pdm_default: cdc-pdm-default-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <8>; - bias-disable; - }; - - cdc_pdm_sleep: cdc-pdm-sleep-state { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <2>; - bias-pull-down; - }; - - pri_mi2s_default: mi2s-pri-default-state { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_sleep: mi2s-pri-sleep-state { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - - pri_mi2s_ws_default: mi2s-pri-ws-default-state { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <2>; - bias-disable; - }; - - pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - - pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - - sec_mi2s_default: mi2s-sec-default-state { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - - sec_mi2s_sleep: mi2s-sec-sleep-state { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - - cdc_dmic_default: cdc-dmic-default-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <8>; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <8>; - }; - }; - - cdc_dmic_sleep: cdc-dmic-sleep-state { - clk-pins { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <2>; - bias-disable; - }; - data-pins { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <2>; - bias-disable; - }; - }; - - wcss_wlan_default: wcss-wlan-default-state { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - function = "wcss_wlan"; - - drive-strength = <6>; - bias-pull-up; - }; - - cci0_default: cci0-default-state { - pins = "gpio29", "gpio30"; - function = "cci_i2c"; - - drive-strength = <16>; - bias-disable; - }; - - camera_front_default: camera-front-default-state { - pwdn-pins { - pins = "gpio33"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio28"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk1-pins { - pins = "gpio27"; - function = "cam_mclk1"; - - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera-rear-default-state { - pwdn-pins { - pins = "gpio34"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst-pins { - pins = "gpio35"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk0-pins { - pins = "gpio26"; - function = "cam_mclk0"; - - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8d4a58551291d..21d54e6684e6f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -996,6 +996,485 @@ tlmm: pinctrl@1000000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + blsp_i2c1_default: blsp-i2c1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c1_sleep: blsp-i2c1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_default: blsp-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c2_sleep: blsp-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_default: blsp-i2c3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c3_sleep: blsp-i2c3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_default: blsp-i2c4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c4_sleep: blsp-i2c4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_default: blsp-i2c5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c5_sleep: blsp-i2c5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_default: blsp-i2c6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp_i2c6_sleep: blsp-i2c6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp_spi1_default: blsp-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi1_sleep: blsp-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi2_default: blsp-spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi2_sleep: blsp-spi2-sleep-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi3_default: blsp-spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi3_sleep: blsp-spi3-sleep-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi4_default: blsp-spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio14"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi4_sleep: blsp-spi4-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi5_default: blsp-spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi5_sleep: blsp-spi5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_spi6_default: blsp-spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp_spi6_sleep: blsp-spi6-sleep-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart1_default: blsp-uart1-default-state { + /* TX, RX, CTS_N, RTS_N */ + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart2_default: blsp-uart2-default-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart2_sleep: blsp-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio28"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk1-pins { + pins = "gpio27"; + function = "cam_mclk1"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins = "gpio34"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + rst-pins { + pins = "gpio35"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + mclk0-pins { + pins = "gpio26"; + function = "cam_mclk0"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + cdc_dmic_default: cdc-dmic-default-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <8>; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <8>; + }; + }; + + cdc_dmic_sleep: cdc-dmic-sleep-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; + drive-strength = <2>; + bias-disable; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_pdm_default: cdc-pdm-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <8>; + bias-disable; + }; + + cdc_pdm_sleep: cdc-pdm-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-pull-down; + }; + + pri_mi2s_default: mi2s-pri-default-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_sleep: mi2s-pri-sleep-state { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { + pins = "gpio116"; + function = "pri_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + pri_mi2s_ws_default: mi2s-pri-ws-default-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + + pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { + pins = "gpio110"; + function = "pri_mi2s_ws"; + drive-strength = <2>; + bias-disable; + }; + + sec_mi2s_default: mi2s-sec-default-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + sec_mi2s_sleep: mi2s-sec-sleep-state { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcss_wlan_default: wcss-wlan-default-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; }; gcc: clock-controller@1800000 { @@ -2191,5 +2670,3 @@ timer { ; }; }; - -#include "msm8916-pins.dtsi" -- GitLab From 1b118df488f2be09b846994a4135d57f634e564b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Tue, 30 May 2023 01:14:59 +0300 Subject: [PATCH 740/926] ARM: dts: qcom: pm8226: Add thermal sensor and thermal zone config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add thermal sensor, which is using on chip VADC channel to report PMIC die temperature. Also add the corresponding thermal zone. Signed-off-by: Matti Lehtimäki Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529221501.43455-2-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-pm8226.dtsi | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index 46ba84f86c9f1..3b8ad28cecb0d 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -4,6 +4,36 @@ #include #include +/ { + thermal-zones { + pm8226-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8226_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8226_0: pm8226@0 { compatible = "qcom,pm8226", "qcom,spmi-pmic"; @@ -55,6 +85,15 @@ smbb: charger@1000 { chg_otg: otg-vbus { }; }; + pm8226_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8226_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + pm8226_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; -- GitLab From 84e72ea467db83043858b48fcd97de4c9e68881a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Tue, 30 May 2023 01:15:00 +0300 Subject: [PATCH 741/926] ARM: dts: qcom: pm8841: Add thermal zone config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add thermal zone for the PMIC thermal sensor. Temperatures are based on downstream values, except for critical trip point where 140°C is used instead of 145°C due to limitations without a configured ADC. Signed-off-by: Matti Lehtimäki Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529221501.43455-3-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-pm8841.dtsi | 33 +++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index b5cdde034d188..3bf2ce5c86a64 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -2,6 +2,37 @@ #include #include + +/ { + thermal-zones { + pm8841-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8841_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <140000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8841_0: pm8841@4 { @@ -20,7 +51,7 @@ pm8841_mpps: mpps@a000 { #interrupt-cells = <2>; }; - temp-alarm@2400 { + pm8841_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; -- GitLab From 637cc974046abe5718bf045a1bc66a238778a145 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Tue, 30 May 2023 01:15:01 +0300 Subject: [PATCH 742/926] ARM: dts: qcom: pm8941: Add thermal zone config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add thermal zone for the PMIC thermal sensor. Signed-off-by: Matti Lehtimäki Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529221501.43455-4-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-pm8941.dtsi | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index a821f0368a289..b3e246bacd78c 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -3,6 +3,37 @@ #include #include + +/ { + thermal-zones { + pm8941-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8941_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "hot"; + }; + + crit { + temperature = <145000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8941_0: pm8941@0 { -- GitLab From 16a9fa7ab27b69be3a34b97ff8c7b034fcc73b88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sun, 7 May 2023 23:12:22 +0300 Subject: [PATCH 743/926] ARM: dts: qcom: msm8226: Add qfprom node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing QFPROM definition for MSM8226 SoC. Signed-off-by: Matti Lehtimäki Reviewed-by: Dmitry Baryshkov Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507201225.89694-5-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index ec1b72af80aac..cf6692ecc05f5 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -533,6 +533,13 @@ restart@fc4ab000 { reg = <0xfc4ab000 0x4>; }; + qfprom: qfprom@fc4bc000 { + compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + spmi_bus: spmi@fc4cf000 { compatible = "qcom,spmi-pmic-arb"; reg-names = "core", "intr", "cnfg"; -- GitLab From 0f8861c9fc7cc9af6d6f65d6657aa9cf2531b29c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sun, 7 May 2023 23:12:23 +0300 Subject: [PATCH 744/926] ARM: dts: qcom: msm8226: Add tsens node and related nvmem cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specify pre-parsed per-sensor calibration nvmem cells in the qfprom device node rather than parsing the whole data blob in the driver. Signed-off-by: Matti Lehtimäki Reviewed-by: Dmitry Baryshkov Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507201225.89694-6-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 113 ++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index cf6692ecc05f5..594daec6fc2b5 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -528,6 +528,34 @@ data-pins { }; }; + tsens: thermal-sensor@fc4a9000 { + compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2"; + #qcom,sensors = <6>; + interrupts = ; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; @@ -538,6 +566,91 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + tsens_base1: base1@1c1 { + reg = <0x1c1 0x2>; + bits = <5 8>; + }; + + tsens_s0_p1: s0-p1@1c2 { + reg = <0x1c2 0x2>; + bits = <5 6>; + }; + + tsens_s1_p1: s1-p1@1c4 { + reg = <0x1c4 0x1>; + bits = <0 6>; + }; + + tsens_s2_p1: s2-p1@1c4 { + reg = <0x1c4 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1c5 { + reg = <0x1c5 0x2>; + bits = <4 6>; + }; + + tsens_s4_p1: s4-p1@1c6 { + reg = <0x1c6 0x1>; + bits = <2 6>; + }; + + tsens_s5_p1: s5-p1@1c7 { + reg = <0x1c7 0x1>; + bits = <0 6>; + }; + + tsens_s6_p1: s6-p1@1ca { + reg = <0x1ca 0x2>; + bits = <4 6>; + }; + + tsens_base2: base2@1cc { + reg = <0x1cc 0x1>; + bits = <0 8>; + }; + + tsens_s0_p2: s0-p2@1cd { + reg = <0x1cd 0x1>; + bits = <0 6>; + }; + + tsens_s1_p2: s1-p2@1cd { + reg = <0x1cd 0x2>; + bits = <6 6>; + }; + + tsens_s2_p2: s2-p2@1ce { + reg = <0x1ce 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1cf { + reg = <0x1cf 0x1>; + bits = <2 6>; + }; + + tsens_s4_p2: s4-p2@446 { + reg = <0x446 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@447 { + reg = <0x447 0x1>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@44e { + reg = <0x44e 0x1>; + bits = <1 6>; + }; + + tsens_mode: mode@44f { + reg = <0x44f 0x1>; + bits = <5 3>; + }; }; spmi_bus: spmi@fc4cf000 { -- GitLab From 8d4236f62f3acbc6a0def79106c13fe7344d8238 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Sun, 7 May 2023 23:12:24 +0300 Subject: [PATCH 745/926] ARM: dts: qcom: msm8226: Add thermal zones node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add thermal zones present on MSM8226 SoC. Signed-off-by: Matti Lehtimäki Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230507201225.89694-7-matti.lehtimaki@gmail.com --- arch/arm/boot/dts/qcom-msm8226.dtsi | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 594daec6fc2b5..313a726f47047 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -799,6 +799,50 @@ reboot-mode { }; }; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = Date: Tue, 2 May 2023 18:15:25 -0500 Subject: [PATCH 746/926] arm64: dts: ti: k3-j784s4-main: Add R5F cluster nodes The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality of the R5FSS is same as the R5FSS functionality on earlier K3 platform device J721S2. Each of the R5FSS can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding cluster node. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-2-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 120 ++++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 40 ++++++ 2 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c16..3c785cef4f200 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1112,4 +1112,124 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 383 1>; status = "disabled"; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <339>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 339 1>; + firmware-name = "j784s4-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <340>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 340 1>; + firmware-name = "j784s4-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <341>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 341 1>; + firmware-name = "j784s4-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <342>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 342 1>; + firmware-name = "j784s4-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss2: r5fss@5900000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5900000 0x00 0x5900000 0x20000>, + <0x5a00000 0x00 0x5a00000 0x20000>; + power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss2_core0: r5f@5900000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5900000 0x00010000>, + <0x5910000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <343>; + ti,sci-proc-ids = <0x0a 0xff>; + resets = <&k3_reset 343 1>; + firmware-name = "j784s4-main-r5f2_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss2_core1: r5f@5a00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5a00000 0x00010000>, + <0x5a10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <344>; + ti,sci-proc-ids = <0x0b 0xff>; + resets = <&k3_reset 344 1>; + firmware-name = "j784s4-main-r5f2_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index f04fcb614cbe4..e517043d3eb28 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -342,4 +342,44 @@ cpts@3d000 { ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <346>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 346 1>; + firmware-name = "j784s4-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <347>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 347 1>; + firmware-name = "j784s4-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; -- GitLab From 257d206b6d117d8e40742dc17ae02406747753ad Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Tue, 2 May 2023 18:15:26 -0500 Subject: [PATCH 747/926] arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-3-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3c785cef4f200..7277bf6eda093 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1232,4 +1232,52 @@ main_r5fss2_core1: r5f@5a00000 { ti,loczrama = <1>; }; }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <30>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 30 1>; + firmware-name = "j784s4-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <33>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 33 1>; + firmware-name = "j784s4-c71_1-fw"; + }; + + c71_2: dsp@66800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x66800000 0x00 0x00080000>, + <0x00 0x66e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <37>; + ti,sci-proc-ids = <0x32 0xff>; + resets = <&k3_reset 37 1>; + firmware-name = "j784s4-c71_2-fw"; + }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + }; }; -- GitLab From ba12d4dde708de01d3cae5ae368a930ec5f5fd07 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Tue, 2 May 2023 18:15:27 -0500 Subject: [PATCH 748/926] arm64: dts: ti: k3-j784s4-evm: Reserve memory for remote proc IPC Reserve memory for remote processors. Two memory regions are reserved for each remote processor. The first 1Mb region is used for virtio Vring buffers for IPC and the second region is used for holding resource table, trace buffer and as external memory to the remote processor. The mailboxes are also assigned for each remote processor. Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 318 +++++++++++++++++++++++ 1 file changed, 318 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f33815953e779..1200cc677eb69 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -42,6 +42,150 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; }; evm_12v0: regulator-evm12v0 { @@ -253,3 +397,177 @@ &mcu_cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; -- GitLab From 2c213d19515caf880e6c8266fbeda4145894c10e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 30 Mar 2023 11:49:53 +0300 Subject: [PATCH 749/926] arm64: dts: ti: k3-am625: Enable Type-C port for USB0 USB0 is a Type-C port with dual data role and power sink. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20230330084954.49763-3-rogerq@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 2 +- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 35 ++++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 2a1adda9bff6a..729f95e190423 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -161,7 +161,7 @@ exp1: gpio@22 { "UART1_FET_BUF_EN", "WL_LT_EN", "GPIO_HDMI_RSTn", "CSI_GPIO1", "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "TEST_GPIO2", + "HDMI_INTn", "PD_I2C_IRQ", "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "TSINT#", "IO_EXP_TEST_LED"; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index a61e8648f1894..4345b9fdd2a07 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -241,6 +241,30 @@ &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; }; &main_i2c1 { @@ -320,7 +344,16 @@ &usbss1 { }; &usb0 { - dr_mode = "peripheral"; + #address-cells = <1>; + #size-cells = <0>; + usb-role-switch; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; }; &usb1 { -- GitLab From 20fcf9d691ff6cde865f8486288b7babe1826b49 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:21 +0530 Subject: [PATCH 750/926] arm64: dts: ti: k3-j721s2-main: Add support for USB Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-2-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f76548..8d7b64728f882 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,21 @@ l3cache-sram@200000 { }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -745,6 +760,36 @@ cpts@310d0000 { }; }; + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- GitLab From 393eee04065d26d53e9167e3721ad9a0ff89d40f Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Fri, 31 Mar 2023 14:30:22 +0530 Subject: [PATCH 751/926] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 8d7b64728f882..931263919086f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -39,6 +50,14 @@ usb_serdes_mux: mux-controller@0 { #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; gic500: interrupt-controller@1800000 { @@ -790,6 +809,44 @@ usb0: usb@6000000 { }; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- GitLab From 80cfbf2f4ac735ab8e72a3c70188c433f06810c1 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:23 +0530 Subject: [PATCH 752/926] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Add support for two instance of OSPI in J721S2 SoC. Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-4-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463e..6e981fe4727eb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -379,4 +379,48 @@ adc { compatible = "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; }; -- GitLab From da61731dc7f5d7a676acd81124229b57e6fbe0ef Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:24 +0530 Subject: [PATCH 753/926] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-5-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 1299c715f34ca..30a566fef1951 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -321,6 +324,26 @@ &cpsw_port1 { phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- GitLab From 7743a9d7517a6a1f3b21d32db3bc1d00d6b16983 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:25 +0530 Subject: [PATCH 754/926] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-6-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 30a566fef1951..f81a40bbdac0e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -146,6 +146,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -344,6 +350,23 @@ serdes0_pcie_link: phy@0 { }; }; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- GitLab From bbabba4ece74c51b98e7c8dbd8fa4725d0ae9baf Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:26 +0530 Subject: [PATCH 755/926] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-7-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721s2-common-proc-board.dts | 33 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 +++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index f81a40bbdac0e..9066d8bc34bef 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -231,6 +231,20 @@ J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; &main_gpio2 { @@ -367,6 +381,25 @@ &usb0 { maximum-speed = "high-speed"; }; +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a3..d473d79c27574 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ transceiver0: can-phy0 { }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -79,3 +101,22 @@ &main_mcan16 { pinctrl-names = "default"; phys = <&transceiver0>; }; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + }; +}; -- GitLab From b6f18aa80f4eee59f9292f0007c021cb7e7dbbec Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:27 +0530 Subject: [PATCH 756/926] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-8-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 931263919086f..6629b2989180e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -847,6 +847,49 @@ serdes0: serdes@5060000 { }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- GitLab From 715084ecc25adafe7f724721807b64fcc3a13e4a Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:28 +0530 Subject: [PATCH 757/926] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 9066d8bc34bef..924e0dc4ac1e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -400,6 +400,14 @@ flash@0{ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- GitLab From d34654f54ebad11263cf7c411d8c60cd8941e2d4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 13 Jun 2023 20:09:00 +0200 Subject: [PATCH 758/926] arm64: dts: qcom: qrb4210-rb2: Enable on-board buttons Enable the PMIC GPIO- and RESIN-connected buttons on the board. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230613-topic-rb2_-v1-1-696cd7dbda28@linaro.org --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 39597277343cf..e23a0406eaccd 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -7,6 +7,7 @@ #include #include "sm4250.dtsi" +#include "pm6125.dtsi" / { model = "Qualcomm Technologies, Inc. QRB4210 RB2"; @@ -28,6 +29,23 @@ clk40M: can-clk { }; }; + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -219,6 +237,25 @@ &mdss_dsi0_phy { status = "okay"; }; +&pm6125_gpios { + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; -- GitLab From dce9254511d6c9ea0d5ed7e4f21e6206e2ca35ce Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:15:59 +0200 Subject: [PATCH 759/926] arm64: dts: qcom: msm8939-pm8916: Add missing pm8916_codec supplies Update for recent changes to pm8916.dtsi in commit 38218822a72f ("arm64: dts: qcom: pm8916: Move default regulator "-supply"s") and add the now missing pm8916_codec supplies to msm8939-pm8916.dtsi as well. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-1-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index 33e02f42f5e4e..503c2dd5fe47a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -25,6 +25,12 @@ &mpss { pll-supply = <&pm8916_l7>; }; +&pm8916_codec { + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; +}; + &rpm_requests { smd_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; -- GitLab From 6002a78023cded6f02eac7c812b076046cab8060 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:00 +0200 Subject: [PATCH 760/926] arm64: dts: qcom: msm8939: Disable lpass_codec by default Update for recent changes to msm8916.dtsi in commit a5cf21b14666 ("arm64: dts: qcom: msm8916: Disable audio codecs by default") and make lpass_codec disabled by default for devices that are not using the audio codec functionality inside MSM8939. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-2-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 4 ++++ arch/arm64/boot/dts/qcom/msm8939.dtsi | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 2a39216ceef59..c8442242137a3 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -135,6 +135,10 @@ &lpass { status = "okay"; }; +&lpass_codec { + status = "okay"; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 3c1505b69a6ba..895cafc11480b 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1608,6 +1608,7 @@ lpass_codec: audio-codec@771c000 { <&gcc GCC_CODEC_DIGCODEC_CLK>; clock-names = "ahbix-clk", "mclk"; #sound-dai-cells = <1>; + status = "disabled"; }; sdhc_1: mmc@7824900 { -- GitLab From 209aea1ad505519faf018b596e4fdca0d0569469 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:01 +0200 Subject: [PATCH 761/926] arm64: dts: qcom: msm8939-sony-tulip: Fix l10-l12 regulator voltages msm8939-sony-xperia-kanuti-tulip.dts has several regulator voltages that do not quite seem to match what is used in the vendor kernel. In particular: - l10 is fixed at 2.8V [1, 2] - l11/l12 are 2.95V max [1] [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.BR.1.3.3_rb2.14/arch/arm/boot/dts/qcom/msm8939-regulator.dtsi [2]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.BR.1.3.3_rb2.14/arch/arm/boot/dts/qcom/msm8939-kanuti_tulip.dtsi#L671C1-L673 Fixes: f1134f738fad ("arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua") Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-3-a3c3ac833567@gerhold.net --- .../boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index a9df8dab5481f..dc5b8cd5b9f47 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -110,20 +110,20 @@ pm8916_l9: l9 { }; pm8916_l10: l10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; pm8916_l11: l11 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; }; pm8916_l12: l12 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <2950000>; }; pm8916_l13: l13 { -- GitLab From 8771308c91cefc072f36415cec0b802ee55b1d96 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:02 +0200 Subject: [PATCH 762/926] arm64: dts: qcom: msm8939-sony-tulip: Allow disabling pm8916_l6 The vendor kernel from Sony does not have regulator-always-on for pm8916_l6, so we should be able to disable it when setting up the display properly. Since sony-tulip does not have display set up currently it should be fine to let the regulator disable until then. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-4-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index dc5b8cd5b9f47..509abcdad2879 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -91,7 +91,6 @@ pm8916_l5: l5 { pm8916_l6: l6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; }; pm8916_l7: l7 { -- GitLab From 9187d555c4ba9544c7f117062d241aa085f59a06 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:03 +0200 Subject: [PATCH 763/926] arm64: dts: qcom: msm8939: Fix regulator constraints The regulator constraints for the MSM8939 devices were originally taken from Qualcomm's msm-3.10 vendor device tree (for lack of better documentation). Unfortunately it turns out that Qualcomm's voltages are slightly off as well and do not match the voltage constraints applied by the RPM firmware. This means that we sometimes request a specific voltage but the RPM firmware actually applies a much lower or higher voltage. This is particularly critical for pm8916_l11 which is used as SD card VMMC regulator: The SD card can choose a voltage from the current range of 1.8 - 2.95V. If it chooses to run at 1.8V we pretend that this is fine but the RPM firmware will still silently end up configuring 2.95V. This can be easily reproduced with a multimeter or by checking the SPMI hardware registers of the regulator. Apply the same change as for MSM8916 in commit 355750828c55 ("arm64: dts: qcom: msm8916: Fix regulator constraints") and make the voltages match the actual "specified range" in the PM8916 Device Specification which is enforced by the RPM firmware. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-5-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 12 ++++++------ .../dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index c8442242137a3..ceae83b1480bb 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -164,13 +164,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; pm8916_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; pm8916_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; /* l1 is fixed to 1225000, but not connected in schematic */ @@ -201,7 +201,7 @@ pm8916_l7: l7 { }; pm8916_l8: l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -216,7 +216,7 @@ pm8916_l10: l10 { }; pm8916_l11: l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 509abcdad2879..2905dd8d4bf91 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -64,13 +64,13 @@ &smd_rpm_regulators { vdd_l7-supply = <&pm8916_s4>; pm8916_s3: s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; }; pm8916_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; }; pm8916_l2: l2 { @@ -99,7 +99,7 @@ pm8916_l7: l7 { }; pm8916_l8: l8 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; @@ -114,7 +114,7 @@ pm8916_l10: l10 { }; pm8916_l11: l11 { - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-system-load = <200000>; regulator-allow-set-load; -- GitLab From 88028fa047fb72826dd206b51550be780777718c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:04 +0200 Subject: [PATCH 764/926] arm64: dts: qcom: msm8939-pm8916: Clarify purpose Add the same comment to msm8939-pm8916.dtsi that was added for the MSM8916 variant in commit f193264986b5 ("arm64: dts: qcom: msm8916-pm8916: Clarify purpose"). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-6-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index 503c2dd5fe47a..3bede1a236037 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -1,4 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only +/* + * msm8939-pm8916.dtsi describes common properties (e.g. regulator connections) + * that apply to most devices that make use of the MSM8939 SoC and PM8916 PMIC. + * Many regulators have a fixed purpose in the original reference design and + * were rarely re-used for different purposes. Devices that deviate from the + * typical reference design should not make use of this include and instead add + * the necessary properties in the board-specific device tree. + */ #include "msm8939.dtsi" #include "pm8916.dtsi" -- GitLab From 5cdab9a8c70c4d979909dd1bb6d1f3eacd9fa270 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:05 +0200 Subject: [PATCH 765/926] arm64: dts: qcom: msm8939: Define regulator constraints next to usage Right now each MSM8939 device has a huge block of regulator constraints with allowed voltages for each regulator. For lack of better documentation these voltages are often copied as-is from the vendor device tree, without much extra thought. Unfortunately, the voltages in the vendor device trees are often misleading or even wrong, e.g. because: - There is a large voltage range allowed and the actual voltage is only set somewhere hidden in some messy vendor driver. This is often the case for pm8916_{l14,l15,l16} because they have a broad range of 1.8-3.3V by default. - The voltage is actually wrong but thanks to the voltage constraints in the RPM firmware it still ends up applying the correct voltage. To have proper regulator constraints it is important to review them in context of the usage. The current setup in the MSM8939 device trees makes this quite hard because each device duplicates the standard voltages for components of the SoC and mixes those with minor device-specific additions and dummy voltages for completely unused regulators. The actual usage of the regulators for the SoC components is in msm8939-pm8916.dtsi, so it can and should also define the related voltage constraints. These are not board-specific but defined in the MSM8939/PM8916 specification. There is no documentation available for MSM8939 but in practice it's almost identical to MSM8916. Note that this commit does not make any functional change. All used regulators still have the same regulator constraints as before. Unused regulators do not have regulator constraints anymore because most of these were too broad or even entirely wrong. They should be added back with proper voltage constraints when there is an actual usage. The same changes were already made for MSM8916 in commit b0a8f16ae4a0 ("arm64: dts: qcom: msm8916: Define regulator constraints next to usage"). Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-7-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 98 ----------------- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 100 ++++++++++++++---- .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 98 ----------------- 3 files changed, 80 insertions(+), 216 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index ceae83b1480bb..40644c242fb7d 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -158,104 +158,6 @@ &pm8916_gpios { "PM_GPIO4"; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - pm8916_s3: s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - pm8916_s4: s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - /* l1 is fixed to 1225000, but not connected in schematic */ - - pm8916_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8916_l4: l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8916_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l8: l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - pm8916_l9: l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l10: l10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l11: l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - - pm8916_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8916_l13: l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8916_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l16: l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8916_l18: l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &sdhc_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index 3bede1a236037..12538211bc72d 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -40,32 +40,92 @@ &pm8916_codec { }; &rpm_requests { - smd_rpm_regulators: regulators { + pm8916_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; /* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */ /* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */ - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; + pm8916_s3: s3 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + }; + pm8916_s4: s4 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2150000>; + }; + + /* + * Some of the regulators are unused or managed by another + * processor (e.g. the modem). We should still define nodes for + * them to ensure the vote from the application processor can be + * dropped in case the regulators are already on during boot. + * + * The labels for these nodes are omitted on purpose because + * boards should configure a proper voltage before using them. + */ + l1 {}; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */ - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; + + l4 {}; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 {}; + + pm8916_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 {}; + l15 {}; + l16 {}; + l17 {}; + l18 {}; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 2905dd8d4bf91..8613cf93dac58 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -58,104 +58,6 @@ usb_id_default: usb-id-default-state { }; }; -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - pm8916_s3: s3 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1350000>; - }; - - pm8916_s4: s4 { - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2150000>; - }; - - pm8916_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8916_l4: l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8916_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8916_l8: l8 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - }; - - pm8916_l9: l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l10: l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8916_l11: l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - pm8916_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8916_l13: l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8916_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l16: l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8916_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pm8916_l18: l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - &sdhc_1 { status = "okay"; }; -- GitLab From ecbfba694b5baf2b854689c63ef011e905810c59 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 14 Jun 2023 09:16:06 +0200 Subject: [PATCH 766/926] arm64: dts: qcom: msm8939-pm8916: Mark always-on regulators Some of the regulators must be always-on to ensure correct operation of the system, e.g. PM8916 L2 for the LPDDR RAM, L5 for most digital I/O and L7 for the CPU PLL (strictly speaking the CPU PLL might only need an active-only vote but this is not supported for regulators in mainline currently). The RPM firmware seems to enforce that internally, these supplies stay on even if we vote for them to power off (and there is no other processor running). This means it's pointless to keep sending enable/disable requests because they will just be ignored. Also, drivers are much more likely to get a wrong impression of the regulator status, because regulator_is_enabled() will return false when there are no users, even though the regulator is always on. Describe this properly by marking the regulators as always-on. The same changes was already made for MSM8916 in commit 8bbd35771f90 ("arm64: dts: qcom: msm8916-pm8916: Mark always-on regulators"). Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230530-msm8939-regulators-v1-8-a3c3ac833567@gerhold.net --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index 12538211bc72d..adb96cd8d643e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -51,10 +51,12 @@ pm8916_rpm_regulators: regulators { pm8916_s3: s3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <1350000>; + regulator-always-on; /* Needed for L2 */ }; pm8916_s4: s4 { regulator-min-microvolt = <1850000>; regulator-max-microvolt = <2150000>; + regulator-always-on; /* Needed for L5/L7 */ }; /* @@ -71,6 +73,7 @@ pm8916_s4: s4 { pm8916_l2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; /* Needed for LPDDR RAM */ }; /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */ @@ -80,6 +83,7 @@ pm8916_l2: l2 { pm8916_l5: l5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for most digital I/O */ }; pm8916_l6: l6 { @@ -90,6 +94,7 @@ pm8916_l6: l6 { pm8916_l7: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; /* Needed for CPU PLL */ }; pm8916_l8: l8 { -- GitLab From 831b802a7727ba6e67c5ed585c54f610d9db1316 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Wed, 14 Jun 2023 19:54:25 +0530 Subject: [PATCH 767/926] arm: dts: qcom: sdx55: Add interconnect path Add pcie-mem interconnect path to sdx55 target. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686752666-13426-3-git-send-email-quic_krichai@quicinc.com --- arch/arm/boot/dts/qcom-sdx55.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 06c2646dd673d..df3cd9c4ffb93 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -421,6 +421,10 @@ pcie_ep: pcie-ep@1c00000 { ; interrupt-names = "global", "doorbell"; + + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "pcie-mem"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; -- GitLab From eec51ab2fd6f447a993c502364704d0cb5bc8cae Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 14 Jun 2023 07:22:03 -0700 Subject: [PATCH 768/926] arm64: dts: qcom: sc8280xp: Add GPU related nodes Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the SC8280XP. Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Tested-by: Johan Hovold Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230614142204.2675653-2-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 8 ++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 175 +++++++++++++++++++++++++ 2 files changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 4a990fda8fc32..bacbdec562814 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -167,6 +167,14 @@ opp-2592000000 { }; }; +&gpucc { + status = "disabled"; +}; + +&gpu_smmu { + status = "disabled"; +}; + &pcie2a { compatible = "qcom,pcie-sa8540p"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 2f7ead41021cf..c77278712b12e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -2332,6 +2333,180 @@ tcsr: syscon@1fc0000 { reg = <0x0 0x01fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-690.0", "qcom,adreno"; + + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + opp-level = ; + opp-peak-kBps = <451000>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-547000000 { + opp-hz = /bits/ 64 <547000000>; + opp-level = ; + opp-peak-kBps = <1555000>; + }; + + opp-606000000 { + opp-hz = /bits/ 64 <606000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-655000000 { + opp-hz = /bits/ 64 <655000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + + opp-690000000 { + opp-hz = /bits/ 64 <690000000>; + opp-level = ; + opp-peak-kBps = <2736000>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&gpu_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sc8280xp-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + + power-domains = <&rpmhpd SC8280XP_GFX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpu_smmu: iommu@3da0000 { + compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + usb_0_hsphy: phy@88e5000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; -- GitLab From 598a06afca5a2ab4850ce9ff8146ec728cca570c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 14 Jun 2023 07:22:04 -0700 Subject: [PATCH 769/926] arm64: dts: qcom: sc8280xp: Enable GPU related nodes Add memory reservation for the zap-shader and enable the Adreno SMMU, GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the Lenovo ThinkPad X13s. Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Tested-by: Johan Hovold Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230614142204.2675653-3-quic_bjorande@quicinc.com --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 14 ++++++++++++++ .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index cd7e0097d8bc5..b566e403d1db2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -210,6 +210,11 @@ vreg_wwan: regulator-wwan { }; reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -390,6 +395,15 @@ &dispcc0 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8280xp/qcdxkmsuc8280.mbn"; + }; +}; + &mdss0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 5ae057ad64381..7cc3028440b64 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -264,6 +264,11 @@ vreg_wwan: regulator-wwan { }; reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; size = <0x0 0x8000000>; @@ -518,6 +523,15 @@ &dispcc0 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn"; + }; +}; + &mdss0 { status = "okay"; }; -- GitLab From 96135297a76003faae68e3aa86e2e19851510eb9 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:22 -0500 Subject: [PATCH 770/926] arm64: dts: ti: k3-am64-main: add VTM node The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by: Christian Gmeiner Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-2-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 +++++ arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 3 ++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index f5e25d6c3c28b..9dea128893db1 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1536,4 +1536,12 @@ elm0: ecc@25010000 { clock-names = "fck"; status = "disabled"; }; + + main_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi new file mode 100644 index 0000000000000..036db56ba7977 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index d6262b5a0a104..8e9c2bc70f4d7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -54,6 +54,7 @@ cbass_main: bus@f4000 { <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ @@ -90,6 +91,8 @@ cbass_mcu: bus@4000000 { ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; }; + + #include "k3-am64-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- GitLab From bbb6dc62505acf6fcb80573f7e7a59875c33be0d Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:23 -0500 Subject: [PATCH 771/926] arm64: dts: ti: k3-am62-wakeup: add VTM node The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die. Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-3-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 +++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 +++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 +++-- 3 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi new file mode 100644 index 0000000000000..a358757e26f07 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 7726ebae25394..eae0528871862 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -61,4 +61,12 @@ wkup_rti0: watchdog@2b000000 { /* Used by DM firmware */ status = "reserved"; }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index a401f52252439..5e72c445f37a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -81,6 +81,7 @@ cbass_main: bus@f0000 { <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; @@ -91,14 +92,17 @@ cbass_mcu: bus@4000000 { ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; - cbass_wakeup: bus@2b000000 { + cbass_wakeup: bus@b00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; }; }; + + #include "k3-am62-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- GitLab From 225312fbaf37bb283dbc92a0a1d4dfe58629ab64 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:24 -0500 Subject: [PATCH 772/926] arm64: dts: ti: k3-am62a-wakeup: add VTM node The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-4-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi | 47 ++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 8 ++++ arch/arm64/boot/dts/ti/k3-am62a.dtsi | 2 + 3 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi new file mode 100644 index 0000000000000..85ce545633ea5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index d848eb24b5522..4e8279fa01e15 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -62,4 +62,12 @@ wkup_rti0: watchdog@2b000000 { /* Used by DM firmware */ status = "reserved"; }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi index fe60c9ce21e3d..61a210ecd5ff1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi @@ -115,6 +115,8 @@ cbass_wakeup: bus@b00000 { <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62a-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- GitLab From 64821fbf67382951c5eae4e088df93f236c1ead6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:25 -0500 Subject: [PATCH 773/926] arm64: dts: ti: j784s4: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-5-bb@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 8 ++ arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi | 101 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 4 + 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index e517043d3eb28..32ba27680c6d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -382,4 +382,12 @@ mcu_r5fss0_core1: r5f@41400000 { ti,loczrama = <1>; }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi new file mode 100644 index 0000000000000..f7b1a15b8fa0a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 2e03d84da7d2e..cd403c3d2be88 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -281,6 +281,10 @@ cbass_mcu_wakeup: bus@28380000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + thermal_zones: thermal-zones { + #include "k3-j784s4-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ -- GitLab From 8fb4e87c55979c1f6691346205b884d1863ca6db Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:26 -0500 Subject: [PATCH 774/926] arm64: dts: ti: j721e: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-6-bb@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++ arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 + 3 files changed, 86 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 24e8125db8c44..8d86f23b21237 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -458,4 +458,13 @@ mcu_spi2: spi@40320000 { clocks = <&k3_clks 276 0>; status = "disabled"; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j721e-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi new file mode 100644 index 0000000000000..c2523279001bf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + wkup_thermal: wkup-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + c7x_thermal: c7x-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + gpu_crit: gpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + r5f_thermal: r5f-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + r5f_crit: r5f-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index c577f37394071..99436105ada1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -185,6 +185,8 @@ cbass_mcu_wakeup: bus@28380000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + #include "k3-j721e-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- GitLab From 4aa6586a9720849527379c415d0977f0d5bcfcac Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:27 -0500 Subject: [PATCH 775/926] arm64: dts: ti: j7200: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-7-bb@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++++ arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 + 3 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 331b4e482e41c..6a26758af7be0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -459,4 +459,12 @@ rng: rng@40910000 { status = "disabled"; /* Used by OP-TEE */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi new file mode 100644 index 0000000000000..e7e3a643a6f0c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + mcu_thermal: mcu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main_thermal: main-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index f1836ec8e9340..6c96759e87524 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -171,6 +171,8 @@ cbass_mcu_wakeup: bus@28380000 { <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ }; }; + + #include "k3-j7200-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- GitLab From d148e3fe52c855b1709ed031eff6e63e87ad0372 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:28 -0500 Subject: [PATCH 776/926] arm64: dts: ti: j721s2: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++ arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 101 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 4 + 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 6e981fe4727eb..9c6bb6db59f83 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -423,4 +423,12 @@ ospi1: spi@47050000 { status = "disabled"; /* Needs pinmux */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x0 0x350>, + <0x00 0x42050000 0x0 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi new file mode 100644 index 0000000000000..f7b1a15b8fa0a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index f3db277628cd0..2abeb857fde7e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -164,6 +164,10 @@ cbass_mcu_wakeup: bus@28380000 { }; }; + + thermal_zones: thermal-zones { + #include "k3-j721s2-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ -- GitLab From 5e880618936229b85a185cef736c573b81ef0c9d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 17:54:50 -0500 Subject: [PATCH 777/926] arm64: dts: ti: k3: j721s2/j784s4: Switch to https links Looks like a couple of http:// links crept in. Use https instead. While at it, drop unicode encoded character. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230417225450.1182047-1-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 2abeb857fde7e..1f636acd4eee4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721S2 SoC Family * - * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index cd403c3d2be88..8b5974d92e33a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J784S4 SoC Family * - * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52 + * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * -- GitLab From 477d43f6d8546597e007a3a2ebd19f6e4e090fee Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:37 -0500 Subject: [PATCH 778/926] arm64: dts: ti: k3-am62x-sk-common: Drop extra EoL Drop an extra EoL Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 4345b9fdd2a07..29a43db97b3dc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -31,7 +31,6 @@ memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { -- GitLab From 76194aba0c30b1ee25067b34235141443bd078fb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:38 -0500 Subject: [PATCH 779/926] arm64: dts: ti: k3-am62x-sk-common: Describe main_uart1 and wkup_uart wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 29a43db97b3dc..3e6ae4c4f8ee4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -125,6 +125,15 @@ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ @@ -219,9 +228,22 @@ AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ }; }; +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { @@ -233,6 +255,8 @@ &main_uart0 { &main_uart1 { /* Main UART1 is used by TIFS firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- GitLab From f40ed3b39b486ed8fbca7aa4a319c8d1d14ac97d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:39 -0500 Subject: [PATCH 780/926] arm64: dts: ti: k3-am62x-sk-common: Add eeprom Add board EEPROM support to device tree Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 3e6ae4c4f8ee4..4f06d25f0b92d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -265,6 +265,12 @@ &main_i2c0 { pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; + typec_pd0: tps6598x@3f { compatible = "ti,tps6598x"; reg = <0x3f>; -- GitLab From 5cab8abaee22470523a5293994a52784360a7926 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:40 -0500 Subject: [PATCH 781/926] arm64: dts: ti: k3-am62x-sk-common: Improve documentation of mcasp1_pins Include documentation of the AMC package pin name as well to keep it consistent with the rest of the pinctrl documentation. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 4f06d25f0b92d..d39cfc5335831 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -220,10 +220,10 @@ AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ main_mcasp1_pins_default: main-mcasp1-pins-default { pinctrl-single,pins = < - AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ - AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ - AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ - AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ >; }; }; -- GitLab From af398252d68edbeef3b1f8cbdf3867b70d2dbbe8 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 24 Apr 2023 15:08:27 +0530 Subject: [PATCH 782/926] arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 10c8a5fb4ee29..c249cc3d1fbaf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1287,8 +1287,8 @@ main_sdhci0: mmc@4f80000 { bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1309,11 +1309,12 @@ main_sdhci1: mmc@4fb0000 { assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1335,11 +1336,12 @@ main_sdhci2: mmc@4f98000 { assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; -- GitLab From b8690ed3d1d16153be76f24de3a13797c9fd29b3 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 9 May 2023 15:53:53 +0530 Subject: [PATCH 783/926] arm64: dts: ti: am65x: Add Rocktech OLDI panel DT overlay The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with integrated touch screen. The integrated touch screen is Goodix GT928. This panel connects with AM65 GP-EVM[2]. Add DT nodes for these and connect the endpoint nodes with DSS. [1]: Panel link https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT [2]: AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM Signed-off-by: Jyri Sarha Signed-off-by: Nikhil Devshatwar [abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes] Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230509102354.10116-2-a-bhatia1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + ...am654-base-board-rocktech-rk101-panel.dtso | 71 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81c..47b0d257b5087 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -22,12 +22,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb # Boards with AM65x SoC +k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso new file mode 100644 index 0000000000000..3be92c39ecbae --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. + * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT + * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + display0 { + compatible = "rocktech,rk101ii01d-ct"; + backlight = <&lcd_bl>; + enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + port { + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = + <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + + interrupt-parent = <&pca9554>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + + reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>; + }; +}; -- GitLab From ad5f7c514442a5eb29a415f75b3ea2744933e274 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 13:41:16 +0530 Subject: [PATCH 784/926] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add support for ADC nodes J784S4 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502081117.21431-2-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 32ba27680c6d0..d640e31a83351 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -390,4 +390,44 @@ wkup_vtm0: temperature-sensor@42040000 { power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; -- GitLab From e99913ad58af3172343e3b22fa7a2a794d78b8c1 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 13:41:17 +0530 Subject: [PATCH 785/926] arm64: dts: ti: k3-j784s4-evm: Add pinmux information for ADC J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502081117.21431-3-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 1200cc677eb69..64b58e0d2e5d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -309,6 +309,32 @@ J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; }; &main_uart8 { @@ -571,3 +597,21 @@ &c71_3 { memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; -- GitLab From 426e720259c9e4066cafac9d4592cfbca4031b1d Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 14:38:14 +0530 Subject: [PATCH 786/926] arm64: dts: ti: k3-j784s4-main: Enable support for high speed modes eMMC tuning was incomplete earlier, so support for high speed modes was kept disabled. Remove no-1-8-v property to enable support for high speed modes for eMMC in J784S4 SoC. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 7277bf6eda093..742bab1c5103e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -378,7 +378,6 @@ main_sdhci0: mmc@4f80000 { mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; - no-1-8-v; status = "disabled"; }; -- GitLab From 155e7635ed1f3814d94d12556a3a0fed41d05b76 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:33 -0500 Subject: [PATCH 787/926] arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT addition went in at around the same time and must have missed that change so the mailboxes are not re-enabled. Do that here. Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64") Signed-off-by: Andrew Davis Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 37c24b077b6aa..8a62ac263b89a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -936,6 +936,7 @@ &ufs_wrapper { }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -950,6 +951,7 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -964,6 +966,7 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -978,6 +981,7 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -992,6 +996,7 @@ mbox_c66_1: mbox-c66-1 { }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { -- GitLab From a0cfd88d4a8a1106e9de5c3b03e68efe9e6249ec Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:34 -0500 Subject: [PATCH 788/926] arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------ .../dts/ti/k3-j721e-common-proc-board.dts | 25 ------ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 ------------------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------ 4 files changed, 155 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 8a62ac263b89a..d77eeff0d81d4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -892,35 +892,11 @@ &pcie2_rc { status = "disabled"; }; -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - &pcie3_rc { /* Unused */ status = "disabled"; }; -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c11c092c1ce0c..7957d09bf04b5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -839,35 +839,10 @@ &pcie2_rc { num-lanes = <2>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; - status = "disabled"; -}; - -&pcie1_ep { - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie2_ep { - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - &pcie3_rc { status = "disabled"; }; -&pcie3_ep { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c249cc3d1fbaf..5ca0ddd82bfc6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -816,26 +816,6 @@ pcie0_rc: pcie@2900000 { dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie0_ep: pcie-ep@2900000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie1_rc: pcie@2910000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02910000 0x00 0x1000>, @@ -864,26 +844,6 @@ pcie1_rc: pcie@2910000 { dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie2_rc: pcie@2920000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02920000 0x00 0x1000>, @@ -912,26 +872,6 @@ pcie2_rc: pcie@2920000 { dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie2_ep: pcie-ep@2920000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie3_rc: pcie@2930000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02930000 0x00 0x1000>, @@ -960,28 +900,6 @@ pcie3_rc: pcie@2930000 { dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie3_ep: pcie-ep@2930000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - #address-cells = <2>; - #size-cells = <2>; - }; - serdes_wiz4: wiz@5050000 { compatible = "ti,am64-wiz-10g"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ad7b45aeed0ae..3fb24b68fe8e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -895,35 +895,11 @@ &pcie2_rc { status = "disabled"; }; -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - &pcie3_rc { /* Unused */ status = "disabled"; }; -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- GitLab From 731c6deda85ffcac3629bea757a806306e335618 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:35 -0500 Subject: [PATCH 789/926] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 16 +--------------- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 7 +++---- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++---------- 4 files changed, 10 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index d77eeff0d81d4..be0c5431119ee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -872,12 +872,8 @@ serdes1_pcie_link: phy@0 { }; }; -&pcie0_rc { - /* Unused */ - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_rst_pins_default>; phys = <&serdes1_pcie_link>; @@ -887,16 +883,6 @@ &pcie1_rc { reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7957d09bf04b5..42579564c3bde 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -819,6 +819,7 @@ &mhdp { }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -826,6 +827,7 @@ &pcie0_rc { }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; @@ -833,16 +835,13 @@ &pcie1_rc { }; &pcie2_rc { + status = "okay"; reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie3_rc { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5ca0ddd82bfc6..af5bc2d284ca8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -814,6 +814,7 @@ pcie0_rc: pcie@2900000 { ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie1_rc: pcie@2910000 { @@ -842,6 +843,7 @@ pcie1_rc: pcie@2910000 { ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie2_rc: pcie@2920000 { @@ -870,6 +872,7 @@ pcie2_rc: pcie@2920000 { ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie3_rc: pcie@2930000 { @@ -898,6 +901,7 @@ pcie3_rc: pcie@2930000 { ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; serdes_wiz4: wiz@5050000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 3fb24b68fe8e5..50364c05415e4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -871,6 +871,7 @@ serdes1_pcie_link: phy@0 { }; &pcie0_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ekey_reset_pins_default>; reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; @@ -881,6 +882,7 @@ &pcie0_rc { }; &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mkey_reset_pins_default>; reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; @@ -890,16 +892,6 @@ &pcie1_rc { num-lanes = <2>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- GitLab From 91f983ff7039fa2ff8ef153e118eec6d60f55e45 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:36 -0500 Subject: [PATCH 790/926] arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++++ .../boot/dts/ti/k3-am64-phycore-som.dtsi | 24 ------------------- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 18 +++++--------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 18 +++++--------- 4 files changed, 18 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 9dea128893db1..3c387d479b366 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -820,6 +820,7 @@ mailbox0_cluster2: mailbox@29020000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -830,6 +831,7 @@ mailbox0_cluster3: mailbox@29030000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster4: mailbox@29040000 { @@ -840,6 +842,7 @@ mailbox0_cluster4: mailbox@29040000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster5: mailbox@29050000 { @@ -850,6 +853,7 @@ mailbox0_cluster5: mailbox@29050000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster6: mailbox@29060000 { @@ -859,6 +863,7 @@ mailbox0_cluster6: mailbox@29060000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster7: mailbox@29070000 { @@ -868,6 +873,7 @@ mailbox0_cluster7: mailbox@29070000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; main_r5fss0: r5fss@78000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 8dfb6301b17dc..7c2e26ef726c0 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -160,30 +160,6 @@ &cpsw_port2 { status = "disabled"; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 3db740f78cd25..7c90e284e2bff 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -537,6 +537,8 @@ flash@0 { }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -548,11 +550,9 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -564,21 +564,15 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 003cff9a27990..f9ed22c5a4720 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -535,6 +535,8 @@ flash@0 { }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -546,11 +548,9 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -562,21 +562,15 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, -- GitLab From b0efb45d126ee914bafca37a582ae6574560dd25 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:37 -0500 Subject: [PATCH 791/926] arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 -------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 8 -------- 4 files changed, 2 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index be0c5431119ee..a7b686cab3e67 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -883,16 +883,6 @@ &pcie1_rc { reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&icssg0_mdio { - /* Unused */ - status = "disabled"; -}; - -&icssg1_mdio { - /* Unused */ - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 42579564c3bde..7f9bd6bb004ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -842,14 +842,6 @@ &pcie2_rc { num-lanes = <2>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index af5bc2d284ca8..5f35f823a8fa4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2015,6 +2015,7 @@ icssg0_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -2156,6 +2157,7 @@ icssg1_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 50364c05415e4..72804a03c10d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -892,14 +892,6 @@ &pcie1_rc { num-lanes = <2>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; -- GitLab From d93036b47f354b7acb95aad5c91e9becbe4e9f61 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:10 +0530 Subject: [PATCH 792/926] arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node J721E has a Flash SubSystem that has one OSPI and one HyperBus with muxed datapath and another independent OSPI. Add DT nodes for HyperBus controller and keep it disabled and model the data path selection mux as a reg-mux. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 8d86f23b21237..bfe3907b4b55b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -181,6 +181,27 @@ fss: fss@47000000 { #size-cells = <2>; ranges; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x2>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x00 0x47034000 0x00 0x100>, + <0x05 0x00000000 0x01 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 0>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + status = "disabled"; + }; + ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, -- GitLab From 0979c0069cb669528d13818410de9f0dd41585f3 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:11 +0530 Subject: [PATCH 793/926] arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory controller, add corresponding node, pinmux and partitions for the same. HyperBus is muxed with OSPI and only one controller can be active at a time, therefore keep HyperBus node disabled. Bootloader will detect the external mux state through a wkup gpio and enable the node as required. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e289d5b443568..b96e5fdddb4ba 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -165,6 +165,25 @@ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ + >; + }; }; &ospi0 { @@ -185,6 +204,58 @@ flash@0 { }; }; +&hbmc { + /* OSPI and HBMC are muxed inside FSS, Bootloader will enable + * appropriate node based on board detection + */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "hbmc.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "hbmc.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "hbmc.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "hbmc.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; + }; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>; -- GitLab From be8be0d036b2fed1f705931ac3901077039b7496 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:12 +0530 Subject: [PATCH 794/926] arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux J7200 common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0cc0e1dc40c54..e1017027d6499 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -97,6 +97,12 @@ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ @@ -186,6 +192,11 @@ &main_gpio6 { status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; -- GitLab From 58cd171af4d7e27525b1924b72100cba98d88d2a Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:13 +0530 Subject: [PATCH 795/926] arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux J721E common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7f9bd6bb004ef..dea451e10f2a9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -362,6 +362,12 @@ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ + >; + }; }; &wkup_uart0 { @@ -419,6 +425,11 @@ &main_gpio7 { status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; -- GitLab From 2dc39c564982f2ca77a9589a3d9906ecaf5a42e4 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 5 May 2023 15:10:12 +0200 Subject: [PATCH 796/926] arm64: dts: ti: Add LED controller to phyBOARD-Electra With commit 9f6ffd0da650 ("dt-bindings: leds: Convert PCA9532 to dtschema"), we can now add the LED controller without introducing new dtbs_check warnings. Add missing I2C LED controller. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8d3114d14a8b5..8199ac06c09aa 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "k3-am642.dtsi" @@ -210,6 +211,26 @@ eeprom@51 { pagesize = <16>; reg = <0x51>; }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-3 { + label = "red:user"; + type = ; + }; + + led-4 { + label = "green:user"; + type = ; + }; + + led-5 { + label = "blue:user"; + type = ; + }; + }; }; &main_mcan0 { -- GitLab From 8758109d135401c8afea0d0e3c51e7a52c843b7b Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Thu, 4 May 2023 13:33:04 +0530 Subject: [PATCH 797/926] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1 TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS bus for interfacing with OSPI flashes. Add the nodes to allow using SPI flashes. Signed-off-by: Apurva Nandan Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index d640e31a83351..ae9a8856bc402 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -430,4 +430,45 @@ adc { compatible = "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + reg = <0x00 0x47000000 0x00 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 161 7>; + assigned-clocks = <&k3_clks 161 7>; + assigned-clock-parents = <&k3_clks 161 9>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 162 7>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; -- GitLab From 150ce1b10740c10f87e90e485bc279c205e3f731 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Thu, 4 May 2023 13:33:05 +0530 Subject: [PATCH 798/926] arm64: dts: ti: k3-j784s4-evm: Add support for OSPI and QSPI flashes J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI flash connected to OSPI1, enable support for the same. Also describe the partition information according to the offsets in the bootloader. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Apurva Nandan Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 158 +++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 64b58e0d2e5d7..8271ac16b3193 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -337,12 +337,170 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; }; +&fss { + status = "okay"; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; -- GitLab From e96b5e98482354be3ef666704964f8c2ed6b6e8d Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:07 +0530 Subject: [PATCH 799/926] arm64: dts: ti: k3-j721e: Describe OSPI and QSPI flash partition info Describe OSPI and QSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB QSPI flash both with sector size of 128 KiB thus the size of the smallest partition is chosen as 128KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721e-common-proc-board.dts | 46 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 46 +++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index dea451e10f2a9..fa6ac3475290c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -523,6 +523,52 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "qspi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "qspi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "qspi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index b96e5fdddb4ba..67e52ee3a8bda 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,6 +201,52 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; -- GitLab From 2f1023d5f050e4b83b5e71fb9ad5a81e95e4123d Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:08 +0530 Subject: [PATCH 800/926] arm64: dts: ti: k3-j721e-sk: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SK has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 72804a03c10d7..ffb9820cb61f4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -568,6 +568,52 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@7c0000 { + label = "ospi.env.backup"; + reg = <0x7c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- GitLab From 7f80deb0c6c779ee19996918962c8cad058efd10 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:09 +0530 Subject: [PATCH 801/926] arm64: dts: ti: k3-j7200-som: Describe OSPI and Hyperflash partition info Describe OSPI and Hyperflash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the SoM also has a 64 MiB Hyperflash present on it, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 72 +++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 269424154771a..2a743b8950742 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -149,6 +149,37 @@ &hbmc { flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "hbmc.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "hbmc.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "hbmc.env"; + reg = <0x700000 0x40000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; @@ -250,5 +281,46 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- GitLab From c08cb9cef76abc6216347af8fd8452037b9795de Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:10 +0530 Subject: [PATCH 802/926] arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM654 baseboard has a MT35XU512ABA 64 MiB OSPI flash with sector size of 128 KiB thus the size of the smallest partition is chosen as 128 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0a018bcf57353..73dd50586c64a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -544,6 +544,52 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; -- GitLab From 9227c49a09b0cfb152a7824b69db46940db81ff3 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:11 +0530 Subject: [PATCH 803/926] arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 41 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 41 +++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 7c90e284e2bff..309500e4c2372 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -533,6 +533,47 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index f9ed22c5a4720..9ea012b883e8a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -531,6 +531,47 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- GitLab From 498f7b0f9da9be6f6c099b4c8ffb502174623565 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:41 -0500 Subject: [PATCH 804/926] arm64: dts: ti: k3-am65-main: Fix mcan node name s/mcan/can to stay in sync with bindings conventions. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 5dfa31840e9c3..c2519d4607a53 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -227,7 +227,7 @@ mcu_udmap: dma-controller@285c0000 { }; }; - m_can0: mcan@40528000 { + m_can0: can@40528000 { compatible = "bosch,m_can"; reg = <0x0 0x40528000 0x0 0x400>, <0x0 0x40500000 0x0 0x4400>; @@ -243,7 +243,7 @@ m_can0: mcan@40528000 { status = "disabled"; }; - m_can1: mcan@40568000 { + m_can1: can@40568000 { compatible = "bosch,m_can"; reg = <0x0 0x40568000 0x0 0x400>, <0x0 0x40540000 0x0 0x4400>; -- GitLab From 2b9bb988742d1794e78d4297a99658f38477eedd Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:42 -0500 Subject: [PATCH 805/926] arm64: dts: ti: k3-am65-main: Drop deprecated ti,otap-del-sel property ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy. Drop the duplicate and misleading ti,otap-del-sel property. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index bc63d10bad5af..3f8ff25898426 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -469,7 +469,6 @@ sdhci1: mmc@4fa0000 { ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; ti,clkbuf-sel = <0x7>; - ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; }; -- GitLab From 400f4953d53ccc07bb26bb6c9d425934ecab4aa8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:43 -0500 Subject: [PATCH 806/926] arm64: dts: ti: k3-am65-iot2050-common: Rename rtc8564 nodename Just use "rtc" as the nodename to better match with the bindings. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 7d256a1638ff2..6b052a0ecfa1b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -482,7 +482,7 @@ &main_i2c0 { pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; - rtc: rtc8564@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; -- GitLab From 7450aa5153af55a0c63785a6917e35a989a4fdf5 Mon Sep 17 00:00:00 2001 From: Nitin Yadav Date: Tue, 30 May 2023 11:58:54 -0500 Subject: [PATCH 807/926] arm64: dts: ti: k3-am62-main: Add sa3_secproxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nitin Yadav [nm@ti.com: Update commit message, minor updates] Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index b3e4857bbbe47..bf3e054c72ce9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -184,6 +184,21 @@ crypto: crypto@40900000 { dma-names = "tx", "rx1", "rx2"; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; -- GitLab From f7d3b11cacd1fc9596444e89209b80800d20ea22 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:55 -0500 Subject: [PATCH 808/926] arm64: dts: ti: k3-am62a-main: Add sa3_secproxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index e43e64451bc17..8b315cc61550c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -169,6 +169,21 @@ k3_reset: reset-controller { }; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; -- GitLab From 84debc33b529cae428f29b1eb21ccc05c8b47a16 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:56 -0500 Subject: [PATCH 809/926] arm64: dts: ti: k3-am65-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index c2519d4607a53..b7a4b5a89aaf1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -227,6 +227,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + m_can0: can@40528000 { compatible = "bosch,m_can"; reg = <0x0 0x40528000 0x0 0x400>, -- GitLab From c4e43f5aef9731c480789dcb044d261f894a102e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:57 -0500 Subject: [PATCH 810/926] arm64: dts: ti: k3-j7200-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230530165900.47502-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 6a26758af7be0..22084bdf6d262 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -209,6 +209,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- GitLab From 753904da7072646666fa17a5030ef2be871a385a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:58 -0500 Subject: [PATCH 811/926] arm64: dts: ti: k3-j721e-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index bfe3907b4b55b..230d14fe11b4f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -317,6 +317,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- GitLab From 77f622cb8633c020a78cfb8b7d3d73ba3eaf0a44 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:59 -0500 Subject: [PATCH 812/926] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. In addition MCU island has it's own secure proxy for usecases involving the MCU micro controllers. These are in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the nodes for use with bootloaders and firmware that require these communication paths which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since these instances do not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 9c6bb6db59f83..4013f036d371f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -280,6 +295,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- GitLab From 389ad7111ddd99a05c75bc7d4f480a0526761d06 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:59:00 -0500 Subject: [PATCH 813/926] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. In addition MCU island has it's own secure proxy for usecases involving the MCU micro controllers. These are in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the nodes for use with bootloaders and firmware that require these communication paths which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since these instances do not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index ae9a8856bc402..b356845412bfa 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -280,6 +295,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- GitLab From 7f209dd1267ce2a4a5f6a9e4571858fa2d2e588c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:10 -0500 Subject: [PATCH 814/926] arm64: dts: ti: k3-j721e: Add general purpose timers There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. These instantiation differs from J7200 and other SoCs with the device IDs and clocks involved for muxing. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 139 ++++++++++ 2 files changed, 379 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5f35f823a8fa4..784cce413a117 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -945,6 +945,246 @@ serdes4: serdes@5050000 { }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 230d14fe11b4f..edad335de0c26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -70,6 +70,145 @@ mcu_ram: sram@41c00000 { #size-cells = <1>; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; -- GitLab From 72a44d1c473486582d1d6177404e2fa7adf531ac Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:11 -0500 Subject: [PATCH 815/926] arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in Technical Reference Manual[1] under "Timer IO Muxing Control Registers" and "Timer IO Muxing Control Registers", and the "Timers Overview" chapters. We do not expose the cascade_en bit due to the racy usage of independent 32 bit registers in-line with the timer instantiation in the device tree. The MCU timer controls are also marked as reserved for usage by the MCU firmware. [1] http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 18 +++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 22 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 784cce413a117..a40d34f43abc3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -548,6 +548,24 @@ main_pmx0: pinctrl@11c000 { pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index edad335de0c26..ea5b9e104491f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -62,6 +62,28 @@ wkup_pmx0: pinctrl@4301c000 { pinctrl-single,function-mask = <0xffffffff>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; -- GitLab From 835d04422f9d4c232c060150e696075cd34e081a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:12 -0500 Subject: [PATCH 816/926] arm64: dts: ti: k3-j721s2: Add general purpose timers There are 20 general purpose timers on j721s2 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. Though the count is similar to J721e/J7200, the device IDs and clocks used in j721s2 are different with the option of certain clocks having options of additional clock muxes. Since there is very minimal reuse, it is cleaner to integrate as part of SoC files itself. The defaults are configured for clocking the timers from system clock(HFOSC0). Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 140 ++++++++++ 2 files changed, 380 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 6629b2989180e..eeb20353599be 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -125,6 +125,246 @@ rng: rng@4e10000 { }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>; + assigned-clock-parents = <&k3_clks 64 2>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 80 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 80 1>; + assigned-clock-parents = <&k3_clks 80 2>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 81 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 81 1>; + assigned-clock-parents = <&k3_clks 81 2>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 82 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 82 1>; + assigned-clock-parents = <&k3_clks 82 2>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4013f036d371f..4b05399c15366 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -98,6 +98,146 @@ phy_gmii_sel: phy@4040 { }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 83 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 83 1>; + assigned-clock-parents = <&k3_clks 83 2>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 84 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 84 1>; + assigned-clock-parents = <&k3_clks 84 2>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 85 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 85 1>; + assigned-clock-parents = <&k3_clks 85 2>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 86 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 86 1>; + assigned-clock-parents = <&k3_clks 86 2>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 87 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 87 1>; + assigned-clock-parents = <&k3_clks 87 2>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 88 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 88 1>; + assigned-clock-parents = <&k3_clks 88 2>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 89 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 89 1>; + assigned-clock-parents = <&k3_clks 89 2>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 90 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 90 1>; + assigned-clock-parents = <&k3_clks 90 2>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 91 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 91 1>; + assigned-clock-parents = <&k3_clks 91 2>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; -- GitLab From 1ecc75be7bc522941261b5eb0c315b09098a47f4 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:13 -0500 Subject: [PATCH 817/926] arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. The details of the multiplexing can be found in the register documentation and Technical Reference Manual[1]. These are similar to J721e/J7200, but have different mux capabilities. [1] https://www.ti.com/lit/zip/spruj28 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 18 +++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 22 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index eeb20353599be..12a5b7008aca5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -106,6 +106,24 @@ main_pmx0: pinctrl@11c000 { pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x04e00000 0x00 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4b05399c15366..939cd037a814e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -71,6 +71,28 @@ wkup_pmx0: pinctrl@4301c000 { pinctrl-single,function-mask = <0xffffffff>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; reg = <0x00 0x42200000 0x00 0x400>; -- GitLab From 833377cf858b24d45e658454bcb683dd9076b576 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:14 -0500 Subject: [PATCH 818/926] arm64: dts: ti: k3-j784s4: Add general purpose timers There are 20 general purpose timers on j784s4 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. Though the count is similar to J721e/J7200/j721s2, the device IDs and clocks used in j784s4 are different with the option of certain clocks having options of additional clock muxes. Since there is very minimal reuse, it is cleaner to integrate as part of SoC files itself. The defaults are configured for clocking the timers from system clock(HFOSC0). Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 140 ++++++++++ 2 files changed, 380 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 742bab1c5103e..446350f099f3a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -91,6 +91,246 @@ rng: rng@4e10000 { }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 97 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 97 2>; + assigned-clock-parents = <&k3_clks 97 3>; + power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 98 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 98 2>; + assigned-clock-parents = <&k3_clks 98 3>; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 99 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 99 2>; + assigned-clock-parents = <&k3_clks 99 3>; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 100 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 100 2>; + assigned-clock-parents = <&k3_clks 100 3>; + power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 101 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 101 2>; + assigned-clock-parents = <&k3_clks 101 3>; + power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 102 2>; + assigned-clock-parents = <&k3_clks 102 3>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 103 2>; + assigned-clock-parents = <&k3_clks 103 3>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 104 2>; + assigned-clock-parents = <&k3_clks 104 3>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 105 2>; + assigned-clock-parents = <&k3_clks 105 3>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 106 2>; + assigned-clock-parents = <&k3_clks 106 3>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 107 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 107 2>; + assigned-clock-parents = <&k3_clks 107 3>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 108 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 108 2>; + assigned-clock-parents = <&k3_clks 108 3>; + power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 109 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 109 2>; + assigned-clock-parents = <&k3_clks 109 3>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 110 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 110 2>; + assigned-clock-parents = <&k3_clks 110 3>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 111 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 111 2>; + assigned-clock-parents = <&k3_clks 111 3>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 112 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 112 2>; + assigned-clock-parents = <&k3_clks 112 3>; + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 113 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 113 2>; + assigned-clock-parents = <&k3_clks 113 3>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 114 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 114 2>; + assigned-clock-parents = <&k3_clks 114 3>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 115 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 115 2>; + assigned-clock-parents = <&k3_clks 115 3>; + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 116 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 116 2>; + assigned-clock-parents = <&k3_clks 116 3>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index b356845412bfa..591fce5ad56ea 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -97,6 +97,146 @@ phy_gmii_sel: phy@4040 { }; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 2>; + assigned-clock-parents = <&k3_clks 35 3>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 117 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 117 2>; + assigned-clock-parents = <&k3_clks 117 3>; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 118 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 118 2>; + assigned-clock-parents = <&k3_clks 118 3>; + power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 119 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 119 2>; + assigned-clock-parents = <&k3_clks 119 3>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 120 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 120 2>; + assigned-clock-parents = <&k3_clks 120 3>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 121 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 121 2>; + assigned-clock-parents = <&k3_clks 121 3>; + power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 122 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 122 2>; + assigned-clock-parents = <&k3_clks 122 3>; + power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 123 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 123 2>; + assigned-clock-parents = <&k3_clks 123 3>; + power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 124 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 124 2>; + assigned-clock-parents = <&k3_clks 124 3>; + power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 125 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 125 2>; + assigned-clock-parents = <&k3_clks 125 3>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; -- GitLab From 5a41bcff08f9c0705f4e6c576d168051a7b323be Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:15 -0500 Subject: [PATCH 819/926] arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. The details of the multiplexing can be found in the register documentation and Technical Reference Manual[1]. These are similar to J721e/J7200, but have different mux capabilities. [1] http://www.ti.com/lit/zip/spruj52 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 18 +++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 22 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 446350f099f3a..2ea0adae6832f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -72,6 +72,24 @@ main_pmx0: pinctrl@11c000 { pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x4e00000 0x00 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 591fce5ad56ea..4dda88e777ab1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -83,6 +83,28 @@ wkup_gpio_intr: interrupt-controller@42200000 { ti,interrupt-ranges = <16 928 16>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_conf: syscon@40f00000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; -- GitLab From 12bf41da5c3a02a9a6f8059404ba97c39a8f1852 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:07 -0500 Subject: [PATCH 820/926] arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ffb9820cb61f4..c8db9d7ea200e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -826,7 +826,7 @@ &tscadc1 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -1013,55 +1013,55 @@ mbox_c71_0: mbox-c71-0 { }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- GitLab From 7335c987de3e4741908a032914bd3f2979898375 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:08 -0500 Subject: [PATCH 821/926] arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 18 +++++++++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index fa6ac3475290c..2d5d75fffde9b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -23,7 +23,7 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; + pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; sw10: switch-10 { label = "GPIO Key USER1"; @@ -702,7 +702,7 @@ exp5: gpio@20 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 67e52ee3a8bda..7a4c00ca93718 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -373,55 +373,55 @@ mbox_c71_0: mbox-c71-0 { }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- GitLab From d528c29fa7526adf7074fb166b99df7d5fd90670 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:09 -0500 Subject: [PATCH 822/926] arm64: dts: ti: k3-j721e-beagleboneai64: Move camera gpio pinctrl to gpio node Move the GPIO mux configuration needed for camera module to work to the GPIO node instead of the I2C node. Camera nodes are maintained as overlay files, but the common mux is always needed to ensure that camera probes fine and ensuring the mux is configured as part of the GPIO module allows for the multiple overlay files to be simpler. Cc: Robert Nelson Suggested-by: Udit Kumar Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index a7b686cab3e67..e9fadacb4d5ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -593,7 +593,7 @@ &main_i2c0 { &main_i2c1 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; + pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; @@ -623,7 +623,7 @@ &main_i2c4 { &main_i2c5 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; + pinctrl-0 = <&main_i2c5_pins_default>; clock-frequency = <400000>; }; @@ -688,6 +688,11 @@ &wkup_gpio1 { status = "disabled"; }; +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; +}; + &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; -- GitLab From 88875d4c70cabcb509e9836086fdf2064ef89468 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:10 -0500 Subject: [PATCH 823/926] arm64: dts: ti: k3-j721e-beagleboneai64: Move eeprom WP gpio pinctrl to eeprom node Move the eeprom WP GPIO mux configuration to be part of the eeprom node instead of the I2C node. Cc: Robert Nelson Suggested-by: Udit Kumar Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index e9fadacb4d5ad..ecf7811ca8ff0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -639,12 +639,14 @@ &main_i2c6 { &wkup_i2c0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; + pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; }; }; -- GitLab From 4a701c01e7ff96966fcf2cf9df0d3dd851197317 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:11 -0500 Subject: [PATCH 824/926] arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Robert Nelson Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index ecf7811ca8ff0..961ca4fb3a43e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -682,7 +682,8 @@ &main_gpio7 { &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; + pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, + <&mikro_bus_pins_default>; }; &wkup_gpio1 { @@ -766,7 +767,7 @@ serdes2_usb_link: phy@1 { &usbss1 { pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; + pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; ti,vbus-divider; }; @@ -965,55 +966,55 @@ mbox_c71_0: mbox-c71-0 { }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- GitLab From 56ccd4b1eb52e153d557c7c7ae19f849e5d5c2e1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:12 -0500 Subject: [PATCH 825/926] arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Wadim Egorov Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8199ac06c09aa..8d9ca6e5b087c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -76,7 +76,7 @@ key-menu { leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default &user_leds_pins_default>; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; led-1 { color = ; -- GitLab From a6550e2547acbcd7b01ea26d447a437140df7c43 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:13 -0500 Subject: [PATCH 826/926] arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e1017027d6499..e8a2997289ba1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -203,7 +203,7 @@ &wkup_gpio1 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 2a743b8950742..e763d571b9162 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -214,25 +214,25 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; -- GitLab From 6a2baa853500d1bbe986f29aacce4a0c859bf017 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:14 -0500 Subject: [PATCH 827/926] arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 924e0dc4ac1e5..a5ba2945c35f9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -327,7 +327,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { -- GitLab From 875aad10d219494bb0ef0880b1b4a33f99c98a13 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:15 -0500 Subject: [PATCH 828/926] arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 729f95e190423..c0a69093c324e 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -183,8 +183,7 @@ &sdhci1 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default - &main_rgmii2_pins_default>; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; &cpsw_port2 { -- GitLab From bb867df51d3b7f305222405c4e01373efc8866c7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:16 -0500 Subject: [PATCH 829/926] arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-11-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 309500e4c2372..c3fd417f3842b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -487,8 +487,7 @@ &usb0 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -615,25 +614,25 @@ mbox_m4_0: mbox-m4-0 { }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; -- GitLab From 0e97d245633bffc0ae348c95f98a2af5b973811c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:17 -0500 Subject: [PATCH 830/926] arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-12-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 9ea012b883e8a..3e27bd65cb2e9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -480,8 +480,7 @@ &usb0 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -613,25 +612,25 @@ mbox_m4_0: mbox-m4-0 { }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; -- GitLab From f722090aeb70ca67b5f5a37a39a26fca29664dce Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:18 -0500 Subject: [PATCH 831/926] arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Jan Kiszka Reviewed-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-13-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 17 ++++++++--------- .../dts/ti/k3-am6548-iot2050-advanced-m2.dts | 18 ++++++++---------- 2 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6b052a0ecfa1b..bbbb5c169ccc0 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -384,13 +384,12 @@ &main_gpio0 { &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &arduino_io_d2_to_d3_pins_default - &arduino_i2c_aio_switch_pins_default - &arduino_io_oe_pins_default - &push_button_pins_default - &db9_com_mode_pins_default - >; + pinctrl-0 = + <&arduino_io_d2_to_d3_pins_default>, + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; gpio-line-names = /* 0..9 */ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", @@ -711,11 +710,11 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 9400e35882a6e..9209b5a7baa4d 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -66,20 +66,18 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ &main_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_pcie_mux_control - &arduino_io_d4_to_d9_pins_default - >; + pinctrl-0 = + <&main_m2_pcie_mux_control>, + <&arduino_io_d4_to_d9_pins_default>; }; &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_enable_pins_default - &main_pmx0_m2_config_pins_default - &main_pmx1_m2_config_pins_default - &cp2102n_reset_pin_default - >; + pinctrl-0 = + <&main_m2_enable_pins_default>, + <&main_pmx0_m2_config_pins_default>, + <&main_pmx1_m2_config_pins_default>, + <&cp2102n_reset_pin_default>; }; /* -- GitLab From 9da060be7491cc67323b8f4386ebc4524eba5970 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:19 -0500 Subject: [PATCH 832/926] arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 73dd50586c64a..c8c80cd756d9a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -520,13 +520,13 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; &ospi0 { -- GitLab From 918ef215db22b18b75292b6e5bcb763ce27e0483 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:20 -0500 Subject: [PATCH 833/926] arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-15-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 27a43a8ecffd4..ae9116655a831 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -287,7 +287,7 @@ &main_sdhci1 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { -- GitLab From 74428680d71a37e6ee458b6eccf085114e0e4167 Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Mon, 5 Jun 2023 23:15:51 +0530 Subject: [PATCH 834/926] arm64: dts: ti: k3-am69-sk: Add eMMC mmc0 support Add support for eMMC card connected to main sdhci0 instance. Signed-off-by: Dasnavis Sabiya Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230605174551.160262-1-sabiya.d@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790e..3099c0098ca68 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -22,6 +22,7 @@ chosen { aliases { serial2 = &main_uart8; + mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; i2c0 = &main_i2c0; }; @@ -165,6 +166,14 @@ exp1: gpio@21 { }; }; +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &main_sdhci1 { /* SD card */ status = "okay"; -- GitLab From 1f36d0e8be3ae7717c801e954275fba6247b2f46 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 5 Jun 2023 16:34:43 +0530 Subject: [PATCH 835/926] arm64: dts: ti: k3-j721s2: Change CPTS clock parent MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's capability to re-initialise clock frequencies. CPTS and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs this reinitialisation to default frequency to be able to get 250MHz with its divider, CPTS can not get its required 200MHz with its divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side for the same reason) Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 12a5b7008aca5..ed79ab3a32718 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1030,6 +1030,8 @@ cpts@310d0000 { reg-names = "cpts"; clocks = <&k3_clks 226 5>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 939cd037a814e..5734c67b6763d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -525,6 +525,8 @@ cpts@3d000 { reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 29 3>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; -- GitLab From c10a9df30e3401bd5a5ee43f1afd6c2b2ca75ad7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:30 -0500 Subject: [PATCH 836/926] arm64: dts: ti: k3-j784s4-evm: Fix main_i2c0 alias main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: e20a06aca5c9 ("arm64: dts: ti: Add support for J784S4 EVM board") Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 8271ac16b3193..bf22b86cca93b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -23,7 +23,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { -- GitLab From 14462bd0b247d05070d48d0f02eb7ca2680ab7bd Mon Sep 17 00:00:00 2001 From: Thejasvi Konduru Date: Wed, 3 May 2023 14:01:43 +0530 Subject: [PATCH 837/926] arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets The wkup_pmx register region in j784s4 has multiple non-addressable regions, hence the existing wkup_pmx region is split as follows to avoid the non-addressable regions. The pinctrl node offsets are also corrected as per the newly split wkup_pmx* nodes. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Thejasvi Konduru Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230503083143.32369-1-t-konduru@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 30 +++++++++---------- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 29 +++++++++++++++++- 2 files changed, 43 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index bf22b86cca93b..e51471f8e1fde 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -285,28 +285,28 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 4dda88e777ab1..657fb1d72512c 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -65,7 +65,34 @@ mcu_ram: sram@41c00000 { wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- GitLab From 6fa5d37a2f34476613012789d4618c3dc6c68b35 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:31 -0500 Subject: [PATCH 838/926] arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index e51471f8e1fde..de7c44af3bec0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -20,6 +20,8 @@ chosen { }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -286,6 +288,24 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -370,6 +390,19 @@ J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; -- GitLab From 5dfbd1debc8ce5123310265cd44b5d99d272b1fe Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:32 -0500 Subject: [PATCH 839/926] arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index de7c44af3bec0..09f052c948447 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -25,6 +25,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; }; @@ -297,6 +298,13 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ @@ -397,6 +405,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- GitLab From b38c6ced4ec5b3f6260ff6cc2b71e8a3d8c897d7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:33 -0500 Subject: [PATCH 840/926] arm64: dts: ti: k3-am69-sk: Fix main_i2c0 alias main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: 635fb18ba008 ("arch: arm64: dts: Add support for AM69 Starter Kit") Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 3099c0098ca68..d51e1123e6b18 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -24,7 +24,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { -- GitLab From 7b72bd25508de6a5eee2cb1679b9d4b8bc25de5a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:34 -0500 Subject: [PATCH 841/926] arm64: dts: ti: k3-am69-sk: Enable mcu network port Enable networking for NFS and basic networking functionality. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d51e1123e6b18..21949106a1075 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -25,6 +25,7 @@ aliases { mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; }; memory@80000000 { @@ -140,6 +141,32 @@ J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ }; }; +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -187,3 +214,24 @@ &main_sdhci1 { &main_gpio0 { status = "okay"; }; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; +}; + +&davinci_mdio { + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; -- GitLab From 45299dd1991b496ddab5ab4a86d7ae601e0e4c7f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:35 -0500 Subject: [PATCH 842/926] arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 21949106a1075..125e4af174f6d 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -21,6 +21,8 @@ chosen { }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -142,6 +144,22 @@ J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -167,6 +185,19 @@ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; -- GitLab From 08ae12b637507cd22fbcdb82521b8b8a5ae96222 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:36 -0500 Subject: [PATCH 843/926] arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 125e4af174f6d..08ec94289beb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -26,6 +26,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; }; @@ -153,6 +154,13 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ @@ -192,6 +200,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- GitLab From 0ec1a48d99ddd11c265f7f1b2573fb2c8e0db0ab Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Fri, 2 Jun 2023 16:49:37 -0500 Subject: [PATCH 844/926] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by: Dasnavis Sabiya Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 63 +++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 08ec94289beb7..6e12a45a22875 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -142,6 +142,25 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; }; &wkup_pmx2 { @@ -168,6 +187,13 @@ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -191,6 +217,28 @@ J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + >; + }; }; &wkup_uart0 { @@ -213,12 +261,25 @@ eeprom@51 { }; }; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -265,6 +326,8 @@ &main_sdhci1 { &main_gpio0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &mcu_cpsw { -- GitLab From 27f98f3eca7334fec668ec637ed5e0514458bba8 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 1 Jun 2023 13:49:32 -0500 Subject: [PATCH 845/926] arm64: dts: ti: k3-am64: Only set UART baud for used ports As the binding for "current-speed" states, this should only be used when the baud rate of an attached device cannot be detected. This is the case for our attached on-board USB-to-UART converter used for early kernel console. For all other unconnected/disabled ports this can be configured in userspace later, DT is not the place for device configuration, especially when there are already standard ways to set serial baud in userspace. Remove setting baud for all disabled serial ports and move setting it for the couple enabled ports down into the board files. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ------- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + 5 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 3c387d479b366..71081970edd8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -377,7 +377,6 @@ main_uart0: serial@2800000 { reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; @@ -389,7 +388,6 @@ main_uart1: serial@2810000 { reg = <0x00 0x02810000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; @@ -401,7 +399,6 @@ main_uart2: serial@2820000 { reg = <0x00 0x02820000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; @@ -413,7 +410,6 @@ main_uart3: serial@2830000 { reg = <0x00 0x02830000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; @@ -425,7 +421,6 @@ main_uart4: serial@2840000 { reg = <0x00 0x02840000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; @@ -437,7 +432,6 @@ main_uart5: serial@2850000 { reg = <0x00 0x02850000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; @@ -449,7 +443,6 @@ main_uart6: serial@2860000 { reg = <0x00 0x02860000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 31336b0e290e5..67ad414a5eab9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -55,7 +55,6 @@ mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; @@ -66,7 +65,6 @@ mcu_uart1: serial@4a10000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index c3fd417f3842b..4fd5c398a1653 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -375,6 +375,7 @@ &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; /* main_uart1 is reserved for firmware usage */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8d9ca6e5b087c..59c091bc30ab0 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -251,6 +251,7 @@ &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { @@ -258,6 +259,7 @@ &main_uart1 { pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + current-speed = <115200>; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3e27bd65cb2e9..44e18c89beda1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -369,6 +369,7 @@ &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { -- GitLab From 6b343136388fe1ef5837e45ab921705de76665ee Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 1 Jun 2023 13:49:33 -0500 Subject: [PATCH 846/926] arm64: dts: ti: k3-am64: Use phandle to stdout UART node Using a phandle makes it clear which UART we are choosing without needing to resolve through an alias first. Especially useful for boards like the TI J721s2-EVM where the alias is "serial2" but it actually resolves to the 8th UART instance(main_uart8). Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 4fd5c398a1653..e897feacd1224 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -17,7 +17,7 @@ / { model = "Texas Instruments AM642 EVM"; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &main_uart0; }; aliases { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 44e18c89beda1..78ae490a0c762 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -17,7 +17,7 @@ / { model = "Texas Instruments AM642 SK"; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &main_uart0; }; aliases { -- GitLab From acfb362a9c78d6708080cdd850b036225c78371b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:43 -0500 Subject: [PATCH 847/926] arm64: dts: ti: k3-j721e-sk: Add missing uart pinmuxes Rather than depend on the default pinmuxes, explicitly describe the pinmux Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 31 ++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index c8db9d7ea200e..1969c62262a28 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -302,6 +302,13 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ @@ -495,6 +502,22 @@ J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ @@ -513,11 +536,14 @@ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -530,7 +556,8 @@ &main_uart0 { &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_sdhci0 { -- GitLab From 1b4b376c878b36d1a1c848ebc885487e4cad2546 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:44 -0500 Subject: [PATCH 848/926] arm64: dts: ti: k3-j721e-sk: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 1969c62262a28..0b15c44e0e668 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -540,6 +540,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- GitLab From 26efc8d1ad0cc14e2740d310935fa146b1fc5a58 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:45 -0500 Subject: [PATCH 849/926] arm64: dts: ti: j721e-som/common-proc-board: Add product links Add product links to get reference to schematics and design files Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d5d75fffde9b..84336376aad19 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 7a4c00ca93718..1326b09a9c363 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ /dts-v1/; -- GitLab From 86718345b4d3c0d386b3f73ef43e7f72ff04cf4a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:46 -0500 Subject: [PATCH 850/926] arm64: dts: ti: j721e-common-proc-board: Add uart pinmux Explicitly define the pinmux rather than depend on bootloader configured pinmux for the platform. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721e-common-proc-board.dts | 62 +++++++++++++++++-- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 84336376aad19..fa90943217291 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -174,6 +174,36 @@ dp_connector_in: endpoint { }; &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ + J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ + >; + }; + + main_uart4_pins_default: main-uart4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ + J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ + >; + }; + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ @@ -295,6 +325,22 @@ J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + sw11_button_pins_default: sw11-button-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ @@ -375,32 +421,40 @@ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; }; &main_uart4 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins_default>; }; &main_gpio2 { -- GitLab From b04b18ccb3d5c19c864c10f7cc7b014218aecb22 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:47 -0500 Subject: [PATCH 851/926] arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 1326b09a9c363..643ecac9effec 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -188,6 +188,19 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- GitLab From 4c2c99026ca1525912b40cbc1b69306145ce7082 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:48 -0500 Subject: [PATCH 852/926] arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmux Define the wakeup uart pin-mux for completeness. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 961ca4fb3a43e..27347a07d3309 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -20,6 +20,7 @@ / { model = "BeagleBoard.org BeagleBone AI-64"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -531,6 +532,13 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + mcu_usbss1_pins_default: mcu-usbss1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ @@ -541,6 +549,8 @@ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO &wkup_uart0 { /* Wakeup UART is used by TIFS firmware. */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { -- GitLab From d1a4304c149d1a26a912d532501ead42e5952501 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:49 -0500 Subject: [PATCH 853/926] arm64: dts: ti: k3-j721e-sk: Define aliases at board level Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0b15c44e0e668..ce6eb93fca9e2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -16,6 +16,15 @@ / { compatible = "ti,j721e-sk", "ti,j721e"; model = "Texas Instruments J721E SK"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + ethernet0 = &cpsw_port1; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- GitLab From ff59580bf2580ec262098399aab03dfca537bec8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:50 -0500 Subject: [PATCH 854/926] arm64: dts: ti: k3-j721e-common-proc-board: Define aliases at board level Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index fa90943217291..5fc002e5a18c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -17,6 +17,18 @@ / { compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial6 = &main_uart4; + ethernet0 = &cpsw_port1; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- GitLab From 8be20986e0c54420e52048d20bdc31e3a8aec93f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:51 -0500 Subject: [PATCH 855/926] arm64: dts: ti: k3-j721e: Drop SoC level aliases Drop the SoC level aliases as these need to be done at board level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 99436105ada1b..95f67e1d0c01a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -18,25 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - mmc2 = &main_sdhci2; - }; - chosen { }; cpus { -- GitLab From c8a28ed4837ce03254e0941f4fbc8364b1e78543 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:35 +0530 Subject: [PATCH 856/926] arm64: dts: ti: k3-j7200: Add general purpose timers There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by: Udit Kumar Reviewed-by: Tony Lindgren Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 240 ++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 130 ++++++++++ 2 files changed, 370 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d2..c6b15aceea82e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -971,6 +971,246 @@ watchdog1: watchdog@2210000 { assigned-clock-parents = <&k3_clks 253 5>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 22084bdf6d262..d76510b55af6a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,136 @@ k3_reset: reset-controller { }; }; + mcu_timer0: timer@40400000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; -- GitLab From 03612d384621ffe21c6d338de916251d1bfd84fa Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:36 +0530 Subject: [PATCH 857/926] arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 +++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c6b15aceea82e..a9b3bf8a5c6a7 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ cpts@3d000 { }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index d76510b55af6a..e66c2495f54d9 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -183,6 +183,26 @@ chipid@43000014 { reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ -- GitLab From 7f58e2b418d89f38f242b04da5a1dd93a2c514fd Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:37 +0530 Subject: [PATCH 858/926] arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e8a2997289ba1..ea5a4a61e531b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -112,13 +112,6 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ -- GitLab From 3709ea7f960ed77ac29af692c9e32351060400d9 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:38 +0530 Subject: [PATCH 859/926] arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j7200-common-proc-board.dts | 58 ++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ea5a4a61e531b..7d67e4b731b2c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,6 +79,24 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; }; +&wkup_pmx0 { + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < @@ -112,6 +130,29 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ + J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ + J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -150,22 +191,30 @@ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { status = "okay"; /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { @@ -173,6 +222,13 @@ &main_uart2 { status = "reserved"; }; +&main_uart3 { + /* Shared with MCAN Interface */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; +}; + &main_gpio2 { status = "disabled"; }; -- GitLab From c4ba159fff90791956370ce93c130aadea87dbb6 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:39 +0530 Subject: [PATCH 860/926] arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board level Define aliases at board level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 7d67e4b731b2c..b5159a30108c9 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -15,6 +15,16 @@ / { compatible = "ti,j7200-evm", "ti,j7200"; model = "Texas Instruments J7200 EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial5 = &main_uart3; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- GitLab From 858dde8a3f56f0b7a0c217ac4abf56e34c34ae74 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:40 +0530 Subject: [PATCH 861/926] arm64: dts: ti: k3-j7200: Drop SoC level aliases Aiases are defined at board level, so dropping from soc level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-7-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 6c96759e87524..3b3a1af7d60de 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -18,23 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - chosen { }; cpus { -- GitLab From 6bc829ceea4158c7aeb3a9e73d5c52634d78fb6f Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Fri, 2 Jun 2023 10:35:49 -0500 Subject: [PATCH 862/926] arm64: dts: ti: k3-j721s2: Fix wkup pinmux range The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable regions, accordingly split the existing wkup_pmx region as follows to avoid the non-addressable regions and include the rest of valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: # 6.3 Signed-off-by: Sinthu Raja Signed-off-by: Thejasvi Konduru Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 42 +++++----- .../dts/ti/k3-j721s2-common-proc-board.dts | 76 +++++++++---------- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 29 ++++++- 3 files changed, 87 insertions(+), 60 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index ae9116655a831..37b598e98f8bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -175,49 +175,49 @@ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; mcu_mcan0_pins_default: mcu-mcan0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; mcu_i2c1_pins_default: mcu-i2c1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a5ba2945c35f9..aef62ac9b6895 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -154,81 +154,81 @@ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; mcu_mcan0_pins_default: mcu-mcan0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; mcu_adc0_pins_default: mcu-adc0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ >; }; mcu_adc1_pins_default: mcu-adc1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5734c67b6763d..e7dd947a1814b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -65,7 +65,34 @@ mcu_ram: sram@41c00000 { wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02C>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- GitLab From 92fee724058d5272f1b1be7805fe3cdf0f561c8f Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Fri, 2 Jun 2023 10:35:50 -0500 Subject: [PATCH 863/926] arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header Add pinmux required to bring out the i2c and gpios on 40-pin RPi expansion header on the AM68 SK board. Signed-off-by: Sinthu Raja Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 77 ++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 37b598e98f8bd..014ff13d10325 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -173,6 +173,32 @@ J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ >; }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ + >; + }; }; &wkup_pmx2 { @@ -214,12 +240,46 @@ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ + >; + }; + mcu_i2c1_pins_default: mcu-i2c1-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; + + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ + J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ + J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ + J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &main_gpio2 { @@ -235,7 +295,8 @@ &main_gpio6 { }; &wkup_gpio0 { - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; &wkup_gpio1 { @@ -271,6 +332,20 @@ exp1: gpio@21 { }; }; +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_sdhci0 { /* Unused */ status = "disabled"; -- GitLab From 4c8c2471c7b6230fc41cf839c7b2ead836e71a6c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:51 -0500 Subject: [PATCH 864/926] arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmux Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 014ff13d10325..979898bc5b023 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -22,6 +22,8 @@ chosen { }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; can0 = &mcu_mcan0; @@ -202,6 +204,15 @@ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ @@ -254,6 +265,13 @@ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ @@ -305,6 +323,14 @@ &wkup_gpio1 { &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { -- GitLab From 7d9b3820d756584939ed6d5e4c010aa5927edcc8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:52 -0500 Subject: [PATCH 865/926] arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Sinthu Raja Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index e92431250729a..e2c80fff74786 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,3 +27,25 @@ secure_ddr: optee@9e800000 { }; }; }; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; -- GitLab From f5e9ee0b354ac5a02871959c4dad80acfc0fda6b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:53 -0500 Subject: [PATCH 866/926] arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-j721s2-common-proc-board.dts | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index aef62ac9b6895..e7136ddb91781 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -155,6 +155,24 @@ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ @@ -265,11 +283,14 @@ &wkup_gpio1 { &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { -- GitLab From 9d0350e8a46cae9c77abef1c8193b01a39e64f71 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:54 -0500 Subject: [PATCH 867/926] arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index d473d79c27574..c1a6c36cde1de 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -61,6 +61,15 @@ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -77,6 +86,19 @@ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; -- GitLab From 444f312a73f789bb9f10bbb423f7ae6c3aa76198 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:24 +0530 Subject: [PATCH 868/926] dt-bindings: misc: esm: Add ESM support for TI K3 devices Document the binding for TI K3 ESM (Error Signaling Module) block. Signed-off-by: Neha Malcom Francis Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- .../bindings/misc/ti,j721e-esm.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml diff --git a/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml new file mode 100644 index 0000000000000..0c9a8444844c5 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 ESM + +maintainers: + - Neha Malcom Francis + +description: + The ESM (Error Signaling Module) is an IP block on TI K3 devices + that allows handling of safety events somewhat similar to what interrupt + controller would do. The safety signals have their separate paths within + the SoC, and they are handled by the ESM, which routes them to the proper + destination, which can be system reset, interrupt controller, etc. In the + simplest configuration the signals are just routed to reset the SoC. + +properties: + compatible: + const: ti,j721e-esm + + reg: + maxItems: 1 + + ti,esm-pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + integer array of ESM interrupt pins to route to external event pin + which can be used to reset the SoC. + minItems: 1 + maxItems: 255 + +required: + - compatible + - reg + - ti,esm-pins + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; + }; -- GitLab From 19bfd51845d551c6f4e39969c13c6b8285b94d1c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:25 +0530 Subject: [PATCH 869/926] arm64: dts: ti: k3-j721e: Add ESM support Add address entry mapping ESM on J721E. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index a40d34f43abc3..2ded1ee1a8541 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2716,4 +2716,10 @@ main_spi7: spi@2170000 { clocks = <&k3_clks 273 1>; status = "disabled"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 95f67e1d0c01a..a200810df54a5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -113,6 +113,7 @@ cbass_main: bus@100000 { #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ -- GitLab From e3d1f2768853f375b87a1c6fc00501165ddae49d Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:26 +0530 Subject: [PATCH 870/926] arm64: dts: ti: k3-j7200: Add ESM support Add address entry mapping ESM on J7200. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230504080526.133149-4-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a9b3bf8a5c6a7..ac62bbc1660d5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1268,4 +1268,10 @@ main_r5fss0_core1: r5f@5d00000 { ti,loczrama = <1>; }; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <656>, <657>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 3b3a1af7d60de..ef73e6d7e8581 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -112,6 +112,7 @@ cbass_main: bus@100000 { #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ -- GitLab From a58eedd1d195f17418c327482a79de5b84bc5aa8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 13:53:34 -0500 Subject: [PATCH 871/926] arm64: dts: ti: k3-am62: Add ESM support Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530185335.79942-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index bf3e054c72ce9..2488e3a537fe4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -207,6 +207,12 @@ main_pmx0: pinctrl@f4000 { pinctrl-single,function-mask = <0xffffffff>; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + }; + main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 076601a41e843..19fc38157d94e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -14,6 +14,12 @@ mcu_pmx0: pinctrl@4084000 { pinctrl-single,function-mask = <0xffffffff>; }; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + }; + /* * The MCU domain timer interrupts are routed only to the ESM module, * and not currently available for Linux. The MCU domain timers are -- GitLab From f049b541b81acd88133c2c2247d4fae6c33f1b99 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 13:53:35 -0500 Subject: [PATCH 872/926] arm64: dts: ti: k3-am64: Add ESM support Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 71081970edd8c..1664d9f0241c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -372,6 +372,12 @@ main_timer11: timer@24b0000 { ti,timer-pwm; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 67ad414a5eab9..686d497907218 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -152,4 +152,10 @@ mcu_pmx0: pinctrl@4084000 { pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>; + }; }; -- GitLab From 4af0332876f945ea1784970727c231f2cfaa3b23 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:47 -0500 Subject: [PATCH 873/926] arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 643ecac9effec..8431f5f57cd25 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,6 +201,19 @@ eeprom@50 { }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- GitLab From 4c3cdac1955a5274a42d915e98827ba0f136c286 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 24 Apr 2023 12:36:21 -0500 Subject: [PATCH 874/926] arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodename unit-address should not use a 0x prefix. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230424173623.477577-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index e66c2495f54d9..c5e4c41effd18 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -212,7 +212,7 @@ wkup_pmx0: pinctrl@4301c000 { pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx1: pinctrl@0x4301c038 { + wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; @@ -221,7 +221,7 @@ wkup_pmx1: pinctrl@0x4301c038 { pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx2: pinctrl@0x4301c068 { + wkup_pmx2: pinctrl@4301c068 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; @@ -230,7 +230,7 @@ wkup_pmx2: pinctrl@0x4301c068 { pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx3: pinctrl@0x4301c174 { + wkup_pmx3: pinctrl@4301c174 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; -- GitLab From 94a58c5f131d7f0cf735af24574b7626aab77ab1 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 4 May 2023 16:01:42 +0200 Subject: [PATCH 875/926] dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Add devicetree bindings for AM62x based phyCORE-AM62 SoM and phyBOARD-Lyra RDK. Signed-off-by: Wadim Egorov Acked-by: Krzysztof Kozlowski Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230504140143.1425951-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e1183f90bb068..254b5ec51f340 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra + items: + - const: phytec,am625-phyboard-lyra-rdk + - const: phytec,am62-phycore-som + - const: ti,am625 + - description: K3 AM625 SoC items: - enum: -- GitLab From 621a046d9b2f38a2fccb1651cbe4351f586e80a1 Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Mon, 17 Apr 2023 20:39:56 +0800 Subject: [PATCH 876/926] arm64: dts: mt8173: Power on panel regulator on boot Add "regulator-boot-on" to "panel_fixed_3v3" to save time on powering the regulator during boot. Also add "off-on-delay-us" to the node to make sure the regulator never violates the panel timing requirements. Signed-off-by: Pin-yen Lin Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20230417123956.926266-1-treapking@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index d77f6af19065e..03d1ab2ca8203 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -96,6 +96,8 @@ panel_fixed_3v3: regulator1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; + regulator-boot-on; + off-on-delay-us = <500000>; gpio = <&pio 41 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&panel_fixed_pins>; -- GitLab From 7afe7b5969329175ac4f55a6b9c13ba4f6dc267e Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sun, 28 May 2023 13:33:42 +0200 Subject: [PATCH 877/926] arm64: dts: mt7986: use size of reserved partition for bl2 To store uncompressed bl2 more space is required than partition is actually defined. There is currently no known usage of this reserved partition. Openwrt uses same partition layout. We added same change to u-boot with commit d7bb1099 [1]. [1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e Cc: stable@vger.kernel.org Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Daniel Golle Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso index 84aa229e80f37..e48881be4ed60 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -27,15 +27,10 @@ partitions { partition@0 { label = "bl2"; - reg = <0x0 0x20000>; + reg = <0x0 0x40000>; read-only; }; - partition@20000 { - label = "reserved"; - reg = <0x20000 0x20000>; - }; - partition@40000 { label = "u-boot-env"; reg = <0x40000 0x40000>; -- GitLab From 6322555dbeb46c512d6be42c3829087af4e4db9d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 26 May 2023 18:08:01 +0800 Subject: [PATCH 878/926] arm64: dts: mediatek: mt8173-elm: remove panel model number in DT Currently a specific panel number is used in the Elm DTSI, which is corresponded to a 12" panel. However, according to the official Chrome OS devices document, Elm refers to Acer Chromebook R13, which, as the name specifies, uses a 13.3" panel, which comes with EDID information. As the kernel currently prioritizes the hardcoded timing parameters matched with the panel number compatible, a wrong timing will be applied to the 13.3" panel on Acer Chromebook R13, which leads to blank display. Because the Elm DTSI is shared with Hana board, and Hana corresponds to multiple devices from 11" to 14", a certain panel model number shouldn't be present, and driving the panel according to its EDID information is necessary. Signed-off-by: Icenowy Zheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20230526100801.16310-1-uwu@icenowy.me Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 03d1ab2ca8203..111495622cacd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -287,7 +287,7 @@ ps8640_out: endpoint { aux-bus { panel: panel { - compatible = "lg,lp120up1"; + compatible = "edp-panel"; power-supply = <&panel_fixed_3v3>; backlight = <&backlight>; -- GitLab From 9d498cce9298a71e3896e2d1aee24a1a4c531d81 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 17 Mar 2023 14:19:44 +0800 Subject: [PATCH 879/926] arm64: dts: mediatek: Add cpufreq nodes for MT8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the cpufreq nodes for MT8192 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index faaff39155dca..d28f5b1bc5512 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -70,6 +70,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -87,6 +88,7 @@ cpu1: cpu@100 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -104,6 +106,7 @@ cpu2: cpu@200 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -121,6 +124,7 @@ cpu3: cpu@300 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -138,6 +142,7 @@ cpu4: cpu@400 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -155,6 +160,7 @@ cpu5: cpu@500 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -172,6 +178,7 @@ cpu6: cpu@600 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -189,6 +196,7 @@ cpu7: cpu@700 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -405,6 +413,12 @@ soc { compatible = "simple-bus"; ranges; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; -- GitLab From 1b85a4256ec193f5016b7c8973cbf7f01d11d5f9 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 3 Mar 2023 09:38:39 +0800 Subject: [PATCH 880/926] arm64: dts: mt8192: Add video-codec nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add video-codec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230303013842.23259-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index d28f5b1bc5512..693c55c5f11ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1641,6 +1641,65 @@ larb11: larb@1582e000 { power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; }; + vcodec_dec: video-codec@16000000 { + compatible = "mediatek,mt8192-vcodec-dec"; + reg = <0 0x16000000 0 0x1000>; + mediatek,scp = <&scp>; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0x16000000 0 0x26000>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0x0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + interrupts = ; + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1600d000 0 0x1000>; -- GitLab From 64bceed383fbce8ef54200d2849935096fe8f831 Mon Sep 17 00:00:00 2001 From: Yunfei Dong Date: Fri, 3 Mar 2023 09:38:42 +0800 Subject: [PATCH 881/926] arm64: dts: mt8195: Add video decoder node Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230303013842.23259-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b53e959911999..4dbbf8fdab758 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2370,6 +2370,76 @@ larb18: larb@17201000 { power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "sel", "vdec", "lat", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>; -- GitLab From 127e33f91ed90db67fe8e18eb48054f9a96e809f Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Mon, 20 Feb 2023 17:33:43 +0800 Subject: [PATCH 882/926] arm64: dts: mediatek: mt8183: kukui: Add scp firmware-name The upstream SCP firmware path is /lib/firmware/mediatek/mt8183/scp.img Signed-off-by: Hsin-Yi Wang Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230220093343.3447381-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 8892b2f64a0f0..6ce16a265e053 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -826,6 +826,8 @@ &pwm0 { &scp { status = "okay"; + + firmware-name = "mediatek/mt8183/scp.img"; pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; -- GitLab From 6970cadb216cef7951bc915a841123d0967e08bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Thu, 1 Jun 2023 16:32:21 -0400 Subject: [PATCH 883/926] arm64: dts: mediatek: mt8192: Add missing dma-ranges to soc node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the series "Adjust the dma-ranges for MTK IOMMU", the mtk-iommu driver was adapted to separate the iova range based on the larb used, and a dma-ranges property was added to the soc node in the devicetree of the affected SoCs allowing the whole 16GB iova range to be used. Except that for mt8192, there was no patch adding dma-ranges. Add the missing dma-ranges property to the soc node like was done for mt8195 and mt8186. This fixes the usage of the vcodec, which would otherwise trigger iommu faults. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230601203221.3675915-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 693c55c5f11ae..bab403a43c4d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -411,6 +411,7 @@ soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; + dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; performance: performance-controller@11bc10 { -- GitLab From a4366b5695c984b8a3fc8b31de9e758c8f6d1aed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Fri, 2 Jun 2023 14:35:15 -0400 Subject: [PATCH 884/926] arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A76) cluster at a maximum of 2200MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculated the mean result for each cluster 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scaled results to 1024: result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 12016411 Dhry/s Cluster 1 (BIG): 31702034 Dhry/s The calculated scaled results are: Cluster 0: 426.953226899238 (rounded to 427) Cluster 1: 1024 Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230602183515.3778780-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index bab403a43c4d8..69f4cded5dbbf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -71,7 +71,7 @@ cpu0: cpu@0 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu1: cpu@100 { @@ -89,7 +89,7 @@ cpu1: cpu@100 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu2: cpu@200 { @@ -107,7 +107,7 @@ cpu2: cpu@200 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu3: cpu@300 { @@ -125,7 +125,7 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu4: cpu@400 { -- GitLab From 0a9615d58d0494802ffdd99c3d6d3d13b70687b8 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 30 May 2023 22:12:33 +0200 Subject: [PATCH 885/926] arm64: dts: mt7986: add thermal and efuse Add thermal related nodes to mt7986 devicetree. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index aa9e679b78e2b..ad4fd77b65a78 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -337,6 +337,15 @@ spi1: spi@1100b000 { status = "disabled"; }; + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + ssusb: usb@11200000 { compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; @@ -375,6 +384,21 @@ mmc0: mmc@11230000 { status = "disabled"; }; + thermal: thermal@1100c800 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + pcie: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; @@ -426,6 +450,17 @@ pcie_port: pcie-phy@11c00000 { }; }; + efuse: efuse@11d00000 { + compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; + reg = <0 0x11d00000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@274 { + reg = <0x274 0xc>; + }; + }; + usb_phy: t-phy@11e10000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; @@ -567,5 +602,4 @@ wifi: wifi@18000000 { memory-region = <&wmcpu_emi>; }; }; - }; -- GitLab From 1f5be05132f38cdc2f11e12f9d0b6cf0f106d568 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 30 May 2023 22:12:34 +0200 Subject: [PATCH 886/926] arm64: dts: mt7986: add thermal-zones Add thermal-zones to mt7986 devicetree. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index ad4fd77b65a78..68539ea788dfc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -602,4 +602,32 @@ wifi: wifi@18000000 { memory-region = <&wmcpu_emi>; }; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + + trips { + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + }; + }; }; -- GitLab From c26f779a2295b81891078cc6f791856fa2705b50 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 30 May 2023 22:12:35 +0200 Subject: [PATCH 887/926] arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index be96f59e63529..af4a4309bda4b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -38,6 +38,15 @@ dcin: regulator-12vd { regulator-always-on; }; + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* cooling level (0, 1, 2) - pwm inverted */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000 0>; + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -133,6 +142,28 @@ sfp2: sfp-2 { }; }; +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; +}; + &crypto { status = "okay"; }; -- GitLab From 32dfbc03fc26a5aeeaff5b34d3d45f94be21cfae Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 9 Jun 2023 15:29:02 +0800 Subject: [PATCH 888/926] arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230609072906.2784594-2-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 101 +++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 8c02232cac38f..93f3c45ba3723 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -27,6 +27,99 @@ aliases { rdma1 = &rdma1; }; + cci: cci { + compatible = "mediatek,mt8186-cci"; + clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <600000>; + }; + + cci_opp_1: opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-microvolt = <675000>; + }; + + cci_opp_2: opp-612000000 { + opp-hz = /bits/ 64 <612000000>; + opp-microvolt = <693750>; + }; + + cci_opp_3: opp-682000000 { + opp-hz = /bits/ 64 <682000000>; + opp-microvolt = <718750>; + }; + + cci_opp_4: opp-752000000 { + opp-hz = /bits/ 64 <752000000>; + opp-microvolt = <743750>; + }; + + cci_opp_5: opp-822000000 { + opp-hz = /bits/ 64 <822000000>; + opp-microvolt = <768750>; + }; + + cci_opp_6: opp-875000000 { + opp-hz = /bits/ 64 <875000000>; + opp-microvolt = <781250>; + }; + + cci_opp_7: opp-927000000 { + opp-hz = /bits/ 64 <927000000>; + opp-microvolt = <800000>; + }; + + cci_opp_8: opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + opp-microvolt = <818750>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + opp-microvolt = <843750>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz = /bits/ 64 <1120000000>; + opp-microvolt = <862500>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz = /bits/ 64 <1155000000>; + opp-microvolt = <887500>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz = /bits/ 64 <1190000000>; + opp-microvolt = <906250>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz = /bits/ 64 <1260000000>; + opp-microvolt = <950000>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz = /bits/ 64 <1330000000>; + opp-microvolt = <993750>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1031250>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -83,6 +176,7 @@ cpu0: cpu@0 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@100 { @@ -101,6 +195,7 @@ cpu1: cpu@100 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@200 { @@ -119,6 +214,7 @@ cpu2: cpu@200 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@300 { @@ -137,6 +233,7 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@400 { @@ -155,6 +252,7 @@ cpu4: cpu@400 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@500 { @@ -173,6 +271,7 @@ cpu5: cpu@500 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@600 { @@ -191,6 +290,7 @@ cpu6: cpu@600 { d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@700 { @@ -209,6 +309,7 @@ cpu7: cpu@700 { d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states { -- GitLab From 8f4ed8fc51569307d6aec959e1f1c1c790c7fcd7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 9 Jun 2023 15:29:03 +0800 Subject: [PATCH 889/926] arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230609072906.2784594-3-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 242 +++++++++++++++++++++++ 1 file changed, 242 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 93f3c45ba3723..e2becf2fe79f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -120,6 +120,208 @@ cci_opp_15: opp-1400000000 { }; }; + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <600000>; + required-opps = <&cci_opp_0>; + }; + + opp-774000000 { + opp-hz = /bits/ 64 <774000000>; + opp-microvolt = <675000>; + required-opps = <&cci_opp_1>; + }; + + opp-875000000 { + opp-hz = /bits/ 64 <875000000>; + opp-microvolt = <700000>; + required-opps = <&cci_opp_2>; + }; + + opp-975000000 { + opp-hz = /bits/ 64 <975000000>; + opp-microvolt = <725000>; + required-opps = <&cci_opp_3>; + }; + + opp-1075000000 { + opp-hz = /bits/ 64 <1075000000>; + opp-microvolt = <750000>; + required-opps = <&cci_opp_4>; + }; + + opp-1175000000 { + opp-hz = /bits/ 64 <1175000000>; + opp-microvolt = <775000>; + required-opps = <&cci_opp_5>; + }; + + opp-1275000000 { + opp-hz = /bits/ 64 <1275000000>; + opp-microvolt = <800000>; + required-opps = <&cci_opp_6>; + }; + + opp-1375000000 { + opp-hz = /bits/ 64 <1375000000>; + opp-microvolt = <825000>; + required-opps = <&cci_opp_7>; + }; + + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <856250>; + required-opps = <&cci_opp_8>; + }; + + opp-1618000000 { + opp-hz = /bits/ 64 <1618000000>; + opp-microvolt = <875000>; + required-opps = <&cci_opp_9>; + }; + + opp-1666000000 { + opp-hz = /bits/ 64 <1666000000>; + opp-microvolt = <900000>; + required-opps = <&cci_opp_10>; + }; + + opp-1733000000 { + opp-hz = /bits/ 64 <1733000000>; + opp-microvolt = <925000>; + required-opps = <&cci_opp_11>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000>; + required-opps = <&cci_opp_12>; + }; + + opp-1866000000 { + opp-hz = /bits/ 64 <1866000000>; + opp-microvolt = <981250>; + required-opps = <&cci_opp_13>; + }; + + opp-1933000000 { + opp-hz = /bits/ 64 <1933000000>; + opp-microvolt = <1006250>; + required-opps = <&cci_opp_14>; + }; + + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <1031250>; + required-opps = <&cci_opp_15>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-774000000 { + opp-hz = /bits/ 64 <774000000>; + opp-microvolt = <675000>; + required-opps = <&cci_opp_0>; + }; + + opp-835000000 { + opp-hz = /bits/ 64 <835000000>; + opp-microvolt = <693750>; + required-opps = <&cci_opp_1>; + }; + + opp-919000000 { + opp-hz = /bits/ 64 <919000000>; + opp-microvolt = <718750>; + required-opps = <&cci_opp_2>; + }; + + opp-1002000000 { + opp-hz = /bits/ 64 <1002000000>; + opp-microvolt = <743750>; + required-opps = <&cci_opp_3>; + }; + + opp-1085000000 { + opp-hz = /bits/ 64 <1085000000>; + opp-microvolt = <775000>; + required-opps = <&cci_opp_4>; + }; + + opp-1169000000 { + opp-hz = /bits/ 64 <1169000000>; + opp-microvolt = <800000>; + required-opps = <&cci_opp_5>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <843750>; + required-opps = <&cci_opp_6>; + }; + + opp-1419000000 { + opp-hz = /bits/ 64 <1419000000>; + opp-microvolt = <875000>; + required-opps = <&cci_opp_7>; + }; + + opp-1530000000 { + opp-hz = /bits/ 64 <1530000000>; + opp-microvolt = <912500>; + required-opps = <&cci_opp_8>; + }; + + opp-1670000000 { + opp-hz = /bits/ 64 <1670000000>; + opp-microvolt = <956250>; + required-opps = <&cci_opp_9>; + }; + + opp-1733000000 { + opp-hz = /bits/ 64 <1733000000>; + opp-microvolt = <981250>; + required-opps = <&cci_opp_10>; + }; + + opp-1796000000 { + opp-hz = /bits/ 64 <1796000000>; + opp-microvolt = <1012500>; + required-opps = <&cci_opp_11>; + }; + + opp-1860000000 { + opp-hz = /bits/ 64 <1860000000>; + opp-microvolt = <1037500>; + required-opps = <&cci_opp_12>; + }; + + opp-1923000000 { + opp-hz = /bits/ 64 <1923000000>; + opp-microvolt = <1062500>; + required-opps = <&cci_opp_13>; + }; + + cluster1_opp_14: opp-1986000000 { + opp-hz = /bits/ 64 <1986000000>; + opp-microvolt = <1093750>; + required-opps = <&cci_opp_14>; + }; + + cluster1_opp_15: opp-2050000000 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1118750>; + required-opps = <&cci_opp_15>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -166,6 +368,11 @@ cpu0: cpu@0 { reg = <0x000>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -185,6 +392,11 @@ cpu1: cpu@100 { reg = <0x100>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -204,6 +416,11 @@ cpu2: cpu@200 { reg = <0x200>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -223,6 +440,11 @@ cpu3: cpu@300 { reg = <0x300>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -242,6 +464,11 @@ cpu4: cpu@400 { reg = <0x400>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -261,6 +488,11 @@ cpu5: cpu@500 { reg = <0x500>; enable-method = "psci"; clock-frequency = <2000000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; capacity-dmips-mhz = <382>; cpu-idle-states = <&cpu_ret_l &cpu_off_l>; i-cache-size = <32768>; @@ -280,6 +512,11 @@ cpu6: cpu@600 { reg = <0x600>; enable-method = "psci"; clock-frequency = <2050000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <335>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_ret_b &cpu_off_b>; i-cache-size = <65536>; @@ -299,6 +536,11 @@ cpu7: cpu@700 { reg = <0x700>; enable-method = "psci"; clock-frequency = <2050000000>; + clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <335>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_ret_b &cpu_off_b>; i-cache-size = <65536>; -- GitLab From 263d2fd02afc57909959616c234d8ff09f52d6ae Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 9 Jun 2023 15:29:04 +0800 Subject: [PATCH 890/926] arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230609072906.2784594-4-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index e2becf2fe79f9..3762a70ccafb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1519,6 +1519,11 @@ efuse: efuse@11cb0000 { reg = <0 0x11cb0000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + gpu_speedbin: gpu-speed-bin@59c { + reg = <0x59c 0x4>; + bits = <0 3>; + }; }; mipi_tx0: dsi-phy@11cc0000 { @@ -1551,6 +1556,8 @@ gpu: gpu@13040000 { <&spm MT8186_POWER_DOMAIN_MFG3>; power-domain-names = "core0", "core1"; #cooling-cells = <2>; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; status = "disabled"; }; -- GitLab From f38ea593ad0d487c0fe79867f98840593c47e2d6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 9 Jun 2023 15:29:05 +0800 Subject: [PATCH 891/926] arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU. Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230609072906.2784594-5-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 140 ++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 3762a70ccafb8..f04ae70c470aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -647,6 +647,142 @@ clk32k: oscillator-32k { clock-output-names = "clk32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-299000000 { + opp-hz = /bits/ 64 <299000000>; + opp-microvolt = <612500>; + opp-supported-hw = <0xff>; + }; + + opp-332000000 { + opp-hz = /bits/ 64 <332000000>; + opp-microvolt = <625000>; + opp-supported-hw = <0xff>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-microvolt = <637500>; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <643750>; + opp-supported-hw = <0xff>; + }; + + opp-434000000 { + opp-hz = /bits/ 64 <434000000>; + opp-microvolt = <656250>; + opp-supported-hw = <0xff>; + }; + + opp-484000000 { + opp-hz = /bits/ 64 <484000000>; + opp-microvolt = <668750>; + opp-supported-hw = <0xff>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + opp-microvolt = <687500>; + opp-supported-hw = <0xff>; + }; + + opp-586000000 { + opp-hz = /bits/ 64 <586000000>; + opp-microvolt = <700000>; + opp-supported-hw = <0xff>; + }; + + opp-637000000 { + opp-hz = /bits/ 64 <637000000>; + opp-microvolt = <712500>; + opp-supported-hw = <0xff>; + }; + + opp-690000000 { + opp-hz = /bits/ 64 <690000000>; + opp-microvolt = <737500>; + opp-supported-hw = <0xff>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <756250>; + opp-supported-hw = <0xff>; + }; + + opp-796000000 { + opp-hz = /bits/ 64 <796000000>; + opp-microvolt = <781250>; + opp-supported-hw = <0xff>; + }; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + opp-supported-hw = <0xff>; + }; + + opp-900000000-3 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8>; + }; + + opp-900000000-4 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <837500>; + opp-supported-hw = <0x10>; + }; + + opp-900000000-5 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <825000>; + opp-supported-hw = <0x30>; + }; + + opp-950000000-3 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <900000>; + opp-supported-hw = <0x8>; + }; + + opp-950000000-4 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <875000>; + opp-supported-hw = <0x10>; + }; + + opp-950000000-5 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x30>; + }; + + opp-1000000000-3 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0x8>; + }; + + opp-1000000000-4 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <912500>; + opp-supported-hw = <0x10>; + }; + + opp-1000000000-5 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <875000>; + opp-supported-hw = <0x30>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -765,7 +901,7 @@ mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8186_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 { reg = ; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; @@ -1558,6 +1694,8 @@ gpu: gpu@13040000 { #cooling-cells = <2>; nvmem-cells = <&gpu_speedbin>; nvmem-cell-names = "speed-bin"; + operating-points-v2 = <&gpu_opp_table>; + dynamic-power-coefficient = <4687>; status = "disabled"; }; -- GitLab From 3bfbff9b461e3506dfb5b2904e8c15a0aea39e07 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 6 Jun 2023 16:43:20 +0100 Subject: [PATCH 892/926] arm64: dts: mt7986: increase bl2 partition on NAND of Bananapi R3 The bootrom burned into the MT7986 SoC will try multiple locations on the SPI-NAND flash to load bl2 in case the bl2 image located at the the previously attempted offset is corrupt. Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND, allowing for up to four redundant copies of bl2 (typically sized a bit less than 0x40000). Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3") Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 15ee8c568f3c3..543c13385d6e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -29,13 +29,13 @@ partitions { partition@0 { label = "bl2"; - reg = <0x0 0x80000>; + reg = <0x0 0x100000>; read-only; }; - partition@80000 { + partition@100000 { label = "reserved"; - reg = <0x80000 0x300000>; + reg = <0x100000 0x280000>; }; partition@380000 { -- GitLab From 3443c1c4ed61c3b9d0d211f81ebfa0b559836646 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 4 May 2023 16:01:43 +0200 Subject: [PATCH 893/926] arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. A development Kit, called phyBOARD-Lyra [2] is used as a carrier board reference design around the AM62x SoM. Supported features: * Debug UART * SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * GPIO Expander * LEDs * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am62x [2] Product page CB: https://www.phytec.com/product/phyboard-am62x Signed-off-by: Wadim Egorov Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230504140143.1425951-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am62-phycore-som.dtsi | 324 ++++++++++++++++++ .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 266 ++++++++++++++ 3 files changed, 591 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 47b0d257b5087..acd8f97d57b6a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -10,6 +10,7 @@ # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi new file mode 100644 index 0000000000000..056ffe6f6f6af --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62x + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-AM62x"; + compatible = "phytec,am62-phycore-som", "ti,am625"; + + aliases { + ethernet0 = &cpsw_port1; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + rtc1 = &wkup_rtc0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v0_som>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = ; + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; +}; + +&main_pmx0 { + leds_pins_default: leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_5v0_som>; + buck2-supply = <&vcc_5v0_som>; + buck3-supply = <&vcc_5v0_som>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&vdd_1v8>; + ldo3-supply = <&vcc_5v0_som>; + ldo4-supply = <&vcc_5v0_som>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + ti,power-button; + system-power-controller; + + regulators { + vdd_core: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_3v3: buck2 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr4: buck3 { + regulator-name = "VDD_DDR4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vddshv5_sdio: ldo1 { + regulator-name = "VDDSHV5_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + vddr_core: ldo2 { + regulator-name = "VDDR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdda_1v8: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_2v5: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts new file mode 100644 index 0000000000000..3a10b21fec1bb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am62x + */ + +#include +#include +#include +#include +#include "k3-am625.dtsi" +#include "k3-am62-phycore-som.dtsi" + +/ { + compatible = "phytec,am625-phyboard-lyra-rdk", + "phytec,am62-phycore-som", "ti,am625"; + model = "PHYTEC phyBOARD-Lyra AM625"; + + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + ethernet1 = &cpsw_port2; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = ; + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = ; + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; + + led-1 { + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + vcc_3v3_mmc: regulator-vcc-3v3-mmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + gpio_keys_pins_default: gpio-keys-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; + + gpio_exp_int_pins_default: gpio-exp-int-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + user_leds_pins_default: user-leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + gpio_exp: gpio-expander@21 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_exp_int_pins_default>; + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN", + "GPIO2_LED2", "GPIO3_LVDS_GPIO", + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 may be used by TIFS firmware */ + status = "okay"; +}; + +&sdhci1 { + vmmc-supply = <&vcc_3v3_mmc>; + vqmmc-supply = <&vddshv5_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; -- GitLab From cf04083c59fbd5e0172dfcdc1f3735dcce42fc28 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:54 +0200 Subject: [PATCH 894/926] dt-bindings: arm: ti: add toradex,verdin-am62 et al. Add toradex,verdin-am62 for Toradex Verdin AM62 SoM, its nonwifi and wifi variants and the carrier boards (Dahlia, Verdin Development Board and Yavia) they may be mated in. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Signed-off-by: Francesco Dolcini Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230615095058.33890-2-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- .../devicetree/bindings/arm/ti/k3.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 254b5ec51f340..577eee95c8932 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -39,6 +39,26 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia + - toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board + - toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia + - const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + - description: K3 AM642 SoC items: - enum: -- GitLab From 316b80246b16bd1063e41e74ec7bae85e0813dd2 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:56 +0200 Subject: [PATCH 895/926] arm64: dts: ti: add verdin am62 This patch adds the device tree to support Toradex Verdin AM62 a computer on module which can be used on different carrier boards and the Toradex Verdin Development Board carrier board. The module consists of an TI AM62 family SoC (either AM623 or AM625), a TPS65219 PMIC, a Gigabit Ethernet PHY, 512MB to 2GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, and optional Parallel RGB to MIPI DSI bridge plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. So far there is no display nor USB role switch supported, apart of that all the other functionalities are fine. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-4-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + .../arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 190 +++ .../boot/dts/ti/k3-am62-verdin-nonwifi.dtsi | 20 + .../boot/dts/ti/k3-am62-verdin-wifi.dtsi | 39 + arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 1401 +++++++++++++++++ .../dts/ti/k3-am625-verdin-nonwifi-dev.dts | 22 + .../boot/dts/ti/k3-am625-verdin-wifi-dev.dts | 22 + 7 files changed, 1696 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index acd8f97d57b6a..2b8ec35462737 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi new file mode 100644 index 0000000000000..846caee7dfa41 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + cpsw3g_phy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&main_gpio0>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&cpsw3g_phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* IO Expander */ + gpio_expander_21: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver. */ +&main_uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi new file mode 100644 index 0000000000000..68d07695e1db5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +&sdhci2 { + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + status = "disabled"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi new file mode 100644 index 0000000000000..90ddc71bcd306 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +/ { + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_en>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + ti,fails-without-test-cd; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi new file mode 100644 index 0000000000000..432968bd7ec33 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -0,0 +1,1401 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart5; + usb0 = &usb0; + usb1 = &usb1; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + /* Non PMIC On-module Supplies */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3"; + vin-supply = <®_vsodimm>; + }; + + reg_1v2_dsi: regulator-1v2-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V1.2_DSI */ + reg_1v8_dsi: regulator-1v8-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v0_eth: regulator-1v0-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "On-module +V1.0_ETH"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v8_eth: regulator-1v8-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_ETH"; + vin-supply = <®_1v8>; + }; + + /* Verdin SD_1 Power Supply */ + reg_sdhc1_vmmc: regulator-sdhci1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vsel_sd>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_1 */ + pinctrl_epwm0_a: main-epwm0a-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm0_b: main-epwm0b-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_3_DSI */ + pinctrl_epwm1_a: main-epwm1a-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* WiFi_W_WKUP_HOST# */ + pinctrl_wifi_w_wkup_host: main-gpio0-15-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ + >; + }; + + /* WiFi_BT_WKUP_HOST# */ + pinctrl_bt_wkup_host: main-gpio0-16-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ + >; + }; + + /* PMIC_ETH_RESET# */ + pinctrl_eth_reset: main-gpio0-17-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ + >; + }; + + /* PMIC_BRIDGE_RESET# */ + pinctrl_bridge_reset: main-gpio0-20-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ + >; + }; + + /* PMIC_VSEL_SD */ + pinctrl_vsel_sd: main-gpio0-21-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + /* PMIC_EN_WIFI */ + pinctrl_wifi_en: main-gpio0-22-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ + >; + }; + + /* PMIC_ETH_INT# */ + pinctrl_eth_int: main-gpio0-25-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ + >; + }; + + /* WiFi_WKUP_BT# */ + pinctrl_wifi_wkup_bt: main-gpio0-26-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ + >; + }; + + /* WiFi_WKUP_WLAN# */ + pinctrl_wifi_wkup_wlan: main-gpio0-27-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-29-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ + >; + }; + + /* Verdin DSI_1_BKL_EN */ + pinctrl_dsi1_bkl_en: main-gpio0-30-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ + >; + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: main-gpio0-31-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-32-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-36-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-38-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-40-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-41-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-42-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-71-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-72-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-17-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO */ + pinctrl_qspi1_dqs_gpio: main-gpio1-18-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio1-19-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ + >; + }; + + /* Verdin DSI_1_INT# (pulled-up as active-low) */ + pinctrl_dsi1_int: main-gpio1-49-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_i2c0: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c1: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ + AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: main-i2c3-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* I2S_1_MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: main-mcasp0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: main-mcasp1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_mcan0: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ + AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ + >; + }; + + /* On-module eMMC */ + pinctrl_sdhci0: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ + AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_spi1: main-spi1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* ETH_25MHz_CLK */ + pinctrl_eth_clock: main-system-clkout0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + /* PMIC_EXTINT# */ + pinctrl_pmic_extint: main-system-extint-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + >; + }; + + /* Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_uart5: main-uart5-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ + AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ + AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */ + AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */ + >; + }; + + /* Verdin USB_1 */ + pinctrl_usb0: main-usb0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ + >; + }; + + /* Verdin USB_2 */ + pinctrl_usb1: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* DSS VOUT0 RGB */ + pinctrl_parallel_rgb: main-vout-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: mcu-gpio0-0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ + >; + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin UART_4 - Reserved to Cortex-M4 */ + pinctrl_mcu_uart0: mcu-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: wkup-clkout0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&cpsw3g_phy0>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>; + status = "disabled"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>; + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <1000>; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm1_a>; + status = "disabled"; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", /* 0 */ + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "", + "", + "SODIMM_174", + "SODIMM_172", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_76", + "SODIMM_21", /* 30 */ + "SODIMM_256", + "SODIMM_252", + "", + "SODIMM_46", + "SODIMM_42", + "SODIMM_218", + "", + "SODIMM_189", + "", + "SODIMM_216", /* 40 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "SODIMM_157", + "SODIMM_187", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + ""; + + verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <31 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "SODIMM_15", + "SODIMM_16", + "SODIMM_19", + "SODIMM_66", + "SODIMM_161", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_17", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + ""; +}; + +/* On-module I2C - PMIC_I2C */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + dsi_bridge: dsi@e { + compatible = "toshiba,tc358778"; + reg = <0xe>; + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bridge_reset>; + clocks = <&k3_clks 157 20>; + clock-names = "refclk"; + reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + vddc-supply = <®_1v2_dsi>; + vddmipi-supply = <®_1v2_dsi>; + vddio-supply = <®_1v8_dsi>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + rgb_in: endpoint { + data-lines = <18>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_vdd_core: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_CORE (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + reg_vdd_ddr: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + reg_vddr_core: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDDR_CORE (PMIC LDO2)"; + }; + + reg_1v8a: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + reg_eth_2v5: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + status = "disabled"; +}; + +/* Verdin CAN_2 - Reserved to Cortex-M4 */ + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "SODIMM_244", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin UART_4 - Cortex-M4 UART */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + disable-wp; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +/* TODO: role swich using ID pin */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + status = "disabled"; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts new file mode 100644 index 0000000000000..31d2a3066d43b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 on Verdin Development Board"; + compatible = "toradex,verdin-am62-nonwifi-dev", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts new file mode 100644 index 0000000000000..4b657d6d3e0dc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Verdin Development Board"; + compatible = "toradex,verdin-am62-wifi-dev", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- GitLab From 50e3424fbb77c853d14143949cdc1c6a8152c479 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:57 +0200 Subject: [PATCH 896/926] arm64: dts: ti: add verdin am62 dahlia Add Toradex Verdin AM62 Dahlia. Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-5-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 161 ++++++++++++++++++ .../dts/ti/k3-am625-verdin-nonwifi-dahlia.dts | 22 +++ .../dts/ti/k3-am625-verdin-wifi-dahlia.dts | 22 +++ 4 files changed, 207 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 2b8ec35462737..c6ba52bbca1ce 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,7 +12,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi new file mode 100644 index 0000000000000..3abd8d1d6761e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts new file mode 100644 index 0000000000000..d38bfef29d71e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Dahlia Board"; + compatible = "toradex,verdin-am62-nonwifi-dahlia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts new file mode 100644 index 0000000000000..3850a706edb77 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Dahlia Board"; + compatible = "toradex,verdin-am62-wifi-dahlia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- GitLab From 7f066473e49ace276274336cd95f3c828ae4d2f8 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:58 +0200 Subject: [PATCH 897/926] arm64: dts: ti: add verdin am62 yavia Add Toradex Verdin AM62 Yavia. Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-6-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am62-verdin-yavia.dtsi | 207 ++++++++++++++++++ .../dts/ti/k3-am625-verdin-nonwifi-yavia.dts | 22 ++ .../dts/ti/k3-am625-verdin-wifi-yavia.dts | 22 ++ 4 files changed, 253 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c6ba52bbca1ce..6dd7b6f1d6ab5 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -14,8 +14,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi new file mode 100644 index 0000000000000..cb11d6e7f5256 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>, + <&pinctrl_qspi1_cs2_gpio>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts new file mode 100644 index 0000000000000..e80332e1f030b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Yavia Board"; + compatible = "toradex,verdin-am62-nonwifi-yavia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts new file mode 100644 index 0000000000000..8a2506068ac46 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Yavia Board"; + compatible = "toradex,verdin-am62-wifi-yavia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- GitLab From a49568115143435390f20965902809471b6f830c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 15 Jun 2023 19:34:06 +0530 Subject: [PATCH 898/926] arm64: dts: ti: Unify pin group node names for make dtbs checks Prepare for pinctrl-single yaml binding and unify pin group node names. Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users. Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched. And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on. Signed-off-by: Tony Lindgren [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 6 +- .../boot/dts/ti/k3-am62-phycore-som.dtsi | 14 +- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 138 +++++++++--------- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 52 +++---- .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 20 +-- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 8 +- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 22 +-- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 26 ++-- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 12 +- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 ++-- .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 26 ++-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 28 ++-- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 48 +++--- .../ti/k3-am6528-iot2050-basic-common.dtsi | 2 +- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 36 ++--- .../ti/k3-am6548-iot2050-advanced-common.dtsi | 2 +- .../dts/ti/k3-am6548-iot2050-advanced-m2.dts | 6 +- .../boot/dts/ti/k3-am68-sk-base-board.dts | 34 ++--- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 26 ++-- .../dts/ti/k3-j7200-common-proc-board.dts | 24 +-- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 +- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 58 ++++---- .../dts/ti/k3-j721e-common-proc-board.dts | 62 ++++---- .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 52 +++---- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 +- .../dts/ti/k3-j721s2-common-proc-board.dts | 32 ++-- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 8 +- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 26 ++-- 31 files changed, 409 insertions(+), 409 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 4b94f7a863166..5e6feb8cd1255 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -73,19 +73,19 @@ vddshv_sdio: regulator-4 { }; &main_pmx0 { - vddshv_sdio_pins_default: vddshv-sdio-pins-default { + vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 056ffe6f6f6af..aa43e7407eee4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -98,27 +98,27 @@ led-0 { }; &main_pmx0 { - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ @@ -133,7 +133,7 @@ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -150,7 +150,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -166,7 +166,7 @@ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 432968bd7ec33..57dd061911abb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -176,259 +176,259 @@ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { &main_pmx0 { /* Verdin PWM_1 */ - pinctrl_epwm0_a: main-epwm0a-pins-default { + pinctrl_epwm0_a: main-epwm0a-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ >; }; /* Verdin PWM_2 */ - pinctrl_epwm0_b: main-epwm0b-pins-default { + pinctrl_epwm0_b: main-epwm0b-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ >; }; /* Verdin PWM_3_DSI */ - pinctrl_epwm1_a: main-epwm1a-pins-default { + pinctrl_epwm1_a: main-epwm1a-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ >; }; /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_clk_gpio: main-gpio0-0-pins-default { + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ >; }; /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io0_gpio: main-gpio0-3-pins-default { + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ >; }; /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io1_gpio: main-gpio0-4-pins-default { + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ >; }; /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io2_gpio: main-gpio0-5-pins-default { + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ >; }; /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io3_gpio: main-gpio0-6-pins-default { + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ >; }; /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs_gpio: main-gpio0-11-pins-default { + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ >; }; /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs2_gpio: main-gpio0-12-pins-default { + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ >; }; /* WiFi_W_WKUP_HOST# */ - pinctrl_wifi_w_wkup_host: main-gpio0-15-pins-default { + pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ >; }; /* WiFi_BT_WKUP_HOST# */ - pinctrl_bt_wkup_host: main-gpio0-16-pins-default { + pinctrl_bt_wkup_host: main-gpio0-16-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ >; }; /* PMIC_ETH_RESET# */ - pinctrl_eth_reset: main-gpio0-17-pins-default { + pinctrl_eth_reset: main-gpio0-17-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ >; }; /* PMIC_BRIDGE_RESET# */ - pinctrl_bridge_reset: main-gpio0-20-pins-default { + pinctrl_bridge_reset: main-gpio0-20-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ >; }; /* PMIC_VSEL_SD */ - pinctrl_vsel_sd: main-gpio0-21-pins-default { + pinctrl_vsel_sd: main-gpio0-21-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ >; }; /* PMIC_EN_WIFI */ - pinctrl_wifi_en: main-gpio0-22-pins-default { + pinctrl_wifi_en: main-gpio0-22-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ >; }; /* PMIC_ETH_INT# */ - pinctrl_eth_int: main-gpio0-25-pins-default { + pinctrl_eth_int: main-gpio0-25-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ >; }; /* WiFi_WKUP_BT# */ - pinctrl_wifi_wkup_bt: main-gpio0-26-pins-default { + pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ >; }; /* WiFi_WKUP_WLAN# */ - pinctrl_wifi_wkup_wlan: main-gpio0-27-pins-default { + pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ >; }; /* Verdin SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-29-pins-default { + pinctrl_sd1_pwr_en: main-gpio0-29-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ >; }; /* Verdin DSI_1_BKL_EN */ - pinctrl_dsi1_bkl_en: main-gpio0-30-pins-default { + pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ >; }; /* Verdin CTRL_SLEEP_MOCI# */ - pinctrl_ctrl_sleep_moci: main-gpio0-31-pins-default { + pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ >; }; /* Verdin CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: main-gpio0-32-pins-default { + pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ >; }; /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_out_gpio: main-gpio0-34-pins-default { + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ >; }; /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_bclk_gpio: main-gpio0-35-pins-default { + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ >; }; /* Verdin GPIO_6 */ - pinctrl_gpio_6: main-gpio0-36-pins-default { + pinctrl_gpio_6: main-gpio0-36-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ >; }; /* Verdin ETH_2_RGMII_INT# */ - pinctrl_eth2_rgmii_int: main-gpio0-38-pins-default { + pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ >; }; /* Verdin GPIO_5 */ - pinctrl_gpio_5: main-gpio0-40-pins-default { + pinctrl_gpio_5: main-gpio0-40-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ >; }; /* Verdin GPIO_7 */ - pinctrl_gpio_7: main-gpio0-41-pins-default { + pinctrl_gpio_7: main-gpio0-41-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ >; }; /* Verdin GPIO_8 */ - pinctrl_gpio_8: main-gpio0-42-pins-default { + pinctrl_gpio_8: main-gpio0-42-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ >; }; /* Verdin USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-71-pins-default { + pinctrl_usb1_oc: main-gpio0-71-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ >; }; /* Verdin USB_2_OC# */ - pinctrl_usb2_oc: main-gpio0-72-pins-default { + pinctrl_usb2_oc: main-gpio0-72-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ >; }; /* Verdin PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio1-17-pins-default { + pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ >; }; /* Verdin QSPI_1_DQS as GPIO */ - pinctrl_qspi1_dqs_gpio: main-gpio1-18-pins-default { + pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ >; }; /* Verdin USB_1_ID */ - pinctrl_usb0_id: main-gpio1-19-pins-default { + pinctrl_usb0_id: main-gpio1-19-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ >; }; /* Verdin DSI_1_INT# (pulled-up as active-low) */ - pinctrl_dsi1_int: main-gpio1-49-pins-default { + pinctrl_dsi1_int: main-gpio1-49-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ >; }; /* On-module I2C - PMIC_I2C */ - pinctrl_i2c0: main-i2c0-pins-default { + pinctrl_i2c0: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ @@ -436,7 +436,7 @@ AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ }; /* Verdin I2C_1 */ - pinctrl_i2c1: main-i2c1-pins-default { + pinctrl_i2c1: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ @@ -444,7 +444,7 @@ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ }; /* Verdin I2C_2_DSI */ - pinctrl_i2c2: main-i2c2-pins-default { + pinctrl_i2c2: main-i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ @@ -452,7 +452,7 @@ AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 * }; /* Verdin I2C_4_CSI */ - pinctrl_i2c3: main-i2c3-pins-default { + pinctrl_i2c3: main-i2c3-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ @@ -460,14 +460,14 @@ AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 * }; /* I2S_1_MCLK */ - pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-pins-default { + pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ >; }; /* Verdin I2S_1 */ - pinctrl_mcasp0: main-mcasp0-pins-default { + pinctrl_mcasp0: main-mcasp0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ @@ -477,7 +477,7 @@ AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ }; /* Verdin I2S_2 */ - pinctrl_mcasp1: main-mcasp1-pins-default { + pinctrl_mcasp1: main-mcasp1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ @@ -487,7 +487,7 @@ AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SO }; /* Verdin CAN_1 */ - pinctrl_mcan0: main-mcan0-pins-default { + pinctrl_mcan0: main-mcan0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ @@ -495,7 +495,7 @@ AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ }; /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ - pinctrl_mdio: main-mdio1-pins-default { + pinctrl_mdio: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ @@ -503,7 +503,7 @@ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM }; /* On-module eMMC */ - pinctrl_sdhci0: main-mmc0-pins-default { + pinctrl_sdhci0: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -519,7 +519,7 @@ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ }; /* Verdin SD_1 */ - pinctrl_sdhci1: main-mmc1-pins-default { + pinctrl_sdhci1: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ @@ -532,7 +532,7 @@ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ }; /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ - pinctrl_sdhci2: main-mmc2-pins-default { + pinctrl_sdhci2: main-mmc2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ @@ -545,7 +545,7 @@ AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ }; /* Verdin QSPI_1 */ - pinctrl_ospi0: main-ospi0-pins-default { + pinctrl_ospi0: main-ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ @@ -558,7 +558,7 @@ AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ }; /* Verdin ETH_1 RGMII (On-module PHY) */ - pinctrl_rgmii1: main-rgmii1-pins-default { + pinctrl_rgmii1: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -576,7 +576,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ }; /* Verdin ETH_2 RGMII */ - pinctrl_rgmii2: main-rgmii2-pins-default { + pinctrl_rgmii2: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ @@ -594,7 +594,7 @@ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ }; /* Verdin SPI_1 */ - pinctrl_spi1: main-spi1-pins-default { + pinctrl_spi1: main-spi1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ @@ -604,21 +604,21 @@ AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ }; /* ETH_25MHz_CLK */ - pinctrl_eth_clock: main-system-clkout0-pins-default { + pinctrl_eth_clock: main-system-clkout0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; }; /* PMIC_EXTINT# */ - pinctrl_pmic_extint: main-system-extint-pins-default { + pinctrl_pmic_extint: main-system-extint-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ >; }; /* Verdin UART_3, used as the Linux console */ - pinctrl_uart0: main-uart0-pins-default { + pinctrl_uart0: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ @@ -626,7 +626,7 @@ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ }; /* Verdin UART_1 */ - pinctrl_uart1: main-uart1-pins-default { + pinctrl_uart1: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ @@ -636,7 +636,7 @@ AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* S }; /* Bluetooth on WB SKUs, module-specific UART otherwise */ - pinctrl_uart5: main-uart5-pins-default { + pinctrl_uart5: main-uart5-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ @@ -646,21 +646,21 @@ AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* }; /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-pins-default { + pinctrl_usb0: main-usb0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ >; }; /* Verdin USB_2 */ - pinctrl_usb1: main-usb1-pins-default { + pinctrl_usb1: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ >; }; /* DSS VOUT0 RGB */ - pinctrl_parallel_rgb: main-vout-pins-default { + pinctrl_parallel_rgb: main-vout-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ @@ -690,42 +690,42 @@ AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ &mcu_pmx0 { /* Verdin PCIE_1_RESET# */ - pinctrl_pcie_1_reset: mcu-gpio0-0-pins-default { + pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ >; }; /* Verdin GPIO_1 */ - pinctrl_gpio_1: mcu-gpio0-1-pins-default { + pinctrl_gpio_1: mcu-gpio0-1-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ >; }; /* Verdin GPIO_2 */ - pinctrl_gpio_2: mcu-gpio0-2-pins-default { + pinctrl_gpio_2: mcu-gpio0-2-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ >; }; /* Verdin GPIO_3 */ - pinctrl_gpio_3: mcu-gpio0-3-pins-default { + pinctrl_gpio_3: mcu-gpio0-3-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ >; }; /* Verdin GPIO_4 */ - pinctrl_gpio_4: mcu-gpio0-4-pins-default { + pinctrl_gpio_4: mcu-gpio0-4-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ >; }; /* Verdin I2C_3_HDMI */ - pinctrl_mcu_i2c0: mcu-i2c0-pins-default { + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ @@ -733,7 +733,7 @@ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ }; /* Verdin UART_4 - Reserved to Cortex-M4 */ - pinctrl_mcu_uart0: mcu-uart0-pins-default { + pinctrl_mcu_uart0: mcu-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ @@ -741,14 +741,14 @@ AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM }; /* Verdin CSI_1_MCLK */ - pinctrl_csi1_mclk: wkup-clkout0-pins-default { + pinctrl_csi1_mclk: wkup-clkout0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ >; }; /* Verdin UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-pins-default { + pinctrl_wkup_uart0: wkup-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index cb46c38ce2cc1..589bf998bc528 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -216,7 +216,7 @@ cpsw3g_phy1: ethernet-phy@1 { }; &main_pmx0 { - gpio0_pins_default: gpio0-pins-default { + gpio0_pins_default: gpio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ @@ -235,47 +235,47 @@ AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ >; }; - vdd_sd_dv_pins_default: vdd-sd-pins-default { + vdd_sd_dv_pins_default: vdd-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; - usr_button_pins_default: usr-button-pins-default { + usr_button_pins_default: usr-button-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ >; }; - grove_pins_default: grove-pins-default { + grove_pins_default: grove-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - local_i2c_pins_default: local-i2c-pins-default { + local_i2c_pins_default: local-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - i2c2_1v8_pins_default: i2c2-pins-default { + i2c2_1v8_pins_default: i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -292,7 +292,7 @@ AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ >; }; - emmc_pins_default: emmc-pins-default { + emmc_pins_default: emmc-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -307,13 +307,13 @@ AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ >; }; - vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ >; }; - sd_pins_default: sd-pins-default { + sd_pins_default: sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -325,7 +325,7 @@ AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ >; }; - wifi_pins_default: wifi-pins-default { + wifi_pins_default: wifi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ @@ -338,19 +338,19 @@ AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ >; }; - wifi_en_pins_default: wifi-en-pins-default { + wifi_en_pins_default: wifi-en-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ >; }; - wifi_wlirq_pins_default: wifi-wlirq-pins-default { + wifi_wlirq_pins_default: wifi-wlirq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ >; }; - spe_pins_default: spe-pins-default { + spe_pins_default: spe-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ @@ -366,21 +366,21 @@ AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; }; - mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { + mikrobus_i2c_pins_default: mikrobus-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ >; }; - mikrobus_uart_pins_default: mikrobus-uart-pins-default { + mikrobus_uart_pins_default: mikrobus-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ >; }; - mikrobus_spi_pins_default: mikrobus-spi-pins-default { + mikrobus_spi_pins_default: mikrobus-spi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ @@ -389,7 +389,7 @@ AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ >; }; - mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { + mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ @@ -397,27 +397,27 @@ AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ >; }; - console_pins_default: console-pins-default { + console_pins_default: console-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; }; - wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { + wifi_debug_uart_pins_default: wifi-debug-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ >; @@ -425,7 +425,7 @@ AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ }; &mcu_pmx0 { - i2c_qwiic_pins_default: i2c-qwiic-pins-default { + i2c_qwiic_pins_default: i2c-qwiic-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ @@ -438,14 +438,14 @@ AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ >; }; - i2c_csi_pins_default: i2c-csi-pins-default { + i2c_csi_pins_default: i2c-csi-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ >; }; - wifi_32k_clk: mcu-clk-out-pins-default { + wifi_32k_clk: mcu-clk-out-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index 3a10b21fec1bb..a438baf542c22 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -81,33 +81,33 @@ vcc_3v3_mmc: regulator-vcc-3v3-mmc { }; &main_pmx0 { - gpio_keys_pins_default: gpio-keys-pins-default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; - gpio_exp_int_pins_default: gpio-exp-int-pins-default { + gpio_exp_int_pins_default: gpio-exp-int-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ @@ -119,7 +119,7 @@ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ >; }; - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -136,14 +136,14 @@ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ @@ -152,13 +152,13 @@ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - user_leds_pins_default: user-leds-pins-default { + user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index c0a69093c324e..3f9ef4053aa61 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -101,7 +101,7 @@ vcc_1v8: regulator-5 { }; &main_pmx0 { - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -118,7 +118,7 @@ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -134,13 +134,13 @@ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 65caa5611d6d5..ecc0e13331c41 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -117,7 +117,7 @@ led-0 { }; &mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ @@ -135,14 +135,14 @@ &wkup_uart0 { }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ @@ -151,28 +151,28 @@ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -184,26 +184,26 @@ AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index d39cfc5335831..34c8ffc553ec3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -118,14 +118,14 @@ sound_master: simple-audio-card,codec { &main_pmx0 { /* First pad number is ALW package and second is AMC package */ - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ @@ -134,28 +134,28 @@ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ @@ -170,7 +170,7 @@ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ @@ -182,20 +182,20 @@ AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ @@ -212,13 +212,13 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; - main_mcasp1_pins_default: main-mcasp1-pins-default { + main_mcasp1_pins_default: main-mcasp1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ @@ -229,7 +229,7 @@ AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ }; &mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 7c2e26ef726c0..5606d775153d4 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -66,7 +66,7 @@ vcc_5v0_som: regulator-vcc-5v0-som { }; &main_pmx0 { - cpsw_mdio_pins_default: cpsw-mdio-pins-default { + cpsw_mdio_pins_default: cpsw-mdio-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ @@ -74,7 +74,7 @@ AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ >; }; - cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default { + cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ @@ -92,26 +92,26 @@ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ >; }; - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */ >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e897feacd1224..15c282c93467a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -226,7 +226,7 @@ transceiver2: can-phy1 { }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ @@ -240,7 +240,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -249,7 +249,7 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -258,7 +258,7 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ @@ -267,28 +267,28 @@ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ @@ -305,7 +305,7 @@ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -322,13 +322,13 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -344,27 +344,27 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; - ddr_vtt_pins_default: ddr-vtt-pins-default { + ddr_vtt_pins_default: ddr-vtt-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 59c091bc30ab0..9c418abd29d86 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -105,47 +105,47 @@ vcc_3v3_mmc: regulator-sd { }; &main_pmx0 { - can_tc1_pins_default: can-tc1-pins-default { + can_tc1_pins_default: can-tc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */ >; }; - can_tc2_pins_default: can-tc2-pins-default { + can_tc2_pins_default: can-tc2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */ >; }; - gpio_keys_pins_default: gpio-keys-pins-default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */ AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ @@ -158,14 +158,14 @@ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -174,25 +174,25 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - pcie_usb_sel_pins_default: pcie-usb-sel-pins-default { + pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ >; }; - pcie0_pins_default: pcie0-pins-default { + pcie0_pins_default: pcie0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ >; }; - user_leds_pins_default: user-leds-pins-default { + user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 78ae490a0c762..cbce43dbe3f9c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -232,7 +232,7 @@ led-7 { }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ @@ -246,7 +246,7 @@ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -255,7 +255,7 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -264,34 +264,34 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ @@ -308,7 +308,7 @@ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -325,7 +325,7 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -341,24 +341,24 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_wlan_en_pins_default: main-wlan-en-pins-default { + main_wlan_en_pins_default: main-wlan-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ >; }; - main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + main_com8_ls_en_pins_default: main-com8-ls-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ >; }; - main_wlan_pins_default: main-wlan-pins-default { + main_wlan_pins_default: main-wlan-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index bbbb5c169ccc0..e26bd988e5224 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -104,7 +104,7 @@ dp_refclk: clock { }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) @@ -113,7 +113,7 @@ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) @@ -122,21 +122,21 @@ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { pinctrl-single,pins = < /* (R2) WKUP_GPIO0_21 */ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) >; }; - arduino_uart_pins_default: arduino-uart-pins-default { + arduino_uart_pins_default: arduino-uart-default-pins { pinctrl-single,pins = < /* (P4) MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) @@ -145,7 +145,7 @@ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) >; }; - arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { + arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins { pinctrl-single,pins = < /* (P1) WKUP_GPIO0_31 */ AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) @@ -154,7 +154,7 @@ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) >; }; - arduino_io_oe_pins_default: arduino-io-oe-pins-default { + arduino_io_oe_pins_default: arduino-io-oe-default-pins { pinctrl-single,pins = < /* (N4) WKUP_GPIO0_34 */ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) @@ -169,7 +169,7 @@ AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7) >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) @@ -184,7 +184,7 @@ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) >; }; - db9_com_mode_pins_default: db9-com-mode-pins-default { + db9_com_mode_pins_default: db9-com-mode-default-pins { pinctrl-single,pins = < /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) @@ -197,7 +197,7 @@ AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7) >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < /* (T2) WKUP_GPIO0_17, used as user led1 red */ AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) @@ -210,7 +210,7 @@ AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7) >; }; - mcu_spi0_pins_default: mcu-spi0-pins-default { + mcu_spi0_pins_default: mcu-spi0-default-pins { pinctrl-single,pins = < /* (Y1) MCU_SPI0_CLK */ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) @@ -223,7 +223,7 @@ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) >; }; - minipcie_pins_default: minipcie-pins-default { + minipcie_pins_default: minipcie-default-pins { pinctrl-single,pins = < /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) @@ -232,7 +232,7 @@ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) }; &main_pmx0 { - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ @@ -241,14 +241,14 @@ AM65X_IOPAD(0x017c, PIN_OUTPUT, 6) /* (AC21) UART1_RTSn */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -261,19 +261,19 @@ AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */ >; }; - usb0_pins_default: usb0-pins-default { + usb0_pins_default: usb0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; - arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { + arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ @@ -284,7 +284,7 @@ AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ >; }; - dss_vout1_pins_default: dss-vout1-pins-default { + dss_vout1_pins_default: dss-vout1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ @@ -317,13 +317,13 @@ AM65X_IOPAD(0x006c, PIN_OUTPUT, 1) /* VOUT1_DE */ >; }; - dp_pins_default: dp-pins-default { + dp_pins_default: dp-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ @@ -332,21 +332,21 @@ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index cd43fd11a5c2c..5ab434c02ab6b 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -35,7 +35,7 @@ &sdhci0 { }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index c8c80cd756d9a..973a89b04a22f 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -147,7 +147,7 @@ vtt_supply: regulator-3 { }; &wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ @@ -156,27 +156,27 @@ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ >; }; - ddr_vtt_pins_default: ddr-vtt-pins-default { + ddr_vtt_pins_default: ddr-vtt-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ @@ -198,7 +198,7 @@ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ @@ -207,7 +207,7 @@ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ @@ -224,14 +224,14 @@ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ @@ -240,7 +240,7 @@ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ @@ -249,14 +249,14 @@ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ @@ -265,7 +265,7 @@ AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ @@ -282,7 +282,7 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -295,7 +295,7 @@ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; @@ -303,21 +303,21 @@ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index 0f67e1ec0fb86..be55494b1f3fc 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -22,7 +22,7 @@ memory@80000000 { }; &main_pmx0 { - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 9209b5a7baa4d..cbe44634914fd 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -27,7 +27,7 @@ &mcu_r5fss0 { }; &main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-pins-default { + main_m2_enable_pins_default: main-m2-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ >; @@ -39,7 +39,7 @@ AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ >; }; - main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default { + main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ @@ -56,7 +56,7 @@ AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */ }; &main_pmx1 { - main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default { + main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 979898bc5b023..d5889ba3fa467 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -124,21 +124,21 @@ transceiver4: can-phy3 { }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -150,40 +150,40 @@ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; - main_mcan6_pins_default: main-mcan6-pins-default { + main_mcan6_pins_default: main-mcan6-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ >; }; - main_mcan7_pins_default: main-mcan7-pins-default { + main_mcan7_pins_default: main-mcan7-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ >; }; - main_i2c4_pins_default: main-i2c4-pins-default { + main_i2c4_pins_default: main-i2c4-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ @@ -204,7 +204,7 @@ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -213,7 +213,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ @@ -230,42 +230,42 @@ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ >; }; - mcu_i2c1_pins_default: mcu-i2c1-pins-default { + mcu_i2c1_pins_default: mcu-i2c1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index e2c80fff74786..6c9139f73201a 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -29,7 +29,7 @@ secure_ddr: optee@9e800000 { }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 6e12a45a22875..d282c2c633c1c 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,21 +110,21 @@ vdd_sd_dv: regulator-tlv71033 { }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -137,13 +137,13 @@ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ @@ -164,7 +164,7 @@ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -173,28 +173,28 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ @@ -211,14 +211,14 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; - mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ @@ -234,7 +234,7 @@ J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ }; &wkup_pmx3 { - mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index b5159a30108c9..3cf288128c3f4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -90,7 +90,7 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; &wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ @@ -99,7 +99,7 @@ J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ @@ -108,7 +108,7 @@ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ }; &wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -125,13 +125,13 @@ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; - wkup_gpio_pins_default: wkup-gpio-pins-default { + wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ @@ -140,7 +140,7 @@ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ @@ -149,28 +149,28 @@ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ >; }; - main_uart3_pins_default: main-uart3-pins-default { + main_uart3_pins_default: main-uart3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ @@ -183,7 +183,7 @@ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; @@ -191,7 +191,7 @@ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ }; &main_pmx1 { - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 31b932eebc0a9..34a0747cbe691 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -92,7 +92,7 @@ qsgmii-line-hog { }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index e763d571b9162..b37f4f88ece4f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -83,7 +83,7 @@ rtos_ipc_memory_region: ipc-memories@a4000000 { }; &wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ @@ -101,7 +101,7 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ @@ -119,7 +119,7 @@ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ @@ -128,7 +128,7 @@ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 27347a07d3309..66aac145e7530 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -305,7 +305,7 @@ dp_connector_in: endpoint { }; &main_pmx0 { - led_pins_default: led-pins-default { + led_pins_default: led-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ @@ -315,7 +315,7 @@ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -328,64 +328,64 @@ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; - sd_pwr_en_pins_default: sd-pwr-en-pins-default { + sd_pwr_en_pins_default: sd-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ >; }; - dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { + dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ @@ -394,14 +394,14 @@ J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c4_pins_default: main-i2c4-pins-default { + main_i2c4_pins_default: main-i2c4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ @@ -410,14 +410,14 @@ J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ @@ -426,21 +426,21 @@ J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ >; }; - csi0_gpio_pins_default: csi0-gpio-pins-default { + csi0_gpio_pins_default: csi0-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ >; }; - csi1_gpio_pins_default: csi1-gpio-pins-default { + csi1_gpio_pins_default: csi1-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ >; }; - pcie1_rst_pins_default: pcie1-rst-pins-default { + pcie1_rst_pins_default: pcie1-rst-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ >; @@ -448,13 +448,13 @@ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ }; &wkup_pmx0 { - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ @@ -466,13 +466,13 @@ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ >; }; - mikro_bus_pins_default: mikro-bus-pins-default { + mikro_bus_pins_default: mikro-bus-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ @@ -495,7 +495,7 @@ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -512,34 +512,34 @@ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - sw_pwr_pins_default: sw-pwr-pins-default { + sw_pwr_pins_default: sw-pwr-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_usbss1_pins_default: mcu-usbss1-pins-default { + mcu_usbss1_pins_default: mcu-usbss1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 5fc002e5a18c1..c1cbbae761827 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -186,7 +186,7 @@ dp_connector_in: endpoint { }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ @@ -195,34 +195,34 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ >; }; - main_uart2_pins_default: main-uart2-pins-default { + main_uart2_pins_default: main-uart2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ >; }; - main_uart4_pins_default: main-uart4-pins-default { + main_uart4_pins_default: main-uart4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ >; }; - sw10_button_pins_default: sw10-button-pins-default { + sw10_button_pins_default: sw10-button-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -236,66 +236,66 @@ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { + main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ >; }; - mcasp10_pins_default: mcasp10-pins-default { + mcasp10_pins_default: mcasp10-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ @@ -309,27 +309,27 @@ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ >; }; - audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { + audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ >; }; - main_mcan2_pins_default: main-mcan2-pins-default { + main_mcan2_pins_default: main-mcan2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ >; }; - main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { + main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; @@ -337,14 +337,14 @@ J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ }; &wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -353,13 +353,13 @@ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - sw11_button_pins_default: sw11-button-pins-default { + sw11_button_pins_default: sw11-button-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ @@ -372,7 +372,7 @@ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -389,41 +389,41 @@ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; - wkup_gpio_pins_default: wkup-gpio-pins-default { + wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso index 6ff7b6ad33ed3..6f0adf591b982 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -94,7 +94,7 @@ qsgmii-line-hog { }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ce6eb93fca9e2..0ee4f38ec8f03 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -289,7 +289,7 @@ tfp410_out: endpoint { }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -302,7 +302,7 @@ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ @@ -311,60 +311,60 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - dp_pwr_en_pins_default: dp-pwr-en-pins-default { + dp_pwr_en_pins_default: dp-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ >; }; - dss_vout0_pins_default: dss-vout0-pins-default { + dss_vout0_pins_default: dss-vout0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ @@ -397,33 +397,33 @@ J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ >; }; - hdmi_hpd_pins_default: hdmi-hpd-pins-default { + hdmi_hpd_pins_default: hdmi-hpd-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ >; }; - hdmi_pdn_pins_default: hdmi-pdn-pins-default { + hdmi_pdn_pins_default: hdmi-pdn-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; }; /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-pins-default { + ekey_reset_pins_default: ekey-reset-pns-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ @@ -451,7 +451,7 @@ J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ >; }; - rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ >; @@ -459,7 +459,7 @@ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ }; &wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -476,14 +476,14 @@ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ @@ -499,26 +499,26 @@ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; }; - vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { + vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ @@ -527,7 +527,7 @@ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ @@ -535,7 +535,7 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ }; /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-pins-default { + mkey_reset_pins_default: mkey-reset-pns-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8431f5f57cd25..38ae13cc3aa3e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -145,14 +145,14 @@ rtos_ipc_memory_region: ipc-memories@aa000000 { }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ @@ -168,7 +168,7 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e7136ddb91781..04d4739d72457 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -112,7 +112,7 @@ transceiver2: can-phy2 { }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ @@ -121,14 +121,14 @@ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -141,13 +141,13 @@ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; @@ -155,7 +155,7 @@ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -164,7 +164,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -173,7 +173,7 @@ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ @@ -190,41 +190,41 @@ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ @@ -237,7 +237,7 @@ J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ @@ -250,7 +250,7 @@ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index c1a6c36cde1de..d57dd43da0ef4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -40,7 +40,7 @@ transceiver0: can-phy0 { }; &wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ @@ -62,7 +62,7 @@ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ @@ -71,14 +71,14 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ >; }; - main_mcan16_pins_default: main-mcan16-pins-default { + main_mcan16_pins_default: main-mcan16-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 09f052c948447..430b8a2c5df57 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,7 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -261,14 +261,14 @@ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -281,7 +281,7 @@ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; @@ -289,7 +289,7 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -298,14 +298,14 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -314,7 +314,7 @@ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ @@ -331,14 +331,14 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ @@ -351,7 +351,7 @@ J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ @@ -366,7 +366,7 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; &wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +384,7 @@ J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ -- GitLab From c2951581e69c8fef39120068d1ef5b1974d54ff1 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 15 Jun 2023 08:45:29 -0700 Subject: [PATCH 899/926] Revert "arm64: dts: adapt to LP855X bindings changes" commit 'ebdcfc8c42c2 ("arm64: dts: adapt to LP855X bindings changes")' is a Tegra change, but was accidentally merged in the Qualcomm tree. The change is reverted to avoid rebasing a large number of other changes. This reverts commit ebdcfc8c42c2b9d5ca1b27d8ee558eefb3e904d8. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index a6a58e51822d9..38f4ff229beff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -58,17 +58,19 @@ backlight: backlight@2c { dev-ctrl = /bits/ 8 <0x80>; init-brt = /bits/ 8 <0xff>; + pwm-period = <29334>; + pwms = <&pwm 0 29334>; pwm-names = "lp8557"; /* boost frequency 1 MHz */ - rom-13h { + rom_13h { rom-addr = /bits/ 8 <0x13>; rom-val = /bits/ 8 <0x01>; }; /* 3 LED string */ - rom-14h { + rom_14h { rom-addr = /bits/ 8 <0x14>; rom-val = /bits/ 8 <0x87>; }; -- GitLab From b29381e91e52e787d65d07216ad826efe7dafd43 Mon Sep 17 00:00:00 2001 From: Vadym Kochan Date: Thu, 15 Jun 2023 16:04:45 +1200 Subject: [PATCH 900/926] arm64: dts: marvell: cp11x: Fix nand_controller node name according to YAML Marvell NAND controller has now YAML to validate it's DT bindings, so change the node name of cp11x DTSI as it is required by nand-controller.yaml Signed-off-by: Vadym Kochan Signed-off-by: Chris Packham Reviewed-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 0cc9ee9871e70..4ec1aae0a3a9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -468,7 +468,7 @@ CP11X_LABEL(uart3): serial@702300 { status = "disabled"; }; - CP11X_LABEL(nand_controller): nand@720000 { + CP11X_LABEL(nand_controller): nand-controller@720000 { /* * Due to the limitation of the pins available * this controller is only usable on the CPM -- GitLab From dc393f1fdf22eda7255e99aadb400d8faaf3bdcf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 15 Jun 2023 16:04:46 +1200 Subject: [PATCH 901/926] ARM: dts: mvebu: align MTD partition nodes to dtschema Update the node names for the SPI NOR and NAND partitions to conform to the partition properties in the relevant dtschema. Signed-off-by: Chris Packham Reviewed-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-atl-x530.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/armada-385-atl-x530.dts index 241f5d7c80e9a..5a9ab8410b7b6 100644 --- a/arch/arm/boot/dts/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/armada-385-atl-x530.dts @@ -179,19 +179,19 @@ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@u-boot { + partition@0 { reg = <0x00000000 0x00100000>; label = "u-boot"; }; - partition@u-boot-env { + partition@100000 { reg = <0x00100000 0x00040000>; label = "u-boot-env"; }; - partition@unused { + partition@140000 { reg = <0x00140000 0x00e80000>; label = "unused"; }; - partition@idprom { + partition@fc0000 { reg = <0x00fc0000 0x00040000>; label = "idprom"; }; @@ -216,16 +216,16 @@ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - partition@user { + partition@0 { reg = <0x00000000 0x0f000000>; label = "user"; }; - partition@errlog { + partition@f000000 { /* Maximum mtdoops size is 8MB, so set to that. */ reg = <0x0f000000 0x00800000>; label = "errlog"; }; - partition@nand-bbt { + partition@f800000 { reg = <0x0f800000 0x00800000>; label = "nand-bbt"; }; -- GitLab From fe96d8b2a59f46d8d30977ffe5edf745e889c1ee Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 23 May 2023 17:50:21 +0200 Subject: [PATCH 902/926] arm64: dts: marvell: Fix pca954x i2c-mux node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "make dtbs_check": arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtb: i2c-switch@70: $nodename:0: 'i2c-switch@70' does not match '^(i2c-?)?mux' From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtb: i2c-switch@70: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c@0', 'i2c@1', 'i2c@2' were unexpected) From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml ... Fix this by renaming PCA954x nodes to "i2c-mux", to match the I2C bus multiplexer/switch DT bindings and the Generic Names Recommendation in the Devicetree Specification. Signed-off-by: Geert Uytterhoeven Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index ca1aeb69a8929..c864df9ec84d1 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -135,7 +135,7 @@ &cp0_i2c1 { pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index eb04735039362..42a60f3dd5d14 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -285,7 +285,7 @@ &cp0_i2c1 { pinctrl-0 = <&cp0_i2c1_pins>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; -- GitLab From 0ee03b8c8576bf00bd65e60f9a6bb49ca17102ae Mon Sep 17 00:00:00 2001 From: Ben Schneider Date: Sat, 3 Jun 2023 05:23:56 +0000 Subject: [PATCH 903/926] arm64: dts: marvell: Fix espressobin-ultra boot failure and wifi Boot hangs on EspressoBIN Ultra (Armada 3720) after a message that device vcc_sd1 had been disabled. The device manufacturer patched this issue in their kernel fork noting that vcc_sd1 is used by the EspressoBIN model but not the EspressoBIN Ultra. Removing the device from the tree fixes the boot hang and wifi. Signed-off-by: Ben Schneider Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index d29d2da95f4c3..f9abef8dcc948 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -24,6 +24,8 @@ aliases { ethernet5 = &switch0port4; }; + /delete-node/ regulator; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; @@ -66,6 +68,7 @@ &sdhci0 { }; &sdhci1 { + /delete-property/ vqmmc-supply; status = "disabled"; }; -- GitLab From a04cc7391d88a6e857611f009d30f49b7551daf3 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:22 +0800 Subject: [PATCH 904/926] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Add compatible string for T-HEAD TH1520 plic. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af7..0fa9b862e4a52 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - thead,th1520-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 -- GitLab From 413c24b03f4e50f7e8000079d51122e44d8a8f64 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:23 +0800 Subject: [PATCH 905/926] dt-bindings: timer: Add T-HEAD TH1520 clint Add compatible string for the T-HEAD TH1520 clint. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1b..388d3385d7ebb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 -- GitLab From 89b0186ab5325fa70852b42d7b0012bb2a1a4891 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:24 +0800 Subject: [PATCH 906/926] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml new file mode 100644 index 0000000000000..e62f6821372e4 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD SoC-based boards + +maintainers: + - Jisheng Zhang + +description: + T-HEAD SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A + items: + - enum: + - sipeed,lichee-pi-4a + - const: sipeed,lichee-module-4a + - const: thead,th1520 + +additionalProperties: true + +... -- GitLab From da47ce0039632d2e82ee70a86079d7a8b4c92103 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:25 +0800 Subject: [PATCH 907/926] riscv: Add the T-HEAD SoC family Kconfig option The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f104..ce10a38dff376 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT -- GitLab From 8e396880a864b80381b3f402e36d9c428422315b Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:26 +0800 Subject: [PATCH 908/926] riscv: dts: add initial T-HEAD TH1520 SoC device tree Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 422 ++++++++++++++++++++++++++ 1 file changed, 422 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi new file mode 100644 index 0000000000000..56a73134b49e6 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible = "thead,th1520"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,th1520-plic", "thead,c900-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <240>; + }; + + clint: timer@ffdc000000 { + compatible = "thead,th1520-clint", "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x100>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb_clk>, <&apb_clk>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; -- GitLab From 5af4cb0c42c5ee084c40ae37f6ecce839b4f65bc Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:27 +0800 Subject: [PATCH 909/926] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f82..1e884868ccba4 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y += allwinner subdir-y += sifive subdir-y += starfive +subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 0000000000000..e311fc9a59390 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 0000000000000..4b0249ac710f4 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 0000000000000..a1248b2ee3a3e --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; -- GitLab From 1203f584fe66522b0cf294424a35b4cfbc747d71 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:28 +0800 Subject: [PATCH 910/926] MAINTAINERS: add entry for T-HEAD RISC-V SoC Currently, I would like to maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e0ad886d31632..68805b09654f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18162,6 +18162,14 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +M: Guo Ren +M: Fu Wei +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang -- GitLab From 318afa0812049ddaff644482b035ab861d2a920c Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sun, 18 Jun 2023 00:15:29 +0800 Subject: [PATCH 911/926] riscv: defconfig: enable T-HEAD SoC Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Guo Ren Signed-off-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b82..109e4b5b003c3 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_THEAD=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y -- GitLab From 2bd9e07140ae7b22b5d049b1dde0449b2f2a28f8 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Sat, 17 Jun 2023 21:27:35 +0100 Subject: [PATCH 912/926] riscv: dts: sort makefile entries by directory New additions to the list have tried to respect alphanumeric ordering, but the thing was out of order to start with. Sort it. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 1e884868ccba4..f60a280abb157 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner -subdir-y += sifive -subdir-y += starfive -subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas +subdir-y += sifive +subdir-y += starfive +subdir-y += thead obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) -- GitLab From bf3ca248714b663455d0894557efd3a268797739 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sun, 18 Jun 2023 17:13:08 +0200 Subject: [PATCH 913/926] dt-bindings: firmware: brcm,kona-smc: convert to YAML Convert Broadcom Kona family Secure Monitor bounce buffer bindings to DT schema. Changes during conversion: - move from misc to firmware subdirectory - add used, but previously undocumented SoC-specific compatibles - drop deprecated compatibles (they've been deprecated for ~10 years) Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/20230618151308.GA23586@standask-GA-A55M-S2HP Signed-off-by: Florian Fainelli --- .../bindings/firmware/brcm,kona-smc.yaml | 39 +++++++++++++++++++ .../bindings/misc/brcm,kona-smc.txt | 15 ------- 2 files changed, 39 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/brcm,kona-smc.txt diff --git a/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml b/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml new file mode 100644 index 0000000000000..684b15ba9ad09 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/brcm,kona-smc.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/brcm,kona-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Kona family Secure Monitor bounce buffer + +description: + A bounce buffer used for non-secure to secure communications. + +maintainers: + - Florian Fainelli + +properties: + compatible: + items: + - enum: + - brcm,bcm11351-smc + - brcm,bcm21664-smc + - brcm,bcm23550-smc + - const: brcm,kona-smc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smc@3404c000 { + compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; + reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ + }; +... diff --git a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt b/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt deleted file mode 100644 index 05b47232ed9ed..0000000000000 --- a/Documentation/devicetree/bindings/misc/brcm,kona-smc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Broadcom Secure Monitor Bounce buffer ------------------------------------------------------ -This binding defines the location of the bounce buffer -used for non-secure to secure communications. - -Required properties: -- compatible : "brcm,kona-smc" -- DEPRECATED: compatible : "bcm,kona-smc" -- reg : Location and size of bounce buffer - -Example: - smc@3404c000 { - compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; - reg = <0x3404c000 0x400>; //1 KiB in SRAM - }; -- GitLab From b67cad33176e472df6d16a24ee7624299bdcd5d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 16 Jun 2023 12:58:27 +0200 Subject: [PATCH 914/926] ARM: dts: BCM5301X: Add cells sizes to PCIe nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#address-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#size-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#address-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#size-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#address-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#size-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml Two properties that need to be added later are "device_type" and "ranges". Adding "device_type" on its own causes a new warning and the value of "ranges" needs to be determined yet. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230616105827.21656-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-ns.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 53472d376a2c0..dae9c47ace761 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -176,14 +176,23 @@ chipcommon: chipcommon@0 { pcie0: pcie@12000 { reg = <0x00012000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie1: pcie@13000 { reg = <0x00013000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie2: pcie@14000 { reg = <0x00014000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@21000 { -- GitLab From 327ca228e58be498446244eb7cf39b892adda5d7 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 16 Jun 2023 13:16:43 +0300 Subject: [PATCH 915/926] ARM: dts: at91: use generic name for shutdown controller Use poweroff generic name for shdwc node to cope with device tree specifications. Signed-off-by: Claudiu Beznea Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/20230616101646.879480-2-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91-qil_a9260.dts | 2 +- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 2 +- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 2 +- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9260ek.dts | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- arch/arm/boot/dts/sama7g5.dtsi | 2 +- arch/arm/boot/dts/usb_a9260.dts | 2 +- arch/arm/boot/dts/usb_a9263.dts | 2 +- 20 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index 9d26f99963483..5ccb3c139592d 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -108,7 +108,7 @@ dbgu: serial@fffff200 { status = "okay"; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 52ddd0571f1c0..d0a6dbd377dfa 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -139,7 +139,7 @@ i2c3: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index bf1c9ca72a9f3..200b20515ab12 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -204,7 +204,7 @@ i2c2: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; input@0 { diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 2d53c47d7cc86..6680031387e8c 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -348,7 +348,7 @@ i2c2: i2c@600 { }; }; - shdwc@f8048010 { + poweroff@f8048010 { debounce-delay-us = <976>; atmel,wakeup-rtc-timer; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 16e3b24b4dddb..35a007365b6a5 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -130,7 +130,7 @@ reset-controller@fffffd00 { clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index bb72f050a4fef..720c15472c4a5 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -112,7 +112,7 @@ pinctrl_board_mmc0_slot1: mmc0_slot1-board { }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index fe9ead867e2ab..528ffc6f6f962 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -614,7 +614,7 @@ reset-controller@fffffd00 { clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index ee5e6ed44dd40..75d8ff2d12c8a 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -158,7 +158,7 @@ reset-controller@fffffd00 { clocks = <&slow_xtal>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index 024af2db638eb..565b99e79c520 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -126,7 +126,7 @@ flash@1 { }; }; - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 498cb92b29f96..7cccc606e36cd 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -152,7 +152,7 @@ pit: timer@fffffd30 { }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9rl-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0e28101b26bf0..8dc04e9031a6c 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -140,7 +140,7 @@ pit: timer@fffffe30 { clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; - shdwc@fffffe10 { + poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index d7e8a115c916c..3d089ffbe1626 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -778,7 +778,7 @@ reset-controller@fffffd00 { clocks = <&clk32k>; }; - shdwc@fffffd10 { + poweroff@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 0123ee47151cb..a1fed912f2eea 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -141,7 +141,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index c8bedfa987e57..8b53997675e75 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -1297,7 +1297,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k 0>; }; - shutdown_controller: shdwc@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "microchip,sam9x60-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 7b6471655deec..daeeb24e5f4db 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -680,7 +680,7 @@ reset_controller: reset-controller@f8048000 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@f8048010 { + shutdown_controller: poweroff@f8048010 { compatible = "atmel,sama5d2-shdwc"; reg = <0xf8048010 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 0eebf6c760b3d..d9e66700d1c20 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1016,7 +1016,7 @@ reset_controller: reset-controller@fffffe00 { clocks = <&clk32k>; }; - shutdown_controller: shutdown-controller@fffffe10 { + shutdown_controller: poweroff@fffffe10 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfffffe10 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index de6c829692327..41284e013f531 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -740,7 +740,7 @@ reset_controller: reset-controller@fc068600 { clocks = <&clk32k>; }; - shutdown_controller: shdwc@fc068610 { + shutdown_controller: poweroff@fc068610 { compatible = "atmel,at91sam9x5-shdwc"; reg = <0xfc068610 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index b55adb96a06ec..9642a42d84e60 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -257,7 +257,7 @@ reset_controller: reset-controller@e001d000 { clocks = <&clk32k 0>; }; - shdwc: shdwc@e001d010 { + shdwc: poweroff@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index 6cfa83921ac26..66f8da89007db 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -22,7 +22,7 @@ memory@20000000 { ahb { apb { - shdwc@fffffd10 { + shdwc: poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index b6cb9cdf81973..45745915b2e16 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -67,7 +67,7 @@ flash@0 { }; }; - shdwc@fffffd10 { + poweroff@fffffd10 { atmel,wakeup-counter = <10>; atmel,wakeup-rtt-timer; }; -- GitLab From 12109610a5ce5fe257a1ab6132234d6c9346044d Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 12 Jun 2023 20:01:02 +0200 Subject: [PATCH 916/926] arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller As described in the corresponding binding documentation for "samsung,exynos850-pmu", the "clocks" property should be used for specifying CLKOUT mux inputs. Therefore, the clock provided to exynos850 pmu_system_controller is incorrect and should be removed. Instead of making syscon regmap keep that clock running for PMU accesses, it should be made always running in the clock driver, because the kernel is not the only software accessing PMU registers on Exynos850 platform. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20230308233822.31180-8-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230612180102.289745-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d67e981203132..aa077008b3bef 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -200,7 +200,6 @@ gic: interrupt-controller@12a01000 { pmu_system_controller: system-controller@11860000 { compatible = "samsung,exynos850-pmu", "syscon"; reg = <0x11860000 0x10000>; - clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; reboot: syscon-reboot { compatible = "syscon-reboot"; -- GitLab From 11d5441cde740c89252290e04ad79f133c366bdb Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Fri, 16 Jun 2023 18:29:32 +0300 Subject: [PATCH 917/926] arm: dts: Enable device-tree overlay support for AT91 boards Add the '-@' DTC option for AT91 boards that have device-tree overlays. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (from bootloader) on these devices. This change increases the size of the resulting DTB with ~30%-40%. Below are the measurements performed v6.4-rc6: at91-sam9x60_curiosity.dtb 28499 -> 36641 bytes at91-sam9x60ek.dtb 30867 -> 39609 bytes at91-sama5d27_som1_ek.dtb 26086 -> 34166 bytes at91-sama5d27_wlsom1_ek.dtb 26045 -> 33184 bytes at91-sama5d2_icp.dtb 27521 -> 36155 bytes at91-sama5d2_ptc_ek.dtb 23237 -> 29612 bytes at91-sama5d2_xplained.dtb 27262 -> 35326 bytes at91-sama5d3_eds.dtb 27924 -> 39939 bytes at91-sama5d3_xplained.dtb 28400 -> 40650 bytes at91-sama5d4_xplained.dtb 26456 -> 36107 bytes at91-sama7g5ek.dtb 29212 -> 37289 bytes Signed-off-by: Cristian Birsan Link: https://lore.kernel.org/r/20230616152932.1484154-1-cristian.birsan@microchip.com Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 29b1386e24cd6..7e0f392dffdea 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -50,9 +50,21 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91sam9g35ek.dtb \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ @@ -79,6 +91,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g5ek.dtb dtb-$(CONFIG_SOC_SP7021) += \ -- GitLab From 15e2d241d160a1a0816588d96b56e54c306fc1da Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Fri, 16 Jun 2023 18:29:32 +0300 Subject: [PATCH 918/926] ARM: dts: at91: Enable device-tree overlay support for AT91 boards Add the '-@' DTC option for AT91 boards that have device-tree overlays. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (from bootloader) on these devices. This change increases the size of the resulting DTB with ~30%-40%. Below are the measurements performed v6.4-rc6: at91-sam9x60_curiosity.dtb 28499 -> 36641 bytes at91-sam9x60ek.dtb 30867 -> 39609 bytes at91-sama5d27_som1_ek.dtb 26086 -> 34166 bytes at91-sama5d27_wlsom1_ek.dtb 26045 -> 33184 bytes at91-sama5d2_icp.dtb 27521 -> 36155 bytes at91-sama5d2_ptc_ek.dtb 23237 -> 29612 bytes at91-sama5d2_xplained.dtb 27262 -> 35326 bytes at91-sama5d3_eds.dtb 27924 -> 39939 bytes at91-sama5d3_xplained.dtb 28400 -> 40650 bytes at91-sama5d4_xplained.dtb 26456 -> 36107 bytes at91-sama7g5ek.dtb 29212 -> 37289 bytes Signed-off-by: Cristian Birsan [claudiu.beznea: s/arm: dts/ARM: dts: at91/ in commit title] Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230616152932.1484154-1-cristian.birsan@microchip.com --- arch/arm/boot/dts/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc903152..38b82af2bf691 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -50,9 +50,21 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91sam9g35ek.dtb \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ @@ -79,6 +91,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g5ek.dtb dtb-$(CONFIG_SOC_SP7021) += \ -- GitLab From bfcd5714f6424c03e385e0e9296dcd69855cfea7 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 16 Jun 2023 15:18:39 +0200 Subject: [PATCH 919/926] ARM: dts: lan966x: kontron-d10: fix board reset The pinctrl node was missing which change the pin mux to GPIO mode. Add it. Fixes: 79d83b3a458e ("ARM: dts: lan966x: add basic Kontron KSwitch D10 support") Signed-off-by: Michael Walle [claudiu.beznea: moved pinctrl-* bindings after compatible] Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230616-feature-d10-dt-cleanups-v1-1-50dd0452b8fe@kernel.org --- arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi index 0097e72e3fb22..42be207509a46 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -18,6 +18,8 @@ chosen { gpio-restart { compatible = "gpio-restart"; + pinctrl-0 = <&reset_pins>; + pinctrl-names = "default"; gpios = <&gpio 56 GPIO_ACTIVE_LOW>; priority = <200>; }; @@ -59,6 +61,12 @@ miim_c_pins: miim-c-pins { function = "miim_c"; }; + reset_pins: reset-pins { + /* SYS_RST# */ + pins = "GPIO_56"; + function = "gpio"; + }; + sgpio_a_pins: sgpio-a-pins { /* SCK, D0, D1 */ pins = "GPIO_32", "GPIO_33", "GPIO_34"; -- GitLab From fcb79ee3f0b15ed15f35eca5f24e952fdced9c61 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 16 Jun 2023 15:18:40 +0200 Subject: [PATCH 920/926] ARM: dts: lan966x: kontron-d10: fix SPI CS The pinctrl node was missing which change the pin mux to GPIO mode. Add it so we don't have to rely on the bootloader to set the correct mode. Fixes: 79d83b3a458e ("ARM: dts: lan966x: add basic Kontron KSwitch D10 support") Signed-off-by: Michael Walle Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230616-feature-d10-dt-cleanups-v1-2-50dd0452b8fe@kernel.org --- arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi index 42be207509a46..f4df4cc1dfa5e 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -41,7 +41,7 @@ &flx3 { status = "okay"; spi3: spi@400 { - pinctrl-0 = <&fc3_b_pins>; + pinctrl-0 = <&fc3_b_pins>, <&spi3_cs_pins>; pinctrl-names = "default"; status = "okay"; cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; @@ -79,6 +79,12 @@ sgpio_b_pins: sgpio-b-pins { function = "sgpio_b"; }; + spi3_cs_pins: spi3-cs-pins { + /* CS# */ + pins = "GPIO_46"; + function = "gpio"; + }; + usart0_pins: usart0-pins { /* RXD, TXD */ pins = "GPIO_25", "GPIO_26"; -- GitLab From 33c01ff3b1003aea11288f2bf7924ada5b5b8327 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 16 Jun 2023 15:18:41 +0200 Subject: [PATCH 921/926] ARM: dts: lan966x: kontron-d10: add PHY interrupts With interrupt handling fixed in the MaxLinear PHY driver, see commit 97a89ed101bb ("net: phy: mxl-gpy: disable interrupts on GPY215 by default"), we can finally add the correct interrupt description to the device tree. Signed-off-by: Michael Walle Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230616-feature-d10-dt-cleanups-v1-3-50dd0452b8fe@kernel.org --- .../boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts | 2 ++ .../boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts index 5feef9a59a790..ad5d8b56e6fa9 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -15,10 +15,12 @@ / { &mdio0 { phy2: ethernet-phy@3 { reg = <3>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; }; phy3: ethernet-phy@4 { reg = <4>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi index f4df4cc1dfa5e..426893750d51f 100644 --- a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -49,6 +49,9 @@ spi3: spi@400 { }; &gpio { + pinctrl-0 = <&phy_int_pins>; + pinctrl-names = "default"; + fc3_b_pins: fc3-b-pins { /* SCK, MISO, MOSI */ pins = "GPIO_51", "GPIO_52", "GPIO_53"; @@ -61,6 +64,12 @@ miim_c_pins: miim-c-pins { function = "miim_c"; }; + phy_int_pins: phy-int-pins { + /* PHY_INT# */ + pins = "GPIO_24"; + function = "gpio"; + }; + reset_pins: reset-pins { /* SYS_RST# */ pins = "GPIO_56"; @@ -107,21 +116,25 @@ &mdio0 { phy4: ethernet-phy@5 { reg = <5>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy5: ethernet-phy@6 { reg = <6>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy6: ethernet-phy@7 { reg = <7>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; phy7: ethernet-phy@8 { reg = <8>; + interrupts-extended = <&gpio 24 IRQ_TYPE_LEVEL_LOW>; coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>; }; }; -- GitLab From ca2fb05cb7e41d7f8b7399adbc2e71016483efad Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 2 May 2023 12:02:42 -0500 Subject: [PATCH 922/926] ARM: dts: allwinner: Use quoted #include In preparation to move .dts files into subdirectories, include sunxi-h3-h5-emlid-neutis.dtsi from the current directory rather than the symlinked include path. Reviewed-by: Andre Przywara Signed-off-by: Rob Herring --- arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi index eedd5da5dc2f2..35e71f46c197e 100644 --- a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun8i-h3.dtsi" -#include +#include "sunxi-h3-h5-emlid-neutis.dtsi" -- GitLab From 86684c2481b6e6a46c2282acee13554e34e66071 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 2 May 2023 12:25:29 -0500 Subject: [PATCH 923/926] ARM: dts: Add .dts files missing from the build Comparing .dts files to built .dtb files yielded a few .dts files which are never built. Add them to the build. Signed-off-by: Rob Herring --- arch/arm/boot/dts/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e1b1f2cfb274..c6798925fe453 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -368,6 +368,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-iconnect.dtb \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ + kirkwood-km_fixedeth.dtb \ kirkwood-km_kirkwood.dtb \ kirkwood-l-50.dtb \ kirkwood-laplug.dtb \ @@ -914,7 +915,10 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ am3517-craneboard.dtb \ am3517-evm.dtb \ am3517_mt_ventoux.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ logicpd-torpedo-37xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit-28.dtb \ + logicpd-som-lv-35xx-devkit.dtb \ logicpd-som-lv-37xx-devkit.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ @@ -1599,6 +1603,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \ armada-388-helios4.dtb \ armada-388-rd.dtb dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-390-db.dtb \ + armada-395-gp.dtb \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ @@ -1628,6 +1634,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt2701-evb.dtb \ mt6580-evbp1.dtb \ + mt6582-prestigio-pmt5008-3g.dtb \ mt6589-aquaris5.dtb \ mt6589-fairphone-fp1.dtb \ mt6592-evb.dtb \ @@ -1683,6 +1690,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-inspur-nf5280m6.dtb \ + aspeed-bmc-inspur-on5263m5.dtb \ aspeed-bmc-lenovo-hr630.dtb \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ -- GitLab From 6a1d798feb65d2a67e6e2cafb0b0e4f430603226 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Dec 2018 10:29:51 -0600 Subject: [PATCH 924/926] kbuild: Support flat DTBs install In preparation to move Arm .dts files into sub-directories grouped by vendor/family, the current flat tree of DTBs generated by dtbs_install needs to be maintained. Moving the installed DTBs to sub-directories would break various consumers using 'make dtbs_install'. This is a NOP until sub-directories are introduced. Signed-off-by: Rob Herring --- arch/arm/Kconfig | 3 +++ scripts/Makefile.dtbinst | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0fb4b218f6658..47c1845f0b1bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1460,6 +1460,9 @@ config USE_OF help Include support for flattened device tree machine descriptions. +config ARCH_WANT_FLAT_DTB_INSTALL + def_bool y + config ATAGS bool "Support for the traditional ATAGS boot data passing" default y diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index 2ab936e4179da..4405d5b67578d 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst @@ -34,6 +34,6 @@ $(dst)/%.dtbo: $(obj)/%.dtbo PHONY += $(subdirs) $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) + $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) .PHONY: $(PHONY) -- GitLab From 724ba6751532055db75992fc6ae21c3e322e94a7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 4 May 2023 18:38:52 -0500 Subject: [PATCH 925/926] ARM: dts: Move .dts files to vendor sub-directories The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar Acked-by: Michal Simek #Xilinx Acked-by: Krzysztof Kozlowski Acked-by: Neil Armstrong Acked-by: Paul Barker Acked-by: Tony Lindgren Acked-by: Gregory CLEMENT Acked-by: Heiko Stuebner Acked-by: Wei Xu #hisilicon Acked-by: Geert Uytterhoeven Acked-by: Nick Hawkins Acked-by: Baruch Siach Reviewed-by: Linus Walleij Reviewed-by: Andre Przywara Acked-by: Andre Przywara Reviewed-by: Claudiu Beznea Acked-by: Peter Rosin Acked-by: Jesper Nilsson Acked-by: Sudeep Holla Acked-by: Florian Fainelli #broadcom Acked-by: Manivannan Sadhasivam Reviewed-by: Jisheng Zhang Acked-by: Patrice Chotard Acked-by: Romain Perier Acked-by: Alexandre TORGUE Acked-by: Shawn Guo Acked-by: Kunihiko Hayashi Acked-by: Enric Balletbo i Serra Signed-off-by: Rob Herring --- MAINTAINERS | 186 +- arch/arm/boot/dts/Makefile | 1757 +---------------- arch/arm/boot/dts/actions/Makefile | 7 + .../{ => actions}/owl-s500-cubieboard6.dts | 0 .../owl-s500-guitar-bb-rev-b.dts | 0 .../dts/{ => actions}/owl-s500-guitar.dtsi | 0 .../owl-s500-labrador-base-m.dts | 0 .../{ => actions}/owl-s500-labrador-v2.dtsi | 0 .../{ => actions}/owl-s500-roseapplepi.dts | 0 .../dts/{ => actions}/owl-s500-sparky.dts | 0 arch/arm/boot/dts/{ => actions}/owl-s500.dtsi | 0 arch/arm/boot/dts/airoha/Makefile | 3 + arch/arm/boot/dts/{ => airoha}/en7523-evb.dts | 0 arch/arm/boot/dts/{ => airoha}/en7523.dtsi | 0 arch/arm/boot/dts/allwinner/Makefile | 315 +++ arch/arm/boot/dts/{ => allwinner}/axp152.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/axp209.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/axp223.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/axp22x.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/axp809.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/axp81x.dtsi | 0 .../dts/{ => allwinner}/sun4i-a10-a1000.dts | 0 .../{ => allwinner}/sun4i-a10-ba10-tvbox.dts | 0 .../sun4i-a10-chuwi-v7-cw0825.dts | 0 .../{ => allwinner}/sun4i-a10-cubieboard.dts | 0 .../sun4i-a10-dserve-dsrv9703c.dts | 0 .../{ => allwinner}/sun4i-a10-gemei-g9.dts | 0 .../{ => allwinner}/sun4i-a10-hackberry.dts | 0 .../sun4i-a10-hyundai-a7hd.dts | 0 .../dts/{ => allwinner}/sun4i-a10-inet1.dts | 0 .../{ => allwinner}/sun4i-a10-inet97fv2.dts | 0 .../sun4i-a10-inet9f-rev03.dts | 0 .../sun4i-a10-itead-iteaduino-plus.dts | 0 .../{ => allwinner}/sun4i-a10-jesurun-q5.dts | 0 .../{ => allwinner}/sun4i-a10-marsboard.dts | 0 .../{ => allwinner}/sun4i-a10-mini-xplus.dts | 0 .../dts/{ => allwinner}/sun4i-a10-mk802.dts | 0 .../dts/{ => allwinner}/sun4i-a10-mk802ii.dts | 0 .../sun4i-a10-olinuxino-lime.dts | 0 .../dts/{ => allwinner}/sun4i-a10-pcduino.dts | 0 .../{ => allwinner}/sun4i-a10-pcduino2.dts | 0 .../sun4i-a10-pov-protab2-ips9.dts | 0 .../sun4i-a10-topwise-a721.dts | 0 .../boot/dts/{ => allwinner}/sun4i-a10.dtsi | 0 .../sun5i-a10s-auxtek-t003.dts | 0 .../sun5i-a10s-auxtek-t004.dts | 0 .../dts/{ => allwinner}/sun5i-a10s-mk802.dts | 0 .../sun5i-a10s-olinuxino-micro.dts | 0 .../sun5i-a10s-r7-tv-dongle.dts | 0 .../{ => allwinner}/sun5i-a10s-wobo-i5.dts | 0 .../boot/dts/{ => allwinner}/sun5i-a10s.dtsi | 0 .../sun5i-a13-difrnce-dit4350.dts | 0 .../sun5i-a13-empire-electronix-d709.dts | 0 .../sun5i-a13-empire-electronix-m712.dts | 0 .../{ => allwinner}/sun5i-a13-hsg-h702.dts | 0 .../sun5i-a13-inet-98v-rev2.dts | 0 .../sun5i-a13-licheepi-one.dts | 0 .../sun5i-a13-olinuxino-micro.dts | 0 .../{ => allwinner}/sun5i-a13-olinuxino.dts | 0 .../sun5i-a13-pocketbook-touch-lux-3.dts | 0 .../{ => allwinner}/sun5i-a13-q8-tablet.dts | 0 .../{ => allwinner}/sun5i-a13-utoo-p66.dts | 0 .../boot/dts/{ => allwinner}/sun5i-a13.dtsi | 0 .../{ => allwinner}/sun5i-gr8-chip-pro.dts | 0 .../dts/{ => allwinner}/sun5i-gr8-evb.dts | 0 .../boot/dts/{ => allwinner}/sun5i-gr8.dtsi | 0 .../dts/{ => allwinner}/sun5i-r8-chip.dts | 0 .../boot/dts/{ => allwinner}/sun5i-r8.dtsi | 0 .../sun5i-reference-design-tablet.dtsi | 0 arch/arm/boot/dts/{ => allwinner}/sun5i.dtsi | 0 .../{ => allwinner}/sun6i-a31-app4-evb1.dts | 0 .../{ => allwinner}/sun6i-a31-colombus.dts | 0 .../{ => allwinner}/sun6i-a31-hummingbird.dts | 0 .../boot/dts/{ => allwinner}/sun6i-a31-i7.dts | 0 .../boot/dts/{ => allwinner}/sun6i-a31-m9.dts | 0 .../sun6i-a31-mele-a1000g-quad.dts | 0 .../boot/dts/{ => allwinner}/sun6i-a31.dtsi | 0 .../sun6i-a31s-colorfly-e708-q1.dts | 0 .../dts/{ => allwinner}/sun6i-a31s-cs908.dts | 0 .../{ => allwinner}/sun6i-a31s-inet-q972.dts | 0 .../{ => allwinner}/sun6i-a31s-primo81.dts | 0 .../sun6i-a31s-sina31s-core.dtsi | 0 .../{ => allwinner}/sun6i-a31s-sina31s.dts | 0 .../sun6i-a31s-sinovoip-bpi-m2.dts | 0 .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 0 .../boot/dts/{ => allwinner}/sun6i-a31s.dtsi | 0 .../sun6i-reference-design-tablet.dtsi | 0 .../sun7i-a20-bananapi-m1-plus.dts | 0 .../{ => allwinner}/sun7i-a20-bananapi.dts | 0 .../{ => allwinner}/sun7i-a20-bananapro.dts | 0 .../{ => allwinner}/sun7i-a20-cubieboard2.dts | 0 .../{ => allwinner}/sun7i-a20-cubietruck.dts | 0 .../sun7i-a20-haoyu-marsboard.dts | 0 .../{ => allwinner}/sun7i-a20-hummingbird.dts | 0 .../{ => allwinner}/sun7i-a20-i12-tvbox.dts | 0 .../sun7i-a20-icnova-a20-adb4006.dts | 0 .../{ => allwinner}/sun7i-a20-icnova-a20.dtsi | 0 .../{ => allwinner}/sun7i-a20-icnova-swac.dts | 0 .../{ => allwinner}/sun7i-a20-itead-ibox.dts | 0 .../{ => allwinner}/sun7i-a20-lamobo-r1.dts | 0 .../sun7i-a20-linutronix-testbox-v2.dts | 0 .../boot/dts/{ => allwinner}/sun7i-a20-m3.dts | 0 .../dts/{ => allwinner}/sun7i-a20-mk808c.dts | 0 .../sun7i-a20-olimex-som-evb-emmc.dts | 0 .../sun7i-a20-olimex-som-evb.dts | 0 .../sun7i-a20-olimex-som204-evb-emmc.dts | 0 .../sun7i-a20-olimex-som204-evb.dts | 0 .../sun7i-a20-olinuxino-lime-emmc.dts | 0 .../sun7i-a20-olinuxino-lime.dts | 0 .../sun7i-a20-olinuxino-lime2-emmc.dts | 0 .../sun7i-a20-olinuxino-lime2.dts | 0 .../sun7i-a20-olinuxino-micro-emmc.dts | 0 .../sun7i-a20-olinuxino-micro.dts | 0 .../sun7i-a20-orangepi-mini.dts | 0 .../{ => allwinner}/sun7i-a20-orangepi.dts | 0 .../sun7i-a20-pcduino3-nano.dts | 0 .../{ => allwinner}/sun7i-a20-pcduino3.dts | 0 .../sun7i-a20-wexler-tab7200.dts | 0 .../sun7i-a20-wits-pro-a20-dkt.dts | 0 .../boot/dts/{ => allwinner}/sun7i-a20.dtsi | 0 .../dts/{ => allwinner}/sun8i-a23-a33.dtsi | 0 .../dts/{ => allwinner}/sun8i-a23-evb.dts | 0 .../{ => allwinner}/sun8i-a23-gt90h-v4.dts | 0 .../{ => allwinner}/sun8i-a23-inet86dz.dts | 0 .../sun8i-a23-ippo-q8h-v1.2.dts | 0 .../{ => allwinner}/sun8i-a23-ippo-q8h-v5.dts | 0 .../sun8i-a23-polaroid-mid2407pxe03.dts | 0 .../sun8i-a23-polaroid-mid2809pxe04.dts | 0 .../{ => allwinner}/sun8i-a23-q8-tablet.dts | 0 .../boot/dts/{ => allwinner}/sun8i-a23.dtsi | 0 .../{ => allwinner}/sun8i-a33-et-q8-v1.6.dts | 0 .../{ => allwinner}/sun8i-a33-ga10h-v1.1.dts | 0 .../sun8i-a33-inet-d978-rev2.dts | 0 .../sun8i-a33-ippo-q8h-v1.2.dts | 0 .../{ => allwinner}/sun8i-a33-olinuxino.dts | 0 .../{ => allwinner}/sun8i-a33-q8-tablet.dts | 0 .../sun8i-a33-sinlinx-sina33.dts | 0 .../boot/dts/{ => allwinner}/sun8i-a33.dtsi | 0 .../sun8i-a83t-allwinner-h8homlet-v2.dts | 0 .../sun8i-a83t-bananapi-m3.dts | 0 .../sun8i-a83t-cubietruck-plus.dts | 0 .../{ => allwinner}/sun8i-a83t-tbs-a711.dts | 0 .../boot/dts/{ => allwinner}/sun8i-a83t.dtsi | 0 .../sun8i-h2-plus-bananapi-m2-zero.dts | 0 .../sun8i-h2-plus-libretech-all-h3-cc.dts | 0 .../sun8i-h2-plus-orangepi-r1.dts | 0 .../sun8i-h2-plus-orangepi-zero.dts | 0 .../sun8i-h3-bananapi-m2-plus-v1.2.dts | 0 .../sun8i-h3-bananapi-m2-plus.dts | 0 .../{ => allwinner}/sun8i-h3-beelink-x2.dts | 0 .../sun8i-h3-emlid-neutis-n5h3-devboard.dts | 0 .../sun8i-h3-emlid-neutis-n5h3.dtsi | 0 .../sun8i-h3-libretech-all-h3-cc.dts | 0 .../sun8i-h3-mapleboard-mp130.dts | 0 .../{ => allwinner}/sun8i-h3-nanopi-duo2.dts | 0 .../sun8i-h3-nanopi-m1-plus.dts | 0 .../{ => allwinner}/sun8i-h3-nanopi-m1.dts | 0 .../sun8i-h3-nanopi-neo-air.dts | 0 .../{ => allwinner}/sun8i-h3-nanopi-neo.dts | 0 .../{ => allwinner}/sun8i-h3-nanopi-r1.dts | 0 .../dts/{ => allwinner}/sun8i-h3-nanopi.dtsi | 0 .../{ => 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broadcom}/bcm953012er.dts | 0 .../boot/dts/{ => broadcom}/bcm953012hr.dts | 0 .../boot/dts/{ => broadcom}/bcm953012k.dts | 0 .../boot/dts/{ => broadcom}/bcm958300k.dts | 0 .../boot/dts/{ => broadcom}/bcm958305k.dts | 0 .../boot/dts/{ => broadcom}/bcm958522er.dts | 0 .../boot/dts/{ => broadcom}/bcm958525er.dts | 0 .../boot/dts/{ => broadcom}/bcm958525xmc.dts | 0 .../boot/dts/{ => broadcom}/bcm958622hr.dts | 0 .../boot/dts/{ => broadcom}/bcm958623hr.dts | 0 .../bcm958625-meraki-alamo.dtsi | 0 .../bcm958625-meraki-kingpin.dtsi | 0 .../bcm958625-meraki-mx64-a0.dts | 0 .../{ => broadcom}/bcm958625-meraki-mx64.dts | 0 .../bcm958625-meraki-mx64w-a0.dts | 0 .../{ => broadcom}/bcm958625-meraki-mx64w.dts | 0 .../{ => broadcom}/bcm958625-meraki-mx65.dts | 0 .../{ => broadcom}/bcm958625-meraki-mx65w.dts | 0 .../bcm958625-meraki-mx6x-common.dtsi | 0 .../boot/dts/{ => broadcom}/bcm958625hr.dts | 0 .../boot/dts/{ => broadcom}/bcm958625k.dts | 0 .../arm/boot/dts/{ => broadcom}/bcm963138.dts | 0 .../boot/dts/{ => broadcom}/bcm963138dvt.dts | 0 .../arm/boot/dts/{ => broadcom}/bcm963148.dts | 0 .../arm/boot/dts/{ => broadcom}/bcm963178.dts | 0 arch/arm/boot/dts/{ => broadcom}/bcm96756.dts | 0 arch/arm/boot/dts/{ => broadcom}/bcm96846.dts | 0 arch/arm/boot/dts/{ => broadcom}/bcm96855.dts | 0 arch/arm/boot/dts/{ => broadcom}/bcm96878.dts | 0 .../boot/dts/{ => broadcom}/bcm988312hr.dts | 0 .../boot/dts/{ => broadcom}/bcm9hmidc.dtsi | 0 arch/arm/boot/dts/calxeda/Makefile | 7 + arch/arm/boot/dts/{ => calxeda}/ecx-2000.dts | 0 .../boot/dts/{ => calxeda}/ecx-common.dtsi | 0 arch/arm/boot/dts/{ => calxeda}/highbank.dts | 0 arch/arm/boot/dts/cirrus/Makefile | 5 + arch/arm/boot/dts/{ => cirrus}/ep7209.dtsi | 0 .../boot/dts/{ => cirrus}/ep7211-edb7211.dts | 0 arch/arm/boot/dts/{ => cirrus}/ep7211.dtsi | 0 arch/arm/boot/dts/cnxt/Makefile | 5 + arch/arm/boot/dts/{ => cnxt}/cx92755.dtsi | 0 .../boot/dts/{ => cnxt}/cx92755_equinox.dts | 0 arch/arm/boot/dts/gemini/Makefile | 12 + .../dts/{ => gemini}/gemini-dlink-dir-685.dts | 0 .../dts/{ => gemini}/gemini-dlink-dns-313.dts | 0 .../boot/dts/{ => gemini}/gemini-nas4220b.dts | 0 .../boot/dts/{ => gemini}/gemini-ns2502.dts | 0 .../boot/dts/{ => gemini}/gemini-rut1xx.dts | 0 .../boot/dts/{ => gemini}/gemini-sl93512r.dts | 0 .../boot/dts/{ => gemini}/gemini-sq201.dts | 0 .../boot/dts/{ => gemini}/gemini-ssi1328.dts | 0 .../boot/dts/{ => gemini}/gemini-wbd111.dts | 0 .../boot/dts/{ => gemini}/gemini-wbd222.dts | 0 arch/arm/boot/dts/{ => gemini}/gemini.dtsi | 0 arch/arm/boot/dts/hisilicon/Makefile | 13 + .../boot/dts/{ => hisilicon}/hi3519-demb.dts | 0 arch/arm/boot/dts/{ => hisilicon}/hi3519.dtsi | 0 .../dts/{ => hisilicon}/hi3620-hi4511.dts | 0 arch/arm/boot/dts/{ => hisilicon}/hi3620.dtsi | 0 .../boot/dts/{ => hisilicon}/hip01-ca9x2.dts | 0 arch/arm/boot/dts/{ => hisilicon}/hip01.dtsi | 0 .../boot/dts/{ => hisilicon}/hip04-d01.dts | 0 arch/arm/boot/dts/{ => hisilicon}/hip04.dtsi | 0 .../dts/{ => hisilicon}/hisi-x5hd2-dkb.dts | 0 .../boot/dts/{ => hisilicon}/hisi-x5hd2.dtsi | 0 arch/arm/boot/dts/{ => hisilicon}/sd5203.dts | 0 arch/arm/boot/dts/hpe/Makefile | 3 + .../boot/dts/{ => hpe}/hpe-bmc-dl360gen10.dts | 0 arch/arm/boot/dts/{ => hpe}/hpe-gxp.dtsi | 0 arch/arm/boot/dts/intel/Makefile | 5 + arch/arm/boot/dts/intel/axm/Makefile | 5 + .../dts/{ => intel/axm}/axm5516-amarillo.dts | 0 .../dts/{ => intel/axm}/axm5516-cpus.dtsi | 0 .../arm/boot/dts/{ => intel/axm}/axm55xx.dtsi | 0 arch/arm/boot/dts/intel/ixp/Makefile | 19 + .../ixp}/intel-ixp42x-adi-coyote.dts | 0 .../ixp}/intel-ixp42x-arcom-vulcan.dts | 0 .../ixp}/intel-ixp42x-dlink-dsm-g600.dts | 0 .../ixp}/intel-ixp42x-freecom-fsg-3.dts | 0 .../ixp}/intel-ixp42x-gateway-7001.dts | 0 .../ixp}/intel-ixp42x-gateworks-gw2348.dts | 0 .../ixp}/intel-ixp42x-goramo-multilink.dts | 0 .../ixp}/intel-ixp42x-iomega-nas100d.dts | 0 .../{ => intel/ixp}/intel-ixp42x-ixdp425.dts | 0 .../{ => intel/ixp}/intel-ixp42x-ixdpg425.dts | 0 .../ixp}/intel-ixp42x-linksys-nslu2.dts | 0 .../ixp}/intel-ixp42x-linksys-wrv54g.dts | 0 .../ixp}/intel-ixp42x-netgear-wg302v1.dts | 0 .../ixp}/intel-ixp42x-welltech-epbx100.dts | 0 .../dts/{ => intel/ixp}/intel-ixp42x.dtsi | 0 .../ixp}/intel-ixp43x-gateworks-gw2358.dts | 0 .../{ => intel/ixp}/intel-ixp43x-kixrp435.dts | 0 .../dts/{ => intel/ixp}/intel-ixp43x.dtsi | 0 .../{ => intel/ixp}/intel-ixp45x-ixp46x.dtsi | 0 .../{ => intel/ixp}/intel-ixp46x-ixdp465.dts | 0 .../ixp}/intel-ixp4xx-reference-design.dtsi | 0 .../dts/{ => intel/ixp}/intel-ixp4xx.dtsi | 0 arch/arm/boot/dts/intel/pxa/Makefile | 8 + arch/arm/boot/dts/{ => intel/pxa}/pxa25x.dtsi | 0 arch/arm/boot/dts/{ => intel/pxa}/pxa27x.dtsi | 0 arch/arm/boot/dts/{ => intel/pxa}/pxa2xx.dtsi | 0 .../pxa}/pxa300-raumfeld-common.dtsi | 0 .../pxa}/pxa300-raumfeld-connector.dts | 0 .../pxa}/pxa300-raumfeld-controller.dts | 0 .../pxa}/pxa300-raumfeld-speaker-l.dts | 0 .../pxa}/pxa300-raumfeld-speaker-m.dts | 0 .../pxa}/pxa300-raumfeld-speaker-one.dts | 0 .../pxa}/pxa300-raumfeld-speaker-s.dts | 0 .../pxa}/pxa300-raumfeld-tuneable-clock.dtsi | 0 arch/arm/boot/dts/{ => intel/pxa}/pxa3xx.dtsi | 0 arch/arm/boot/dts/intel/socfpga/Makefile | 17 + .../boot/dts/{ => intel/socfpga}/socfpga.dtsi | 0 .../{ => intel/socfpga}/socfpga_arria10.dtsi | 0 .../socfpga}/socfpga_arria10_chameleonv3.dts | 0 .../socfpga}/socfpga_arria10_mercury_aa1.dtsi | 0 .../socfpga}/socfpga_arria10_mercury_pe1.dts | 0 .../socfpga}/socfpga_arria10_socdk.dtsi | 0 .../socfpga}/socfpga_arria10_socdk_nand.dts | 0 .../socfpga}/socfpga_arria10_socdk_qspi.dts | 0 .../socfpga}/socfpga_arria10_socdk_sdmmc.dts | 0 .../{ => intel/socfpga}/socfpga_arria5.dtsi | 0 .../socfpga}/socfpga_arria5_socdk.dts | 0 .../{ => intel/socfpga}/socfpga_cyclone5.dtsi | 0 .../socfpga}/socfpga_cyclone5_chameleon96.dts | 0 .../socfpga_cyclone5_de0_nano_soc.dts | 0 .../socfpga}/socfpga_cyclone5_mcv.dtsi | 0 .../socfpga}/socfpga_cyclone5_mcvevk.dts | 0 .../socfpga}/socfpga_cyclone5_socdk.dts | 0 .../socfpga}/socfpga_cyclone5_sockit.dts | 0 .../socfpga}/socfpga_cyclone5_socrates.dts | 0 .../socfpga}/socfpga_cyclone5_sodia.dts | 0 .../socfpga}/socfpga_cyclone5_vining_fpga.dts | 0 .../dts/{ => intel/socfpga}/socfpga_vt.dts | 0 arch/arm/boot/dts/marvell/Makefile | 165 ++ .../dts/{ => marvell}/armada-370-c200-v2.dts | 0 .../boot/dts/{ => marvell}/armada-370-db.dts | 0 .../armada-370-dlink-dns327l.dts | 0 .../dts/{ => marvell}/armada-370-mirabox.dts | 0 .../armada-370-netgear-rn102.dts | 0 .../armada-370-netgear-rn104.dts | 0 .../boot/dts/{ => marvell}/armada-370-rd.dts | 0 .../armada-370-seagate-nas-2bay.dts | 0 .../armada-370-seagate-nas-4bay.dts | 0 .../armada-370-seagate-nas-xbay.dtsi | 0 ...armada-370-seagate-personal-cloud-2bay.dts | 0 .../armada-370-seagate-personal-cloud.dts | 0 .../armada-370-seagate-personal-cloud.dtsi | 0 .../armada-370-synology-ds213j.dts | 0 .../boot/dts/{ => marvell}/armada-370-xp.dtsi | 0 .../boot/dts/{ => marvell}/armada-370.dtsi | 0 .../boot/dts/{ => marvell}/armada-375-db.dts | 0 .../boot/dts/{ => marvell}/armada-375.dtsi | 0 .../boot/dts/{ => marvell}/armada-380.dtsi | 0 .../armada-381-netgear-gs110emx.dts | 0 .../armada-382-rd-ac3x-48g4x2xl.dts | 0 .../dts/{ => marvell}/armada-385-atl-x530.dts | 0 .../armada-385-clearfog-gtr-l8.dts | 0 .../armada-385-clearfog-gtr-s4.dts | 0 .../armada-385-clearfog-gtr.dtsi | 0 .../armada-385-db-88f6820-amc.dts | 0 .../dts/{ => marvell}/armada-385-db-ap.dts | 0 .../armada-385-linksys-caiman.dts | 0 .../armada-385-linksys-cobra.dts | 0 .../armada-385-linksys-rango.dts | 0 .../armada-385-linksys-shelby.dts | 0 .../dts/{ => marvell}/armada-385-linksys.dtsi | 0 .../armada-385-synology-ds116.dts | 0 .../{ => marvell}/armada-385-turris-omnia.dts | 0 .../boot/dts/{ => marvell}/armada-385.dtsi | 0 .../armada-388-clearfog-base.dts | 0 .../{ => marvell}/armada-388-clearfog-pro.dts | 0 .../dts/{ => marvell}/armada-388-clearfog.dts | 0 .../{ => marvell}/armada-388-clearfog.dtsi | 0 .../boot/dts/{ => marvell}/armada-388-db.dts | 0 .../boot/dts/{ => marvell}/armada-388-gp.dts | 0 .../dts/{ => marvell}/armada-388-helios4.dts | 0 .../boot/dts/{ => marvell}/armada-388-rd.dts | 0 .../boot/dts/{ => marvell}/armada-388.dtsi | 0 .../armada-38x-solidrun-microsom.dtsi | 0 .../boot/dts/{ => marvell}/armada-38x.dtsi | 0 .../boot/dts/{ => marvell}/armada-390-db.dts | 0 .../boot/dts/{ => marvell}/armada-390.dtsi | 0 .../boot/dts/{ => marvell}/armada-395-gp.dts | 0 .../boot/dts/{ => marvell}/armada-395.dtsi | 0 .../boot/dts/{ => marvell}/armada-398-db.dts | 0 .../boot/dts/{ => marvell}/armada-398.dtsi | 0 .../boot/dts/{ => marvell}/armada-39x.dtsi | 0 .../dts/{ => marvell}/armada-xp-98dx3236.dtsi | 0 .../dts/{ => marvell}/armada-xp-98dx3336.dtsi | 0 .../dts/{ => marvell}/armada-xp-98dx4251.dtsi | 0 .../dts/{ => marvell}/armada-xp-axpwifiap.dts | 0 .../armada-xp-crs305-1g-4s-bit.dts | 0 .../{ => marvell}/armada-xp-crs305-1g-4s.dts | 0 .../{ => marvell}/armada-xp-crs305-1g-4s.dtsi | 0 .../armada-xp-crs326-24g-2s-bit.dts | 0 .../{ => marvell}/armada-xp-crs326-24g-2s.dts | 0 .../armada-xp-crs326-24g-2s.dtsi | 0 .../armada-xp-crs328-4c-20s-4s-bit.dts | 0 .../armada-xp-crs328-4c-20s-4s.dts | 0 .../armada-xp-crs328-4c-20s-4s.dtsi | 0 .../dts/{ => marvell}/armada-xp-db-dxbc2.dts | 0 .../{ => marvell}/armada-xp-db-xc3-24g4xg.dts | 0 .../boot/dts/{ => marvell}/armada-xp-db.dts | 0 .../boot/dts/{ => marvell}/armada-xp-gp.dts | 0 .../armada-xp-lenovo-ix4-300d.dts | 0 .../{ => marvell}/armada-xp-linksys-mamba.dts | 0 .../dts/{ => marvell}/armada-xp-matrix.dts | 0 .../dts/{ => marvell}/armada-xp-mv78230.dtsi | 0 .../dts/{ => marvell}/armada-xp-mv78260.dtsi | 0 .../dts/{ => marvell}/armada-xp-mv78460.dtsi | 0 .../armada-xp-netgear-rn2120.dts | 0 .../armada-xp-openblocks-ax3-4.dts | 0 .../armada-xp-synology-ds414.dts | 0 .../arm/boot/dts/{ => marvell}/armada-xp.dtsi | 0 .../boot/dts/{ => marvell}/dove-cm-a510.dtsi | 0 .../boot/dts/{ => marvell}/dove-cubox-es.dts | 0 .../arm/boot/dts/{ => marvell}/dove-cubox.dts | 0 .../boot/dts/{ => marvell}/dove-d2plug.dts | 0 .../boot/dts/{ => marvell}/dove-d3plug.dts | 0 .../boot/dts/{ => marvell}/dove-dove-db.dts | 0 .../boot/dts/{ => marvell}/dove-sbc-a510.dts | 0 arch/arm/boot/dts/{ => marvell}/dove.dtsi | 0 .../{ => marvell}/kirkwood-4i-edge-200.dts | 0 .../boot/dts/{ => marvell}/kirkwood-6192.dtsi | 0 .../boot/dts/{ => marvell}/kirkwood-6281.dtsi | 0 .../boot/dts/{ => marvell}/kirkwood-6282.dtsi | 0 .../dts/{ => marvell}/kirkwood-98dx4122.dtsi | 0 .../boot/dts/{ => marvell}/kirkwood-b3.dts | 0 .../kirkwood-blackarmor-nas220.dts | 0 .../dts/{ => marvell}/kirkwood-c200-v1.dts | 0 .../dts/{ => marvell}/kirkwood-cloudbox.dts | 0 .../boot/dts/{ => marvell}/kirkwood-d2net.dts | 0 .../dts/{ => marvell}/kirkwood-db-88f6281.dts | 0 .../dts/{ => marvell}/kirkwood-db-88f6282.dts | 0 .../boot/dts/{ => marvell}/kirkwood-db.dtsi | 0 .../dts/{ => marvell}/kirkwood-dir665.dts | 0 .../dts/{ => marvell}/kirkwood-dns320.dts | 0 .../dts/{ => marvell}/kirkwood-dns325.dts | 0 .../dts/{ => marvell}/kirkwood-dnskw.dtsi | 0 .../dts/{ => marvell}/kirkwood-dockstar.dts | 0 .../dts/{ => marvell}/kirkwood-dreamplug.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds109.dts | 0 .../dts/{ => marvell}/kirkwood-ds110jv10.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds111.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds112.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds209.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds210.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds212.dts | 0 .../dts/{ => marvell}/kirkwood-ds212j.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds409.dts | 0 .../dts/{ => marvell}/kirkwood-ds409slim.dts | 0 .../boot/dts/{ => marvell}/kirkwood-ds411.dts | 0 .../dts/{ => marvell}/kirkwood-ds411j.dts | 0 .../dts/{ => marvell}/kirkwood-ds411slim.dts | 0 .../dts/{ => marvell}/kirkwood-goflexnet.dts | 0 .../kirkwood-guruplug-server-plus.dts | 0 .../dts/{ => marvell}/kirkwood-ib62x0.dts | 0 .../dts/{ => marvell}/kirkwood-iconnect.dts | 0 .../{ => marvell}/kirkwood-iomega_ix2_200.dts | 0 .../boot/dts/{ => marvell}/kirkwood-is2.dts | 0 .../dts/{ => marvell}/kirkwood-km_common.dtsi | 0 .../{ => marvell}/kirkwood-km_fixedeth.dts | 0 .../{ => marvell}/kirkwood-km_kirkwood.dts | 0 .../boot/dts/{ => marvell}/kirkwood-l-50.dts | 0 .../dts/{ => marvell}/kirkwood-laplug.dts | 0 .../kirkwood-linkstation-6282.dtsi | 0 .../kirkwood-linkstation-duo-6281.dtsi | 0 .../kirkwood-linkstation-lsqvl.dts | 0 .../kirkwood-linkstation-lsvl.dts | 0 .../kirkwood-linkstation-lswsxl.dts | 0 .../kirkwood-linkstation-lswvl.dts | 0 .../kirkwood-linkstation-lswxl.dts | 0 .../{ => marvell}/kirkwood-linkstation.dtsi | 0 .../{ => marvell}/kirkwood-linksys-viper.dts | 0 .../dts/{ => marvell}/kirkwood-lschlv2.dts | 0 .../boot/dts/{ => marvell}/kirkwood-lsxhl.dts | 0 .../boot/dts/{ => marvell}/kirkwood-lsxl.dtsi | 0 .../dts/{ => marvell}/kirkwood-mplcec4.dts | 0 .../kirkwood-mv88f6281gtw-ge.dts | 0 .../dts/{ => marvell}/kirkwood-nas2big.dts | 0 .../dts/{ => marvell}/kirkwood-net2big.dts | 0 .../dts/{ => marvell}/kirkwood-net5big.dts | 0 .../kirkwood-netgear_readynas_duo_v2.dts | 0 .../kirkwood-netgear_readynas_nv+_v2.dts | 0 .../dts/{ => marvell}/kirkwood-netxbig.dtsi | 0 .../{ => marvell}/kirkwood-ns2-common.dtsi | 0 .../boot/dts/{ => marvell}/kirkwood-ns2.dts | 0 .../dts/{ => marvell}/kirkwood-ns2lite.dts | 0 .../dts/{ => marvell}/kirkwood-ns2max.dts | 0 .../dts/{ => marvell}/kirkwood-ns2mini.dts | 0 .../dts/{ => marvell}/kirkwood-nsa310.dts | 0 .../dts/{ => marvell}/kirkwood-nsa310a.dts | 0 .../dts/{ => marvell}/kirkwood-nsa310s.dts | 0 .../dts/{ => marvell}/kirkwood-nsa320.dts | 0 .../dts/{ => marvell}/kirkwood-nsa325.dts | 0 .../{ => marvell}/kirkwood-nsa3x0-common.dtsi | 0 .../{ => marvell}/kirkwood-openblocks_a6.dts | 0 .../{ => marvell}/kirkwood-openblocks_a7.dts | 0 .../{ => marvell}/kirkwood-openrd-base.dts | 0 .../{ => marvell}/kirkwood-openrd-client.dts | 0 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=> marvell}/orion5x-rd88f5182-nas.dts | 0 arch/arm/boot/dts/{ => marvell}/orion5x.dtsi | 0 .../dts/{ => marvell}/pxa168-aspenite.dts | 0 arch/arm/boot/dts/{ => marvell}/pxa168.dtsi | 0 .../arm/boot/dts/{ => marvell}/pxa910-dkb.dts | 0 arch/arm/boot/dts/{ => marvell}/pxa910.dtsi | 0 arch/arm/boot/dts/mediatek/Makefile | 15 + .../boot/dts/{ => mediatek}/mt2701-evb.dts | 0 .../boot/dts/{ => mediatek}/mt2701-pinfunc.h | 0 arch/arm/boot/dts/{ => mediatek}/mt2701.dtsi | 0 arch/arm/boot/dts/{ => mediatek}/mt6323.dtsi | 0 .../boot/dts/{ => mediatek}/mt6580-evbp1.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt6580.dtsi | 0 .../mt6582-prestigio-pmt5008-3g.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt6582.dtsi | 0 .../dts/{ => mediatek}/mt6589-aquaris5.dts | 0 .../{ => mediatek}/mt6589-fairphone-fp1.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt6589.dtsi | 0 .../boot/dts/{ => mediatek}/mt6592-evb.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt6592.dtsi | 0 arch/arm/boot/dts/{ => mediatek}/mt7623.dtsi | 0 .../dts/{ => mediatek}/mt7623a-rfb-emmc.dts | 0 .../dts/{ => mediatek}/mt7623a-rfb-nand.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt7623a.dtsi | 0 .../mt7623n-bananapi-bpi-r2.dts | 0 .../dts/{ => mediatek}/mt7623n-rfb-emmc.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt7623n.dtsi | 0 .../boot/dts/{ => mediatek}/mt7629-rfb.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt7629.dtsi | 0 .../boot/dts/{ => mediatek}/mt8127-moose.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt8127.dtsi | 0 .../boot/dts/{ => mediatek}/mt8135-evbp1.dts | 0 arch/arm/boot/dts/{ => mediatek}/mt8135.dtsi | 0 arch/arm/boot/dts/microchip/Makefile | 108 + arch/arm/boot/dts/{ => microchip}/aks-cdu.dts | 0 .../boot/dts/{ => microchip}/animeo_ip.dts | 0 .../boot/dts/{ => microchip}/at91-ariag25.dts | 0 .../dts/{ => microchip}/at91-ariettag25.dts | 0 .../boot/dts/{ => microchip}/at91-cosino.dtsi | 0 .../{ => microchip}/at91-cosino_mega2560.dts | 0 .../dts/{ => microchip}/at91-dvk_som60.dts | 0 .../{ => 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.../dts/{ => microchip}/sama5d3xmb_cmp.dtsi | 0 .../dts/{ => microchip}/sama5d3xmb_emac.dtsi | 0 .../dts/{ => microchip}/sama5d3xmb_gmac.dtsi | 0 .../arm/boot/dts/{ => microchip}/sama5d4.dtsi | 0 .../dts/{ => microchip}/sama7g5-pinfunc.h | 0 .../arm/boot/dts/{ => microchip}/sama7g5.dtsi | 0 .../boot/dts/{ => microchip}/tny_a9260.dts | 0 .../dts/{ => microchip}/tny_a9260_common.dtsi | 0 .../boot/dts/{ => microchip}/tny_a9263.dts | 0 .../boot/dts/{ => microchip}/tny_a9g20.dts | 0 .../boot/dts/{ => microchip}/usb_a9260.dts | 0 .../dts/{ => microchip}/usb_a9260_common.dtsi | 0 .../boot/dts/{ => microchip}/usb_a9263.dts | 0 .../{ => microchip}/usb_a9g20-dab-mmx.dtsi | 0 .../boot/dts/{ => microchip}/usb_a9g20.dts | 0 .../dts/{ => microchip}/usb_a9g20_common.dtsi | 0 .../dts/{ => microchip}/usb_a9g20_lpw.dts | 0 arch/arm/boot/dts/moxa/Makefile | 3 + .../boot/dts/{ => moxa}/moxart-uc7112lx.dts | 0 arch/arm/boot/dts/{ => moxa}/moxart.dtsi | 0 arch/arm/boot/dts/nspire/Makefile | 5 + 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=> nvidia}/tegra30-colibri.dtsi | 0 .../tegra30-cpu-opp-microvolt.dtsi | 0 .../dts/{ => nvidia}/tegra30-cpu-opp.dtsi | 0 .../boot/dts/{ => nvidia}/tegra30-ouya.dts | 0 .../{ => nvidia}/tegra30-pegatron-chagall.dts | 0 .../{ => nvidia}/tegra30-peripherals-opp.dtsi | 0 arch/arm/boot/dts/{ => nvidia}/tegra30.dtsi | 0 arch/arm/boot/dts/nxp/Makefile | 6 + arch/arm/boot/dts/nxp/imx/Makefile | 388 ++++ arch/arm/boot/dts/{ => nxp/imx}/e60k02.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/e70k02.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx1-ads.dts | 0 .../boot/dts/{ => nxp/imx}/imx1-apf9328.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx1-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx1.dtsi | 0 .../{ => nxp/imx}/imx25-eukrea-cpuimx25.dtsi | 0 ...25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts | 0 ...25-eukrea-mbimxsd25-baseboard-dvi-svga.dts | 0 ...x25-eukrea-mbimxsd25-baseboard-dvi-vga.dts | 0 .../imx}/imx25-eukrea-mbimxsd25-baseboard.dts | 0 .../dts/{ => nxp/imx}/imx25-karo-tx25.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx25-pdk.dts | 0 .../boot/dts/{ => nxp/imx}/imx25-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx25.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx27-apf27.dts | 0 .../boot/dts/{ => nxp/imx}/imx27-apf27dev.dts | 0 .../{ => nxp/imx}/imx27-eukrea-cpuimx27.dtsi | 0 .../imx}/imx27-eukrea-mbimxsd27-baseboard.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx27-pdk.dts | 0 .../imx}/imx27-phytec-phycard-s-rdk.dts | 0 .../imx}/imx27-phytec-phycard-s-som.dtsi | 0 .../imx}/imx27-phytec-phycore-rdk.dts | 0 .../imx}/imx27-phytec-phycore-som.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx27-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx27.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx31-bug.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx31-lite.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx31.dtsi | 0 .../{ => nxp/imx}/imx35-eukrea-cpuimx35.dtsi | 0 .../imx}/imx35-eukrea-mbimxsd35-baseboard.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx35-pdk.dts | 0 .../boot/dts/{ => nxp/imx}/imx35-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx35.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx50-evk.dts | 0 .../dts/{ => nxp/imx}/imx50-kobo-aura.dts | 0 .../boot/dts/{ => nxp/imx}/imx50-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx50.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx51-apf51.dts | 0 .../boot/dts/{ => nxp/imx}/imx51-apf51dev.dts | 0 .../boot/dts/{ => nxp/imx}/imx51-babbage.dts | 0 .../imx}/imx51-digi-connectcore-jsk.dts | 0 .../imx}/imx51-digi-connectcore-som.dtsi | 0 .../{ => nxp/imx}/imx51-eukrea-cpuimx51.dtsi | 0 .../imx}/imx51-eukrea-mbimxsd51-baseboard.dts | 0 .../boot/dts/{ => nxp/imx}/imx51-pinfunc.h | 0 .../boot/dts/{ => nxp/imx}/imx51-ts4800.dts | 0 .../boot/dts/{ => nxp/imx}/imx51-zii-rdu1.dts | 0 .../dts/{ => nxp/imx}/imx51-zii-scu2-mezz.dts | 0 .../dts/{ => nxp/imx}/imx51-zii-scu3-esb.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx51.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53-ard.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-cx9020.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-kp-ddc.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-kp-hsc.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53-kp.dtsi | 0 .../arm/boot/dts/{ => nxp/imx}/imx53-m53.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx53-m53evk.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-m53menlo.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-mba53.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53-ppd.dts | 0 .../dts/{ => nxp/imx}/imx53-qsb-common.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53-qsb.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx53-qsrb.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-sk-imx53.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53-smd.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-tqma53.dtsi | 0 .../dts/{ => nxp/imx}/imx53-tx53-x03x.dts | 0 .../dts/{ => nxp/imx}/imx53-tx53-x13x.dts | 0 .../boot/dts/{ => nxp/imx}/imx53-tx53.dtsi | 0 .../dts/{ => nxp/imx}/imx53-usbarmory.dts | 0 .../dts/{ => nxp/imx}/imx53-voipac-bsb.dts | 0 .../{ => nxp/imx}/imx53-voipac-dmm-668.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx53.dtsi | 0 .../{ => nxp/imx}/imx6-logicpd-baseboard.dtsi | 0 .../dts/{ => nxp/imx}/imx6-logicpd-som.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-alti6p.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-apf6dev.dts | 0 .../{ => nxp/imx}/imx6dl-aristainetos2_4.dts | 0 .../{ => nxp/imx}/imx6dl-aristainetos2_7.dts | 0 .../{ => nxp/imx}/imx6dl-aristainetos_4.dts | 0 .../{ => nxp/imx}/imx6dl-aristainetos_7.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b105pv2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b105v2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b125pv2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b125v2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b155v2.dts | 0 .../dts/{ => nxp/imx}/imx6dl-b1x5pv2.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-b1x5v2.dtsi | 0 .../{ => nxp/imx}/imx6dl-colibri-aster.dts | 0 .../{ => nxp/imx}/imx6dl-colibri-eval-v3.dts | 0 .../{ => nxp/imx}/imx6dl-colibri-iris-v2.dts | 0 .../dts/{ => nxp/imx}/imx6dl-colibri-iris.dts | 0 .../imx}/imx6dl-cubox-i-emmc-som-v15.dts | 0 .../{ => nxp/imx}/imx6dl-cubox-i-som-v15.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-cubox-i.dts | 0 .../{ => nxp/imx}/imx6dl-dfi-fs700-m60.dts | 0 .../{ => nxp/imx}/imx6dl-dhcom-picoitx.dts | 0 .../{ => nxp/imx}/imx6dl-eckelmann-ci4x10.dts | 0 .../dts/{ => nxp/imx}/imx6dl-emcon-avari.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw51xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw52xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw53xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw54xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw551x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw552x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw553x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw560x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5903.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5904.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5907.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5910.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5912.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-gw5913.dts | 0 .../imx}/imx6dl-hummingboard-emmc-som-v15.dts | 0 .../imx}/imx6dl-hummingboard-som-v15.dts | 0 .../dts/{ => nxp/imx}/imx6dl-hummingboard.dts | 0 .../imx6dl-hummingboard2-emmc-som-v15.dts | 0 .../imx}/imx6dl-hummingboard2-som-v15.dts | 0 .../{ => nxp/imx}/imx6dl-hummingboard2.dts | 0 .../dts/{ => nxp/imx}/imx6dl-icore-mipi.dts | 0 .../dts/{ => nxp/imx}/imx6dl-icore-rqs.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-icore.dts | 0 .../{ => nxp/imx}/imx6dl-kontron-samx6i.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-lanmcu.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-mamoj.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-mba6.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-mba6a.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-mba6b.dts | 0 .../dts/{ => nxp/imx}/imx6dl-nit6xlite.dts | 0 .../dts/{ => nxp/imx}/imx6dl-nitrogen6x.dts | 0 .../imx}/imx6dl-phytec-mira-rdk-nand.dts | 0 .../{ => nxp/imx}/imx6dl-phytec-pbab01.dts | 0 .../{ => nxp/imx}/imx6dl-phytec-pfla02.dtsi | 0 .../dts/{ => nxp/imx}/imx6dl-pico-dwarf.dts | 0 .../dts/{ => nxp/imx}/imx6dl-pico-hobbit.dts | 0 .../dts/{ => nxp/imx}/imx6dl-pico-nymph.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-pico-pi.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-pinfunc.h | 0 .../boot/dts/{ => nxp/imx}/imx6dl-plybas.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-plym2m.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-prtmvt.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-prtrvt.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-prtvt7.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-qmx6.dtsi | 0 .../dts/{ => nxp/imx}/imx6dl-rex-basic.dts | 0 .../dts/{ => nxp/imx}/imx6dl-riotboard.dts | 0 .../dts/{ => nxp/imx}/imx6dl-sabreauto.dts | 0 .../dts/{ => nxp/imx}/imx6dl-sabrelite.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-sabresd.dts | 0 .../dts/{ => nxp/imx}/imx6dl-savageboard.dts | 0 .../{ => nxp/imx}/imx6dl-skov-revc-lt2.dts | 0 .../{ => nxp/imx}/imx6dl-skov-revc-lt6.dts | 0 .../dts/{ => nxp/imx}/imx6dl-solidsense.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-tqma6a.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-tqma6b.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6dl-ts4900.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-ts7970.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6dl-comtft.dts | 0 .../{ => nxp/imx}/imx6dl-tx6s-8034-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6s-8034.dts | 0 .../{ => nxp/imx}/imx6dl-tx6s-8035-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6s-8035.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6u-801x.dts | 0 .../{ => nxp/imx}/imx6dl-tx6u-8033-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6u-8033.dts | 0 .../{ => nxp/imx}/imx6dl-tx6u-80xx-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6dl-tx6u-811x.dts | 0 .../{ => nxp/imx}/imx6dl-tx6u-81xx-mb7.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-udoo.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-victgo.dts | 0 .../boot/dts/{ => nxp/imx}/imx6dl-vicut1.dts | 0 .../{ => nxp/imx}/imx6dl-wandboard-revb1.dts | 0 .../{ => nxp/imx}/imx6dl-wandboard-revd1.dts | 0 .../dts/{ => nxp/imx}/imx6dl-wandboard.dts | 0 .../{ => nxp/imx}/imx6dl-yapp4-common.dtsi | 0 .../dts/{ => nxp/imx}/imx6dl-yapp4-draco.dts | 0 .../dts/{ => nxp/imx}/imx6dl-yapp4-hydra.dts | 0 .../dts/{ => nxp/imx}/imx6dl-yapp4-lynx.dts | 0 .../dts/{ => nxp/imx}/imx6dl-yapp4-orion.dts | 0 .../{ => nxp/imx}/imx6dl-yapp4-phoenix.dts | 0 .../dts/{ => nxp/imx}/imx6dl-yapp4-ursa.dts | 0 .../{ => nxp/imx}/imx6dl-yapp43-common.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6dl.dtsi | 0 .../dts/{ => nxp/imx}/imx6q-apalis-eval.dts | 0 .../{ => nxp/imx}/imx6q-apalis-ixora-v1.1.dts | 0 .../{ => nxp/imx}/imx6q-apalis-ixora-v1.2.dts | 0 .../dts/{ => nxp/imx}/imx6q-apalis-ixora.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-apf6dev.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx6q-arm2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-b450v3.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-b650v3.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-b850v3.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-ba16.dtsi | 0 .../dts/{ => nxp/imx}/imx6q-bosch-acc.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-bx50v3.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-cm-fx6.dts | 0 .../imx}/imx6q-cubox-i-emmc-som-v15.dts | 0 .../{ => nxp/imx}/imx6q-cubox-i-som-v15.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-cubox-i.dts | 0 .../dts/{ => nxp/imx}/imx6q-dfi-fs700-m60.dts | 0 .../dts/{ => nxp/imx}/imx6q-dhcom-pdk2.dts | 0 .../imx6q-display5-tianma-tm070-1280x768.dts | 0 .../dts/{ => nxp/imx}/imx6q-display5.dtsi | 0 .../dts/{ => nxp/imx}/imx6q-dmo-edmqmx6.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-dms-ba16.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6q-ds.dts | 0 .../dts/{ => nxp/imx}/imx6q-emcon-avari.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6q-evi.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gk802.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw51xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw52xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw53xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5400-a.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw54xx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw551x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw552x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw553x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw560x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5903.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5904.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5907.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5910.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5912.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-gw5913.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx6q-h100.dts | 0 .../imx}/imx6q-hummingboard-emmc-som-v15.dts | 0 .../imx}/imx6q-hummingboard-som-v15.dts | 0 .../dts/{ => nxp/imx}/imx6q-hummingboard.dts | 0 .../imx}/imx6q-hummingboard2-emmc-som-v15.dts | 0 .../imx}/imx6q-hummingboard2-som-v15.dts | 0 .../dts/{ => nxp/imx}/imx6q-hummingboard2.dts | 0 .../dts/{ => nxp/imx}/imx6q-icore-mipi.dts | 0 .../dts/{ => nxp/imx}/imx6q-icore-ofcap10.dts | 0 .../dts/{ => nxp/imx}/imx6q-icore-ofcap12.dts | 0 .../dts/{ => nxp/imx}/imx6q-icore-rqs.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-icore.dts | 0 .../{ => nxp/imx}/imx6q-kontron-samx6i.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-kp-tpc.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6q-kp.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-logicpd.dts | 0 .../dts/{ => nxp/imx}/imx6q-marsboard.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-mba6.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-mba6a.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-mba6b.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-mccmon6.dts | 0 .../dts/{ => nxp/imx}/imx6q-nitrogen6_max.dts | 0 .../{ => nxp/imx}/imx6q-nitrogen6_som2.dts | 0 .../dts/{ => nxp/imx}/imx6q-nitrogen6x.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-novena.dts | 0 .../imx}/imx6q-phytec-mira-rdk-emmc.dts | 0 .../imx}/imx6q-phytec-mira-rdk-nand.dts | 0 .../dts/{ => nxp/imx}/imx6q-phytec-pbab01.dts | 0 .../{ => nxp/imx}/imx6q-phytec-pfla02.dtsi | 0 .../dts/{ => nxp/imx}/imx6q-pico-dwarf.dts | 0 .../dts/{ => nxp/imx}/imx6q-pico-hobbit.dts | 0 .../dts/{ => nxp/imx}/imx6q-pico-nymph.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-pico-pi.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-pinfunc.h | 0 .../dts/{ => nxp/imx}/imx6q-pistachio.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-prti6q.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-prtwd2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-rex-pro.dts | 0 .../dts/{ => nxp/imx}/imx6q-sabreauto.dts | 0 .../dts/{ => nxp/imx}/imx6q-sabrelite.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-sabresd.dts | 0 .../dts/{ => nxp/imx}/imx6q-savageboard.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-sbc6x.dts | 0 .../dts/{ => nxp/imx}/imx6q-skov-revc-lt2.dts | 0 .../dts/{ => nxp/imx}/imx6q-skov-revc-lt6.dts | 0 .../imx}/imx6q-skov-reve-mi1010ait-1cp1.dts | 0 .../dts/{ => nxp/imx}/imx6q-solidsense.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-tbs2910.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-tqma6a.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-tqma6b.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6q-ts4900.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-ts7970.dts | 0 .../{ => nxp/imx}/imx6q-tx6q-1010-comtft.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-1010.dts | 0 .../{ => nxp/imx}/imx6q-tx6q-1020-comtft.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-1020.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-1036-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-1036.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-10x0-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-1110.dts | 0 .../dts/{ => nxp/imx}/imx6q-tx6q-11x0-mb7.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx6q-udoo.dts | 0 .../dts/{ => nxp/imx}/imx6q-utilite-pro.dts | 0 .../imx}/imx6q-var-dt6customboard.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-vicut1.dts | 0 .../{ => nxp/imx}/imx6q-wandboard-revb1.dts | 0 .../{ => nxp/imx}/imx6q-wandboard-revd1.dts | 0 .../dts/{ => nxp/imx}/imx6q-wandboard.dts | 0 .../dts/{ => nxp/imx}/imx6q-yapp4-crux.dts | 0 .../dts/{ => nxp/imx}/imx6q-yapp4-pegasus.dts | 0 .../boot/dts/{ => nxp/imx}/imx6q-zii-rdu2.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6q.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-apalis.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-apf6.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-apf6dev.dtsi | 0 .../{ => nxp/imx}/imx6qdl-aristainetos.dtsi | 0 .../{ => nxp/imx}/imx6qdl-aristainetos2.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-colibri.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-cubox-i.dtsi | 0 .../{ => nxp/imx}/imx6qdl-dfi-fs700-m60.dtsi | 0 .../{ => nxp/imx}/imx6qdl-dhcom-drc02.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-dhcom-pdk2.dtsi | 0 .../{ => nxp/imx}/imx6qdl-dhcom-picoitx.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-dhcom-som.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-ds.dtsi | 0 .../{ => nxp/imx}/imx6qdl-emcon-avari.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-emcon.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw51xx.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw52xx.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw53xx.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw54xx.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw551x.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw552x.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw553x.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw560x.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5903.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5904.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5907.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5910.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5912.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-gw5913.dtsi | 0 .../{ => nxp/imx}/imx6qdl-hummingboard.dtsi | 0 .../imx}/imx6qdl-hummingboard2-emmc.dtsi | 0 .../{ => nxp/imx}/imx6qdl-hummingboard2.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-icore-1.5.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-icore-rqs.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-icore.dtsi | 0 .../{ => nxp/imx}/imx6qdl-kontron-samx6i.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-mba6.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-mba6a.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-mba6b.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-nit6xlite.dtsi | 0 .../{ => nxp/imx}/imx6qdl-nitrogen6_max.dtsi | 0 .../{ => nxp/imx}/imx6qdl-nitrogen6_som2.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-nitrogen6x.dtsi | 0 .../imx}/imx6qdl-phytec-mira-peb-av-02.dtsi | 0 .../imx}/imx6qdl-phytec-mira-peb-eval-01.dtsi | 0 .../imx}/imx6qdl-phytec-mira-peb-wlbt-05.dtsi | 0 .../{ => nxp/imx}/imx6qdl-phytec-mira.dtsi | 0 .../{ => nxp/imx}/imx6qdl-phytec-pbab01.dtsi | 0 .../{ => nxp/imx}/imx6qdl-phytec-pfla02.dtsi | 0 .../imx}/imx6qdl-phytec-phycore-som.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-pico-dwarf.dtsi | 0 .../{ => nxp/imx}/imx6qdl-pico-hobbit.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-pico-nymph.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-pico-pi.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-pico.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-prti6q.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-rex.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-sabreauto.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-sabrelite.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-sabresd.dtsi | 0 .../{ => nxp/imx}/imx6qdl-savageboard.dtsi | 0 .../{ => nxp/imx}/imx6qdl-skov-cpu-revc.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-skov-cpu.dtsi | 0 .../{ => nxp/imx}/imx6qdl-skov-revc-lt2.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-solidsense.dtsi | 0 .../{ => nxp/imx}/imx6qdl-sr-som-brcm.dtsi | 0 .../{ => nxp/imx}/imx6qdl-sr-som-emmc.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-sr-som-ti.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-sr-som.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-tqma6.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-tqma6a.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-tqma6b.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-ts4900.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-ts7970.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-tx6-lcd.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-tx6-lvds.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-tx6-mb7.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-tx6.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qdl-udoo.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-var-dart.dtsi | 0 .../{ => nxp/imx}/imx6qdl-vicut1-12inch.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-vicut1.dtsi | 0 .../imx}/imx6qdl-wandboard-revb1.dtsi | 0 .../imx}/imx6qdl-wandboard-revc1.dtsi | 0 .../imx}/imx6qdl-wandboard-revd1.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-wandboard.dtsi | 0 .../dts/{ => nxp/imx}/imx6qdl-zii-rdu2.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6qdl.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6qp-mba6b.dts | 0 .../{ => nxp/imx}/imx6qp-nitrogen6_max.dts | 0 .../{ => nxp/imx}/imx6qp-nitrogen6_som2.dts | 0 .../imx}/imx6qp-phytec-mira-rdk-nand.dts | 0 .../boot/dts/{ => nxp/imx}/imx6qp-prtwd3.dts | 0 .../dts/{ => nxp/imx}/imx6qp-sabreauto.dts | 0 .../boot/dts/{ => nxp/imx}/imx6qp-sabresd.dts | 0 .../boot/dts/{ => nxp/imx}/imx6qp-tqma6b.dtsi | 0 .../{ => nxp/imx}/imx6qp-tx6qp-8037-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6qp-tx6qp-8037.dts | 0 .../{ => nxp/imx}/imx6qp-tx6qp-8137-mb7.dts | 0 .../dts/{ => nxp/imx}/imx6qp-tx6qp-8137.dts | 0 .../boot/dts/{ => nxp/imx}/imx6qp-vicutp.dts | 0 .../{ => nxp/imx}/imx6qp-wandboard-revd1.dts | 0 .../{ => nxp/imx}/imx6qp-yapp4-crux-plus.dts | 0 .../imx}/imx6qp-yapp4-pegasus-plus.dts | 0 .../dts/{ => nxp/imx}/imx6qp-zii-rdu2.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6qp.dtsi | 0 .../dts/{ => nxp/imx}/imx6s-dhcom-drc02.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx6sl-evk.dts | 0 .../dts/{ => nxp/imx}/imx6sl-kobo-aura2.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sl-pinfunc.h | 0 .../{ => nxp/imx}/imx6sl-tolino-shine2hd.dts | 0 .../{ => nxp/imx}/imx6sl-tolino-shine3.dts | 0 .../{ => nxp/imx}/imx6sl-tolino-vision.dts | 0 .../{ => nxp/imx}/imx6sl-tolino-vision5.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sl-warp.dts | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6sl.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6sll-evk.dts | 0 .../{ => nxp/imx}/imx6sll-kobo-clarahd.dts | 0 .../{ => nxp/imx}/imx6sll-kobo-librah2o.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sll-pinfunc.h | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6sll.dtsi | 0 .../dts/{ => nxp/imx}/imx6sx-nitrogen6sx.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sx-pinfunc.h | 0 .../dts/{ => nxp/imx}/imx6sx-sabreauto.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sx-sdb-mqs.dts | 0 .../dts/{ => nxp/imx}/imx6sx-sdb-reva.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sx-sdb-sai.dts | 0 .../arm/boot/dts/{ => nxp/imx}/imx6sx-sdb.dts | 0 .../boot/dts/{ => nxp/imx}/imx6sx-sdb.dtsi | 0 .../imx}/imx6sx-softing-vining-2000.dts | 0 .../{ => nxp/imx}/imx6sx-udoo-neo-basic.dts | 0 .../imx}/imx6sx-udoo-neo-extended.dts | 0 .../{ => nxp/imx}/imx6sx-udoo-neo-full.dts | 0 .../dts/{ => nxp/imx}/imx6sx-udoo-neo.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6sx.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-14x14-evk.dts | 0 .../dts/{ => nxp/imx}/imx6ul-14x14-evk.dtsi | 0 .../imx}/imx6ul-ccimx6ulsbcexpress.dts | 0 .../{ => nxp/imx}/imx6ul-ccimx6ulsbcpro.dts | 0 .../dts/{ => nxp/imx}/imx6ul-ccimx6ulsom.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6ul-geam.dts | 0 .../{ => nxp/imx}/imx6ul-imx6ull-opos6ul.dtsi | 0 .../imx}/imx6ul-imx6ull-opos6uldev.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-isiot-emmc.dts | 0 .../dts/{ => nxp/imx}/imx6ul-isiot-nand.dts | 0 .../boot/dts/{ => nxp/imx}/imx6ul-isiot.dtsi | 0 .../{ => nxp/imx}/imx6ul-kontron-bl-43.dts | 0 .../imx}/imx6ul-kontron-bl-common.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-kontron-bl.dts | 0 .../imx}/imx6ul-kontron-sl-common.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-kontron-sl.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-liteboard.dts | 0 .../dts/{ => nxp/imx}/imx6ul-litesom.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-opos6ul.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-opos6uldev.dts | 0 .../imx}/imx6ul-phytec-phycore-som.dtsi | 0 .../imx}/imx6ul-phytec-segin-ff-rdk-emmc.dts | 0 .../imx}/imx6ul-phytec-segin-ff-rdk-nand.dts | 0 .../imx}/imx6ul-phytec-segin-peb-av-02.dtsi | 0 .../imx}/imx6ul-phytec-segin-peb-eval-01.dtsi | 0 .../imx}/imx6ul-phytec-segin-peb-wlbt-05.dtsi | 0 .../{ => nxp/imx}/imx6ul-phytec-segin.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-pico-dwarf.dts | 0 .../dts/{ => nxp/imx}/imx6ul-pico-hobbit.dts | 0 .../boot/dts/{ => nxp/imx}/imx6ul-pico-pi.dts | 0 .../boot/dts/{ => nxp/imx}/imx6ul-pico.dtsi | 0 .../boot/dts/{ => nxp/imx}/imx6ul-pinfunc.h | 0 .../boot/dts/{ => nxp/imx}/imx6ul-prti6g.dts | 0 .../{ => nxp/imx}/imx6ul-tqma6ul-common.dtsi | 0 .../{ => nxp/imx}/imx6ul-tqma6ul1-mba6ulx.dts | 0 .../dts/{ => nxp/imx}/imx6ul-tqma6ul1.dtsi | 0 .../{ => nxp/imx}/imx6ul-tqma6ul2-mba6ulx.dts | 0 .../dts/{ => nxp/imx}/imx6ul-tqma6ul2.dtsi | 0 .../imx}/imx6ul-tqma6ul2l-mba6ulx.dts | 0 .../dts/{ => nxp/imx}/imx6ul-tqma6ul2l.dtsi | 0 .../{ => nxp/imx}/imx6ul-tqma6ulx-common.dtsi | 0 .../imx}/imx6ul-tqma6ulxl-common.dtsi | 0 .../dts/{ => nxp/imx}/imx6ul-tx6ul-0010.dts | 0 .../dts/{ => nxp/imx}/imx6ul-tx6ul-0011.dts | 0 .../{ => nxp/imx}/imx6ul-tx6ul-mainboard.dts | 0 .../boot/dts/{ => nxp/imx}/imx6ul-tx6ul.dtsi | 0 arch/arm/boot/dts/{ => nxp/imx}/imx6ul.dtsi | 0 .../dts/{ => nxp/imx}/imx6ull-14x14-evk.dts | 0 .../{ => nxp/imx}/imx6ull-colibri-aster.dts | 0 .../{ => nxp/imx}/imx6ull-colibri-aster.dtsi | 0 .../imx}/imx6ull-colibri-emmc-aster.dts | 0 .../imx}/imx6ull-colibri-emmc-eval-v3.dts | 0 .../imx}/imx6ull-colibri-emmc-iris-v2.dts | 0 .../imx}/imx6ull-colibri-emmc-iris.dts | 0 .../imx}/imx6ull-colibri-emmc-nonwifi.dtsi | 0 .../{ => nxp/imx}/imx6ull-colibri-eval-v3.dts | 0 .../imx}/imx6ull-colibri-eval-v3.dtsi | 0 .../{ => nxp/imx}/imx6ull-colibri-iris-v2.dts | 0 .../imx}/imx6ull-colibri-iris-v2.dtsi | 0 .../{ => nxp/imx}/imx6ull-colibri-iris.dts | 0 .../{ => nxp/imx}/imx6ull-colibri-iris.dtsi | 0 .../imx}/imx6ull-colibri-nonwifi.dtsi | 0 .../imx}/imx6ull-colibri-wifi-aster.dts | 0 .../imx}/imx6ull-colibri-wifi-eval-v3.dts | 0 .../imx}/imx6ull-colibri-wifi-iris-v2.dts | 0 .../imx}/imx6ull-colibri-wifi-iris.dts | 0 .../{ => nxp/imx}/imx6ull-colibri-wifi.dtsi | 0 .../dts/{ => nxp/imx}/imx6ull-colibri.dtsi | 0 .../dts/{ => nxp/imx}/imx6ull-dhcom-drc02.dts | 0 .../dts/{ => nxp/imx}/imx6ull-dhcom-pdk2.dts | 0 .../{ => nxp/imx}/imx6ull-dhcom-picoitx.dts | 0 .../imx}/imx6ull-dhcom-som-cfg-sdcard.dtsi | 0 .../dts/{ => nxp/imx}/imx6ull-dhcom-som.dtsi | 0 .../{ => nxp/imx}/imx6ull-dhcor-maveo-box.dts | 0 .../dts/{ => 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renesas}/r8a7740-armadillo800eva.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7740.dtsi | 0 .../r8a7742-iwg21d-q7-dbcm-ca.dts | 0 .../r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi | 0 .../r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi | 0 .../dts/{ => renesas}/r8a7742-iwg21d-q7.dts | 0 .../dts/{ => renesas}/r8a7742-iwg21m.dtsi | 0 arch/arm/boot/dts/{ => renesas}/r8a7742.dtsi | 0 .../r8a7743-iwg20d-q7-dbcm-ca.dts | 0 .../dts/{ => renesas}/r8a7743-iwg20d-q7.dts | 0 .../dts/{ => renesas}/r8a7743-iwg20m.dtsi | 0 .../dts/{ => renesas}/r8a7743-sk-rzg1m.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7743.dtsi | 0 .../r8a7744-iwg20d-q7-dbcm-ca.dts | 0 .../dts/{ => renesas}/r8a7744-iwg20d-q7.dts | 0 .../dts/{ => renesas}/r8a7744-iwg20m.dtsi | 0 arch/arm/boot/dts/{ => renesas}/r8a7744.dtsi | 0 .../r8a7745-iwg22d-sodimm-dbhd-ca.dts | 0 .../{ => renesas}/r8a7745-iwg22d-sodimm.dts | 0 .../dts/{ => renesas}/r8a7745-iwg22m.dtsi | 0 .../dts/{ => renesas}/r8a7745-sk-rzg1e.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7745.dtsi | 0 .../dts/{ => renesas}/r8a77470-iwg23s-sbc.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a77470.dtsi | 0 .../boot/dts/{ => renesas}/r8a7778-bockw.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7778.dtsi | 0 .../boot/dts/{ => renesas}/r8a7779-marzen.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7779.dtsi | 0 .../boot/dts/{ => renesas}/r8a7790-lager.dts | 0 .../boot/dts/{ => renesas}/r8a7790-stout.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7790.dtsi | 0 .../dts/{ => renesas}/r8a7791-koelsch.dts | 0 .../boot/dts/{ => renesas}/r8a7791-porter.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7791.dtsi | 0 .../dts/{ => renesas}/r8a7792-blanche.dts | 0 .../boot/dts/{ => renesas}/r8a7792-wheat.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7792.dtsi | 0 .../boot/dts/{ => renesas}/r8a7793-gose.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7793.dtsi | 0 .../boot/dts/{ => renesas}/r8a7794-alt.dts | 0 .../boot/dts/{ => renesas}/r8a7794-silk.dts | 0 arch/arm/boot/dts/{ => renesas}/r8a7794.dtsi | 0 .../r8a77xx-aa121td01-panel.dtsi | 0 .../{ => renesas}/r9a06g032-rzn1d400-db.dts | 0 .../arm/boot/dts/{ => renesas}/r9a06g032.dtsi | 0 .../boot/dts/{ => renesas}/sh73a0-kzm9g.dts | 0 arch/arm/boot/dts/{ => renesas}/sh73a0.dtsi | 0 arch/arm/boot/dts/rockchip/Makefile | 42 + .../boot/dts/{ => rockchip}/rk3036-evb.dts | 0 .../boot/dts/{ => rockchip}/rk3036-kylin.dts | 0 arch/arm/boot/dts/{ => rockchip}/rk3036.dtsi | 0 .../dts/{ => rockchip}/rk3066a-bqcurie2.dts | 2 +- .../dts/{ => rockchip}/rk3066a-marsboard.dts | 2 +- .../boot/dts/{ => rockchip}/rk3066a-mk808.dts | 0 .../dts/{ => rockchip}/rk3066a-rayeager.dts | 2 +- arch/arm/boot/dts/{ => rockchip}/rk3066a.dtsi | 0 .../boot/dts/{ => rockchip}/rk3128-evb.dts | 0 arch/arm/boot/dts/{ => rockchip}/rk3128.dtsi | 0 .../dts/{ => rockchip}/rk3188-bqedison2qc.dts | 0 .../dts/{ => rockchip}/rk3188-px3-evb.dts | 0 .../dts/{ => rockchip}/rk3188-radxarock.dts | 0 arch/arm/boot/dts/{ => rockchip}/rk3188.dtsi | 0 .../boot/dts/{ => rockchip}/rk3228-evb.dts | 0 .../boot/dts/{ => rockchip}/rk3229-evb.dts | 0 .../boot/dts/{ => rockchip}/rk3229-xms6.dts | 0 arch/arm/boot/dts/{ => rockchip}/rk3229.dtsi | 0 arch/arm/boot/dts/{ => rockchip}/rk322x.dtsi | 0 .../dts/{ => rockchip}/rk3288-evb-act8846.dts | 0 .../dts/{ => rockchip}/rk3288-evb-rk808.dts | 0 .../boot/dts/{ => rockchip}/rk3288-evb.dtsi | 0 .../{ => rockchip}/rk3288-firefly-beta.dts | 0 .../rk3288-firefly-reload-core.dtsi | 0 .../{ => rockchip}/rk3288-firefly-reload.dts | 0 .../dts/{ => rockchip}/rk3288-firefly.dts | 0 .../dts/{ => rockchip}/rk3288-firefly.dtsi | 0 .../boot/dts/{ => rockchip}/rk3288-miqi.dts | 0 .../dts/{ => rockchip}/rk3288-phycore-rdk.dts | 0 .../{ => rockchip}/rk3288-phycore-som.dtsi | 0 .../dts/{ => rockchip}/rk3288-popmetal.dts | 0 .../boot/dts/{ => rockchip}/rk3288-r89.dts | 0 .../dts/{ => rockchip}/rk3288-rock-pi-n8.dts | 2 +- .../dts/{ => rockchip}/rk3288-rock2-som.dtsi | 0 .../{ => rockchip}/rk3288-rock2-square.dts | 0 .../dts/{ => rockchip}/rk3288-tinker-s.dts | 0 .../boot/dts/{ => rockchip}/rk3288-tinker.dts | 0 .../dts/{ => rockchip}/rk3288-tinker.dtsi | 0 .../rk3288-veyron-analog-audio.dtsi | 0 .../{ => rockchip}/rk3288-veyron-brain.dts | 0 .../rk3288-veyron-broadcom-bluetooth.dtsi | 0 .../rk3288-veyron-chromebook.dtsi | 2 +- .../dts/{ => rockchip}/rk3288-veyron-edp.dtsi | 0 .../{ => rockchip}/rk3288-veyron-fievel.dts | 0 .../dts/{ => rockchip}/rk3288-veyron-jaq.dts | 2 +- .../{ => rockchip}/rk3288-veyron-jerry.dts | 2 +- .../{ => rockchip}/rk3288-veyron-mickey.dts | 0 .../{ => rockchip}/rk3288-veyron-mighty.dts | 0 .../{ => rockchip}/rk3288-veyron-minnie.dts | 0 .../{ => rockchip}/rk3288-veyron-pinky.dts | 2 +- .../{ => rockchip}/rk3288-veyron-sdmmc.dtsi | 0 .../{ => rockchip}/rk3288-veyron-speedy.dts | 2 +- .../{ => rockchip}/rk3288-veyron-tiger.dts | 0 .../dts/{ => rockchip}/rk3288-veyron.dtsi | 0 .../dts/{ => rockchip}/rk3288-vmarc-som.dtsi | 0 .../boot/dts/{ => rockchip}/rk3288-vyasa.dts | 0 arch/arm/boot/dts/{ => rockchip}/rk3288.dtsi | 0 arch/arm/boot/dts/{ => rockchip}/rk3xxx.dtsi | 0 .../rockchip-radxa-dalang-carrier.dtsi | 0 .../dts/{ => rockchip}/rv1108-elgin-r1.dts | 0 .../boot/dts/{ => rockchip}/rv1108-evb.dts | 0 arch/arm/boot/dts/{ => rockchip}/rv1108.dtsi | 0 .../{ => rockchip}/rv1126-edgeble-neu2-io.dts | 0 .../{ => rockchip}/rv1126-edgeble-neu2.dtsi | 0 .../dts/{ => rockchip}/rv1126-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => rockchip}/rv1126.dtsi | 0 arch/arm/boot/dts/samsung/Makefile | 54 + .../exynos-mfc-reserved-memory.dtsi | 0 .../boot/dts/{ => samsung}/exynos-pinctrl.h | 0 .../{ => samsung}/exynos-syscon-restart.dtsi | 0 .../{ => samsung}/exynos3250-artik5-eval.dts | 0 .../dts/{ => samsung}/exynos3250-artik5.dtsi | 0 .../dts/{ => samsung}/exynos3250-monk.dts | 0 .../dts/{ => samsung}/exynos3250-pinctrl.dtsi | 0 .../dts/{ => samsung}/exynos3250-rinato.dts | 0 .../boot/dts/{ => samsung}/exynos3250.dtsi | 0 .../{ => samsung}/exynos4-cpu-thermal.dtsi | 0 arch/arm/boot/dts/{ => samsung}/exynos4.dtsi | 0 .../dts/{ => samsung}/exynos4210-i9100.dts | 0 .../dts/{ => samsung}/exynos4210-origen.dts | 0 .../dts/{ => samsung}/exynos4210-pinctrl.dtsi | 0 .../dts/{ => samsung}/exynos4210-smdkv310.dts | 0 .../dts/{ => samsung}/exynos4210-trats.dts | 0 .../exynos4210-universal_c210.dts | 0 .../boot/dts/{ => samsung}/exynos4210.dtsi | 0 .../boot/dts/{ => samsung}/exynos4212.dtsi | 0 .../{ => samsung}/exynos4412-galaxy-s3.dtsi | 0 .../dts/{ => samsung}/exynos4412-i9300.dts | 0 .../dts/{ => samsung}/exynos4412-i9305.dts | 0 .../{ => samsung}/exynos4412-itop-elite.dts | 0 .../exynos4412-itop-scp-core.dtsi | 0 .../dts/{ => samsung}/exynos4412-midas.dtsi | 0 .../dts/{ => samsung}/exynos4412-n710x.dts | 0 .../exynos4412-odroid-common.dtsi | 0 .../dts/{ => samsung}/exynos4412-odroidu3.dts | 0 .../dts/{ => samsung}/exynos4412-odroidx.dts | 0 .../dts/{ => samsung}/exynos4412-odroidx2.dts | 0 .../dts/{ => samsung}/exynos4412-origen.dts | 0 .../{ => samsung}/exynos4412-p4note-n8010.dts | 0 .../dts/{ => samsung}/exynos4412-p4note.dtsi | 0 .../{ => samsung}/exynos4412-ppmu-common.dtsi | 0 .../dts/{ => samsung}/exynos4412-prime.dtsi | 0 .../dts/{ => samsung}/exynos4412-smdk4412.dts | 0 .../dts/{ => samsung}/exynos4412-tiny4412.dts | 0 .../dts/{ => samsung}/exynos4412-trats2.dts | 0 .../boot/dts/{ => samsung}/exynos4412.dtsi | 0 .../dts/{ => samsung}/exynos4x12-pinctrl.dtsi | 0 .../boot/dts/{ => samsung}/exynos4x12.dtsi | 0 arch/arm/boot/dts/{ => samsung}/exynos5.dtsi | 0 .../dts/{ => samsung}/exynos5250-arndale.dts | 0 .../dts/{ => samsung}/exynos5250-pinctrl.dtsi | 0 .../dts/{ => samsung}/exynos5250-smdk5250.dts | 0 .../{ => samsung}/exynos5250-snow-common.dtsi | 2 +- .../{ => samsung}/exynos5250-snow-rev5.dts | 0 .../dts/{ => samsung}/exynos5250-snow.dts | 0 .../dts/{ => samsung}/exynos5250-spring.dts | 2 +- .../boot/dts/{ => samsung}/exynos5250.dtsi | 0 .../dts/{ => samsung}/exynos5260-pinctrl.dtsi | 0 .../{ => samsung}/exynos5260-xyref5260.dts | 0 .../boot/dts/{ => samsung}/exynos5260.dtsi | 0 .../dts/{ => samsung}/exynos5410-odroidxu.dts | 0 .../dts/{ => samsung}/exynos5410-pinctrl.dtsi | 0 .../dts/{ => samsung}/exynos5410-smdk5410.dts | 0 .../boot/dts/{ => samsung}/exynos5410.dtsi | 0 .../{ => samsung}/exynos5420-arndale-octa.dts | 0 .../{ => samsung}/exynos5420-chagall-wifi.dts | 0 .../dts/{ => samsung}/exynos5420-cpus.dtsi | 0 .../exynos5420-galaxy-tab-common.dtsi | 0 .../{ => samsung}/exynos5420-klimt-wifi.dts | 0 .../{ => samsung}/exynos5420-peach-pit.dts | 4 +- .../dts/{ => samsung}/exynos5420-pinctrl.dtsi | 0 .../dts/{ => samsung}/exynos5420-smdk5420.dts | 0 .../{ => samsung}/exynos5420-trip-points.dtsi | 0 .../boot/dts/{ => samsung}/exynos5420.dtsi | 0 .../dts/{ => samsung}/exynos5422-cpus.dtsi | 0 .../{ => samsung}/exynos5422-odroid-core.dtsi | 0 .../{ => samsung}/exynos5422-odroidhc1.dts | 0 .../exynos5422-odroidxu3-audio.dtsi | 0 .../exynos5422-odroidxu3-common.dtsi | 0 .../exynos5422-odroidxu3-lite.dts | 0 .../{ => samsung}/exynos5422-odroidxu3.dts | 0 .../{ => samsung}/exynos5422-odroidxu4.dts | 0 .../{ => samsung}/exynos5422-samsung-k3g.dts | 0 .../exynos54xx-odroidxu-leds.dtsi | 0 .../boot/dts/{ => samsung}/exynos54xx.dtsi | 0 .../dts/{ => samsung}/exynos5800-peach-pi.dts | 4 +- .../boot/dts/{ => samsung}/exynos5800.dtsi | 0 arch/arm/boot/dts/{ => samsung}/s3c6400.dtsi | 0 .../dts/{ => samsung}/s3c6410-mini6410.dts | 0 .../dts/{ => samsung}/s3c6410-smdk6410.dts | 0 arch/arm/boot/dts/{ => samsung}/s3c6410.dtsi | 0 .../dts/{ => samsung}/s3c64xx-pinctrl.dtsi | 0 .../boot/dts/{ => samsung}/s3c64xx-pinctrl.h | 0 arch/arm/boot/dts/{ => samsung}/s3c64xx.dtsi | 0 .../boot/dts/{ => samsung}/s5pv210-aquila.dts | 0 .../boot/dts/{ => samsung}/s5pv210-aries.dtsi | 0 .../dts/{ => samsung}/s5pv210-fascinate4g.dts | 0 .../dts/{ => samsung}/s5pv210-galaxys.dts | 0 .../boot/dts/{ => samsung}/s5pv210-goni.dts | 0 .../dts/{ => samsung}/s5pv210-pinctrl.dtsi | 0 .../boot/dts/{ => samsung}/s5pv210-pinctrl.h | 0 .../dts/{ => samsung}/s5pv210-smdkc110.dts | 0 .../dts/{ => samsung}/s5pv210-smdkv210.dts | 0 .../dts/{ => samsung}/s5pv210-torbreck.dts | 0 arch/arm/boot/dts/{ => samsung}/s5pv210.dtsi | 0 arch/arm/boot/dts/sigmastar/Makefile | 10 + .../mstar-infinity-breadbee-common.dtsi | 0 .../mstar-infinity-msc313-breadbee_crust.dts | 0 .../mstar-infinity-msc313.dtsi | 0 .../dts/{ => sigmastar}/mstar-infinity.dtsi | 0 .../mstar-infinity2m-ssd201-som2d01.dtsi | 0 ...nfinity2m-ssd202d-100ask-dongshanpione.dts | 0 .../mstar-infinity2m-ssd202d-miyoo-mini.dts | 0 .../mstar-infinity2m-ssd202d-ssd201htv2.dts | 0 .../mstar-infinity2m-ssd202d-unitv2.dts | 0 ...sd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts | 0 ...ity2m-ssd202d-wirelesstag-ido-som2d01.dtsi | 0 .../mstar-infinity2m-ssd202d.dtsi | 0 .../mstar-infinity2m-ssd20xd.dtsi | 0 .../dts/{ => sigmastar}/mstar-infinity2m.dtsi | 0 .../mstar-infinity3-msc313e-breadbee.dts | 0 .../mstar-infinity3-msc313e.dtsi | 0 .../dts/{ => sigmastar}/mstar-infinity3.dtsi | 0 .../mstar-mercury5-ssc8336n-midrived08.dts | 0 .../mstar-mercury5-ssc8336n.dtsi | 0 .../dts/{ => sigmastar}/mstar-mercury5.dtsi | 0 .../boot/dts/{ => sigmastar}/mstar-v7.dtsi | 0 arch/arm/boot/dts/socionext/Makefile | 13 + .../dts/{ => socionext}/milbeaut-m10v-evb.dts | 0 .../dts/{ => socionext}/milbeaut-m10v.dtsi | 0 .../dts/{ => socionext}/uniphier-ld4-ref.dts | 0 .../dts/{ => socionext}/uniphier-ld4.dtsi | 0 .../dts/{ => socionext}/uniphier-ld6b-ref.dts | 0 .../dts/{ => socionext}/uniphier-ld6b.dtsi | 0 .../dts/{ => socionext}/uniphier-pinctrl.dtsi | 0 .../dts/{ => socionext}/uniphier-pro4-ace.dts | 0 .../dts/{ => socionext}/uniphier-pro4-ref.dts | 0 .../{ => socionext}/uniphier-pro4-sanji.dts | 0 .../dts/{ => socionext}/uniphier-pro4.dtsi | 0 .../{ => socionext}/uniphier-pro5-epcore.dts | 0 .../{ => socionext}/uniphier-pro5-proex.dts | 0 .../dts/{ => socionext}/uniphier-pro5.dtsi | 0 .../{ => socionext}/uniphier-pxs2-gentil.dts | 0 .../{ => socionext}/uniphier-pxs2-vodka.dts | 0 .../dts/{ => socionext}/uniphier-pxs2.dtsi | 0 .../uniphier-ref-daughter.dtsi | 0 .../dts/{ => socionext}/uniphier-sld8-ref.dts | 0 .../dts/{ => socionext}/uniphier-sld8.dtsi | 0 .../uniphier-support-card.dtsi | 0 arch/arm/boot/dts/st/Makefile | 74 + arch/arm/boot/dts/{ => st}/spear1310-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear1310.dtsi | 0 arch/arm/boot/dts/{ => st}/spear1340-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear1340.dtsi | 0 arch/arm/boot/dts/{ => st}/spear13xx.dtsi | 0 arch/arm/boot/dts/{ => st}/spear300-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear300.dtsi | 0 arch/arm/boot/dts/{ => st}/spear310-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear310.dtsi | 0 arch/arm/boot/dts/{ => st}/spear320-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear320-hmi.dts | 0 arch/arm/boot/dts/{ => st}/spear320.dtsi | 0 arch/arm/boot/dts/{ => st}/spear320s.dtsi | 0 arch/arm/boot/dts/{ => st}/spear3xx.dtsi | 0 arch/arm/boot/dts/{ => st}/spear600-evb.dts | 0 arch/arm/boot/dts/{ => st}/spear600.dtsi | 0 arch/arm/boot/dts/{ => st}/st-pincfg.h | 0 arch/arm/boot/dts/{ => st}/ste-ab8500.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-ab8505.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-db8500.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-db8520.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-db9500.dtsi | 0 .../boot/dts/{ => st}/ste-dbx5x0-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-dbx5x0.dtsi | 0 .../boot/dts/{ => st}/ste-href-ab8500.dtsi | 0 .../dts/{ => st}/ste-href-family-pinctrl.dtsi | 0 .../arm/boot/dts/{ => st}/ste-href-stuib.dtsi | 0 .../dts/{ => st}/ste-href-tvk1281618-r2.dtsi | 0 .../dts/{ => st}/ste-href-tvk1281618-r3.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-href.dtsi | 0 .../arm/boot/dts/{ => st}/ste-href520-tvk.dts | 0 .../dts/{ => st}/ste-hrefprev60-stuib.dts | 0 .../boot/dts/{ => st}/ste-hrefprev60-tvk.dts | 0 .../arm/boot/dts/{ => st}/ste-hrefprev60.dtsi | 0 .../dts/{ => st}/ste-hrefv60plus-stuib.dts | 0 .../boot/dts/{ => st}/ste-hrefv60plus-tvk.dts | 0 .../boot/dts/{ => st}/ste-hrefv60plus.dtsi | 0 .../boot/dts/{ => st}/ste-nomadik-nhk15.dts | 0 .../dts/{ => st}/ste-nomadik-pinctrl.dtsi | 0 .../boot/dts/{ => st}/ste-nomadik-s8815.dts | 0 .../dts/{ => st}/ste-nomadik-stn8815.dtsi | 0 arch/arm/boot/dts/{ => st}/ste-snowball.dts | 0 .../{ => st}/ste-ux500-samsung-codina-tmo.dts | 0 .../dts/{ => st}/ste-ux500-samsung-codina.dts | 0 .../dts/{ => st}/ste-ux500-samsung-gavini.dts | 0 .../dts/{ => st}/ste-ux500-samsung-golden.dts | 0 .../dts/{ => st}/ste-ux500-samsung-janice.dts | 0 .../dts/{ => st}/ste-ux500-samsung-kyle.dts | 0 .../dts/{ => st}/ste-ux500-samsung-skomer.dts | 0 arch/arm/boot/dts/{ => st}/stih407-b2120.dts | 0 arch/arm/boot/dts/{ => st}/stih407-clock.dtsi | 0 .../arm/boot/dts/{ => st}/stih407-family.dtsi | 0 .../boot/dts/{ => st}/stih407-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stih407.dtsi | 0 arch/arm/boot/dts/{ => st}/stih410-b2120.dts | 0 arch/arm/boot/dts/{ => st}/stih410-b2260.dts | 0 arch/arm/boot/dts/{ => st}/stih410-clock.dtsi | 0 .../boot/dts/{ => st}/stih410-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stih410.dtsi | 0 arch/arm/boot/dts/{ => st}/stih418-b2199.dts | 0 arch/arm/boot/dts/{ => st}/stih418-b2264.dts | 0 arch/arm/boot/dts/{ => st}/stih418-clock.dtsi | 0 arch/arm/boot/dts/{ => st}/stih418.dtsi | 0 arch/arm/boot/dts/{ => st}/stihxxx-b2120.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32429i-eval.dts | 0 arch/arm/boot/dts/{ => st}/stm32746g-eval.dts | 0 .../boot/dts/{ => st}/stm32f4-pinctrl.dtsi | 0 .../arm/boot/dts/{ => st}/stm32f429-disco.dts | 0 .../boot/dts/{ => st}/stm32f429-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32f429.dtsi | 2 +- .../arm/boot/dts/{ => st}/stm32f469-disco.dts | 0 .../boot/dts/{ => st}/stm32f469-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32f469.dtsi | 0 .../boot/dts/{ => st}/stm32f7-pinctrl.dtsi | 0 .../arm/boot/dts/{ => st}/stm32f746-disco.dts | 0 .../boot/dts/{ => st}/stm32f746-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32f746.dtsi | 2 +- .../arm/boot/dts/{ => st}/stm32f769-disco.dts | 0 .../boot/dts/{ => st}/stm32f769-pinctrl.dtsi | 0 .../boot/dts/{ => st}/stm32h7-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32h743.dtsi | 2 +- .../boot/dts/{ => st}/stm32h743i-disco.dts | 0 .../arm/boot/dts/{ => st}/stm32h743i-eval.dts | 0 arch/arm/boot/dts/{ => st}/stm32h750.dtsi | 0 .../boot/dts/{ => st}/stm32h750i-art-pi.dts | 0 .../boot/dts/{ => st}/stm32mp13-pinctrl.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp131.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp133.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp135.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp135f-dk.dts | 0 arch/arm/boot/dts/{ => st}/stm32mp13xc.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp13xf.dtsi | 0 .../boot/dts/{ => st}/stm32mp15-pinctrl.dtsi | 0 .../arm/boot/dts/{ => st}/stm32mp15-scmi.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp151.dtsi | 0 .../{ => st}/stm32mp151a-dhcor-testbench.dts | 0 .../boot/dts/{ => st}/stm32mp151a-prtt1a.dts | 0 .../boot/dts/{ => st}/stm32mp151a-prtt1c.dts | 0 .../boot/dts/{ => st}/stm32mp151a-prtt1l.dtsi | 0 .../boot/dts/{ => st}/stm32mp151a-prtt1s.dts | 0 arch/arm/boot/dts/{ => st}/stm32mp153.dtsi | 0 .../dts/{ => st}/stm32mp153c-dhcom-drc02.dts | 0 .../stm32mp153c-dhcor-drc-compact.dts | 0 arch/arm/boot/dts/{ => st}/stm32mp157.dtsi | 0 .../dts/{ => st}/stm32mp157a-avenger96.dts | 0 .../{ => st}/stm32mp157a-dhcor-avenger96.dts | 0 .../dts/{ => st}/stm32mp157a-dk1-scmi.dts | 0 .../arm/boot/dts/{ => st}/stm32mp157a-dk1.dts | 0 ...tm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 0 .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 0 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 0 .../{ => st}/stm32mp157a-icore-stm32mp1.dtsi | 0 .../boot/dts/{ => st}/stm32mp157a-iot-box.dts | 0 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 0 ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 0 .../stm32mp157a-microgea-stm32mp1.dtsi | 0 .../dts/{ => st}/stm32mp157a-stinger96.dts | 0 .../dts/{ => st}/stm32mp157a-stinger96.dtsi | 0 .../dts/{ => st}/stm32mp157c-dhcom-pdk2.dts | 0 .../{ => st}/stm32mp157c-dhcom-picoitx.dts | 0 .../dts/{ => st}/stm32mp157c-dk2-scmi.dts | 0 .../arm/boot/dts/{ => st}/stm32mp157c-dk2.dts | 0 .../dts/{ => st}/stm32mp157c-ed1-scmi.dts | 0 .../arm/boot/dts/{ => st}/stm32mp157c-ed1.dts | 0 .../dts/{ => st}/stm32mp157c-emsbc-argon.dts | 0 .../{ => st}/stm32mp157c-emstamp-argon.dtsi | 0 .../dts/{ => st}/stm32mp157c-ev1-scmi.dts | 0 .../arm/boot/dts/{ => st}/stm32mp157c-ev1.dts | 0 .../boot/dts/{ => st}/stm32mp157c-lxa-mc1.dts | 0 .../dts/{ => st}/stm32mp157c-odyssey-som.dtsi | 0 .../boot/dts/{ => st}/stm32mp157c-odyssey.dts | 0 .../stm32mp157c-phycore-stm32mp1-3.dts | 0 .../stm32mp157c-phycore-stm32mp15-som.dtsi | 0 arch/arm/boot/dts/{ => st}/stm32mp15xc.dtsi | 0 .../dts/{ => st}/stm32mp15xx-dhcom-drc02.dtsi | 0 .../dts/{ => st}/stm32mp15xx-dhcom-pdk2.dtsi | 0 .../{ => st}/stm32mp15xx-dhcom-picoitx.dtsi | 0 .../dts/{ => st}/stm32mp15xx-dhcom-som.dtsi | 0 .../{ => st}/stm32mp15xx-dhcor-avenger96.dtsi | 0 .../stm32mp15xx-dhcor-drc-compact.dtsi | 0 .../dts/{ => st}/stm32mp15xx-dhcor-io1v8.dtsi | 0 .../dts/{ => st}/stm32mp15xx-dhcor-som.dtsi | 0 .../{ => st}/stm32mp15xx-dhcor-testbench.dtsi | 0 .../boot/dts/{ => st}/stm32mp15xx-dkx.dtsi | 0 .../boot/dts/{ => st}/stm32mp15xx-osd32.dtsi | 0 .../dts/{ => st}/stm32mp15xxaa-pinctrl.dtsi | 0 .../dts/{ => st}/stm32mp15xxab-pinctrl.dtsi | 0 .../dts/{ => st}/stm32mp15xxac-pinctrl.dtsi | 0 .../dts/{ => st}/stm32mp15xxad-pinctrl.dtsi | 0 arch/arm/boot/dts/sunplus/Makefile | 5 + .../{ => sunplus}/sunplus-sp7021-achip.dtsi | 0 .../{ => sunplus}/sunplus-sp7021-demo-v3.dts | 0 .../dts/{ => sunplus}/sunplus-sp7021.dtsi | 0 arch/arm/boot/dts/synaptics/Makefile | 6 + .../{ => synaptics}/berlin2-sony-nsz-gs7.dts | 0 .../arm/boot/dts/{ => synaptics}/berlin2.dtsi | 0 .../berlin2cd-google-chromecast.dts | 0 .../berlin2cd-valve-steamlink.dts | 0 .../boot/dts/{ => synaptics}/berlin2cd.dtsi | 0 .../{ => synaptics}/berlin2q-marvell-dmp.dts | 0 .../boot/dts/{ => synaptics}/berlin2q.dtsi | 0 arch/arm/boot/dts/ti/Makefile | 4 + arch/arm/boot/dts/ti/davinci/Makefile | 6 + .../dts/{ => ti/davinci}/da850-enbw-cmc.dts | 0 .../boot/dts/{ => ti/davinci}/da850-evm.dts | 2 +- .../boot/dts/{ => ti/davinci}/da850-lcdk.dts | 0 .../dts/{ => ti/davinci}/da850-lego-ev3.dts | 0 arch/arm/boot/dts/{ => ti/davinci}/da850.dtsi | 0 arch/arm/boot/dts/ti/keystone/Makefile | 7 + .../{ => ti/keystone}/keystone-clocks.dtsi | 0 .../keystone}/keystone-k2e-clocks.dtsi | 0 .../{ => ti/keystone}/keystone-k2e-evm.dts | 0 .../{ => ti/keystone}/keystone-k2e-netcp.dtsi | 0 .../dts/{ => ti/keystone}/keystone-k2e.dtsi | 0 .../{ => ti/keystone}/keystone-k2g-evm.dts | 0 .../{ => ti/keystone}/keystone-k2g-ice.dts | 0 .../{ => ti/keystone}/keystone-k2g-netcp.dtsi | 0 .../dts/{ => ti/keystone}/keystone-k2g.dtsi | 0 .../keystone}/keystone-k2hk-clocks.dtsi | 0 .../{ => ti/keystone}/keystone-k2hk-evm.dts | 0 .../keystone}/keystone-k2hk-netcp.dtsi | 0 .../dts/{ => ti/keystone}/keystone-k2hk.dtsi | 0 .../keystone}/keystone-k2l-clocks.dtsi | 0 .../{ => ti/keystone}/keystone-k2l-evm.dts | 0 .../{ => ti/keystone}/keystone-k2l-netcp.dtsi | 0 .../dts/{ => ti/keystone}/keystone-k2l.dtsi | 0 .../boot/dts/{ => ti/keystone}/keystone.dtsi | 0 arch/arm/boot/dts/ti/omap/Makefile | 163 ++ .../{ => ti/omap}/am335x-baltos-ir2110.dts | 0 .../{ => ti/omap}/am335x-baltos-ir3220.dts | 0 .../{ => ti/omap}/am335x-baltos-ir5221.dts | 0 .../dts/{ => ti/omap}/am335x-baltos-leds.dtsi | 0 .../boot/dts/{ => ti/omap}/am335x-baltos.dtsi | 2 +- .../dts/{ => ti/omap}/am335x-base0033.dts | 0 .../dts/{ => ti/omap}/am335x-bone-common.dtsi | 2 +- .../boot/dts/{ => ti/omap}/am335x-bone.dts | 0 .../omap}/am335x-boneblack-common.dtsi | 0 .../{ => ti/omap}/am335x-boneblack-hdmi.dtsi | 0 .../omap}/am335x-boneblack-wireless.dts | 0 .../dts/{ => ti/omap}/am335x-boneblack.dts | 0 .../dts/{ => ti/omap}/am335x-boneblue.dts | 2 +- .../omap}/am335x-bonegreen-common.dtsi | 0 .../omap}/am335x-bonegreen-wireless.dts | 0 .../dts/{ => ti/omap}/am335x-bonegreen.dts | 0 .../dts/{ => ti/omap}/am335x-chiliboard.dts | 0 .../dts/{ => ti/omap}/am335x-chilisom.dtsi | 2 +- .../boot/dts/{ => ti/omap}/am335x-cm-t335.dts | 0 .../arm/boot/dts/{ => ti/omap}/am335x-evm.dts | 2 +- .../boot/dts/{ => ti/omap}/am335x-evmsk.dts | 2 +- .../dts/{ => ti/omap}/am335x-guardian.dts | 2 +- .../boot/dts/{ => ti/omap}/am335x-icev2.dts | 2 +- .../dts/{ => ti/omap}/am335x-igep0033.dtsi | 2 +- .../arm/boot/dts/{ => ti/omap}/am335x-lxm.dts | 2 +- .../omap}/am335x-moxa-uc-2100-common.dtsi | 0 .../dts/{ => ti/omap}/am335x-moxa-uc-2101.dts | 0 .../omap}/am335x-moxa-uc-8100-common.dtsi | 2 +- .../omap}/am335x-moxa-uc-8100-me-t.dts | 0 .../{ => ti/omap}/am335x-myirtech-myc.dtsi | 0 .../dts/{ => ti/omap}/am335x-myirtech-myd.dts | 0 .../boot/dts/{ => ti/omap}/am335x-nano.dts | 2 +- .../{ => ti/omap}/am335x-netcan-plus-1xx.dts | 0 .../{ => ti/omap}/am335x-netcom-plus-2xx.dts | 0 .../{ => ti/omap}/am335x-netcom-plus-8xx.dts | 0 .../{ => ti/omap}/am335x-osd3358-sm-red.dts | 0 .../{ => ti/omap}/am335x-osd335x-common.dtsi | 2 +- .../dts/{ => ti/omap}/am335x-pcm-953.dtsi | 0 .../boot/dts/{ => ti/omap}/am335x-pdu001.dts | 2 +- .../boot/dts/{ => ti/omap}/am335x-pepper.dts | 2 +- .../dts/{ => ti/omap}/am335x-phycore-rdk.dts | 0 .../dts/{ => ti/omap}/am335x-phycore-som.dtsi | 2 +- .../dts/{ => ti/omap}/am335x-pocketbeagle.dts | 0 .../dts/{ => ti/omap}/am335x-regor-rdk.dts | 0 .../boot/dts/{ => ti/omap}/am335x-regor.dtsi | 0 .../omap}/am335x-sancloud-bbe-common.dtsi | 0 .../am335x-sancloud-bbe-extended-wifi.dts | 0 .../omap}/am335x-sancloud-bbe-lite.dts | 0 .../dts/{ => ti/omap}/am335x-sancloud-bbe.dts | 0 .../dts/{ => ti/omap}/am335x-sbc-t335.dts | 0 .../arm/boot/dts/{ => ti/omap}/am335x-shc.dts | 0 .../boot/dts/{ => ti/omap}/am335x-sl50.dts | 2 +- .../dts/{ => ti/omap}/am335x-wega-rdk.dts | 0 .../boot/dts/{ => ti/omap}/am335x-wega.dtsi | 0 .../boot/dts/{ => ti/omap}/am33xx-clocks.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/am33xx-l4.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/am33xx.dtsi | 0 .../dts/{ => ti/omap}/am3517-craneboard.dts | 2 +- .../boot/dts/{ => ti/omap}/am3517-evm-ui.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/am3517-evm.dts | 0 .../boot/dts/{ => ti/omap}/am3517-som.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/am3517.dtsi | 0 .../dts/{ => ti/omap}/am3517_mt_ventoux.dts | 0 .../boot/dts/{ => ti/omap}/am35xx-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/am3703.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/am3715.dtsi | 0 .../dts/{ => ti/omap}/am3874-iceboard.dts | 0 arch/arm/boot/dts/{ => ti/omap}/am4372.dtsi | 0 .../boot/dts/{ => ti/omap}/am437x-cm-t43.dts | 0 .../boot/dts/{ => ti/omap}/am437x-gp-evm.dts | 0 .../boot/dts/{ => ti/omap}/am437x-idk-evm.dts | 0 .../arm/boot/dts/{ => ti/omap}/am437x-l4.dtsi | 0 .../boot/dts/{ => ti/omap}/am437x-sbc-t43.dts | 0 .../boot/dts/{ => ti/omap}/am437x-sk-evm.dts | 0 .../boot/dts/{ => ti/omap}/am43x-epos-evm.dts | 0 .../boot/dts/{ => ti/omap}/am43xx-clocks.dtsi | 0 .../boot/dts/{ => ti/omap}/am57-pruss.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/am5718.dtsi | 0 .../{ => ti/omap}/am571x-idk-touchscreen.dtso | 0 .../arm/boot/dts/{ => ti/omap}/am571x-idk.dts | 0 arch/arm/boot/dts/{ => ti/omap}/am5728.dtsi | 0 .../dts/{ => ti/omap}/am5729-beagleboneai.dts | 0 .../dts/{ => ti/omap}/am572x-idk-common.dtsi | 0 .../{ => ti/omap}/am572x-idk-touchscreen.dtso | 0 .../arm/boot/dts/{ => ti/omap}/am572x-idk.dts | 0 arch/arm/boot/dts/{ => ti/omap}/am5748.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/am574x-idk.dts | 0 .../omap}/am57xx-beagle-x15-common.dtsi | 0 .../{ => ti/omap}/am57xx-beagle-x15-revb1.dts | 0 .../{ => ti/omap}/am57xx-beagle-x15-revc.dts | 0 .../dts/{ => ti/omap}/am57xx-beagle-x15.dts | 0 .../dts/{ => ti/omap}/am57xx-cl-som-am57x.dts | 0 .../omap}/am57xx-commercial-grade.dtsi | 0 .../boot/dts/{ => ti/omap}/am57xx-evm.dtso | 0 .../dts/{ => ti/omap}/am57xx-idk-common.dtsi | 0 .../omap}/am57xx-idk-lcd-osd101t2045.dtso | 0 .../omap}/am57xx-idk-lcd-osd101t2587.dtso | 0 .../omap}/am57xx-industrial-grade.dtsi | 0 .../dts/{ => ti/omap}/am57xx-sbc-am57x.dts | 0 .../dts/{ => ti/omap}/compulab-sb-som.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dm3725.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/dm8148-evm.dts | 0 .../boot/dts/{ => ti/omap}/dm8148-t410.dts | 0 .../boot/dts/{ => ti/omap}/dm814x-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dm814x.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/dm8168-evm.dts | 0 .../boot/dts/{ => ti/omap}/dm816x-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dm816x.dtsi | 0 .../boot/dts/{ => ti/omap}/dra62x-clocks.dtsi | 0 .../dts/{ => ti/omap}/dra62x-j5eco-evm.dts | 0 arch/arm/boot/dts/{ => ti/omap}/dra62x.dtsi | 0 .../{ => ti/omap}/dra7-dspeve-thermal.dtsi | 0 .../dts/{ => ti/omap}/dra7-evm-common.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra7-evm.dts | 0 .../{ => ti/omap}/dra7-ipu-dsp-common.dtsi | 0 .../dts/{ => ti/omap}/dra7-iva-thermal.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra7-l4.dtsi | 0 .../dts/{ => ti/omap}/dra7-mmc-iodelay.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra7.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra71-evm.dts | 0 arch/arm/boot/dts/{ => ti/omap}/dra71x.dtsi | 0 .../dts/{ => ti/omap}/dra72-evm-common.dtsi | 0 .../boot/dts/{ => ti/omap}/dra72-evm-revc.dts | 0 .../dts/{ => ti/omap}/dra72-evm-tps65917.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra72-evm.dts | 0 .../dts/{ => ti/omap}/dra72x-mmc-iodelay.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra72x.dtsi | 0 .../{ => ti/omap}/dra74-ipu-dsp-common.dtsi | 0 .../dts/{ => ti/omap}/dra74x-mmc-iodelay.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra74x-p.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra74x.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra76-evm.dts | 0 .../dts/{ => ti/omap}/dra76x-mmc-iodelay.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/dra76x.dtsi | 0 .../boot/dts/{ => ti/omap}/dra7xx-clocks.dtsi | 0 .../dts/{ => ti/omap}/elpida_ecb240abacn.dtsi | 0 .../omap}/logicpd-som-lv-35xx-devkit.dts | 0 .../omap}/logicpd-som-lv-37xx-devkit.dts | 0 .../omap}/logicpd-som-lv-baseboard.dtsi | 0 .../dts/{ => ti/omap}/logicpd-som-lv.dtsi | 0 .../omap}/logicpd-torpedo-35xx-devkit.dts | 0 .../omap}/logicpd-torpedo-37xx-devkit-28.dts | 0 .../omap}/logicpd-torpedo-37xx-devkit.dts | 0 .../omap}/logicpd-torpedo-baseboard.dtsi | 0 .../{ => ti/omap}/logicpd-torpedo-som.dtsi | 0 .../omap}/motorola-cpcap-mapphone.dtsi | 0 .../omap}/motorola-mapphone-common.dtsi | 0 .../dts/{ => ti/omap}/omap-gpmc-smsc911x.dtsi | 0 .../dts/{ => ti/omap}/omap-gpmc-smsc9221.dtsi | 0 .../dts/{ => ti/omap}/omap-zoom-common.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap2.dtsi | 0 .../dts/{ => ti/omap}/omap2420-clocks.dtsi | 0 .../boot/dts/{ => ti/omap}/omap2420-h4.dts | 0 .../boot/dts/{ => ti/omap}/omap2420-n800.dts | 0 .../dts/{ => ti/omap}/omap2420-n810-wimax.dts | 0 .../boot/dts/{ => ti/omap}/omap2420-n810.dts | 0 .../{ => ti/omap}/omap2420-n8x0-common.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap2420.dtsi | 0 .../dts/{ => ti/omap}/omap2430-clocks.dtsi | 0 .../boot/dts/{ => ti/omap}/omap2430-sdp.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap2430.dtsi | 0 .../dts/{ => ti/omap}/omap24xx-clocks.dtsi | 0 .../dts/{ => ti/omap}/omap3-beagle-ab4.dts | 0 .../dts/{ => ti/omap}/omap3-beagle-xm-ab.dts | 0 .../dts/{ => ti/omap}/omap3-beagle-xm.dts | 0 .../boot/dts/{ => ti/omap}/omap3-beagle.dts | 0 .../boot/dts/{ => ti/omap}/omap3-cm-t3517.dts | 0 .../boot/dts/{ => ti/omap}/omap3-cm-t3530.dts | 0 .../boot/dts/{ => ti/omap}/omap3-cm-t3730.dts | 0 .../boot/dts/{ => ti/omap}/omap3-cm-t3x.dtsi | 0 .../dts/{ => ti/omap}/omap3-cm-t3x30.dtsi | 0 .../dts/{ => ti/omap}/omap3-cpu-thermal.dtsi | 0 .../omap}/omap3-devkit8000-common.dtsi | 0 .../omap}/omap3-devkit8000-lcd-common.dtsi | 0 .../{ => ti/omap}/omap3-devkit8000-lcd43.dts | 0 .../{ => ti/omap}/omap3-devkit8000-lcd70.dts | 0 .../dts/{ => ti/omap}/omap3-devkit8000.dts | 0 .../arm/boot/dts/{ => ti/omap}/omap3-echo.dts | 2 +- .../boot/dts/{ => ti/omap}/omap3-evm-37xx.dts | 0 .../dts/{ => ti/omap}/omap3-evm-common.dtsi | 0 .../omap}/omap3-evm-processor-common.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap3-evm.dts | 0 .../boot/dts/{ => ti/omap}/omap3-gta04.dtsi | 0 .../boot/dts/{ => ti/omap}/omap3-gta04a3.dts | 0 .../boot/dts/{ => ti/omap}/omap3-gta04a4.dts | 0 .../boot/dts/{ => ti/omap}/omap3-gta04a5.dts | 0 .../dts/{ => ti/omap}/omap3-gta04a5one.dts | 0 .../dts/{ => ti/omap}/omap3-ha-common.dtsi | 0 .../boot/dts/{ => ti/omap}/omap3-ha-lcd.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap3-ha.dts | 0 .../boot/dts/{ => ti/omap}/omap3-igep.dtsi | 0 .../{ => ti/omap}/omap3-igep0020-common.dtsi | 0 .../{ => ti/omap}/omap3-igep0020-rev-f.dts | 0 .../boot/dts/{ => ti/omap}/omap3-igep0020.dts | 0 .../{ => ti/omap}/omap3-igep0030-common.dtsi | 0 .../{ => ti/omap}/omap3-igep0030-rev-g.dts | 0 .../boot/dts/{ => ti/omap}/omap3-igep0030.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap3-ldp.dts | 0 .../dts/{ => ti/omap}/omap3-lilly-a83x.dtsi | 0 .../dts/{ => ti/omap}/omap3-lilly-dbb056.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap3-n9.dts | 0 .../arm/boot/dts/{ => ti/omap}/omap3-n900.dts | 0 .../boot/dts/{ => ti/omap}/omap3-n950-n9.dtsi | 0 .../arm/boot/dts/{ => ti/omap}/omap3-n950.dts | 0 .../omap}/omap3-overo-alto35-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-alto35.dts | 0 .../dts/{ => ti/omap}/omap3-overo-base.dtsi | 0 .../omap}/omap3-overo-chestnut43-common.dtsi | 0 .../{ => ti/omap}/omap3-overo-chestnut43.dts | 0 .../{ => ti/omap}/omap3-overo-common-dvi.dtsi | 0 .../omap}/omap3-overo-common-lcd35.dtsi | 0 .../omap}/omap3-overo-common-lcd43.dtsi | 0 .../omap}/omap3-overo-common-peripherals.dtsi | 0 .../omap}/omap3-overo-gallop43-common.dtsi | 0 .../{ => ti/omap}/omap3-overo-gallop43.dts | 0 .../omap}/omap3-overo-palo35-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-palo35.dts | 0 .../omap}/omap3-overo-palo43-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-palo43.dts | 0 .../omap}/omap3-overo-storm-alto35.dts | 0 .../omap}/omap3-overo-storm-chestnut43.dts | 0 .../omap}/omap3-overo-storm-gallop43.dts | 0 .../omap}/omap3-overo-storm-palo35.dts | 0 .../omap}/omap3-overo-storm-palo43.dts | 0 .../omap}/omap3-overo-storm-summit.dts | 0 .../{ => ti/omap}/omap3-overo-storm-tobi.dts | 0 .../omap}/omap3-overo-storm-tobiduo.dts | 0 .../dts/{ => ti/omap}/omap3-overo-storm.dtsi | 0 .../omap}/omap3-overo-summit-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-summit.dts | 0 .../omap}/omap3-overo-tobi-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-tobi.dts | 0 .../omap}/omap3-overo-tobiduo-common.dtsi | 0 .../dts/{ => ti/omap}/omap3-overo-tobiduo.dts | 0 .../boot/dts/{ => ti/omap}/omap3-overo.dtsi | 0 .../dts/{ => ti/omap}/omap3-pandora-1ghz.dts | 0 .../{ => ti/omap}/omap3-pandora-600mhz.dts | 0 .../{ => ti/omap}/omap3-pandora-common.dtsi | 0 .../omap}/omap3-panel-sharp-ls037v7dw01.dtsi | 0 .../boot/dts/{ => ti/omap}/omap3-sb-t35.dtsi | 0 .../dts/{ => ti/omap}/omap3-sbc-t3517.dts | 0 .../dts/{ => ti/omap}/omap3-sbc-t3530.dts | 0 .../dts/{ => ti/omap}/omap3-sbc-t3730.dts | 0 .../boot/dts/{ => ti/omap}/omap3-sniper.dts | 0 .../boot/dts/{ => ti/omap}/omap3-tao3530.dtsi | 0 .../boot/dts/{ => ti/omap}/omap3-thunder.dts | 0 .../boot/dts/{ => ti/omap}/omap3-zoom3.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap3.dtsi | 0 .../boot/dts/{ => ti/omap}/omap3430-sdp.dts | 0 .../dts/{ => ti/omap}/omap3430es1-clocks.dtsi | 0 .../omap}/omap34xx-omap36xx-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap34xx.dtsi | 0 ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 0 .../dts/{ => ti/omap}/omap36xx-clocks.dtsi | 0 .../omap36xx-omap3430es2plus-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap36xx.dtsi | 0 .../dts/{ => ti/omap}/omap3xxx-clocks.dtsi | 0 .../dts/{ => ti/omap}/omap4-cpu-thermal.dtsi | 0 .../omap}/omap4-droid-bionic-xt875.dts | 0 .../dts/{ => ti/omap}/omap4-droid4-xt894.dts | 0 .../{ => ti/omap}/omap4-duovero-parlor.dts | 0 .../boot/dts/{ => ti/omap}/omap4-duovero.dtsi | 0 .../dts/{ => ti/omap}/omap4-epson-embt2ws.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap4-kc1.dts | 0 .../boot/dts/{ => ti/omap}/omap4-l4-abe.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap4-l4.dtsi | 0 .../boot/dts/{ => ti/omap}/omap4-mcpdm.dtsi | 0 .../boot/dts/{ => ti/omap}/omap4-panda-a4.dts | 0 .../dts/{ => ti/omap}/omap4-panda-common.dtsi | 0 .../boot/dts/{ => ti/omap}/omap4-panda-es.dts | 0 .../boot/dts/{ => ti/omap}/omap4-panda.dts | 0 .../dts/{ => ti/omap}/omap4-sdp-es23plus.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap4-sdp.dts | 0 .../dts/{ => ti/omap}/omap4-var-dvk-om44.dts | 0 .../omap}/omap4-var-om44customboard.dtsi | 0 .../omap}/omap4-var-som-om44-wlan.dtsi | 0 .../dts/{ => ti/omap}/omap4-var-som-om44.dtsi | 0 .../dts/{ => ti/omap}/omap4-var-stk-om44.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap4.dtsi | 0 .../dts/{ => ti/omap}/omap443x-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap443x.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap4460.dtsi | 0 .../dts/{ => ti/omap}/omap446x-clocks.dtsi | 0 .../dts/{ => ti/omap}/omap44xx-clocks.dtsi | 0 .../dts/{ => ti/omap}/omap5-board-common.dtsi | 0 .../boot/dts/{ => ti/omap}/omap5-cm-t54.dts | 0 .../dts/{ => ti/omap}/omap5-core-thermal.dtsi | 0 .../dts/{ => ti/omap}/omap5-gpu-thermal.dtsi | 0 .../boot/dts/{ => ti/omap}/omap5-igep0050.dts | 0 .../boot/dts/{ => ti/omap}/omap5-l4-abe.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/omap5-l4.dtsi | 0 .../boot/dts/{ => ti/omap}/omap5-sbc-t54.dts | 0 .../arm/boot/dts/{ => ti/omap}/omap5-uevm.dts | 0 arch/arm/boot/dts/{ => ti/omap}/omap5.dtsi | 0 .../dts/{ => ti/omap}/omap54xx-clocks.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/twl4030.dtsi | 0 .../boot/dts/{ => ti/omap}/twl4030_omap3.dtsi | 0 arch/arm/boot/dts/{ => ti/omap}/twl6030.dtsi | 0 .../boot/dts/{ => ti/omap}/twl6030_omap4.dtsi | 0 arch/arm/boot/dts/unisoc/Makefile | 4 + .../rda8810pl-orangepi-2g-iot.dts | 0 .../{ => unisoc}/rda8810pl-orangepi-i96.dts | 0 arch/arm/boot/dts/{ => unisoc}/rda8810pl.dtsi | 0 arch/arm/boot/dts/vt8500/Makefile | 7 + .../arm/boot/dts/{ => vt8500}/vt8500-bv07.dts | 0 arch/arm/boot/dts/{ => vt8500}/vt8500.dtsi | 0 arch/arm/boot/dts/{ => vt8500}/wm8505-ref.dts | 0 arch/arm/boot/dts/{ => vt8500}/wm8505.dtsi | 0 arch/arm/boot/dts/{ => vt8500}/wm8650-mid.dts | 0 arch/arm/boot/dts/{ => vt8500}/wm8650.dtsi | 0 .../boot/dts/{ => vt8500}/wm8750-apc8750.dts | 0 arch/arm/boot/dts/{ => vt8500}/wm8750.dtsi | 0 .../boot/dts/{ => vt8500}/wm8850-w70v2.dts | 0 arch/arm/boot/dts/{ => vt8500}/wm8850.dtsi | 0 arch/arm/boot/dts/xen/Makefile | 3 + arch/arm/boot/dts/{ => xen}/xenvm-4.2.dts | 0 arch/arm/boot/dts/xilinx/Makefile | 17 + arch/arm/boot/dts/{ => xilinx}/zynq-7000.dtsi | 0 arch/arm/boot/dts/{ => xilinx}/zynq-cc108.dts | 0 .../boot/dts/{ => xilinx}/zynq-ebaz4205.dts | 0 .../boot/dts/{ => xilinx}/zynq-microzed.dts | 0 .../boot/dts/{ => xilinx}/zynq-parallella.dts | 0 arch/arm/boot/dts/{ => xilinx}/zynq-zc702.dts | 0 arch/arm/boot/dts/{ => xilinx}/zynq-zc706.dts | 0 .../dts/{ => xilinx}/zynq-zc770-xm010.dts | 0 .../dts/{ => xilinx}/zynq-zc770-xm011.dts | 0 .../dts/{ => xilinx}/zynq-zc770-xm012.dts | 0 .../dts/{ => xilinx}/zynq-zc770-xm013.dts | 0 arch/arm/boot/dts/{ => xilinx}/zynq-zed.dts | 0 .../dts/{ => xilinx}/zynq-zturn-common.dtsi | 0 .../boot/dts/{ => xilinx}/zynq-zturn-v5.dts | 0 arch/arm/boot/dts/{ => xilinx}/zynq-zturn.dts | 0 .../boot/dts/{ => xilinx}/zynq-zybo-z7.dts | 0 arch/arm/boot/dts/{ => xilinx}/zynq-zybo.dts | 0 .../sun50i-h5-bananapi-m2-plus-v1.2.dts | 2 +- .../allwinner/sun50i-h5-bananapi-m2-plus.dts | 2 +- .../allwinner/sun50i-h5-emlid-neutis-n5.dtsi | 2 +- .../sun50i-h5-libretech-all-h3-cc.dts | 2 +- .../sun50i-h5-libretech-all-h3-it.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +- .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- .../boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 +- .../boot/dts/broadcom/bcm2711-rpi-400.dts | 2 +- .../boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 2 +- .../dts/broadcom/bcm2837-rpi-3-a-plus.dts | 2 +- .../dts/broadcom/bcm2837-rpi-3-b-plus.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-3-b.dts | 2 +- .../boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts | 2 +- .../dts/broadcom/bcm2837-rpi-zero-2-w.dts | 2 +- arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- .../dts/rockchip/rk3399pro-rock-pi-n10.dts | 2 +- .../boot/dts/socionext/uniphier-pinctrl.dtsi | 2 +- .../dts/socionext/uniphier-ref-daughter.dtsi | 2 +- .../dts/socionext/uniphier-support-card.dtsi | 2 +- 2666 files changed, 2153 insertions(+), 1887 deletions(-) create mode 100644 arch/arm/boot/dts/actions/Makefile rename arch/arm/boot/dts/{ => actions}/owl-s500-cubieboard6.dts (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-guitar-bb-rev-b.dts (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-guitar.dtsi (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-labrador-base-m.dts (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-labrador-v2.dtsi (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-roseapplepi.dts (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500-sparky.dts (100%) rename arch/arm/boot/dts/{ => actions}/owl-s500.dtsi (100%) create mode 100644 arch/arm/boot/dts/airoha/Makefile rename arch/arm/boot/dts/{ => airoha}/en7523-evb.dts (100%) rename arch/arm/boot/dts/{ => airoha}/en7523.dtsi (100%) create mode 100644 arch/arm/boot/dts/allwinner/Makefile rename arch/arm/boot/dts/{ => allwinner}/axp152.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/axp209.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/axp223.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/axp22x.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/axp809.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/axp81x.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-a1000.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-ba10-tvbox.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-chuwi-v7-cw0825.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-cubieboard.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-dserve-dsrv9703c.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-gemei-g9.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-hackberry.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-hyundai-a7hd.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-inet1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-inet97fv2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-inet9f-rev03.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-itead-iteaduino-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-jesurun-q5.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-marsboard.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-mini-xplus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-mk802.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-mk802ii.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-olinuxino-lime.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-pcduino.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-pcduino2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-pov-protab2-ips9.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10-topwise-a721.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun4i-a10.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-auxtek-t003.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-auxtek-t004.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-mk802.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-olinuxino-micro.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-r7-tv-dongle.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s-wobo-i5.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a10s.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-difrnce-dit4350.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-empire-electronix-d709.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-empire-electronix-m712.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-hsg-h702.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-inet-98v-rev2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-licheepi-one.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-olinuxino-micro.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-olinuxino.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-pocketbook-touch-lux-3.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-q8-tablet.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13-utoo-p66.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-a13.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-gr8-chip-pro.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-gr8-evb.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-gr8.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-r8-chip.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-r8.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i-reference-design-tablet.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun5i.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-app4-evb1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-colombus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-hummingbird.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-i7.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-m9.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31-mele-a1000g-quad.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-colorfly-e708-q1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-cs908.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-inet-q972.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-primo81.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-sina31s-core.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-sina31s.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-sinovoip-bpi-m2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s-yones-toptech-bs1078-v2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-a31s.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun6i-reference-design-tablet.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-bananapi-m1-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-bananapi.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-bananapro.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-cubieboard2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-cubietruck.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-haoyu-marsboard.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-hummingbird.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-i12-tvbox.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-icnova-a20-adb4006.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-icnova-a20.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-icnova-swac.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-itead-ibox.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-lamobo-r1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-linutronix-testbox-v2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-m3.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-mk808c.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olimex-som-evb-emmc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olimex-som-evb.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olimex-som204-evb-emmc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olimex-som204-evb.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-lime-emmc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-lime.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-lime2-emmc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-lime2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-micro-emmc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-olinuxino-micro.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-orangepi-mini.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-orangepi.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-pcduino3-nano.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-pcduino3.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-wexler-tab7200.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20-wits-pro-a20-dkt.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun7i-a20.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-a33.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-evb.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-gt90h-v4.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-inet86dz.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-ippo-q8h-v1.2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-ippo-q8h-v5.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-polaroid-mid2407pxe03.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-polaroid-mid2809pxe04.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23-q8-tablet.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a23.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-et-q8-v1.6.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-ga10h-v1.1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-inet-d978-rev2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-ippo-q8h-v1.2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-olinuxino.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-q8-tablet.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33-sinlinx-sina33.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a33.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a83t-allwinner-h8homlet-v2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a83t-bananapi-m3.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a83t-cubietruck-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a83t-tbs-a711.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-a83t.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h2-plus-bananapi-m2-zero.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h2-plus-libretech-all-h3-cc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h2-plus-orangepi-r1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h2-plus-orangepi-zero.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-bananapi-m2-plus-v1.2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-bananapi-m2-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-beelink-x2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-emlid-neutis-n5h3-devboard.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-emlid-neutis-n5h3.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-libretech-all-h3-cc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-mapleboard-mp130.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-duo2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-m1-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-m1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-neo-air.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-neo.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi-r1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-nanopi.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-lite.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-one.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-pc-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-pc.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-plus2e.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-orangepi-zero-plus2.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-rervision-dvk.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3-zeropi.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-h3.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-q8-common.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r16-bananapi-m2m.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r16-nintendo-nes-classic.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r16-nintendo-super-nes-classic.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r16-parrot.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r40-bananapi-m2-ultra.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r40-cpu-opp.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r40-feta40i.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r40-oka40i-c.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-r40.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-reference-design-tablet.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-s3-elimo-impetus.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-s3-elimo-initium.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-s3-lichee-zero-plus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-s3-pinecube.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-t113s-mangopi-mq-r-t113.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-t113s.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-t3-cqa3t-bv3.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3-sl631-imx179.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3-sl631.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3s-licheepi-zero-dock.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3s-licheepi-zero.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v3s.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sun8i-v40-bananapi-m2-berry.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun9i-a80-cubieboard4.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun9i-a80-optimus.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sun9i-a80.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/suniv-f1c100s-licheepi-nano.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/suniv-f1c100s.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/suniv-f1c200s-lctech-pi.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/suniv-f1c200s-popstick-v1.1.dts (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-bananapi-m2-plus-v1.2.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-bananapi-m2-plus.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-common-regulators.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-d1s-t113-mangopi-mq-r.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-h3-h5-emlid-neutis.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-h3-h5.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-itead-core-common.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-libretech-all-h3-cc.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-libretech-all-h3-it.dtsi (100%) rename arch/arm/boot/dts/{ => allwinner}/sunxi-reference-design-tablet.dtsi (100%) create mode 100644 arch/arm/boot/dts/alphascale/Makefile rename arch/arm/boot/dts/{ => alphascale}/alphascale-asm9260-devkit.dts (100%) rename arch/arm/boot/dts/{ => alphascale}/alphascale-asm9260.dtsi (100%) create mode 100644 arch/arm/boot/dts/amazon/Makefile rename arch/arm/boot/dts/{ => amazon}/alpine-db.dts (100%) rename arch/arm/boot/dts/{ => amazon}/alpine.dtsi (100%) create mode 100644 arch/arm/boot/dts/amlogic/Makefile rename arch/arm/boot/dts/{ => amlogic}/meson.dtsi (100%) rename arch/arm/boot/dts/{ => amlogic}/meson6-atv1200.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson6.dtsi (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8-minix-neo-x8.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8.dtsi (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8b-ec100.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8b-mxq.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8b-odroidc1.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8b.dtsi (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8m2-mxiii-plus.dts (100%) rename arch/arm/boot/dts/{ => amlogic}/meson8m2.dtsi (100%) create mode 100644 arch/arm/boot/dts/arm/Makefile rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-11mp-bbrevd-ctrevb.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-11mp-bbrevd.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-11mp-ctrevb.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-11mp.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-a9mp-bbrevd.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-a9mp.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-bbrevd.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-bbrevd.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb-mp.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-eb.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-pb1176.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-pb11mp.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-pba8.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-pbx-a9.dts (100%) rename arch/arm/boot/dts/{ => arm}/arm-realview-pbx.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/integrator.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/integratorap-im-pd1.dts (100%) rename arch/arm/boot/dts/{ => arm}/integratorap.dts (100%) rename arch/arm/boot/dts/{ => arm}/integratorcp.dts (100%) rename arch/arm/boot/dts/{ => arm}/mps2-an385.dts (100%) rename arch/arm/boot/dts/{ => arm}/mps2-an399.dts (100%) rename arch/arm/boot/dts/{ => arm}/mps2.dtsi (99%) rename arch/arm/boot/dts/{ => arm}/versatile-ab-ib2.dts (100%) rename arch/arm/boot/dts/{ => arm}/versatile-ab.dts (100%) rename arch/arm/boot/dts/{ => arm}/versatile-pb.dts (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2m-rs1.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2m.dtsi (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2p-ca15-tc1.dts (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2p-ca15_a7.dts (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2p-ca5s.dts (100%) rename arch/arm/boot/dts/{ => arm}/vexpress-v2p-ca9.dts (100%) create mode 100644 arch/arm/boot/dts/aspeed/Makefile rename arch/arm/boot/dts/{ => aspeed}/aspeed-ast2500-evb.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-ast2600-evb-a1.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-ast2600-evb.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-amd-daytonax.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-amd-ethanolx.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ampere-mtjade.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ampere-mtmitchell.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-arm-stardragon4800-rep2.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-asrock-e3c246d4i.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-asrock-romed8hm3.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-bytedance-g220a.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-delta-ahe50dc.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-bletchley.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-cloudripper.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-cmm.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-elbert.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-fuji.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-galaxy100.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-greatlakes.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-minipack.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-tiogapass.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-wedge100.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-wedge40.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-wedge400.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-yamp.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-facebook-yosemitev2.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ibm-bonnell.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ibm-everest.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ibm-rainier-1s4u.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ibm-rainier-4u.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ibm-rainier.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-inspur-fp5280g2.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-inspur-nf5280m6.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-inspur-on5263m5.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-intel-s2600wf.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-inventec-transformers.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-lenovo-hr630.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-lenovo-hr855xg2.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-microsoft-olympus.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-lanyang.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-mowgli.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-nicole.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-palmetto.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-romulus.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-swift.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-tacoma.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-vesnin.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-witherspoon.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-opp-zaius.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-portwell-neptune.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-qcom-dc-scm-v1.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-quanta-q71l.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-quanta-s6q.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-supermicro-x11spi.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-tyan-s7106.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-tyan-s8036.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-ufispace-ncplite.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-vegman-n110.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-vegman-rx20.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-vegman-sx20.dts (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-bmc-vegman.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-g4.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-g5.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-g6-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/aspeed-g6.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/ast2400-facebook-netbmc-common.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/ast2500-facebook-netbmc-common.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/ast2600-facebook-netbmc-common.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/facebook-bmc-flash-layout-128.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/facebook-bmc-flash-layout.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/ibm-power9-dual.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/openbmc-flash-layout-128.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/openbmc-flash-layout-64-alt.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/openbmc-flash-layout-64.dtsi (100%) rename arch/arm/boot/dts/{ => aspeed}/openbmc-flash-layout.dtsi (100%) create mode 100644 arch/arm/boot/dts/axis/Makefile rename arch/arm/boot/dts/{ => axis}/artpec6-devboard.dts (100%) rename arch/arm/boot/dts/{ => axis}/artpec6.dtsi (100%) create mode 100644 arch/arm/boot/dts/broadcom/Makefile rename arch/arm/boot/dts/{ => broadcom}/bcm-cygnus-clock.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm-cygnus.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm-hr2.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm-ns.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm-nsp-ax.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm-nsp.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm11351.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm21664-garnet.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm21664.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm23550-sparrow.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm23550.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711-rpi-4-b.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711-rpi-400.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711-rpi-cm4-io.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711-rpi-cm4.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711-rpi.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2711.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm28155-ap.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-common.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-a-plus.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-a.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-b-plus.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-b-rev2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-b.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-cm1-io1.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-cm1.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-common.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-zero-w.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi-zero.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835-rpi.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2835.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2836-rpi-2-b.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2836-rpi.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2836.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-3-a-plus.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-3-b-plus.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-3-b.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-cm3-io3.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-cm3.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837-rpi-zero-2-w.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm2837.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-lan7515.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-led-deprecated.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-smsc9512.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-smsc9514.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-usb-host.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-usb-otg.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-usb-peripheral.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x-rpi-wifi-bt.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm283x.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-asus-rt-ac56u.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-asus-rt-ac68u.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-buffalo-wzr-1166dhp-common.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-buffalo-wzr-1166dhp.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-buffalo-wzr-1166dhp2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-buffalo-wzr-1750dhp.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-linksys-ea6300-v1.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-linksys-ea6500-v2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-luxul-xap-1510.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-luxul-xwc-1000.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-netgear-r6250.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-netgear-r6300-v2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708-smartrg-sr400ac.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4708.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-asus-rt-n18u.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-buffalo-wzr-600dhp2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-buffalo-wzr-900dhp.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-luxul-xap-1410.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-luxul-xwr-1200.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081-tplink-archer-c5-v2.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47081.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-asus-rt-ac87u.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-buffalo-wxr-1900dhp.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-linksys-ea9200.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-netgear-r7000.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-netgear-r8000.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709-tplink-archer-c9-v1.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm4709.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-asus-rt-ac88u.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-dlink-dir-885l.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-dlink-dir-890l.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-linksys-panamera.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-abr-4500.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-xap-1610.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-xbr-4500.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-xwc-2000.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-xwr-3100.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-luxul-xwr-3150-v1.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-netgear-r8500.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094-phicomm-k3.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47094.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47189-luxul-xap-1440.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47189-luxul-xap-810.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47189-tenda-ac9.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm47622.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm53015-meraki-mr26.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm53016-dlink-dwl-8610ap.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm53016-meraki-mr32.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm5301x-nand-cs0-bch1.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm5301x-nand-cs0-bch4.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm5301x-nand-cs0-bch8.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm5301x-nand-cs0.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm5301x.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm53340-ubnt-unifi-switch8.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm53573.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm59056.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm63138.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm63148.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm63178.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm6756.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm6846.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm6855.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm6878.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm7445-bcm97445svmb.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm7445.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm911360_entphn.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm911360k.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm94708.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm94709.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm947189acdbmr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm947622.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm953012er.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm953012hr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm953012k.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958300k.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958305k.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958522er.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958525er.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958525xmc.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958622hr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958623hr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-alamo.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-kingpin.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx64-a0.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx64.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx64w-a0.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx64w.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx65.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx65w.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625-meraki-mx6x-common.dtsi (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625hr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm958625k.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm963138.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm963138dvt.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm963148.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm963178.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm96756.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm96846.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm96855.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm96878.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm988312hr.dts (100%) rename arch/arm/boot/dts/{ => broadcom}/bcm9hmidc.dtsi (100%) create mode 100644 arch/arm/boot/dts/calxeda/Makefile rename arch/arm/boot/dts/{ => calxeda}/ecx-2000.dts (100%) rename arch/arm/boot/dts/{ => calxeda}/ecx-common.dtsi (100%) rename arch/arm/boot/dts/{ => calxeda}/highbank.dts (100%) create mode 100644 arch/arm/boot/dts/cirrus/Makefile rename arch/arm/boot/dts/{ => cirrus}/ep7209.dtsi (100%) rename arch/arm/boot/dts/{ => cirrus}/ep7211-edb7211.dts (100%) rename arch/arm/boot/dts/{ => cirrus}/ep7211.dtsi (100%) create mode 100644 arch/arm/boot/dts/cnxt/Makefile rename arch/arm/boot/dts/{ => cnxt}/cx92755.dtsi (100%) rename arch/arm/boot/dts/{ => cnxt}/cx92755_equinox.dts (100%) create mode 100644 arch/arm/boot/dts/gemini/Makefile rename arch/arm/boot/dts/{ => gemini}/gemini-dlink-dir-685.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-dlink-dns-313.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-nas4220b.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-ns2502.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-rut1xx.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-sl93512r.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-sq201.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-ssi1328.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-wbd111.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini-wbd222.dts (100%) rename arch/arm/boot/dts/{ => gemini}/gemini.dtsi (100%) create mode 100644 arch/arm/boot/dts/hisilicon/Makefile rename arch/arm/boot/dts/{ => hisilicon}/hi3519-demb.dts (100%) rename arch/arm/boot/dts/{ => hisilicon}/hi3519.dtsi (100%) rename arch/arm/boot/dts/{ => hisilicon}/hi3620-hi4511.dts (100%) rename arch/arm/boot/dts/{ => hisilicon}/hi3620.dtsi (100%) rename arch/arm/boot/dts/{ => hisilicon}/hip01-ca9x2.dts (100%) rename arch/arm/boot/dts/{ => hisilicon}/hip01.dtsi (100%) rename arch/arm/boot/dts/{ => hisilicon}/hip04-d01.dts (100%) rename arch/arm/boot/dts/{ => hisilicon}/hip04.dtsi (100%) rename arch/arm/boot/dts/{ => hisilicon}/hisi-x5hd2-dkb.dts (100%) rename arch/arm/boot/dts/{ => hisilicon}/hisi-x5hd2.dtsi (100%) rename arch/arm/boot/dts/{ => hisilicon}/sd5203.dts (100%) create mode 100644 arch/arm/boot/dts/hpe/Makefile rename arch/arm/boot/dts/{ => hpe}/hpe-bmc-dl360gen10.dts (100%) rename arch/arm/boot/dts/{ => hpe}/hpe-gxp.dtsi (100%) create mode 100644 arch/arm/boot/dts/intel/Makefile create mode 100644 arch/arm/boot/dts/intel/axm/Makefile rename arch/arm/boot/dts/{ => intel/axm}/axm5516-amarillo.dts (100%) rename arch/arm/boot/dts/{ => intel/axm}/axm5516-cpus.dtsi (100%) rename arch/arm/boot/dts/{ => intel/axm}/axm55xx.dtsi (100%) create mode 100644 arch/arm/boot/dts/intel/ixp/Makefile rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-adi-coyote.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-arcom-vulcan.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-dlink-dsm-g600.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-freecom-fsg-3.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-gateway-7001.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-gateworks-gw2348.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-goramo-multilink.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-iomega-nas100d.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-ixdp425.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-ixdpg425.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-linksys-nslu2.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-linksys-wrv54g.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-netgear-wg302v1.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x-welltech-epbx100.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp42x.dtsi (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp43x-gateworks-gw2358.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp43x-kixrp435.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp43x.dtsi (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp45x-ixp46x.dtsi (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp46x-ixdp465.dts (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp4xx-reference-design.dtsi (100%) rename arch/arm/boot/dts/{ => intel/ixp}/intel-ixp4xx.dtsi (100%) create mode 100644 arch/arm/boot/dts/intel/pxa/Makefile rename arch/arm/boot/dts/{ => intel/pxa}/pxa25x.dtsi (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa27x.dtsi (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa2xx.dtsi (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-common.dtsi (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-connector.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-controller.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-speaker-l.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-speaker-m.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-speaker-one.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-speaker-s.dts (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa300-raumfeld-tuneable-clock.dtsi (100%) rename arch/arm/boot/dts/{ => intel/pxa}/pxa3xx.dtsi (100%) create mode 100644 arch/arm/boot/dts/intel/socfpga/Makefile rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_chameleonv3.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_mercury_aa1.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_mercury_pe1.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_socdk.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_socdk_nand.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_socdk_qspi.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria10_socdk_sdmmc.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria5.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_arria5_socdk.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_chameleon96.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_de0_nano_soc.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_mcv.dtsi (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_mcvevk.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_socdk.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_sockit.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_socrates.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_sodia.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_cyclone5_vining_fpga.dts (100%) rename arch/arm/boot/dts/{ => intel/socfpga}/socfpga_vt.dts (100%) create mode 100644 arch/arm/boot/dts/marvell/Makefile rename arch/arm/boot/dts/{ => marvell}/armada-370-c200-v2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-dlink-dns327l.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-mirabox.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-netgear-rn102.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-netgear-rn104.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-rd.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-nas-2bay.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-nas-4bay.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-nas-xbay.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-personal-cloud-2bay.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-personal-cloud.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-seagate-personal-cloud.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-synology-ds213j.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370-xp.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-370.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-375-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-375.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-380.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-381-netgear-gs110emx.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-382-rd-ac3x-48g4x2xl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-atl-x530.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-clearfog-gtr-l8.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-clearfog-gtr-s4.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-clearfog-gtr.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-db-88f6820-amc.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-db-ap.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-linksys-caiman.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-linksys-cobra.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-linksys-rango.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-linksys-shelby.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-linksys.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-synology-ds116.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385-turris-omnia.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-385.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-clearfog-base.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-clearfog-pro.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-clearfog.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-clearfog.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-gp.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-helios4.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388-rd.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-388.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-38x-solidrun-microsom.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-38x.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-390-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-390.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-395-gp.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-395.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-398-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-398.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-39x.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-98dx3236.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-98dx3336.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-98dx4251.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-axpwifiap.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs305-1g-4s-bit.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs305-1g-4s.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs305-1g-4s.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs326-24g-2s-bit.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs326-24g-2s.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs326-24g-2s.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs328-4c-20s-4s-bit.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs328-4c-20s-4s.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-crs328-4c-20s-4s.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-db-dxbc2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-db-xc3-24g4xg.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-gp.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-lenovo-ix4-300d.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-linksys-mamba.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-matrix.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-mv78230.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-mv78260.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-mv78460.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-netgear-rn2120.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-openblocks-ax3-4.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp-synology-ds414.dts (100%) rename arch/arm/boot/dts/{ => marvell}/armada-xp.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/dove-cm-a510.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/dove-cubox-es.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove-cubox.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove-d2plug.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove-d3plug.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove-dove-db.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove-sbc-a510.dts (100%) rename arch/arm/boot/dts/{ => marvell}/dove.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-4i-edge-200.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-6192.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-6281.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-6282.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-98dx4122.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-b3.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-blackarmor-nas220.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-c200-v1.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-cloudbox.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-d2net.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-db-88f6281.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-db-88f6282.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-db.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dir665.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dns320.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dns325.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dnskw.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dockstar.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-dreamplug.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds109.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds110jv10.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds111.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds112.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds209.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds210.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds212.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds212j.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds409.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds409slim.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds411.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds411j.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ds411slim.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-goflexnet.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-guruplug-server-plus.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ib62x0.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-iconnect.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-iomega_ix2_200.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-is2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-km_common.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-km_fixedeth.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-km_kirkwood.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-l-50.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-laplug.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-6282.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-duo-6281.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-lsqvl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-lsvl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-lswsxl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-lswvl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation-lswxl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linkstation.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-linksys-viper.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-lschlv2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-lsxhl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-lsxl.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-mplcec4.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-mv88f6281gtw-ge.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nas2big.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-net2big.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-net5big.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-netgear_readynas_duo_v2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-netgear_readynas_nv+_v2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-netxbig.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ns2-common.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ns2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ns2lite.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ns2max.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ns2mini.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa310.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa310a.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa310s.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa320.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa325.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-nsa3x0-common.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openblocks_a6.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openblocks_a7.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openrd-base.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openrd-client.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openrd-ultimate.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-openrd.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-pogo_e02.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-pogoplug-series-4.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rd88f6192.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rd88f6281-a.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rd88f6281-z0.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rd88f6281.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rs212.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rs409.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-rs411.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-sheevaplug-common.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-sheevaplug-esata.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-sheevaplug.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-synology.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-t5325.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-topkick.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts219-6281.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts219-6282.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts219.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts419-6281.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts419-6282.dts (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood-ts419.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/kirkwood.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/mmp2-brownstone.dts (100%) rename arch/arm/boot/dts/{ => marvell}/mmp2-olpc-xo-1-75.dts (100%) rename arch/arm/boot/dts/{ => marvell}/mmp2.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/mmp3-dell-ariel.dts (100%) rename arch/arm/boot/dts/{ => marvell}/mmp3.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/mvebu-linkstation-fan.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/mvebu-linkstation-gpio-simple.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-kuroboxpro.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-lacie-d2-network.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-lacie-ethernet-disk-mini-v2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-linkstation-lschl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-linkstation-lsgl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-linkstation-lswtgl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-linkstation.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-lswsgl.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-maxtor-shared-storage-2.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-mv88f5181.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-mv88f5182.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-netgear-wnr854t.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x-rd88f5182-nas.dts (100%) rename arch/arm/boot/dts/{ => marvell}/orion5x.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/pxa168-aspenite.dts (100%) rename arch/arm/boot/dts/{ => marvell}/pxa168.dtsi (100%) rename arch/arm/boot/dts/{ => marvell}/pxa910-dkb.dts (100%) rename arch/arm/boot/dts/{ => marvell}/pxa910.dtsi (100%) create mode 100644 arch/arm/boot/dts/mediatek/Makefile rename arch/arm/boot/dts/{ => mediatek}/mt2701-evb.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt2701-pinfunc.h (100%) rename arch/arm/boot/dts/{ => mediatek}/mt2701.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6323.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6580-evbp1.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6580.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6582-prestigio-pmt5008-3g.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6582.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6589-aquaris5.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6589-fairphone-fp1.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6589.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6592-evb.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt6592.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623a-rfb-emmc.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623a-rfb-nand.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623a.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623n-bananapi-bpi-r2.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623n-rfb-emmc.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7623n.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7629-rfb.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt7629.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt8127-moose.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt8127.dtsi (100%) rename arch/arm/boot/dts/{ => mediatek}/mt8135-evbp1.dts (100%) rename arch/arm/boot/dts/{ => mediatek}/mt8135.dtsi (100%) create mode 100644 arch/arm/boot/dts/microchip/Makefile rename arch/arm/boot/dts/{ => microchip}/aks-cdu.dts (100%) rename arch/arm/boot/dts/{ => microchip}/animeo_ip.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-ariag25.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-ariettag25.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-cosino.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-cosino_mega2560.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-dvk_som60.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-dvk_su60_somc.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-dvk_su60_somc_lcm.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-foxg20.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-gatwick.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizbox.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizbox2-2.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizbox2-common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizbox3-hs.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizbox3_common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizboxmini-base.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizboxmini-common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizboxmini-mb.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-kizboxmini-rd.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-linea.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-lmu5000.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-natte.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-nattis-2-natte-2.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-q5xr5.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-qil_a9260.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sam9_l9260.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sam9x60_curiosity.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sam9x60ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d27_som1.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d27_som1_ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d27_wlsom1.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d27_wlsom1_ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d2_icp.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d2_ptc_ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d2_xplained.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d3_eds.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d3_ksz9477_evb.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d3_xplained.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d4_ma5d4.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d4_ma5d4evk.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d4_xplained.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama5d4ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-sama7g5ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-smartkiz.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-som60.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-tse850-3.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-vinco.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-wb45n.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-wb45n.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91-wb50n.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91-wb50n.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91rm9200.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91rm9200_pqfp.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91rm9200ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9260.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9260ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9261.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9261ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9263.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9263ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g15.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g15ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g20.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g20ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g20ek_2mmc.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g20ek_common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g25-gardena-smart-gateway.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g25.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g25ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g35.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g35ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9g45.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9m10g45ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9n12.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9n12ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9rl.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9rlek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x25.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x25ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x35.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x35ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_can.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_isi.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_lcd.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_macb0.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_macb1.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5_usart3.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5cm.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5dm.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9x5ek.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/at91sam9xe.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/ethernut5.dts (100%) rename arch/arm/boot/dts/{ => microchip}/evk-pro3.dts (100%) rename arch/arm/boot/dts/{ => microchip}/ge863-pro3.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-kontron-kswitch-d10-mmt-8g.dts (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-kontron-kswitch-d10-mmt.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-pcb8290.dts (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-pcb8291.dts (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x-pcb8309.dts (100%) rename arch/arm/boot/dts/{ => microchip}/lan966x.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/mpa1600.dts (100%) rename arch/arm/boot/dts/{ => microchip}/pm9g45.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sam9x60.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d2-pinfunc.h (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d2.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d29.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d31.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d31ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d33.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d33ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d34.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d34ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d35.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d35ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d36.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d36ek.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d36ek_cmp.dts (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_can.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_emac.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_gmac.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_lcd.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_mci2.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_tcb1.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3_uart.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xcm.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xcm_cmp.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xdm.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xmb.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xmb_cmp.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xmb_emac.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d3xmb_gmac.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama5d4.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/sama7g5-pinfunc.h (100%) rename arch/arm/boot/dts/{ => microchip}/sama7g5.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/tny_a9260.dts (100%) rename arch/arm/boot/dts/{ => microchip}/tny_a9260_common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/tny_a9263.dts (100%) rename arch/arm/boot/dts/{ => microchip}/tny_a9g20.dts (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9260.dts (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9260_common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9263.dts (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9g20-dab-mmx.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9g20.dts (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9g20_common.dtsi (100%) rename arch/arm/boot/dts/{ => microchip}/usb_a9g20_lpw.dts (100%) create mode 100644 arch/arm/boot/dts/moxa/Makefile rename arch/arm/boot/dts/{ => moxa}/moxart-uc7112lx.dts (100%) rename arch/arm/boot/dts/{ => moxa}/moxart.dtsi (100%) create mode 100644 arch/arm/boot/dts/nspire/Makefile rename arch/arm/boot/dts/{ => nspire}/nspire-classic.dtsi (100%) rename arch/arm/boot/dts/{ => nspire}/nspire-clp.dts (100%) rename arch/arm/boot/dts/{ => nspire}/nspire-cx.dts (100%) rename arch/arm/boot/dts/{ => nspire}/nspire-tp.dts (100%) rename arch/arm/boot/dts/{ => nspire}/nspire.dtsi (100%) create mode 100644 arch/arm/boot/dts/nuvoton/Makefile rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-common-npcm7xx.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm730-gbs.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm730-gsj-gpio.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm730-gsj.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm730-kudo.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm730.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm750-evb.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm750-pincfg-evb.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm750-runbmc-olympus.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-npcm750.dtsi (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts (100%) rename arch/arm/boot/dts/{ => nuvoton}/nuvoton-wpcm450.dtsi (100%) create mode 100644 arch/arm/boot/dts/nvidia/Makefile rename arch/arm/boot/dts/{ => nvidia}/tegra114-asus-tf701t.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra114-dalmore.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra114-roth.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra114-tn7.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra114.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-apalis-emc.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-apalis-eval.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-apalis-v1.2-eval.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-apalis-v1.2.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-apalis.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-jetson-tk1-emc.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-jetson-tk1.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan-big-emc.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan-big-fhd.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan-big.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan-blaze-emc.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan-blaze.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-nyan.dtsi (99%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-peripherals-opp.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra124-venice2.dts (99%) rename arch/arm/boot/dts/{ => nvidia}/tegra124.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-acer-a500-picasso.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-asus-tf101.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-colibri-iris.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-cpu-opp-microvolt.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-cpu-opp.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-harmony.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-medcom-wide.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-paz00.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-peripherals-opp.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-plutux.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-seaboard.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-tamonten.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-tec.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-trimslice.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20-ventana.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra20.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-apalis-eval.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-apalis-v1.1-eval.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-apalis-v1.1.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-apalis.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-lvds-display.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-E1565.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-PM269.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-common.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-memory-timings.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper-ti-pmic.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-grouper.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-tilapia-E1565.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-tilapia-memory-timings.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-nexus7-tilapia.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-tf201.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-tf300t.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-tf300tg.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-tf700t.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-asus-transformer-common.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-beaver.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-cardhu-a02.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-cardhu-a04.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-cardhu.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-cpu-opp-microvolt.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-cpu-opp.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-ouya.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-pegatron-chagall.dts (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30-peripherals-opp.dtsi (100%) rename arch/arm/boot/dts/{ => nvidia}/tegra30.dtsi (100%) create mode 100644 arch/arm/boot/dts/nxp/Makefile create mode 100644 arch/arm/boot/dts/nxp/imx/Makefile rename arch/arm/boot/dts/{ => nxp/imx}/e60k02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/e70k02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx1-ads.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx1-apf9328.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx1-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-eukrea-cpuimx25.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-eukrea-mbimxsd25-baseboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-karo-tx25.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-pdk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx25.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-apf27.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-apf27dev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-eukrea-cpuimx27.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-eukrea-mbimxsd27-baseboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-pdk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-phytec-phycard-s-rdk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-phytec-phycard-s-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-phytec-phycore-rdk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-phytec-phycore-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx27.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx31-bug.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx31-lite.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx31.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx35-eukrea-cpuimx35.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx35-eukrea-mbimxsd35-baseboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx35-pdk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx35-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx35.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx50-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx50-kobo-aura.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx50-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx50.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-apf51.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-apf51dev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-babbage.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-digi-connectcore-jsk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-digi-connectcore-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-eukrea-cpuimx51.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-eukrea-mbimxsd51-baseboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-ts4800.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-zii-rdu1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-zii-scu2-mezz.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51-zii-scu3-esb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx51.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-ard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-cx9020.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-kp-ddc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-kp-hsc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-kp.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-m53.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-m53evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-m53menlo.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-mba53.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-ppd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-qsb-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-qsb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-qsrb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-sk-imx53.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-smd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-tqma53.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-tx53-x03x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-tx53-x13x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-tx53.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-usbarmory.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-voipac-bsb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53-voipac-dmm-668.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx53.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6-logicpd-baseboard.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6-logicpd-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-alti6p.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-apf6dev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-aristainetos2_4.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-aristainetos2_7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-aristainetos_4.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-aristainetos_7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b105pv2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b105v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b125pv2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b125v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b155v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b1x5pv2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-b1x5v2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-colibri-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-colibri-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-colibri-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-cubox-i-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-cubox-i-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-cubox-i.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-dfi-fs700-m60.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-dhcom-picoitx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-eckelmann-ci4x10.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-emcon-avari.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw51xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw52xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw53xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw54xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw551x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw552x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw553x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw560x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5903.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5904.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5907.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5910.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5912.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-gw5913.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard2-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard2-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-hummingboard2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-icore-mipi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-icore-rqs.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-icore.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-kontron-samx6i.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-lanmcu.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-mamoj.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-mba6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-mba6a.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-mba6b.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-nit6xlite.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-nitrogen6x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-phytec-mira-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-phytec-pbab01.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-phytec-pfla02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-pico-dwarf.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-pico-hobbit.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-pico-nymph.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-pico-pi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-plybas.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-plym2m.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-prtmvt.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-prtrvt.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-prtvt7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-qmx6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-rex-basic.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-riotboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-sabreauto.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-sabrelite.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-sabresd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-savageboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-skov-revc-lt2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-skov-revc-lt6.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-solidsense.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tqma6a.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tqma6b.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-ts4900.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-ts7970.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6dl-comtft.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6s-8034-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6s-8034.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6s-8035-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6s-8035.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-801x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-8033-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-8033.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-80xx-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-811x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-tx6u-81xx-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-udoo.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-victgo.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-vicut1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-wandboard-revb1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-wandboard-revd1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-wandboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-draco.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-hydra.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-lynx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-orion.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-phoenix.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp4-ursa.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl-yapp43-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6dl.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-apalis-eval.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-apalis-ixora-v1.1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-apalis-ixora-v1.2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-apalis-ixora.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-apf6dev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-arm2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-b450v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-b650v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-b850v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-ba16.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-bosch-acc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-bx50v3.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-cm-fx6.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-cubox-i-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-cubox-i-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-cubox-i.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-dfi-fs700-m60.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-dhcom-pdk2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-display5-tianma-tm070-1280x768.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-display5.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-dmo-edmqmx6.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-dms-ba16.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-ds.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-emcon-avari.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-evi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gk802.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw51xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw52xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw53xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5400-a.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw54xx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw551x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw552x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw553x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw560x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5903.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5904.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5907.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5910.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5912.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-gw5913.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-h100.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard2-emmc-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard2-som-v15.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-hummingboard2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-icore-mipi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-icore-ofcap10.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-icore-ofcap12.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-icore-rqs.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-icore.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-kontron-samx6i.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-kp-tpc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-kp.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-logicpd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-marsboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-mba6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-mba6a.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-mba6b.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-mccmon6.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-nitrogen6_max.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-nitrogen6_som2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-nitrogen6x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-novena.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-phytec-mira-rdk-emmc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-phytec-mira-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-phytec-pbab01.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-phytec-pfla02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pico-dwarf.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pico-hobbit.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pico-nymph.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pico-pi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-pistachio.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-prti6q.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-prtwd2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-rex-pro.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-sabreauto.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-sabrelite.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-sabresd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-savageboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-sbc6x.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-skov-revc-lt2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-skov-revc-lt6.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-skov-reve-mi1010ait-1cp1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-solidsense.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tbs2910.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tqma6a.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tqma6b.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-ts4900.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-ts7970.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1010-comtft.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1010.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1020-comtft.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1020.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1036-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1036.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-10x0-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-1110.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-tx6q-11x0-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-udoo.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-utilite-pro.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-var-dt6customboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-vicut1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-wandboard-revb1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-wandboard-revd1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-wandboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-yapp4-crux.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-yapp4-pegasus.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q-zii-rdu2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6q.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-apalis.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-apf6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-apf6dev.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-aristainetos.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-aristainetos2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-cubox-i.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-dfi-fs700-m60.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-dhcom-drc02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-dhcom-pdk2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-dhcom-picoitx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-dhcom-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-ds.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-emcon-avari.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-emcon.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw51xx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw52xx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw53xx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw54xx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw551x.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw552x.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw553x.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw560x.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5903.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5904.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5907.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5910.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5912.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-gw5913.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-hummingboard.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-hummingboard2-emmc.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-hummingboard2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-icore-1.5.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-icore-rqs.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-icore.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-kontron-samx6i.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-mba6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-mba6a.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-mba6b.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-nit6xlite.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-nitrogen6_max.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-nitrogen6_som2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-nitrogen6x.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-mira-peb-av-02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-mira-peb-eval-01.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-mira-peb-wlbt-05.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-mira.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-pbab01.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-pfla02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-phytec-phycore-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-pico-dwarf.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-pico-hobbit.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-pico-nymph.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-pico-pi.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-pico.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-prti6q.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-rex.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sabreauto.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sabrelite.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sabresd.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-savageboard.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-skov-cpu-revc.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-skov-cpu.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-skov-revc-lt2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-solidsense.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sr-som-brcm.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sr-som-emmc.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sr-som-ti.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-sr-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tqma6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tqma6a.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tqma6b.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-ts4900.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-ts7970.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tx6-lcd.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tx6-lvds.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tx6-mb7.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-tx6.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-udoo.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-var-dart.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-vicut1-12inch.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-vicut1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-wandboard-revb1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-wandboard-revc1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-wandboard-revd1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-wandboard.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl-zii-rdu2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qdl.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-mba6b.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-nitrogen6_max.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-nitrogen6_som2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-phytec-mira-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-prtwd3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-sabreauto.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-sabresd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-tqma6b.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-tx6qp-8037-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-tx6qp-8037.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-tx6qp-8137-mb7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-tx6qp-8137.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-vicutp.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-wandboard-revd1.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-yapp4-crux-plus.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-yapp4-pegasus-plus.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp-zii-rdu2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6qp.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6s-dhcom-drc02.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-kobo-aura2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-tolino-shine2hd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-tolino-shine3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-tolino-vision.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-tolino-vision5.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl-warp.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sl.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sll-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sll-kobo-clarahd.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sll-kobo-librah2o.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sll-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sll.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-nitrogen6sx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sabreauto.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sdb-mqs.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sdb-reva.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sdb-sai.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sdb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-sdb.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-softing-vining-2000.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-udoo-neo-basic.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-udoo-neo-extended.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-udoo-neo-full.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx-udoo-neo.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6sx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-14x14-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-14x14-evk.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-ccimx6ulsbcexpress.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-ccimx6ulsbcpro.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-ccimx6ulsom.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-geam.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-imx6ull-opos6ul.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-imx6ull-opos6uldev.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-isiot-emmc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-isiot-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-isiot.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-kontron-bl-43.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-kontron-bl-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-kontron-bl.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-kontron-sl-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-kontron-sl.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-liteboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-litesom.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-opos6ul.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-opos6uldev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-phycore-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin-ff-rdk-emmc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin-ff-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin-peb-av-02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin-peb-eval-01.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin-peb-wlbt-05.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-phytec-segin.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-pico-dwarf.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-pico-hobbit.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-pico-pi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-pico.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-prti6g.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul1-mba6ulx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul1.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul2-mba6ulx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul2l-mba6ulx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ul2l.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ulx-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tqma6ulxl-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tx6ul-0010.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tx6ul-0011.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tx6ul-mainboard.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul-tx6ul.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ul.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-14x14-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-aster.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-emmc-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-emmc-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-emmc-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-emmc-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-emmc-nonwifi.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-eval-v3.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-iris-v2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-iris.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-nonwifi.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-wifi-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-wifi-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-wifi-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-wifi-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri-wifi.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcom-drc02.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcom-pdk2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcom-picoitx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcom-som-cfg-sdcard.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcom-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcor-maveo-box.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-dhcor-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-jozacp.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-kontron-bl.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-kontron-sl.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-myir-mys-6ulx-eval.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-myir-mys-6ulx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-opos6ul.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-opos6uldev.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-phycore-som.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-ff-rdk-emmc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-ff-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-lc-rdk-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-peb-av-02.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-peb-eval-01.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin-peb-wlbt-05.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-segin.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-tauri-emmc.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-tauri-nand.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-phytec-tauri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-pinfunc-snvs.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tarragon-common.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tarragon-master.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tarragon-micro.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tarragon-slave.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tarragon-slavext.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tqma6ull2-mba6ulx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tqma6ull2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tqma6ull2l-mba6ulx.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull-tqma6ull2l.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ull.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ulz-14x14-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ulz-bsh-smm-m2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx6ulz.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-colibri-aster.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-colibri-eval-v3.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-colibri-iris-v2.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-colibri-iris.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-mba7.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7-tqma7.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-cl-som-imx7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-emmc-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-emmc-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-emmc-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-emmc-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-emmc.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-flex-concentrator-mfg.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-flex-concentrator.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-mba7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-meerkat96.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-nitrogen7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pico-dwarf.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pico-hobbit.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pico-nymph.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pico-pi.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pico.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-remarkable2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-sbc-imx7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-sdb-reva.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-sdb-sht11.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-sdb.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-smegw01.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-tqma7.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-zii-rmu2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d-zii-rpu2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7d.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-colibri-aster.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-colibri-iris-v2.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-colibri-iris.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-mba7.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-tqma7.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s-warp.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7s.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7ulp-com.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7ulp-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7ulp-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imx7ulp.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imxrt1050-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imxrt1050-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/imxrt1050.dtsi (99%) rename arch/arm/boot/dts/{ => nxp/imx}/imxrt1170-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/imx}/mba6ulx.dtsi (100%) create mode 100644 arch/arm/boot/dts/nxp/lpc/Makefile rename arch/arm/boot/dts/{ => nxp/lpc}/lpc18xx.dtsi (99%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc3250-ea3250.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc3250-phy3250.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc32xx.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4337-ciaa.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4350-hitex-eval.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4350.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4357-ea4357-devkit.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4357-myd-lpc4357.dts (100%) rename arch/arm/boot/dts/{ => nxp/lpc}/lpc4357.dtsi (100%) create mode 100644 arch/arm/boot/dts/nxp/ls/Makefile rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a-iot.dts (100%) rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a-moxa-uc-8410a.dts (100%) rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a-qds.dts (100%) rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a-tsn.dts (100%) rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a-twr.dts (100%) rename arch/arm/boot/dts/{ => nxp/ls}/ls1021a.dtsi (100%) create mode 100644 arch/arm/boot/dts/nxp/mxs/Makefile rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-olinuxino.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-sansa.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-stmp378x_devb.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23-xfi3.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx23.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-apf28.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-apf28dev.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-apx4devkit.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10036.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10037.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10049.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10055.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10056.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10057.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-cfa10058.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-duckbill-2-485.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-duckbill-2-enocean.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-duckbill-2-spi.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-duckbill-2.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-duckbill.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-eukrea-mbmx283lc.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-eukrea-mbmx287lc.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-eukrea-mbmx28lc.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-lwe.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-m28.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-m28cu3.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-m28evk.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-sps1.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-ts4600.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-tx28.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28-xea.dts (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/imx28.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/mxs}/mxs-pinfunc.h (100%) create mode 100644 arch/arm/boot/dts/nxp/vf/Makefile rename arch/arm/boot/dts/{ => nxp/vf}/vf-colibri-eval-v3.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf500-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf500-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf500.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-bk4.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-colibri-eval-v3.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-colibri.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-cosmic.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-pinfunc.h (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-twr.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-cfu1.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-dev-rev-b.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-dev-rev-c.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-dev.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-scu4-aib.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-spb4.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-ssmb-dtu.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610-zii-ssmb-spu3.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610.dtsi (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610m4-colibri.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610m4-cosmic.dts (100%) rename arch/arm/boot/dts/{ => nxp/vf}/vf610m4.dtsi (98%) rename arch/arm/boot/dts/{ => nxp/vf}/vfxxx.dtsi (100%) create mode 100644 arch/arm/boot/dts/qcom/Makefile rename arch/arm/boot/dts/{ => qcom}/qcom-apq8016-sbc.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8026-asus-sparrow.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8026-huawei-sturgeon.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8026-lg-lenok.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8026-samsung-matisse-wifi.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8060-dragonboard.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-asus-nexus7-flo.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-cm-qs600.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-ifc6410.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-pins.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-sony-xperia-lagan-yuga.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064-v2.0.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8064.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8074-dragonboard.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8084-ifc6540.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8084-mtp.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-apq8084.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4018-ap120c-ac-bit.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4018-ap120c-ac.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4018-ap120c-ac.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4018-jalapeno.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk01.1-c1.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk01.1.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk04.1-c1.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk04.1-c3.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk04.1.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk07.1-c1.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk07.1-c2.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019-ap.dk07.1.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq4019.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8062-smb208.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8062.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-ap148.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-rb3011.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-smb208.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-v1.0.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-v2.0-smb208.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064-v2.0.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8064.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8065-smb208.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-ipq8065.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-mdm9615-wp8548-mangoh-green.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-mdm9615-wp8548.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-mdm9615.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8226-samsung-s3ve3g.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8226.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8660-surf.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8660.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8916-samsung-e5.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8916-samsung-e7.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8916-samsung-grandmax.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8916-samsung-serranove.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8916-smp.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8960-cdp.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8960-samsung-expressatt.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8960.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974-lge-nexus5-hammerhead.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974-sony-xperia-rhine-amami.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974-sony-xperia-rhine-honami.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974-sony-xperia-rhine.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974pro-fairphone-fp2.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974pro-oneplus-bacon.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974pro-samsung-klte.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974pro-sony-xperia-shinano-castor.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-msm8974pro.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pm8226.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pm8841.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pm8941.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pma8084.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pmx55.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-pmx65.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx55-mtp.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx55-t55.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx55-telit-fn980-tlb.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx55.dtsi (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx65-mtp.dts (100%) rename arch/arm/boot/dts/{ => qcom}/qcom-sdx65.dtsi (100%) create mode 100644 arch/arm/boot/dts/realtek/Makefile rename arch/arm/boot/dts/{ => realtek}/rtd1195-horseradish.dts (100%) rename arch/arm/boot/dts/{ => realtek}/rtd1195-mele-x1000.dts (100%) rename arch/arm/boot/dts/{ => realtek}/rtd1195.dtsi (100%) create mode 100644 arch/arm/boot/dts/renesas/Makefile rename arch/arm/boot/dts/{ => renesas}/emev2-kzm9d.dts (100%) rename arch/arm/boot/dts/{ => renesas}/emev2.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/gr-peach-audiocamerashield.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/iwg20d-q7-common.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/iwg20d-q7-dbcm-ca.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r7s72100-genmai.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r7s72100-gr-peach.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r7s72100-rskrza1.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r7s72100.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r7s9210-rza2mevb.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r7s9210.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a73a4-ape6evm.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a73a4.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7740-armadillo800eva.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7740.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742-iwg21d-q7-dbcm-ca.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742-iwg21d-q7.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742-iwg21m.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7742.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7743-iwg20d-q7-dbcm-ca.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7743-iwg20d-q7.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7743-iwg20m.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7743-sk-rzg1m.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7743.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7744-iwg20d-q7-dbcm-ca.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7744-iwg20d-q7.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7744-iwg20m.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7744.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7745-iwg22d-sodimm-dbhd-ca.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7745-iwg22d-sodimm.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7745-iwg22m.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7745-sk-rzg1e.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7745.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a77470-iwg23s-sbc.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a77470.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7778-bockw.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7778.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7779-marzen.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7779.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7790-lager.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7790-stout.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7790.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7791-koelsch.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7791-porter.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7791.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7792-blanche.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7792-wheat.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7792.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7793-gose.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7793.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7794-alt.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7794-silk.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r8a7794.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r8a77xx-aa121td01-panel.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/r9a06g032-rzn1d400-db.dts (100%) rename arch/arm/boot/dts/{ => renesas}/r9a06g032.dtsi (100%) rename arch/arm/boot/dts/{ => renesas}/sh73a0-kzm9g.dts (100%) rename arch/arm/boot/dts/{ => renesas}/sh73a0.dtsi (100%) create mode 100644 arch/arm/boot/dts/rockchip/Makefile rename arch/arm/boot/dts/{ => rockchip}/rk3036-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3036-kylin.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3036.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3066a-bqcurie2.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3066a-marsboard.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3066a-mk808.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3066a-rayeager.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3066a.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3128-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3128.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3188-bqedison2qc.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3188-px3-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3188-radxarock.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3188.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3228-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3229-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3229-xms6.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3229.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk322x.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-evb-act8846.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-evb-rk808.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-evb.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-firefly-beta.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-firefly-reload-core.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-firefly-reload.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-firefly.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-firefly.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-miqi.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-phycore-rdk.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-phycore-som.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-popmetal.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-r89.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-rock-pi-n8.dts (86%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-rock2-som.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-rock2-square.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-tinker-s.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-tinker.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-tinker.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-analog-audio.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-brain.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-broadcom-bluetooth.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-chromebook.dtsi (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-edp.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-fievel.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-jaq.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-jerry.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-mickey.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-mighty.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-minnie.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-pinky.dts (98%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-sdmmc.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-speedy.dts (99%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron-tiger.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-veyron.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-vmarc-som.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288-vyasa.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3288.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rk3xxx.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rockchip-radxa-dalang-carrier.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1108-elgin-r1.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1108-evb.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1108.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1126-edgeble-neu2-io.dts (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1126-edgeble-neu2.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1126-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => rockchip}/rv1126.dtsi (100%) create mode 100644 arch/arm/boot/dts/samsung/Makefile rename arch/arm/boot/dts/{ => samsung}/exynos-mfc-reserved-memory.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos-pinctrl.h (100%) rename arch/arm/boot/dts/{ => samsung}/exynos-syscon-restart.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250-artik5-eval.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250-artik5.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250-monk.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250-rinato.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos3250.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4-cpu-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-i9100.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-origen.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-smdkv310.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-trats.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210-universal_c210.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4210.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4212.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-galaxy-s3.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-i9300.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-i9305.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-itop-elite.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-itop-scp-core.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-midas.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-n710x.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-odroid-common.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-odroidu3.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-odroidx.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-odroidx2.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-origen.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-p4note-n8010.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-p4note.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-ppmu-common.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-prime.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-smdk4412.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-tiny4412.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412-trats2.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4412.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4x12-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos4x12.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-arndale.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-smdk5250.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-snow-common.dtsi (99%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-snow-rev5.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-snow.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5250-spring.dts (99%) rename arch/arm/boot/dts/{ => samsung}/exynos5250.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5260-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5260-xyref5260.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5260.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5410-odroidxu.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5410-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5410-smdk5410.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5410.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-arndale-octa.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-chagall-wifi.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-cpus.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-galaxy-tab-common.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-klimt-wifi.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-peach-pit.dts (99%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-smdk5420.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420-trip-points.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5420.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-cpus.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroid-core.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidhc1.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidxu3-audio.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidxu3-common.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidxu3-lite.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidxu3.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-odroidxu4.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5422-samsung-k3g.dts (100%) rename arch/arm/boot/dts/{ => samsung}/exynos54xx-odroidxu-leds.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos54xx.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/exynos5800-peach-pi.dts (99%) rename arch/arm/boot/dts/{ => samsung}/exynos5800.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s3c6400.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s3c6410-mini6410.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s3c6410-smdk6410.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s3c6410.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s3c64xx-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s3c64xx-pinctrl.h (100%) rename arch/arm/boot/dts/{ => samsung}/s3c64xx.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-aquila.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-aries.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-fascinate4g.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-galaxys.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-goni.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-pinctrl.h (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-smdkc110.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-smdkv210.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210-torbreck.dts (100%) rename arch/arm/boot/dts/{ => samsung}/s5pv210.dtsi (100%) create mode 100644 arch/arm/boot/dts/sigmastar/Makefile rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity-breadbee-common.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity-msc313-breadbee_crust.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity-msc313.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd201-som2d01.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-miyoo-mini.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-ssd201htv2.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-unitv2.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd202d.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m-ssd20xd.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity2m.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity3-msc313e-breadbee.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity3-msc313e.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-infinity3.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-mercury5-ssc8336n-midrived08.dts (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-mercury5-ssc8336n.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-mercury5.dtsi (100%) rename arch/arm/boot/dts/{ => sigmastar}/mstar-v7.dtsi (100%) create mode 100644 arch/arm/boot/dts/socionext/Makefile rename arch/arm/boot/dts/{ => socionext}/milbeaut-m10v-evb.dts (100%) rename arch/arm/boot/dts/{ => socionext}/milbeaut-m10v.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-ld4-ref.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-ld4.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-ld6b-ref.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-ld6b.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro4-ace.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro4-ref.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro4-sanji.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro4.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro5-epcore.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro5-proex.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pro5.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pxs2-gentil.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pxs2-vodka.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-pxs2.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-ref-daughter.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-sld8-ref.dts (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-sld8.dtsi (100%) rename arch/arm/boot/dts/{ => socionext}/uniphier-support-card.dtsi (100%) create mode 100644 arch/arm/boot/dts/st/Makefile rename arch/arm/boot/dts/{ => st}/spear1310-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear1310.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear1340-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear1340.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear13xx.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear300-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear300.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear310-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear310.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear320-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear320-hmi.dts (100%) rename arch/arm/boot/dts/{ => st}/spear320.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear320s.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear3xx.dtsi (100%) rename arch/arm/boot/dts/{ => st}/spear600-evb.dts (100%) rename arch/arm/boot/dts/{ => st}/spear600.dtsi (100%) rename arch/arm/boot/dts/{ => st}/st-pincfg.h (100%) rename arch/arm/boot/dts/{ => st}/ste-ab8500.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-ab8505.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-db8500.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-db8520.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-db9500.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-dbx5x0-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-dbx5x0.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href-ab8500.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href-family-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href-stuib.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href-tvk1281618-r2.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href-tvk1281618-r3.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-href520-tvk.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefprev60-stuib.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefprev60-tvk.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefprev60.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefv60plus-stuib.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefv60plus-tvk.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-hrefv60plus.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-nomadik-nhk15.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-nomadik-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-nomadik-s8815.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-nomadik-stn8815.dtsi (100%) rename arch/arm/boot/dts/{ => st}/ste-snowball.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-codina-tmo.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-codina.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-gavini.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-golden.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-janice.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-kyle.dts (100%) rename arch/arm/boot/dts/{ => st}/ste-ux500-samsung-skomer.dts (100%) rename arch/arm/boot/dts/{ => st}/stih407-b2120.dts (100%) rename arch/arm/boot/dts/{ => st}/stih407-clock.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih407-family.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih407-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih407.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih410-b2120.dts (100%) rename arch/arm/boot/dts/{ => st}/stih410-b2260.dts (100%) rename arch/arm/boot/dts/{ => st}/stih410-clock.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih410-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih410.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih418-b2199.dts (100%) rename arch/arm/boot/dts/{ => st}/stih418-b2264.dts (100%) rename arch/arm/boot/dts/{ => st}/stih418-clock.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stih418.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stihxxx-b2120.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32429i-eval.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32746g-eval.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32f4-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f429-disco.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32f429-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f429.dtsi (99%) rename arch/arm/boot/dts/{ => st}/stm32f469-disco.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32f469-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f469.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f7-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f746-disco.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32f746-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32f746.dtsi (99%) rename arch/arm/boot/dts/{ => st}/stm32f769-disco.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32f769-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32h7-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32h743.dtsi (99%) rename arch/arm/boot/dts/{ => st}/stm32h743i-disco.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32h743i-eval.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32h750.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32h750i-art-pi.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp13-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp131.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp133.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp135.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp135f-dk.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp13xc.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp13xf.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15-scmi.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151a-dhcor-testbench.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151a-prtt1a.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151a-prtt1c.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151a-prtt1l.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp151a-prtt1s.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp153.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp153c-dhcom-drc02.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp153c-dhcor-drc-compact.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-avenger96.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-dhcor-avenger96.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-dk1-scmi.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-dk1.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-icore-stm32mp1-ctouch2.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-icore-stm32mp1-edimm2.2.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-icore-stm32mp1.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-iot-box.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-microgea-stm32mp1-microdev2.0.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-microgea-stm32mp1.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-stinger96.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157a-stinger96.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-dhcom-pdk2.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-dhcom-picoitx.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-dk2-scmi.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-dk2.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-ed1-scmi.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-ed1.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-emsbc-argon.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-emstamp-argon.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-ev1-scmi.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-ev1.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-lxa-mc1.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-odyssey-som.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-odyssey.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-phycore-stm32mp1-3.dts (100%) rename arch/arm/boot/dts/{ => st}/stm32mp157c-phycore-stm32mp15-som.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xc.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcom-drc02.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcom-pdk2.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcom-picoitx.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcom-som.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcor-avenger96.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcor-drc-compact.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcor-io1v8.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcor-som.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dhcor-testbench.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-dkx.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xx-osd32.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xxaa-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xxab-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xxac-pinctrl.dtsi (100%) rename arch/arm/boot/dts/{ => st}/stm32mp15xxad-pinctrl.dtsi (100%) create mode 100644 arch/arm/boot/dts/sunplus/Makefile rename arch/arm/boot/dts/{ => sunplus}/sunplus-sp7021-achip.dtsi (100%) rename arch/arm/boot/dts/{ => sunplus}/sunplus-sp7021-demo-v3.dts (100%) rename arch/arm/boot/dts/{ => sunplus}/sunplus-sp7021.dtsi (100%) create mode 100644 arch/arm/boot/dts/synaptics/Makefile rename arch/arm/boot/dts/{ => synaptics}/berlin2-sony-nsz-gs7.dts (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2.dtsi (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2cd-google-chromecast.dts (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2cd-valve-steamlink.dts (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2cd.dtsi (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2q-marvell-dmp.dts (100%) rename arch/arm/boot/dts/{ => synaptics}/berlin2q.dtsi (100%) create mode 100644 arch/arm/boot/dts/ti/Makefile create mode 100644 arch/arm/boot/dts/ti/davinci/Makefile rename arch/arm/boot/dts/{ => ti/davinci}/da850-enbw-cmc.dts (100%) rename arch/arm/boot/dts/{ => ti/davinci}/da850-evm.dts (99%) rename arch/arm/boot/dts/{ => ti/davinci}/da850-lcdk.dts (100%) rename arch/arm/boot/dts/{ => ti/davinci}/da850-lego-ev3.dts (100%) rename arch/arm/boot/dts/{ => ti/davinci}/da850.dtsi (100%) create mode 100644 arch/arm/boot/dts/ti/keystone/Makefile rename arch/arm/boot/dts/{ => ti/keystone}/keystone-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2e-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2e-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2e-netcp.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2e.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2g-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2g-ice.dts (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2g-netcp.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2g.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2hk-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2hk-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2hk-netcp.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2hk.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2l-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2l-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2l-netcp.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone-k2l.dtsi (100%) rename arch/arm/boot/dts/{ => ti/keystone}/keystone.dtsi (100%) create mode 100644 arch/arm/boot/dts/ti/omap/Makefile rename arch/arm/boot/dts/{ => ti/omap}/am335x-baltos-ir2110.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-baltos-ir3220.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-baltos-ir5221.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-baltos-leds.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-baltos.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-base0033.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-bone-common.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-bone.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-boneblack-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-boneblack-hdmi.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-boneblack-wireless.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-boneblack.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-boneblue.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-bonegreen-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-bonegreen-wireless.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-bonegreen.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-chiliboard.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-chilisom.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-cm-t335.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-evm.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-evmsk.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-guardian.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-icev2.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-igep0033.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-lxm.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-moxa-uc-2100-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-moxa-uc-2101.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-moxa-uc-8100-common.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-moxa-uc-8100-me-t.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-myirtech-myc.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-myirtech-myd.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-nano.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-netcan-plus-1xx.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-netcom-plus-2xx.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-netcom-plus-8xx.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-osd3358-sm-red.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-osd335x-common.dtsi (98%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-pcm-953.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-pdu001.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-pepper.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-phycore-rdk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-phycore-som.dtsi (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-pocketbeagle.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-regor-rdk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-regor.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sancloud-bbe-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sancloud-bbe-extended-wifi.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sancloud-bbe-lite.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sancloud-bbe.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sbc-t335.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-shc.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-sl50.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-wega-rdk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am335x-wega.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am33xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am33xx-l4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am33xx.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3517-craneboard.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/am3517-evm-ui.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3517-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3517-som.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3517.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3517_mt_ventoux.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am35xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3703.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3715.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am3874-iceboard.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am4372.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-cm-t43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-gp-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-idk-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-l4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-sbc-t43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am437x-sk-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am43x-epos-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am43xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57-pruss.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am5718.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am571x-idk-touchscreen.dtso (100%) rename arch/arm/boot/dts/{ => ti/omap}/am571x-idk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am5728.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am5729-beagleboneai.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am572x-idk-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am572x-idk-touchscreen.dtso (100%) rename arch/arm/boot/dts/{ => ti/omap}/am572x-idk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am5748.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am574x-idk.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-beagle-x15-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-beagle-x15-revb1.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-beagle-x15-revc.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-beagle-x15.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-cl-som-am57x.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-commercial-grade.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-evm.dtso (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-idk-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-idk-lcd-osd101t2045.dtso (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-idk-lcd-osd101t2587.dtso (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-industrial-grade.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/am57xx-sbc-am57x.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/compulab-sb-som.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm3725.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm8148-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm8148-t410.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm814x-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm814x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm8168-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm816x-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dm816x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra62x-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra62x-j5eco-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra62x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-dspeve-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-evm-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-ipu-dsp-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-iva-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-l4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7-mmc-iodelay.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra71-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra71x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72-evm-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72-evm-revc.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72-evm-tps65917.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72x-mmc-iodelay.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra72x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra74-ipu-dsp-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra74x-mmc-iodelay.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra74x-p.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra74x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra76-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra76x-mmc-iodelay.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra76x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/dra7xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/elpida_ecb240abacn.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-som-lv-35xx-devkit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-som-lv-37xx-devkit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-som-lv-baseboard.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-som-lv.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-torpedo-35xx-devkit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-torpedo-37xx-devkit-28.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-torpedo-37xx-devkit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-torpedo-baseboard.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/logicpd-torpedo-som.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/motorola-cpcap-mapphone.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/motorola-mapphone-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap-gpmc-smsc911x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap-gpmc-smsc9221.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap-zoom-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-h4.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-n800.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-n810-wimax.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-n810.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420-n8x0-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2420.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2430-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2430-sdp.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap2430.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap24xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-beagle-ab4.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-beagle-xm-ab.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-beagle-xm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-beagle.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cm-t3517.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cm-t3530.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cm-t3730.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cm-t3x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cm-t3x30.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-cpu-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-devkit8000-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-devkit8000-lcd-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-devkit8000-lcd43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-devkit8000-lcd70.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-devkit8000.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-echo.dts (99%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-evm-37xx.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-evm-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-evm-processor-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-evm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-gta04.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-gta04a3.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-gta04a4.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-gta04a5.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-gta04a5one.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-ha-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-ha-lcd.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-ha.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0020-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0020-rev-f.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0020.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0030-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0030-rev-g.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-igep0030.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-ldp.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-lilly-a83x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-lilly-dbb056.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-n9.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-n900.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-n950-n9.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-n950.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-alto35-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-alto35.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-base.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-chestnut43-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-chestnut43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-common-dvi.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-common-lcd35.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-common-lcd43.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-common-peripherals.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-gallop43-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-gallop43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-palo35-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-palo35.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-palo43-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-palo43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-alto35.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-chestnut43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-gallop43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-palo35.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-palo43.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-summit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-tobi.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm-tobiduo.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-storm.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-summit-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-summit.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-tobi-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-tobi.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-tobiduo-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo-tobiduo.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-overo.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-pandora-1ghz.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-pandora-600mhz.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-pandora-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-panel-sharp-ls037v7dw01.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-sb-t35.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-sbc-t3517.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-sbc-t3530.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-sbc-t3730.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-sniper.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-tao3530.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-thunder.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3-zoom3.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3430-sdp.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3430es1-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap34xx-omap36xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap34xx.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap36xx-am35xx-omap3430es2plus-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap36xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap36xx-omap3430es2plus-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap36xx.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap3xxx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-cpu-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-droid-bionic-xt875.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-droid4-xt894.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-duovero-parlor.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-duovero.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-epson-embt2ws.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-kc1.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-l4-abe.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-l4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-mcpdm.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-panda-a4.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-panda-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-panda-es.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-panda.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-sdp-es23plus.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-sdp.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-var-dvk-om44.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-var-om44customboard.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-var-som-om44-wlan.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-var-som-om44.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4-var-stk-om44.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap443x-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap443x.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap4460.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap446x-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap44xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-board-common.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-cm-t54.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-core-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-gpu-thermal.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-igep0050.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-l4-abe.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-l4.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-sbc-t54.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5-uevm.dts (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap5.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/omap54xx-clocks.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/twl4030.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/twl4030_omap3.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/twl6030.dtsi (100%) rename arch/arm/boot/dts/{ => ti/omap}/twl6030_omap4.dtsi (100%) create mode 100644 arch/arm/boot/dts/unisoc/Makefile rename arch/arm/boot/dts/{ => unisoc}/rda8810pl-orangepi-2g-iot.dts (100%) rename arch/arm/boot/dts/{ => unisoc}/rda8810pl-orangepi-i96.dts (100%) rename arch/arm/boot/dts/{ => unisoc}/rda8810pl.dtsi (100%) create mode 100644 arch/arm/boot/dts/vt8500/Makefile rename arch/arm/boot/dts/{ => vt8500}/vt8500-bv07.dts (100%) rename arch/arm/boot/dts/{ => vt8500}/vt8500.dtsi (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8505-ref.dts (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8505.dtsi (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8650-mid.dts (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8650.dtsi (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8750-apc8750.dts (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8750.dtsi (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8850-w70v2.dts (100%) rename arch/arm/boot/dts/{ => vt8500}/wm8850.dtsi (100%) create mode 100644 arch/arm/boot/dts/xen/Makefile rename arch/arm/boot/dts/{ => xen}/xenvm-4.2.dts (100%) create mode 100644 arch/arm/boot/dts/xilinx/Makefile rename arch/arm/boot/dts/{ => xilinx}/zynq-7000.dtsi (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-cc108.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-ebaz4205.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-microzed.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-parallella.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc702.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc706.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc770-xm010.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc770-xm011.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc770-xm012.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zc770-xm013.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zed.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zturn-common.dtsi (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zturn-v5.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zturn.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zybo-z7.dts (100%) rename arch/arm/boot/dts/{ => xilinx}/zynq-zybo.dts (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 9b7d23efc2703..f304b54e33d4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1664,9 +1664,9 @@ F: Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml F: Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml -F: arch/arm/boot/dts/arm-realview-* -F: arch/arm/boot/dts/integrator* -F: arch/arm/boot/dts/versatile* +F: arch/arm/boot/dts/arm/arm-realview-* +F: arch/arm/boot/dts/arm/integrator* +F: arch/arm/boot/dts/arm/versatile* F: arch/arm/mach-versatile/ F: drivers/bus/arm-integrator-lm.c F: drivers/clk/versatile/ @@ -1837,7 +1837,7 @@ F: Documentation/devicetree/bindings/net/actions,owl-emac.yaml F: Documentation/devicetree/bindings/pinctrl/actions,* F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt -F: arch/arm/boot/dts/owl-* +F: arch/arm/boot/dts/actions/ F: arch/arm/mach-actions/ F: arch/arm64/boot/dts/actions/ F: drivers/clk/actions/ @@ -1910,7 +1910,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-amlogic@lists.infradead.org S: Maintained W: http://linux-meson.com/ -F: arch/arm/boot/dts/meson* +F: arch/arm/boot/dts/amlogic/ F: arch/arm/mach-meson/ F: arch/arm64/boot/dts/amlogic/ F: drivers/mmc/host/meson* @@ -1924,7 +1924,7 @@ M: Tsahee Zidenberg M: Antoine Tenart L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/alpine* +F: arch/arm/boot/dts/amazon/ F: arch/arm/mach-alpine/ F: arch/arm64/boot/dts/amazon/ F: drivers/*/*alpine* @@ -1995,7 +1995,7 @@ M: Lars Persson L: linux-arm-kernel@axis.com S: Maintained F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt -F: arch/arm/boot/dts/artpec6* +F: arch/arm/boot/dts/axis/ F: arch/arm/mach-artpec F: drivers/clk/axis F: drivers/crypto/axis @@ -2023,7 +2023,7 @@ S: Supported Q: https://patchwork.ozlabs.org/project/linux-aspeed/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed.git F: Documentation/devicetree/bindings/arm/aspeed/ -F: arch/arm/boot/dts/aspeed-* +F: arch/arm/boot/dts/aspeed/ F: arch/arm/mach-aspeed/ N: aspeed @@ -2042,8 +2042,7 @@ ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/ecx-*.dts* -F: arch/arm/boot/dts/highbank.dts +F: arch/arm/boot/dts/calxeda/ F: arch/arm/mach-highbank/ ARM/CAVIUM THUNDER NETWORK DRIVER @@ -2091,7 +2090,7 @@ ARM/CONEXANT DIGICOLOR MACHINE SUPPORT M: Baruch Siach L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/cx92755* +F: arch/arm/boot/dts/cnxt/ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS @@ -2130,7 +2129,7 @@ F: Documentation/devicetree/bindings/arm/gemini.yaml F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.yaml -F: arch/arm/boot/dts/gemini* +F: arch/arm/boot/dts/gemini/ F: arch/arm/mach-gemini/ F: drivers/crypto/gemini/ F: drivers/net/ethernet/cortina/ @@ -2183,7 +2182,8 @@ R: NXP Linux Team L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm64/boot/dts/freescale/ +F: arch/arm/boot/dts/nxp/imx/ +F: arch/arm/boot/dts/nxp/mxs/ X: arch/arm64/boot/dts/freescale/fsl-* X: arch/arm64/boot/dts/freescale/qoriq-* X: drivers/media/i2c/ @@ -2196,7 +2196,7 @@ M: Li Yang L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/ls1021a* +F: arch/arm/boot/dts/nxp/ls/ F: arch/arm64/boot/dts/freescale/fsl-* F: arch/arm64/boot/dts/freescale/qoriq-* @@ -2208,7 +2208,7 @@ R: Stefan Agner L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git -F: arch/arm/boot/dts/vf* +F: arch/arm/boot/dts/nxp/vf/ F: arch/arm/mach-imx/*vf610* ARM/GUMSTIX MACHINE SUPPORT @@ -2222,9 +2222,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.hisilicon.com T: git https://github.com/hisilicon/linux-hisi.git -F: arch/arm/boot/dts/hi3* -F: arch/arm/boot/dts/hip* -F: arch/arm/boot/dts/hisi* +F: arch/arm/boot/dts/hisilicon/ F: arch/arm/mach-hisi/ F: arch/arm64/boot/dts/hisilicon/ @@ -2246,8 +2244,7 @@ F: Documentation/devicetree/bindings/i2c/hpe,gxp-i2c.yaml F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst -F: arch/arm/boot/dts/hpe-bmc* -F: arch/arm/boot/dts/hpe-gxp* +F: arch/arm/boot/dts/hpe/ F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c @@ -2261,7 +2258,7 @@ M: Javier Martinez Canillas L: linux-omap@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/omap3-igep* +F: arch/arm/boot/dts/ti/omap/omap3-igep* ARM/INTEL IXP4XX ARM ARCHITECTURE M: Linus Walleij @@ -2274,7 +2271,7 @@ F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml -F: arch/arm/boot/dts/intel-ixp* +F: arch/arm/boot/dts/intel/ixp/ F: arch/arm/mach-ixp4xx/ F: drivers/bus/intel-ixp4xx-eb.c F: drivers/clocksource/timer-ixp4xx.c @@ -2306,7 +2303,7 @@ M: Vladimir Zapolskiy L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/i2c/i2c-lpc2k.txt -F: arch/arm/boot/dts/lpc43* +F: arch/arm/boot/dts/nxp/lpc/lpc43* F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/controllers/nxp-spifi.c @@ -2319,7 +2316,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/vzapolskiy/linux-lpc32xx.git F: Documentation/devicetree/bindings/i2c/i2c-pnx.txt -F: arch/arm/boot/dts/lpc32* +F: arch/arm/boot/dts/nxp/lpc/lpc32* F: arch/arm/mach-lpc32xx/ F: drivers/i2c/busses/i2c-pnx.c F: drivers/net/ethernet/nxp/lpc_eth.c @@ -2337,8 +2334,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt F: Documentation/devicetree/bindings/soc/dove/ -F: arch/arm/boot/dts/dove* -F: arch/arm/boot/dts/orion5x* +F: arch/arm/boot/dts/marvell/dove* +F: arch/arm/boot/dts/marvell/orion5x* F: arch/arm/mach-dove/ F: arch/arm/mach-mv78xx0/ F: arch/arm/mach-orion5x/ @@ -2353,8 +2350,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ -F: arch/arm/boot/dts/armada* -F: arch/arm/boot/dts/kirkwood* +F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ F: arch/arm64/boot/dts/marvell/armada* @@ -2388,10 +2385,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained W: https://mtk.wiki.kernel.org/ C: irc://irc.libera.chat/linux-mediatek -F: arch/arm/boot/dts/mt2* -F: arch/arm/boot/dts/mt6* -F: arch/arm/boot/dts/mt7* -F: arch/arm/boot/dts/mt8* +F: arch/arm/boot/dts/mediatek/ F: arch/arm/mach-mediatek/ F: arch/arm64/boot/dts/mediatek/ F: drivers/soc/mediatek/ @@ -2415,10 +2409,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported W: http://www.linux4sam.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git -F: arch/arm/boot/dts/at91*.dts -F: arch/arm/boot/dts/at91*.dtsi -F: arch/arm/boot/dts/sama*.dts -F: arch/arm/boot/dts/sama*.dtsi +F: arch/arm/boot/dts/microchip/at91* +F: arch/arm/boot/dts/microchip/sama* F: arch/arm/include/debug/at91.S F: arch/arm/mach-at91/ F: drivers/memory/atmel* @@ -2447,7 +2439,7 @@ M: Taichi Sugaya M: Takao Orito L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/milbeaut* +F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut @@ -2461,7 +2453,7 @@ T: git git://github.com/linux-chenxing/linux.git F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml -F: arch/arm/boot/dts/mstar-* +F: arch/arm/boot/dts/sigmastar/ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c @@ -2480,7 +2472,7 @@ F: Documentation/devicetree/bindings/arm/ste-* F: Documentation/devicetree/bindings/arm/ux500.yaml F: Documentation/devicetree/bindings/arm/ux500/ F: Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml -F: arch/arm/boot/dts/ste-* +F: arch/arm/boot/dts/st/ste-* F: arch/arm/mach-nomadik/ F: arch/arm/mach-ux500/ F: drivers/clk/clk-nomadik.c @@ -2510,7 +2502,7 @@ F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* F: Documentation/devicetree/bindings/arm/npcm/* F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml -F: arch/arm/boot/dts/nuvoton-npcm* +F: arch/arm/boot/dts/nuvoton/nuvoton-npcm* F: arch/arm/mach-npcm/ F: arch/arm64/boot/dts/nuvoton/ F: drivers/*/*/*npcm* @@ -2525,7 +2517,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* -F: arch/arm/boot/dts/nuvoton-wpcm450* +F: arch/arm/boot/dts/nuvoton/nuvoton-wpcm450* F: arch/arm/configs/wpcm450_defconfig F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*/*wpcm* @@ -2572,8 +2564,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git F: Documentation/devicetree/bindings/*/qcom* F: Documentation/devicetree/bindings/soc/qcom/ -F: arch/arm/boot/dts/qcom-*.dts -F: arch/arm/boot/dts/qcom-*.dtsi +F: arch/arm/boot/dts/qcom/ F: arch/arm/configs/qcom_defconfig F: arch/arm/mach-qcom/ F: arch/arm64/boot/dts/qcom/ @@ -2616,7 +2607,7 @@ F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.yaml F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml -F: arch/arm/boot/dts/rda8810pl-* +F: arch/arm/boot/dts/unisoc/ F: drivers/clocksource/timer-rda.c F: drivers/gpio/gpio-rda.c F: drivers/irqchip/irq-rda-intc.c @@ -2628,7 +2619,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/realtek.yaml -F: arch/arm/boot/dts/rtd* +F: arch/arm/boot/dts/realtek/ F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ @@ -2642,13 +2633,7 @@ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml F: Documentation/devicetree/bindings/soc/renesas/ -F: arch/arm/boot/dts/emev2* -F: arch/arm/boot/dts/gr-peach* -F: arch/arm/boot/dts/iwg20d-q7* -F: arch/arm/boot/dts/r7s* -F: arch/arm/boot/dts/r8a* -F: arch/arm/boot/dts/r9a* -F: arch/arm/boot/dts/sh* +F: arch/arm/boot/dts/renesas/ F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ @@ -2681,8 +2666,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml -F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv11* +F: arch/arm/boot/dts/rockchip/ F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* @@ -2706,9 +2690,7 @@ F: Documentation/devicetree/bindings/arm/samsung/ F: Documentation/devicetree/bindings/hwinfo/samsung,* F: Documentation/devicetree/bindings/power/pd-samsung.yaml F: Documentation/devicetree/bindings/soc/samsung/ -F: arch/arm/boot/dts/exynos* -F: arch/arm/boot/dts/s3c* -F: arch/arm/boot/dts/s5p* +F: arch/arm/boot/dts/samsung/ F: arch/arm/mach-exynos*/ F: arch/arm/mach-s3c/ F: arch/arm/mach-s5p*/ @@ -2768,7 +2750,7 @@ M: Dinh Nguyen S: Maintained W: http://www.rocketboards.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git -F: arch/arm/boot/dts/socfpga* +F: arch/arm/boot/dts/intel/socfpga/ F: arch/arm/configs/socfpga_defconfig F: arch/arm/mach-socfpga/ F: arch/arm64/boot/dts/altera/ @@ -2801,7 +2783,7 @@ S: Maintained W: http://www.stlinux.com F: Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml F: Documentation/devicetree/bindings/spi/st,ssc-spi.yaml -F: arch/arm/boot/dts/sti* +F: arch/arm/boot/dts/st/sti* F: arch/arm/mach-sti/ F: drivers/ata/ahci_st.c F: drivers/char/hw_random/st-rng.c @@ -2834,7 +2816,7 @@ L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-next -F: arch/arm/boot/dts/stm32* +F: arch/arm/boot/dts/st/stm32* F: arch/arm/mach-stm32/ F: drivers/clocksource/armv7m_systick.c N: stm32 @@ -2849,7 +2831,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml -F: arch/arm/boot/dts/sunplus-sp7021*.dts* +F: arch/arm/boot/dts/sunplus/ F: arch/arm/configs/sp7021_*defconfig F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c @@ -2863,7 +2845,7 @@ M: Jisheng Zhang M: Sebastian Hesselbarth L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/berlin* +F: arch/arm/boot/dts/synaptics/ F: arch/arm/mach-berlin/ F: arch/arm64/boot/dts/synaptics/ @@ -2905,7 +2887,7 @@ M: Santosh Shilimkar L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -F: arch/arm/boot/dts/keystone-* +F: arch/arm/boot/dts/ti/keystone/ F: arch/arm/mach-keystone/ ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK @@ -2970,7 +2952,7 @@ F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml -F: arch/arm/boot/dts/uniphier* +F: arch/arm/boot/dts/socionext/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ F: arch/arm/mm/cache-uniphier.c @@ -2995,7 +2977,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: */*/*/vexpress* F: */*/vexpress* -F: arch/arm/boot/dts/vexpress* +F: arch/arm/boot/dts/arm/vexpress* F: arch/arm/mach-versatile/ F: arch/arm64/boot/dts/arm/ F: drivers/clk/versatile/clk-vexpress-osc.c @@ -3402,10 +3384,10 @@ AXENTIA ARM DEVICES M: Peter Rosin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/at91-linea.dtsi -F: arch/arm/boot/dts/at91-natte.dtsi -F: arch/arm/boot/dts/at91-nattis-2-natte-2.dts -F: arch/arm/boot/dts/at91-tse850-3.dts +F: arch/arm/boot/dts/microchip/at91-linea.dtsi +F: arch/arm/boot/dts/microchip/at91-natte.dtsi +F: arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts +F: arch/arm/boot/dts/microchip/at91-tse850-3.dts AXENTIA ASOC DRIVERS M: Peter Rosin @@ -3961,10 +3943,10 @@ M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm-ns.dtsi -F: arch/arm/boot/dts/bcm470* -F: arch/arm/boot/dts/bcm5301* -F: arch/arm/boot/dts/bcm953012* +F: arch/arm/boot/dts/broadcom/bcm-ns.dtsi +F: arch/arm/boot/dts/broadcom/bcm470* +F: arch/arm/boot/dts/broadcom/bcm5301* +F: arch/arm/boot/dts/broadcom/bcm953012* F: arch/arm/mach-bcm/bcm_5301x.c BROADCOM BCM53573 ARM ARCHITECTURE @@ -3973,8 +3955,8 @@ M: Rafał Miłecki R: Broadcom internal kernel review list L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: arch/arm/boot/dts/bcm47189* -F: arch/arm/boot/dts/bcm53573* +F: arch/arm/boot/dts/broadcom/bcm47189* +F: arch/arm/boot/dts/broadcom/bcm53573* BROADCOM BCM63XX/BCM33XX UDC DRIVER M: Kevin Cernekee @@ -3989,7 +3971,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git https://github.com/broadcom/stblinux.git F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml -F: arch/arm/boot/dts/bcm7*.dts* +F: arch/arm/boot/dts/broadcom/bcm7*.dts* F: arch/arm/include/asm/hardware/cache-b15-rac.h F: arch/arm/mach-bcm/*brcmstb* F: arch/arm/mm/cache-b15-rac.c @@ -5990,15 +5972,15 @@ DH ELECTRONICS IMX6 DHCOM/DHCOR BOARD SUPPORT M: Christoph Niedermaier L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/imx6*-dhcom-* -F: arch/arm/boot/dts/imx6*-dhcor-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcom-* +F: arch/arm/boot/dts/nxp/imx/imx6*-dhcor-* DH ELECTRONICS STM32MP1 DHCOM/DHCOR BOARD SUPPORT M: Marek Vasut L: kernel@dh-electronics.com S: Maintained -F: arch/arm/boot/dts/stm32mp1*-dhcom-* -F: arch/arm/boot/dts/stm32mp1*-dhcor-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcom-* +F: arch/arm/boot/dts/st/stm32mp1*-dhcor-* DIALOG SEMICONDUCTOR DRIVERS M: Support Opensource @@ -11732,7 +11714,7 @@ LEGO MINDSTORMS EV3 R: David Lechner S: Maintained F: Documentation/devicetree/bindings/power/supply/lego,ev3-battery.yaml -F: arch/arm/boot/dts/da850-lego-ev3.dts +F: arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts F: drivers/power/supply/lego_ev3_battery.c LEGO USB Tower driver @@ -14026,12 +14008,12 @@ MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT M: Luka Kovacic M: Luka Perkov S: Maintained -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts -F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts +F: arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER M: Sakari Ailus @@ -14134,7 +14116,7 @@ R: Lubomir Rintel L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Odd Fixes T: git git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp.git -F: arch/arm/boot/dts/mmp* +F: arch/arm/boot/dts/marvell/mmp* F: arch/arm/mach-mmp/ F: include/linux/soc/mmp/ @@ -15265,13 +15247,7 @@ M: Tony Lindgren L: linux-omap@vger.kernel.org L: devicetree@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/*am3* -F: arch/arm/boot/dts/*am4* -F: arch/arm/boot/dts/*am5* -F: arch/arm/boot/dts/*dra7* -F: arch/arm/boot/dts/*omap* -F: arch/arm/boot/dts/logicpd-som-lv* -F: arch/arm/boot/dts/logicpd-torpedo* +F: arch/arm/boot/dts/ti/omap/ OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) L: linux-omap@vger.kernel.org @@ -15379,7 +15355,7 @@ OMAP/NEWFLOW NANOBONE MACHINE SUPPORT M: Mark Jackson L: linux-omap@vger.kernel.org S: Maintained -F: arch/arm/boot/dts/am335x-nano.dts +F: arch/arm/boot/dts/ti/omap/am335x-nano.dts OMAP1 SUPPORT M: Aaro Koskinen @@ -17126,7 +17102,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/hzhuang1/linux.git T: git git://github.com/rjarzmik/linux.git -F: arch/arm/boot/dts/pxa* +F: arch/arm/boot/dts/intel/pxa/ F: arch/arm/mach-pxa/ F: drivers/dma/pxa* F: drivers/pcmcia/pxa2xx* @@ -18755,7 +18731,7 @@ SANCLOUD BEAGLEBONE ENHANCED DEVICE TREE M: Paul Barker R: Marc Murphy S: Supported -F: arch/arm/boot/dts/am335x-sancloud* +F: arch/arm/boot/dts/ti/omap/am335x-sancloud* SC1200 WDT DRIVER M: Zwane Mwaikambo @@ -19581,15 +19557,15 @@ F: include/uapi/linux/raid/ SOLIDRUN CLEARFOG SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/armada-388-clearfog* -F: arch/arm/boot/dts/armada-38x-solidrun-* +F: arch/arm/boot/dts/marvell/armada-388-clearfog* +F: arch/arm/boot/dts/marvell/armada-38x-solidrun-* SOLIDRUN CUBOX-I/HUMMINGBOARD SUPPORT M: Russell King S: Maintained -F: arch/arm/boot/dts/imx6*-cubox-i* -F: arch/arm/boot/dts/imx6*-hummingboard* -F: arch/arm/boot/dts/imx6*-sr-* +F: arch/arm/boot/dts/nxp/imx/imx6*-cubox-i* +F: arch/arm/boot/dts/nxp/imx/imx6*-hummingboard* +F: arch/arm/boot/dts/nxp/imx/imx6*-sr-* SONIC NETWORK DRIVER M: Thomas Bogendoerfer @@ -19874,7 +19850,7 @@ M: soc@kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://www.st.com/spear -F: arch/arm/boot/dts/spear* +F: arch/arm/boot/dts/st/spear* F: arch/arm/mach-spear/ F: drivers/clk/spear/ F: drivers/pinctrl/spear/ @@ -21082,7 +21058,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git F: Documentation/devicetree/bindings/i2c/i2c-davinci.txt -F: arch/arm/boot/dts/da850* +F: arch/arm/boot/dts/ti/davinci/ F: arch/arm/mach-davinci/ F: drivers/i2c/busses/i2c-davinci.c diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c6798925fe453..efe38eb253016 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1,1718 +1,41 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine-db.dtb -dtb-$(CONFIG_MACH_ARTPEC6) += \ - artpec6-devboard.dtb -dtb-$(CONFIG_MACH_ASM9260) += \ - alphascale-asm9260-devkit.dtb -# Keep at91 dtb files sorted alphabetically for each SoC -dtb-$(CONFIG_SOC_AT91RM9200) += \ - at91rm9200ek.dtb \ - mpa1600.dtb -dtb-$(CONFIG_SOC_AT91SAM9) += \ - animeo_ip.dtb \ - at91-qil_a9260.dtb \ - aks-cdu.dtb \ - ethernut5.dtb \ - evk-pro3.dtb \ - tny_a9260.dtb \ - usb_a9260.dtb \ - at91sam9260ek.dtb \ - at91sam9261ek.dtb \ - at91sam9263ek.dtb \ - at91-sam9_l9260.dtb \ - tny_a9263.dtb \ - usb_a9263.dtb \ - at91-foxg20.dtb \ - at91-kizbox.dtb \ - at91-lmu5000.dtb \ - at91sam9g20ek.dtb \ - at91sam9g20ek_2mmc.dtb \ - tny_a9g20.dtb \ - usb_a9g20.dtb \ - usb_a9g20_lpw.dtb \ - at91sam9m10g45ek.dtb \ - pm9g45.dtb \ - at91sam9n12ek.dtb \ - at91sam9rlek.dtb \ - at91-ariag25.dtb \ - at91-ariettag25.dtb \ - at91-cosino_mega2560.dtb \ - at91-kizboxmini-base.dtb \ - at91-kizboxmini-mb.dtb \ - at91-kizboxmini-rd.dtb \ - at91-q5xr5.dtb \ - at91-smartkiz.dtb \ - at91-wb45n.dtb \ - at91sam9g15ek.dtb \ - at91sam9g25-gardena-smart-gateway.dtb \ - at91sam9g25ek.dtb \ - at91sam9g35ek.dtb \ - at91sam9x25ek.dtb \ - at91sam9x35ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sam9x60_curiosity := -@ -DTC_FLAGS_at91-sam9x60ek := -@ -dtb-$(CONFIG_SOC_SAM9X60) += \ - at91-sam9x60_curiosity.dtb \ - at91-sam9x60ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama5d27_som1_ek := -@ -DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ -DTC_FLAGS_at91-sama5d2_icp := -@ -DTC_FLAGS_at91-sama5d2_ptc_ek := -@ -DTC_FLAGS_at91-sama5d2_xplained := -@ -DTC_FLAGS_at91-sama5d3_eds := -@ -DTC_FLAGS_at91-sama5d3_xplained := -@ -DTC_FLAGS_at91-sama5d4_xplained := -@ -dtb-$(CONFIG_SOC_SAM_V7) += \ - at91-kizbox2-2.dtb \ - at91-kizbox3-hs.dtb \ - at91-nattis-2-natte-2.dtb \ - at91-sama5d27_som1_ek.dtb \ - at91-sama5d27_wlsom1_ek.dtb \ - at91-sama5d2_icp.dtb \ - at91-sama5d2_ptc_ek.dtb \ - at91-sama5d2_xplained.dtb \ - at91-sama5d3_eds.dtb \ - at91-sama5d3_ksz9477_evb.dtb \ - at91-sama5d3_xplained.dtb \ - at91-dvk_som60.dtb \ - at91-gatwick.dtb \ - at91-tse850-3.dtb \ - at91-wb50n.dtb \ - sama5d31ek.dtb \ - sama5d33ek.dtb \ - sama5d34ek.dtb \ - sama5d35ek.dtb \ - sama5d36ek.dtb \ - sama5d36ek_cmp.dtb \ - at91-sama5d4_ma5d4evk.dtb \ - at91-sama5d4_xplained.dtb \ - at91-sama5d4ek.dtb \ - at91-vinco.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama7g5ek := -@ -dtb-$(CONFIG_SOC_SAMA7G5) += \ - at91-sama7g5ek.dtb -dtb-$(CONFIG_SOC_SP7021) += \ - sunplus-sp7021-demo-v3.dtb -dtb-$(CONFIG_ARCH_AXXIA) += \ - axm5516-amarillo.dtb -# Enables support for device-tree overlays -DTC_FLAGS_bcm2835-rpi-b := -@ -DTC_FLAGS_bcm2835-rpi-a := -@ -DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ -DTC_FLAGS_bcm2835-rpi-b-plus := -@ -DTC_FLAGS_bcm2835-rpi-a-plus := -@ -DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ -DTC_FLAGS_bcm2836-rpi-2-b := -@ -DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ -DTC_FLAGS_bcm2837-rpi-3-b := -@ -DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ -DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ -DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ -DTC_FLAGS_bcm2711-rpi-400 := -@ -DTC_FLAGS_bcm2711-rpi-4-b := -@ -DTC_FLAGS_bcm2711-rpi-cm4-io := -@ -DTC_FLAGS_bcm2835-rpi-zero := -@ -DTC_FLAGS_bcm2835-rpi-zero-w := -@ -dtb-$(CONFIG_ARCH_BCM2835) += \ - bcm2835-rpi-b.dtb \ - bcm2835-rpi-a.dtb \ - bcm2835-rpi-b-rev2.dtb \ - bcm2835-rpi-b-plus.dtb \ - bcm2835-rpi-a-plus.dtb \ - bcm2835-rpi-cm1-io1.dtb \ - bcm2836-rpi-2-b.dtb \ - bcm2837-rpi-3-a-plus.dtb \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb \ - bcm2837-rpi-zero-2-w.dtb \ - bcm2711-rpi-400.dtb \ - bcm2711-rpi-4-b.dtb \ - bcm2711-rpi-cm4-io.dtb \ - bcm2835-rpi-zero.dtb \ - bcm2835-rpi-zero-w.dtb -dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4708-asus-rt-ac56u.dtb \ - bcm4708-asus-rt-ac68u.dtb \ - bcm4708-buffalo-wzr-1750dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp.dtb \ - bcm4708-buffalo-wzr-1166dhp2.dtb \ - bcm4708-linksys-ea6300-v1.dtb \ - bcm4708-linksys-ea6500-v2.dtb \ - bcm4708-luxul-xap-1510.dtb \ - bcm4708-luxul-xwc-1000.dtb \ - bcm4708-netgear-r6250.dtb \ - bcm4708-netgear-r6300-v2.dtb \ - bcm4708-smartrg-sr400ac.dtb \ - bcm47081-asus-rt-n18u.dtb \ - bcm47081-buffalo-wzr-600dhp2.dtb \ - bcm47081-buffalo-wzr-900dhp.dtb \ - bcm47081-luxul-xap-1410.dtb \ - bcm47081-luxul-xwr-1200.dtb \ - bcm47081-tplink-archer-c5-v2.dtb \ - bcm4709-asus-rt-ac87u.dtb \ - bcm4709-buffalo-wxr-1900dhp.dtb \ - bcm4709-linksys-ea9200.dtb \ - bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb \ - bcm4709-tplink-archer-c9-v1.dtb \ - bcm47094-asus-rt-ac88u.dtb \ - bcm47094-dlink-dir-885l.dtb \ - bcm47094-dlink-dir-890l.dtb \ - bcm47094-linksys-panamera.dtb \ - bcm47094-luxul-abr-4500.dtb \ - bcm47094-luxul-xap-1610.dtb \ - bcm47094-luxul-xbr-4500.dtb \ - bcm47094-luxul-xwc-2000.dtb \ - bcm47094-luxul-xwr-3100.dtb \ - bcm47094-luxul-xwr-3150-v1.dtb \ - bcm47094-netgear-r8500.dtb \ - bcm47094-phicomm-k3.dtb \ - bcm53015-meraki-mr26.dtb \ - bcm53016-dlink-dwl-8610ap.dtb \ - bcm53016-meraki-mr32.dtb \ - bcm94708.dtb \ - bcm94709.dtb \ - bcm953012er.dtb \ - bcm953012hr.dtb \ - bcm953012k.dtb -dtb-$(CONFIG_ARCH_BCM_53573) += \ - bcm47189-luxul-xap-1440.dtb \ - bcm47189-luxul-xap-810.dtb \ - bcm47189-tenda-ac9.dtb \ - bcm947189acdbmr.dtb -dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ - bcm911360_entphn.dtb \ - bcm911360k.dtb \ - bcm958300k.dtb \ - bcm958305k.dtb -dtb-$(CONFIG_ARCH_BCM_HR2) += \ - bcm53340-ubnt-unifi-switch8.dtb -dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ - bcm28155-ap.dtb \ - bcm21664-garnet.dtb \ - bcm23550-sparrow.dtb -dtb-$(CONFIG_ARCH_BCM_NSP) += \ - bcm958522er.dtb \ - bcm958525er.dtb \ - bcm958525xmc.dtb \ - bcm958622hr.dtb \ - bcm958623hr.dtb \ - bcm958625-meraki-mx64.dtb \ - bcm958625-meraki-mx64-a0.dtb \ - bcm958625-meraki-mx64w.dtb \ - bcm958625-meraki-mx64w-a0.dtb \ - bcm958625-meraki-mx65.dtb \ - bcm958625-meraki-mx65w.dtb \ - bcm958625hr.dtb \ - bcm988312hr.dtb \ - bcm958625k.dtb -dtb-$(CONFIG_ARCH_BERLIN) += \ - berlin2-sony-nsz-gs7.dtb \ - berlin2cd-google-chromecast.dtb \ - berlin2cd-valve-steamlink.dtb \ - berlin2q-marvell-dmp.dtb -dtb-$(CONFIG_ARCH_BRCMSTB) += \ - bcm7445-bcm97445svmb.dtb -dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb \ - bcm963138.dtb \ - bcm963138dvt.dtb \ - bcm963148.dtb \ - bcm963178.dtb \ - bcm96756.dtb \ - bcm96846.dtb \ - bcm96855.dtb \ - bcm96878.dtb -dtb-$(CONFIG_ARCH_CLPS711X) += \ - ep7211-edb7211.dtb -dtb-$(CONFIG_ARCH_DAVINCI) += \ - da850-lcdk.dtb \ - da850-enbw-cmc.dtb \ - da850-evm.dtb \ - da850-lego-ev3.dtb -dtb-$(CONFIG_ARCH_DIGICOLOR) += \ - cx92755_equinox.dtb -dtb-$(CONFIG_ARCH_AIROHA) += \ - en7523-evb.dtb -dtb-$(CONFIG_ARCH_EXYNOS3) += \ - exynos3250-artik5-eval.dtb \ - exynos3250-monk.dtb \ - exynos3250-rinato.dtb -dtb-$(CONFIG_ARCH_EXYNOS4) += \ - exynos4210-i9100.dtb \ - exynos4210-origen.dtb \ - exynos4210-smdkv310.dtb \ - exynos4210-trats.dtb \ - exynos4210-universal_c210.dtb \ - exynos4412-i9300.dtb \ - exynos4412-i9305.dtb \ - exynos4412-itop-elite.dtb \ - exynos4412-n710x.dtb \ - exynos4412-odroidu3.dtb \ - exynos4412-odroidx.dtb \ - exynos4412-odroidx2.dtb \ - exynos4412-origen.dtb \ - exynos4412-p4note-n8010.dtb \ - exynos4412-smdk4412.dtb \ - exynos4412-tiny4412.dtb \ - exynos4412-trats2.dtb -dtb-$(CONFIG_ARCH_EXYNOS5) += \ - exynos5250-arndale.dtb \ - exynos5250-smdk5250.dtb \ - exynos5250-snow.dtb \ - exynos5250-snow-rev5.dtb \ - exynos5250-spring.dtb \ - exynos5260-xyref5260.dtb \ - exynos5410-odroidxu.dtb \ - exynos5410-smdk5410.dtb \ - exynos5420-arndale-octa.dtb \ - exynos5420-peach-pit.dtb \ - exynos5420-smdk5420.dtb \ - exynos5420-chagall-wifi.dtb \ - exynos5420-klimt-wifi.dtb \ - exynos5422-odroidhc1.dtb \ - exynos5422-odroidxu3.dtb \ - exynos5422-odroidxu3-lite.dtb \ - exynos5422-odroidxu4.dtb \ - exynos5422-samsung-k3g.dtb \ - exynos5800-peach-pi.dtb -dtb-$(CONFIG_ARCH_GEMINI) += \ - gemini-dlink-dir-685.dtb \ - gemini-dlink-dns-313.dtb \ - gemini-nas4220b.dtb \ - gemini-ns2502.dtb \ - gemini-rut1xx.dtb \ - gemini-sl93512r.dtb \ - gemini-sq201.dtb \ - gemini-ssi1328.dtb \ - gemini-wbd111.dtb \ - gemini-wbd222.dtb -dtb-$(CONFIG_ARCH_HI3xxx) += \ - hi3620-hi4511.dtb -dtb-$(CONFIG_ARCH_HIGHBANK) += \ - highbank.dtb \ - ecx-2000.dtb -dtb-$(CONFIG_ARCH_HIP01) += \ - hip01-ca9x2.dtb -dtb-$(CONFIG_ARCH_HIP04) += \ - hip04-d01.dtb -dtb-$(CONFIG_ARCH_HISI) += \ - hi3519-demb.dtb -dtb-$(CONFIG_ARCH_HIX5HD2) += \ - hisi-x5hd2-dkb.dtb -dtb-$(CONFIG_ARCH_HPE_GXP) += \ - hpe-bmc-dl360gen10.dtb -dtb-$(CONFIG_ARCH_INTEGRATOR) += \ - integratorap.dtb \ - integratorap-im-pd1.dtb \ - integratorcp.dtb -dtb-$(CONFIG_ARCH_IXP4XX) += \ - intel-ixp42x-linksys-nslu2.dtb \ - intel-ixp42x-linksys-wrv54g.dtb \ - intel-ixp42x-freecom-fsg-3.dtb \ - intel-ixp42x-welltech-epbx100.dtb \ - intel-ixp42x-ixdp425.dtb \ - intel-ixp43x-kixrp435.dtb \ - intel-ixp46x-ixdp465.dtb \ - intel-ixp42x-adi-coyote.dtb \ - intel-ixp42x-ixdpg425.dtb \ - intel-ixp42x-goramo-multilink.dtb \ - intel-ixp42x-iomega-nas100d.dtb \ - intel-ixp42x-dlink-dsm-g600.dtb \ - intel-ixp42x-gateworks-gw2348.dtb \ - intel-ixp43x-gateworks-gw2358.dtb \ - intel-ixp42x-netgear-wg302v1.dtb \ - intel-ixp42x-arcom-vulcan.dtb \ - intel-ixp42x-gateway-7001.dtb -dtb-$(CONFIG_ARCH_KEYSTONE) += \ - keystone-k2hk-evm.dtb \ - keystone-k2l-evm.dtb \ - keystone-k2e-evm.dtb \ - keystone-k2g-evm.dtb \ - keystone-k2g-ice.dtb -dtb-$(CONFIG_MACH_KIRKWOOD) += \ - kirkwood-4i-edge-200.dtb \ - kirkwood-b3.dtb \ - kirkwood-blackarmor-nas220.dtb \ - kirkwood-c200-v1.dtb \ - kirkwood-cloudbox.dtb \ - kirkwood-d2net.dtb \ - kirkwood-db-88f6281.dtb \ - kirkwood-db-88f6282.dtb \ - kirkwood-dir665.dtb \ - kirkwood-dns320.dtb \ - kirkwood-dns325.dtb \ - kirkwood-dockstar.dtb \ - kirkwood-dreamplug.dtb \ - kirkwood-ds109.dtb \ - kirkwood-ds110jv10.dtb \ - kirkwood-ds111.dtb \ - kirkwood-ds112.dtb \ - kirkwood-ds209.dtb \ - kirkwood-ds210.dtb \ - kirkwood-ds212.dtb \ - kirkwood-ds212j.dtb \ - kirkwood-ds409.dtb \ - kirkwood-ds409slim.dtb \ - kirkwood-ds411.dtb \ - kirkwood-ds411j.dtb \ - kirkwood-ds411slim.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ - kirkwood-iconnect.dtb \ - kirkwood-iomega_ix2_200.dtb \ - kirkwood-is2.dtb \ - kirkwood-km_fixedeth.dtb \ - kirkwood-km_kirkwood.dtb \ - kirkwood-l-50.dtb \ - kirkwood-laplug.dtb \ - kirkwood-linkstation-lsqvl.dtb \ - kirkwood-linkstation-lsvl.dtb \ - kirkwood-linkstation-lswsxl.dtb \ - kirkwood-linkstation-lswvl.dtb \ - kirkwood-linkstation-lswxl.dtb \ - kirkwood-linksys-viper.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-lsxhl.dtb \ - kirkwood-mplcec4.dtb \ - kirkwood-mv88f6281gtw-ge.dtb \ - kirkwood-nas2big.dtb \ - kirkwood-net2big.dtb \ - kirkwood-net5big.dtb \ - kirkwood-netgear_readynas_duo_v2.dtb \ - kirkwood-netgear_readynas_nv+_v2.dtb \ - kirkwood-ns2.dtb \ - kirkwood-ns2lite.dtb \ - kirkwood-ns2max.dtb \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310.dtb \ - kirkwood-nsa310a.dtb \ - kirkwood-nsa310s.dtb \ - kirkwood-nsa320.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openblocks_a6.dtb \ - kirkwood-openblocks_a7.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-pogoplug-series-4.dtb \ - kirkwood-rd88f6192.dtb \ - kirkwood-rd88f6281-z0.dtb \ - kirkwood-rd88f6281-a.dtb \ - kirkwood-rs212.dtb \ - kirkwood-rs409.dtb \ - kirkwood-rs411.dtb \ - kirkwood-sheevaplug.dtb \ - kirkwood-sheevaplug-esata.dtb \ - kirkwood-t5325.dtb \ - kirkwood-topkick.dtb \ - kirkwood-ts219-6281.dtb \ - kirkwood-ts219-6282.dtb \ - kirkwood-ts419-6281.dtb \ - kirkwood-ts419-6282.dtb -dtb-$(CONFIG_ARCH_LPC18XX) += \ - lpc4337-ciaa.dtb \ - lpc4350-hitex-eval.dtb \ - lpc4357-ea4357-devkit.dtb \ - lpc4357-myd-lpc4357.dtb -dtb-$(CONFIG_ARCH_LPC32XX) += \ - lpc3250-ea3250.dtb \ - lpc3250-phy3250.dtb -dtb-$(CONFIG_ARCH_WPCM450) += \ - nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb -dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm730-gsj.dtb \ - nuvoton-npcm730-gbs.dtb \ - nuvoton-npcm730-kudo.dtb \ - nuvoton-npcm750-evb.dtb \ - nuvoton-npcm750-runbmc-olympus.dtb -dtb-$(CONFIG_MACH_MESON6) += \ - meson6-atv1200.dtb -dtb-$(CONFIG_MACH_MESON8) += \ - meson8-minix-neo-x8.dtb \ - meson8b-ec100.dtb \ - meson8b-mxq.dtb \ - meson8b-odroidc1.dtb \ - meson8m2-mxiii-plus.dtb -dtb-$(CONFIG_ARCH_MMP) += \ - pxa168-aspenite.dtb \ - pxa910-dkb.dtb \ - mmp2-brownstone.dtb \ - mmp2-olpc-xo-1-75.dtb \ - mmp3-dell-ariel.dtb -dtb-$(CONFIG_ARCH_MPS2) += \ - mps2-an385.dtb \ - mps2-an399.dtb -dtb-$(CONFIG_ARCH_MOXART) += \ - moxart-uc7112lx.dtb -dtb-$(CONFIG_ARCH_SD5203) += \ - sd5203.dtb -dtb-$(CONFIG_SOC_IMX1) += \ - imx1-ads.dtb \ - imx1-apf9328.dtb -dtb-$(CONFIG_SOC_IMX25) += \ - imx25-eukrea-mbimxsd25-baseboard.dtb \ - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ - imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ - imx25-karo-tx25.dtb \ - imx25-pdk.dtb -dtb-$(CONFIG_SOC_IMX27) += \ - imx27-apf27.dtb \ - imx27-apf27dev.dtb \ - imx27-eukrea-mbimxsd27-baseboard.dtb \ - imx27-pdk.dtb \ - imx27-phytec-phycore-rdk.dtb \ - imx27-phytec-phycard-s-rdk.dtb -dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb \ - imx31-lite.dtb -dtb-$(CONFIG_SOC_IMX35) += \ - imx35-eukrea-mbimxsd35-baseboard.dtb \ - imx35-pdk.dtb -dtb-$(CONFIG_SOC_IMX50) += \ - imx50-evk.dtb \ - imx50-kobo-aura.dtb -dtb-$(CONFIG_SOC_IMX51) += \ - imx51-apf51.dtb \ - imx51-apf51dev.dtb \ - imx51-babbage.dtb \ - imx51-digi-connectcore-jsk.dtb \ - imx51-eukrea-mbimxsd51-baseboard.dtb \ - imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb \ - imx51-zii-scu2-mezz.dtb \ - imx51-zii-scu3-esb.dtb -dtb-$(CONFIG_SOC_IMX53) += \ - imx53-ard.dtb \ - imx53-cx9020.dtb \ - imx53-kp-ddc.dtb \ - imx53-kp-hsc.dtb \ - imx53-m53evk.dtb \ - imx53-m53menlo.dtb \ - imx53-mba53.dtb \ - imx53-ppd.dtb \ - imx53-qsb.dtb \ - imx53-qsrb.dtb \ - imx53-sk-imx53.dtb \ - imx53-smd.dtb \ - imx53-tx53-x03x.dtb \ - imx53-tx53-x13x.dtb \ - imx53-usbarmory.dtb \ - imx53-voipac-bsb.dtb -dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-alti6p.dtb \ - imx6dl-apf6dev.dtb \ - imx6dl-aristainetos_4.dtb \ - imx6dl-aristainetos_7.dtb \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-colibri-aster.dtb \ - imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-iris.dtb \ - imx6dl-colibri-iris-v2.dtb \ - imx6dl-cubox-i.dtb \ - imx6dl-cubox-i-emmc-som-v15.dtb \ - imx6dl-cubox-i-som-v15.dtb \ - imx6dl-dfi-fs700-m60.dtb \ - imx6dl-dhcom-picoitx.dtb \ - imx6dl-eckelmann-ci4x10.dtb \ - imx6dl-emcon-avari.dtb \ - imx6dl-gw51xx.dtb \ - imx6dl-gw52xx.dtb \ - imx6dl-gw53xx.dtb \ - imx6dl-gw54xx.dtb \ - imx6dl-gw551x.dtb \ - imx6dl-gw552x.dtb \ - imx6dl-gw553x.dtb \ - imx6dl-gw560x.dtb \ - imx6dl-gw5903.dtb \ - imx6dl-gw5904.dtb \ - imx6dl-gw5907.dtb \ - imx6dl-gw5910.dtb \ - imx6dl-gw5912.dtb \ - imx6dl-gw5913.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-hummingboard-emmc-som-v15.dtb \ - imx6dl-hummingboard-som-v15.dtb \ - imx6dl-hummingboard2.dtb \ - imx6dl-hummingboard2-emmc-som-v15.dtb \ - imx6dl-hummingboard2-som-v15.dtb \ - imx6dl-icore.dtb \ - imx6dl-icore-mipi.dtb \ - imx6dl-icore-rqs.dtb \ - imx6dl-lanmcu.dtb \ - imx6dl-mamoj.dtb \ - imx6dl-mba6a.dtb \ - imx6dl-mba6b.dtb \ - imx6dl-nit6xlite.dtb \ - imx6dl-nitrogen6x.dtb \ - imx6dl-phytec-mira-rdk-nand.dtb \ - imx6dl-phytec-pbab01.dtb \ - imx6dl-pico-dwarf.dtb \ - imx6dl-pico-hobbit.dtb \ - imx6dl-pico-nymph.dtb \ - imx6dl-pico-pi.dtb \ - imx6dl-plybas.dtb \ - imx6dl-plym2m.dtb \ - imx6dl-prtmvt.dtb \ - imx6dl-prtrvt.dtb \ - imx6dl-prtvt7.dtb \ - imx6dl-rex-basic.dtb \ - imx6dl-riotboard.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabrelite.dtb \ - imx6dl-sabresd.dtb \ - imx6dl-savageboard.dtb \ - imx6dl-skov-revc-lt2.dtb \ - imx6dl-skov-revc-lt6.dtb \ - imx6dl-solidsense.dtb \ - imx6dl-ts4900.dtb \ - imx6dl-ts7970.dtb \ - imx6dl-tx6dl-comtft.dtb \ - imx6dl-tx6s-8034.dtb \ - imx6dl-tx6s-8034-mb7.dtb \ - imx6dl-tx6s-8035.dtb \ - imx6dl-tx6s-8035-mb7.dtb \ - imx6dl-tx6u-801x.dtb \ - imx6dl-tx6u-80xx-mb7.dtb \ - imx6dl-tx6u-8033.dtb \ - imx6dl-tx6u-8033-mb7.dtb \ - imx6dl-tx6u-811x.dtb \ - imx6dl-tx6u-81xx-mb7.dtb \ - imx6dl-udoo.dtb \ - imx6dl-victgo.dtb \ - imx6dl-vicut1.dtb \ - imx6dl-wandboard.dtb \ - imx6dl-wandboard-revb1.dtb \ - imx6dl-wandboard-revd1.dtb \ - imx6dl-yapp4-draco.dtb \ - imx6dl-yapp4-hydra.dtb \ - imx6dl-yapp4-lynx.dtb \ - imx6dl-yapp4-orion.dtb \ - imx6dl-yapp4-phoenix.dtb \ - imx6dl-yapp4-ursa.dtb \ - imx6q-apalis-eval.dtb \ - imx6q-apalis-ixora.dtb \ - imx6q-apalis-ixora-v1.1.dtb \ - imx6q-apalis-ixora-v1.2.dtb \ - imx6q-apf6dev.dtb \ - imx6q-arm2.dtb \ - imx6q-b450v3.dtb \ - imx6q-b650v3.dtb \ - imx6q-b850v3.dtb \ - imx6q-bosch-acc.dtb \ - imx6q-cm-fx6.dtb \ - imx6q-cubox-i.dtb \ - imx6q-cubox-i-emmc-som-v15.dtb \ - imx6q-cubox-i-som-v15.dtb \ - imx6q-dfi-fs700-m60.dtb \ - imx6q-dhcom-pdk2.dtb \ - imx6q-display5-tianma-tm070-1280x768.dtb \ - imx6q-dmo-edmqmx6.dtb \ - imx6q-dms-ba16.dtb \ - imx6q-ds.dtb \ - imx6q-emcon-avari.dtb \ - imx6q-evi.dtb \ - imx6dl-b105pv2.dtb \ - imx6dl-b105v2.dtb \ - imx6dl-b125v2.dtb \ - imx6dl-b125pv2.dtb \ - imx6dl-b155v2.dtb \ - imx6q-gk802.dtb \ - imx6q-gw51xx.dtb \ - imx6q-gw52xx.dtb \ - imx6q-gw53xx.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ - imx6q-gw551x.dtb \ - imx6q-gw552x.dtb \ - imx6q-gw553x.dtb \ - imx6q-gw560x.dtb \ - imx6q-gw5903.dtb \ - imx6q-gw5904.dtb \ - imx6q-gw5907.dtb \ - imx6q-gw5910.dtb \ - imx6q-gw5912.dtb \ - imx6q-gw5913.dtb \ - imx6q-h100.dtb \ - imx6q-hummingboard.dtb \ - imx6q-hummingboard-emmc-som-v15.dtb \ - imx6q-hummingboard-som-v15.dtb \ - imx6q-hummingboard2.dtb \ - imx6q-hummingboard2-emmc-som-v15.dtb \ - imx6q-hummingboard2-som-v15.dtb \ - imx6q-icore.dtb \ - imx6q-icore-mipi.dtb \ - imx6q-icore-ofcap10.dtb \ - imx6q-icore-ofcap12.dtb \ - imx6q-icore-rqs.dtb \ - imx6q-kp-tpc.dtb \ - imx6q-logicpd.dtb \ - imx6q-marsboard.dtb \ - imx6q-mba6a.dtb \ - imx6q-mba6b.dtb \ - imx6q-mccmon6.dtb \ - imx6q-nitrogen6x.dtb \ - imx6q-nitrogen6_max.dtb \ - imx6q-nitrogen6_som2.dtb \ - imx6q-novena.dtb \ - imx6q-phytec-mira-rdk-emmc.dtb \ - imx6q-phytec-mira-rdk-nand.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-pico-dwarf.dtb \ - imx6q-pico-hobbit.dtb \ - imx6q-pico-nymph.dtb \ - imx6q-pico-pi.dtb \ - imx6q-pistachio.dtb \ - imx6q-prti6q.dtb \ - imx6q-prtwd2.dtb \ - imx6q-rex-pro.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ - imx6q-savageboard.dtb \ - imx6q-sbc6x.dtb \ - imx6q-skov-revc-lt2.dtb \ - imx6q-skov-revc-lt6.dtb \ - imx6q-skov-reve-mi1010ait-1cp1.dtb \ - imx6q-solidsense.dtb \ - imx6q-tbs2910.dtb \ - imx6q-ts4900.dtb \ - imx6q-ts7970.dtb \ - imx6q-tx6q-1010.dtb \ - imx6q-tx6q-1010-comtft.dtb \ - imx6q-tx6q-1020.dtb \ - imx6q-tx6q-1020-comtft.dtb \ - imx6q-tx6q-1036.dtb \ - imx6q-tx6q-1036-mb7.dtb \ - imx6q-tx6q-10x0-mb7.dtb \ - imx6q-tx6q-1110.dtb \ - imx6q-tx6q-11x0-mb7.dtb \ - imx6q-udoo.dtb \ - imx6q-utilite-pro.dtb \ - imx6q-var-dt6customboard.dtb \ - imx6q-vicut1.dtb \ - imx6q-wandboard.dtb \ - imx6q-wandboard-revb1.dtb \ - imx6q-wandboard-revd1.dtb \ - imx6q-yapp4-crux.dtb \ - imx6q-yapp4-pegasus.dtb \ - imx6q-zii-rdu2.dtb \ - imx6qp-mba6b.dtb \ - imx6qp-nitrogen6_max.dtb \ - imx6qp-nitrogen6_som2.dtb \ - imx6qp-phytec-mira-rdk-nand.dtb \ - imx6qp-prtwd3.dtb \ - imx6qp-sabreauto.dtb \ - imx6qp-sabresd.dtb \ - imx6qp-tx6qp-8037.dtb \ - imx6qp-tx6qp-8037-mb7.dtb \ - imx6qp-tx6qp-8137.dtb \ - imx6qp-tx6qp-8137-mb7.dtb \ - imx6qp-vicutp.dtb \ - imx6qp-wandboard-revd1.dtb \ - imx6qp-yapp4-crux-plus.dtb \ - imx6qp-yapp4-pegasus-plus.dtb \ - imx6qp-zii-rdu2.dtb \ - imx6s-dhcom-drc02.dtb -dtb-$(CONFIG_SOC_IMX6SL) += \ - imx6sl-evk.dtb \ - imx6sl-kobo-aura2.dtb \ - imx6sl-tolino-shine2hd.dtb \ - imx6sl-tolino-shine3.dtb \ - imx6sl-tolino-vision.dtb \ - imx6sl-tolino-vision5.dtb \ - imx6sl-warp.dtb -dtb-$(CONFIG_SOC_IMX6SLL) += \ - imx6sll-evk.dtb \ - imx6sll-kobo-clarahd.dtb \ - imx6sll-kobo-librah2o.dtb -dtb-$(CONFIG_SOC_IMX6SX) += \ - imx6sx-nitrogen6sx.dtb \ - imx6sx-sabreauto.dtb \ - imx6sx-sdb-reva.dtb \ - imx6sx-sdb-sai.dtb \ - imx6sx-sdb.dtb \ - imx6sx-sdb-mqs.dtb \ - imx6sx-softing-vining-2000.dtb \ - imx6sx-udoo-neo-basic.dtb \ - imx6sx-udoo-neo-extended.dtb \ - imx6sx-udoo-neo-full.dtb -dtb-$(CONFIG_SOC_IMX6UL) += \ - imx6ul-14x14-evk.dtb \ - imx6ul-ccimx6ulsbcexpress.dtb \ - imx6ul-ccimx6ulsbcpro.dtb \ - imx6ul-geam.dtb \ - imx6ul-isiot-emmc.dtb \ - imx6ul-isiot-nand.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ul-kontron-bl-43.dtb \ - imx6ul-liteboard.dtb \ - imx6ul-tqma6ul1-mba6ulx.dtb \ - imx6ul-tqma6ul2-mba6ulx.dtb \ - imx6ul-tqma6ul2l-mba6ulx.dtb \ - imx6ul-opos6uldev.dtb \ - imx6ul-pico-dwarf.dtb \ - imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-phytec-segin-ff-rdk-emmc.dtb \ - imx6ul-phytec-segin-ff-rdk-nand.dtb \ - imx6ul-prti6g.dtb \ - imx6ul-tx6ul-0010.dtb \ - imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb \ - imx6ull-14x14-evk.dtb \ - imx6ull-colibri-aster.dtb \ - imx6ull-colibri-emmc-aster.dtb \ - imx6ull-colibri-emmc-eval-v3.dtb \ - imx6ull-colibri-emmc-iris.dtb \ - imx6ull-colibri-emmc-iris-v2.dtb \ - imx6ull-colibri-eval-v3.dtb \ - imx6ull-colibri-iris.dtb \ - imx6ull-colibri-iris-v2.dtb \ - imx6ull-colibri-wifi-aster.dtb \ - imx6ull-colibri-wifi-eval-v3.dtb \ - imx6ull-colibri-wifi-iris.dtb \ - imx6ull-colibri-wifi-iris-v2.dtb \ - imx6ull-dhcom-drc02.dtb \ - imx6ull-dhcom-pdk2.dtb \ - imx6ull-dhcom-picoitx.dtb \ - imx6ull-dhcor-maveo-box.dtb \ - imx6ull-jozacp.dtb \ - imx6ull-kontron-bl.dtb \ - imx6ull-myir-mys-6ulx-eval.dtb \ - imx6ull-opos6uldev.dtb \ - imx6ull-phytec-segin-ff-rdk-nand.dtb \ - imx6ull-phytec-segin-ff-rdk-emmc.dtb \ - imx6ull-phytec-segin-lc-rdk-nand.dtb \ - imx6ull-phytec-tauri-emmc.dtb \ - imx6ull-phytec-tauri-nand.dtb \ - imx6ull-tarragon-master.dtb \ - imx6ull-tarragon-micro.dtb \ - imx6ull-tarragon-slave.dtb \ - imx6ull-tarragon-slavext.dtb \ - imx6ull-tqma6ull2-mba6ulx.dtb \ - imx6ull-tqma6ull2l-mba6ulx.dtb \ - imx6ulz-14x14-evk.dtb \ - imx6ulz-bsh-smm-m2.dtb -dtb-$(CONFIG_SOC_IMX7D) += \ - imx7d-cl-som-imx7.dtb \ - imx7d-colibri-aster.dtb \ - imx7d-colibri-emmc-aster.dtb \ - imx7d-colibri-emmc-iris.dtb \ - imx7d-colibri-emmc-iris-v2.dtb \ - imx7d-colibri-emmc-eval-v3.dtb \ - imx7d-colibri-eval-v3.dtb \ - imx7d-colibri-iris.dtb \ - imx7d-colibri-iris-v2.dtb \ - imx7d-flex-concentrator.dtb \ - imx7d-flex-concentrator-mfg.dtb \ - imx7d-mba7.dtb \ - imx7d-meerkat96.dtb \ - imx7d-nitrogen7.dtb \ - imx7d-pico-dwarf.dtb \ - imx7d-pico-hobbit.dtb \ - imx7d-pico-nymph.dtb \ - imx7d-pico-pi.dtb \ - imx7d-remarkable2.dtb \ - imx7d-sbc-imx7.dtb \ - imx7d-sdb.dtb \ - imx7d-sdb-reva.dtb \ - imx7d-sdb-sht11.dtb \ - imx7d-smegw01.dtb \ - imx7d-zii-rmu2.dtb \ - imx7d-zii-rpu2.dtb \ - imx7s-colibri-aster.dtb \ - imx7s-colibri-eval-v3.dtb \ - imx7s-colibri-iris.dtb \ - imx7s-colibri-iris-v2.dtb \ - imx7s-mba7.dtb \ - imx7s-warp.dtb -dtb-$(CONFIG_SOC_IMX7ULP) += \ - imx7ulp-com.dtb \ - imx7ulp-evk.dtb -dtb-$(CONFIG_SOC_IMXRT) += \ - imxrt1050-evk.dtb -dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ - lan966x-kontron-kswitch-d10-mmt-8g.dtb \ - lan966x-pcb8290.dtb \ - lan966x-pcb8291.dtb \ - lan966x-pcb8309.dtb -dtb-$(CONFIG_SOC_LS1021A) += \ - ls1021a-iot.dtb \ - ls1021a-moxa-uc-8410a.dtb \ - ls1021a-qds.dtb \ - ls1021a-tsn.dtb \ - ls1021a-twr.dtb -dtb-$(CONFIG_SOC_VF610) += \ - vf500-colibri-eval-v3.dtb \ - vf610-bk4.dtb \ - vf610-colibri-eval-v3.dtb \ - vf610m4-colibri.dtb \ - vf610-cosmic.dtb \ - vf610m4-cosmic.dtb \ - vf610-twr.dtb \ - vf610-zii-cfu1.dtb \ - vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb \ - vf610-zii-scu4-aib.dtb \ - vf610-zii-spb4.dtb \ - vf610-zii-ssmb-dtu.dtb \ - vf610-zii-ssmb-spu3.dtb -dtb-$(CONFIG_ARCH_MXS) += \ - imx23-evk.dtb \ - imx23-olinuxino.dtb \ - imx23-sansa.dtb \ - imx23-stmp378x_devb.dtb \ - imx23-xfi3.dtb \ - imx28-apf28.dtb \ - imx28-apf28dev.dtb \ - imx28-apx4devkit.dtb \ - imx28-cfa10036.dtb \ - imx28-cfa10037.dtb \ - imx28-cfa10049.dtb \ - imx28-cfa10055.dtb \ - imx28-cfa10056.dtb \ - imx28-cfa10057.dtb \ - imx28-cfa10058.dtb \ - imx28-duckbill-2-485.dtb \ - imx28-duckbill-2.dtb \ - imx28-duckbill-2-enocean.dtb \ - imx28-duckbill-2-spi.dtb \ - imx28-duckbill.dtb \ - imx28-eukrea-mbmx283lc.dtb \ - imx28-eukrea-mbmx287lc.dtb \ - imx28-evk.dtb \ - imx28-m28cu3.dtb \ - imx28-m28evk.dtb \ - imx28-sps1.dtb \ - imx28-ts4600.dtb \ - imx28-tx28.dtb \ - imx28-xea.dtb -dtb-$(CONFIG_ARCH_NOMADIK) += \ - ste-nomadik-s8815.dtb \ - ste-nomadik-nhk15.dtb -dtb-$(CONFIG_ARCH_NSPIRE) += \ - nspire-cx.dtb \ - nspire-tp.dtb \ - nspire-clp.dtb -dtb-$(CONFIG_ARCH_OMAP2) += \ - omap2420-h4.dtb \ - omap2420-n800.dtb \ - omap2420-n810.dtb \ - omap2420-n810-wimax.dtb \ - omap2430-sdp.dtb -dtb-$(CONFIG_ARCH_OMAP3) += \ - am3517-craneboard.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ - logicpd-torpedo-35xx-devkit.dtb \ - logicpd-torpedo-37xx-devkit.dtb \ - logicpd-torpedo-37xx-devkit-28.dtb \ - logicpd-som-lv-35xx-devkit.dtb \ - logicpd-som-lv-37xx-devkit.dtb \ - omap3430-sdp.dtb \ - omap3-beagle.dtb \ - omap3-beagle-ab4.dtb \ - omap3-beagle-xm.dtb \ - omap3-beagle-xm-ab.dtb \ - omap3-cm-t3517.dtb \ - omap3-cm-t3530.dtb \ - omap3-cm-t3730.dtb \ - omap3-devkit8000.dtb \ - omap3-devkit8000-lcd43.dtb \ - omap3-devkit8000-lcd70.dtb \ - omap3-echo.dtb \ - omap3-evm.dtb \ - omap3-evm-37xx.dtb \ - omap3-gta04a3.dtb \ - omap3-gta04a4.dtb \ - omap3-gta04a5.dtb \ - omap3-gta04a5one.dtb \ - omap3-ha.dtb \ - omap3-ha-lcd.dtb \ - omap3-igep0020.dtb \ - omap3-igep0020-rev-f.dtb \ - omap3-igep0030.dtb \ - omap3-igep0030-rev-g.dtb \ - omap3-ldp.dtb \ - omap3-lilly-dbb056.dtb \ - omap3-n900.dtb \ - omap3-n9.dtb \ - omap3-n950.dtb \ - omap3-overo-alto35.dtb \ - omap3-overo-chestnut43.dtb \ - omap3-overo-gallop43.dtb \ - omap3-overo-palo35.dtb \ - omap3-overo-palo43.dtb \ - omap3-overo-storm-alto35.dtb \ - omap3-overo-storm-chestnut43.dtb \ - omap3-overo-storm-gallop43.dtb \ - omap3-overo-storm-palo35.dtb \ - omap3-overo-storm-palo43.dtb \ - omap3-overo-storm-summit.dtb \ - omap3-overo-storm-tobi.dtb \ - omap3-overo-storm-tobiduo.dtb \ - omap3-overo-summit.dtb \ - omap3-overo-tobi.dtb \ - omap3-overo-tobiduo.dtb \ - omap3-pandora-600mhz.dtb \ - omap3-pandora-1ghz.dtb \ - omap3-sbc-t3517.dtb \ - omap3-sbc-t3530.dtb \ - omap3-sbc-t3730.dtb \ - omap3-sniper.dtb \ - omap3-thunder.dtb \ - omap3-zoom3.dtb -dtb-$(CONFIG_SOC_TI81XX) += \ - am3874-iceboard.dtb \ - dm8148-evm.dtb \ - dm8148-t410.dtb \ - dm8168-evm.dtb \ - dra62x-j5eco-evm.dtb -dtb-$(CONFIG_SOC_AM33XX) += \ - am335x-baltos-ir2110.dtb \ - am335x-baltos-ir3220.dtb \ - am335x-baltos-ir5221.dtb \ - am335x-base0033.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-boneblack-wireless.dtb \ - am335x-boneblue.dtb \ - am335x-bonegreen.dtb \ - am335x-bonegreen-wireless.dtb \ - am335x-chiliboard.dtb \ - am335x-cm-t335.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-guardian.dtb \ - am335x-icev2.dtb \ - am335x-lxm.dtb \ - am335x-moxa-uc-2101.dtb \ - am335x-moxa-uc-8100-me-t.dtb \ - am335x-myirtech-myd.dtb \ - am335x-nano.dtb \ - am335x-netcan-plus-1xx.dtb \ - am335x-netcom-plus-2xx.dtb \ - am335x-netcom-plus-8xx.dtb \ - am335x-pdu001.dtb \ - am335x-pepper.dtb \ - am335x-phycore-rdk.dtb \ - am335x-pocketbeagle.dtb \ - am335x-regor-rdk.dtb \ - am335x-sancloud-bbe.dtb \ - am335x-sancloud-bbe-lite.dtb \ - am335x-sancloud-bbe-extended-wifi.dtb \ - am335x-shc.dtb \ - am335x-sbc-t335.dtb \ - am335x-sl50.dtb \ - am335x-wega-rdk.dtb \ - am335x-osd3358-sm-red.dtb -dtb-$(CONFIG_ARCH_OMAP4) += \ - omap4-droid-bionic-xt875.dtb \ - omap4-droid4-xt894.dtb \ - omap4-duovero-parlor.dtb \ - omap4-epson-embt2ws.dtb \ - omap4-kc1.dtb \ - omap4-panda.dtb \ - omap4-panda-a4.dtb \ - omap4-panda-es.dtb \ - omap4-sdp.dtb \ - omap4-sdp-es23plus.dtb \ - omap4-var-dvk-om44.dtb \ - omap4-var-stk-om44.dtb -dtb-$(CONFIG_SOC_AM43XX) += \ - am43x-epos-evm.dtb \ - am437x-cm-t43.dtb \ - am437x-gp-evm.dtb \ - am437x-idk-evm.dtb \ - am437x-sbc-t43.dtb \ - am437x-sk-evm.dtb -dtb-$(CONFIG_SOC_OMAP5) += \ - omap5-cm-t54.dtb \ - omap5-igep0050.dtb \ - omap5-sbc-t54.dtb \ - omap5-uevm.dtb -am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo -am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo -dtb-$(CONFIG_SOC_DRA7XX) += \ - am57xx-beagle-x15.dtb \ - am57xx-beagle-x15-revb1.dtb \ - am57xx-beagle-x15-revc.dtb \ - am57xx-evm.dtb \ - am57xx-evm-reva3.dtb \ - am5729-beagleboneai.dtb \ - am57xx-cl-som-am57x.dtb \ - am57xx-sbc-am57x.dtb \ - am572x-idk.dtb \ - am572x-idk-touchscreen.dtbo \ - am571x-idk.dtb \ - am571x-idk-touchscreen.dtbo \ - am574x-idk.dtb \ - am57xx-idk-lcd-osd101t2045.dtbo \ - am57xx-idk-lcd-osd101t2587.dtbo \ - dra7-evm.dtb \ - dra72-evm.dtb \ - dra72-evm-revc.dtb \ - dra71-evm.dtb \ - dra76-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-kuroboxpro.dtb \ - orion5x-lacie-d2-network.dtb \ - orion5x-lacie-ethernet-disk-mini-v2.dtb \ - orion5x-linkstation-lsgl.dtb \ - orion5x-linkstation-lswtgl.dtb \ - orion5x-linkstation-lschl.dtb \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-netgear-wnr854t.dtb \ - orion5x-rd88f5182-nas.dtb -dtb-$(CONFIG_ARCH_ACTIONS) += \ - owl-s500-cubieboard6.dtb \ - owl-s500-guitar-bb-rev-b.dtb \ - owl-s500-labrador-base-m.dtb \ - owl-s500-roseapplepi.dtb \ - owl-s500-sparky.dtb -dtb-$(CONFIG_ARCH_PXA) += \ - pxa300-raumfeld-connector.dtb \ - pxa300-raumfeld-controller.dtb \ - pxa300-raumfeld-speaker-l.dtb \ - pxa300-raumfeld-speaker-m.dtb \ - pxa300-raumfeld-speaker-one.dtb \ - pxa300-raumfeld-speaker-s.dtb -dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8016-sbc.dtb \ - qcom-apq8026-asus-sparrow.dtb \ - qcom-apq8026-huawei-sturgeon.dtb \ - qcom-apq8026-lg-lenok.dtb \ - qcom-apq8026-samsung-matisse-wifi.dtb \ - qcom-apq8060-dragonboard.dtb \ - qcom-apq8064-cm-qs600.dtb \ - qcom-apq8064-ifc6410.dtb \ - qcom-apq8064-sony-xperia-lagan-yuga.dtb \ - qcom-apq8064-asus-nexus7-flo.dtb \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ - qcom-ipq4018-ap120c-ac.dtb \ - qcom-ipq4018-ap120c-ac-bit.dtb \ - qcom-ipq4018-jalapeno.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-ipq8064-rb3011.dtb \ - qcom-msm8226-samsung-s3ve3g.dtb \ - qcom-msm8660-surf.dtb \ - qcom-msm8916-samsung-e5.dtb \ - qcom-msm8916-samsung-e7.dtb \ - qcom-msm8916-samsung-grandmax.dtb \ - qcom-msm8916-samsung-serranove.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-msm8960-samsung-expressatt.dtb \ - qcom-msm8974-lge-nexus5-hammerhead.dtb \ - qcom-msm8974-sony-xperia-rhine-amami.dtb \ - qcom-msm8974-sony-xperia-rhine-honami.dtb \ - qcom-msm8974pro-fairphone-fp2.dtb \ - qcom-msm8974pro-oneplus-bacon.dtb \ - qcom-msm8974pro-samsung-klte.dtb \ - qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ - qcom-mdm9615-wp8548-mangoh-green.dtb \ - qcom-sdx55-mtp.dtb \ - qcom-sdx55-t55.dtb \ - qcom-sdx55-telit-fn980-tlb.dtb \ - qcom-sdx65-mtp.dtb -dtb-$(CONFIG_ARCH_RDA) += \ - rda8810pl-orangepi-2g-iot.dtb \ - rda8810pl-orangepi-i96.dtb -dtb-$(CONFIG_ARCH_REALTEK) += \ - rtd1195-horseradish.dtb \ - rtd1195-mele-x1000.dtb -dtb-$(CONFIG_ARCH_REALVIEW) += \ - arm-realview-pb1176.dtb \ - arm-realview-pb11mp.dtb \ - arm-realview-eb.dtb \ - arm-realview-eb-bbrevd.dtb \ - arm-realview-eb-11mp.dtb \ - arm-realview-eb-11mp-bbrevd.dtb \ - arm-realview-eb-11mp-ctrevb.dtb \ - arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ - arm-realview-eb-a9mp.dtb \ - arm-realview-eb-a9mp-bbrevd.dtb \ - arm-realview-pba8.dtb \ - arm-realview-pbx-a9.dtb -dtb-$(CONFIG_ARCH_RENESAS) += \ - emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ - r7s72100-gr-peach.dtb \ - r7s72100-rskrza1.dtb \ - r7s9210-rza2mevb.dtb \ - r8a73a4-ape6evm.dtb \ - r8a7740-armadillo800eva.dtb \ - r8a7742-iwg21d-q7.dtb \ - r8a7742-iwg21d-q7-dbcm-ca.dtb \ - r8a7743-iwg20d-q7.dtb \ - r8a7743-iwg20d-q7-dbcm-ca.dtb \ - r8a7743-sk-rzg1m.dtb \ - r8a7744-iwg20d-q7.dtb \ - r8a7744-iwg20d-q7-dbcm-ca.dtb \ - r8a7745-iwg22d-sodimm.dtb \ - r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ - r8a7745-sk-rzg1e.dtb \ - r8a77470-iwg23s-sbc.dtb \ - r8a7778-bockw.dtb \ - r8a7779-marzen.dtb \ - r8a7790-lager.dtb \ - r8a7790-stout.dtb \ - r8a7791-koelsch.dtb \ - r8a7791-porter.dtb \ - r8a7792-blanche.dtb \ - r8a7792-wheat.dtb \ - r8a7793-gose.dtb \ - r8a7794-alt.dtb \ - r8a7794-silk.dtb \ - r9a06g032-rzn1d400-db.dtb \ - sh73a0-kzm9g.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rv1108-elgin-r1.dtb \ - rv1108-evb.dtb \ - rv1126-edgeble-neu2-io.dtb \ - rk3036-evb.dtb \ - rk3036-kylin.dtb \ - rk3066a-bqcurie2.dtb \ - rk3066a-marsboard.dtb \ - rk3066a-mk808.dtb \ - rk3066a-rayeager.dtb \ - rk3128-evb.dtb \ - rk3188-bqedison2qc.dtb \ - rk3188-px3-evb.dtb \ - rk3188-radxarock.dtb \ - rk3228-evb.dtb \ - rk3229-evb.dtb \ - rk3229-xms6.dtb \ - rk3288-evb-act8846.dtb \ - rk3288-evb-rk808.dtb \ - rk3288-firefly-beta.dtb \ - rk3288-firefly.dtb \ - rk3288-firefly-reload.dtb \ - rk3288-miqi.dtb \ - rk3288-phycore-rdk.dtb \ - rk3288-popmetal.dtb \ - rk3288-r89.dtb \ - rk3288-rock2-square.dtb \ - rk3288-rock-pi-n8.dtb \ - rk3288-tinker.dtb \ - rk3288-tinker-s.dtb \ - rk3288-veyron-brain.dtb \ - rk3288-veyron-fievel.dtb \ - rk3288-veyron-jaq.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-mighty.dtb \ - rk3288-veyron-minnie.dtb \ - rk3288-veyron-pinky.dtb \ - rk3288-veyron-speedy.dtb \ - rk3288-veyron-tiger.dtb \ - rk3288-vyasa.dtb -dtb-$(CONFIG_ARCH_S3C64XX) += \ - s3c6410-mini6410.dtb \ - s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_S5PV210) += \ - s5pv210-aquila.dtb \ - s5pv210-fascinate4g.dtb \ - s5pv210-galaxys.dtb \ - s5pv210-goni.dtb \ - s5pv210-smdkc110.dtb \ - s5pv210-smdkv210.dtb \ - s5pv210-torbreck.dtb -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ - socfpga_arria5_socdk.dtb \ - socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ - socfpga_arria10_socdk_nand.dtb \ - socfpga_arria10_socdk_qspi.dtb \ - socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_cyclone5_chameleon96.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_socdk.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sodia.dtb \ - socfpga_cyclone5_vining_fpga.dtb \ - socfpga_vt.dtb -dtb-$(CONFIG_ARCH_SPEAR13XX) += \ - spear1310-evb.dtb \ - spear1340-evb.dtb -dtb-$(CONFIG_ARCH_SPEAR3XX) += \ - spear300-evb.dtb \ - spear310-evb.dtb \ - spear320-evb.dtb \ - spear320-hmi.dtb -dtb-$(CONFIG_ARCH_SPEAR6XX) += \ - spear600-evb.dtb -dtb-$(CONFIG_ARCH_STI) += \ - stih407-b2120.dtb \ - stih410-b2120.dtb \ - stih410-b2260.dtb \ - stih418-b2199.dtb \ - stih418-b2264.dtb -dtb-$(CONFIG_ARCH_STM32) += \ - stm32f429-disco.dtb \ - stm32f469-disco.dtb \ - stm32f746-disco.dtb \ - stm32f769-disco.dtb \ - stm32429i-eval.dtb \ - stm32746g-eval.dtb \ - stm32h743i-eval.dtb \ - stm32h743i-disco.dtb \ - stm32h750i-art-pi.dtb \ - stm32mp135f-dk.dtb \ - stm32mp151a-prtt1a.dtb \ - stm32mp151a-prtt1c.dtb \ - stm32mp151a-prtt1s.dtb \ - stm32mp151a-dhcor-testbench.dtb \ - stm32mp153c-dhcom-drc02.dtb \ - stm32mp153c-dhcor-drc-compact.dtb \ - stm32mp157a-avenger96.dtb \ - stm32mp157a-dhcor-avenger96.dtb \ - stm32mp157a-dk1.dtb \ - stm32mp157a-dk1-scmi.dtb \ - stm32mp157a-iot-box.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ - stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2.dtb \ - stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ - stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ - stm32mp157a-stinger96.dtb \ - stm32mp157c-dhcom-pdk2.dtb \ - stm32mp157c-dhcom-picoitx.dtb \ - stm32mp157c-dk2.dtb \ - stm32mp157c-dk2-scmi.dtb \ - stm32mp157c-ed1.dtb \ - stm32mp157c-ed1-scmi.dtb \ - stm32mp157c-emsbc-argon.dtb \ - stm32mp157c-ev1.dtb \ - stm32mp157c-ev1-scmi.dtb \ - stm32mp157c-lxa-mc1.dtb \ - stm32mp157c-odyssey.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb -dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ - sun4i-a10-ba10-tvbox.dtb \ - sun4i-a10-chuwi-v7-cw0825.dtb \ - sun4i-a10-cubieboard.dtb \ - sun4i-a10-dserve-dsrv9703c.dtb \ - sun4i-a10-gemei-g9.dtb \ - sun4i-a10-hackberry.dtb \ - sun4i-a10-hyundai-a7hd.dtb \ - sun4i-a10-inet1.dtb \ - sun4i-a10-inet97fv2.dtb \ - sun4i-a10-inet9f-rev03.dtb \ - sun4i-a10-itead-iteaduino-plus.dtb \ - sun4i-a10-jesurun-q5.dtb \ - sun4i-a10-marsboard.dtb \ - sun4i-a10-mini-xplus.dtb \ - sun4i-a10-mk802.dtb \ - sun4i-a10-mk802ii.dtb \ - sun4i-a10-olinuxino-lime.dtb \ - sun4i-a10-pcduino.dtb \ - sun4i-a10-pcduino2.dtb \ - sun4i-a10-pov-protab2-ips9.dtb \ - sun4i-a10-topwise-a721.dtb -dtb-$(CONFIG_MACH_SUN5I) += \ - sun5i-a10s-auxtek-t003.dtb \ - sun5i-a10s-auxtek-t004.dtb \ - sun5i-a10s-mk802.dtb \ - sun5i-a10s-olinuxino-micro.dtb \ - sun5i-a10s-r7-tv-dongle.dtb \ - sun5i-a10s-wobo-i5.dtb \ - sun5i-a13-difrnce-dit4350.dtb \ - sun5i-a13-empire-electronix-d709.dtb \ - sun5i-a13-empire-electronix-m712.dtb \ - sun5i-a13-hsg-h702.dtb \ - sun5i-a13-inet-98v-rev2.dtb \ - sun5i-a13-licheepi-one.dtb \ - sun5i-a13-olinuxino.dtb \ - sun5i-a13-olinuxino-micro.dtb \ - sun5i-a13-pocketbook-touch-lux-3.dtb \ - sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb \ - sun5i-gr8-chip-pro.dtb \ - sun5i-gr8-evb.dtb \ - sun5i-r8-chip.dtb -dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-app4-evb1.dtb \ - sun6i-a31-colombus.dtb \ - sun6i-a31-hummingbird.dtb \ - sun6i-a31-i7.dtb \ - sun6i-a31-m9.dtb \ - sun6i-a31-mele-a1000g-quad.dtb \ - sun6i-a31s-colorfly-e708-q1.dtb \ - sun6i-a31s-cs908.dtb \ - sun6i-a31s-inet-q972.dtb \ - sun6i-a31s-primo81.dtb \ - sun6i-a31s-sina31s.dtb \ - sun6i-a31s-sinovoip-bpi-m2.dtb \ - sun6i-a31s-yones-toptech-bs1078-v2.dtb -dtb-$(CONFIG_MACH_SUN7I) += \ - sun7i-a20-bananapi.dtb \ - sun7i-a20-bananapi-m1-plus.dtb \ - sun7i-a20-bananapro.dtb \ - sun7i-a20-cubieboard2.dtb \ - sun7i-a20-cubietruck.dtb \ - sun7i-a20-haoyu-marsboard.dtb \ - sun7i-a20-hummingbird.dtb \ - sun7i-a20-itead-ibox.dtb \ - sun7i-a20-i12-tvbox.dtb \ - sun7i-a20-icnova-a20-adb4006.dtb \ - sun7i-a20-icnova-swac.dtb \ - sun7i-a20-lamobo-r1.dtb \ - sun7i-a20-linutronix-testbox-v2.dtb \ - sun7i-a20-m3.dtb \ - sun7i-a20-mk808c.dtb \ - sun7i-a20-olimex-som-evb.dtb \ - sun7i-a20-olimex-som-evb-emmc.dtb \ - sun7i-a20-olimex-som204-evb.dtb \ - sun7i-a20-olimex-som204-evb-emmc.dtb \ - sun7i-a20-olinuxino-lime.dtb \ - sun7i-a20-olinuxino-lime-emmc.dtb \ - sun7i-a20-olinuxino-lime2.dtb \ - sun7i-a20-olinuxino-lime2-emmc.dtb \ - sun7i-a20-olinuxino-micro.dtb \ - sun7i-a20-olinuxino-micro-emmc.dtb \ - sun7i-a20-orangepi.dtb \ - sun7i-a20-orangepi-mini.dtb \ - sun7i-a20-pcduino3.dtb \ - sun7i-a20-pcduino3-nano.dtb \ - sun7i-a20-wexler-tab7200.dtb \ - sun7i-a20-wits-pro-a20-dkt.dtb -dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a23-evb.dtb \ - sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-inet86dz.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ - sun8i-a23-polaroid-mid2407pxe03.dtb \ - sun8i-a23-polaroid-mid2809pxe04.dtb \ - sun8i-a23-q8-tablet.dtb \ - sun8i-a33-et-q8-v1.6.dtb \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-inet-d978-rev2.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-bananapi-m2-plus-v1.2.dtb \ - sun8i-h3-beelink-x2.dtb \ - sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-mapleboard-mp130.dtb \ - sun8i-h3-nanopi-duo2.dtb \ - sun8i-h3-nanopi-m1.dtb \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ - sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ - sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-zeropi.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ - sun8i-r16-parrot.dtb \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-r40-oka40i-c.dtb \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-lichee-zero-plus.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-t113s-mangopi-mq-r-t113.dtb \ - sun8i-t3-cqa3t-bv3.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb \ - sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ - sun9i-a80-cubieboard4.dtb -dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb \ - suniv-f1c200s-lctech-pi.dtb \ - suniv-f1c200s-popstick-v1.1.dtb -dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ - tegra20-acer-a500-picasso.dtb \ - tegra20-asus-tf101.dtb \ - tegra20-harmony.dtb \ - tegra20-colibri-eval-v3.dtb \ - tegra20-colibri-iris.dtb \ - tegra20-medcom-wide.dtb \ - tegra20-paz00.dtb \ - tegra20-plutux.dtb \ - tegra20-seaboard.dtb \ - tegra20-tec.dtb \ - tegra20-trimslice.dtb \ - tegra20-ventana.dtb -dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ - tegra30-apalis-eval.dtb \ - tegra30-apalis-v1.1-eval.dtb \ - tegra30-asus-nexus7-grouper-PM269.dtb \ - tegra30-asus-nexus7-grouper-E1565.dtb \ - tegra30-asus-nexus7-tilapia-E1565.dtb \ - tegra30-asus-tf201.dtb \ - tegra30-asus-tf300t.dtb \ - tegra30-asus-tf300tg.dtb \ - tegra30-asus-tf700t.dtb \ - tegra30-beaver.dtb \ - tegra30-cardhu-a02.dtb \ - tegra30-cardhu-a04.dtb \ - tegra30-colibri-eval-v3.dtb \ - tegra30-ouya.dtb \ - tegra30-pegatron-chagall.dtb -dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ - tegra114-asus-tf701t.dtb \ - tegra114-dalmore.dtb \ - tegra114-roth.dtb \ - tegra114-tn7.dtb -dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ - tegra124-apalis-eval.dtb \ - tegra124-apalis-v1.2-eval.dtb \ - tegra124-jetson-tk1.dtb \ - tegra124-nyan-big.dtb \ - tegra124-nyan-big-fhd.dtb \ - tegra124-nyan-blaze.dtb \ - tegra124-venice2.dtb -dtb-$(CONFIG_ARCH_U8500) += \ - ste-snowball.dtb \ - ste-hrefprev60-stuib.dtb \ - ste-hrefprev60-tvk.dtb \ - ste-hrefv60plus-stuib.dtb \ - ste-hrefv60plus-tvk.dtb \ - ste-href520-tvk.dtb \ - ste-ux500-samsung-golden.dtb \ - ste-ux500-samsung-janice.dtb \ - ste-ux500-samsung-gavini.dtb \ - ste-ux500-samsung-codina.dtb \ - ste-ux500-samsung-codina-tmo.dtb \ - ste-ux500-samsung-skomer.dtb \ - ste-ux500-samsung-kyle.dtb -dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ld4-ref.dtb \ - uniphier-ld6b-ref.dtb \ - uniphier-pro4-ace.dtb \ - uniphier-pro4-ref.dtb \ - uniphier-pro4-sanji.dtb \ - uniphier-pro5-epcore.dtb \ - uniphier-pro5-proex.dtb \ - uniphier-pxs2-gentil.dtb \ - uniphier-pxs2-vodka.dtb \ - uniphier-sld8-ref.dtb -dtb-$(CONFIG_ARCH_VERSATILE) += \ - versatile-ab.dtb \ - versatile-ab-ib2.dtb \ - versatile-pb.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += \ - vexpress-v2p-ca5s.dtb \ - vexpress-v2p-ca9.dtb \ - vexpress-v2p-ca15-tc1.dtb \ - vexpress-v2p-ca15_a7.dtb -dtb-$(CONFIG_ARCH_VIRT) += \ - xenvm-4.2.dtb -dtb-$(CONFIG_ARCH_VT8500) += \ - vt8500-bv07.dtb \ - wm8505-ref.dtb \ - wm8650-mid.dtb \ - wm8750-apc8750.dtb \ - wm8850-w70v2.dtb -dtb-$(CONFIG_ARCH_ZYNQ) += \ - zynq-cc108.dtb \ - zynq-ebaz4205.dtb \ - zynq-microzed.dtb \ - zynq-parallella.dtb \ - zynq-zc702.dtb \ - zynq-zc706.dtb \ - zynq-zc770-xm010.dtb \ - zynq-zc770-xm011.dtb \ - zynq-zc770-xm012.dtb \ - zynq-zc770-xm013.dtb \ - zynq-zed.dtb \ - zynq-zturn.dtb \ - zynq-zturn-v5.dtb \ - zynq-zybo.dtb \ - zynq-zybo-z7.dtb -dtb-$(CONFIG_MACH_ARMADA_370) += \ - armada-370-c200-v2.dtb \ - armada-370-db.dtb \ - armada-370-dlink-dns327l.dtb \ - armada-370-mirabox.dtb \ - armada-370-netgear-rn102.dtb \ - armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb \ - armada-370-seagate-nas-2bay.dtb \ - armada-370-seagate-nas-4bay.dtb \ - armada-370-seagate-personal-cloud.dtb \ - armada-370-seagate-personal-cloud-2bay.dtb \ - armada-370-synology-ds213j.dtb -dtb-$(CONFIG_MACH_ARMADA_375) += \ - armada-375-db.dtb -dtb-$(CONFIG_MACH_ARMADA_38X) += \ - armada-381-netgear-gs110emx.dtb \ - armada-382-rd-ac3x-48g4x2xl.dtb \ - armada-385-atl-x530.dtb\ - armada-385-clearfog-gtr-s4.dtb \ - armada-385-clearfog-gtr-l8.dtb \ - armada-385-db-88f6820-amc.dtb \ - armada-385-db-ap.dtb \ - armada-385-linksys-caiman.dtb \ - armada-385-linksys-cobra.dtb \ - armada-385-linksys-rango.dtb \ - armada-385-linksys-shelby.dtb \ - armada-385-synology-ds116.dtb \ - armada-385-turris-omnia.dtb \ - armada-388-clearfog.dtb \ - armada-388-clearfog-base.dtb \ - armada-388-clearfog-pro.dtb \ - armada-388-db.dtb \ - armada-388-gp.dtb \ - armada-388-helios4.dtb \ - armada-388-rd.dtb -dtb-$(CONFIG_MACH_ARMADA_39X) += \ - armada-390-db.dtb \ - armada-395-gp.dtb \ - armada-398-db.dtb -dtb-$(CONFIG_MACH_ARMADA_XP) += \ - armada-xp-axpwifiap.dtb \ - armada-xp-crs305-1g-4s.dtb \ - armada-xp-crs305-1g-4s-bit.dtb \ - armada-xp-crs326-24g-2s.dtb \ - armada-xp-crs326-24g-2s-bit.dtb \ - armada-xp-crs328-4c-20s-4s.dtb \ - armada-xp-crs328-4c-20s-4s-bit.dtb \ - armada-xp-db.dtb \ - armada-xp-db-dxbc2.dtb \ - armada-xp-db-xc3-24g4xg.dtb \ - armada-xp-gp.dtb \ - armada-xp-lenovo-ix4-300d.dtb \ - armada-xp-linksys-mamba.dtb \ - armada-xp-matrix.dtb \ - armada-xp-netgear-rn2120.dtb \ - armada-xp-openblocks-ax3-4.dtb \ - armada-xp-synology-ds414.dtb -dtb-$(CONFIG_MACH_DOVE) += \ - dove-cubox.dtb \ - dove-cubox-es.dtb \ - dove-d2plug.dtb \ - dove-d3plug.dtb \ - dove-dove-db.dtb \ - dove-sbc-a510.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += \ - mt2701-evb.dtb \ - mt6580-evbp1.dtb \ - mt6582-prestigio-pmt5008-3g.dtb \ - mt6589-aquaris5.dtb \ - mt6589-fairphone-fp1.dtb \ - mt6592-evb.dtb \ - mt7623a-rfb-emmc.dtb \ - mt7623a-rfb-nand.dtb \ - mt7623n-rfb-emmc.dtb \ - mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb \ - mt8127-moose.dtb \ - mt8135-evbp1.dtb -dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb -dtb-$(CONFIG_ARCH_MSTARV7) += \ - mstar-infinity-msc313-breadbee_crust.dtb \ - mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ - mstar-infinity2m-ssd202d-miyoo-mini.dtb \ - mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ - mstar-infinity2m-ssd202d-ssd201htv2.dtb \ - mstar-infinity2m-ssd202d-unitv2.dtb \ - mstar-infinity3-msc313e-breadbee.dtb \ - mstar-mercury5-ssc8336n-midrived08.dtb -dtb-$(CONFIG_ARCH_ASPEED) += \ - aspeed-ast2500-evb.dtb \ - aspeed-ast2600-evb-a1.dtb \ - aspeed-ast2600-evb.dtb \ - aspeed-bmc-amd-daytonax.dtb \ - aspeed-bmc-amd-ethanolx.dtb \ - aspeed-bmc-ampere-mtjade.dtb \ - aspeed-bmc-ampere-mtmitchell.dtb \ - aspeed-bmc-arm-stardragon4800-rep2.dtb \ - aspeed-bmc-asrock-e3c246d4i.dtb \ - aspeed-bmc-asrock-romed8hm3.dtb \ - aspeed-bmc-bytedance-g220a.dtb \ - aspeed-bmc-delta-ahe50dc.dtb \ - aspeed-bmc-facebook-bletchley.dtb \ - aspeed-bmc-facebook-cloudripper.dtb \ - aspeed-bmc-facebook-cmm.dtb \ - aspeed-bmc-facebook-elbert.dtb \ - aspeed-bmc-facebook-fuji.dtb \ - aspeed-bmc-facebook-galaxy100.dtb \ - aspeed-bmc-facebook-greatlakes.dtb \ - aspeed-bmc-facebook-minipack.dtb \ - aspeed-bmc-facebook-tiogapass.dtb \ - aspeed-bmc-facebook-wedge40.dtb \ - aspeed-bmc-facebook-wedge100.dtb \ - aspeed-bmc-facebook-wedge400.dtb \ - aspeed-bmc-facebook-yamp.dtb \ - aspeed-bmc-facebook-yosemitev2.dtb \ - aspeed-bmc-ibm-bonnell.dtb \ - aspeed-bmc-ibm-everest.dtb \ - aspeed-bmc-ibm-rainier.dtb \ - aspeed-bmc-ibm-rainier-1s4u.dtb \ - aspeed-bmc-ibm-rainier-4u.dtb \ - aspeed-bmc-intel-s2600wf.dtb \ - aspeed-bmc-inspur-fp5280g2.dtb \ - aspeed-bmc-inspur-nf5280m6.dtb \ - aspeed-bmc-inspur-on5263m5.dtb \ - aspeed-bmc-lenovo-hr630.dtb \ - aspeed-bmc-lenovo-hr855xg2.dtb \ - aspeed-bmc-microsoft-olympus.dtb \ - aspeed-bmc-opp-lanyang.dtb \ - aspeed-bmc-opp-mowgli.dtb \ - aspeed-bmc-opp-nicole.dtb \ - aspeed-bmc-opp-palmetto.dtb \ - aspeed-bmc-opp-romulus.dtb \ - aspeed-bmc-opp-swift.dtb \ - aspeed-bmc-opp-tacoma.dtb \ - aspeed-bmc-opp-vesnin.dtb \ - aspeed-bmc-opp-witherspoon.dtb \ - aspeed-bmc-opp-zaius.dtb \ - aspeed-bmc-portwell-neptune.dtb \ - aspeed-bmc-qcom-dc-scm-v1.dtb \ - aspeed-bmc-quanta-q71l.dtb \ - aspeed-bmc-quanta-s6q.dtb \ - aspeed-bmc-supermicro-x11spi.dtb \ - aspeed-bmc-inventec-transformers.dtb \ - aspeed-bmc-tyan-s7106.dtb \ - aspeed-bmc-tyan-s8036.dtb \ - aspeed-bmc-ufispace-ncplite.dtb \ - aspeed-bmc-vegman-n110.dtb \ - aspeed-bmc-vegman-rx20.dtb \ - aspeed-bmc-vegman-sx20.dtb +subdir-y += actions +subdir-y += airoha +subdir-y += allwinner +subdir-y += alphascale +subdir-y += amazon +subdir-y += amlogic +subdir-y += arm +subdir-y += aspeed +subdir-y += axis +subdir-y += broadcom +subdir-y += calxeda +subdir-y += cirrus +subdir-y += cnxt +subdir-y += gemini +subdir-y += hisilicon +subdir-y += hpe +subdir-y += intel +subdir-y += marvell +subdir-y += mediatek +subdir-y += microchip +subdir-y += moxa +subdir-y += nspire +subdir-y += nuvoton +subdir-y += nvidia +subdir-y += nxp +subdir-y += qcom +subdir-y += realtek +subdir-y += renesas +subdir-y += rockchip +subdir-y += samsung +subdir-y += sigmastar +subdir-y += socionext +subdir-y += st +subdir-y += sunplus +subdir-y += synaptics +subdir-y += ti +subdir-y += unisoc +subdir-y += vt8500 +subdir-y += xen +subdir-y += xilinx diff --git a/arch/arm/boot/dts/actions/Makefile b/arch/arm/boot/dts/actions/Makefile new file mode 100644 index 0000000000000..f384e4a48e6f6 --- /dev/null +++ b/arch/arm/boot/dts/actions/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ACTIONS) += \ + owl-s500-cubieboard6.dtb \ + owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-labrador-base-m.dtb \ + owl-s500-roseapplepi.dtb \ + owl-s500-sparky.dtb diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-cubieboard6.dts rename to arch/arm/boot/dts/actions/owl-s500-cubieboard6.dts diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts rename to arch/arm/boot/dts/actions/owl-s500-guitar-bb-rev-b.dts diff --git a/arch/arm/boot/dts/owl-s500-guitar.dtsi b/arch/arm/boot/dts/actions/owl-s500-guitar.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500-guitar.dtsi rename to arch/arm/boot/dts/actions/owl-s500-guitar.dtsi diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-labrador-base-m.dts rename to arch/arm/boot/dts/actions/owl-s500-labrador-base-m.dts diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500-labrador-v2.dtsi rename to arch/arm/boot/dts/actions/owl-s500-labrador-v2.dtsi diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-roseapplepi.dts rename to arch/arm/boot/dts/actions/owl-s500-roseapplepi.dts diff --git a/arch/arm/boot/dts/owl-s500-sparky.dts b/arch/arm/boot/dts/actions/owl-s500-sparky.dts similarity index 100% rename from arch/arm/boot/dts/owl-s500-sparky.dts rename to arch/arm/boot/dts/actions/owl-s500-sparky.dts diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/actions/owl-s500.dtsi similarity index 100% rename from arch/arm/boot/dts/owl-s500.dtsi rename to arch/arm/boot/dts/actions/owl-s500.dtsi diff --git a/arch/arm/boot/dts/airoha/Makefile b/arch/arm/boot/dts/airoha/Makefile new file mode 100644 index 0000000000000..00c31389f622e --- /dev/null +++ b/arch/arm/boot/dts/airoha/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/airoha/en7523-evb.dts similarity index 100% rename from arch/arm/boot/dts/en7523-evb.dts rename to arch/arm/boot/dts/airoha/en7523-evb.dts diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/airoha/en7523.dtsi similarity index 100% rename from arch/arm/boot/dts/en7523.dtsi rename to arch/arm/boot/dts/airoha/en7523.dtsi diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile new file mode 100644 index 0000000000000..589a1ce1120aa --- /dev/null +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ + sun4i-a10-chuwi-v7-cw0825.dtb \ + sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ + sun4i-a10-gemei-g9.dtb \ + sun4i-a10-hackberry.dtb \ + sun4i-a10-hyundai-a7hd.dtb \ + sun4i-a10-inet1.dtb \ + sun4i-a10-inet97fv2.dtb \ + sun4i-a10-inet9f-rev03.dtb \ + sun4i-a10-itead-iteaduino-plus.dtb \ + sun4i-a10-jesurun-q5.dtb \ + sun4i-a10-marsboard.dtb \ + sun4i-a10-mini-xplus.dtb \ + sun4i-a10-mk802.dtb \ + sun4i-a10-mk802ii.dtb \ + sun4i-a10-olinuxino-lime.dtb \ + sun4i-a10-pcduino.dtb \ + sun4i-a10-pcduino2.dtb \ + sun4i-a10-pov-protab2-ips9.dtb \ + sun4i-a10-topwise-a721.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN5I) += \ + sun5i-a10s-auxtek-t003.dtb \ + sun5i-a10s-auxtek-t004.dtb \ + sun5i-a10s-mk802.dtb \ + sun5i-a10s-olinuxino-micro.dtb \ + sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ + sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ + sun5i-a13-hsg-h702.dtb \ + sun5i-a13-inet-98v-rev2.dtb \ + sun5i-a13-licheepi-one.dtb \ + sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-q8-tablet.dtb \ + sun5i-a13-utoo-p66.dtb \ + sun5i-gr8-chip-pro.dtb \ + sun5i-gr8-evb.dtb \ + sun5i-r8-chip.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN6I) += \ + sun6i-a31-app4-evb1.dtb \ + sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ + sun6i-a31-i7.dtb \ + sun6i-a31-m9.dtb \ + sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ + sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ + sun6i-a31s-primo81.dtb \ + sun6i-a31s-sina31s.dtb \ + sun6i-a31s-sinovoip-bpi-m2.dtb \ + sun6i-a31s-yones-toptech-bs1078-v2.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ + sun7i-a20-bananapi-m1-plus.dtb \ + sun7i-a20-bananapro.dtb \ + sun7i-a20-cubieboard2.dtb \ + sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ + sun7i-a20-hummingbird.dtb \ + sun7i-a20-itead-ibox.dtb \ + sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-icnova-a20-adb4006.dtb \ + sun7i-a20-icnova-swac.dtb \ + sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-mk808c.dtb \ + sun7i-a20-olimex-som-evb.dtb \ + sun7i-a20-olimex-som-evb-emmc.dtb \ + sun7i-a20-olimex-som204-evb.dtb \ + sun7i-a20-olimex-som204-evb-emmc.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ + sun7i-a20-pcduino3-nano.dtb \ + sun7i-a20-wexler-tab7200.dtb \ + sun7i-a20-wits-pro-a20-dkt.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-evb.dtb \ + sun8i-a23-gt90h-v4.dtb \ + sun8i-a23-inet86dz.dtb \ + sun8i-a23-ippo-q8h-v5.dtb \ + sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2407pxe03.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ + sun8i-a23-q8-tablet.dtb \ + sun8i-a33-et-q8-v1.6.dtb \ + sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ + sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-bananapi-m2-plus-v1.2.dtb \ + sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ + sun8i-h3-nanopi-duo2.dtb \ + sun8i-h3-nanopi-m1.dtb\ + \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ + sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ + sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-super-nes-classic.dtb \ + sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ + sun8i-s3-elimo-initium.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ + sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb +dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ + suniv-f1c200s-popstick-v1.1.dtb diff --git a/arch/arm/boot/dts/axp152.dtsi b/arch/arm/boot/dts/allwinner/axp152.dtsi similarity index 100% rename from arch/arm/boot/dts/axp152.dtsi rename to arch/arm/boot/dts/allwinner/axp152.dtsi diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/allwinner/axp209.dtsi similarity index 100% rename from arch/arm/boot/dts/axp209.dtsi rename to arch/arm/boot/dts/allwinner/axp209.dtsi diff --git a/arch/arm/boot/dts/axp223.dtsi b/arch/arm/boot/dts/allwinner/axp223.dtsi similarity index 100% rename from arch/arm/boot/dts/axp223.dtsi rename to arch/arm/boot/dts/allwinner/axp223.dtsi diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/allwinner/axp22x.dtsi similarity index 100% rename from arch/arm/boot/dts/axp22x.dtsi rename to arch/arm/boot/dts/allwinner/axp22x.dtsi diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/allwinner/axp809.dtsi similarity index 100% rename from arch/arm/boot/dts/axp809.dtsi rename to arch/arm/boot/dts/allwinner/axp809.dtsi diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi similarity index 100% rename from arch/arm/boot/dts/axp81x.dtsi rename to arch/arm/boot/dts/allwinner/axp81x.dtsi diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-a1000.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-a1000.dts diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-ba10-tvbox.dts diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-chuwi-v7-cw0825.dts diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-cubieboard.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-gemei-g9.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-hackberry.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-hackberry.dts diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-hyundai-a7hd.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet1.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet97fv2.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet97fv2.dts diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-inet9f-rev03.dts diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-itead-iteaduino-plus.dts diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-jesurun-q5.dts diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-marsboard.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-marsboard.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mini-xplus.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mini-xplus.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mk802.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mk802.dts diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-mk802ii.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-mk802ii.dts diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-olinuxino-lime.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pcduino.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pcduino.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pcduino2.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pcduino2.dts diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts diff --git a/arch/arm/boot/dts/sun4i-a10-topwise-a721.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts similarity index 100% rename from arch/arm/boot/dts/sun4i-a10-topwise-a721.dts rename to arch/arm/boot/dts/allwinner/sun4i-a10-topwise-a721.dts diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi similarity index 100% rename from arch/arm/boot/dts/sun4i-a10.dtsi rename to arch/arm/boot/dts/allwinner/sun4i-a10.dtsi diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t003.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-auxtek-t004.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-mk802.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-mk802.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-r7-tv-dongle.dts diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts rename to arch/arm/boot/dts/allwinner/sun5i-a10s-wobo-i5.dts diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-a10s.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-a10s.dtsi diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-difrnce-dit4350.dts diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-d709.dts diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-empire-electronix-m712.dts diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-hsg-h702.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-hsg-h702.dts diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-inet-98v-rev2.dts diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-licheepi-one.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-licheepi-one.dts diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-olinuxino.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts diff --git a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-a13-utoo-p66.dts rename to arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-a13.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-a13.dtsi diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8-chip-pro.dts rename to arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8-evb.dts rename to arch/arm/boot/dts/allwinner/sun5i-gr8-evb.dts diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-gr8.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-gr8.dtsi diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts similarity index 100% rename from arch/arm/boot/dts/sun5i-r8-chip.dts rename to arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/allwinner/sun5i-r8.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-r8.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-r8.dtsi diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun5i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi similarity index 100% rename from arch/arm/boot/dts/sun5i.dtsi rename to arch/arm/boot/dts/allwinner/sun5i.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-app4-evb1.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-app4-evb1.dts diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-colombus.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-colombus.dts diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-hummingbird.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-i7.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-i7.dts diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-m9.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-m9.dts diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31-mele-a1000g-quad.dts diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-colorfly-e708-q1.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-cs908.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-cs908.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-inet-q972.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-inet-q972.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-primo81.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s-core.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sina31s.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sina31s.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts rename to arch/arm/boot/dts/allwinner/sun6i-a31s-yones-toptech-bs1078-v2.dts diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-a31s.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-a31s.dtsi diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun6i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapi.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-bananapro.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-cubieboard2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-cubieboard2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-cubietruck.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts diff --git a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-haoyu-marsboard.dts diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-hummingbird.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-i12-tvbox.dts diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-icnova-a20-adb4006.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20-adb4006.dts diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-icnova-a20.dtsi rename to arch/arm/boot/dts/allwinner/sun7i-a20-icnova-a20.dtsi diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-icnova-swac.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-icnova-swac.dts diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-itead-ibox.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-itead-ibox.dts diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-lamobo-r1.dts diff --git a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-linutronix-testbox-v2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-m3.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-m3.dts diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-mk808c.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-mk808c.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-orangepi.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3-nano.dts diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-pcduino3.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-pcduino3.dts diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-wexler-tab7200.dts diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts similarity index 100% rename from arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts rename to arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi similarity index 100% rename from arch/arm/boot/dts/sun7i-a20.dtsi rename to arch/arm/boot/dts/allwinner/sun7i-a20.dtsi diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-a33.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-evb.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-evb.dts diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-gt90h-v4.dts diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-inet86dz.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-inet86dz.dts diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-ippo-q8h-v5.dts diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a23-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun8i-a23-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a23.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a23.dtsi diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-et-q8-v1.6.dts diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-ippo-q8h-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-olinuxino.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-olinuxino.dts diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-q8-tablet.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-q8-tablet.dts diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts rename to arch/arm/boot/dts/allwinner/sun8i-a33-sinlinx-sina33.dts diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a33.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a33.dtsi diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-allwinner-h8homlet-v2.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts rename to arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-a83t.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-libretech-all-h3-cc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-libretech-all-h3-cc.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus-v1.2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-beelink-x2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dts diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-mapleboard-mp130.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-nanopi.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-one.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-plus2e.dts diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts diff --git a/arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-rervision-dvk.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-h3-zeropi.dts rename to arch/arm/boot/dts/allwinner/sun8i-h3-zeropi.dts diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-h3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-h3.dtsi diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-q8-common.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-nes-classic.dts diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-nintendo-super-nes-classic.dts diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r16-parrot.dts rename to arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts rename to arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts diff --git a/arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-cpu-opp.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-feta40i.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-r40-oka40i-c.dts rename to arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-r40.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-r40.dtsi diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-s3-elimo-impetus.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-elimo-initium.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-elimo-initium.dts diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-lichee-zero-plus.dts diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-s3-pinecube.dts rename to arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts rename to arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-t113s.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts rename to arch/arm/boot/dts/allwinner/sun8i-t3-cqa3t-bv3.dts diff --git a/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3-sl631-imx179.dts diff --git a/arch/arm/boot/dts/sun8i-v3-sl631.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-v3-sl631.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3-sl631.dtsi diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-v3.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3.dtsi diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero-dock.dts diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts rename to arch/arm/boot/dts/allwinner/sun8i-v3s-licheepi-zero.dts diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi similarity index 100% rename from arch/arm/boot/dts/sun8i-v3s.dtsi rename to arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts similarity index 100% rename from arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts rename to arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts similarity index 100% rename from arch/arm/boot/dts/sun9i-a80-cubieboard4.dts rename to arch/arm/boot/dts/allwinner/sun9i-a80-cubieboard4.dts diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts similarity index 100% rename from arch/arm/boot/dts/sun9i-a80-optimus.dts rename to arch/arm/boot/dts/allwinner/sun9i-a80-optimus.dts diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi similarity index 100% rename from arch/arm/boot/dts/sun9i-a80.dtsi rename to arch/arm/boot/dts/allwinner/sun9i-a80.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi similarity index 100% rename from arch/arm/boot/dts/suniv-f1c100s.dtsi rename to arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c200s-lctech-pi.dts diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts rename to arch/arm/boot/dts/allwinner/suniv-f1c200s-popstick-v1.1.dts diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-common-regulators.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-common-regulators.dtsi diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-h3-h5.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-itead-core-common.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-itead-core-common.dtsi diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-cc.dtsi diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-libretech-all-h3-it.dtsi diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi similarity index 100% rename from arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi rename to arch/arm/boot/dts/allwinner/sunxi-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/alphascale/Makefile b/arch/arm/boot/dts/alphascale/Makefile new file mode 100644 index 0000000000000..8d1314fc79d01 --- /dev/null +++ b/arch/arm/boot/dts/alphascale/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb +dtb-$(CONFIG_MACH_ASM9260) += \ + alphascale-asm9260-devkit.dtb diff --git a/arch/arm/boot/dts/alphascale-asm9260-devkit.dts b/arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts similarity index 100% rename from arch/arm/boot/dts/alphascale-asm9260-devkit.dts rename to arch/arm/boot/dts/alphascale/alphascale-asm9260-devkit.dts diff --git a/arch/arm/boot/dts/alphascale-asm9260.dtsi b/arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi similarity index 100% rename from arch/arm/boot/dts/alphascale-asm9260.dtsi rename to arch/arm/boot/dts/alphascale/alphascale-asm9260.dtsi diff --git a/arch/arm/boot/dts/amazon/Makefile b/arch/arm/boot/dts/amazon/Makefile new file mode 100644 index 0000000000000..58af5c4846efc --- /dev/null +++ b/arch/arm/boot/dts/amazon/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb +dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb diff --git a/arch/arm/boot/dts/alpine-db.dts b/arch/arm/boot/dts/amazon/alpine-db.dts similarity index 100% rename from arch/arm/boot/dts/alpine-db.dts rename to arch/arm/boot/dts/amazon/alpine-db.dts diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/amazon/alpine.dtsi similarity index 100% rename from arch/arm/boot/dts/alpine.dtsi rename to arch/arm/boot/dts/amazon/alpine.dtsi diff --git a/arch/arm/boot/dts/amlogic/Makefile b/arch/arm/boot/dts/amlogic/Makefile new file mode 100644 index 0000000000000..a84310780ea34 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_MESON6) += \ + meson6-atv1200.dtb +dtb-$(CONFIG_MACH_MESON8) += \ + meson8-minix-neo-x8.dtb \ + meson8b-ec100.dtb \ + meson8b-mxq.dtb \ + meson8b-odroidc1.dtb \ + meson8m2-mxiii-plus.dtb diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi similarity index 100% rename from arch/arm/boot/dts/meson.dtsi rename to arch/arm/boot/dts/amlogic/meson.dtsi diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/amlogic/meson6-atv1200.dts similarity index 100% rename from arch/arm/boot/dts/meson6-atv1200.dts rename to arch/arm/boot/dts/amlogic/meson6-atv1200.dts diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/amlogic/meson6.dtsi similarity index 100% rename from arch/arm/boot/dts/meson6.dtsi rename to arch/arm/boot/dts/amlogic/meson6.dtsi diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts similarity index 100% rename from arch/arm/boot/dts/meson8-minix-neo-x8.dts rename to arch/arm/boot/dts/amlogic/meson8-minix-neo-x8.dts diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi similarity index 100% rename from arch/arm/boot/dts/meson8.dtsi rename to arch/arm/boot/dts/amlogic/meson8.dtsi diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-ec100.dts rename to arch/arm/boot/dts/amlogic/meson8b-ec100.dts diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-mxq.dts rename to arch/arm/boot/dts/amlogic/meson8b-mxq.dts diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts similarity index 100% rename from arch/arm/boot/dts/meson8b-odroidc1.dts rename to arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi similarity index 100% rename from arch/arm/boot/dts/meson8b.dtsi rename to arch/arm/boot/dts/amlogic/meson8b.dtsi diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts similarity index 100% rename from arch/arm/boot/dts/meson8m2-mxiii-plus.dts rename to arch/arm/boot/dts/amlogic/meson8m2-mxiii-plus.dts diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi similarity index 100% rename from arch/arm/boot/dts/meson8m2.dtsi rename to arch/arm/boot/dts/amlogic/meson8m2.dtsi diff --git a/arch/arm/boot/dts/arm/Makefile b/arch/arm/boot/dts/arm/Makefile new file mode 100644 index 0000000000000..07ebb64e2cd01 --- /dev/null +++ b/arch/arm/boot/dts/arm/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEGRATOR) += \ + integratorap.dtb \ + integratorap-im-pd1.dtb \ + integratorcp.dtb +dtb-$(CONFIG_ARCH_MPS2) += \ + mps2-an385.dtb \ + mps2-an399.dtb +dtb-$(CONFIG_ARCH_REALVIEW) += \ + arm-realview-pb1176.dtb \ + arm-realview-pb11mp.dtb \ + arm-realview-eb.dtb \ + arm-realview-eb-bbrevd.dtb \ + arm-realview-eb-11mp.dtb \ + arm-realview-eb-11mp-bbrevd.dtb \ + arm-realview-eb-11mp-ctrevb.dtb \ + arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ + arm-realview-eb-a9mp.dtb \ + arm-realview-eb-a9mp-bbrevd.dtb \ + arm-realview-pba8.dtb \ + arm-realview-pbx-a9.dtb +dtb-$(CONFIG_ARCH_VERSATILE) += \ + versatile-ab.dtb \ + versatile-ab-ib2.dtb \ + versatile-pb.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += \ + vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb \ + vexpress-v2p-ca15-tc1.dtb \ + vexpress-v2p-ca15_a7.dtb diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd-ctrevb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp-ctrevb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-11mp.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-11mp.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-a9mp-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-a9mp.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-a9mp.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-bbrevd.dts rename to arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dts diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb-mp.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb-mp.dtsi diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm/arm-realview-eb.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb.dts rename to arch/arm/boot/dts/arm/arm-realview-eb.dts diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-eb.dtsi rename to arch/arm/boot/dts/arm/arm-realview-eb.dtsi diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pb1176.dts rename to arch/arm/boot/dts/arm/arm-realview-pb1176.dts diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pb11mp.dts rename to arch/arm/boot/dts/arm/arm-realview-pb11mp.dts diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm/arm-realview-pba8.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pba8.dts rename to arch/arm/boot/dts/arm/arm-realview-pba8.dts diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts similarity index 100% rename from arch/arm/boot/dts/arm-realview-pbx-a9.dts rename to arch/arm/boot/dts/arm/arm-realview-pbx-a9.dts diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi similarity index 100% rename from arch/arm/boot/dts/arm-realview-pbx.dtsi rename to arch/arm/boot/dts/arm/arm-realview-pbx.dtsi diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/arm/integrator.dtsi similarity index 100% rename from arch/arm/boot/dts/integrator.dtsi rename to arch/arm/boot/dts/arm/integrator.dtsi diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts similarity index 100% rename from arch/arm/boot/dts/integratorap-im-pd1.dts rename to arch/arm/boot/dts/arm/integratorap-im-pd1.dts diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts similarity index 100% rename from arch/arm/boot/dts/integratorap.dts rename to arch/arm/boot/dts/arm/integratorap.dts diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/arm/integratorcp.dts similarity index 100% rename from arch/arm/boot/dts/integratorcp.dts rename to arch/arm/boot/dts/arm/integratorcp.dts diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/arm/mps2-an385.dts similarity index 100% rename from arch/arm/boot/dts/mps2-an385.dts rename to arch/arm/boot/dts/arm/mps2-an385.dts diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/arm/mps2-an399.dts similarity index 100% rename from arch/arm/boot/dts/mps2-an399.dts rename to arch/arm/boot/dts/arm/mps2-an399.dts diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi similarity index 99% rename from arch/arm/boot/dts/mps2.dtsi rename to arch/arm/boot/dts/arm/mps2.dtsi index b99577d411b19..ce308820765b8 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -42,7 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" / { #address-cells = <1>; diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/arm/versatile-ab-ib2.dts similarity index 100% rename from arch/arm/boot/dts/versatile-ab-ib2.dts rename to arch/arm/boot/dts/arm/versatile-ab-ib2.dts diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts similarity index 100% rename from arch/arm/boot/dts/versatile-ab.dts rename to arch/arm/boot/dts/arm/versatile-ab.dts diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/arm/versatile-pb.dts similarity index 100% rename from arch/arm/boot/dts/versatile-pb.dts rename to arch/arm/boot/dts/arm/versatile-pb.dts diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi similarity index 100% rename from arch/arm/boot/dts/vexpress-v2m-rs1.dtsi rename to arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi similarity index 100% rename from arch/arm/boot/dts/vexpress-v2m.dtsi rename to arch/arm/boot/dts/arm/vexpress-v2m.dtsi diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca5s.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts similarity index 100% rename from arch/arm/boot/dts/vexpress-v2p-ca9.dts rename to arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile new file mode 100644 index 0000000000000..c68984322a86c --- /dev/null +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ASPEED) += \ + aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ + aspeed-ast2600-evb.dtb \ + aspeed-bmc-amd-daytonax.dtb \ + aspeed-bmc-amd-ethanolx.dtb \ + aspeed-bmc-ampere-mtjade.dtb \ + aspeed-bmc-ampere-mtmitchell.dtb \ + aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-romed8hm3.dtb \ + aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-bletchley.dtb \ + aspeed-bmc-facebook-cloudripper.dtb \ + aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-elbert.dtb \ + aspeed-bmc-facebook-fuji.dtb \ + aspeed-bmc-facebook-galaxy100.dtb \ + aspeed-bmc-facebook-greatlakes.dtb \ + aspeed-bmc-facebook-minipack.dtb \ + aspeed-bmc-facebook-tiogapass.dtb \ + aspeed-bmc-facebook-wedge40.dtb \ + aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400.dtb \ + aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-facebook-yosemitev2.dtb \ + aspeed-bmc-ibm-bonnell.dtb \ + aspeed-bmc-ibm-everest.dtb \ + aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-1s4u.dtb \ + aspeed-bmc-ibm-rainier-4u.dtb \ + aspeed-bmc-intel-s2600wf.dtb \ + aspeed-bmc-inspur-fp5280g2.dtb \ + aspeed-bmc-inspur-nf5280m6.dtb \ + aspeed-bmc-inspur-on5263m5.dtb \ + aspeed-bmc-lenovo-hr630.dtb \ + aspeed-bmc-lenovo-hr855xg2.dtb \ + aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-opp-lanyang.dtb \ + aspeed-bmc-opp-mowgli.dtb \ + aspeed-bmc-opp-nicole.dtb \ + aspeed-bmc-opp-palmetto.dtb \ + aspeed-bmc-opp-romulus.dtb \ + aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-tacoma.dtb \ + aspeed-bmc-opp-vesnin.dtb \ + aspeed-bmc-opp-witherspoon.dtb \ + aspeed-bmc-opp-zaius.dtb \ + aspeed-bmc-portwell-neptune.dtb \ + aspeed-bmc-qcom-dc-scm-v1.dtb \ + aspeed-bmc-quanta-q71l.dtb \ + aspeed-bmc-quanta-s6q.dtb \ + aspeed-bmc-supermicro-x11spi.dtb \ + aspeed-bmc-inventec-transformers.dtb \ + aspeed-bmc-tyan-s7106.dtb \ + aspeed-bmc-tyan-s8036.dtb \ + aspeed-bmc-ufispace-ncplite.dtb \ + aspeed-bmc-vegman-n110.dtb \ + aspeed-bmc-vegman-rx20.dtb \ + aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2500-evb.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2600-evb-a1.dts diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-ast2600-evb.dts rename to arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-amd-daytonax.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-amd-ethanolx.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-greatlakes.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge40.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemitev2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-1s4u.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier-4u.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-nf5280m6.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-on5263m5.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-intel-s2600wf.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-microsoft-olympus.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-swift.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-swift.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-portwell-neptune.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-qcom-dc-scm-v1.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-supermicro-x11spi.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s7106.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-tyan-s8036.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-ufispace-ncplite.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts diff --git a/arch/arm/boot/dts/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-bmc-vegman.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g4.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g4.dtsi diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g5.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g5.dtsi diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi similarity index 100% rename from arch/arm/boot/dts/aspeed-g6.dtsi rename to arch/arm/boot/dts/aspeed/aspeed-g6.dtsi diff --git a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2400-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi rename to arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi similarity index 100% rename from arch/arm/boot/dts/facebook-bmc-flash-layout-128.dtsi rename to arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128.dtsi diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi similarity index 100% rename from arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi rename to arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout.dtsi diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi similarity index 100% rename from arch/arm/boot/dts/ibm-power9-dual.dtsi rename to arch/arm/boot/dts/aspeed/ibm-power9-dual.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-128.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-128.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-64-alt.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-64-alt.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout-64.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout-64.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi similarity index 100% rename from arch/arm/boot/dts/openbmc-flash-layout.dtsi rename to arch/arm/boot/dts/aspeed/openbmc-flash-layout.dtsi diff --git a/arch/arm/boot/dts/axis/Makefile b/arch/arm/boot/dts/axis/Makefile new file mode 100644 index 0000000000000..2cab41451281a --- /dev/null +++ b/arch/arm/boot/dts/axis/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb +dtb-$(CONFIG_MACH_ARTPEC6) += \ + artpec6-devboard.dtb diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/axis/artpec6-devboard.dts similarity index 100% rename from arch/arm/boot/dts/artpec6-devboard.dts rename to arch/arm/boot/dts/axis/artpec6-devboard.dts diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi similarity index 100% rename from arch/arm/boot/dts/artpec6.dtsi rename to arch/arm/boot/dts/axis/artpec6.dtsi diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile new file mode 100644 index 0000000000000..95b0ef2a42152 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays +DTC_FLAGS_bcm2835-rpi-b := -@ +DTC_FLAGS_bcm2835-rpi-a := -@ +DTC_FLAGS_bcm2835-rpi-b-rev2 := -@ +DTC_FLAGS_bcm2835-rpi-b-plus := -@ +DTC_FLAGS_bcm2835-rpi-a-plus := -@ +DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ +DTC_FLAGS_bcm2836-rpi-2-b := -@ +DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ +DTC_FLAGS_bcm2837-rpi-3-b := -@ +DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ +DTC_FLAGS_bcm2837-rpi-cm3-io3 := -@ +DTC_FLAGS_bcm2837-rpi-zero-2-w := -@ +DTC_FLAGS_bcm2711-rpi-400 := -@ +DTC_FLAGS_bcm2711-rpi-4-b := -@ +DTC_FLAGS_bcm2711-rpi-cm4-io := -@ +DTC_FLAGS_bcm2835-rpi-zero := -@ +DTC_FLAGS_bcm2835-rpi-zero-w := -@ +dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-a.dtb \ + bcm2835-rpi-b-rev2.dtb \ + bcm2835-rpi-b-plus.dtb \ + bcm2835-rpi-a-plus.dtb \ + bcm2835-rpi-cm1-io1.dtb \ + bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb \ + bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-cm4-io.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb \ + bcm963138.dtb \ + bcm963138dvt.dtb \ + bcm963148.dtb \ + bcm963178.dtb \ + bcm96756.dtb \ + bcm96846.dtb \ + bcm96855.dtb \ + bcm96878.dtb +dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp.dtb \ + bcm4708-buffalo-wzr-1166dhp2.dtb \ + bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-linksys-ea6500-v2.dtb \ + bcm4708-luxul-xap-1510.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ + bcm4708-smartrg-sr400ac.dtb \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm47081-luxul-xap-1410.dtb \ + bcm47081-luxul-xwr-1200.dtb \ + bcm47081-tplink-archer-c5-v2.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-linksys-ea9200.dtb \ + bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ + bcm47094-asus-rt-ac88u.dtb \ + bcm47094-dlink-dir-885l.dtb \ + bcm47094-dlink-dir-890l.dtb \ + bcm47094-linksys-panamera.dtb \ + bcm47094-luxul-abr-4500.dtb \ + bcm47094-luxul-xap-1610.dtb \ + bcm47094-luxul-xbr-4500.dtb \ + bcm47094-luxul-xwc-2000.dtb \ + bcm47094-luxul-xwr-3100.dtb \ + bcm47094-luxul-xwr-3150-v1.dtb \ + bcm47094-netgear-r8500.dtb \ + bcm47094-phicomm-k3.dtb \ + bcm53015-meraki-mr26.dtb \ + bcm53016-dlink-dwl-8610ap.dtb \ + bcm53016-meraki-mr32.dtb \ + bcm94708.dtb \ + bcm94709.dtb \ + bcm953012er.dtb \ + bcm953012hr.dtb \ + bcm953012k.dtb +dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-luxul-xap-1440.dtb \ + bcm47189-luxul-xap-810.dtb \ + bcm47189-tenda-ac9.dtb \ + bcm947189acdbmr.dtb +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ + bcm911360_entphn.dtb \ + bcm911360k.dtb \ + bcm958300k.dtb \ + bcm958305k.dtb +dtb-$(CONFIG_ARCH_BCM_HR2) += \ + bcm53340-ubnt-unifi-switch8.dtb +dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ + bcm28155-ap.dtb \ + bcm21664-garnet.dtb \ + bcm23550-sparrow.dtb +dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958522er.dtb \ + bcm958525er.dtb \ + bcm958525xmc.dtb \ + bcm958622hr.dtb \ + bcm958623hr.dtb \ + bcm958625-meraki-mx64.dtb \ + bcm958625-meraki-mx64-a0.dtb \ + bcm958625-meraki-mx64w.dtb \ + bcm958625-meraki-mx64w-a0.dtb \ + bcm958625-meraki-mx65.dtb \ + bcm958625-meraki-mx65w.dtb \ + bcm958625hr.dtb \ + bcm988312hr.dtb \ + bcm958625k.dtb +dtb-$(CONFIG_ARCH_BRCMSTB) += \ + bcm7445-bcm97445svmb.dtb diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-cygnus-clock.dtsi rename to arch/arm/boot/dts/broadcom/bcm-cygnus-clock.dtsi diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-cygnus.dtsi rename to arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-hr2.dtsi rename to arch/arm/boot/dts/broadcom/bcm-hr2.dtsi diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-ns.dtsi rename to arch/arm/boot/dts/broadcom/bcm-ns.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp-ax.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-nsp-ax.dtsi rename to arch/arm/boot/dts/broadcom/bcm-nsp-ax.dtsi diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm-nsp.dtsi rename to arch/arm/boot/dts/broadcom/bcm-nsp.dtsi diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/broadcom/bcm11351.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm11351.dtsi rename to arch/arm/boot/dts/broadcom/bcm11351.dtsi diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/broadcom/bcm21664-garnet.dts similarity index 100% rename from arch/arm/boot/dts/bcm21664-garnet.dts rename to arch/arm/boot/dts/broadcom/bcm21664-garnet.dts diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/broadcom/bcm21664.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm21664.dtsi rename to arch/arm/boot/dts/broadcom/bcm21664.dtsi diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts similarity index 100% rename from arch/arm/boot/dts/bcm23550-sparrow.dts rename to arch/arm/boot/dts/broadcom/bcm23550-sparrow.dts diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/broadcom/bcm23550.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm23550.dtsi rename to arch/arm/boot/dts/broadcom/bcm23550.dtsi diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-4-b.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-400.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dtsi diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2711.dtsi rename to arch/arm/boot/dts/broadcom/bcm2711.dtsi diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts similarity index 100% rename from arch/arm/boot/dts/bcm28155-ap.dts rename to arch/arm/boot/dts/broadcom/bcm28155-ap.dts diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-common.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-a-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-a.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-b.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-zero-w.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi-zero.dts rename to arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/broadcom/bcm2835.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2835.dtsi rename to arch/arm/boot/dts/broadcom/bcm2835.dtsi diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2836-rpi-2-b.dts rename to arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2836-rpi.dtsi rename to arch/arm/boot/dts/broadcom/bcm2836-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/broadcom/bcm2836.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2836.dtsi rename to arch/arm/boot/dts/broadcom/bcm2836.dtsi diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-3-b.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-3-b.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3.dtsi diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts similarity index 100% rename from arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts rename to arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/broadcom/bcm2837.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm2837.dtsi rename to arch/arm/boot/dts/broadcom/bcm2837.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-led-deprecated.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9512.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-otg.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-usb-peripheral.dtsi diff --git a/arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x-rpi-wifi-bt.dtsi diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm283x.dtsi rename to arch/arm/boot/dts/broadcom/bcm283x.dtsi diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts rename to arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac56u.dts diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts rename to arch/arm/boot/dts/broadcom/bcm4708-asus-rt-ac68u.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp2.dts diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1750dhp.dts diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts rename to arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6300-v1.dts diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts rename to arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts rename to arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-netgear-r6250.dts rename to arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts rename to arch/arm/boot/dts/broadcom/bcm4708-netgear-r6300-v2.dts diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts similarity index 100% rename from arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts rename to arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/broadcom/bcm4708.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm4708.dtsi rename to arch/arm/boot/dts/broadcom/bcm4708.dtsi diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts rename to arch/arm/boot/dts/broadcom/bcm47081-asus-rt-n18u.dts diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts rename to arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts rename to arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-900dhp.dts diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts rename to arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts rename to arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts similarity index 100% rename from arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts rename to arch/arm/boot/dts/broadcom/bcm47081-tplink-archer-c5-v2.dts diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/broadcom/bcm47081.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm47081.dtsi rename to arch/arm/boot/dts/broadcom/bcm47081.dtsi diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts rename to arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts rename to arch/arm/boot/dts/broadcom/bcm4709-buffalo-wxr-1900dhp.dts diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-linksys-ea9200.dts rename to arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-netgear-r7000.dts rename to arch/arm/boot/dts/broadcom/bcm4709-netgear-r7000.dts diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-netgear-r8000.dts rename to arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts similarity index 100% rename from arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts rename to arch/arm/boot/dts/broadcom/bcm4709-tplink-archer-c9-v1.dts diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/broadcom/bcm4709.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm4709.dtsi rename to arch/arm/boot/dts/broadcom/bcm4709.dtsi diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts rename to arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts rename to arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts rename to arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-linksys-panamera.dts rename to arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts rename to arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-netgear-r8500.dts rename to arch/arm/boot/dts/broadcom/bcm47094-netgear-r8500.dts diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts similarity index 100% rename from arch/arm/boot/dts/bcm47094-phicomm-k3.dts rename to arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/broadcom/bcm47094.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm47094.dtsi rename to arch/arm/boot/dts/broadcom/bcm47094.dtsi diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts rename to arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-luxul-xap-810.dts rename to arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts similarity index 100% rename from arch/arm/boot/dts/bcm47189-tenda-ac9.dts rename to arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/broadcom/bcm47622.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm47622.dtsi rename to arch/arm/boot/dts/broadcom/bcm47622.dtsi diff --git a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts similarity index 100% rename from arch/arm/boot/dts/bcm53015-meraki-mr26.dts rename to arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts diff --git a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts similarity index 100% rename from arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts rename to arch/arm/boot/dts/broadcom/bcm53016-dlink-dwl-8610ap.dts diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts similarity index 100% rename from arch/arm/boot/dts/bcm53016-meraki-mr32.dts rename to arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch1.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch4.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0-bch8.dtsi diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x-nand-cs0.dtsi diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm5301x.dtsi rename to arch/arm/boot/dts/broadcom/bcm5301x.dtsi diff --git a/arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts similarity index 100% rename from arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dts rename to arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/broadcom/bcm53573.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm53573.dtsi rename to arch/arm/boot/dts/broadcom/bcm53573.dtsi diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/broadcom/bcm59056.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm59056.dtsi rename to arch/arm/boot/dts/broadcom/bcm59056.dtsi diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm63138.dtsi rename to arch/arm/boot/dts/broadcom/bcm63138.dtsi diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm63148.dtsi rename to arch/arm/boot/dts/broadcom/bcm63148.dtsi diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/broadcom/bcm63178.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm63178.dtsi rename to arch/arm/boot/dts/broadcom/bcm63178.dtsi diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/broadcom/bcm6756.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm6756.dtsi rename to arch/arm/boot/dts/broadcom/bcm6756.dtsi diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm6846.dtsi rename to arch/arm/boot/dts/broadcom/bcm6846.dtsi diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm6855.dtsi rename to arch/arm/boot/dts/broadcom/bcm6855.dtsi diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm6878.dtsi rename to arch/arm/boot/dts/broadcom/bcm6878.dtsi diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts similarity index 100% rename from arch/arm/boot/dts/bcm7445-bcm97445svmb.dts rename to arch/arm/boot/dts/broadcom/bcm7445-bcm97445svmb.dts diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/broadcom/bcm7445.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm7445.dtsi rename to arch/arm/boot/dts/broadcom/bcm7445.dtsi diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/broadcom/bcm911360_entphn.dts similarity index 100% rename from arch/arm/boot/dts/bcm911360_entphn.dts rename to arch/arm/boot/dts/broadcom/bcm911360_entphn.dts diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/broadcom/bcm911360k.dts similarity index 100% rename from arch/arm/boot/dts/bcm911360k.dts rename to arch/arm/boot/dts/broadcom/bcm911360k.dts diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/broadcom/bcm94708.dts similarity index 100% rename from arch/arm/boot/dts/bcm94708.dts rename to arch/arm/boot/dts/broadcom/bcm94708.dts diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/broadcom/bcm94709.dts similarity index 100% rename from arch/arm/boot/dts/bcm94709.dts rename to arch/arm/boot/dts/broadcom/bcm94709.dts diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts similarity index 100% rename from arch/arm/boot/dts/bcm947189acdbmr.dts rename to arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/broadcom/bcm947622.dts similarity index 100% rename from arch/arm/boot/dts/bcm947622.dts rename to arch/arm/boot/dts/broadcom/bcm947622.dts diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/broadcom/bcm953012er.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012er.dts rename to arch/arm/boot/dts/broadcom/bcm953012er.dts diff --git a/arch/arm/boot/dts/bcm953012hr.dts b/arch/arm/boot/dts/broadcom/bcm953012hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012hr.dts rename to arch/arm/boot/dts/broadcom/bcm953012hr.dts diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/broadcom/bcm953012k.dts similarity index 100% rename from arch/arm/boot/dts/bcm953012k.dts rename to arch/arm/boot/dts/broadcom/bcm953012k.dts diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/broadcom/bcm958300k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958300k.dts rename to arch/arm/boot/dts/broadcom/bcm958300k.dts diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/broadcom/bcm958305k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958305k.dts rename to arch/arm/boot/dts/broadcom/bcm958305k.dts diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/broadcom/bcm958522er.dts similarity index 100% rename from arch/arm/boot/dts/bcm958522er.dts rename to arch/arm/boot/dts/broadcom/bcm958522er.dts diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/broadcom/bcm958525er.dts similarity index 100% rename from arch/arm/boot/dts/bcm958525er.dts rename to arch/arm/boot/dts/broadcom/bcm958525er.dts diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts similarity index 100% rename from arch/arm/boot/dts/bcm958525xmc.dts rename to arch/arm/boot/dts/broadcom/bcm958525xmc.dts diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/broadcom/bcm958622hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958622hr.dts rename to arch/arm/boot/dts/broadcom/bcm958622hr.dts diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/broadcom/bcm958623hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958623hr.dts rename to arch/arm/boot/dts/broadcom/bcm958623hr.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-kingpin.dtsi diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64-a0.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w-a0.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx64w.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx64w.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx65.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx65w.dts rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx65w.dts diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi rename to arch/arm/boot/dts/broadcom/bcm958625-meraki-mx6x-common.dtsi diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/broadcom/bcm958625hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625hr.dts rename to arch/arm/boot/dts/broadcom/bcm958625hr.dts diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/broadcom/bcm958625k.dts similarity index 100% rename from arch/arm/boot/dts/bcm958625k.dts rename to arch/arm/boot/dts/broadcom/bcm958625k.dts diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/broadcom/bcm963138.dts similarity index 100% rename from arch/arm/boot/dts/bcm963138.dts rename to arch/arm/boot/dts/broadcom/bcm963138.dts diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/broadcom/bcm963138dvt.dts similarity index 100% rename from arch/arm/boot/dts/bcm963138dvt.dts rename to arch/arm/boot/dts/broadcom/bcm963138dvt.dts diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/broadcom/bcm963148.dts similarity index 100% rename from arch/arm/boot/dts/bcm963148.dts rename to arch/arm/boot/dts/broadcom/bcm963148.dts diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/broadcom/bcm963178.dts similarity index 100% rename from arch/arm/boot/dts/bcm963178.dts rename to arch/arm/boot/dts/broadcom/bcm963178.dts diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/broadcom/bcm96756.dts similarity index 100% rename from arch/arm/boot/dts/bcm96756.dts rename to arch/arm/boot/dts/broadcom/bcm96756.dts diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/broadcom/bcm96846.dts similarity index 100% rename from arch/arm/boot/dts/bcm96846.dts rename to arch/arm/boot/dts/broadcom/bcm96846.dts diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/broadcom/bcm96855.dts similarity index 100% rename from arch/arm/boot/dts/bcm96855.dts rename to arch/arm/boot/dts/broadcom/bcm96855.dts diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/broadcom/bcm96878.dts similarity index 100% rename from arch/arm/boot/dts/bcm96878.dts rename to arch/arm/boot/dts/broadcom/bcm96878.dts diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/broadcom/bcm988312hr.dts similarity index 100% rename from arch/arm/boot/dts/bcm988312hr.dts rename to arch/arm/boot/dts/broadcom/bcm988312hr.dts diff --git a/arch/arm/boot/dts/bcm9hmidc.dtsi b/arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi similarity index 100% rename from arch/arm/boot/dts/bcm9hmidc.dtsi rename to arch/arm/boot/dts/broadcom/bcm9hmidc.dtsi diff --git a/arch/arm/boot/dts/calxeda/Makefile b/arch/arm/boot/dts/calxeda/Makefile new file mode 100644 index 0000000000000..f5126b6d26adc --- /dev/null +++ b/arch/arm/boot/dts/calxeda/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb +dtb-$(CONFIG_ARCH_HIGHBANK) += \ + highbank.dtb \ + ecx-2000.dtb diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/calxeda/ecx-2000.dts similarity index 100% rename from arch/arm/boot/dts/ecx-2000.dts rename to arch/arm/boot/dts/calxeda/ecx-2000.dts diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/calxeda/ecx-common.dtsi similarity index 100% rename from arch/arm/boot/dts/ecx-common.dtsi rename to arch/arm/boot/dts/calxeda/ecx-common.dtsi diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/calxeda/highbank.dts similarity index 100% rename from arch/arm/boot/dts/highbank.dts rename to arch/arm/boot/dts/calxeda/highbank.dts diff --git a/arch/arm/boot/dts/cirrus/Makefile b/arch/arm/boot/dts/cirrus/Makefile new file mode 100644 index 0000000000000..e944d3e2129db --- /dev/null +++ b/arch/arm/boot/dts/cirrus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb +dtb-$(CONFIG_ARCH_CLPS711X) += \ + ep7211-edb7211.dtb diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/cirrus/ep7209.dtsi similarity index 100% rename from arch/arm/boot/dts/ep7209.dtsi rename to arch/arm/boot/dts/cirrus/ep7209.dtsi diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts similarity index 100% rename from arch/arm/boot/dts/ep7211-edb7211.dts rename to arch/arm/boot/dts/cirrus/ep7211-edb7211.dts diff --git a/arch/arm/boot/dts/ep7211.dtsi b/arch/arm/boot/dts/cirrus/ep7211.dtsi similarity index 100% rename from arch/arm/boot/dts/ep7211.dtsi rename to arch/arm/boot/dts/cirrus/ep7211.dtsi diff --git a/arch/arm/boot/dts/cnxt/Makefile b/arch/arm/boot/dts/cnxt/Makefile new file mode 100644 index 0000000000000..d49df53f65a16 --- /dev/null +++ b/arch/arm/boot/dts/cnxt/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_DIGICOLOR) += \ + cx92755_equinox.dtb diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cnxt/cx92755.dtsi similarity index 100% rename from arch/arm/boot/dts/cx92755.dtsi rename to arch/arm/boot/dts/cnxt/cx92755.dtsi diff --git a/arch/arm/boot/dts/cx92755_equinox.dts b/arch/arm/boot/dts/cnxt/cx92755_equinox.dts similarity index 100% rename from arch/arm/boot/dts/cx92755_equinox.dts rename to arch/arm/boot/dts/cnxt/cx92755_equinox.dts diff --git a/arch/arm/boot/dts/gemini/Makefile b/arch/arm/boot/dts/gemini/Makefile new file mode 100644 index 0000000000000..f9f63ce3eb496 --- /dev/null +++ b/arch/arm/boot/dts/gemini/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_GEMINI) += \ + gemini-dlink-dir-685.dtb \ + gemini-dlink-dns-313.dtb \ + gemini-nas4220b.dtb \ + gemini-ns2502.dtb \ + gemini-rut1xx.dtb \ + gemini-sl93512r.dtb \ + gemini-sq201.dtb \ + gemini-ssi1328.dtb \ + gemini-wbd111.dtb \ + gemini-wbd222.dtb diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts similarity index 100% rename from arch/arm/boot/dts/gemini-dlink-dir-685.dts rename to arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts similarity index 100% rename from arch/arm/boot/dts/gemini-dlink-dns-313.dts rename to arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini/gemini-nas4220b.dts similarity index 100% rename from arch/arm/boot/dts/gemini-nas4220b.dts rename to arch/arm/boot/dts/gemini/gemini-nas4220b.dts diff --git a/arch/arm/boot/dts/gemini-ns2502.dts b/arch/arm/boot/dts/gemini/gemini-ns2502.dts similarity index 100% rename from arch/arm/boot/dts/gemini-ns2502.dts rename to arch/arm/boot/dts/gemini/gemini-ns2502.dts diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini/gemini-rut1xx.dts similarity index 100% rename from arch/arm/boot/dts/gemini-rut1xx.dts rename to arch/arm/boot/dts/gemini/gemini-rut1xx.dts diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts similarity index 100% rename from arch/arm/boot/dts/gemini-sl93512r.dts rename to arch/arm/boot/dts/gemini/gemini-sl93512r.dts diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini/gemini-sq201.dts similarity index 100% rename from arch/arm/boot/dts/gemini-sq201.dts rename to arch/arm/boot/dts/gemini/gemini-sq201.dts diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini/gemini-ssi1328.dts similarity index 100% rename from arch/arm/boot/dts/gemini-ssi1328.dts rename to arch/arm/boot/dts/gemini/gemini-ssi1328.dts diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini/gemini-wbd111.dts similarity index 100% rename from arch/arm/boot/dts/gemini-wbd111.dts rename to arch/arm/boot/dts/gemini/gemini-wbd111.dts diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini/gemini-wbd222.dts similarity index 100% rename from arch/arm/boot/dts/gemini-wbd222.dts rename to arch/arm/boot/dts/gemini/gemini-wbd222.dts diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini/gemini.dtsi similarity index 100% rename from arch/arm/boot/dts/gemini.dtsi rename to arch/arm/boot/dts/gemini/gemini.dtsi diff --git a/arch/arm/boot/dts/hisilicon/Makefile b/arch/arm/boot/dts/hisilicon/Makefile new file mode 100644 index 0000000000000..5ce0512c0010e --- /dev/null +++ b/arch/arm/boot/dts/hisilicon/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HI3xxx) += \ + hi3620-hi4511.dtb +dtb-$(CONFIG_ARCH_HIP01) += \ + hip01-ca9x2.dtb +dtb-$(CONFIG_ARCH_HIP04) += \ + hip04-d01.dtb +dtb-$(CONFIG_ARCH_HISI) += \ + hi3519-demb.dtb +dtb-$(CONFIG_ARCH_HIX5HD2) += \ + hisi-x5hd2-dkb.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hisilicon/hi3519-demb.dts similarity index 100% rename from arch/arm/boot/dts/hi3519-demb.dts rename to arch/arm/boot/dts/hisilicon/hi3519-demb.dts diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hisilicon/hi3519.dtsi similarity index 100% rename from arch/arm/boot/dts/hi3519.dtsi rename to arch/arm/boot/dts/hisilicon/hi3519.dtsi diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts similarity index 100% rename from arch/arm/boot/dts/hi3620-hi4511.dts rename to arch/arm/boot/dts/hisilicon/hi3620-hi4511.dts diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hisilicon/hi3620.dtsi similarity index 100% rename from arch/arm/boot/dts/hi3620.dtsi rename to arch/arm/boot/dts/hisilicon/hi3620.dtsi diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts similarity index 100% rename from arch/arm/boot/dts/hip01-ca9x2.dts rename to arch/arm/boot/dts/hisilicon/hip01-ca9x2.dts diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hisilicon/hip01.dtsi similarity index 100% rename from arch/arm/boot/dts/hip01.dtsi rename to arch/arm/boot/dts/hisilicon/hip01.dtsi diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hisilicon/hip04-d01.dts similarity index 100% rename from arch/arm/boot/dts/hip04-d01.dts rename to arch/arm/boot/dts/hisilicon/hip04-d01.dts diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hisilicon/hip04.dtsi similarity index 100% rename from arch/arm/boot/dts/hip04.dtsi rename to arch/arm/boot/dts/hisilicon/hip04.dtsi diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts similarity index 100% rename from arch/arm/boot/dts/hisi-x5hd2-dkb.dts rename to arch/arm/boot/dts/hisilicon/hisi-x5hd2-dkb.dts diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi similarity index 100% rename from arch/arm/boot/dts/hisi-x5hd2.dtsi rename to arch/arm/boot/dts/hisilicon/hisi-x5hd2.dtsi diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/hisilicon/sd5203.dts similarity index 100% rename from arch/arm/boot/dts/sd5203.dts rename to arch/arm/boot/dts/hisilicon/sd5203.dts diff --git a/arch/arm/boot/dts/hpe/Makefile b/arch/arm/boot/dts/hpe/Makefile new file mode 100644 index 0000000000000..e175b1732cdb5 --- /dev/null +++ b/arch/arm/boot/dts/hpe/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_HPE_GXP) += \ + hpe-bmc-dl360gen10.dtb diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts similarity index 100% rename from arch/arm/boot/dts/hpe-bmc-dl360gen10.dts rename to arch/arm/boot/dts/hpe/hpe-bmc-dl360gen10.dts diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe/hpe-gxp.dtsi similarity index 100% rename from arch/arm/boot/dts/hpe-gxp.dtsi rename to arch/arm/boot/dts/hpe/hpe-gxp.dtsi diff --git a/arch/arm/boot/dts/intel/Makefile b/arch/arm/boot/dts/intel/Makefile new file mode 100644 index 0000000000000..c5fc845deb61c --- /dev/null +++ b/arch/arm/boot/dts/intel/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += axm +subdir-y += ixp +subdir-y += pxa +subdir-y += socfpga diff --git a/arch/arm/boot/dts/intel/axm/Makefile b/arch/arm/boot/dts/intel/axm/Makefile new file mode 100644 index 0000000000000..7c7dc679964d1 --- /dev/null +++ b/arch/arm/boot/dts/intel/axm/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb +dtb-$(CONFIG_ARCH_AXXIA) += \ + axm5516-amarillo.dtb diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts similarity index 100% rename from arch/arm/boot/dts/axm5516-amarillo.dts rename to arch/arm/boot/dts/intel/axm/axm5516-amarillo.dts diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/axm5516-cpus.dtsi rename to arch/arm/boot/dts/intel/axm/axm5516-cpus.dtsi diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/intel/axm/axm55xx.dtsi similarity index 100% rename from arch/arm/boot/dts/axm55xx.dtsi rename to arch/arm/boot/dts/intel/axm/axm55xx.dtsi diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile new file mode 100644 index 0000000000000..1a25ce3cf84f0 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-linksys-wrv54g.dtb \ + intel-ixp42x-freecom-fsg-3.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ + intel-ixp42x-ixdp425.dtb \ + intel-ixp43x-kixrp435.dtb \ + intel-ixp46x-ixdp465.dtb \ + intel-ixp42x-adi-coyote.dtb \ + intel-ixp42x-ixdpg425.dtb \ + intel-ixp42x-goramo-multilink.dtb \ + intel-ixp42x-iomega-nas100d.dtb \ + intel-ixp42x-dlink-dsm-g600.dtb \ + intel-ixp42x-gateworks-gw2348.dtb \ + intel-ixp43x-gateworks-gw2358.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ + intel-ixp42x-arcom-vulcan.dtb \ + intel-ixp42x-gateway-7001.dtb diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-adi-coyote.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-arcom-vulcan.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateworks-gw2348.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-ixdp425.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdp425.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-ixdpg425.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x-welltech-epbx100.dts diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp42x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp42x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x-gateworks-gw2358.dts diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x-kixrp435.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp43x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp43x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp45x-ixp46x.dtsi diff --git a/arch/arm/boot/dts/intel-ixp46x-ixdp465.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts similarity index 100% rename from arch/arm/boot/dts/intel-ixp46x-ixdp465.dts rename to arch/arm/boot/dts/intel/ixp/intel-ixp46x-ixdp465.dts diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp4xx-reference-design.dtsi diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi similarity index 100% rename from arch/arm/boot/dts/intel-ixp4xx.dtsi rename to arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi diff --git a/arch/arm/boot/dts/intel/pxa/Makefile b/arch/arm/boot/dts/intel/pxa/Makefile new file mode 100644 index 0000000000000..24d5240f08e7e --- /dev/null +++ b/arch/arm/boot/dts/intel/pxa/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PXA) += \ + pxa300-raumfeld-connector.dtb \ + pxa300-raumfeld-controller.dtb \ + pxa300-raumfeld-speaker-l.dtb \ + pxa300-raumfeld-speaker-m.dtb \ + pxa300-raumfeld-speaker-one.dtb \ + pxa300-raumfeld-speaker-s.dtb diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa25x.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa25x.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa25x.dtsi diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/intel/pxa/pxa27x.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa27x.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa27x.dtsi diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa2xx.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa2xx.dtsi diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-common.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-common.dtsi diff --git a/arch/arm/boot/dts/pxa300-raumfeld-connector.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-connector.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-connector.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-controller.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-controller.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-l.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-m.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-one.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-speaker-s.dts diff --git a/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi b/arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa300-raumfeld-tuneable-clock.dtsi diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa3xx.dtsi rename to arch/arm/boot/dts/intel/pxa/pxa3xx.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile new file mode 100644 index 0000000000000..c467828aeb4b0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ + socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_pe1.dtb \ + socfpga_arria10_socdk_nand.dtb \ + socfpga_arria10_socdk_qspi.dtb \ + socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ + socfpga_cyclone5_mcvevk.dtb \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sodia.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_vt.dtb diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_chameleonv3.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_nand.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_qspi.dts diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria10_socdk_sdmmc.dts diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_arria5.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria5.dtsi diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_arria5_socdk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5.dtsi diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcv.dtsi diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_socdk.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_sockit.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_socrates.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_sodia.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dts diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dts diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts similarity index 100% rename from arch/arm/boot/dts/socfpga_vt.dts rename to arch/arm/boot/dts/intel/socfpga/socfpga_vt.dts diff --git a/arch/arm/boot/dts/marvell/Makefile b/arch/arm/boot/dts/marvell/Makefile new file mode 100644 index 0000000000000..1e0f5ff492f78 --- /dev/null +++ b/arch/arm/boot/dts/marvell/Makefile @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MMP) += \ + pxa168-aspenite.dtb \ + pxa910-dkb.dtb \ + mmp2-brownstone.dtb \ + mmp2-olpc-xo-1-75.dtb \ + mmp3-dell-ariel.dtb +dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-kuroboxpro.dtb \ + orion5x-lacie-d2-network.dtb \ + orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-linkstation-lsgl.dtb \ + orion5x-linkstation-lswtgl.dtb \ + orion5x-linkstation-lschl.dtb \ + orion5x-lswsgl.dtb \ + orion5x-maxtor-shared-storage-2.dtb \ + orion5x-netgear-wnr854t.dtb \ + orion5x-rd88f5182-nas.dtb +dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-c200-v2.dtb \ + armada-370-db.dtb \ + armada-370-dlink-dns327l.dtb \ + armada-370-mirabox.dtb \ + armada-370-netgear-rn102.dtb \ + armada-370-netgear-rn104.dtb \ + armada-370-rd.dtb \ + armada-370-seagate-nas-2bay.dtb \ + armada-370-seagate-nas-4bay.dtb \ + armada-370-seagate-personal-cloud.dtb \ + armada-370-seagate-personal-cloud-2bay.dtb \ + armada-370-synology-ds213j.dtb +dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb +dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-381-netgear-gs110emx.dtb \ + armada-382-rd-ac3x-48g4x2xl.dtb \ + armada-385-atl-x530.dtb \ + armada-385-clearfog-gtr-s4.dtb \ + armada-385-clearfog-gtr-l8.dtb \ + armada-385-db-88f6820-amc.dtb \ + armada-385-db-ap.dtb \ + armada-385-linksys-caiman.dtb \ + armada-385-linksys-cobra.dtb \ + armada-385-linksys-rango.dtb \ + armada-385-linksys-shelby.dtb \ + armada-385-synology-ds116.dtb \ + armada-385-turris-omnia.dtb \ + armada-388-clearfog.dtb \ + armada-388-clearfog-base.dtb \ + armada-388-clearfog-pro.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-helios4.dtb \ + armada-388-rd.dtb +dtb-$(CONFIG_MACH_ARMADA_39X) += \ + armada-390-db.dtb \ + armada-395-gp.dtb \ + armada-398-db.dtb +dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ + armada-xp-db.dtb \ + armada-xp-db-dxbc2.dtb \ + armada-xp-db-xc3-24g4xg.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ + armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb \ + armada-xp-synology-ds414.dtb +dtb-$(CONFIG_MACH_DOVE) += \ + dove-cubox.dtb \ + dove-cubox-es.dtb \ + dove-d2plug.dtb \ + dove-d3plug.dtb \ + dove-dove-db.dtb \ + dove-sbc-a510.dtb +dtb-$(CONFIG_MACH_KIRKWOOD) += \ + kirkwood-4i-edge-200.dtb \ + kirkwood-b3.dtb \ + kirkwood-blackarmor-nas220.dtb \ + kirkwood-c200-v1.dtb \ + kirkwood-cloudbox.dtb \ + kirkwood-d2net.dtb \ + kirkwood-db-88f6281.dtb \ + kirkwood-db-88f6282.dtb \ + kirkwood-dir665.dtb \ + kirkwood-dns320.dtb \ + kirkwood-dns325.dtb \ + kirkwood-dockstar.dtb \ + kirkwood-dreamplug.dtb \ + kirkwood-ds109.dtb \ + kirkwood-ds110jv10.dtb \ + kirkwood-ds111.dtb \ + kirkwood-ds112.dtb \ + kirkwood-ds209.dtb \ + kirkwood-ds210.dtb \ + kirkwood-ds212.dtb \ + kirkwood-ds212j.dtb \ + kirkwood-ds409.dtb \ + kirkwood-ds409slim.dtb \ + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ + kirkwood-iconnect.dtb \ + kirkwood-iomega_ix2_200.dtb \ + kirkwood-is2.dtb \ + kirkwood-km_fixedeth.dtb \ + kirkwood-km_kirkwood.dtb \ + kirkwood-l-50.dtb \ + kirkwood-laplug.dtb \ + kirkwood-linkstation-lsqvl.dtb \ + kirkwood-linkstation-lsvl.dtb \ + kirkwood-linkstation-lswsxl.dtb \ + kirkwood-linkstation-lswvl.dtb \ + kirkwood-linkstation-lswxl.dtb \ + kirkwood-linksys-viper.dtb \ + kirkwood-lschlv2.dtb \ + kirkwood-lsxhl.dtb \ + kirkwood-mplcec4.dtb \ + kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ + kirkwood-net2big.dtb \ + kirkwood-net5big.dtb \ + kirkwood-netgear_readynas_duo_v2.dtb \ + kirkwood-netgear_readynas_nv+_v2.dtb \ + kirkwood-ns2.dtb \ + kirkwood-ns2lite.dtb \ + kirkwood-ns2max.dtb \ + kirkwood-ns2mini.dtb \ + kirkwood-nsa310.dtb \ + kirkwood-nsa310a.dtb \ + kirkwood-nsa310s.dtb \ + kirkwood-nsa320.dtb \ + kirkwood-nsa325.dtb \ + kirkwood-openblocks_a6.dtb \ + kirkwood-openblocks_a7.dtb \ + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ + kirkwood-pogo_e02.dtb \ + kirkwood-pogoplug-series-4.dtb \ + kirkwood-rd88f6192.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ + kirkwood-rs212.dtb \ + kirkwood-rs409.dtb \ + kirkwood-rs411.dtb \ + kirkwood-sheevaplug.dtb \ + kirkwood-sheevaplug-esata.dtb \ + kirkwood-t5325.dtb \ + kirkwood-topkick.dtb \ + kirkwood-ts219-6281.dtb \ + kirkwood-ts219-6282.dtb \ + kirkwood-ts419-6281.dtb \ + kirkwood-ts419-6282.dtb diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/marvell/armada-370-c200-v2.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-c200-v2.dts rename to arch/arm/boot/dts/marvell/armada-370-c200-v2.dts diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/marvell/armada-370-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-db.dts rename to arch/arm/boot/dts/marvell/armada-370-db.dts diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-dlink-dns327l.dts rename to arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/marvell/armada-370-mirabox.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-mirabox.dts rename to arch/arm/boot/dts/marvell/armada-370-mirabox.dts diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-netgear-rn102.dts rename to arch/arm/boot/dts/marvell/armada-370-netgear-rn102.dts diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-netgear-rn104.dts rename to arch/arm/boot/dts/marvell/armada-370-netgear-rn104.dts diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/marvell/armada-370-rd.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-rd.dts rename to arch/arm/boot/dts/marvell/armada-370-rd.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-2bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi rename to arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dts diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi rename to arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts similarity index 100% rename from arch/arm/boot/dts/armada-370-synology-ds213j.dts rename to arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370-xp.dtsi rename to arch/arm/boot/dts/marvell/armada-370-xp.dtsi diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/marvell/armada-370.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-370.dtsi rename to arch/arm/boot/dts/marvell/armada-370.dtsi diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/marvell/armada-375-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-375-db.dts rename to arch/arm/boot/dts/marvell/armada-375-db.dts diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-375.dtsi rename to arch/arm/boot/dts/marvell/armada-375.dtsi diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-380.dtsi rename to arch/arm/boot/dts/marvell/armada-380.dtsi diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts similarity index 100% rename from arch/arm/boot/dts/armada-381-netgear-gs110emx.dts rename to arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts diff --git a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts similarity index 100% rename from arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts rename to arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts diff --git a/arch/arm/boot/dts/armada-385-atl-x530.dts b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-atl-x530.dts rename to arch/arm/boot/dts/marvell/armada-385-atl-x530.dts diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi rename to arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-db-88f6820-amc.dts rename to arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/marvell/armada-385-db-ap.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-db-ap.dts rename to arch/arm/boot/dts/marvell/armada-385-db-ap.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-caiman.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-caiman.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-cobra.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-cobra.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-rango.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-rango.dts diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys-shelby.dts rename to arch/arm/boot/dts/marvell/armada-385-linksys-shelby.dts diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385-linksys.dtsi rename to arch/arm/boot/dts/marvell/armada-385-linksys.dtsi diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-synology-ds116.dts rename to arch/arm/boot/dts/marvell/armada-385-synology-ds116.dts diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts similarity index 100% rename from arch/arm/boot/dts/armada-385-turris-omnia.dts rename to arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/marvell/armada-385.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-385.dtsi rename to arch/arm/boot/dts/marvell/armada-385.dtsi diff --git a/arch/arm/boot/dts/armada-388-clearfog-base.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog-base.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts diff --git a/arch/arm/boot/dts/armada-388-clearfog-pro.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog-pro.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog-pro.dts diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog.dts rename to arch/arm/boot/dts/marvell/armada-388-clearfog.dts diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-388-clearfog.dtsi rename to arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/marvell/armada-388-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-db.dts rename to arch/arm/boot/dts/marvell/armada-388-db.dts diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/marvell/armada-388-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-gp.dts rename to arch/arm/boot/dts/marvell/armada-388-gp.dts diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-helios4.dts rename to arch/arm/boot/dts/marvell/armada-388-helios4.dts diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/marvell/armada-388-rd.dts similarity index 100% rename from arch/arm/boot/dts/armada-388-rd.dts rename to arch/arm/boot/dts/marvell/armada-388-rd.dts diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/marvell/armada-388.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-388.dtsi rename to arch/arm/boot/dts/marvell/armada-388.dtsi diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi rename to arch/arm/boot/dts/marvell/armada-38x-solidrun-microsom.dtsi diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-38x.dtsi rename to arch/arm/boot/dts/marvell/armada-38x.dtsi diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/marvell/armada-390-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-390-db.dts rename to arch/arm/boot/dts/marvell/armada-390-db.dts diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/marvell/armada-390.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-390.dtsi rename to arch/arm/boot/dts/marvell/armada-390.dtsi diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/marvell/armada-395-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-395-gp.dts rename to arch/arm/boot/dts/marvell/armada-395-gp.dts diff --git a/arch/arm/boot/dts/armada-395.dtsi b/arch/arm/boot/dts/marvell/armada-395.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-395.dtsi rename to arch/arm/boot/dts/marvell/armada-395.dtsi diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/marvell/armada-398-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-398-db.dts rename to arch/arm/boot/dts/marvell/armada-398-db.dts diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/marvell/armada-398.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-398.dtsi rename to arch/arm/boot/dts/marvell/armada-398.dtsi diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-39x.dtsi rename to arch/arm/boot/dts/marvell/armada-39x.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx3236.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx3336.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx3336.dtsi diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-98dx4251.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-98dx4251.dtsi diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-axpwifiap.dts rename to arch/arm/boot/dts/marvell/armada-xp-axpwifiap.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs305-1g-4s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs326-24g-2s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s-bit.dts diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dts diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-crs328-4c-20s-4s.dtsi diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db-dxbc2.dts rename to arch/arm/boot/dts/marvell/armada-xp-db-dxbc2.dts diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts rename to arch/arm/boot/dts/marvell/armada-xp-db-xc3-24g4xg.dts diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/marvell/armada-xp-db.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-db.dts rename to arch/arm/boot/dts/marvell/armada-xp-db.dts diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/marvell/armada-xp-gp.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-gp.dts rename to arch/arm/boot/dts/marvell/armada-xp-gp.dts diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts rename to arch/arm/boot/dts/marvell/armada-xp-lenovo-ix4-300d.dts diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-linksys-mamba.dts rename to arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/marvell/armada-xp-matrix.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-matrix.dts rename to arch/arm/boot/dts/marvell/armada-xp-matrix.dts diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78230.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78230.dtsi diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78260.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78260.dtsi diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp-mv78460.dtsi rename to arch/arm/boot/dts/marvell/armada-xp-mv78460.dtsi diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-netgear-rn2120.dts rename to arch/arm/boot/dts/marvell/armada-xp-netgear-rn2120.dts diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts rename to arch/arm/boot/dts/marvell/armada-xp-openblocks-ax3-4.dts diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts similarity index 100% rename from arch/arm/boot/dts/armada-xp-synology-ds414.dts rename to arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/marvell/armada-xp.dtsi similarity index 100% rename from arch/arm/boot/dts/armada-xp.dtsi rename to arch/arm/boot/dts/marvell/armada-xp.dtsi diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi similarity index 100% rename from arch/arm/boot/dts/dove-cm-a510.dtsi rename to arch/arm/boot/dts/marvell/dove-cm-a510.dtsi diff --git a/arch/arm/boot/dts/dove-cubox-es.dts b/arch/arm/boot/dts/marvell/dove-cubox-es.dts similarity index 100% rename from arch/arm/boot/dts/dove-cubox-es.dts rename to arch/arm/boot/dts/marvell/dove-cubox-es.dts diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts similarity index 100% rename from arch/arm/boot/dts/dove-cubox.dts rename to arch/arm/boot/dts/marvell/dove-cubox.dts diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/marvell/dove-d2plug.dts similarity index 100% rename from arch/arm/boot/dts/dove-d2plug.dts rename to arch/arm/boot/dts/marvell/dove-d2plug.dts diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/marvell/dove-d3plug.dts similarity index 100% rename from arch/arm/boot/dts/dove-d3plug.dts rename to arch/arm/boot/dts/marvell/dove-d3plug.dts diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/marvell/dove-dove-db.dts similarity index 100% rename from arch/arm/boot/dts/dove-dove-db.dts rename to arch/arm/boot/dts/marvell/dove-dove-db.dts diff --git a/arch/arm/boot/dts/dove-sbc-a510.dts b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts similarity index 100% rename from arch/arm/boot/dts/dove-sbc-a510.dts rename to arch/arm/boot/dts/marvell/dove-sbc-a510.dts diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/marvell/dove.dtsi similarity index 100% rename from arch/arm/boot/dts/dove.dtsi rename to arch/arm/boot/dts/marvell/dove.dtsi diff --git a/arch/arm/boot/dts/kirkwood-4i-edge-200.dts b/arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-4i-edge-200.dts rename to arch/arm/boot/dts/marvell/kirkwood-4i-edge-200.dts diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6192.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6192.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6192.dtsi diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-6282.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-6282.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-6282.dtsi diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-98dx4122.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-98dx4122.dtsi diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/marvell/kirkwood-b3.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-b3.dts rename to arch/arm/boot/dts/marvell/kirkwood-b3.dts diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts rename to arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts diff --git a/arch/arm/boot/dts/kirkwood-c200-v1.dts b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-c200-v1.dts rename to arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-cloudbox.dts rename to arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-d2net.dts rename to arch/arm/boot/dts/marvell/kirkwood-d2net.dts diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-db-88f6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-db-88f6281.dts diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-db-88f6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-db-88f6282.dts diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-db.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-db.dtsi diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dir665.dts rename to arch/arm/boot/dts/marvell/kirkwood-dir665.dts diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dns320.dts rename to arch/arm/boot/dts/marvell/kirkwood-dns320.dts diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dns325.dts rename to arch/arm/boot/dts/marvell/kirkwood-dns325.dts diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-dnskw.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dockstar.dts rename to arch/arm/boot/dts/marvell/kirkwood-dockstar.dts diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-dreamplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/marvell/kirkwood-ds109.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds109.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds109.dts diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds110jv10.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds110jv10.dts diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/marvell/kirkwood-ds111.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds111.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds111.dts diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/marvell/kirkwood-ds112.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds112.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds112.dts diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/marvell/kirkwood-ds209.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds209.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds209.dts diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/marvell/kirkwood-ds210.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds210.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds210.dts diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds212.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds212.dts diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds212j.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds212j.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds212j.dts diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds409.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds409.dts diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds409slim.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds409slim.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411j.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411j.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411j.dts diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ds411slim.dts rename to arch/arm/boot/dts/marvell/kirkwood-ds411slim.dts diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-goflexnet.dts rename to arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts rename to arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ib62x0.dts rename to arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-iconnect.dts rename to arch/arm/boot/dts/marvell/kirkwood-iconnect.dts diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts rename to arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/marvell/kirkwood-is2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-is2.dts rename to arch/arm/boot/dts/marvell/kirkwood-is2.dts diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-km_common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_fixedeth.dts rename to arch/arm/boot/dts/marvell/kirkwood-km_fixedeth.dts diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-km_kirkwood.dts rename to arch/arm/boot/dts/marvell/kirkwood-km_kirkwood.dts diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-l-50.dts rename to arch/arm/boot/dts/marvell/kirkwood-l-50.dts diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-laplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-laplug.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-6282.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-6282.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-duo-6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-duo-6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lsqvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lsqvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lsvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lsvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswsxl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswsxl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswvl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswvl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts b/arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation-lswxl.dts rename to arch/arm/boot/dts/marvell/kirkwood-linkstation-lswxl.dts diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-linkstation.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-linksys-viper.dts rename to arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-lschlv2.dts rename to arch/arm/boot/dts/marvell/kirkwood-lschlv2.dts diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-lsxhl.dts rename to arch/arm/boot/dts/marvell/kirkwood-lsxhl.dts diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-lsxl.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-mplcec4.dts rename to arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts rename to arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/marvell/kirkwood-nas2big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nas2big.dts rename to arch/arm/boot/dts/marvell/kirkwood-nas2big.dts diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/marvell/kirkwood-net2big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-net2big.dts rename to arch/arm/boot/dts/marvell/kirkwood-net2big.dts diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/marvell/kirkwood-net5big.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-net5big.dts rename to arch/arm/boot/dts/marvell/kirkwood-net5big.dts diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts rename to arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts rename to arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_nv+_v2.dts diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-netxbig.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2lite.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2max.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2max.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2max.dts diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ns2mini.dts rename to arch/arm/boot/dts/marvell/kirkwood-ns2mini.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310a.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa310s.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa320.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa320.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa325.dts rename to arch/arm/boot/dts/marvell/kirkwood-nsa325.dts diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openblocks_a6.dts rename to arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openblocks_a7.dts rename to arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-base.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-base.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-client.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-client.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd-ultimate.dts rename to arch/arm/boot/dts/marvell/kirkwood-openrd-ultimate.dts diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-openrd.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-pogo_e02.dts rename to arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts rename to arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6192.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6192.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281-a.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281-a.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281-z0.dts diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-rd88f6281.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-rd88f6281.dtsi diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/marvell/kirkwood-rs212.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs212.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs212.dts diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/marvell/kirkwood-rs409.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs409.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs409.dts diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/marvell/kirkwood-rs411.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-rs411.dts rename to arch/arm/boot/dts/marvell/kirkwood-rs411.dts diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug-common.dtsi diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-sheevaplug.dts rename to arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-synology.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-synology.dtsi diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-t5325.dts rename to arch/arm/boot/dts/marvell/kirkwood-t5325.dts diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/marvell/kirkwood-topkick.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-topkick.dts rename to arch/arm/boot/dts/marvell/kirkwood-topkick.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219-6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219-6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts219.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ts219.dtsi diff --git a/arch/arm/boot/dts/kirkwood-ts419-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419-6281.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts419-6281.dts diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419-6282.dts rename to arch/arm/boot/dts/marvell/kirkwood-ts419-6282.dts diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood-ts419.dtsi rename to arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/marvell/kirkwood.dtsi similarity index 100% rename from arch/arm/boot/dts/kirkwood.dtsi rename to arch/arm/boot/dts/marvell/kirkwood.dtsi diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts similarity index 100% rename from arch/arm/boot/dts/mmp2-brownstone.dts rename to arch/arm/boot/dts/marvell/mmp2-brownstone.dts diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts similarity index 100% rename from arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts rename to arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/marvell/mmp2.dtsi similarity index 100% rename from arch/arm/boot/dts/mmp2.dtsi rename to arch/arm/boot/dts/marvell/mmp2.dtsi diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts similarity index 100% rename from arch/arm/boot/dts/mmp3-dell-ariel.dts rename to arch/arm/boot/dts/marvell/mmp3-dell-ariel.dts diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/marvell/mmp3.dtsi similarity index 100% rename from arch/arm/boot/dts/mmp3.dtsi rename to arch/arm/boot/dts/marvell/mmp3.dtsi diff --git a/arch/arm/boot/dts/mvebu-linkstation-fan.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi similarity index 100% rename from arch/arm/boot/dts/mvebu-linkstation-fan.dtsi rename to arch/arm/boot/dts/marvell/mvebu-linkstation-fan.dtsi diff --git a/arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi similarity index 100% rename from arch/arm/boot/dts/mvebu-linkstation-gpio-simple.dtsi rename to arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi diff --git a/arch/arm/boot/dts/orion5x-kuroboxpro.dts b/arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-kuroboxpro.dts rename to arch/arm/boot/dts/marvell/orion5x-kuroboxpro.dts diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lacie-d2-network.dts rename to arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts rename to arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lschl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lsgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lsgl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lsgl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation-lswtgl.dts rename to arch/arm/boot/dts/marvell/orion5x-linkstation-lswtgl.dts diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-linkstation.dtsi rename to arch/arm/boot/dts/marvell/orion5x-linkstation.dtsi diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-lswsgl.dts rename to arch/arm/boot/dts/marvell/orion5x-lswsgl.dts diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts rename to arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-mv88f5181.dtsi rename to arch/arm/boot/dts/marvell/orion5x-mv88f5181.dtsi diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x-mv88f5182.dtsi rename to arch/arm/boot/dts/marvell/orion5x-mv88f5182.dtsi diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-netgear-wnr854t.dts rename to arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts similarity index 100% rename from arch/arm/boot/dts/orion5x-rd88f5182-nas.dts rename to arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/marvell/orion5x.dtsi similarity index 100% rename from arch/arm/boot/dts/orion5x.dtsi rename to arch/arm/boot/dts/marvell/orion5x.dtsi diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/marvell/pxa168-aspenite.dts similarity index 100% rename from arch/arm/boot/dts/pxa168-aspenite.dts rename to arch/arm/boot/dts/marvell/pxa168-aspenite.dts diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/marvell/pxa168.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa168.dtsi rename to arch/arm/boot/dts/marvell/pxa168.dtsi diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/marvell/pxa910-dkb.dts similarity index 100% rename from arch/arm/boot/dts/pxa910-dkb.dts rename to arch/arm/boot/dts/marvell/pxa910-dkb.dts diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/marvell/pxa910.dtsi similarity index 100% rename from arch/arm/boot/dts/pxa910.dtsi rename to arch/arm/boot/dts/marvell/pxa910.dtsi diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile new file mode 100644 index 0000000000000..1957947cb41ce --- /dev/null +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt2701-evb.dtb \ + mt6580-evbp1.dtb \ + mt6582-prestigio-pmt5008-3g.dtb \ + mt6589-aquaris5.dtb \ + mt6589-fairphone-fp1.dtb \ + mt6592-evb.dtb \ + mt7623a-rfb-emmc.dtb \ + mt7623a-rfb-nand.dtb \ + mt7623n-rfb-emmc.dtb \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts similarity index 100% rename from arch/arm/boot/dts/mt2701-evb.dts rename to arch/arm/boot/dts/mediatek/mt2701-evb.dts diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mediatek/mt2701-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/mt2701-pinfunc.h rename to arch/arm/boot/dts/mediatek/mt2701-pinfunc.h diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi similarity index 100% rename from arch/arm/boot/dts/mt2701.dtsi rename to arch/arm/boot/dts/mediatek/mt2701.dtsi diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6323.dtsi rename to arch/arm/boot/dts/mediatek/mt6323.dtsi diff --git a/arch/arm/boot/dts/mt6580-evbp1.dts b/arch/arm/boot/dts/mediatek/mt6580-evbp1.dts similarity index 100% rename from arch/arm/boot/dts/mt6580-evbp1.dts rename to arch/arm/boot/dts/mediatek/mt6580-evbp1.dts diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mediatek/mt6580.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6580.dtsi rename to arch/arm/boot/dts/mediatek/mt6580.dtsi diff --git a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts similarity index 100% rename from arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts rename to arch/arm/boot/dts/mediatek/mt6582-prestigio-pmt5008-3g.dts diff --git a/arch/arm/boot/dts/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6582.dtsi rename to arch/arm/boot/dts/mediatek/mt6582.dtsi diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts similarity index 100% rename from arch/arm/boot/dts/mt6589-aquaris5.dts rename to arch/arm/boot/dts/mediatek/mt6589-aquaris5.dts diff --git a/arch/arm/boot/dts/mt6589-fairphone-fp1.dts b/arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts similarity index 100% rename from arch/arm/boot/dts/mt6589-fairphone-fp1.dts rename to arch/arm/boot/dts/mediatek/mt6589-fairphone-fp1.dts diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6589.dtsi rename to arch/arm/boot/dts/mediatek/mt6589.dtsi diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mediatek/mt6592-evb.dts similarity index 100% rename from arch/arm/boot/dts/mt6592-evb.dts rename to arch/arm/boot/dts/mediatek/mt6592-evb.dts diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mediatek/mt6592.dtsi similarity index 100% rename from arch/arm/boot/dts/mt6592.dtsi rename to arch/arm/boot/dts/mediatek/mt6592.dtsi diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7623.dtsi rename to arch/arm/boot/dts/mediatek/mt7623.dtsi diff --git a/arch/arm/boot/dts/mt7623a-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/mt7623a-rfb-emmc.dts rename to arch/arm/boot/dts/mediatek/mt7623a-rfb-emmc.dts diff --git a/arch/arm/boot/dts/mt7623a-rfb-nand.dts b/arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts similarity index 100% rename from arch/arm/boot/dts/mt7623a-rfb-nand.dts rename to arch/arm/boot/dts/mediatek/mt7623a-rfb-nand.dts diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mediatek/mt7623a.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7623a.dtsi rename to arch/arm/boot/dts/mediatek/mt7623a.dtsi diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts similarity index 100% rename from arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts rename to arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts similarity index 100% rename from arch/arm/boot/dts/mt7623n-rfb-emmc.dts rename to arch/arm/boot/dts/mediatek/mt7623n-rfb-emmc.dts diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mediatek/mt7623n.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7623n.dtsi rename to arch/arm/boot/dts/mediatek/mt7623n.dtsi diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts similarity index 100% rename from arch/arm/boot/dts/mt7629-rfb.dts rename to arch/arm/boot/dts/mediatek/mt7629-rfb.dts diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mediatek/mt7629.dtsi similarity index 100% rename from arch/arm/boot/dts/mt7629.dtsi rename to arch/arm/boot/dts/mediatek/mt7629.dtsi diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mediatek/mt8127-moose.dts similarity index 100% rename from arch/arm/boot/dts/mt8127-moose.dts rename to arch/arm/boot/dts/mediatek/mt8127-moose.dts diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mediatek/mt8127.dtsi similarity index 100% rename from arch/arm/boot/dts/mt8127.dtsi rename to arch/arm/boot/dts/mediatek/mt8127.dtsi diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mediatek/mt8135-evbp1.dts similarity index 100% rename from arch/arm/boot/dts/mt8135-evbp1.dts rename to arch/arm/boot/dts/mediatek/mt8135-evbp1.dts diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mediatek/mt8135.dtsi similarity index 100% rename from arch/arm/boot/dts/mt8135.dtsi rename to arch/arm/boot/dts/mediatek/mt8135.dtsi diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile new file mode 100644 index 0000000000000..0f5193d05a31c --- /dev/null +++ b/arch/arm/boot/dts/microchip/Makefile @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0 +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_AT91RM9200) += \ + at91rm9200ek.dtb \ + mpa1600.dtb +dtb-$(CONFIG_SOC_AT91SAM9) += \ + animeo_ip.dtb \ + at91-qil_a9260.dtb \ + aks-cdu.dtb \ + ethernut5.dtb \ + evk-pro3.dtb \ + tny_a9260.dtb \ + usb_a9260.dtb \ + at91sam9260ek.dtb \ + at91sam9261ek.dtb \ + at91sam9263ek.dtb \ + at91-sam9_l9260.dtb \ + tny_a9263.dtb \ + usb_a9263.dtb \ + at91-foxg20.dtb \ + at91-kizbox.dtb \ + at91-lmu5000.dtb \ + at91sam9g20ek.dtb \ + at91sam9g20ek_2mmc.dtb \ + tny_a9g20.dtb \ + usb_a9g20.dtb \ + usb_a9g20_lpw.dtb \ + at91sam9m10g45ek.dtb \ + pm9g45.dtb \ + at91sam9n12ek.dtb \ + at91sam9rlek.dtb \ + at91-ariag25.dtb \ + at91-ariettag25.dtb \ + at91-cosino_mega2560.dtb \ + at91-kizboxmini-base.dtb \ + at91-kizboxmini-mb.dtb \ + at91-kizboxmini-rd.dtb \ + at91-q5xr5.dtb \ + at91-smartkiz.dtb \ + at91-wb45n.dtb \ + at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sam9x60_curiosity := -@ +DTC_FLAGS_at91-sam9x60ek := -@ +dtb-$(CONFIG_SOC_SAM9X60) += \ + at91-sam9x60_curiosity.dtb \ + at91-sam9x60ek.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama5d27_som1_ek := -@ +DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d2_icp := -@ +DTC_FLAGS_at91-sama5d2_ptc_ek := -@ +DTC_FLAGS_at91-sama5d2_xplained := -@ +DTC_FLAGS_at91-sama5d3_eds := -@ +DTC_FLAGS_at91-sama5d3_xplained := -@ +DTC_FLAGS_at91-sama5d4_xplained := -@ +dtb-$(CONFIG_SOC_SAM_V7) += \ + at91-kizbox2-2.dtb \ + at91-kizbox3-hs.dtb \ + at91-nattis-2-natte-2.dtb \ + at91-sama5d27_som1_ek.dtb \ + at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d2_icp.dtb \ + at91-sama5d2_ptc_ek.dtb \ + at91-sama5d2_xplained.dtb \ + at91-sama5d3_eds.dtb \ + at91-sama5d3_ksz9477_evb.dtb \ + at91-sama5d3_xplained.dtb \ + at91-dvk_som60.dtb \ + at91-gatwick.dtb \ + at91-tse850-3.dtb \ + at91-wb50n.dtb \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb \ + at91-sama5d4_ma5d4evk.dtb \ + at91-sama5d4_xplained.dtb \ + at91-sama5d4ek.dtb \ + at91-vinco.dtb +# Enables support for device-tree overlays +DTC_FLAGS_at91-sama7g5ek := -@ +dtb-$(CONFIG_SOC_SAMA7G5) += \ + at91-sama7g5ek.dtb + +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb \ + lan966x-pcb8290.dtb \ + lan966x-pcb8291.dtb \ + lan966x-pcb8309.dtb diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/microchip/aks-cdu.dts similarity index 100% rename from arch/arm/boot/dts/aks-cdu.dts rename to arch/arm/boot/dts/microchip/aks-cdu.dts diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/microchip/animeo_ip.dts similarity index 100% rename from arch/arm/boot/dts/animeo_ip.dts rename to arch/arm/boot/dts/microchip/animeo_ip.dts diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/microchip/at91-ariag25.dts similarity index 100% rename from arch/arm/boot/dts/at91-ariag25.dts rename to arch/arm/boot/dts/microchip/at91-ariag25.dts diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/microchip/at91-ariettag25.dts similarity index 100% rename from arch/arm/boot/dts/at91-ariettag25.dts rename to arch/arm/boot/dts/microchip/at91-ariettag25.dts diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/microchip/at91-cosino.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-cosino.dtsi rename to arch/arm/boot/dts/microchip/at91-cosino.dtsi diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts similarity index 100% rename from arch/arm/boot/dts/at91-cosino_mega2560.dts rename to arch/arm/boot/dts/microchip/at91-cosino_mega2560.dts diff --git a/arch/arm/boot/dts/at91-dvk_som60.dts b/arch/arm/boot/dts/microchip/at91-dvk_som60.dts similarity index 100% rename from arch/arm/boot/dts/at91-dvk_som60.dts rename to arch/arm/boot/dts/microchip/at91-dvk_som60.dts diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-dvk_su60_somc.dtsi rename to arch/arm/boot/dts/microchip/at91-dvk_su60_somc.dtsi diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi rename to arch/arm/boot/dts/microchip/at91-dvk_su60_somc_lcm.dtsi diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/microchip/at91-foxg20.dts similarity index 100% rename from arch/arm/boot/dts/at91-foxg20.dts rename to arch/arm/boot/dts/microchip/at91-foxg20.dts diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/microchip/at91-gatwick.dts similarity index 100% rename from arch/arm/boot/dts/at91-gatwick.dts rename to arch/arm/boot/dts/microchip/at91-gatwick.dts diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/microchip/at91-kizbox.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizbox.dts rename to arch/arm/boot/dts/microchip/at91-kizbox.dts diff --git a/arch/arm/boot/dts/at91-kizbox2-2.dts b/arch/arm/boot/dts/microchip/at91-kizbox2-2.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizbox2-2.dts rename to arch/arm/boot/dts/microchip/at91-kizbox2-2.dts diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-kizbox2-common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizbox2-common.dtsi diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizbox3-hs.dts rename to arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-kizbox3_common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi diff --git a/arch/arm/boot/dts/at91-kizboxmini-base.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-base.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-base.dts diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-common.dtsi rename to arch/arm/boot/dts/microchip/at91-kizboxmini-common.dtsi diff --git a/arch/arm/boot/dts/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-mb.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-mb.dts diff --git a/arch/arm/boot/dts/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts similarity index 100% rename from arch/arm/boot/dts/at91-kizboxmini-rd.dts rename to arch/arm/boot/dts/microchip/at91-kizboxmini-rd.dts diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/microchip/at91-linea.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-linea.dtsi rename to arch/arm/boot/dts/microchip/at91-linea.dtsi diff --git a/arch/arm/boot/dts/at91-lmu5000.dts b/arch/arm/boot/dts/microchip/at91-lmu5000.dts similarity index 100% rename from arch/arm/boot/dts/at91-lmu5000.dts rename to arch/arm/boot/dts/microchip/at91-lmu5000.dts diff --git a/arch/arm/boot/dts/at91-natte.dtsi b/arch/arm/boot/dts/microchip/at91-natte.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-natte.dtsi rename to arch/arm/boot/dts/microchip/at91-natte.dtsi diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts similarity index 100% rename from arch/arm/boot/dts/at91-nattis-2-natte-2.dts rename to arch/arm/boot/dts/microchip/at91-nattis-2-natte-2.dts diff --git a/arch/arm/boot/dts/at91-q5xr5.dts b/arch/arm/boot/dts/microchip/at91-q5xr5.dts similarity index 100% rename from arch/arm/boot/dts/at91-q5xr5.dts rename to arch/arm/boot/dts/microchip/at91-q5xr5.dts diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts similarity index 100% rename from arch/arm/boot/dts/at91-qil_a9260.dts rename to arch/arm/boot/dts/microchip/at91-qil_a9260.dts diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9_l9260.dts rename to arch/arm/boot/dts/microchip/at91-sam9_l9260.dts diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9x60_curiosity.dts rename to arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/microchip/at91-sam9x60ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sam9x60ek.dts rename to arch/arm/boot/dts/microchip/at91-sam9x60ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_som1.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d27_som1.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_som1_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d2_icp.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d2_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_eds.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_eds.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d3_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi rename to arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4.dtsi diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4_xplained.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama5d4ek.dts rename to arch/arm/boot/dts/microchip/at91-sama5d4ek.dts diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts similarity index 100% rename from arch/arm/boot/dts/at91-sama7g5ek.dts rename to arch/arm/boot/dts/microchip/at91-sama7g5ek.dts diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/microchip/at91-smartkiz.dts similarity index 100% rename from arch/arm/boot/dts/at91-smartkiz.dts rename to arch/arm/boot/dts/microchip/at91-smartkiz.dts diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/microchip/at91-som60.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-som60.dtsi rename to arch/arm/boot/dts/microchip/at91-som60.dtsi diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/microchip/at91-tse850-3.dts similarity index 100% rename from arch/arm/boot/dts/at91-tse850-3.dts rename to arch/arm/boot/dts/microchip/at91-tse850-3.dts diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts similarity index 100% rename from arch/arm/boot/dts/at91-vinco.dts rename to arch/arm/boot/dts/microchip/at91-vinco.dts diff --git a/arch/arm/boot/dts/at91-wb45n.dts b/arch/arm/boot/dts/microchip/at91-wb45n.dts similarity index 100% rename from arch/arm/boot/dts/at91-wb45n.dts rename to arch/arm/boot/dts/microchip/at91-wb45n.dts diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/microchip/at91-wb45n.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-wb45n.dtsi rename to arch/arm/boot/dts/microchip/at91-wb45n.dtsi diff --git a/arch/arm/boot/dts/at91-wb50n.dts b/arch/arm/boot/dts/microchip/at91-wb50n.dts similarity index 100% rename from arch/arm/boot/dts/at91-wb50n.dts rename to arch/arm/boot/dts/microchip/at91-wb50n.dts diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/microchip/at91-wb50n.dtsi similarity index 100% rename from arch/arm/boot/dts/at91-wb50n.dtsi rename to arch/arm/boot/dts/microchip/at91-wb50n.dtsi diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi similarity index 100% rename from arch/arm/boot/dts/at91rm9200.dtsi rename to arch/arm/boot/dts/microchip/at91rm9200.dtsi diff --git a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi similarity index 100% rename from arch/arm/boot/dts/at91rm9200_pqfp.dtsi rename to arch/arm/boot/dts/microchip/at91rm9200_pqfp.dtsi diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts similarity index 100% rename from arch/arm/boot/dts/at91rm9200ek.dts rename to arch/arm/boot/dts/microchip/at91rm9200ek.dts diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9260.dtsi rename to arch/arm/boot/dts/microchip/at91sam9260.dtsi diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/microchip/at91sam9260ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9260ek.dts rename to arch/arm/boot/dts/microchip/at91sam9260ek.dts diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9261.dtsi rename to arch/arm/boot/dts/microchip/at91sam9261.dtsi diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/microchip/at91sam9261ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9261ek.dts rename to arch/arm/boot/dts/microchip/at91sam9261ek.dts diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9263.dtsi rename to arch/arm/boot/dts/microchip/at91sam9263.dtsi diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9263ek.dts rename to arch/arm/boot/dts/microchip/at91sam9263ek.dts diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/microchip/at91sam9g15.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g15.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g15.dtsi diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/microchip/at91sam9g15ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g15ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g15ek.dts diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g20.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g20.dtsi diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g20ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g20ek.dts diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g20ek_2mmc.dts rename to arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g20ek_common.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts rename to arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/microchip/at91sam9g25.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g25.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g25.dtsi diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/microchip/at91sam9g25ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g25ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g25ek.dts diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/microchip/at91sam9g35.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g35.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g35.dtsi diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/microchip/at91sam9g35ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9g35ek.dts rename to arch/arm/boot/dts/microchip/at91sam9g35ek.dts diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9g45.dtsi rename to arch/arm/boot/dts/microchip/at91sam9g45.dtsi diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9m10g45ek.dts rename to arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9n12.dtsi rename to arch/arm/boot/dts/microchip/at91sam9n12.dtsi diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9n12ek.dts rename to arch/arm/boot/dts/microchip/at91sam9n12ek.dts diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9rl.dtsi rename to arch/arm/boot/dts/microchip/at91sam9rl.dtsi diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/microchip/at91sam9rlek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9rlek.dts rename to arch/arm/boot/dts/microchip/at91sam9rlek.dts diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/microchip/at91sam9x25.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x25.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x25.dtsi diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/microchip/at91sam9x25ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9x25ek.dts rename to arch/arm/boot/dts/microchip/at91sam9x25ek.dts diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/microchip/at91sam9x35.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x35.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x35.dtsi diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/microchip/at91sam9x35ek.dts similarity index 100% rename from arch/arm/boot/dts/at91sam9x35ek.dts rename to arch/arm/boot/dts/microchip/at91sam9x35ek.dts diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_can.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_can.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_isi.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_isi.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_lcd.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_lcd.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_macb0.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_macb0.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_macb1.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_macb1.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5_usart3.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5_usart3.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5cm.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5cm.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5dm.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5dm.dtsi diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9x5ek.dtsi rename to arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/microchip/at91sam9xe.dtsi similarity index 100% rename from arch/arm/boot/dts/at91sam9xe.dtsi rename to arch/arm/boot/dts/microchip/at91sam9xe.dtsi diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/microchip/ethernut5.dts similarity index 100% rename from arch/arm/boot/dts/ethernut5.dts rename to arch/arm/boot/dts/microchip/ethernut5.dts diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/microchip/evk-pro3.dts similarity index 100% rename from arch/arm/boot/dts/evk-pro3.dts rename to arch/arm/boot/dts/microchip/evk-pro3.dts diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/microchip/ge863-pro3.dtsi similarity index 100% rename from arch/arm/boot/dts/ge863-pro3.dtsi rename to arch/arm/boot/dts/microchip/ge863-pro3.dtsi diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt-8g.dts diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi similarity index 100% rename from arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi rename to arch/arm/boot/dts/microchip/lan966x-kontron-kswitch-d10-mmt.dtsi diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-pcb8290.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8290.dts diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-pcb8291.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8291.dts diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8309.dts similarity index 100% rename from arch/arm/boot/dts/lan966x-pcb8309.dts rename to arch/arm/boot/dts/microchip/lan966x-pcb8309.dts diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/microchip/lan966x.dtsi similarity index 100% rename from arch/arm/boot/dts/lan966x.dtsi rename to arch/arm/boot/dts/microchip/lan966x.dtsi diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/microchip/mpa1600.dts similarity index 100% rename from arch/arm/boot/dts/mpa1600.dts rename to arch/arm/boot/dts/microchip/mpa1600.dts diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/microchip/pm9g45.dts similarity index 100% rename from arch/arm/boot/dts/pm9g45.dts rename to arch/arm/boot/dts/microchip/pm9g45.dts diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi similarity index 100% rename from arch/arm/boot/dts/sam9x60.dtsi rename to arch/arm/boot/dts/microchip/sam9x60.dtsi diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/microchip/sama5d2-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/sama5d2-pinfunc.h rename to arch/arm/boot/dts/microchip/sama5d2-pinfunc.h diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d2.dtsi rename to arch/arm/boot/dts/microchip/sama5d2.dtsi diff --git a/arch/arm/boot/dts/sama5d29.dtsi b/arch/arm/boot/dts/microchip/sama5d29.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d29.dtsi rename to arch/arm/boot/dts/microchip/sama5d29.dtsi diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3.dtsi rename to arch/arm/boot/dts/microchip/sama5d3.dtsi diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/microchip/sama5d31.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d31.dtsi rename to arch/arm/boot/dts/microchip/sama5d31.dtsi diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/microchip/sama5d31ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d31ek.dts rename to arch/arm/boot/dts/microchip/sama5d31ek.dts diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/microchip/sama5d33.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d33.dtsi rename to arch/arm/boot/dts/microchip/sama5d33.dtsi diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/microchip/sama5d33ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d33ek.dts rename to arch/arm/boot/dts/microchip/sama5d33ek.dts diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/microchip/sama5d34.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d34.dtsi rename to arch/arm/boot/dts/microchip/sama5d34.dtsi diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/microchip/sama5d34ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d34ek.dts rename to arch/arm/boot/dts/microchip/sama5d34ek.dts diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/microchip/sama5d35.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d35.dtsi rename to arch/arm/boot/dts/microchip/sama5d35.dtsi diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/microchip/sama5d35ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d35ek.dts rename to arch/arm/boot/dts/microchip/sama5d35ek.dts diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/microchip/sama5d36.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d36.dtsi rename to arch/arm/boot/dts/microchip/sama5d36.dtsi diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/microchip/sama5d36ek.dts similarity index 100% rename from arch/arm/boot/dts/sama5d36ek.dts rename to arch/arm/boot/dts/microchip/sama5d36ek.dts diff --git a/arch/arm/boot/dts/sama5d36ek_cmp.dts b/arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts similarity index 100% rename from arch/arm/boot/dts/sama5d36ek_cmp.dts rename to arch/arm/boot/dts/microchip/sama5d36ek_cmp.dts diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/microchip/sama5d3_can.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_can.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_can.dtsi diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_emac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_emac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_emac.dtsi diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_gmac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_gmac.dtsi diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_lcd.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_lcd.dtsi diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_mci2.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_mci2.dtsi diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_tcb1.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_tcb1.dtsi diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/microchip/sama5d3_uart.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3_uart.dtsi rename to arch/arm/boot/dts/microchip/sama5d3_uart.dtsi diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xcm.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xcm.dtsi diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xcm_cmp.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xcm_cmp.dtsi diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/microchip/sama5d3xdm.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xdm.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xdm.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_cmp.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_cmp.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_emac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_emac.dtsi diff --git a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d3xmb_gmac.dtsi rename to arch/arm/boot/dts/microchip/sama5d3xmb_gmac.dtsi diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi similarity index 100% rename from arch/arm/boot/dts/sama5d4.dtsi rename to arch/arm/boot/dts/microchip/sama5d4.dtsi diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/microchip/sama7g5-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/sama7g5-pinfunc.h rename to arch/arm/boot/dts/microchip/sama7g5-pinfunc.h diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi similarity index 100% rename from arch/arm/boot/dts/sama7g5.dtsi rename to arch/arm/boot/dts/microchip/sama7g5.dtsi diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/microchip/tny_a9260.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9260.dts rename to arch/arm/boot/dts/microchip/tny_a9260.dts diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi similarity index 100% rename from arch/arm/boot/dts/tny_a9260_common.dtsi rename to arch/arm/boot/dts/microchip/tny_a9260_common.dtsi diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9263.dts rename to arch/arm/boot/dts/microchip/tny_a9263.dts diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/microchip/tny_a9g20.dts similarity index 100% rename from arch/arm/boot/dts/tny_a9g20.dts rename to arch/arm/boot/dts/microchip/tny_a9g20.dts diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9260.dts rename to arch/arm/boot/dts/microchip/usb_a9260.dts diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9260_common.dtsi rename to arch/arm/boot/dts/microchip/usb_a9260_common.dtsi diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9263.dts rename to arch/arm/boot/dts/microchip/usb_a9263.dts diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi rename to arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9g20.dts rename to arch/arm/boot/dts/microchip/usb_a9g20.dts diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi similarity index 100% rename from arch/arm/boot/dts/usb_a9g20_common.dtsi rename to arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts similarity index 100% rename from arch/arm/boot/dts/usb_a9g20_lpw.dts rename to arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts diff --git a/arch/arm/boot/dts/moxa/Makefile b/arch/arm/boot/dts/moxa/Makefile new file mode 100644 index 0000000000000..d61ce8d4e732e --- /dev/null +++ b/arch/arm/boot/dts/moxa/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MOXART) += \ + moxart-uc7112lx.dtb diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxa/moxart-uc7112lx.dts similarity index 100% rename from arch/arm/boot/dts/moxart-uc7112lx.dts rename to arch/arm/boot/dts/moxa/moxart-uc7112lx.dts diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxa/moxart.dtsi similarity index 100% rename from arch/arm/boot/dts/moxart.dtsi rename to arch/arm/boot/dts/moxa/moxart.dtsi diff --git a/arch/arm/boot/dts/nspire/Makefile b/arch/arm/boot/dts/nspire/Makefile new file mode 100644 index 0000000000000..82a2515bdd460 --- /dev/null +++ b/arch/arm/boot/dts/nspire/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NSPIRE) += \ + nspire-cx.dtb \ + nspire-tp.dtb \ + nspire-clp.dtb diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi similarity index 100% rename from arch/arm/boot/dts/nspire-classic.dtsi rename to arch/arm/boot/dts/nspire/nspire-classic.dtsi diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire/nspire-clp.dts similarity index 100% rename from arch/arm/boot/dts/nspire-clp.dts rename to arch/arm/boot/dts/nspire/nspire-clp.dts diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts similarity index 100% rename from arch/arm/boot/dts/nspire-cx.dts rename to arch/arm/boot/dts/nspire/nspire-cx.dts diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire/nspire-tp.dts similarity index 100% rename from arch/arm/boot/dts/nspire-tp.dts rename to arch/arm/boot/dts/nspire/nspire-tp.dts diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi similarity index 100% rename from arch/arm/boot/dts/nspire.dtsi rename to arch/arm/boot/dts/nspire/nspire.dtsi diff --git a/arch/arm/boot/dts/nuvoton/Makefile b/arch/arm/boot/dts/nuvoton/Makefile new file mode 100644 index 0000000000000..89c157dad3123 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NPCM7XX) += \ + nuvoton-npcm730-gsj.dtb \ + nuvoton-npcm730-gbs.dtb \ + nuvoton-npcm730-kudo.dtb \ + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm750-runbmc-olympus.dtb +dtb-$(CONFIG_ARCH_WPCM450) += \ + nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gbs.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj-gpio.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-gsj.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730-kudo.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm730.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm730.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-evb.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-evb.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-pincfg-evb.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-npcm750.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts similarity index 100% rename from arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts rename to arch/arm/boot/dts/nuvoton/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi similarity index 100% rename from arch/arm/boot/dts/nuvoton-wpcm450.dtsi rename to arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile new file mode 100644 index 0000000000000..60091bf7e48b0 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ + tegra114-asus-tf701t.dtb \ + tegra114-dalmore.dtb \ + tegra114-roth.dtb \ + tegra114-tn7.dtb +dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ + tegra124-apalis-eval.dtb \ + tegra124-apalis-v1.2-eval.dtb \ + tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ + tegra124-nyan-big-fhd.dtb \ + tegra124-nyan-blaze.dtb \ + tegra124-venice2.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ + tegra20-acer-a500-picasso.dtb \ + tegra20-asus-tf101.dtb \ + tegra20-harmony.dtb \ + tegra20-colibri-eval-v3.dtb \ + tegra20-colibri-iris.dtb \ + tegra20-medcom-wide.dtb \ + tegra20-paz00.dtb \ + tegra20-plutux.dtb \ + tegra20-seaboard.dtb \ + tegra20-tec.dtb \ + tegra20-trimslice.dtb \ + tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ + tegra30-apalis-eval.dtb \ + tegra30-apalis-v1.1-eval.dtb \ + tegra30-asus-nexus7-grouper-PM269.dtb \ + tegra30-asus-nexus7-grouper-E1565.dtb \ + tegra30-asus-nexus7-tilapia-E1565.dtb \ + tegra30-asus-tf201.dtb \ + tegra30-asus-tf300t.dtb \ + tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf700t.dtb \ + tegra30-beaver.dtb \ + tegra30-cardhu-a02.dtb \ + tegra30-cardhu-a04.dtb \ + tegra30-colibri-eval-v3.dtb \ + tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-asus-tf701t.dts rename to arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-dalmore.dts rename to arch/arm/boot/dts/nvidia/tegra114-dalmore.dts diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/nvidia/tegra114-roth.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-roth.dts rename to arch/arm/boot/dts/nvidia/tegra114-roth.dts diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts similarity index 100% rename from arch/arm/boot/dts/tegra114-tn7.dts rename to arch/arm/boot/dts/nvidia/tegra114-tn7.dts diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra114.dtsi rename to arch/arm/boot/dts/nvidia/tegra114.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-eval.dts rename to arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts rename to arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-apalis.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-jetson-tk1-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-jetson-tk1.dts rename to arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-nyan-big-fhd.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big-fhd.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-big.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-big.dts diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan-blaze-emc.dtsi diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts similarity index 100% rename from arch/arm/boot/dts/tegra124-nyan-blaze.dts rename to arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dts diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi similarity index 99% rename from arch/arm/boot/dts/tegra124-nyan.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index 56952333ae285..0c35ca2e91219 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -833,4 +833,4 @@ map0 { }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra124-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts similarity index 99% rename from arch/arm/boot/dts/tegra124-venice2.dts rename to arch/arm/boot/dts/nvidia/tegra124-venice2.dts index 7e739879c00c1..c697301c443c2 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -1253,4 +1253,4 @@ sound { }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra124.dtsi rename to arch/arm/boot/dts/nvidia/tegra124.dtsi diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-acer-a500-picasso.dts rename to arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-asus-tf101.dts rename to arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri-eval-v3.dts rename to arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri-iris.dts rename to arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-colibri.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-cpu-opp-microvolt.dtsi diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-cpu-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-harmony.dts rename to arch/arm/boot/dts/nvidia/tegra20-harmony.dts diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-medcom-wide.dts rename to arch/arm/boot/dts/nvidia/tegra20-medcom-wide.dts diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-paz00.dts rename to arch/arm/boot/dts/nvidia/tegra20-paz00.dts diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/nvidia/tegra20-plutux.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-plutux.dts rename to arch/arm/boot/dts/nvidia/tegra20-plutux.dts diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-seaboard.dts rename to arch/arm/boot/dts/nvidia/tegra20-seaboard.dts diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20-tamonten.dtsi rename to arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/nvidia/tegra20-tec.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-tec.dts rename to arch/arm/boot/dts/nvidia/tegra20-tec.dts diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-trimslice.dts rename to arch/arm/boot/dts/nvidia/tegra20-trimslice.dts diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts similarity index 100% rename from arch/arm/boot/dts/tegra20-ventana.dts rename to arch/arm/boot/dts/nvidia/tegra20-ventana.dts diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra20.dtsi rename to arch/arm/boot/dts/nvidia/tegra20.dtsi diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-eval.dts rename to arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts rename to arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-apalis.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-E1565.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-PM269.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-memory-timings.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-ti-pmic.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-E1565.dts diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia-memory-timings.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-tilapia.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf201.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf201.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf300t.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf300t.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf300tg.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf300tg.dts diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-tf700t.dts rename to arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-beaver.dts rename to arch/arm/boot/dts/nvidia/tegra30-beaver.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu-a02.dts rename to arch/arm/boot/dts/nvidia/tegra30-cardhu-a02.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu-a04.dts rename to arch/arm/boot/dts/nvidia/tegra30-cardhu-a04.dts diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cardhu.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-colibri-eval-v3.dts rename to arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-colibri.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cpu-opp-microvolt.dtsi diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-cpu-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-cpu-opp.dtsi diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-ouya.dts rename to arch/arm/boot/dts/nvidia/tegra30-ouya.dts diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts similarity index 100% rename from arch/arm/boot/dts/tegra30-pegatron-chagall.dts rename to arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30-peripherals-opp.dtsi rename to arch/arm/boot/dts/nvidia/tegra30-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi similarity index 100% rename from arch/arm/boot/dts/tegra30.dtsi rename to arch/arm/boot/dts/nvidia/tegra30.dtsi diff --git a/arch/arm/boot/dts/nxp/Makefile b/arch/arm/boot/dts/nxp/Makefile new file mode 100644 index 0000000000000..db44e7a0a1983 --- /dev/null +++ b/arch/arm/boot/dts/nxp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += imx +subdir-y += lpc +subdir-y += ls +subdir-y += mxs +subdir-y += vf diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile new file mode 100644 index 0000000000000..3629e343d3225 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -0,0 +1,388 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_IMX1) += \ + imx1-ads.dtb \ + imx1-apf9328.dtb +dtb-$(CONFIG_SOC_IMX25) += \ + imx25-eukrea-mbimxsd25-baseboard.dtb \ + imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ + imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \ + imx25-karo-tx25.dtb \ + imx25-pdk.dtb +dtb-$(CONFIG_SOC_IMX27) += \ + imx27-apf27.dtb \ + imx27-apf27dev.dtb \ + imx27-eukrea-mbimxsd27-baseboard.dtb \ + imx27-pdk.dtb \ + imx27-phytec-phycore-rdk.dtb \ + imx27-phytec-phycard-s-rdk.dtb +dtb-$(CONFIG_SOC_IMX31) += \ + imx31-bug.dtb \ + imx31-lite.dtb +dtb-$(CONFIG_SOC_IMX35) += \ + imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-pdk.dtb +dtb-$(CONFIG_SOC_IMX50) += \ + imx50-evk.dtb \ + imx50-kobo-aura.dtb +dtb-$(CONFIG_SOC_IMX51) += \ + imx51-apf51.dtb \ + imx51-apf51dev.dtb \ + imx51-babbage.dtb \ + imx51-digi-connectcore-jsk.dtb \ + imx51-eukrea-mbimxsd51-baseboard.dtb \ + imx51-ts4800.dtb \ + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb +dtb-$(CONFIG_SOC_IMX53) += \ + imx53-ard.dtb \ + imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ + imx53-m53evk.dtb \ + imx53-m53menlo.dtb \ + imx53-mba53.dtb \ + imx53-ppd.dtb \ + imx53-qsb.dtb \ + imx53-qsrb.dtb \ + imx53-sk-imx53.dtb \ + imx53-smd.dtb \ + imx53-tx53-x03x.dtb \ + imx53-tx53-x13x.dtb \ + imx53-usbarmory.dtb \ + imx53-voipac-bsb.dtb +dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ + imx6dl-apf6dev.dtb \ + imx6dl-aristainetos_4.dtb \ + imx6dl-aristainetos_7.dtb \ + imx6dl-aristainetos2_4.dtb \ + imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ + imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ + imx6dl-cubox-i.dtb \ + imx6dl-cubox-i-emmc-som-v15.dtb \ + imx6dl-cubox-i-som-v15.dtb \ + imx6dl-dfi-fs700-m60.dtb \ + imx6dl-dhcom-picoitx.dtb \ + imx6dl-eckelmann-ci4x10.dtb \ + imx6dl-emcon-avari.dtb \ + imx6dl-gw51xx.dtb \ + imx6dl-gw52xx.dtb \ + imx6dl-gw53xx.dtb \ + imx6dl-gw54xx.dtb \ + imx6dl-gw551x.dtb \ + imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ + imx6dl-gw560x.dtb \ + imx6dl-gw5903.dtb \ + imx6dl-gw5904.dtb \ + imx6dl-gw5907.dtb \ + imx6dl-gw5910.dtb \ + imx6dl-gw5912.dtb \ + imx6dl-gw5913.dtb \ + imx6dl-hummingboard.dtb \ + imx6dl-hummingboard-emmc-som-v15.dtb \ + imx6dl-hummingboard-som-v15.dtb \ + imx6dl-hummingboard2.dtb \ + imx6dl-hummingboard2-emmc-som-v15.dtb \ + imx6dl-hummingboard2-som-v15.dtb \ + imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ + imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ + imx6dl-mamoj.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ + imx6dl-nit6xlite.dtb \ + imx6dl-nitrogen6x.dtb \ + imx6dl-phytec-mira-rdk-nand.dtb \ + imx6dl-phytec-pbab01.dtb \ + imx6dl-pico-dwarf.dtb \ + imx6dl-pico-hobbit.dtb \ + imx6dl-pico-nymph.dtb \ + imx6dl-pico-pi.dtb \ + imx6dl-plybas.dtb \ + imx6dl-plym2m.dtb \ + imx6dl-prtmvt.dtb \ + imx6dl-prtrvt.dtb \ + imx6dl-prtvt7.dtb \ + imx6dl-rex-basic.dtb \ + imx6dl-riotboard.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabrelite.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-savageboard.dtb \ + imx6dl-skov-revc-lt2.dtb \ + imx6dl-skov-revc-lt6.dtb \ + imx6dl-solidsense.dtb \ + imx6dl-ts4900.dtb \ + imx6dl-ts7970.dtb \ + imx6dl-tx6dl-comtft.dtb \ + imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8034-mb7.dtb \ + imx6dl-tx6s-8035.dtb \ + imx6dl-tx6s-8035-mb7.dtb \ + imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-80xx-mb7.dtb \ + imx6dl-tx6u-8033.dtb \ + imx6dl-tx6u-8033-mb7.dtb \ + imx6dl-tx6u-811x.dtb \ + imx6dl-tx6u-81xx-mb7.dtb \ + imx6dl-udoo.dtb \ + imx6dl-victgo.dtb \ + imx6dl-vicut1.dtb \ + imx6dl-wandboard.dtb \ + imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ + imx6dl-yapp4-draco.dtb \ + imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-lynx.dtb \ + imx6dl-yapp4-orion.dtb \ + imx6dl-yapp4-phoenix.dtb \ + imx6dl-yapp4-ursa.dtb \ + imx6q-apalis-eval.dtb \ + imx6q-apalis-ixora.dtb \ + imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ + imx6q-apf6dev.dtb \ + imx6q-arm2.dtb \ + imx6q-b450v3.dtb \ + imx6q-b650v3.dtb \ + imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ + imx6q-cm-fx6.dtb \ + imx6q-cubox-i.dtb \ + imx6q-cubox-i-emmc-som-v15.dtb \ + imx6q-cubox-i-som-v15.dtb \ + imx6q-dfi-fs700-m60.dtb \ + imx6q-dhcom-pdk2.dtb \ + imx6q-display5-tianma-tm070-1280x768.dtb \ + imx6q-dmo-edmqmx6.dtb \ + imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ + imx6q-emcon-avari.dtb \ + imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ + imx6q-gk802.dtb \ + imx6q-gw51xx.dtb \ + imx6q-gw52xx.dtb \ + imx6q-gw53xx.dtb \ + imx6q-gw5400-a.dtb \ + imx6q-gw54xx.dtb \ + imx6q-gw551x.dtb \ + imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ + imx6q-gw560x.dtb \ + imx6q-gw5903.dtb \ + imx6q-gw5904.dtb \ + imx6q-gw5907.dtb \ + imx6q-gw5910.dtb \ + imx6q-gw5912.dtb \ + imx6q-gw5913.dtb \ + imx6q-h100.dtb \ + imx6q-hummingboard.dtb \ + imx6q-hummingboard-emmc-som-v15.dtb \ + imx6q-hummingboard-som-v15.dtb \ + imx6q-hummingboard2.dtb \ + imx6q-hummingboard2-emmc-som-v15.dtb \ + imx6q-hummingboard2-som-v15.dtb \ + imx6q-icore.dtb \ + imx6q-icore-mipi.dtb \ + imx6q-icore-ofcap10.dtb \ + imx6q-icore-ofcap12.dtb \ + imx6q-icore-rqs.dtb \ + imx6q-kp-tpc.dtb \ + imx6q-logicpd.dtb \ + imx6q-marsboard.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ + imx6q-mccmon6.dtb \ + imx6q-nitrogen6x.dtb \ + imx6q-nitrogen6_max.dtb \ + imx6q-nitrogen6_som2.dtb \ + imx6q-novena.dtb \ + imx6q-phytec-mira-rdk-emmc.dtb \ + imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-phytec-pbab01.dtb \ + imx6q-pico-dwarf.dtb \ + imx6q-pico-hobbit.dtb \ + imx6q-pico-nymph.dtb \ + imx6q-pico-pi.dtb \ + imx6q-pistachio.dtb \ + imx6q-prti6q.dtb \ + imx6q-prtwd2.dtb \ + imx6q-rex-pro.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ + imx6q-sabresd.dtb \ + imx6q-savageboard.dtb \ + imx6q-sbc6x.dtb \ + imx6q-skov-revc-lt2.dtb \ + imx6q-skov-revc-lt6.dtb \ + imx6q-skov-reve-mi1010ait-1cp1.dtb \ + imx6q-solidsense.dtb \ + imx6q-tbs2910.dtb \ + imx6q-ts4900.dtb \ + imx6q-ts7970.dtb \ + imx6q-tx6q-1010.dtb \ + imx6q-tx6q-1010-comtft.dtb \ + imx6q-tx6q-1020.dtb \ + imx6q-tx6q-1020-comtft.dtb \ + imx6q-tx6q-1036.dtb \ + imx6q-tx6q-1036-mb7.dtb \ + imx6q-tx6q-10x0-mb7.dtb \ + imx6q-tx6q-1110.dtb \ + imx6q-tx6q-11x0-mb7.dtb \ + imx6q-udoo.dtb \ + imx6q-utilite-pro.dtb \ + imx6q-var-dt6customboard.dtb \ + imx6q-vicut1.dtb \ + imx6q-wandboard.dtb \ + imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ + imx6q-yapp4-crux.dtb \ + imx6q-yapp4-pegasus.dtb \ + imx6q-zii-rdu2.dtb \ + imx6qp-mba6b.dtb \ + imx6qp-nitrogen6_max.dtb \ + imx6qp-nitrogen6_som2.dtb \ + imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ + imx6qp-sabreauto.dtb \ + imx6qp-sabresd.dtb \ + imx6qp-tx6qp-8037.dtb \ + imx6qp-tx6qp-8037-mb7.dtb \ + imx6qp-tx6qp-8137.dtb \ + imx6qp-tx6qp-8137-mb7.dtb \ + imx6qp-vicutp.dtb \ + imx6qp-wandboard-revd1.dtb \ + imx6qp-yapp4-crux-plus.dtb \ + imx6qp-yapp4-pegasus-plus.dtb \ + imx6qp-zii-rdu2.dtb \ + imx6s-dhcom-drc02.dtb +dtb-$(CONFIG_SOC_IMX6SL) += \ + imx6sl-evk.dtb \ + imx6sl-kobo-aura2.dtb \ + imx6sl-tolino-shine2hd.dtb \ + imx6sl-tolino-shine3.dtb \ + imx6sl-tolino-vision.dtb \ + imx6sl-tolino-vision5.dtb \ + imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb \ + imx6sll-kobo-clarahd.dtb \ + imx6sll-kobo-librah2o.dtb +dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-nitrogen6sx.dtb \ + imx6sx-sabreauto.dtb \ + imx6sx-sdb-reva.dtb \ + imx6sx-sdb-sai.dtb \ + imx6sx-sdb.dtb \ + imx6sx-sdb-mqs.dtb \ + imx6sx-softing-vining-2000.dtb \ + imx6sx-udoo-neo-basic.dtb \ + imx6sx-udoo-neo-extended.dtb \ + imx6sx-udoo-neo-full.dtb +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ + imx6ul-ccimx6ulsbcpro.dtb \ + imx6ul-geam.dtb \ + imx6ul-isiot-emmc.dtb \ + imx6ul-isiot-nand.dtb \ + imx6ul-kontron-bl.dtb \ + imx6ul-kontron-bl-43.dtb \ + imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ + imx6ul-opos6uldev.dtb \ + imx6ul-pico-dwarf.dtb \ + imx6ul-pico-hobbit.dtb \ + imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ + imx6ul-phytec-segin-ff-rdk-nand.dtb \ + imx6ul-prti6g.dtb \ + imx6ul-tx6ul-0010.dtb \ + imx6ul-tx6ul-0011.dtb \ + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ + imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ + imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ + imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-dhcom-drc02.dtb \ + imx6ull-dhcom-pdk2.dtb \ + imx6ull-dhcom-picoitx.dtb \ + imx6ull-dhcor-maveo-box.dtb \ + imx6ull-jozacp.dtb \ + imx6ull-kontron-bl.dtb \ + imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-opos6uldev.dtb \ + imx6ull-phytec-segin-ff-rdk-nand.dtb \ + imx6ull-phytec-segin-ff-rdk-emmc.dtb \ + imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tarragon-master.dtb \ + imx6ull-tarragon-micro.dtb \ + imx6ull-tarragon-slave.dtb \ + imx6ull-tarragon-slavext.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ulz-14x14-evk.dtb \ + imx6ulz-bsh-smm-m2.dtb +dtb-$(CONFIG_SOC_IMX7D) += \ + imx7d-cl-som-imx7.dtb \ + imx7d-colibri-aster.dtb \ + imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ + imx7d-colibri-eval-v3.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ + imx7d-mba7.dtb \ + imx7d-meerkat96.dtb \ + imx7d-nitrogen7.dtb \ + imx7d-pico-dwarf.dtb \ + imx7d-pico-hobbit.dtb \ + imx7d-pico-nymph.dtb \ + imx7d-pico-pi.dtb \ + imx7d-remarkable2.dtb \ + imx7d-sbc-imx7.dtb \ + imx7d-sdb.dtb \ + imx7d-sdb-reva.dtb \ + imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ + imx7d-zii-rmu2.dtb \ + imx7d-zii-rpu2.dtb \ + imx7s-colibri-aster.dtb \ + imx7s-colibri-eval-v3.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ + imx7s-mba7.dtb \ + imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-com.dtb \ + imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi similarity index 100% rename from arch/arm/boot/dts/e60k02.dtsi rename to arch/arm/boot/dts/nxp/imx/e60k02.dtsi diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi similarity index 100% rename from arch/arm/boot/dts/e70k02.dtsi rename to arch/arm/boot/dts/nxp/imx/e70k02.dtsi diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts similarity index 100% rename from arch/arm/boot/dts/imx1-ads.dts rename to arch/arm/boot/dts/nxp/imx/imx1-ads.dts diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts similarity index 100% rename from arch/arm/boot/dts/imx1-apf9328.dts rename to arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx1-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx1-pinfunc.h diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx1.dtsi diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts similarity index 100% rename from arch/arm/boot/dts/imx25-karo-tx25.dts rename to arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx25-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx25-pdk.dts diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx25-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx25-pinfunc.h diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi similarity index 100% rename from arch/arm/boot/dts/imx25.dtsi rename to arch/arm/boot/dts/nxp/imx/imx25.dtsi diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts similarity index 100% rename from arch/arm/boot/dts/imx27-apf27.dts rename to arch/arm/boot/dts/nxp/imx/imx27-apf27.dts diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts similarity index 100% rename from arch/arm/boot/dts/imx27-apf27dev.dts rename to arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-pdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx27-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx27-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx27-pinfunc.h diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi similarity index 100% rename from arch/arm/boot/dts/imx27.dtsi rename to arch/arm/boot/dts/nxp/imx/imx27.dtsi diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/nxp/imx/imx31-bug.dts similarity index 100% rename from arch/arm/boot/dts/imx31-bug.dts rename to arch/arm/boot/dts/nxp/imx/imx31-bug.dts diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts similarity index 100% rename from arch/arm/boot/dts/imx31-lite.dts rename to arch/arm/boot/dts/nxp/imx/imx31-lite.dts diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi similarity index 100% rename from arch/arm/boot/dts/imx31.dtsi rename to arch/arm/boot/dts/nxp/imx/imx31.dtsi diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi similarity index 100% rename from arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi rename to arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx35-pdk.dts similarity index 100% rename from arch/arm/boot/dts/imx35-pdk.dts rename to arch/arm/boot/dts/nxp/imx/imx35-pdk.dts diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx35-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx35-pinfunc.h diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi similarity index 100% rename from arch/arm/boot/dts/imx35.dtsi rename to arch/arm/boot/dts/nxp/imx/imx35.dtsi diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx50-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx50-evk.dts diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts similarity index 100% rename from arch/arm/boot/dts/imx50-kobo-aura.dts rename to arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx50-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx50-pinfunc.h diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi similarity index 100% rename from arch/arm/boot/dts/imx50.dtsi rename to arch/arm/boot/dts/nxp/imx/imx50.dtsi diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51.dts similarity index 100% rename from arch/arm/boot/dts/imx51-apf51.dts rename to arch/arm/boot/dts/nxp/imx/imx51-apf51.dts diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts similarity index 100% rename from arch/arm/boot/dts/imx51-apf51dev.dts rename to arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts similarity index 100% rename from arch/arm/boot/dts/imx51-babbage.dts rename to arch/arm/boot/dts/nxp/imx/imx51-babbage.dts diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts similarity index 100% rename from arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts rename to arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-jsk.dts diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts similarity index 100% rename from arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts rename to arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx51-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx51-pinfunc.h diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts similarity index 100% rename from arch/arm/boot/dts/imx51-ts4800.dts rename to arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts similarity index 100% rename from arch/arm/boot/dts/imx51-zii-rdu1.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts similarity index 100% rename from arch/arm/boot/dts/imx51-zii-scu2-mezz.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts similarity index 100% rename from arch/arm/boot/dts/imx51-zii-scu3-esb.dts rename to arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi similarity index 100% rename from arch/arm/boot/dts/imx51.dtsi rename to arch/arm/boot/dts/nxp/imx/imx51.dtsi diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts similarity index 100% rename from arch/arm/boot/dts/imx53-ard.dts rename to arch/arm/boot/dts/nxp/imx/imx53-ard.dts diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts similarity index 100% rename from arch/arm/boot/dts/imx53-cx9020.dts rename to arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts similarity index 100% rename from arch/arm/boot/dts/imx53-kp-ddc.dts rename to arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts similarity index 100% rename from arch/arm/boot/dts/imx53-kp-hsc.dts rename to arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dts diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-kp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-m53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts similarity index 100% rename from arch/arm/boot/dts/imx53-m53evk.dts rename to arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts similarity index 100% rename from arch/arm/boot/dts/imx53-m53menlo.dts rename to arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts similarity index 100% rename from arch/arm/boot/dts/imx53-mba53.dts rename to arch/arm/boot/dts/nxp/imx/imx53-mba53.dts diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx53-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx53-pinfunc.h diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts similarity index 100% rename from arch/arm/boot/dts/imx53-ppd.dts rename to arch/arm/boot/dts/nxp/imx/imx53-ppd.dts diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-qsb-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-qsb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-qsb.dts diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-qsrb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-qsrb.dts diff --git a/arch/arm/boot/dts/imx53-sk-imx53.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts similarity index 100% rename from arch/arm/boot/dts/imx53-sk-imx53.dts rename to arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts similarity index 100% rename from arch/arm/boot/dts/imx53-smd.dts rename to arch/arm/boot/dts/nxp/imx/imx53-smd.dts diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-tqma53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts similarity index 100% rename from arch/arm/boot/dts/imx53-tx53-x03x.dts rename to arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts similarity index 100% rename from arch/arm/boot/dts/imx53-tx53-x13x.dts rename to arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-tx53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-tx53.dtsi diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts similarity index 100% rename from arch/arm/boot/dts/imx53-usbarmory.dts rename to arch/arm/boot/dts/nxp/imx/imx53-usbarmory.dts diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts similarity index 100% rename from arch/arm/boot/dts/imx53-voipac-bsb.dts rename to arch/arm/boot/dts/nxp/imx/imx53-voipac-bsb.dts diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi similarity index 100% rename from arch/arm/boot/dts/imx53.dtsi rename to arch/arm/boot/dts/nxp/imx/imx53.dtsi diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6-logicpd-baseboard.dtsi diff --git a/arch/arm/boot/dts/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6-logicpd-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-alti6p.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-apf6dev.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos2_4.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos2_7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos_4.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-aristainetos_7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b105pv2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b105v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b125pv2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b125v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-b155v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-b1x5v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-cubox-i.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dts diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-dfi-fs700-m60.dts diff --git a/arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-dhcom-picoitx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-emcon-avari.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw51xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw52xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw53xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw54xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts diff --git a/arch/arm/boot/dts/imx6dl-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw551x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw551x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw552x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw552x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw553x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw553x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw560x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5903.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5904.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5907.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5907.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5910.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5910.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5912.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5912.dts diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-gw5913.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-gw5913.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2-som-v15.dts diff --git a/arch/arm/boot/dts/imx6dl-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-hummingboard2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard2.dts diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore-mipi.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dts diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore-rqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore-rqs.dts diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-icore.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-icore.dts diff --git a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-lanmcu.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mamoj.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts diff --git a/arch/arm/boot/dts/imx6dl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6.dtsi diff --git a/arch/arm/boot/dts/imx6dl-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6a.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6a.dts diff --git a/arch/arm/boot/dts/imx6dl-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-mba6b.dts diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-nit6xlite.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dts diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-nitrogen6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-pbab01.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pbab01.dts diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6dl-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6dl-pinfunc.h diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-plybas.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-plym2m.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-prtmvt.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-prtrvt.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtrvt.dts diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-prtvt7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-prtvt7.dts diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-qmx6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-rex-basic.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-rex-basic.dts diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-riotboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabrelite.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dts diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dts diff --git a/arch/arm/boot/dts/imx6dl-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-savageboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dts diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dts diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-skov-revc-lt6.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dts diff --git a/arch/arm/boot/dts/imx6dl-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-solidsense.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-solidsense.dts diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-ts4900.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-ts4900.dts diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-ts7970.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8034-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8034.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8034.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8035-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6s-8035.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6s-8035.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-801x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-801x.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-8033-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-8033.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-8033.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-80xx-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-80xx-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-811x.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-811x.dts diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-tx6u-81xx-mb7.dts diff --git a/arch/arm/boot/dts/imx6dl-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-udoo.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-udoo.dts diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-victgo.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-vicut1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-vicut1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard-revb1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revb1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-wandboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-wandboard.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi diff --git a/arch/arm/boot/dts/imx6dl-yapp4-draco.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-draco.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-draco.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-hydra.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-hydra.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-lynx.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-lynx.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-orion.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-orion.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-phoenix.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp4-ursa.dts rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-ursa.dts diff --git a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl-yapp43-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl-yapp43-common.dtsi diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6dl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6dl.dtsi diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-eval.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.1.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora-v1.2.dts diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apalis-ixora.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apalis-ixora.dts diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-apf6dev.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dts diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-arm2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b450v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b650v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-b850v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-ba16.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-bosch-acc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-bx50v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cm-fx6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts diff --git a/arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-cubox-i.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dts diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dfi-fs700-m60.dts diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dhcom-pdk2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-display5-tianma-tm070-1280x768.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-display5.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-dms-ba16.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ds.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ds.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ds.dts diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-emcon-avari.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-evi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-evi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-evi.dts diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gk802.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw51xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw52xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw53xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5400-a.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw54xx.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts diff --git a/arch/arm/boot/dts/imx6q-gw551x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw551x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw551x.dts diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw552x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw552x.dts diff --git a/arch/arm/boot/dts/imx6q-gw553x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw553x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw553x.dts diff --git a/arch/arm/boot/dts/imx6q-gw560x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw560x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dts diff --git a/arch/arm/boot/dts/imx6q-gw5903.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5903.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dts diff --git a/arch/arm/boot/dts/imx6q-gw5904.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5904.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dts diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5907.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5907.dts diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5910.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5910.dts diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5912.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5912.dts diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-gw5913.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-gw5913.dts diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-h100.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-h100.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2-emmc-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-emmc-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2-som-v15.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2-som-v15.dts diff --git a/arch/arm/boot/dts/imx6q-hummingboard2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-hummingboard2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-hummingboard2.dts diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-mipi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dts diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-ofcap10.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dts diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-ofcap12.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dts diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore-rqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore-rqs.dts diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/nxp/imx/imx6q-icore.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-icore.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-icore.dts diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6q-kp-tpc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-kp-tpc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dts diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-kp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-logicpd.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-logicpd.dts diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-marsboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-marsboard.dts diff --git a/arch/arm/boot/dts/imx6q-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6.dtsi diff --git a/arch/arm/boot/dts/imx6q-mba6a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6a.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6a.dts diff --git a/arch/arm/boot/dts/imx6q-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mba6b.dts diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-mccmon6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6_max.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6_som2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dts diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-nitrogen6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dts diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-novena.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-novena.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-pbab01.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-pbab01.dts diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6q-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6q-pinfunc.h diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-pistachio.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-prti6q.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-prtwd2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-rex-pro.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-rex-pro.dts diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabrelite.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dts diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dts diff --git a/arch/arm/boot/dts/imx6q-savageboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-savageboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dts diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-sbc6x.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-sbc6x.dts diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-revc-lt2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dts diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-revc-lt6.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dts diff --git a/arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-skov-reve-mi1010ait-1cp1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dts diff --git a/arch/arm/boot/dts/imx6q-solidsense.dts b/arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-solidsense.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-solidsense.dts diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tbs2910.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ts4900.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ts4900.dts diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-ts7970.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-ts7970.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010-comtft.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1010.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1010.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020-comtft.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1020.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1020.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1036-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1036.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1036.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-10x0-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-10x0-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-1110.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-1110.dts diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-tx6q-11x0-mb7.dts diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-udoo.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-udoo.dts diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-utilite-pro.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-var-dt6customboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-vicut1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-vicut1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard-revb1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revb1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-wandboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-wandboard.dts diff --git a/arch/arm/boot/dts/imx6q-yapp4-crux.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-yapp4-crux.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-yapp4-crux.dts diff --git a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-yapp4-pegasus.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-yapp4-pegasus.dts diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts similarity index 100% rename from arch/arm/boot/dts/imx6q-zii-rdu2.dts rename to arch/arm/boot/dts/nxp/imx/imx6q-zii-rdu2.dts diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6q.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6q.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apalis.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apf6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apf6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-apf6dev.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-aristainetos.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-cubox-i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-drc02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-picoitx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ds.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ds.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-emcon.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw51xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw52xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw53xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw54xx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw551x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw552x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw553x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw560x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5903.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5904.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5907.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5910.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5912.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-gw5913.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-hummingboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-hummingboard2-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2-emmc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore-1.5.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore-rqs.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-icore.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-mba6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-mba6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-mba6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-dwarf.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-hobbit.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-nymph.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico-pi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico-pi.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-prti6q.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-prti6q.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-rex.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sabreauto.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sabrelite.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sabresd.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-savageboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-cpu-revc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu-revc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-skov-revc-lt2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-solidsense.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-solidsense.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-solidsense.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-brcm.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-brcm.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-emmc.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-sr-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6a.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ts4900.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ts4900.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-ts7970.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-lcd.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-lvds.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-mb7.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-tx6.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-udoo.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-var-dart.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-var-dart.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1-12inch.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-vicut1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revb1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revc1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard-revd1.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-wandboard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl-zii-rdu2.dtsi diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qdl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi diff --git a/arch/arm/boot/dts/imx6qp-mba6b.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-mba6b.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-mba6b.dts diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-nitrogen6_max.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dts diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dts diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-prtwd3.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-sabresd.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dts diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qp-tqma6b.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qp-tqma6b.dtsi diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8037-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037-mb7.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8037.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8037.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8037.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8137-mb7.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137-mb7.dts diff --git a/arch/arm/boot/dts/imx6qp-tx6qp-8137.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-tx6qp-8137.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-tx6qp-8137.dts diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-vicutp.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-vicutp.dts diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-wandboard-revd1.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-wandboard-revd1.dts diff --git a/arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-yapp4-crux-plus.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-crux-plus.dts diff --git a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-yapp4-pegasus-plus.dts diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts similarity index 100% rename from arch/arm/boot/dts/imx6qp-zii-rdu2.dts rename to arch/arm/boot/dts/nxp/imx/imx6qp-zii-rdu2.dts diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6qp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6qp.dtsi diff --git a/arch/arm/boot/dts/imx6s-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/imx6s-dhcom-drc02.dts rename to arch/arm/boot/dts/nxp/imx/imx6s-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts diff --git a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-kobo-aura2.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-kobo-aura2.dts diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sl-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sl-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-shine3.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-vision.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision.dts diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-tolino-vision5.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-tolino-vision5.dts diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts similarity index 100% rename from arch/arm/boot/dts/imx6sl-warp.dts rename to arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sl.dtsi diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6sll-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts similarity index 100% rename from arch/arm/boot/dts/imx6sll-kobo-clarahd.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts similarity index 100% rename from arch/arm/boot/dts/imx6sll-kobo-librah2o.dts rename to arch/arm/boot/dts/nxp/imx/imx6sll-kobo-librah2o.dts diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sll-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sll-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sll.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sll.dtsi diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-nitrogen6sx.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6sx-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6sx-pinfunc.h diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sabreauto.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sabreauto.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb-mqs.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb-reva.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb-sai.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dts diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sx-sdb.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-softing-vining-2000.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-basic.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-extended.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo-full.dts rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo-full.dts diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sx-udoo-neo.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx-udoo-neo.dtsi diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6sx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6sx.dtsi diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-14x14-evk.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-geam.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dts diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dts diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-isiot.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-43.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl-43.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-bl.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dts diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-sl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-kontron-sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-kontron-sl.dtsi diff --git a/arch/arm/boot/dts/imx6ul-liteboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-liteboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-liteboard.dts diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-litesom.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-litesom.dtsi diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-opos6uldev.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-phytec-segin.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin.dtsi diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6ul-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6ul-pinfunc.h diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-prti6g.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-prti6g.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-0010.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-0011.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0011.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul-tx6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-aster.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-nonwifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris-v2.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-iris.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-nonwifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi.dtsi diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-drc02.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcom-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi diff --git a/arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcor-maveo-box.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-maveo-box.dts diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-dhcor-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi diff --git a/arch/arm/boot/dts/imx6ull-jozacp.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-jozacp.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-jozacp.dts diff --git a/arch/arm/boot/dts/imx6ull-kontron-bl.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-kontron-bl.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dts diff --git a/arch/arm/boot/dts/imx6ull-kontron-sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-kontron-sl.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-kontron-sl.dtsi diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx-eval.dts diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi diff --git a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-opos6ul.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-opos6ul.dtsi diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-opos6uldev.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-phycore-som.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-ff-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-lc-rdk-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-eval-01.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin-peb-wlbt-05.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin-peb-wlbt-05.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-segin.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-segin.dtsi diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h similarity index 100% rename from arch/arm/boot/dts/imx6ull-pinfunc-snvs.h rename to arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc-snvs.h diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx6ull-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx6ull-pinfunc.h diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-common.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-master.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-micro.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-micro.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-slave.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tarragon-slavext.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ull.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ull.dtsi diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx6ulz-14x14-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dts diff --git a/arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts similarity index 100% rename from arch/arm/boot/dts/imx6ulz-bsh-smm-m2.dts rename to arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi similarity index 100% rename from arch/arm/boot/dts/imx6ulz.dtsi rename to arch/arm/boot/dts/nxp/imx/imx6ulz.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-aster.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-aster.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-iris-v2.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri-iris.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri-iris.dtsi diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-mba7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-cl-som-imx7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-cl-som-imx7.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-emmc.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc.dtsi diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator-mfg.dts diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-flex-concentrator.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-mba7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts diff --git a/arch/arm/boot/dts/imx7d-meerkat96.dts b/arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-meerkat96.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-meerkat96.dts diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-nitrogen7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-dwarf.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-hobbit.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-hobbit.dts diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-nymph.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-pico-pi.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-pico.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx7d-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx7d-pinfunc.h diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-remarkable2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts diff --git a/arch/arm/boot/dts/imx7d-sbc-imx7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sbc-imx7.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sbc-imx7.dts diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sdb-reva.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb-reva.dts diff --git a/arch/arm/boot/dts/imx7d-sdb-sht11.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sdb-sht11.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb-sht11.dts diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-sdb.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-smegw01.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-smegw01.dts diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-zii-rmu2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-zii-rmu2.dts diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts similarity index 100% rename from arch/arm/boot/dts/imx7d-zii-rpu2.dts rename to arch/arm/boot/dts/nxp/imx/imx7d-zii-rpu2.dts diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7d.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7d.dtsi diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-aster.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-aster.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-iris-v2.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris-v2.dts diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri-iris.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri-iris.dts diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7s-colibri.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s-colibri.dtsi diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-mba7.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-mba7.dts diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7s-tqma7.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts similarity index 100% rename from arch/arm/boot/dts/imx7s-warp.dts rename to arch/arm/boot/dts/nxp/imx/imx7s-warp.dts diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7s.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7s.dtsi diff --git a/arch/arm/boot/dts/imx7ulp-com.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts similarity index 100% rename from arch/arm/boot/dts/imx7ulp-com.dts rename to arch/arm/boot/dts/nxp/imx/imx7ulp-com.dts diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx7ulp-evk.dts rename to arch/arm/boot/dts/nxp/imx/imx7ulp-evk.dts diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx7ulp-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi similarity index 100% rename from arch/arm/boot/dts/imx7ulp.dtsi rename to arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts similarity index 100% rename from arch/arm/boot/dts/imxrt1050-evk.dts rename to arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts diff --git a/arch/arm/boot/dts/imxrt1050-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imxrt1050-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi similarity index 99% rename from arch/arm/boot/dts/imxrt1050.dtsi rename to arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi index 852861558b477..dd714d235d5f6 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi @@ -4,7 +4,7 @@ * Author(s): Giulio Benetti */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include #include #include diff --git a/arch/arm/boot/dts/imxrt1170-pinfunc.h b/arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imxrt1170-pinfunc.h rename to arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi similarity index 100% rename from arch/arm/boot/dts/mba6ulx.dtsi rename to arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile new file mode 100644 index 0000000000000..56b9a0ebb9179 --- /dev/null +++ b/arch/arm/boot/dts/nxp/lpc/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LPC18XX) += \ + lpc4337-ciaa.dtb \ + lpc4350-hitex-eval.dtb \ + lpc4357-ea4357-devkit.dtb \ + lpc4357-myd-lpc4357.dtb +dtb-$(CONFIG_ARCH_LPC32XX) += \ + lpc3250-ea3250.dtb \ + lpc3250-phy3250.dtb diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi similarity index 99% rename from arch/arm/boot/dts/lpc18xx.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 1bb686a7b3ec9..9cf09c183b85e 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -11,7 +11,7 @@ * */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include "dt-bindings/clock/lpc18xx-cgu.h" #include "dt-bindings/clock/lpc18xx-ccu.h" diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts similarity index 100% rename from arch/arm/boot/dts/lpc3250-ea3250.dts rename to arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts similarity index 100% rename from arch/arm/boot/dts/lpc3250-phy3250.dts rename to arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc32xx.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts similarity index 100% rename from arch/arm/boot/dts/lpc4337-ciaa.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts similarity index 100% rename from arch/arm/boot/dts/lpc4350-hitex-eval.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts diff --git a/arch/arm/boot/dts/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc4350.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts similarity index 100% rename from arch/arm/boot/dts/lpc4357-ea4357-devkit.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts diff --git a/arch/arm/boot/dts/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts similarity index 100% rename from arch/arm/boot/dts/lpc4357-myd-lpc4357.dts rename to arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts diff --git a/arch/arm/boot/dts/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi similarity index 100% rename from arch/arm/boot/dts/lpc4357.dtsi rename to arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi diff --git a/arch/arm/boot/dts/nxp/ls/Makefile b/arch/arm/boot/dts/nxp/ls/Makefile new file mode 100644 index 0000000000000..3cb1d516f6fb5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ + ls1021a-moxa-uc-8410a.dtb \ + ls1021a-qds.dtb \ + ls1021a-tsn.dtb \ + ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-iot.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-qds.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-tsn.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts similarity index 100% rename from arch/arm/boot/dts/ls1021a-twr.dts rename to arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi similarity index 100% rename from arch/arm/boot/dts/ls1021a.dtsi rename to arch/arm/boot/dts/nxp/ls/ls1021a.dtsi diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile new file mode 100644 index 0000000000000..a430d04f9c693 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MXS) += \ + imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-sansa.dtb \ + imx23-stmp378x_devb.dtb \ + imx23-xfi3.dtb \ + imx28-apf28.dtb \ + imx28-apf28dev.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-cfa10037.dtb \ + imx28-cfa10049.dtb \ + imx28-cfa10055.dtb \ + imx28-cfa10056.dtb \ + imx28-cfa10057.dtb \ + imx28-cfa10058.dtb \ + imx28-duckbill-2-485.dtb \ + imx28-duckbill-2.dtb \ + imx28-duckbill-2-enocean.dtb \ + imx28-duckbill-2-spi.dtb \ + imx28-duckbill.dtb \ + imx28-eukrea-mbmx283lc.dtb \ + imx28-eukrea-mbmx287lc.dtb \ + imx28-evk.dtb \ + imx28-m28cu3.dtb \ + imx28-m28evk.dtb \ + imx28-sps1.dtb \ + imx28-ts4600.dtb \ + imx28-tx28.dtb \ + imx28-xea.dtb diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx23-evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-evk.dts diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts similarity index 100% rename from arch/arm/boot/dts/imx23-olinuxino.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts diff --git a/arch/arm/boot/dts/imx23-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx23-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/imx23-pinfunc.h diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts similarity index 100% rename from arch/arm/boot/dts/imx23-sansa.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts similarity index 100% rename from arch/arm/boot/dts/imx23-stmp378x_devb.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts similarity index 100% rename from arch/arm/boot/dts/imx23-xfi3.dts rename to arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi similarity index 100% rename from arch/arm/boot/dts/imx23.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx23.dtsi diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apf28.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apf28.dts diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apf28dev.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts similarity index 100% rename from arch/arm/boot/dts/imx28-apx4devkit.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10036.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10037.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10049.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10055.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10056.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10057.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts similarity index 100% rename from arch/arm/boot/dts/imx28-cfa10058.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-485.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-enocean.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2-spi.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-spi.dts diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill-2.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts similarity index 100% rename from arch/arm/boot/dts/imx28-duckbill.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx287lc.dts diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts similarity index 100% rename from arch/arm/boot/dts/imx28-evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-evk.dts diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-lwe.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-lwe.dtsi diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28-m28.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts similarity index 100% rename from arch/arm/boot/dts/imx28-m28cu3.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts similarity index 100% rename from arch/arm/boot/dts/imx28-m28evk.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts diff --git a/arch/arm/boot/dts/imx28-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/imx28-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/imx28-pinfunc.h diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts similarity index 100% rename from arch/arm/boot/dts/imx28-sps1.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts similarity index 100% rename from arch/arm/boot/dts/imx28-ts4600.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-ts4600.dts diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts similarity index 100% rename from arch/arm/boot/dts/imx28-tx28.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts similarity index 100% rename from arch/arm/boot/dts/imx28-xea.dts rename to arch/arm/boot/dts/nxp/mxs/imx28-xea.dts diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi similarity index 100% rename from arch/arm/boot/dts/imx28.dtsi rename to arch/arm/boot/dts/nxp/mxs/imx28.dtsi diff --git a/arch/arm/boot/dts/mxs-pinfunc.h b/arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/mxs-pinfunc.h rename to arch/arm/boot/dts/nxp/mxs/mxs-pinfunc.h diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile new file mode 100644 index 0000000000000..0a4a7f9dd43e4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/vf/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_VF610) += \ + vf500-colibri-eval-v3.dtb \ + vf610-bk4.dtb \ + vf610-colibri-eval-v3.dtb \ + vf610m4-colibri.dtb \ + vf610-cosmic.dtb \ + vf610m4-cosmic.dtb \ + vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ + vf610-zii-dev-rev-b.dtb \ + vf610-zii-dev-rev-c.dtb \ + vf610-zii-scu4-aib.dtb \ + vf610-zii-spb4.dtb \ + vf610-zii-ssmb-dtu.dtb \ + vf610-zii-ssmb-spu3.dtb diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm/boot/dts/vf-colibri-eval-v3.dtsi rename to arch/arm/boot/dts/nxp/vf/vf-colibri-eval-v3.dtsi diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf-colibri.dtsi diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/vf500-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/vf/vf500-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf500-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf500-colibri.dtsi diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/nxp/vf/vf500.dtsi similarity index 100% rename from arch/arm/boot/dts/vf500.dtsi rename to arch/arm/boot/dts/nxp/vf/vf500.dtsi diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts similarity index 100% rename from arch/arm/boot/dts/vf610-bk4.dts rename to arch/arm/boot/dts/nxp/vf/vf610-bk4.dts diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts similarity index 100% rename from arch/arm/boot/dts/vf610-colibri-eval-v3.dts rename to arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dts diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610-colibri.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts similarity index 100% rename from arch/arm/boot/dts/vf610-cosmic.dts rename to arch/arm/boot/dts/nxp/vf/vf610-cosmic.dts diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h similarity index 100% rename from arch/arm/boot/dts/vf610-pinfunc.h rename to arch/arm/boot/dts/nxp/vf/vf610-pinfunc.h diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts similarity index 100% rename from arch/arm/boot/dts/vf610-twr.dts rename to arch/arm/boot/dts/nxp/vf/vf610-twr.dts diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-cfu1.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-dev-rev-b.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-dev-rev-c.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610-zii-dev.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-scu4-aib.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-spb4.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts similarity index 100% rename from arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts rename to arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/nxp/vf/vf610.dtsi similarity index 100% rename from arch/arm/boot/dts/vf610.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610.dtsi diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts similarity index 100% rename from arch/arm/boot/dts/vf610m4-colibri.dts rename to arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts diff --git a/arch/arm/boot/dts/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts similarity index 100% rename from arch/arm/boot/dts/vf610m4-cosmic.dts rename to arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi similarity index 98% rename from arch/arm/boot/dts/vf610m4.dtsi rename to arch/arm/boot/dts/nxp/vf/vf610m4.dtsi index 76bbfd5e32b69..2bb331a877210 100644 --- a/arch/arm/boot/dts/vf610m4.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi @@ -42,7 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../../armv7-m.dtsi" #include "vfxxx.dtsi" / { diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi similarity index 100% rename from arch/arm/boot/dts/vfxxx.dtsi rename to arch/arm/boot/dts/nxp/vf/vfxxx.dtsi diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile new file mode 100644 index 0000000000000..3dfb1c8cefb86 --- /dev/null +++ b/arch/arm/boot/dts/qcom/Makefile @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8016-sbc.dtb \ + qcom-apq8026-asus-sparrow.dtb \ + qcom-apq8026-huawei-sturgeon.dtb \ + qcom-apq8026-lg-lenok.dtb \ + qcom-apq8026-samsung-matisse-wifi.dtb \ + qcom-apq8060-dragonboard.dtb \ + qcom-apq8064-cm-qs600.dtb \ + qcom-apq8064-ifc6410.dtb \ + qcom-apq8064-sony-xperia-lagan-yuga.dtb \ + qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-ipq4018-ap120c-ac.dtb \ + qcom-ipq4018-ap120c-ac-bit.dtb \ + qcom-ipq4018-jalapeno.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c1.dtb \ + qcom-ipq4019-ap.dk04.1-c3.dtb \ + qcom-ipq4019-ap.dk07.1-c1.dtb \ + qcom-ipq4019-ap.dk07.1-c2.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8916-samsung-e5.dtb \ + qcom-msm8916-samsung-e7.dtb \ + qcom-msm8916-samsung-grandmax.dtb \ + qcom-msm8916-samsung-serranove.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8960-samsung-expressatt.dtb \ + qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-sony-xperia-rhine-amami.dtb \ + qcom-msm8974-sony-xperia-rhine-honami.dtb \ + qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-oneplus-bacon.dtb \ + qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ + qcom-mdm9615-wp8548-mangoh-green.dtb \ + qcom-sdx55-mtp.dtb \ + qcom-sdx55-t55.dtb \ + qcom-sdx55-telit-fn980-tlb.dtb \ + qcom-sdx65-mtp.dtb diff --git a/arch/arm/boot/dts/qcom-apq8016-sbc.dts b/arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8016-sbc.dts rename to arch/arm/boot/dts/qcom/qcom-apq8016-sbc.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts rename to arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8060-dragonboard.dts rename to arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-ifc6410.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-pins.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts rename to arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064-v2.0.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8064.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8064.dtsi diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8074-dragonboard.dts rename to arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8084-ifc6540.dts rename to arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-apq8084-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-apq8084.dtsi rename to arch/arm/boot/dts/qcom/qcom-apq8084.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac-bit.dts diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dts diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1-c1.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c1.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1-c3.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq4019.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8062.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-ap148.dts rename to arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-rb3011.dts rename to arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8064.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-ipq8065.dtsi rename to arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts rename to arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548-mangoh-green.dts diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi rename to arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-mdm9615.dtsi rename to arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts rename to arch/arm/boot/dts/qcom/qcom-msm8226-samsung-s3ve3g.dts diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8226.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8226.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8660-surf.dts rename to arch/arm/boot/dts/qcom/qcom-msm8660-surf.dts diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8660.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8660.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-e5.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e5.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-e7.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-e7.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-grandmax.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts b/arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-samsung-serranove.dts rename to arch/arm/boot/dts/qcom/qcom-msm8916-samsung-serranove.dts diff --git a/arch/arm/boot/dts/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8916-smp.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8960-cdp.dts rename to arch/arm/boot/dts/qcom/qcom-msm8960-cdp.dts diff --git a/arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8960-samsung-expressatt.dts rename to arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8960.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8960.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-amami.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-amami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine-honami.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine-honami.dts diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts rename to arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts diff --git a/arch/arm/boot/dts/qcom-msm8974pro.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-msm8974pro.dtsi rename to arch/arm/boot/dts/qcom/qcom-msm8974pro.dtsi diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pm8226.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8226.dtsi diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pm8841.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8841.dtsi diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pm8941.dtsi rename to arch/arm/boot/dts/qcom/qcom-pm8941.dtsi diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pma8084.dtsi rename to arch/arm/boot/dts/qcom/qcom-pma8084.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pmx55.dtsi rename to arch/arm/boot/dts/qcom/qcom-pmx55.dtsi diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-pmx65.dtsi rename to arch/arm/boot/dts/qcom/qcom-pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-t55.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts rename to arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-sdx55.dtsi rename to arch/arm/boot/dts/qcom/qcom-sdx55.dtsi diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts similarity index 100% rename from arch/arm/boot/dts/qcom-sdx65-mtp.dts rename to arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi similarity index 100% rename from arch/arm/boot/dts/qcom-sdx65.dtsi rename to arch/arm/boot/dts/qcom/qcom-sdx65.dtsi diff --git a/arch/arm/boot/dts/realtek/Makefile b/arch/arm/boot/dts/realtek/Makefile new file mode 100644 index 0000000000000..c83671b5560fb --- /dev/null +++ b/arch/arm/boot/dts/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-horseradish.dtb \ + rtd1195-mele-x1000.dtb diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/realtek/rtd1195-horseradish.dts similarity index 100% rename from arch/arm/boot/dts/rtd1195-horseradish.dts rename to arch/arm/boot/dts/realtek/rtd1195-horseradish.dts diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts similarity index 100% rename from arch/arm/boot/dts/rtd1195-mele-x1000.dts rename to arch/arm/boot/dts/realtek/rtd1195-mele-x1000.dts diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/realtek/rtd1195.dtsi similarity index 100% rename from arch/arm/boot/dts/rtd1195.dtsi rename to arch/arm/boot/dts/realtek/rtd1195.dtsi diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile new file mode 100644 index 0000000000000..833a02447ecf7 --- /dev/null +++ b/arch/arm/boot/dts/renesas/Makefile @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RENESAS) += \ + emev2-kzm9d.dtb \ + r7s72100-genmai.dtb \ + r7s72100-gr-peach.dtb \ + r7s72100-rskrza1.dtb \ + r7s9210-rza2mevb.dtb \ + r8a73a4-ape6evm.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ + r8a7742-iwg21d-q7-dbcm-ca.dtb \ + r8a7743-iwg20d-q7.dtb \ + r8a7743-iwg20d-q7-dbcm-ca.dtb \ + r8a7743-sk-rzg1m.dtb \ + r8a7744-iwg20d-q7.dtb \ + r8a7744-iwg20d-q7-dbcm-ca.dtb \ + r8a7745-iwg22d-sodimm.dtb \ + r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ + r8a7745-sk-rzg1e.dtb \ + r8a77470-iwg23s-sbc.dtb \ + r8a7778-bockw.dtb \ + r8a7779-marzen.dtb \ + r8a7790-lager.dtb \ + r8a7790-stout.dtb \ + r8a7791-koelsch.dtb \ + r8a7791-porter.dtb \ + r8a7792-blanche.dtb \ + r8a7792-wheat.dtb \ + r8a7793-gose.dtb \ + r8a7794-alt.dtb \ + r8a7794-silk.dtb \ + r9a06g032-rzn1d400-db.dtb \ + sh73a0-kzm9g.dtb diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/renesas/emev2-kzm9d.dts similarity index 100% rename from arch/arm/boot/dts/emev2-kzm9d.dts rename to arch/arm/boot/dts/renesas/emev2-kzm9d.dts diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/renesas/emev2.dtsi similarity index 100% rename from arch/arm/boot/dts/emev2.dtsi rename to arch/arm/boot/dts/renesas/emev2.dtsi diff --git a/arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi similarity index 100% rename from arch/arm/boot/dts/gr-peach-audiocamerashield.dtsi rename to arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi similarity index 100% rename from arch/arm/boot/dts/iwg20d-q7-common.dtsi rename to arch/arm/boot/dts/renesas/iwg20d-q7-common.dtsi diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi similarity index 100% rename from arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi rename to arch/arm/boot/dts/renesas/iwg20d-q7-dbcm-ca.dtsi diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-genmai.dts rename to arch/arm/boot/dts/renesas/r7s72100-genmai.dts diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-gr-peach.dts rename to arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts similarity index 100% rename from arch/arm/boot/dts/r7s72100-rskrza1.dts rename to arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi similarity index 100% rename from arch/arm/boot/dts/r7s72100.dtsi rename to arch/arm/boot/dts/renesas/r7s72100.dtsi diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts similarity index 100% rename from arch/arm/boot/dts/r7s9210-rza2mevb.dts rename to arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/renesas/r7s9210.dtsi similarity index 100% rename from arch/arm/boot/dts/r7s9210.dtsi rename to arch/arm/boot/dts/renesas/r7s9210.dtsi diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts similarity index 100% rename from arch/arm/boot/dts/r8a73a4-ape6evm.dts rename to arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a73a4.dtsi rename to arch/arm/boot/dts/renesas/r8a73a4.dtsi diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts similarity index 100% rename from arch/arm/boot/dts/r8a7740-armadillo800eva.dts rename to arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7740.dtsi rename to arch/arm/boot/dts/renesas/r8a7740.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7.dts diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742-iwg21m.dtsi rename to arch/arm/boot/dts/renesas/r8a7742-iwg21m.dtsi diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7742.dtsi rename to arch/arm/boot/dts/renesas/r8a7742.dtsi diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7743-iwg20d-q7.dts diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7743-iwg20m.dtsi rename to arch/arm/boot/dts/renesas/r8a7743-iwg20m.dtsi diff --git a/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts similarity index 100% rename from arch/arm/boot/dts/r8a7743-sk-rzg1m.dts rename to arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7743.dtsi rename to arch/arm/boot/dts/renesas/r8a7743.dtsi diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts rename to arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20d-q7.dts rename to arch/arm/boot/dts/renesas/r8a7744-iwg20d-q7.dts diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7744-iwg20m.dtsi rename to arch/arm/boot/dts/renesas/r8a7744-iwg20m.dtsi diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7744.dtsi rename to arch/arm/boot/dts/renesas/r8a7744.dtsi diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts rename to arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts rename to arch/arm/boot/dts/renesas/r8a7745-iwg22d-sodimm.dts diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7745-iwg22m.dtsi rename to arch/arm/boot/dts/renesas/r8a7745-iwg22m.dtsi diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts similarity index 100% rename from arch/arm/boot/dts/r8a7745-sk-rzg1e.dts rename to arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7745.dtsi rename to arch/arm/boot/dts/renesas/r8a7745.dtsi diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts similarity index 100% rename from arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts rename to arch/arm/boot/dts/renesas/r8a77470-iwg23s-sbc.dts diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a77470.dtsi rename to arch/arm/boot/dts/renesas/r8a77470.dtsi diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts similarity index 100% rename from arch/arm/boot/dts/r8a7778-bockw.dts rename to arch/arm/boot/dts/renesas/r8a7778-bockw.dts diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7778.dtsi rename to arch/arm/boot/dts/renesas/r8a7778.dtsi diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts similarity index 100% rename from arch/arm/boot/dts/r8a7779-marzen.dts rename to arch/arm/boot/dts/renesas/r8a7779-marzen.dts diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7779.dtsi rename to arch/arm/boot/dts/renesas/r8a7779.dtsi diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts similarity index 100% rename from arch/arm/boot/dts/r8a7790-lager.dts rename to arch/arm/boot/dts/renesas/r8a7790-lager.dts diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts similarity index 100% rename from arch/arm/boot/dts/r8a7790-stout.dts rename to arch/arm/boot/dts/renesas/r8a7790-stout.dts diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7790.dtsi rename to arch/arm/boot/dts/renesas/r8a7790.dtsi diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts similarity index 100% rename from arch/arm/boot/dts/r8a7791-koelsch.dts rename to arch/arm/boot/dts/renesas/r8a7791-koelsch.dts diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts similarity index 100% rename from arch/arm/boot/dts/r8a7791-porter.dts rename to arch/arm/boot/dts/renesas/r8a7791-porter.dts diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7791.dtsi rename to arch/arm/boot/dts/renesas/r8a7791.dtsi diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts similarity index 100% rename from arch/arm/boot/dts/r8a7792-blanche.dts rename to arch/arm/boot/dts/renesas/r8a7792-blanche.dts diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts similarity index 100% rename from arch/arm/boot/dts/r8a7792-wheat.dts rename to arch/arm/boot/dts/renesas/r8a7792-wheat.dts diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7792.dtsi rename to arch/arm/boot/dts/renesas/r8a7792.dtsi diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts similarity index 100% rename from arch/arm/boot/dts/r8a7793-gose.dts rename to arch/arm/boot/dts/renesas/r8a7793-gose.dts diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7793.dtsi rename to arch/arm/boot/dts/renesas/r8a7793.dtsi diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts similarity index 100% rename from arch/arm/boot/dts/r8a7794-alt.dts rename to arch/arm/boot/dts/renesas/r8a7794-alt.dts diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts similarity index 100% rename from arch/arm/boot/dts/r8a7794-silk.dts rename to arch/arm/boot/dts/renesas/r8a7794-silk.dts diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a7794.dtsi rename to arch/arm/boot/dts/renesas/r8a7794.dtsi diff --git a/arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi similarity index 100% rename from arch/arm/boot/dts/r8a77xx-aa121td01-panel.dtsi rename to arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts similarity index 100% rename from arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts rename to arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi similarity index 100% rename from arch/arm/boot/dts/r9a06g032.dtsi rename to arch/arm/boot/dts/renesas/r9a06g032.dtsi diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts similarity index 100% rename from arch/arm/boot/dts/sh73a0-kzm9g.dts rename to arch/arm/boot/dts/renesas/sh73a0-kzm9g.dts diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/renesas/sh73a0.dtsi similarity index 100% rename from arch/arm/boot/dts/sh73a0.dtsi rename to arch/arm/boot/dts/renesas/sh73a0.dtsi diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile new file mode 100644 index 0000000000000..0f46e18fe2754 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1108-elgin-r1.dtb \ + rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ + rk3036-evb.dtb \ + rk3036-kylin.dtb \ + rk3066a-bqcurie2.dtb \ + rk3066a-marsboard.dtb \ + rk3066a-mk808.dtb \ + rk3066a-rayeager.dtb \ + rk3128-evb.dtb \ + rk3188-bqedison2qc.dtb \ + rk3188-px3-evb.dtb \ + rk3188-radxarock.dtb \ + rk3228-evb.dtb \ + rk3229-evb.dtb \ + rk3229-xms6.dtb \ + rk3288-evb-act8846.dtb \ + rk3288-evb-rk808.dtb \ + rk3288-firefly-beta.dtb \ + rk3288-firefly.dtb \ + rk3288-firefly-reload.dtb \ + rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ + rk3288-popmetal.dtb \ + rk3288-r89.dtb \ + rk3288-rock2-square.dtb \ + rk3288-rock-pi-n8.dtb \ + rk3288-tinker.dtb \ + rk3288-tinker-s.dtb \ + rk3288-veyron-brain.dtb \ + rk3288-veyron-fievel.dtb \ + rk3288-veyron-jaq.dtb \ + rk3288-veyron-jerry.dtb \ + rk3288-veyron-mickey.dtb \ + rk3288-veyron-mighty.dtb \ + rk3288-veyron-minnie.dtb \ + rk3288-veyron-pinky.dtb \ + rk3288-veyron-speedy.dtb \ + rk3288-veyron-tiger.dtb \ + rk3288-vyasa.dtb diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3036-evb.dts rename to arch/arm/boot/dts/rockchip/rk3036-evb.dts diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts similarity index 100% rename from arch/arm/boot/dts/rk3036-kylin.dts rename to arch/arm/boot/dts/rockchip/rk3036-kylin.dts diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3036.dtsi rename to arch/arm/boot/dts/rockchip/rk3036.dtsi diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-bqcurie2.dts rename to arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts index 962b4d1291dba..f924d4d64c3d1 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts @@ -159,7 +159,7 @@ vcc28_cif: regulator@12 { }; /* must be included after &tps gets defined */ -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &mmc0 { /* sdmmc */ status = "okay"; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-marsboard.dts rename to arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index 8beecd6282824..f6e8d49a02efc 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -147,7 +147,7 @@ vcc28_cif: regulator@12 { }; /* must be included after &tps gets defined */ -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &emac { phy = <&phy0>; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts similarity index 100% rename from arch/arm/boot/dts/rk3066a-mk808.dts rename to arch/arm/boot/dts/rockchip/rk3066a-mk808.dts diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts similarity index 99% rename from arch/arm/boot/dts/rk3066a-rayeager.dts rename to arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts index 3eee42137b6da..29d8e5bf88f53 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts @@ -296,7 +296,7 @@ vcc28_cif: regulator@12 { }; }; -#include "tps65910.dtsi" +#include "../tps65910.dtsi" &i2c2 { status = "okay"; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3066a.dtsi rename to arch/arm/boot/dts/rockchip/rk3066a.dtsi diff --git a/arch/arm/boot/dts/rk3128-evb.dts b/arch/arm/boot/dts/rockchip/rk3128-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3128-evb.dts rename to arch/arm/boot/dts/rockchip/rk3128-evb.dts diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3128.dtsi rename to arch/arm/boot/dts/rockchip/rk3128.dtsi diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-bqedison2qc.dts rename to arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-px3-evb.dts rename to arch/arm/boot/dts/rockchip/rk3188-px3-evb.dts diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts similarity index 100% rename from arch/arm/boot/dts/rk3188-radxarock.dts rename to arch/arm/boot/dts/rockchip/rk3188-radxarock.dts diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3188.dtsi rename to arch/arm/boot/dts/rockchip/rk3188.dtsi diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rockchip/rk3228-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3228-evb.dts rename to arch/arm/boot/dts/rockchip/rk3228-evb.dts diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rockchip/rk3229-evb.dts similarity index 100% rename from arch/arm/boot/dts/rk3229-evb.dts rename to arch/arm/boot/dts/rockchip/rk3229-evb.dts diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rockchip/rk3229-xms6.dts similarity index 100% rename from arch/arm/boot/dts/rk3229-xms6.dts rename to arch/arm/boot/dts/rockchip/rk3229-xms6.dts diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rockchip/rk3229.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3229.dtsi rename to arch/arm/boot/dts/rockchip/rk3229.dtsi diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi similarity index 100% rename from arch/arm/boot/dts/rk322x.dtsi rename to arch/arm/boot/dts/rockchip/rk322x.dtsi diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-evb-act8846.dts rename to arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-evb-rk808.dts rename to arch/arm/boot/dts/rockchip/rk3288-evb-rk808.dts diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-evb.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-evb.dtsi diff --git a/arch/arm/boot/dts/rk3288-firefly-beta.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-beta.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly-beta.dts diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly-reload.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts diff --git a/arch/arm/boot/dts/rk3288-firefly.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly.dts rename to arch/arm/boot/dts/rockchip/rk3288-firefly.dts diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-firefly.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-miqi.dts rename to arch/arm/boot/dts/rockchip/rk3288-miqi.dts diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-phycore-rdk.dts rename to arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-phycore-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rockchip/rk3288-popmetal.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-popmetal.dts rename to arch/arm/boot/dts/rockchip/rk3288-popmetal.dts diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rockchip/rk3288-r89.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-r89.dts rename to arch/arm/boot/dts/rockchip/rk3288-r89.dts diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts similarity index 86% rename from arch/arm/boot/dts/rk3288-rock-pi-n8.dts rename to arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts index b195930217135..673466d264bef 100644 --- a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-rock-pi-n8.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288.dtsi" -#include +#include #include "rk3288-vmarc-som.dtsi" / { diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-rock2-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-rock2-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-rock2-square.dts rename to arch/arm/boot/dts/rockchip/rk3288-rock2-square.dts diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker-s.dts rename to arch/arm/boot/dts/rockchip/rk3288-tinker-s.dts diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rockchip/rk3288-tinker.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker.dts rename to arch/arm/boot/dts/rockchip/rk3288-tinker.dts diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-tinker.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-analog-audio.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-brain.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-broadcom-bluetooth.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 700bb548d6b27..092316be67f74 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -181,4 +181,4 @@ usbotg_pwren_h: usbotg-pwren-h { }; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-edp.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-fievel.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-jaq.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts index 4a148cf1defc4..0d4c50e055587 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Jaq"; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-jerry.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts index 2c916c50dda50..6894763979f03 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Jerry"; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-mickey.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-mighty.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-mighty.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-minnie.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-minnie.dts diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts similarity index 98% rename from arch/arm/boot/dts/rk3288-veyron-pinky.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts index e2a4e6232eb58..6337238891eb0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts @@ -7,7 +7,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Pinky"; diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron-sdmmc.dtsi diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts similarity index 99% rename from arch/arm/boot/dts/rk3288-veyron-speedy.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts index 4a3ea934d03e5..336cd2be52657 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-speedy.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3288-veyron-chromebook.dtsi" #include "rk3288-veyron-broadcom-bluetooth.dtsi" -#include "cros-ec-sbs.dtsi" +#include "../cros-ec-sbs.dtsi" / { model = "Google Speedy"; diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron-tiger.dts rename to arch/arm/boot/dts/rockchip/rk3288-veyron-tiger.dts diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-veyron.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288-vmarc-som.dtsi rename to arch/arm/boot/dts/rockchip/rk3288-vmarc-som.dtsi diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rockchip/rk3288-vyasa.dts similarity index 100% rename from arch/arm/boot/dts/rk3288-vyasa.dts rename to arch/arm/boot/dts/rockchip/rk3288-vyasa.dts diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3288.dtsi rename to arch/arm/boot/dts/rockchip/rk3288.dtsi diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi similarity index 100% rename from arch/arm/boot/dts/rk3xxx.dtsi rename to arch/arm/boot/dts/rockchip/rk3xxx.dtsi diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi similarity index 100% rename from arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi rename to arch/arm/boot/dts/rockchip/rockchip-radxa-dalang-carrier.dtsi diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts similarity index 100% rename from arch/arm/boot/dts/rv1108-elgin-r1.dts rename to arch/arm/boot/dts/rockchip/rv1108-elgin-r1.dts diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rockchip/rv1108-evb.dts similarity index 100% rename from arch/arm/boot/dts/rv1108-evb.dts rename to arch/arm/boot/dts/rockchip/rv1108-evb.dts diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1108.dtsi rename to arch/arm/boot/dts/rockchip/rv1108.dtsi diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts similarity index 100% rename from arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts rename to arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi rename to arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126-pinctrl.dtsi rename to arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi similarity index 100% rename from arch/arm/boot/dts/rv1126.dtsi rename to arch/arm/boot/dts/rockchip/rv1126.dtsi diff --git a/arch/arm/boot/dts/samsung/Makefile b/arch/arm/boot/dts/samsung/Makefile new file mode 100644 index 0000000000000..c8d067abdd597 --- /dev/null +++ b/arch/arm/boot/dts/samsung/Makefile @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_EXYNOS3) += \ + exynos3250-artik5-eval.dtb \ + exynos3250-monk.dtb \ + exynos3250-rinato.dtb +dtb-$(CONFIG_ARCH_EXYNOS4) += \ + exynos4210-i9100.dtb \ + exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ + exynos4210-trats.dtb \ + exynos4210-universal_c210.dtb \ + exynos4412-i9300.dtb \ + exynos4412-i9305.dtb \ + exynos4412-itop-elite.dtb \ + exynos4412-n710x.dtb \ + exynos4412-odroidu3.dtb \ + exynos4412-odroidx.dtb \ + exynos4412-odroidx2.dtb \ + exynos4412-origen.dtb \ + exynos4412-p4note-n8010.dtb \ + exynos4412-smdk4412.dtb \ + exynos4412-tiny4412.dtb \ + exynos4412-trats2.dtb +dtb-$(CONFIG_ARCH_EXYNOS5) += \ + exynos5250-arndale.dtb \ + exynos5250-smdk5250.dtb \ + exynos5250-snow.dtb \ + exynos5250-snow-rev5.dtb \ + exynos5250-spring.dtb \ + exynos5260-xyref5260.dtb \ + exynos5410-odroidxu.dtb \ + exynos5410-smdk5410.dtb \ + exynos5420-arndale-octa.dtb \ + exynos5420-peach-pit.dtb \ + exynos5420-smdk5420.dtb \ + exynos5420-chagall-wifi.dtb \ + exynos5420-klimt-wifi.dtb \ + exynos5422-odroidhc1.dtb \ + exynos5422-odroidxu3.dtb \ + exynos5422-odroidxu3-lite.dtb \ + exynos5422-odroidxu4.dtb \ + exynos5422-samsung-k3g.dtb \ + exynos5800-peach-pi.dtb +dtb-$(CONFIG_ARCH_S3C64XX) += \ + s3c6410-mini6410.dtb \ + s3c6410-smdk6410.dtb +dtb-$(CONFIG_ARCH_S5PV210) += \ + s5pv210-aquila.dtb \ + s5pv210-fascinate4g.dtb \ + s5pv210-galaxys.dtb \ + s5pv210-goni.dtb \ + s5pv210-smdkc110.dtb \ + s5pv210-smdkv210.dtb \ + s5pv210-torbreck.dtb diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi rename to arch/arm/boot/dts/samsung/exynos-mfc-reserved-memory.dtsi diff --git a/arch/arm/boot/dts/exynos-pinctrl.h b/arch/arm/boot/dts/samsung/exynos-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/exynos-pinctrl.h rename to arch/arm/boot/dts/samsung/exynos-pinctrl.h diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos-syscon-restart.dtsi rename to arch/arm/boot/dts/samsung/exynos-syscon-restart.dtsi diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-artik5-eval.dts rename to arch/arm/boot/dts/samsung/exynos3250-artik5-eval.dts diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos3250-artik5.dtsi rename to arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/samsung/exynos3250-monk.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-monk.dts rename to arch/arm/boot/dts/samsung/exynos3250-monk.dts diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos3250-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos3250-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts similarity index 100% rename from arch/arm/boot/dts/exynos3250-rinato.dts rename to arch/arm/boot/dts/samsung/exynos3250-rinato.dts diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/samsung/exynos3250.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos3250.dtsi rename to arch/arm/boot/dts/samsung/exynos3250.dtsi diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4-cpu-thermal.dtsi rename to arch/arm/boot/dts/samsung/exynos4-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4.dtsi rename to arch/arm/boot/dts/samsung/exynos4.dtsi diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-i9100.dts rename to arch/arm/boot/dts/samsung/exynos4210-i9100.dts diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/samsung/exynos4210-origen.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-origen.dts rename to arch/arm/boot/dts/samsung/exynos4210-origen.dts diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4210-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos4210-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-smdkv310.dts rename to arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/samsung/exynos4210-trats.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-trats.dts rename to arch/arm/boot/dts/samsung/exynos4210-trats.dts diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts similarity index 100% rename from arch/arm/boot/dts/exynos4210-universal_c210.dts rename to arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/samsung/exynos4210.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4210.dtsi rename to arch/arm/boot/dts/samsung/exynos4210.dtsi diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/samsung/exynos4212.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4212.dtsi rename to arch/arm/boot/dts/samsung/exynos4212.dtsi diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/samsung/exynos4412-i9300.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-i9300.dts rename to arch/arm/boot/dts/samsung/exynos4412-i9300.dts diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/samsung/exynos4412-i9305.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-i9305.dts rename to arch/arm/boot/dts/samsung/exynos4412-i9305.dts diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-itop-elite.dts rename to arch/arm/boot/dts/samsung/exynos4412-itop-elite.dts diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-midas.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-midas.dtsi diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-n710x.dts rename to arch/arm/boot/dts/samsung/exynos4412-n710x.dts diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroid-common.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidu3.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidx.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidx.dts diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-odroidx2.dts rename to arch/arm/boot/dts/samsung/exynos4412-odroidx2.dts diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/samsung/exynos4412-origen.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-origen.dts rename to arch/arm/boot/dts/samsung/exynos4412-origen.dts diff --git a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-p4note-n8010.dts rename to arch/arm/boot/dts/samsung/exynos4412-p4note-n8010.dts diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-p4note.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-ppmu-common.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-ppmu-common.dtsi diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/samsung/exynos4412-prime.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412-prime.dtsi rename to arch/arm/boot/dts/samsung/exynos4412-prime.dtsi diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-smdk4412.dts rename to arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-tiny4412.dts rename to arch/arm/boot/dts/samsung/exynos4412-tiny4412.dts diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/samsung/exynos4412-trats2.dts similarity index 100% rename from arch/arm/boot/dts/exynos4412-trats2.dts rename to arch/arm/boot/dts/samsung/exynos4412-trats2.dts diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4412.dtsi rename to arch/arm/boot/dts/samsung/exynos4412.dtsi diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4x12-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos4x12-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/samsung/exynos4x12.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos4x12.dtsi rename to arch/arm/boot/dts/samsung/exynos4x12.dtsi diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/samsung/exynos5.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5.dtsi rename to arch/arm/boot/dts/samsung/exynos5.dtsi diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/samsung/exynos5250-arndale.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-arndale.dts rename to arch/arm/boot/dts/samsung/exynos5250-arndale.dts diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5250-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5250-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-smdk5250.dts rename to arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos5250-snow-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi index 59b2cc35c37b7..c82e2762e07c4 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -715,4 +715,4 @@ &usbdrd_phy { vbus-supply = <&usb3_vbus_reg>; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-snow-rev5.dts rename to arch/arm/boot/dts/samsung/exynos5250-snow-rev5.dts diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/samsung/exynos5250-snow.dts similarity index 100% rename from arch/arm/boot/dts/exynos5250-snow.dts rename to arch/arm/boot/dts/samsung/exynos5250-snow.dts diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/samsung/exynos5250-spring.dts similarity index 99% rename from arch/arm/boot/dts/exynos5250-spring.dts rename to arch/arm/boot/dts/samsung/exynos5250-spring.dts index c12bb17631b7c..d126fccdcaf34 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-spring.dts @@ -564,4 +564,4 @@ &usbdrd { vdd33-supply = <&ldo12_reg>; }; -#include "cros-ec-keyboard.dtsi" +#include "../cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5250.dtsi rename to arch/arm/boot/dts/samsung/exynos5250.dtsi diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5260-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5260-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts similarity index 100% rename from arch/arm/boot/dts/exynos5260-xyref5260.dts rename to arch/arm/boot/dts/samsung/exynos5260-xyref5260.dts diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/samsung/exynos5260.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5260.dtsi rename to arch/arm/boot/dts/samsung/exynos5260.dtsi diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts similarity index 100% rename from arch/arm/boot/dts/exynos5410-odroidxu.dts rename to arch/arm/boot/dts/samsung/exynos5410-odroidxu.dts diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5410-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5410-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts similarity index 100% rename from arch/arm/boot/dts/exynos5410-smdk5410.dts rename to arch/arm/boot/dts/samsung/exynos5410-smdk5410.dts diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/samsung/exynos5410.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5410.dtsi rename to arch/arm/boot/dts/samsung/exynos5410.dtsi diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-arndale-octa.dts rename to arch/arm/boot/dts/samsung/exynos5420-arndale-octa.dts diff --git a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-chagall-wifi.dts rename to arch/arm/boot/dts/samsung/exynos5420-chagall-wifi.dts diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-cpus.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi diff --git a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-klimt-wifi.dts rename to arch/arm/boot/dts/samsung/exynos5420-klimt-wifi.dts diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts similarity index 99% rename from arch/arm/boot/dts/exynos5420-peach-pit.dts rename to arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts index 7a48f2b328193..4e757b6e28e1c 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -1122,5 +1122,5 @@ &watchdog { timeout-sec = <32>; }; -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-pinctrl.dtsi diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts similarity index 100% rename from arch/arm/boot/dts/exynos5420-smdk5420.dts rename to arch/arm/boot/dts/samsung/exynos5420-smdk5420.dts diff --git a/arch/arm/boot/dts/exynos5420-trip-points.dtsi b/arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420-trip-points.dtsi rename to arch/arm/boot/dts/samsung/exynos5420-trip-points.dtsi diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/samsung/exynos5420.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5420.dtsi rename to arch/arm/boot/dts/samsung/exynos5420.dtsi diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-cpus.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroid-core.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroid-core.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidhc1.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidhc1.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3-lite.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu3.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu3.dts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-odroidxu4.dts rename to arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts similarity index 100% rename from arch/arm/boot/dts/exynos5422-samsung-k3g.dts rename to arch/arm/boot/dts/samsung/exynos5422-samsung-k3g.dts diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi rename to arch/arm/boot/dts/samsung/exynos54xx-odroidxu-leds.dtsi diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/samsung/exynos54xx.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos54xx.dtsi rename to arch/arm/boot/dts/samsung/exynos54xx.dtsi diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts similarity index 99% rename from arch/arm/boot/dts/exynos5800-peach-pi.dts rename to arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts index 1f544f12da6c5..f91bc4ae008e4 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -1104,5 +1104,5 @@ &watchdog { timeout-sec = <32>; }; -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" +#include "../cros-ec-keyboard.dtsi" +#include "../cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/samsung/exynos5800.dtsi similarity index 100% rename from arch/arm/boot/dts/exynos5800.dtsi rename to arch/arm/boot/dts/samsung/exynos5800.dtsi diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/samsung/s3c6400.dtsi similarity index 100% rename from arch/arm/boot/dts/s3c6400.dtsi rename to arch/arm/boot/dts/samsung/s3c6400.dtsi diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts similarity index 100% rename from arch/arm/boot/dts/s3c6410-mini6410.dts rename to arch/arm/boot/dts/samsung/s3c6410-mini6410.dts diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts similarity index 100% rename from arch/arm/boot/dts/s3c6410-smdk6410.dts rename to arch/arm/boot/dts/samsung/s3c6410-smdk6410.dts diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/samsung/s3c6410.dtsi similarity index 100% rename from arch/arm/boot/dts/s3c6410.dtsi rename to arch/arm/boot/dts/samsung/s3c6410.dtsi diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/s3c64xx-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/s3c64xx-pinctrl.dtsi diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.h b/arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/s3c64xx-pinctrl.h rename to arch/arm/boot/dts/samsung/s3c64xx-pinctrl.h diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/samsung/s3c64xx.dtsi similarity index 100% rename from arch/arm/boot/dts/s3c64xx.dtsi rename to arch/arm/boot/dts/samsung/s3c64xx.dtsi diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/samsung/s5pv210-aquila.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-aquila.dts rename to arch/arm/boot/dts/samsung/s5pv210-aquila.dts diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi similarity index 100% rename from arch/arm/boot/dts/s5pv210-aries.dtsi rename to arch/arm/boot/dts/samsung/s5pv210-aries.dtsi diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-fascinate4g.dts rename to arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-galaxys.dts rename to arch/arm/boot/dts/samsung/s5pv210-galaxys.dts diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/samsung/s5pv210-goni.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-goni.dts rename to arch/arm/boot/dts/samsung/s5pv210-goni.dts diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/s5pv210-pinctrl.dtsi rename to arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.h b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.h similarity index 100% rename from arch/arm/boot/dts/s5pv210-pinctrl.h rename to arch/arm/boot/dts/samsung/s5pv210-pinctrl.h diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-smdkc110.dts rename to arch/arm/boot/dts/samsung/s5pv210-smdkc110.dts diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-smdkv210.dts rename to arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/samsung/s5pv210-torbreck.dts similarity index 100% rename from arch/arm/boot/dts/s5pv210-torbreck.dts rename to arch/arm/boot/dts/samsung/s5pv210-torbreck.dts diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi similarity index 100% rename from arch/arm/boot/dts/s5pv210.dtsi rename to arch/arm/boot/dts/samsung/s5pv210.dtsi diff --git a/arch/arm/boot/dts/sigmastar/Makefile b/arch/arm/boot/dts/sigmastar/Makefile new file mode 100644 index 0000000000000..b07eaf5d8add9 --- /dev/null +++ b/arch/arm/boot/dts/sigmastar/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MSTARV7) += \ + mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ + mstar-infinity2m-ssd202d-miyoo-mini.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ + mstar-infinity2m-ssd202d-unitv2.dtb \ + mstar-infinity3-msc313e-breadbee.dtb \ + mstar-mercury5-ssc8336n-midrived08.dtb diff --git a/arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-breadbee-common.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity-breadbee-common.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity-msc313-breadbee_crust.dts diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity-msc313.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity-msc313.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd201-som2d01.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-miyoo-mini.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-ssd201htv2.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-unitv2.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd202d.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m-ssd20xd.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity2m.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts rename to arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e-breadbee.dts diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity3-msc313e.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-infinity3.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-infinity3.dtsi diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts rename to arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n-midrived08.dts diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-mercury5-ssc8336n.dtsi diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-mercury5.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-mercury5.dtsi diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/sigmastar/mstar-v7.dtsi similarity index 100% rename from arch/arm/boot/dts/mstar-v7.dtsi rename to arch/arm/boot/dts/sigmastar/mstar-v7.dtsi diff --git a/arch/arm/boot/dts/socionext/Makefile b/arch/arm/boot/dts/socionext/Makefile new file mode 100644 index 0000000000000..dab4275f6bd6f --- /dev/null +++ b/arch/arm/boot/dts/socionext/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb +dtb-$(CONFIG_ARCH_UNIPHIER) += \ + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pro5-epcore.dtb \ + uniphier-pro5-proex.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld8-ref.dtb diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts similarity index 100% rename from arch/arm/boot/dts/milbeaut-m10v-evb.dts rename to arch/arm/boot/dts/socionext/milbeaut-m10v-evb.dts diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi similarity index 100% rename from arch/arm/boot/dts/milbeaut-m10v.dtsi rename to arch/arm/boot/dts/socionext/milbeaut-m10v.dtsi diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-ld4-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-ld4-ref.dts diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld4.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ld4.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ld4.dtsi diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-ld6b-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-ld6b-ref.dts diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ld6b.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ld6b.dtsi diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pinctrl.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pinctrl.dtsi diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-ace.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-ace.dts diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-ref.dts diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4-sanji.dts rename to arch/arm/boot/dts/socionext/uniphier-pro4-sanji.dts diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro4.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pro4.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pro4.dtsi diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5-epcore.dts rename to arch/arm/boot/dts/socionext/uniphier-pro5-epcore.dts diff --git a/arch/arm/boot/dts/uniphier-pro5-proex.dts b/arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5-proex.dts rename to arch/arm/boot/dts/socionext/uniphier-pro5-proex.dts diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/socionext/uniphier-pro5.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pro5.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pro5.dtsi diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2-gentil.dts rename to arch/arm/boot/dts/socionext/uniphier-pxs2-gentil.dts diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2-vodka.dts rename to arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-pxs2.dtsi rename to arch/arm/boot/dts/socionext/uniphier-pxs2.dtsi diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-ref-daughter.dtsi rename to arch/arm/boot/dts/socionext/uniphier-ref-daughter.dtsi diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts similarity index 100% rename from arch/arm/boot/dts/uniphier-sld8-ref.dts rename to arch/arm/boot/dts/socionext/uniphier-sld8-ref.dts diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/socionext/uniphier-sld8.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-sld8.dtsi rename to arch/arm/boot/dts/socionext/uniphier-sld8.dtsi diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/socionext/uniphier-support-card.dtsi similarity index 100% rename from arch/arm/boot/dts/uniphier-support-card.dtsi rename to arch/arm/boot/dts/socionext/uniphier-support-card.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile new file mode 100644 index 0000000000000..b3e9d29390e38 --- /dev/null +++ b/arch/arm/boot/dts/st/Makefile @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_NOMADIK) += \ + ste-nomadik-s8815.dtb \ + ste-nomadik-nhk15.dtb +dtb-$(CONFIG_ARCH_SPEAR13XX) += \ + spear1310-evb.dtb \ + spear1340-evb.dtb +dtb-$(CONFIG_ARCH_SPEAR3XX) += \ + spear300-evb.dtb \ + spear310-evb.dtb \ + spear320-evb.dtb \ + spear320-hmi.dtb +dtb-$(CONFIG_ARCH_SPEAR6XX) += \ + spear600-evb.dtb +dtb-$(CONFIG_ARCH_STI) += \ + stih407-b2120.dtb \ + stih410-b2120.dtb \ + stih410-b2260.dtb \ + stih418-b2199.dtb \ + stih418-b2264.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32f429-disco.dtb \ + stm32f469-disco.dtb \ + stm32f746-disco.dtb \ + stm32f769-disco.dtb \ + stm32429i-eval.dtb \ + stm32746g-eval.dtb \ + stm32h743i-eval.dtb \ + stm32h743i-disco.dtb \ + stm32h750i-art-pi.dtb \ + stm32mp135f-dk.dtb \ + stm32mp151a-prtt1a.dtb \ + stm32mp151a-prtt1c.dtb \ + stm32mp151a-prtt1s.dtb \ + stm32mp151a-dhcor-testbench.dtb \ + stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp157a-avenger96.dtb \ + stm32mp157a-dhcor-avenger96.dtb \ + stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ + stm32mp157a-iot-box.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ + stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2.dtb \ + stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \ + stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ + stm32mp157a-stinger96.dtb \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp157c-dhcom-picoitx.dtb \ + stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ + stm32mp157c-emsbc-argon.dtb \ + stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp157c-phycore-stm32mp1-3.dtb +dtb-$(CONFIG_ARCH_U8500) += \ + ste-snowball.dtb \ + ste-hrefprev60-stuib.dtb \ + ste-hrefprev60-tvk.dtb \ + ste-hrefv60plus-stuib.dtb \ + ste-hrefv60plus-tvk.dtb \ + ste-href520-tvk.dtb \ + ste-ux500-samsung-golden.dtb \ + ste-ux500-samsung-janice.dtb \ + ste-ux500-samsung-gavini.dtb \ + ste-ux500-samsung-codina.dtb \ + ste-ux500-samsung-codina-tmo.dtb \ + ste-ux500-samsung-skomer.dtb \ + ste-ux500-samsung-kyle.dtb diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear1310-evb.dts rename to arch/arm/boot/dts/st/spear1310-evb.dts diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/st/spear1310.dtsi similarity index 100% rename from arch/arm/boot/dts/spear1310.dtsi rename to arch/arm/boot/dts/st/spear1310.dtsi diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear1340-evb.dts rename to arch/arm/boot/dts/st/spear1340-evb.dts diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/st/spear1340.dtsi similarity index 100% rename from arch/arm/boot/dts/spear1340.dtsi rename to arch/arm/boot/dts/st/spear1340.dtsi diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi similarity index 100% rename from arch/arm/boot/dts/spear13xx.dtsi rename to arch/arm/boot/dts/st/spear13xx.dtsi diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/st/spear300-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear300-evb.dts rename to arch/arm/boot/dts/st/spear300-evb.dts diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/st/spear300.dtsi similarity index 100% rename from arch/arm/boot/dts/spear300.dtsi rename to arch/arm/boot/dts/st/spear300.dtsi diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/st/spear310-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear310-evb.dts rename to arch/arm/boot/dts/st/spear310-evb.dts diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/st/spear310.dtsi similarity index 100% rename from arch/arm/boot/dts/spear310.dtsi rename to arch/arm/boot/dts/st/spear310.dtsi diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/st/spear320-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear320-evb.dts rename to arch/arm/boot/dts/st/spear320-evb.dts diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/st/spear320-hmi.dts similarity index 100% rename from arch/arm/boot/dts/spear320-hmi.dts rename to arch/arm/boot/dts/st/spear320-hmi.dts diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/st/spear320.dtsi similarity index 100% rename from arch/arm/boot/dts/spear320.dtsi rename to arch/arm/boot/dts/st/spear320.dtsi diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/st/spear320s.dtsi similarity index 100% rename from arch/arm/boot/dts/spear320s.dtsi rename to arch/arm/boot/dts/st/spear320s.dtsi diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/st/spear3xx.dtsi similarity index 100% rename from arch/arm/boot/dts/spear3xx.dtsi rename to arch/arm/boot/dts/st/spear3xx.dtsi diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/st/spear600-evb.dts similarity index 100% rename from arch/arm/boot/dts/spear600-evb.dts rename to arch/arm/boot/dts/st/spear600-evb.dts diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/st/spear600.dtsi similarity index 100% rename from arch/arm/boot/dts/spear600.dtsi rename to arch/arm/boot/dts/st/spear600.dtsi diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st/st-pincfg.h similarity index 100% rename from arch/arm/boot/dts/st-pincfg.h rename to arch/arm/boot/dts/st/st-pincfg.h diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/st/ste-ab8500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-ab8500.dtsi rename to arch/arm/boot/dts/st/ste-ab8500.dtsi diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/st/ste-ab8505.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-ab8505.dtsi rename to arch/arm/boot/dts/st/ste-ab8505.dtsi diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/st/ste-db8500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db8500.dtsi rename to arch/arm/boot/dts/st/ste-db8500.dtsi diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/st/ste-db8520.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db8520.dtsi rename to arch/arm/boot/dts/st/ste-db8520.dtsi diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/st/ste-db9500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-db9500.dtsi rename to arch/arm/boot/dts/st/ste-db9500.dtsi diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-dbx5x0.dtsi rename to arch/arm/boot/dts/st/ste-dbx5x0.dtsi diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/st/ste-href-ab8500.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-ab8500.dtsi rename to arch/arm/boot/dts/st/ste-href-ab8500.dtsi diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-family-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-href-family-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/st/ste-href-stuib.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-stuib.dtsi rename to arch/arm/boot/dts/st/ste-href-stuib.dtsi diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi rename to arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi rename to arch/arm/boot/dts/st/ste-href-tvk1281618-r3.dtsi diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/st/ste-href.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-href.dtsi rename to arch/arm/boot/dts/st/ste-href.dtsi diff --git a/arch/arm/boot/dts/ste-href520-tvk.dts b/arch/arm/boot/dts/st/ste-href520-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-href520-tvk.dts rename to arch/arm/boot/dts/st/ste-href520-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefprev60-stuib.dts rename to arch/arm/boot/dts/st/ste-hrefprev60-stuib.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefprev60-tvk.dts rename to arch/arm/boot/dts/st/ste-hrefprev60-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/st/ste-hrefprev60.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-hrefprev60.dtsi rename to arch/arm/boot/dts/st/ste-hrefprev60.dtsi diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus-stuib.dts rename to arch/arm/boot/dts/st/ste-hrefv60plus-stuib.dts diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus-tvk.dts rename to arch/arm/boot/dts/st/ste-hrefv60plus-tvk.dts diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/st/ste-hrefv60plus.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-hrefv60plus.dtsi rename to arch/arm/boot/dts/st/ste-hrefv60plus.dtsi diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/st/ste-nomadik-nhk15.dts similarity index 100% rename from arch/arm/boot/dts/ste-nomadik-nhk15.dts rename to arch/arm/boot/dts/st/ste-nomadik-nhk15.dts diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi rename to arch/arm/boot/dts/st/ste-nomadik-pinctrl.dtsi diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts similarity index 100% rename from arch/arm/boot/dts/ste-nomadik-s8815.dts rename to arch/arm/boot/dts/st/ste-nomadik-s8815.dts diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi similarity index 100% rename from arch/arm/boot/dts/ste-nomadik-stn8815.dtsi rename to arch/arm/boot/dts/st/ste-nomadik-stn8815.dtsi diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/st/ste-snowball.dts similarity index 100% rename from arch/arm/boot/dts/ste-snowball.dts rename to arch/arm/boot/dts/st/ste-snowball.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-codina.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-gavini.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-golden.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-golden.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-janice.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-kyle.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts similarity index 100% rename from arch/arm/boot/dts/ste-ux500-samsung-skomer.dts rename to arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/st/stih407-b2120.dts similarity index 100% rename from arch/arm/boot/dts/stih407-b2120.dts rename to arch/arm/boot/dts/st/stih407-b2120.dts diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/st/stih407-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-clock.dtsi rename to arch/arm/boot/dts/st/stih407-clock.dtsi diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-family.dtsi rename to arch/arm/boot/dts/st/stih407-family.dtsi diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407-pinctrl.dtsi rename to arch/arm/boot/dts/st/stih407-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/st/stih407.dtsi similarity index 100% rename from arch/arm/boot/dts/stih407.dtsi rename to arch/arm/boot/dts/st/stih407.dtsi diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/st/stih410-b2120.dts similarity index 100% rename from arch/arm/boot/dts/stih410-b2120.dts rename to arch/arm/boot/dts/st/stih410-b2120.dts diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/st/stih410-b2260.dts similarity index 100% rename from arch/arm/boot/dts/stih410-b2260.dts rename to arch/arm/boot/dts/st/stih410-b2260.dts diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/st/stih410-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410-clock.dtsi rename to arch/arm/boot/dts/st/stih410-clock.dtsi diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/st/stih410-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410-pinctrl.dtsi rename to arch/arm/boot/dts/st/stih410-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi similarity index 100% rename from arch/arm/boot/dts/stih410.dtsi rename to arch/arm/boot/dts/st/stih410.dtsi diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/st/stih418-b2199.dts similarity index 100% rename from arch/arm/boot/dts/stih418-b2199.dts rename to arch/arm/boot/dts/st/stih418-b2199.dts diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/st/stih418-b2264.dts similarity index 100% rename from arch/arm/boot/dts/stih418-b2264.dts rename to arch/arm/boot/dts/st/stih418-b2264.dts diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/st/stih418-clock.dtsi similarity index 100% rename from arch/arm/boot/dts/stih418-clock.dtsi rename to arch/arm/boot/dts/st/stih418-clock.dtsi diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi similarity index 100% rename from arch/arm/boot/dts/stih418.dtsi rename to arch/arm/boot/dts/st/stih418.dtsi diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/st/stihxxx-b2120.dtsi similarity index 100% rename from arch/arm/boot/dts/stihxxx-b2120.dtsi rename to arch/arm/boot/dts/st/stihxxx-b2120.dtsi diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32429i-eval.dts rename to arch/arm/boot/dts/st/stm32429i-eval.dts diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32746g-eval.dts rename to arch/arm/boot/dts/st/stm32746g-eval.dts diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f4-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f429-disco.dts rename to arch/arm/boot/dts/st/stm32f429-disco.dts diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f429-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f429-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32f429.dtsi rename to arch/arm/boot/dts/st/stm32f429.dtsi index 00bf53f99c294..8efcda9ef8ae2 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -45,7 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f469-disco.dts rename to arch/arm/boot/dts/st/stm32f469-disco.dts diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f469-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f469-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f469.dtsi b/arch/arm/boot/dts/st/stm32f469.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f469.dtsi rename to arch/arm/boot/dts/st/stm32f469.dtsi diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f7-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f746-disco.dts rename to arch/arm/boot/dts/st/stm32f746-disco.dts diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f746-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32f746.dtsi rename to arch/arm/boot/dts/st/stm32f746.dtsi index e3564b74a7791..d1802efd067cc 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32f769-disco.dts rename to arch/arm/boot/dts/st/stm32f769-disco.dts diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32f769-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32h7-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi similarity index 99% rename from arch/arm/boot/dts/stm32h743.dtsi rename to arch/arm/boot/dts/st/stm32h743.dtsi index f30796f7adf36..b8d4c44c8a82a 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armv7-m.dtsi" +#include "../armv7-m.dtsi" #include #include #include diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts similarity index 100% rename from arch/arm/boot/dts/stm32h743i-disco.dts rename to arch/arm/boot/dts/st/stm32h743i-disco.dts diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts similarity index 100% rename from arch/arm/boot/dts/stm32h743i-eval.dts rename to arch/arm/boot/dts/st/stm32h743i-eval.dts diff --git a/arch/arm/boot/dts/stm32h750.dtsi b/arch/arm/boot/dts/st/stm32h750.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32h750.dtsi rename to arch/arm/boot/dts/st/stm32h750.dtsi diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts similarity index 100% rename from arch/arm/boot/dts/stm32h750i-art-pi.dts rename to arch/arm/boot/dts/st/stm32h750i-art-pi.dts diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp131.dtsi rename to arch/arm/boot/dts/st/stm32mp131.dtsi diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp133.dtsi rename to arch/arm/boot/dts/st/stm32mp133.dtsi diff --git a/arch/arm/boot/dts/stm32mp135.dtsi b/arch/arm/boot/dts/st/stm32mp135.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp135.dtsi rename to arch/arm/boot/dts/st/stm32mp135.dtsi diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp135f-dk.dts rename to arch/arm/boot/dts/st/stm32mp135f-dk.dts diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13xc.dtsi rename to arch/arm/boot/dts/st/stm32mp13xc.dtsi diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp13xf.dtsi rename to arch/arm/boot/dts/st/stm32mp13xf.dtsi diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15-scmi.dtsi rename to arch/arm/boot/dts/st/stm32mp15-scmi.dtsi diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp151.dtsi rename to arch/arm/boot/dts/st/stm32mp151.dtsi diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts rename to arch/arm/boot/dts/st/stm32mp151a-dhcor-testbench.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1a.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1c.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi rename to arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp151a-prtt1s.dts rename to arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp153.dtsi rename to arch/arm/boot/dts/st/stm32mp153.dtsi diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts rename to arch/arm/boot/dts/st/stm32mp153c-dhcom-drc02.dts diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts rename to arch/arm/boot/dts/st/stm32mp153c-dhcor-drc-compact.dts diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157.dtsi rename to arch/arm/boot/dts/st/stm32mp157.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-avenger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-avenger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-avenger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-dhcor-avenger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-dk1.dts rename to arch/arm/boot/dts/st/stm32mp157a-dk1.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-icore-stm32mp1.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-iot-box.dts rename to arch/arm/boot/dts/st/stm32mp157a-iot-box.dts diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-stinger96.dts rename to arch/arm/boot/dts/st/stm32mp157a-stinger96.dts diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157a-stinger96.dtsi rename to arch/arm/boot/dts/st/stm32mp157a-stinger96.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts rename to arch/arm/boot/dts/st/stm32mp157c-dhcom-pdk2.dts diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts rename to arch/arm/boot/dts/st/stm32mp157c-dhcom-picoitx.dts diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-dk2.dts rename to arch/arm/boot/dts/st/stm32mp157c-dk2.dts diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-ed1.dts rename to arch/arm/boot/dts/st/stm32mp157c-ed1.dts diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts rename to arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi rename to arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts rename to arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-ev1.dts rename to arch/arm/boot/dts/st/stm32mp157c-ev1.dts diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts rename to arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi rename to arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-odyssey.dts rename to arch/arm/boot/dts/st/stm32mp157c-odyssey.dts diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-phycore-stm32mp1-3.dts rename to arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts diff --git a/arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp157c-phycore-stm32mp15-som.dtsi rename to arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xc.dtsi rename to arch/arm/boot/dts/st/stm32mp15xc.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-io1v8.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-dkx.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xx-osd32.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxaa-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxac-pinctrl.dtsi diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi similarity index 100% rename from arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi rename to arch/arm/boot/dts/st/stm32mp15xxad-pinctrl.dtsi diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile new file mode 100644 index 0000000000000..868f2ea0c127a --- /dev/null +++ b/arch/arm/boot/dts/sunplus/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb +dtb-$(CONFIG_SOC_SP7021) += \ + sunplus-sp7021-demo-v3.dtb diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021-achip.dtsi rename to arch/arm/boot/dts/sunplus/sunplus-sp7021-achip.dtsi diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts rename to arch/arm/boot/dts/sunplus/sunplus-sp7021-demo-v3.dts diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi similarity index 100% rename from arch/arm/boot/dts/sunplus-sp7021.dtsi rename to arch/arm/boot/dts/sunplus/sunplus-sp7021.dtsi diff --git a/arch/arm/boot/dts/synaptics/Makefile b/arch/arm/boot/dts/synaptics/Makefile new file mode 100644 index 0000000000000..0ecccd156d185 --- /dev/null +++ b/arch/arm/boot/dts/synaptics/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BERLIN) += \ + berlin2-sony-nsz-gs7.dtb \ + berlin2cd-google-chromecast.dtb \ + berlin2cd-valve-steamlink.dtb \ + berlin2q-marvell-dmp.dtb diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts similarity index 100% rename from arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts rename to arch/arm/boot/dts/synaptics/berlin2-sony-nsz-gs7.dts diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/synaptics/berlin2.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2.dtsi rename to arch/arm/boot/dts/synaptics/berlin2.dtsi diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts similarity index 100% rename from arch/arm/boot/dts/berlin2cd-google-chromecast.dts rename to arch/arm/boot/dts/synaptics/berlin2cd-google-chromecast.dts diff --git a/arch/arm/boot/dts/berlin2cd-valve-steamlink.dts b/arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts similarity index 100% rename from arch/arm/boot/dts/berlin2cd-valve-steamlink.dts rename to arch/arm/boot/dts/synaptics/berlin2cd-valve-steamlink.dts diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/synaptics/berlin2cd.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2cd.dtsi rename to arch/arm/boot/dts/synaptics/berlin2cd.dtsi diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts similarity index 100% rename from arch/arm/boot/dts/berlin2q-marvell-dmp.dts rename to arch/arm/boot/dts/synaptics/berlin2q-marvell-dmp.dts diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/synaptics/berlin2q.dtsi similarity index 100% rename from arch/arm/boot/dts/berlin2q.dtsi rename to arch/arm/boot/dts/synaptics/berlin2q.dtsi diff --git a/arch/arm/boot/dts/ti/Makefile b/arch/arm/boot/dts/ti/Makefile new file mode 100644 index 0000000000000..871079a7bc3b9 --- /dev/null +++ b/arch/arm/boot/dts/ti/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +subdir-y += davinci +subdir-y += keystone +subdir-y += omap diff --git a/arch/arm/boot/dts/ti/davinci/Makefile b/arch/arm/boot/dts/ti/davinci/Makefile new file mode 100644 index 0000000000000..c0e388eb3dd1d --- /dev/null +++ b/arch/arm/boot/dts/ti/davinci/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_DAVINCI) += \ + da850-lcdk.dtb \ + da850-enbw-cmc.dtb \ + da850-evm.dtb \ + da850-lego-ev3.dtb diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts similarity index 100% rename from arch/arm/boot/dts/da850-enbw-cmc.dts rename to arch/arm/boot/dts/ti/davinci/da850-enbw-cmc.dts diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts similarity index 99% rename from arch/arm/boot/dts/da850-evm.dts rename to arch/arm/boot/dts/ti/davinci/da850-evm.dts index 0ca849885d1fe..111708d992caf 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -333,7 +333,7 @@ &gpio { status = "okay"; }; -/include/ "tps6507x.dtsi" +/include/ "../../tps6507x.dtsi" &tps { vdcdc1_2-supply = <&vbat>; diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts similarity index 100% rename from arch/arm/boot/dts/da850-lcdk.dts rename to arch/arm/boot/dts/ti/davinci/da850-lcdk.dts diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts similarity index 100% rename from arch/arm/boot/dts/da850-lego-ev3.dts rename to arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/ti/davinci/da850.dtsi similarity index 100% rename from arch/arm/boot/dts/da850.dtsi rename to arch/arm/boot/dts/ti/davinci/da850.dtsi diff --git a/arch/arm/boot/dts/ti/keystone/Makefile b/arch/arm/boot/dts/ti/keystone/Makefile new file mode 100644 index 0000000000000..4b18d08fa57c7 --- /dev/null +++ b/arch/arm/boot/dts/ti/keystone/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_KEYSTONE) += \ + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb \ + keystone-k2g-ice.dtb diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2e-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts similarity index 100% rename from arch/arm/boot/dts/keystone-k2e-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-evm.dts diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2e-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2e.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2e.dtsi diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts similarity index 100% rename from arch/arm/boot/dts/keystone-k2g-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-evm.dts diff --git a/arch/arm/boot/dts/keystone-k2g-ice.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts similarity index 100% rename from arch/arm/boot/dts/keystone-k2g-ice.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-ice.dts diff --git a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2g-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2g-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2g.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi diff --git a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-evm.dts diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2hk.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2hk.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2l-clocks.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-clocks.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts similarity index 100% rename from arch/arm/boot/dts/keystone-k2l-evm.dts rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-evm.dts diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2l-netcp.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l-netcp.dtsi diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone-k2l.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/ti/keystone/keystone.dtsi similarity index 100% rename from arch/arm/boot/dts/keystone.dtsi rename to arch/arm/boot/dts/ti/keystone/keystone.dtsi diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile new file mode 100644 index 0000000000000..d2b590004fedf --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_OMAP2) += \ + omap2420-h4.dtb \ + omap2420-n800.dtb \ + omap2420-n810.dtb \ + omap2420-n810-wimax.dtb \ + omap2430-sdp.dtb +dtb-$(CONFIG_ARCH_OMAP3) += \ + am3517-craneboard.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ + logicpd-torpedo-35xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit.dtb \ + logicpd-torpedo-37xx-devkit-28.dtb \ + logicpd-som-lv-35xx-devkit.dtb \ + logicpd-som-lv-37xx-devkit.dtb \ + omap3430-sdp.dtb \ + omap3-beagle.dtb \ + omap3-beagle-ab4.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle-xm-ab.dtb \ + omap3-cm-t3517.dtb \ + omap3-cm-t3530.dtb \ + omap3-cm-t3730.dtb \ + omap3-devkit8000.dtb \ + omap3-devkit8000-lcd43.dtb \ + omap3-devkit8000-lcd70.dtb \ + omap3-echo.dtb \ + omap3-evm.dtb \ + omap3-evm-37xx.dtb \ + omap3-gta04a3.dtb \ + omap3-gta04a4.dtb \ + omap3-gta04a5.dtb \ + omap3-gta04a5one.dtb \ + omap3-ha.dtb \ + omap3-ha-lcd.dtb \ + omap3-igep0020.dtb \ + omap3-igep0020-rev-f.dtb \ + omap3-igep0030.dtb \ + omap3-igep0030-rev-g.dtb \ + omap3-ldp.dtb \ + omap3-lilly-dbb056.dtb \ + omap3-n900.dtb \ + omap3-n9.dtb \ + omap3-n950.dtb \ + omap3-overo-alto35.dtb \ + omap3-overo-chestnut43.dtb \ + omap3-overo-gallop43.dtb \ + omap3-overo-palo35.dtb \ + omap3-overo-palo43.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-storm-gallop43.dtb \ + omap3-overo-storm-palo35.dtb \ + omap3-overo-storm-palo43.dtb \ + omap3-overo-storm-summit.dtb \ + omap3-overo-storm-tobi.dtb \ + omap3-overo-storm-tobiduo.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-tobi.dtb \ + omap3-overo-tobiduo.dtb \ + omap3-pandora-600mhz.dtb \ + omap3-pandora-1ghz.dtb \ + omap3-sbc-t3517.dtb \ + omap3-sbc-t3530.dtb \ + omap3-sbc-t3730.dtb \ + omap3-sniper.dtb \ + omap3-thunder.dtb \ + omap3-zoom3.dtb +dtb-$(CONFIG_ARCH_OMAP4) += \ + omap4-droid-bionic-xt875.dtb \ + omap4-droid4-xt894.dtb \ + omap4-duovero-parlor.dtb \ + omap4-epson-embt2ws.dtb \ + omap4-kc1.dtb \ + omap4-panda.dtb \ + omap4-panda-a4.dtb \ + omap4-panda-es.dtb \ + omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb \ + omap4-var-dvk-om44.dtb \ + omap4-var-stk-om44.dtb +dtb-$(CONFIG_SOC_AM33XX) += \ + am335x-baltos-ir2110.dtb \ + am335x-baltos-ir3220.dtb \ + am335x-baltos-ir5221.dtb \ + am335x-base0033.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblue.dtb \ + am335x-bonegreen.dtb \ + am335x-bonegreen-wireless.dtb \ + am335x-chiliboard.dtb \ + am335x-cm-t335.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-guardian.dtb \ + am335x-icev2.dtb \ + am335x-lxm.dtb \ + am335x-moxa-uc-2101.dtb \ + am335x-moxa-uc-8100-me-t.dtb \ + am335x-myirtech-myd.dtb \ + am335x-nano.dtb \ + am335x-netcan-plus-1xx.dtb \ + am335x-netcom-plus-2xx.dtb \ + am335x-netcom-plus-8xx.dtb \ + am335x-pdu001.dtb \ + am335x-pepper.dtb \ + am335x-phycore-rdk.dtb \ + am335x-pocketbeagle.dtb \ + am335x-regor-rdk.dtb \ + am335x-sancloud-bbe.dtb \ + am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ + am335x-shc.dtb \ + am335x-sbc-t335.dtb \ + am335x-sl50.dtb \ + am335x-wega-rdk.dtb \ + am335x-osd3358-sm-red.dtb +dtb-$(CONFIG_SOC_AM43XX) += \ + am43x-epos-evm.dtb \ + am437x-cm-t43.dtb \ + am437x-gp-evm.dtb \ + am437x-idk-evm.dtb \ + am437x-sbc-t43.dtb \ + am437x-sk-evm.dtb + +am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo +am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo + +dtb-$(CONFIG_SOC_DRA7XX) += \ + am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ + am57xx-beagle-x15-revc.dtb \ + am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ + am5729-beagleboneai.dtb \ + am57xx-cl-som-am57x.dtb \ + am57xx-sbc-am57x.dtb \ + am572x-idk.dtb \ + am572x-idk-touchscreen.dtbo \ + am571x-idk.dtb \ + am571x-idk-touchscreen.dtbo \ + am574x-idk.dtb \ + am57xx-idk-lcd-osd101t2045.dtbo \ + am57xx-idk-lcd-osd101t2587.dtbo \ + dra7-evm.dtb \ + dra72-evm.dtb \ + dra72-evm-revc.dtb \ + dra71-evm.dtb \ + dra76-evm.dtb +dtb-$(CONFIG_SOC_OMAP5) += \ + omap5-cm-t54.dtb \ + omap5-igep0050.dtb \ + omap5-sbc-t54.dtb \ + omap5-uevm.dtb +dtb-$(CONFIG_SOC_TI81XX) += \ + am3874-iceboard.dtb \ + dm8148-evm.dtb \ + dm8148-t410.dtb \ + dm8168-evm.dtb \ + dra62x-j5eco-evm.dtb diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts similarity index 100% rename from arch/arm/boot/dts/am335x-baltos-ir2110.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts similarity index 100% rename from arch/arm/boot/dts/am335x-baltos-ir3220.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts similarity index 100% rename from arch/arm/boot/dts/am335x-baltos-ir5221.dts rename to arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-baltos-leds.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-baltos.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi index c56087048cc10..c14d5b70c72f6 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -258,7 +258,7 @@ at24@50 { }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts similarity index 100% rename from arch/arm/boot/dts/am335x-base0033.dts rename to arch/arm/boot/dts/ti/omap/am335x-base0033.dts diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-bone-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index 0b073f290abc7..b958607c71dcf 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -273,7 +273,7 @@ cape3_data: cape_data@0 { }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { /* diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/ti/omap/am335x-bone.dts similarity index 100% rename from arch/arm/boot/dts/am335x-bone.dts rename to arch/arm/boot/dts/ti/omap/am335x-bone.dts diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-common.dtsi diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-hdmi.dtsi diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack-wireless.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblack-wireless.dts diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts similarity index 100% rename from arch/arm/boot/dts/am335x-boneblack.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblack.dts diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts similarity index 99% rename from arch/arm/boot/dts/am335x-boneblue.dts rename to arch/arm/boot/dts/ti/omap/am335x-boneblue.dts index b78e38f87892d..801399702547d 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblue.dts @@ -353,7 +353,7 @@ pressure@76 { }; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { /delete-property/ ti,pmic-shutdown-controller; diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-bonegreen-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen-common.dtsi diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts similarity index 100% rename from arch/arm/boot/dts/am335x-bonegreen-wireless.dts rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen-wireless.dts diff --git a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts similarity index 100% rename from arch/arm/boot/dts/am335x-bonegreen.dts rename to arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts similarity index 100% rename from arch/arm/boot/dts/am335x-chiliboard.dts rename to arch/arm/boot/dts/ti/omap/am335x-chiliboard.dts diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-chilisom.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi index 51021d5822140..bd43da6356b66 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-chilisom.dtsi @@ -66,7 +66,7 @@ tps: tps@24 { }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { regulators { diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts similarity index 100% rename from arch/arm/boot/dts/am335x-cm-t335.dts rename to arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/ti/omap/am335x-evm.dts similarity index 99% rename from arch/arm/boot/dts/am335x-evm.dts rename to arch/arm/boot/dts/ti/omap/am335x-evm.dts index 6560db1dcdbeb..61bf8bcd4c4ed 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts @@ -585,7 +585,7 @@ partition@9 { }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &mcasp1 { #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts similarity index 99% rename from arch/arm/boot/dts/am335x-evmsk.dts rename to arch/arm/boot/dts/ti/omap/am335x-evmsk.dts index 332f6c8ae68b1..57f78846c42d3 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts @@ -517,7 +517,7 @@ ecap2: pwm@100 { }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts similarity index 99% rename from arch/arm/boot/dts/am335x-guardian.dts rename to arch/arm/boot/dts/ti/omap/am335x-guardian.dts index 3031fc9061a4b..205fe0ed73522 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -292,7 +292,7 @@ &spi0 { status = "okay"; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { /* diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts similarity index 99% rename from arch/arm/boot/dts/am335x-icev2.dts rename to arch/arm/boot/dts/ti/omap/am335x-icev2.dts index 7ed2321a8b402..3c4228927f56e 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts @@ -360,7 +360,7 @@ adc { }; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-igep0033.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi index 4aed736554016..e85c33fd42f02 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi @@ -221,7 +221,7 @@ &usb1 { dr_mode = "host"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts similarity index 99% rename from arch/arm/boot/dts/am335x-lxm.dts rename to arch/arm/boot/dts/ti/omap/am335x-lxm.dts index 008be696327aa..be27b5a21b2c6 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-lxm.dts @@ -177,7 +177,7 @@ tps: tps@2d { }; }; -/include/ "tps65910.dtsi" +/include/ "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts similarity index 100% rename from arch/arm/boot/dts/am335x-moxa-uc-2101.dts rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2101.dts diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi index c16f3cff1e4ba..daaa5eee0f0df 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-common.dtsi @@ -233,7 +233,7 @@ &usb1 { }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts similarity index 100% rename from arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts rename to arch/arm/boot/dts/ti/omap/am335x-moxa-uc-8100-me-t.dts diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-myirtech-myc.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts similarity index 100% rename from arch/arm/boot/dts/am335x-myirtech-myd.dts rename to arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/ti/omap/am335x-nano.dts similarity index 99% rename from arch/arm/boot/dts/am335x-nano.dts rename to arch/arm/boot/dts/ti/omap/am335x-nano.dts index 9305ba9d85eff..a475c0d913060 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-nano.dts @@ -427,7 +427,7 @@ &usb0 { dr_mode = "host"; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { regulators { diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts similarity index 100% rename from arch/arm/boot/dts/am335x-netcan-plus-1xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts similarity index 100% rename from arch/arm/boot/dts/am335x-netcom-plus-2xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts similarity index 100% rename from arch/arm/boot/dts/am335x-netcom-plus-8xx.dts rename to arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts similarity index 100% rename from arch/arm/boot/dts/am335x-osd3358-sm-red.dts rename to arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi similarity index 98% rename from arch/arm/boot/dts/am335x-osd335x-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi index 2888b15999ee6..9863bf499a39e 100644 --- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi @@ -54,7 +54,7 @@ tps: tps@24 { }; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { interrupts = <7>; /* NMI */ diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-pcm-953.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-pcm-953.dtsi diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts similarity index 99% rename from arch/arm/boot/dts/am335x-pdu001.dts rename to arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index 92a1d5fea850c..3c9444e98c14b 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -400,7 +400,7 @@ &elm { status = "okay"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vbat>; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts similarity index 99% rename from arch/arm/boot/dts/am335x-pepper.dts rename to arch/arm/boot/dts/ti/omap/am335x-pepper.dts index 5a87b25a983bf..d5a4a21889d1c 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -423,7 +423,7 @@ &vdd5_reg { vin-supply = <&vbat>; }; -/include/ "tps65217.dtsi" +/include/ "../../tps65217.dtsi" &tps { backlight { diff --git a/arch/arm/boot/dts/am335x-phycore-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-phycore-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-phycore-rdk.dts diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi similarity index 99% rename from arch/arm/boot/dts/am335x-phycore-som.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi index feb3f4c249780..84c15a44df6a8 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-phycore-som.dtsi @@ -233,7 +233,7 @@ nandflash: nand@0,0 { }; /* Power */ -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &tps { vcc1-supply = <&vcc5v>; diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts similarity index 100% rename from arch/arm/boot/dts/am335x-pocketbeagle.dts rename to arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts diff --git a/arch/arm/boot/dts/am335x-regor-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-regor-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-regor-rdk.dts diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-regor.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-regor.dtsi diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-common.dtsi diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts similarity index 100% rename from arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts similarity index 100% rename from arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts similarity index 100% rename from arch/arm/boot/dts/am335x-sancloud-bbe.dts rename to arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe.dts diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts similarity index 100% rename from arch/arm/boot/dts/am335x-sbc-t335.dts rename to arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/ti/omap/am335x-shc.dts similarity index 100% rename from arch/arm/boot/dts/am335x-shc.dts rename to arch/arm/boot/dts/ti/omap/am335x-shc.dts diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts similarity index 99% rename from arch/arm/boot/dts/am335x-sl50.dts rename to arch/arm/boot/dts/ti/omap/am335x-sl50.dts index d35ed80de0f02..1115c812f6c8b 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -597,7 +597,7 @@ flash: flash@1 { }; }; -#include "tps65217.dtsi" +#include "../../tps65217.dtsi" &tps { ti,pmic-shutdown-controller; diff --git a/arch/arm/boot/dts/am335x-wega-rdk.dts b/arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts similarity index 100% rename from arch/arm/boot/dts/am335x-wega-rdk.dts rename to arch/arm/boot/dts/ti/omap/am335x-wega-rdk.dts diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/ti/omap/am335x-wega.dtsi similarity index 100% rename from arch/arm/boot/dts/am335x-wega.dtsi rename to arch/arm/boot/dts/ti/omap/am335x-wega.dtsi diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx-l4.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi similarity index 100% rename from arch/arm/boot/dts/am33xx.dtsi rename to arch/arm/boot/dts/ti/omap/am33xx.dtsi diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts similarity index 99% rename from arch/arm/boot/dts/am3517-craneboard.dts rename to arch/arm/boot/dts/ti/omap/am3517-craneboard.dts index afae7a4d232ef..d035c888731fc 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-craneboard.dts @@ -69,7 +69,7 @@ &mmc3 { status = "disabled"; }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &omap3_pmx_core { tps_pins: tps-pins { diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi similarity index 100% rename from arch/arm/boot/dts/am3517-evm-ui.dtsi rename to arch/arm/boot/dts/ti/omap/am3517-evm-ui.dtsi diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts similarity index 100% rename from arch/arm/boot/dts/am3517-evm.dts rename to arch/arm/boot/dts/ti/omap/am3517-evm.dts diff --git a/arch/arm/boot/dts/am3517-som.dtsi b/arch/arm/boot/dts/ti/omap/am3517-som.dtsi similarity index 100% rename from arch/arm/boot/dts/am3517-som.dtsi rename to arch/arm/boot/dts/ti/omap/am3517-som.dtsi diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi similarity index 100% rename from arch/arm/boot/dts/am3517.dtsi rename to arch/arm/boot/dts/ti/omap/am3517.dtsi diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts similarity index 100% rename from arch/arm/boot/dts/am3517_mt_ventoux.dts rename to arch/arm/boot/dts/ti/omap/am3517_mt_ventoux.dts diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am35xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am3703.dtsi b/arch/arm/boot/dts/ti/omap/am3703.dtsi similarity index 100% rename from arch/arm/boot/dts/am3703.dtsi rename to arch/arm/boot/dts/ti/omap/am3703.dtsi diff --git a/arch/arm/boot/dts/am3715.dtsi b/arch/arm/boot/dts/ti/omap/am3715.dtsi similarity index 100% rename from arch/arm/boot/dts/am3715.dtsi rename to arch/arm/boot/dts/ti/omap/am3715.dtsi diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/ti/omap/am3874-iceboard.dts similarity index 100% rename from arch/arm/boot/dts/am3874-iceboard.dts rename to arch/arm/boot/dts/ti/omap/am3874-iceboard.dts diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi similarity index 100% rename from arch/arm/boot/dts/am4372.dtsi rename to arch/arm/boot/dts/ti/omap/am4372.dtsi diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts similarity index 100% rename from arch/arm/boot/dts/am437x-cm-t43.dts rename to arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts similarity index 100% rename from arch/arm/boot/dts/am437x-gp-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-gp-evm.dts diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts similarity index 100% rename from arch/arm/boot/dts/am437x-idk-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/am437x-l4.dtsi rename to arch/arm/boot/dts/ti/omap/am437x-l4.dtsi diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts similarity index 100% rename from arch/arm/boot/dts/am437x-sbc-t43.dts rename to arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts similarity index 100% rename from arch/arm/boot/dts/am437x-sk-evm.dts rename to arch/arm/boot/dts/ti/omap/am437x-sk-evm.dts diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts similarity index 100% rename from arch/arm/boot/dts/am43x-epos-evm.dts rename to arch/arm/boot/dts/ti/omap/am43x-epos-evm.dts diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/am43xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/am43xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi similarity index 100% rename from arch/arm/boot/dts/am57-pruss.dtsi rename to arch/arm/boot/dts/ti/omap/am57-pruss.dtsi diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/ti/omap/am5718.dtsi similarity index 100% rename from arch/arm/boot/dts/am5718.dtsi rename to arch/arm/boot/dts/ti/omap/am5718.dtsi diff --git a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso similarity index 100% rename from arch/arm/boot/dts/am571x-idk-touchscreen.dtso rename to arch/arm/boot/dts/ti/omap/am571x-idk-touchscreen.dtso diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/ti/omap/am571x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am571x-idk.dts rename to arch/arm/boot/dts/ti/omap/am571x-idk.dts diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/ti/omap/am5728.dtsi similarity index 100% rename from arch/arm/boot/dts/am5728.dtsi rename to arch/arm/boot/dts/ti/omap/am5728.dtsi diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts similarity index 100% rename from arch/arm/boot/dts/am5729-beagleboneai.dts rename to arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am572x-idk-common.dtsi rename to arch/arm/boot/dts/ti/omap/am572x-idk-common.dtsi diff --git a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso similarity index 100% rename from arch/arm/boot/dts/am572x-idk-touchscreen.dtso rename to arch/arm/boot/dts/ti/omap/am572x-idk-touchscreen.dtso diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/ti/omap/am572x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am572x-idk.dts rename to arch/arm/boot/dts/ti/omap/am572x-idk.dts diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/ti/omap/am5748.dtsi similarity index 100% rename from arch/arm/boot/dts/am5748.dtsi rename to arch/arm/boot/dts/ti/omap/am5748.dtsi diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/ti/omap/am574x-idk.dts similarity index 100% rename from arch/arm/boot/dts/am574x-idk.dts rename to arch/arm/boot/dts/ti/omap/am574x-idk.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revb1.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15-revc.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-revc.dts diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-beagle-x15.dts rename to arch/arm/boot/dts/ti/omap/am57xx-beagle-x15.dts diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-cl-som-am57x.dts rename to arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts diff --git a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-commercial-grade.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-commercial-grade.dtsi diff --git a/arch/arm/boot/dts/am57xx-evm.dtso b/arch/arm/boot/dts/ti/omap/am57xx-evm.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-evm.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-evm.dtso diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-idk-common.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2045.dtso diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso similarity index 100% rename from arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso rename to arch/arm/boot/dts/ti/omap/am57xx-idk-lcd-osd101t2587.dtso diff --git a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi similarity index 100% rename from arch/arm/boot/dts/am57xx-industrial-grade.dtsi rename to arch/arm/boot/dts/ti/omap/am57xx-industrial-grade.dtsi diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts similarity index 100% rename from arch/arm/boot/dts/am57xx-sbc-am57x.dts rename to arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi similarity index 100% rename from arch/arm/boot/dts/compulab-sb-som.dtsi rename to arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi diff --git a/arch/arm/boot/dts/dm3725.dtsi b/arch/arm/boot/dts/ti/omap/dm3725.dtsi similarity index 100% rename from arch/arm/boot/dts/dm3725.dtsi rename to arch/arm/boot/dts/ti/omap/dm3725.dtsi diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts similarity index 100% rename from arch/arm/boot/dts/dm8148-evm.dts rename to arch/arm/boot/dts/ti/omap/dm8148-evm.dts diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/ti/omap/dm8148-t410.dts similarity index 100% rename from arch/arm/boot/dts/dm8148-t410.dts rename to arch/arm/boot/dts/ti/omap/dm8148-t410.dts diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dm814x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dm814x-clocks.dtsi diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/ti/omap/dm814x.dtsi similarity index 100% rename from arch/arm/boot/dts/dm814x.dtsi rename to arch/arm/boot/dts/ti/omap/dm814x.dtsi diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/ti/omap/dm8168-evm.dts similarity index 100% rename from arch/arm/boot/dts/dm8168-evm.dts rename to arch/arm/boot/dts/ti/omap/dm8168-evm.dts diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dm816x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi similarity index 100% rename from arch/arm/boot/dts/dm816x.dtsi rename to arch/arm/boot/dts/ti/omap/dm816x.dtsi diff --git a/arch/arm/boot/dts/dra62x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dra62x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dra62x-clocks.dtsi diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra62x-j5eco-evm.dts rename to arch/arm/boot/dts/ti/omap/dra62x-j5eco-evm.dts diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/ti/omap/dra62x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra62x.dtsi rename to arch/arm/boot/dts/ti/omap/dra62x.dtsi diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-dspeve-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-dspeve-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-evm-common.dtsi diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/ti/omap/dra7-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra7-evm.dts rename to arch/arm/boot/dts/ti/omap/dra7-evm.dts diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-ipu-dsp-common.dtsi diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-iva-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-iva-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-l4.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-l4.dtsi diff --git a/arch/arm/boot/dts/dra7-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra7-mmc-iodelay.dtsi diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7.dtsi rename to arch/arm/boot/dts/ti/omap/dra7.dtsi diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/ti/omap/dra71-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra71-evm.dts rename to arch/arm/boot/dts/ti/omap/dra71-evm.dts diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/ti/omap/dra71x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra71x.dtsi rename to arch/arm/boot/dts/ti/omap/dra71x.dtsi diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra72-evm-common.dtsi diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts similarity index 100% rename from arch/arm/boot/dts/dra72-evm-revc.dts rename to arch/arm/boot/dts/ti/omap/dra72-evm-revc.dts diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72-evm-tps65917.dtsi rename to arch/arm/boot/dts/ti/omap/dra72-evm-tps65917.dtsi diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/ti/omap/dra72-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra72-evm.dts rename to arch/arm/boot/dts/ti/omap/dra72-evm.dts diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra72x-mmc-iodelay.dtsi diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/ti/omap/dra72x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra72x.dtsi rename to arch/arm/boot/dts/ti/omap/dra72x.dtsi diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi rename to arch/arm/boot/dts/ti/omap/dra74-ipu-dsp-common.dtsi diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x-mmc-iodelay.dtsi diff --git a/arch/arm/boot/dts/dra74x-p.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74x-p.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x-p.dtsi diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/ti/omap/dra74x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra74x.dtsi rename to arch/arm/boot/dts/ti/omap/dra74x.dtsi diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/ti/omap/dra76-evm.dts similarity index 100% rename from arch/arm/boot/dts/dra76-evm.dts rename to arch/arm/boot/dts/ti/omap/dra76-evm.dts diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi similarity index 100% rename from arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi rename to arch/arm/boot/dts/ti/omap/dra76x-mmc-iodelay.dtsi diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi similarity index 100% rename from arch/arm/boot/dts/dra76x.dtsi rename to arch/arm/boot/dts/ti/omap/dra76x.dtsi diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/dra7xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi similarity index 100% rename from arch/arm/boot/dts/elpida_ecb240abacn.dtsi rename to arch/arm/boot/dts/ti/omap/elpida_ecb240abacn.dtsi diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-35xx-devkit.dts diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-37xx-devkit.dts diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi similarity index 100% rename from arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv-baseboard.dtsi diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi similarity index 100% rename from arch/arm/boot/dts/logicpd-som-lv.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-som-lv.dtsi diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-35xx-devkit.dts diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit-28.dts diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-37xx-devkit.dts diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-baseboard.dtsi diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi similarity index 100% rename from arch/arm/boot/dts/logicpd-torpedo-som.dtsi rename to arch/arm/boot/dts/ti/omap/logicpd-torpedo-som.dtsi diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi similarity index 100% rename from arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi rename to arch/arm/boot/dts/ti/omap/motorola-cpcap-mapphone.dtsi diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi similarity index 100% rename from arch/arm/boot/dts/motorola-mapphone-common.dtsi rename to arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi rename to arch/arm/boot/dts/ti/omap/omap-gpmc-smsc911x.dtsi diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi rename to arch/arm/boot/dts/ti/omap/omap-gpmc-smsc9221.dtsi diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap-zoom-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap-zoom-common.dtsi diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/ti/omap/omap2.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2.dtsi rename to arch/arm/boot/dts/ti/omap/omap2.dtsi diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420-clocks.dtsi diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/ti/omap/omap2420-h4.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-h4.dts rename to arch/arm/boot/dts/ti/omap/omap2420-h4.dts diff --git a/arch/arm/boot/dts/omap2420-n800.dts b/arch/arm/boot/dts/ti/omap/omap2420-n800.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-n800.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n800.dts diff --git a/arch/arm/boot/dts/omap2420-n810-wimax.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-n810-wimax.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n810-wimax.dts diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/ti/omap/omap2420-n810.dts similarity index 100% rename from arch/arm/boot/dts/omap2420-n810.dts rename to arch/arm/boot/dts/ti/omap/omap2420-n810.dts diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420-n8x0-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420-n8x0-common.dtsi diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/ti/omap/omap2420.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2420.dtsi rename to arch/arm/boot/dts/ti/omap/omap2420.dtsi diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2430-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap2430-clocks.dtsi diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap2430-sdp.dts similarity index 100% rename from arch/arm/boot/dts/omap2430-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap2430-sdp.dts diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi similarity index 100% rename from arch/arm/boot/dts/omap2430.dtsi rename to arch/arm/boot/dts/ti/omap/omap2430.dtsi diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap24xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap24xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap3-beagle-ab4.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle-ab4.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-ab4.dts diff --git a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle-xm-ab.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-xm-ab.dts diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle-xm.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle-xm.dts diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/ti/omap/omap3-beagle.dts similarity index 100% rename from arch/arm/boot/dts/omap3-beagle.dts rename to arch/arm/boot/dts/ti/omap/omap3-beagle.dts diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts similarity index 100% rename from arch/arm/boot/dts/omap3-cm-t3517.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3517.dts diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts similarity index 100% rename from arch/arm/boot/dts/omap3-cm-t3530.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3530.dts diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts similarity index 100% rename from arch/arm/boot/dts/omap3-cm-t3730.dts rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3730.dts diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-cm-t3x.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3x.dtsi diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-cm-t3x30.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-cpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd43.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd43.dts diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000-lcd70.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd70.dts diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts similarity index 100% rename from arch/arm/boot/dts/omap3-devkit8000.dts rename to arch/arm/boot/dts/ti/omap/omap3-devkit8000.dts diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/ti/omap/omap3-echo.dts similarity index 99% rename from arch/arm/boot/dts/omap3-echo.dts rename to arch/arm/boot/dts/ti/omap/omap3-echo.dts index 263e517944dde..96011c976f5b8 100644 --- a/arch/arm/boot/dts/omap3-echo.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-echo.dts @@ -521,7 +521,7 @@ codec0: codec@18 { }; -#include "tps65910.dtsi" +#include "../../tps65910.dtsi" &omap3_pmx_core { tps_pins: tps-pins { diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts similarity index 100% rename from arch/arm/boot/dts/omap3-evm-37xx.dts rename to arch/arm/boot/dts/ti/omap/omap3-evm-37xx.dts diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-evm-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-evm-common.dtsi diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-evm-processor-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/ti/omap/omap3-evm.dts similarity index 100% rename from arch/arm/boot/dts/omap3-evm.dts rename to arch/arm/boot/dts/ti/omap/omap3-evm.dts diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-gta04.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a3.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a3.dts diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a4.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a4.dts diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a5.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a5.dts diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts similarity index 100% rename from arch/arm/boot/dts/omap3-gta04a5one.dts rename to arch/arm/boot/dts/ti/omap/omap3-gta04a5one.dts diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-ha-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-ha-common.dtsi diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts similarity index 100% rename from arch/arm/boot/dts/omap3-ha-lcd.dts rename to arch/arm/boot/dts/ti/omap/omap3-ha-lcd.dts diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/ti/omap/omap3-ha.dts similarity index 100% rename from arch/arm/boot/dts/omap3-ha.dts rename to arch/arm/boot/dts/ti/omap/omap3-ha.dts diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-igep.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep.dtsi diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-igep0020-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep0020-common.dtsi diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts similarity index 100% rename from arch/arm/boot/dts/omap3-igep0020-rev-f.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0020-rev-f.dts diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0020.dts similarity index 100% rename from arch/arm/boot/dts/omap3-igep0020.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0020.dts diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-igep0030-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-igep0030-common.dtsi diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts similarity index 100% rename from arch/arm/boot/dts/omap3-igep0030-rev-g.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0030-rev-g.dts diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/ti/omap/omap3-igep0030.dts similarity index 100% rename from arch/arm/boot/dts/omap3-igep0030.dts rename to arch/arm/boot/dts/ti/omap/omap3-igep0030.dts diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/ti/omap/omap3-ldp.dts similarity index 100% rename from arch/arm/boot/dts/omap3-ldp.dts rename to arch/arm/boot/dts/ti/omap/omap3-ldp.dts diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-lilly-a83x.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-lilly-a83x.dtsi diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts similarity index 100% rename from arch/arm/boot/dts/omap3-lilly-dbb056.dts rename to arch/arm/boot/dts/ti/omap/omap3-lilly-dbb056.dts diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/ti/omap/omap3-n9.dts similarity index 100% rename from arch/arm/boot/dts/omap3-n9.dts rename to arch/arm/boot/dts/ti/omap/omap3-n9.dts diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts similarity index 100% rename from arch/arm/boot/dts/omap3-n900.dts rename to arch/arm/boot/dts/ti/omap/omap3-n900.dts diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-n950-n9.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/ti/omap/omap3-n950.dts similarity index 100% rename from arch/arm/boot/dts/omap3-n950.dts rename to arch/arm/boot/dts/ti/omap/omap3-n950.dts diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-alto35-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-alto35-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-alto35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-alto35.dts diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-base.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-base.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-chestnut43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-chestnut43.dts diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-common-dvi.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-dvi.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-common-peripherals.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-gallop43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-gallop43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-gallop43.dts diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo35-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo35-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo35.dts diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo43-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo43-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-palo43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-palo43.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-alto35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-alto35.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-chestnut43.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-gallop43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-gallop43.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-palo35.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo35.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-palo43.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-palo43.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-summit.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-summit.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-tobi.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobi.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm-tobiduo.dts diff --git a/arch/arm/boot/dts/omap3-overo-storm.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-storm.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-storm.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-summit-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-summit-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-summit.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-summit.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-summit.dts diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobi-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobi-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobi.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobi.dts diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo-common.dtsi diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo.dts b/arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts similarity index 100% rename from arch/arm/boot/dts/omap3-overo-tobiduo.dts rename to arch/arm/boot/dts/ti/omap/omap3-overo-tobiduo.dts diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-overo.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-overo.dtsi diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts similarity index 100% rename from arch/arm/boot/dts/omap3-pandora-1ghz.dts rename to arch/arm/boot/dts/ti/omap/omap3-pandora-1ghz.dts diff --git a/arch/arm/boot/dts/omap3-pandora-600mhz.dts b/arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts similarity index 100% rename from arch/arm/boot/dts/omap3-pandora-600mhz.dts rename to arch/arm/boot/dts/ti/omap/omap3-pandora-600mhz.dts diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-pandora-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-pandora-common.dtsi diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-panel-sharp-ls037v7dw01.dtsi diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-sb-t35.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-sb-t35.dtsi diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts similarity index 100% rename from arch/arm/boot/dts/omap3-sbc-t3517.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts similarity index 100% rename from arch/arm/boot/dts/omap3-sbc-t3530.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3530.dts diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts similarity index 100% rename from arch/arm/boot/dts/omap3-sbc-t3730.dts rename to arch/arm/boot/dts/ti/omap/omap3-sbc-t3730.dts diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/ti/omap/omap3-sniper.dts similarity index 100% rename from arch/arm/boot/dts/omap3-sniper.dts rename to arch/arm/boot/dts/ti/omap/omap3-sniper.dts diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3-tao3530.dtsi rename to arch/arm/boot/dts/ti/omap/omap3-tao3530.dtsi diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/ti/omap/omap3-thunder.dts similarity index 100% rename from arch/arm/boot/dts/omap3-thunder.dts rename to arch/arm/boot/dts/ti/omap/omap3-thunder.dts diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/ti/omap/omap3-zoom3.dts similarity index 100% rename from arch/arm/boot/dts/omap3-zoom3.dts rename to arch/arm/boot/dts/ti/omap/omap3-zoom3.dts diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3.dtsi rename to arch/arm/boot/dts/ti/omap/omap3.dtsi diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/ti/omap/omap3430-sdp.dts similarity index 100% rename from arch/arm/boot/dts/omap3430-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap3430-sdp.dts diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3430es1-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi similarity index 100% rename from arch/arm/boot/dts/omap34xx.dtsi rename to arch/arm/boot/dts/ti/omap/omap34xx.dtsi diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx-omap3430es2plus-clocks.dtsi diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi similarity index 100% rename from arch/arm/boot/dts/omap36xx.dtsi rename to arch/arm/boot/dts/ti/omap/omap36xx.dtsi diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap3xxx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap3xxx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-cpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-cpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts similarity index 100% rename from arch/arm/boot/dts/omap4-droid-bionic-xt875.dts rename to arch/arm/boot/dts/ti/omap/omap4-droid-bionic-xt875.dts diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts similarity index 100% rename from arch/arm/boot/dts/omap4-droid4-xt894.dts rename to arch/arm/boot/dts/ti/omap/omap4-droid4-xt894.dts diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts similarity index 100% rename from arch/arm/boot/dts/omap4-duovero-parlor.dts rename to arch/arm/boot/dts/ti/omap/omap4-duovero-parlor.dts diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-duovero.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-duovero.dtsi diff --git a/arch/arm/boot/dts/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts similarity index 100% rename from arch/arm/boot/dts/omap4-epson-embt2ws.dts rename to arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/ti/omap/omap4-kc1.dts similarity index 100% rename from arch/arm/boot/dts/omap4-kc1.dts rename to arch/arm/boot/dts/ti/omap/omap4-kc1.dts diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-l4-abe.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-l4.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-l4.dtsi diff --git a/arch/arm/boot/dts/omap4-mcpdm.dtsi b/arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-mcpdm.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-mcpdm.dtsi diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts similarity index 100% rename from arch/arm/boot/dts/omap4-panda-a4.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-panda-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts similarity index 100% rename from arch/arm/boot/dts/omap4-panda-es.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda-es.dts diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/ti/omap/omap4-panda.dts similarity index 100% rename from arch/arm/boot/dts/omap4-panda.dts rename to arch/arm/boot/dts/ti/omap/omap4-panda.dts diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts similarity index 100% rename from arch/arm/boot/dts/omap4-sdp-es23plus.dts rename to arch/arm/boot/dts/ti/omap/omap4-sdp-es23plus.dts diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts similarity index 100% rename from arch/arm/boot/dts/omap4-sdp.dts rename to arch/arm/boot/dts/ti/omap/omap4-sdp.dts diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts similarity index 100% rename from arch/arm/boot/dts/omap4-var-dvk-om44.dts rename to arch/arm/boot/dts/ti/omap/omap4-var-dvk-om44.dts diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-var-om44customboard.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-som-om44-wlan.dtsi diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4-var-som-om44.dtsi rename to arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts similarity index 100% rename from arch/arm/boot/dts/omap4-var-stk-om44.dts rename to arch/arm/boot/dts/ti/omap/omap4-var-stk-om44.dts diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4.dtsi rename to arch/arm/boot/dts/ti/omap/omap4.dtsi diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap443x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap443x-clocks.dtsi diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/ti/omap/omap443x.dtsi similarity index 100% rename from arch/arm/boot/dts/omap443x.dtsi rename to arch/arm/boot/dts/ti/omap/omap443x.dtsi diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/ti/omap/omap4460.dtsi similarity index 100% rename from arch/arm/boot/dts/omap4460.dtsi rename to arch/arm/boot/dts/ti/omap/omap4460.dtsi diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap446x-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap446x-clocks.dtsi diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap44xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap44xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-board-common.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts similarity index 100% rename from arch/arm/boot/dts/omap5-cm-t54.dts rename to arch/arm/boot/dts/ti/omap/omap5-cm-t54.dts diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-core-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-core-thermal.dtsi diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-gpu-thermal.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-gpu-thermal.dtsi diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts similarity index 100% rename from arch/arm/boot/dts/omap5-igep0050.dts rename to arch/arm/boot/dts/ti/omap/omap5-igep0050.dts diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-l4-abe.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5-l4.dtsi rename to arch/arm/boot/dts/ti/omap/omap5-l4.dtsi diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts similarity index 100% rename from arch/arm/boot/dts/omap5-sbc-t54.dts rename to arch/arm/boot/dts/ti/omap/omap5-sbc-t54.dts diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/ti/omap/omap5-uevm.dts similarity index 100% rename from arch/arm/boot/dts/omap5-uevm.dts rename to arch/arm/boot/dts/ti/omap/omap5-uevm.dts diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi similarity index 100% rename from arch/arm/boot/dts/omap5.dtsi rename to arch/arm/boot/dts/ti/omap/omap5.dtsi diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi similarity index 100% rename from arch/arm/boot/dts/omap54xx-clocks.dtsi rename to arch/arm/boot/dts/ti/omap/omap54xx-clocks.dtsi diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/ti/omap/twl4030.dtsi similarity index 100% rename from arch/arm/boot/dts/twl4030.dtsi rename to arch/arm/boot/dts/ti/omap/twl4030.dtsi diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi similarity index 100% rename from arch/arm/boot/dts/twl4030_omap3.dtsi rename to arch/arm/boot/dts/ti/omap/twl4030_omap3.dtsi diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/ti/omap/twl6030.dtsi similarity index 100% rename from arch/arm/boot/dts/twl6030.dtsi rename to arch/arm/boot/dts/ti/omap/twl6030.dtsi diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi similarity index 100% rename from arch/arm/boot/dts/twl6030_omap4.dtsi rename to arch/arm/boot/dts/ti/omap/twl6030_omap4.dtsi diff --git a/arch/arm/boot/dts/unisoc/Makefile b/arch/arm/boot/dts/unisoc/Makefile new file mode 100644 index 0000000000000..dba5cd874ee74 --- /dev/null +++ b/arch/arm/boot/dts/unisoc/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_RDA) += \ + rda8810pl-orangepi-2g-iot.dtb \ + rda8810pl-orangepi-i96.dtb diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts similarity index 100% rename from arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts rename to arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts similarity index 100% rename from arch/arm/boot/dts/rda8810pl-orangepi-i96.dts rename to arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi similarity index 100% rename from arch/arm/boot/dts/rda8810pl.dtsi rename to arch/arm/boot/dts/unisoc/rda8810pl.dtsi diff --git a/arch/arm/boot/dts/vt8500/Makefile b/arch/arm/boot/dts/vt8500/Makefile new file mode 100644 index 0000000000000..255f4403af91c --- /dev/null +++ b/arch/arm/boot/dts/vt8500/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VT8500) += \ + vt8500-bv07.dtb \ + wm8505-ref.dtb \ + wm8650-mid.dtb \ + wm8750-apc8750.dtb \ + wm8850-w70v2.dtb diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts similarity index 100% rename from arch/arm/boot/dts/vt8500-bv07.dts rename to arch/arm/boot/dts/vt8500/vt8500-bv07.dts diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi similarity index 100% rename from arch/arm/boot/dts/vt8500.dtsi rename to arch/arm/boot/dts/vt8500/vt8500.dtsi diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts similarity index 100% rename from arch/arm/boot/dts/wm8505-ref.dts rename to arch/arm/boot/dts/vt8500/wm8505-ref.dts diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8505.dtsi rename to arch/arm/boot/dts/vt8500/wm8505.dtsi diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts similarity index 100% rename from arch/arm/boot/dts/wm8650-mid.dts rename to arch/arm/boot/dts/vt8500/wm8650-mid.dts diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8650.dtsi rename to arch/arm/boot/dts/vt8500/wm8650.dtsi diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts similarity index 100% rename from arch/arm/boot/dts/wm8750-apc8750.dts rename to arch/arm/boot/dts/vt8500/wm8750-apc8750.dts diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8750.dtsi rename to arch/arm/boot/dts/vt8500/wm8750.dtsi diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts similarity index 100% rename from arch/arm/boot/dts/wm8850-w70v2.dts rename to arch/arm/boot/dts/vt8500/wm8850-w70v2.dts diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi similarity index 100% rename from arch/arm/boot/dts/wm8850.dtsi rename to arch/arm/boot/dts/vt8500/wm8850.dtsi diff --git a/arch/arm/boot/dts/xen/Makefile b/arch/arm/boot/dts/xen/Makefile new file mode 100644 index 0000000000000..26c50f1389529 --- /dev/null +++ b/arch/arm/boot/dts/xen/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VIRT) += \ + xenvm-4.2.dtb diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xen/xenvm-4.2.dts similarity index 100% rename from arch/arm/boot/dts/xenvm-4.2.dts rename to arch/arm/boot/dts/xen/xenvm-4.2.dts diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile new file mode 100644 index 0000000000000..9233e539b192b --- /dev/null +++ b/arch/arm/boot/dts/xilinx/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-cc108.dtb \ + zynq-ebaz4205.dtb \ + zynq-microzed.dtb \ + zynq-parallella.dtb \ + zynq-zc702.dtb \ + zynq-zc706.dtb \ + zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ + zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ + zynq-zed.dtb \ + zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ + zynq-zybo.dtb \ + zynq-zybo-z7.dtb diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi similarity index 100% rename from arch/arm/boot/dts/zynq-7000.dtsi rename to arch/arm/boot/dts/xilinx/zynq-7000.dtsi diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts similarity index 100% rename from arch/arm/boot/dts/zynq-cc108.dts rename to arch/arm/boot/dts/xilinx/zynq-cc108.dts diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts similarity index 100% rename from arch/arm/boot/dts/zynq-ebaz4205.dts rename to arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/xilinx/zynq-microzed.dts similarity index 100% rename from arch/arm/boot/dts/zynq-microzed.dts rename to arch/arm/boot/dts/xilinx/zynq-microzed.dts diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/xilinx/zynq-parallella.dts similarity index 100% rename from arch/arm/boot/dts/zynq-parallella.dts rename to arch/arm/boot/dts/xilinx/zynq-parallella.dts diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc702.dts rename to arch/arm/boot/dts/xilinx/zynq-zc702.dts diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc706.dts rename to arch/arm/boot/dts/xilinx/zynq-zc706.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm010.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm011.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm012.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zc770-xm013.dts rename to arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/xilinx/zynq-zed.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zed.dts rename to arch/arm/boot/dts/xilinx/zynq-zed.dts diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi similarity index 100% rename from arch/arm/boot/dts/zynq-zturn-common.dtsi rename to arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zturn-v5.dts rename to arch/arm/boot/dts/xilinx/zynq-zturn-v5.dts diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/xilinx/zynq-zturn.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zturn.dts rename to arch/arm/boot/dts/xilinx/zynq-zturn.dts diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zybo-z7.dts rename to arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/xilinx/zynq-zybo.dts similarity index 100% rename from arch/arm/boot/dts/zynq-zybo.dts rename to arch/arm/boot/dts/xilinx/zynq-zybo.dts diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts index 8857a3791593f..6406a29c85f2a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts @@ -4,7 +4,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus v1.2 H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts index 77661006dfba1..cfb943e9ae85a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Banana Pi BPI-M2-Plus H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi index fc570011495f3..2f4b46746f47c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi @@ -8,4 +8,4 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts index d811df332824b..b79018c65cae1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts @@ -5,7 +5,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" #include "sun50i-h5-cpu-opp.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-CC H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts index e59d68b525fc9..dc657de2a1a40 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts @@ -3,7 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" -#include +#include / { model = "Libre Computer Board ALL-H3-IT H5"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index a56fae761a1f3..d3caf27b6a55c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2016 ARM Ltd. -#include +#include #include diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 796cd7d02eb55..3554201e94d61 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -13,7 +13,7 @@ /dts-v1/; #include -#include "vexpress-v2m-rs1.dtsi" +#include "arm/arm/vexpress-v2m-rs1.dtsi" / { model = "V2F-1XV7 Cortex-A53x2 SMM"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts index d24c53682e449..c7280bdefa8d6 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" +#include "arm/broadcom/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts index b9000f58beb55..d9d2852b794f0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-400.dts" +#include "arm/broadcom/bcm2711-rpi-400.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index e36d395e39510..8810322aa66ae 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-cm4-io.dts" +#include "arm/broadcom/bcm2711-rpi-cm4-io.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts index f0ec56a1c4d72..17d778a7e0c9e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-a-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-a-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts index 46ad2023cccf1..0cf6240b6bf0c 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b-plus.dts" +#include "arm/broadcom/bcm2837-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts index 89b78d6c19bf1..f429468fd86e8 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b.dts" +#include "arm/broadcom/bcm2837-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts index b1c4ab212c649..3fa21bd16b499 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-cm3-io3.dts" +#include "arm/broadcom/bcm2837-rpi-cm3-io3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts index 307ae693e4a0b..363381a0cfb5e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -1,2 +1,2 @@ // SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-zero-2-w.dts" +#include "arm/broadcom/bcm2837-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index b1fa68835b09c..5ea8bda2bfa6b 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -734,4 +734,4 @@ timer { }; #include "exynos7-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0a2c5..d69fc2392bd0e 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -452,4 +452,4 @@ i2c_7: i2c@11cd0000 { }; #include "exynos7885-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" +#include "arm/samsung/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts index 369de5dc0ebdf..c58fb7658d7a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include +#include #include "rk3399pro-vmarc-som.dtsi" / { diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi index 9caabbb8bae3f..3e1132204c7d4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi index e66d999d9f5d3..8afbe5ce45f2e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi @@ -1 +1 @@ -#include +#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi index 28c5b4ed1d950..6d0e3226a966e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi @@ -1 +1 @@ -#include +#include -- GitLab From 46448b36ff8c807194d5884a6efce00891e4bd02 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 22 Jun 2023 10:14:02 +0200 Subject: [PATCH 926/926] ARM: mvebu: fix unit address on armada-390-db flash The unit address needs to be changed to match the reg property: arch/arm/boot/dts/marvell/armada-390-db.dts:84.10-106.4: Warning (spi_bus_reg): /soc/spi@10680/flash@1: SPI bus unit address format error, expected "0" Reported-by: Stephen Rothwell Reviewed-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/marvell/armada-390-db.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/marvell/armada-390-db.dts b/arch/arm/boot/dts/marvell/armada-390-db.dts index 792d0a0184e82..20f518dbac971 100644 --- a/arch/arm/boot/dts/marvell/armada-390-db.dts +++ b/arch/arm/boot/dts/marvell/armada-390-db.dts @@ -81,7 +81,7 @@ &spi1 { pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; - flash@1 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", -- GitLab