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Commit ec9cdaaa authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Andre Przywara
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sunxi: dram: h6: Improve DDR3 config detection



It turns out that in rare cases, current analytical approach to detect
correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
with DDR3, incorrect DRAM configuration triggers write leveling error
which immediately stops initialization process. Exact reason why this
error appears isn't known. However, if correct configuration is used,
initalization works without problem.

In order to fix this issue, simply try another configuration when any
kind of error appears during initialization, not just those related to
rank and bus width.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Tested-by: default avatarThomas Graichen <thomas.graichen@googlemail.com>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Tested-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
parent 92600edb
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