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Commit e9284066 authored by Michal Simek's avatar Michal Simek
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arm64: zynqmp: Enable FPGA loading from SPL



fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 0d76b71d
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