diff --git a/MAINTAINERS b/MAINTAINERS index 6853288975c016e68e7facb888c825ada072c5c8..638b2fdd442f57e7bc48c497dba7bfcfbb1cb985 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -598,22 +598,6 @@ R: Marc Murphy S: Supported F: arch/arm/dts/am335x-sancloud* -ARM SC5XX -M: Nathan Barrett-Morrison -M: Greg Malysa -M: Ian Roberts -M: Vasileios Bimpikas -M: Utsav Agarwal -M: Arturs Artamonovs -S: Supported -T: git https://github.com/analogdevicesinc/lnxdsp-u-boot -F: arch/arm/include/asm/arch-adi/ -F: arch/arm/mach-sc5xx/ -F: drivers/clk/adi/ -F: drivers/serial/serial_adi_uart4.c -F: drivers/timer/adi_sc5xx_timer.c -F: include/env/adi/ - ARM SNAPDRAGON M: Caleb Connolly M: Neil Armstrong @@ -1017,8 +1001,11 @@ F: common/update.c F: doc/api/dfu.rst F: doc/usage/dfu.rst F: drivers/dfu/ +F: drivers/usb/*/*gadget* F: drivers/usb/gadget/ F: include/dfu.h +F: include/linux/usb/ch9.h +F: include/linux/usb/gadget.h DRIVER MODEL M: Simon Glass @@ -1118,6 +1105,7 @@ F: test/py/tests/test_event_dump.py FASTBOOT M: Mattijs Korpershoek S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/fastboot.c F: doc/android/fastboot*.rst F: include/fastboot.h diff --git a/Makefile b/Makefile index 44deb339af197140be63f0fd14dc5baac41aca37..79b28c2d81fd39c9b4ae4a120bb9fa0cc8745764 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* diff --git a/api/api.c b/api/api.c index d22132f62fe336dee9da10c4f93bd5ed9a687657..89003c161c2fbf58cf147a248b7028f38d0f5dea 100644 --- a/api/api.c +++ b/api/api.c @@ -7,13 +7,11 @@ #include #include +#include #include #include -#include #include -#include #include -#include #include #include #include diff --git a/api/api_display.c b/api/api_display.c index 8fd078c8c4aa5f5ee57feed64802f64106b1e55b..2e877a85d1474b3054ca55fc56b651c625c4dbe3 100644 --- a/api/api_display.c +++ b/api/api_display.c @@ -3,9 +3,9 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include -#include /* TODO(clchiou): add support of video device */ diff --git a/api/api_net.c b/api/api_net.c index 264ff530563b913a2db352176901c00f99c4f01c..7515c26e8b44edd3a4cc2e8184776cc97a4612c5 100644 --- a/api/api_net.c +++ b/api/api_net.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/api/api_platform-arm.c b/api/api_platform-arm.c index 9afba66c244218009a6116dca610fce7800f0ac9..6cfd9e6cc20cd2f7d08d90fc550cdac4e25fa4ee 100644 --- a/api/api_platform-arm.c +++ b/api/api_platform-arm.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "api_private.h" diff --git a/api/api_platform-mips.c b/api/api_platform-mips.c index 262b35a277795143c679147b306db6230869e88e..e1509663af54c76d042eff4dbdc67a44330d3281 100644 --- a/api/api_platform-mips.c +++ b/api/api_platform-mips.c @@ -9,6 +9,7 @@ #include #include +#include #include #include "api_private.h" diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c index 3a04a9f691c5b58a30a7160c97f2a435a30304a3..847a4a3015b0a46898a032c581c6fc38c1e49ea3 100644 --- a/api/api_platform-powerpc.c +++ b/api/api_platform-powerpc.c @@ -12,6 +12,7 @@ #include #include +#include #include #include "api_private.h" diff --git a/api/api_storage.c b/api/api_storage.c index 3d2d9d6ef4c181cabfc7df3e1d843497226f83c6..78becbe39fb6546656f62490172da0c1205e0df0 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -6,10 +6,10 @@ */ #include +#include #include #include #include -#include #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) #include diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index fd9b7fb5f8dbe4d7efbab4183404c04ea00db520..e35a26f1eb14d220bcb1ad70a13e83b05e4c6fbe 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -6,8 +6,6 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H -#include - #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d46707957b30703c0533d3d4f467aa7b851ca65..38fc757c1f0044cb8be6aa632f8e88d7290eaa65 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -653,6 +653,7 @@ config ARCH_BCM283X select SERIAL_SEARCH_ALL imply CMD_DM imply FAT_WRITE + imply OF_HAS_PRIOR_STAGE config ARCH_BCMSTB bool "Broadcom BCM7XXX family" @@ -1852,9 +1853,6 @@ config TARGET_LS1046AFRWY development platform that supports the QorIQ LS1046A Layerscape Architecture processor. -config ARCH_SC5XX - bool "Analog Devices SC5XX-processor family" - config TARGET_SL28 bool "Support sl28" select ARCH_LS1028A @@ -2288,8 +2286,6 @@ source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" -source "arch/arm/mach-sc5xx/Kconfig" - source "arch/arm/mach-snapdragon/Kconfig" source "arch/arm/mach-socfpga/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 734c6d69926bb3b8b074482d4d5c31197fb4c258..a4266a3e3668c5fe9b9bfdd16b30b63f762ba020 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -78,7 +78,6 @@ machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_RENESAS) += renesas machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx -machine-$(CONFIG_ARCH_SC5XX) += sc5xx machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_STM32) += stm32 diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 01d2e1a125d6e48e5ed74434fd7782caae40de59..1e16b89d0066349a5e257e0c364cb477b909324a 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -14,6 +14,7 @@ * CPU specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 87ca303e31ba8c53c6dc0ddd053ba89385c0f6f0..9997e8fc3396b8d1a38b943c51e621f3031eed5d 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -6,6 +6,7 @@ * (c) 2007 Pengutronix, Sascha Hauer */ +#include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index fc56baccfcd6e6a013f819568b2f433336dced38..a3d4f14796234df8b6b3c3441afb508a8bb8d3a4 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -4,6 +4,7 @@ * Sascha Hauer, Pengutronix */ +#include #include #include #include diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index b41ca68ae5524f585e492decfeff05fc41a347db..a913860491cb02e6ac33ebb337cb658bb4c7d411 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -4,6 +4,7 @@ * Sascha Hauer, Pengutronix */ +#include #include #include #include diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index e3d0216158fed68f6e2faa217f52502202abc8d1..f0fc58deadbaf0d3b72e237592c0178d55d24b23 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -9,7 +9,7 @@ * Alex Zuepke */ -#include +#include #if defined(CONFIG_ARCH_TEGRA) static ulong timestamp; diff --git a/arch/arm/cpu/arm920t/cpu.c b/arch/arm/cpu/arm920t/cpu.c index 61e182305738859e6e35d74688967a86bd49f923..305713e78615ac058d20dcde5abea2aa98756bd0 100644 --- a/arch/arm/cpu/arm920t/cpu.c +++ b/arch/arm/cpu/arm920t/cpu.c @@ -12,6 +12,7 @@ * CPU specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e792e8e795efb9608b0a5863588cb5819fe53965..cba4a1f0358f50992146ed93f2fb4e80cfe45aa6 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -8,6 +8,7 @@ */ #include +#include #include /* diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 5b87a3af91b22a19cd607a51dea1eef27d20bae6..95963d2665f45543083acd47c750e4dec6d46e34 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -6,6 +6,7 @@ #include #include #include +#include #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 07ab04b7b08a4425d3f8e145107617d2dacaac7c..2ce413a7f8661a2be32a412c9af39fac843ca519 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -12,6 +12,7 @@ * CPU specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 58f6cf80cae048a90bb41e157f15801af9eaa4a8..4e1cf3a1e32bbcdb7cf0cae6524f29c60490ad9e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -9,6 +9,7 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c index 851b4deb080ba43b1956064964a55016aaa3e776..381264b8a18d24a783f70989aed6e73b4f3ccaea 100644 --- a/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 7b2bb09551b5e68fda4d5785da965471754ec67c..4f3cb63c56df5a14c97e36daebaadd95d3fb523d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -9,6 +9,7 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 76a69d7f9586b3e29bd45cd1216b2d9b7e97b9b5..249f8de8fbe14c37f30a7cec8b1b0e9ba7867e4a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c index b2d3b2b13efd83f8f7e1ffb92d4abb8c42c3f84c..2cfbd780953d96f09a9a134d5bc19e388b7d5937 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index c3136dd8976ad341e93de272dd224efcc507b737..a94803ee93d93d77379c47472a7c11c4149d7ccd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8b65c094a8ad6d9fee11df2c91cbef4d0f70f087..77bca7e331a07166132f83b7a432936cd5d82aa7 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index a6eb053cadb0a18eecb74eacb5a824d1a0457739..61982e38a1d4a017873b95ce69e7da262bedaa0d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -20,6 +20,7 @@ #include #include +#include #include /* diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index cbd3b5d9958a01fef9ed9b3538497ea522fd00a9..3dff3d768d1ca8355ed1cd88267a5df3f21f452f 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -9,6 +9,7 @@ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 5d6c9f0861e1409f055b1bca2f133d0960b77e45..c882bd39eab07006120606bfe2152a0ea4e1dee2 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -16,6 +16,7 @@ #include #include +#include #include /* diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index efd232d342378072a64948cd367ab5d8f541e373..334bb5427432ddef2631b1ccb1f6f5563373a8b7 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -12,6 +12,7 @@ * CPU specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index f25a8674dea40a0a5a42dbad26cd7a8d91fc1690..17bd53dae847c46c5ed95d909b2db230c65836ed 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -4,7 +4,7 @@ * Texas Instruments Incorporated, */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c index 7f73f893458b72d1b1d8cf9ceb9ab34434711dfb..39217c5b2bf1d9ea6aa58a5fb80e5f27f597ec24 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c index 55dcc2fd78ca77ba60ca8d248993ce110821036e..1b3f36aebe11e47939c784aeb1ab8b410c567a36 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index b769c451105f02ae13e3dbd2682e961ef14cdf21..d7edefee23184ceaa907876f9685732ad4a8df66 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c index 5f7cc4a102d09b6cf6bcb24aa5096b83fdf43448..209ceca9a06e4b1c4058c2e2e69b2f13cdc1893e 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c index f3ff29bebe850272371639b3eff0201830bc3114..f2ba354c24f8d468f23c81d261177144ffe2ea48 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c index 87918059408c280e8f8eb2e2decf06b0aa8545b5..f604aec62fa6b52642b862ed77060cc272a64a26 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index b258fea45c8e4c90bca29c5929dd1d4232682d83..8f6260e7857ea401b60bb25fead33f31ff7ee576 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c index 55dcc2fd78ca77ba60ca8d248993ce110821036e..1b3f36aebe11e47939c784aeb1ab8b410c567a36 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bsc.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index 3f2e021a307ccf6050836444364757ad73e92bd8..26b673a5405e26e7e8d04d5ef954edf41df1d8e3 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c index 5f7cc4a102d09b6cf6bcb24aa5096b83fdf43448..209ceca9a06e4b1c4058c2e2e69b2f13cdc1893e 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c index f3ff29bebe850272371639b3eff0201830bc3114..f2ba354c24f8d468f23c81d261177144ffe2ea48 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-sdio.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c index 87918059408c280e8f8eb2e2decf06b0aa8545b5..f604aec62fa6b52642b862ed77060cc272a64a26 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include "clk-core.h" diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index 87e4337be4e04055f6fb30a40a0db3b955eae982..1491e5c88b20a4a016592f1f2a0c49e2165b13cd 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 617c8d68a2a92a5d4149dfd3ccea88b7ce7b76a9..63992fd870184bf723f50aaf086c2a4da599c3e9 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index c3be33124c6af1a80109bea6dba715d3094cfdbf..a3137752e8864124ec4fe5bdcb0282fec0625c9c 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index d11420d2fdd02a4934340523148d4c5a93c45e95..19ff4323528b81f37fd0d6ec5197a7e060a30015 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index b2c52db68dc9dc941a03fd0c66dba211861da8b2..0ac4e7ba8c80a18349a90e3f21a8d91f217bfb74 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -7,6 +7,7 @@ * CP15 specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index aa981faef001c3380d33ee4726321818c6613ba5..6259ffa510866024d26aa110c8494d86b719db02 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -14,6 +14,7 @@ * CPU specific code */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/exception_level.c b/arch/arm/cpu/armv7/exception_level.c index 7baade61b073e39f792f93f4f869aa424fc339e3..f6d25bb682c707b4aa8eb52fe5c9a9fd1a02a8a0 100644 --- a/arch/arm/cpu/armv7/exception_level.c +++ b/arch/arm/cpu/armv7/exception_level.c @@ -8,6 +8,7 @@ * secure mode before booting an operating system. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/armpll.c b/arch/arm/cpu/armv7/iproc-common/armpll.c index b345671b0a64f9d3f20f8b0c269cdcde4444179a..8c3a323f0654aacc943f482b47cdf517f73eda99 100644 --- a/arch/arm/cpu/armv7/iproc-common/armpll.c +++ b/arch/arm/cpu/armv7/iproc-common/armpll.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c index eca7e8b512b40619d3bc2324d7a43f42747ea973..896d2f9569427b5040514996c254d05afd49d0c0 100644 --- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include diff --git a/arch/arm/cpu/armv7/iproc-common/timer.c b/arch/arm/cpu/armv7/iproc-common/timer.c index b60d90f7e6a3cb5c5c18004c3b2db9e44dff821c..a4255a44c00138ba5e4746bad00b5a580349bf3a 100644 --- a/arch/arm/cpu/armv7/iproc-common/timer.c +++ b/arch/arm/cpu/armv7/iproc-common/timer.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index e885a85ce65c3f96bfab16646a855a5b1eb9bc65..4e1fe281201f195abcbc64cb98cbc306838af856 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 74a2dcbc116a909a2816a90155ab1764b5132093..c455969609f668cc1e9dcd265691384eaf9f9b58 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -4,6 +4,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 34eea22eb923ccece9ffeafe58b15611657de8ac..1c3d24bcad9400dd8f4d2147d418292bc22ae941 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c index 664eae532d5f9e933abbe900924abb62cbae4cf9..e31a4fb6c31bb439790c8e2159a2bd4de85542bb 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include "fsl_epu.h" diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index c1eadb34523fc58a025b2ac8eb85efb2c78ef06a..f74d819ea1ea6c2f64f410b9be88075aaccc3839 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c index 3032e266c5d4ec60c68ff07e12e140839da8263a..8c030be8b36f72daf9a7bc22a77c7928699eb174 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 7ff59edd452ee4bf1b4b28060b7e08eef3a9d580..84d4ea3a8f4a0d63b7ec78fbf8172893342c3639 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 374de92d026c8697b03ce2a34fdcff7f8e8f4c4d..a19496862359aa1a1d8b8209e02a268ccdec5037 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include u32 spl_boot_device(void) diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index 6f32ced5aec346f70c913f2527961ccf4dc546f6..c6126b10c355bca21ab7f92a979499110886a4e9 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c index 2d83e4c721d25603bf4ec55391a767d23d06504c..1d31c63e5fde29b1e96a49c6f7645b7191d80f64 100644 --- a/arch/arm/cpu/armv7/mpu_v7r.c +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -6,6 +6,7 @@ * Lokesh Vutla */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index 4331dde7643d529307157d1e30ee2b0502ff0687..fb2920950d426508f9ae61ce2172c425c1e97058 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -3,6 +3,7 @@ * Copyright (C) 2009 Samsung Electronics * Minkyu Kang */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 986b585b70e92a0e8a9a7af015bf68f7677fc63a..5068327d3c5fdb7c75ca70986e58156a5cddc450 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -5,7 +5,7 @@ * Donghwa Lee */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c index c0035fb18ebb64d739110106f750f79efd3809ba..0fc170936ae442be71b7a7966ba4147af285e0db 100644 --- a/arch/arm/cpu/armv7/s5p-common/sromc.c +++ b/arch/arm/cpu/armv7/s5p-common/sromc.c @@ -4,7 +4,7 @@ * Naveen Krishna Ch */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 12994ecc843ee0b6dbc205f6bd4dd38116c7b1b8..9d981cce145d72fa3a754add7ecadebc5133b2ce 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -6,6 +6,7 @@ * Minkyu Kang */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 27ffb450378f5b3edf9d66ad8e4ef093551fe188..8febfe5276696132929b3d53c769f5741f66ba03 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -4,6 +4,7 @@ * Hyunseok, Jung */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 4c30f3294b7ac5b286419e22d612cb0b0fdcfec9..5cb8cfa6cf3fc0035a5a25651f48de8dba2c3986 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -7,6 +7,7 @@ * which was based on code by Carl van Schaik . */ #include +#include #include #include diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c index bc25719c9c465deed97c7f5e291f5c282b86af75..28ff6a1b7c23071d6124596fb5dc243a9beda199 100644 --- a/arch/arm/cpu/armv7/sunxi/sram.c +++ b/arch/arm/cpu/armv7/sunxi/sram.c @@ -9,6 +9,7 @@ * SRAM init for older sunxi SoCs. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c index f0eda1ca98d0cf25ae0de98669509b4f9309d9cf..7e29636972d992d3c81c816af71da086943ff54c 100644 --- a/arch/arm/cpu/armv7/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c @@ -7,6 +7,7 @@ * Syed Mohammed Khasim */ +#include #include /************************************************************ diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index e61ad7b96e901fac127e8284bb1135c457bf54a3..c23ddc12b456979aa57c9e6ca5fcaf7bb4296b4e 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -3,6 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/vf610/timer.c b/arch/arm/cpu/armv7/vf610/timer.c index 7bae0b5574af3a742510af1437249722bd017b8a..a9c1a8fcebc14f43d573f52ce653eaa24e21ce58 100644 --- a/arch/arm/cpu/armv7/vf610/timer.c +++ b/arch/arm/cpu/armv7/vf610/timer.c @@ -3,6 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index 5dc7ed5e2707a372e737a37917566233ca8ac561..c0422485ba4eff3efa8ee14668ff3af8fc0414f9 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 811499367d40e691b27b8b3c8f636368af94d05b..5ffeca13d91341d5e2b40f03f44b0076a7b990bb 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -8,6 +8,7 @@ * needed to enable ARMv7 virtualization for current hypervisors */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index b6d08b7aad737c93958aaf4534f6868ba7f57dbb..d1aecf6a85cfdfebf48c832f65c0952a971e8860 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -4,6 +4,7 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index b4440d3f3f8481d5a94aca819b07a66cb2fc5ca3..65427b5312bea62a9a08a02d3b633c3fdb55bcee 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -7,6 +7,7 @@ * Kamil Lulko, */ +#include #include #include #include diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index d8fa4f0c707a81c04ce775d34f1131e555e40d59..c30af4ff7a282f37baa429ed59ff334975555f25 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -21,7 +21,7 @@ * using CFG_SYS_HZ_CLOCK. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index d4c64f2d60d9aeef5fa2ac51acf10222ad0cc8c4..57d06f0575dcfe95b7e9c976de741ea25caf6572 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -7,6 +7,7 @@ * Alexander Graf */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 97667e607a836e2c5847a550c5974948f4a6c825..9bfe3815e51a0b6d4c1f34cb99edbb6331d27e78 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -3,6 +3,7 @@ * Copyright 2016 NXP Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index d568efa427abdbf06a06c26584ecc49e994c420a..3c7f36ad8d89d7b215523cf60542fc67af7f5aac 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -10,6 +10,7 @@ * Gary Jennejohn, DENX Software Engineering, */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c index 85c78f55789dbd2cfb774eafef86527f25ef3bb1..b11936548fb3ed08faa577b4dd4dca598c7bc9e3 100644 --- a/arch/arm/cpu/armv8/exception_level.c +++ b/arch/arm/cpu/armv8/exception_level.c @@ -8,6 +8,7 @@ * level before booting an operating system. */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2dbfdd08a02f65e415dc04758e1d0446cf6413a..12d31184ad91bfa58c5eb2ddf58f7d0375afc935 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ca6be3626fbeeaee5e24342724164e60bcf3c9a6..22ce6992165bdf9b432aaf02b047304f3d6b9682 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -4,7 +4,7 @@ * Copyright 2020-2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 78961d8089e441ee03c17c82cc3bfd124650acc5..b1bb29bcaf55ddbf8809f44f3bfc634d5d0e40f6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -3,12 +3,11 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include #include -#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9a24d4b303138b1a0cb921522a18eddaecbaf310..4455eb1726dc18d857221500097147f8b89223fa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index b768790437fd50018f211f5841ecb0248103aa00..fbd5fd7d433bd0f288f6e1347249944f83146796 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -4,7 +4,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 452246e0e67ff75963e419eb7b3ece700d5654bc..137778dc136b2ec48d447d85285bf6217bf232c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -6,7 +6,7 @@ * Derived from arch/power/cpu/mpc85xx/speed.c */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 04ffefafbf737a18a70836a868509d292b2a465b..c22e73253c3c663210b7a56fc8a6565646923dd5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -3,7 +3,7 @@ * Copyright 2018 NXP */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c index c0e5455507a41cbed4288b8e0d3001f44083eb8f..8d7beca7db38ae7493183e66447893bf0c3760f1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index d48baa63816fb1be3e2e26c990c541c38af5e90f..86a49b152e44fab1ce6aa195f76c386cb7f77bc4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -3,9 +3,9 @@ * Copyright 2019 NXP */ +#include #include #include -#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index 1b4eab3613e567e1214d9353154a6426b43a0b97..80d2910f679f2f6cea00ad3b07be2b5730eb38f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -3,8 +3,7 @@ * Copyright 2019 NXP */ -#include -#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index ec80e42055d9ab280b8040103dbdb2f72a4ecac6..e3c3fc6bfb55f9a60ffb83f76b9d2b1eaebef778 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -3,12 +3,11 @@ * Copyright 2018 NXP */ -#include +#include #include #include #include #include -#include #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c index 1911ca1a175bb89cba44b09e6c8e828385b24dd7..6c5e52ebaa698db3bb412571aa08c6e09a922411 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index a73dd316f8d0fb074056671e932930c1e856f399..333d7e2fa21aebc35460d181c0db38c1cddb762e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -3,11 +3,10 @@ * Copyright 2018 NXP */ -#include +#include #include #include #include -#include #ifdef CONFIG_SYS_DPAA_QBMAN struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 26ca4ca10f3d4913aa67fe88d371449588918be3..9347e516bf695c4bca0f61324aa5a3db004a55a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 3a076ca04f6ea3d3a1cda4dfe101d7cf0cb00873..23743ae10cffd6a824e412602c489efdcbad7542 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -3,11 +3,10 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include -#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 154b727392e12e63200fccbd6b94a16ce2f52491..fe667f06c3956f1e96c81ad8ff972f00763905cd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2017-2019 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 5088c8ebb7ff5b1499be9e7c7c17a64fcfe6b173..7997422840f298bb967bc308adf15ecaec3704e5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c index c320e835c996fc00c91da832f96d64b542b9af1e..e6403b7952632d23ca3606583b3eeebc9c364313 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -3,11 +3,10 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include -#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c index df9329df77e16c9364fbb2eab29625e1964f539f..3a0ed1fa550c4c15db7c4892e3fc1ec173973160 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -3,11 +3,10 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include -#include struct icid_id_table icid_tbl[] = { SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c index 43f0e8c87ba917880d1ad81abea47e9d6e90cfbe..5941d90e036fdfb82cda7e5ee94b1972af68dc18 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -3,7 +3,7 @@ * Copyright 2018, 2020 NXP */ -#include +#include #include struct serdes_config { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index db913208b9e9c287fe6f6269630be570abc2e2b9..ce0c46ad0d4ea32985d683c7071aa7b98c00a441 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d85a630f8a3cb722034b131b94529688af4f55fc..4c61d28c20f004960b530815aecf8c1eac58895b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -4,7 +4,7 @@ * Copyright 2019-2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index a739ff2da581f9d6a931293a80b676e71111d41c..232adfa843a2cce31d95c282e295aa3dc2a368a4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -3,7 +3,7 @@ * Copyright 2014-2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 1de7ec596fc7cbbc3e78a241f163bc0a4fcad6b6..e18b5c81875e7af60601eaafa084968249f41d49 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -4,6 +4,7 @@ * David Feng */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/hisilicon/pinmux.c b/arch/arm/cpu/armv8/hisilicon/pinmux.c index d7a5a7926102543ef31b5f280eaeb8e5a297b7aa..e14057c0a47c372675967a7414513e9be1d63446 100644 --- a/arch/arm/cpu/armv8/hisilicon/pinmux.c +++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c @@ -4,6 +4,7 @@ * Peter Griffin */ +#include #include #include #include diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 44372cbe4a1c631d35bbc654f92d8e5f74670ae4..c0e8726346f584636a3c0f14f6124f48cefae8ac 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -3,7 +3,7 @@ * Copyright 2016 NXP Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/cpu/armv8/sha1_ce_glue.c b/arch/arm/cpu/armv8/sha1_ce_glue.c index c88b4dc66e1f5a0fbdaa42ee7b548dd26ac1a1d6..780b119a90bf47cb1a77f4cc881ca2e3e0823ded 100644 --- a/arch/arm/cpu/armv8/sha1_ce_glue.c +++ b/arch/arm/cpu/armv8/sha1_ce_glue.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Linaro Ltd */ +#include #include extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/sha256_ce_glue.c b/arch/arm/cpu/armv8/sha256_ce_glue.c index d5d2b4f4ac7e4c0fdae40c28822648d48b19efae..67dd796c122d267709b0022abb924c881aa0fac2 100644 --- a/arch/arm/cpu/armv8/sha256_ce_glue.c +++ b/arch/arm/cpu/armv8/sha256_ce_glue.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Linaro Ltd */ +#include #include extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src, diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c index 485294b88d0ac5516f58fb616ca59eebe30ef022..42a0962fdcda111cb47b9628e7af9dfe60eff19c 100644 --- a/arch/arm/cpu/armv8/spin_table.c +++ b/arch/arm/cpu/armv8/spin_table.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 259b49ff3640e1e711b072a85e9dc41ffc66990a..8f1231c86ebb20da3937b878b606fc2e355618c9 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include char __data_save_start[0] __section(".__data_save_start"); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 60660f24d9426de68c3199c6243c4962b2dfcb61..f7032f1e17550ca730176410acbf6f378a8b50d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,7 +41,6 @@ dtb-$(CONFIG_ARCH_APPLE) += \ t8103-j457.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ - da850-evm.dtb \ da850-lcdk.dtb \ da850-lego-ev3.dtb @@ -92,100 +91,12 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-veyron-speedy.dtb \ rk3288-vyasa.dtb -dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - rk3308-evb.dtb \ - rk3308-roc-cc.dtb \ - rk3308-rock-pi-s.dtb - -dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2c-plus.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ - rk3328-orangepi-r1-plus-lts.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion-haikou.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ -dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-evb.dtb \ - rk3399-eaidk-610.dtb \ - rk3399-ficus.dtb \ - rk3399-firefly.dtb \ - rk3399-gru-bob.dtb \ - rk3399-gru-kevin.dtb \ - rk3399-khadas-edge.dtb \ - rk3399-khadas-edge-captain.dtb \ - rk3399-khadas-edge-v.dtb \ - rk3399-leez-p710.dtb \ - rk3399-nanopc-t4.dtb \ - rk3399-nanopi-m4.dtb \ - rk3399-nanopi-m4-2gb.dtb \ - rk3399-nanopi-m4b.dtb \ - rk3399-nanopi-neo4.dtb \ - rk3399-nanopi-r4s.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-pinephone-pro.dtb \ - rk3399-puma-haikou.dtb \ - rk3399-roc-pc.dtb \ - rk3399-roc-pc-mezzanine.dtb \ - rk3399-rock-4c-plus.dtb \ - rk3399-rock-4se.dtb \ - rk3399-rock-pi-4a.dtb \ - rk3399-rock-pi-4c.dtb \ - rk3399-rock960.dtb \ - rk3399-rockpro64.dtb \ - rk3399pro-rock-pi-n10.dtb - -dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3566-anbernic-rgxx3.dtb \ - rk3566-pinetab2-v0.1.dtb \ - rk3566-pinetab2-v2.0.dtb \ - rk3566-quartz64-a.dtb \ - rk3566-quartz64-b.dtb \ - rk3566-radxa-cm3-io.dtb \ - rk3566-soquartz-blade.dtb \ - rk3566-soquartz-cm4.dtb \ - rk3566-soquartz-model-a.dtb \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ - rk3568-generic.dtb \ - rk3568-lubancat-2.dtb \ - rk3568-nanopi-r5c.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3568-odroid-m1.dtb \ - rk3568-radxa-e25.dtb \ - rk3568-rock-3a.dtb - -dtb-$(CONFIG_ROCKCHIP_RK3588) += \ - rk3588s-coolpi-4b.dtb \ - rk3588-coolpi-cm5-evb.dtb \ - rk3588-edgeble-neu6a-io.dtb \ - rk3588-edgeble-neu6b-io.dtb \ - rk3588-evb1-v10.dtb \ - rk3588-generic.dtb \ - rk3588-jaguar.dtb \ - rk3588-nanopc-t6.dtb \ - rk3588s-orangepi-5.dtb \ - rk3588-orangepi-5-plus.dtb \ - rk3588-quartzpro64.dtb \ - rk3588s-rock-5a.dtb \ - rk3588-rock-5b.dtb \ - rk3588-toybrick-x0.dtb \ - rk3588-turing-rk1.dtb - -dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ - rv1108-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RV1126) += \ rv1126-edgeble-neu2-io.dtb @@ -483,7 +394,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am437x-idk-evm.dtb \ am4372-generic.dtb \ am437x-cm-t43.dtb -dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ @@ -1048,41 +958,7 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ -dtb-$(CONFIG_RCAR_GEN2) += \ - r8a7790-lager.dtb \ - r8a7790-stout.dtb \ - r8a7791-koelsch.dtb \ - r8a7791-porter.dtb \ - r8a7792-blanche.dtb \ - r8a7793-gose.dtb \ - r8a7794-alt.dtb \ - r8a7794-silk.dtb - -dtb-$(CONFIG_RCAR_GEN3) += \ - r8a774a1-beacon-rzg2m-kit.dtb \ - r8a774b1-beacon-rzg2n-kit.dtb \ - r8a774e1-beacon-rzg2h-kit.dtb \ - r8a774a1-hihope-rzg2m.dtb \ - r8a774b1-hihope-rzg2n.dtb \ - r8a774c0-ek874.dtb \ - r8a774e1-hihope-rzg2h.dtb \ - r8a77951-ulcb.dtb \ - r8a77951-salvator-x.dtb \ - r8a77960-ulcb.dtb \ - r8a77960-salvator-x.dtb \ - r8a77965-ulcb.dtb \ - r8a77965-salvator-x.dtb \ - r8a77970-eagle.dtb \ - r8a77970-v3msk.dtb \ - r8a77980-condor.dtb \ - r8a77980-v3hsk.dtb \ - r8a77990-ebisu.dtb \ - r8a77995-draak.dtb - dtb-$(CONFIG_RCAR_GEN4) += \ - r8a779a0-falcon.dtb \ - r8a779f0-spider.dtb \ - r8a779g0-white-hawk.dtb \ r8a779h0-gray-hawk.dtb dtb-$(CONFIG_TARGET_RZG2L) += \ @@ -1143,12 +1019,6 @@ dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb -dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ - logicpd-som-lv-35xx-devkit.dtb \ - logicpd-som-lv-37xx-devkit.dtb \ - logicpd-torpedo-35xx-devkit.dtb \ - logicpd-torpedo-37xx-devkit.dtb - dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ omap3-evm-37xx.dtb \ omap3-evm.dtb diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts deleted file mode 100644 index d21bb2ccd0f500cce3db499effb1bce2989897b8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/am3517-evm.dts +++ /dev/null @@ -1,339 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am3517.dtsi" -#include "am3517-som.dtsi" -#include "am3517-evm-ui.dtsi" -#include - -/ { - model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; - compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - - aliases { - display0 = &lcd0; - }; - - chosen { - stdout-path = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - button-user { - label = "User Push Button"; - linux,code = ; - gpios = <&tca6416 5 GPIO_ACTIVE_LOW>; - }; - - switch-1 { - label = "User Switch 1"; - linux,code = ; - gpios = <&tca6416 8 GPIO_ACTIVE_LOW>; - }; - - switch-2 { - label = "User Switch 2"; - linux,code = ; - gpios = <&tca6416 9 GPIO_ACTIVE_LOW>; - }; - - switch-3 { - label = "User Switch 3"; - linux,code = ; - gpios = <&tca6416 10 GPIO_ACTIVE_LOW>; - }; - - switch-4 { - label = "User Switch 4"; - linux,code = ; - gpios = <&tca6416 11 GPIO_ACTIVE_LOW>; - }; - - switch-5 { - label = "User Switch 5"; - linux,code = ; - gpios = <&tca6416 12 GPIO_ACTIVE_LOW>; - }; - - switch-6 { - label = "User Switch 6"; - linux,code = ; - gpios = <&tca6416 13 GPIO_ACTIVE_LOW>; - }; - - switch-7 { - label = "User Switch 7"; - linux,code = ; - gpios = <&tca6416 14 GPIO_ACTIVE_LOW>; - }; - - switch-8 { - label = "User Switch 8"; - linux,code = ; - gpios = <&tca6416 15 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - - user_led_1 { - label = "am3517evm:green:user_led_1"; - gpios = <&tca6416 7 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_2 { - label = "am3517evm:green:user_led_2"; - gpios = <&tca6416 6 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led_3 { - label = "am3517evm:green:user_led_3"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; /* SD/MMC card activity */ - }; - - user_led_4 { - label = "am3517evm:green:user_led_4"; - gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - lcd0: display@0 { - /* This isn't the exact LCD, but the timings meet spec */ - /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - backlight = <&bl>; - enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ - vcc-supply = <&vdd_io_reg>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - power-supply = <&vdd_io_reg>; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm11 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ - }; - - pwm11: pwm-11 { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer11>; - #pwm-cells = <3>; - ti,clock-source = <0x01>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ - #phy-cells = <0>; - }; -}; - -&davinci_emac { - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins>; - status = "okay"; -}; - -&davinci_mdio { - status = "okay"; -}; - -&dss { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins>; - - vdds_dsi-supply = <&vdd_io_reg>; - vdda_video-supply = <&vdd_io_reg>; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - /* User DIP swithes [1:8] / User LEDS [1:2] */ - tca6416: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vdd_io_reg>; - }; -}; - -&i2c3 { - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc_fixed>; - bus-width = <4>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */ -}; - -&mmc3 { - status = "disabled"; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>; - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&omap3_pmx_core { - - ethernet_pins: pinmux_ethernet_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ - OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ - OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ - OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ - OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ - OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ - OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ - OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ - OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ - OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 */ - OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu1.gpio_31 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */ - OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1) /* mcspi2_cs0.gpt11_pwm */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4) /* mcspi2_cs1.gpio_182 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; - - hsusb1_rst_pins: pinmux_hsusb1_rst_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; -}; - -&omap3_pmx_core2 { - - hsusb1_pins: pinmux_hsusb1_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - >; - }; -}; diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi deleted file mode 100644 index 8b669e2eafec4813fa8294c7de5a8d079b30189c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/am3517-som.dtsi +++ /dev/null @@ -1,234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Derald D. Woods - * - * Based on am3517-evm.dts - */ - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vdd_core_reg>; - }; - }; - - wl12xx_buffer: wl12xx_buf { - compatible = "regulator-fixed"; - regulator-name = "wl1271_buf"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_buffer_pins>; - gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */ - regulator-always-on; - vin-supply = <&vdd_1v8_reg>; - }; - - wl12xx_vmmc2: wl12xx_vmmc2 { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_wkup_pins>; - gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */ - startup-delay-us = <70000>; - enable-active-high; - regulator-always-on; - vin-supply = <&wl12xx_buffer>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name = "micron,mt29f4g16abchch"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - - s35390a: s35390a@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - - pinctrl-names = "default"; - pinctrl-0 = <&rtc_pins>; - interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */ - }; - - tps: tps65023@48 { - compatible = "ti,tps65023"; - reg = <0x48>; - - regulators { - vdd_core_reg: VDCDC1 { - regulator-name = "vdd_core"; - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vdd_io_reg: VDCDC2 { - regulator-name = "vdd_io"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_1v8_reg: VDCDC3 { - regulator-name = "vdd_1v8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb18_reg: LDO1 { - regulator-name = "vdd_usb18"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_usb33_reg: LDO2 { - regulator-name = "vdd_usb33"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - touchscreen: tsc2004@4b { - compatible = "ti,tsc2004"; - reg = <0x4b>; - - vio-supply = <&vdd_io_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <480>; - touchscreen-size-y = <272>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc2 { - interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>; - - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&wl12xx_vmmc2>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - bluetooth { - compatible = "ti,wl1271-st"; - enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */ - max-speed = <3000000>; - }; -}; - -&omap3_pmx_core { - - wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */ - OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */ - OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */ - OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */ - OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */ - OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */ - OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */ - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */ - >; - }; - - rtc_pins: pinmux_rtc_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */ - OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */ - >; - }; -}; - -&omap3_pmx_wkup { - - wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi deleted file mode 100644 index 2633fae14b3012e0081cb6183eea280602073b7a..0000000000000000000000000000000000000000 --- a/arch/arm/dts/am3517.dtsi +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for am3517 SoC - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "omap3.dtsi" - -/ { - aliases { - serial3 = &uart4; - can = &hecc; - }; - - ocp@68000000 { - am35x_otg_hs: am35x_otg_hs@5c040000 { - compatible = "ti,omap3-musb"; - ti,hwmods = "am35x_otg_hs"; - status = "disabled"; - reg = <0x5c040000 0x1000>; - interrupts = <71>; - interrupt-names = "mc"; - }; - - davinci_emac: ethernet@5c000000 { - compatible = "ti,am3517-emac"; - ti,hwmods = "davinci_emac"; - status = "disabled"; - reg = <0x5c000000 0x30000>; - interrupts = <67 68 69 70>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0x10000>; - ti,davinci-ctrl-mod-reg-offset = <0>; - ti,davinci-ctrl-ram-offset = <0x20000>; - ti,davinci-ctrl-ram-size = <0x2000>; - ti,davinci-rmii-en = /bits/ 8 <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - clocks = <&emac_ick>; - clock-names = "ick"; - }; - - davinci_mdio: mdio@5c030000 { - compatible = "ti,davinci_mdio"; - ti,hwmods = "davinci_mdio"; - status = "disabled"; - reg = <0x5c030000 0x1000>; - bus_freq = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&emac_fck>; - clock-names = "fck"; - }; - - uart4: serial@4809e000 { - compatible = "ti,omap3-uart"; - ti,hwmods = "uart4"; - status = "disabled"; - reg = <0x4809e000 0x400>; - interrupts = <84>; - dmas = <&sdma 55 &sdma 54>; - dma-names = "tx", "rx"; - clock-frequency = <48000000>; - }; - - omap3_pmx_core2: pinmux@480025d8 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x480025d8 0x24>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - hecc: can@5c050000 { - compatible = "ti,am3517-hecc"; - status = "disabled"; - reg = <0x5c050000 0x80>, - <0x5c053000 0x180>, - <0x5c052000 0x200>; - reg-names = "hecc", "hecc-ram", "mbx"; - interrupts = <24>; - clocks = <&hecc_ck>; - }; - }; -}; - -/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ -&usb_otg_hs { - status = "disabled"; -}; - -&iva { - status = "disabled"; -}; - -&mailbox { - status = "disabled"; -}; - -&mmu_isp { - status = "disabled"; -}; - -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/dts/am35xx-clocks.dtsi b/arch/arm/dts/am35xx-clocks.dtsi deleted file mode 100644 index 220d0a52797e1140f90de287846267a6a50ac2d5..0000000000000000000000000000000000000000 --- a/arch/arm/dts/am35xx-clocks.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - emac_ick: emac_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <1>; - }; - - emac_fck: emac_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&rmii_ck>; - reg = <0x032c>; - ti,bit-shift = <9>; - }; - - vpfe_ick: vpfe_ick@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <2>; - }; - - vpfe_fck: vpfe_fck@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&pclk_ck>; - reg = <0x032c>; - ti,bit-shift = <10>; - }; - - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&ipss_ick>; - reg = <0x032c>; - ti,bit-shift = <0>; - }; - - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <8>; - }; - - hecc_ck: hecc_ck@32c { - #clock-cells = <0>; - compatible = "ti,am35xx-gate-clock"; - clocks = <&sys_ck>; - reg = <0x032c>; - ti,bit-shift = <3>; - }; -}; -&cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; - - rmii_ck: rmii_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - pclk_ck: pclk_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; - - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, - <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, - <&hecc_ck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, - <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, - <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; - }; -}; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts deleted file mode 100644 index 378af9f3445749e86d39d10754d0b8ae4fba0126..0000000000000000000000000000000000000000 --- a/arch/arm/dts/da850-evm.dts +++ /dev/null @@ -1,453 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree for DA850 EVM board - * - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; -#include "da850.dtsi" -#include - -/ { - compatible = "ti,da850-evm", "ti,da850"; - model = "DA850/AM1808/OMAP-L138 EVM"; - - chosen { - stdout-path = &serial2; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - ethernet0 = ð0; - spi0 = &spi1; - }; - - backlight: backlight-pwm { - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - power-supply = <&backlight_lcd>; - compatible = "pwm-backlight"; - /* - * The PWM here corresponds to production hardware. The - * schematic needs to be 1015171 (15 March 2010), Rev A - * or newer. - */ - pwms = <&ecap2 0 50000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; - default-brightness-level = <7>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, change the status below to 'disabled' then - * then change the status of the vpif below to 'okay' - */ - status = "okay"; - enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */ - - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <16>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - native-mode = <&timing0>; - timing0: 480x272 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - baseboard_3v3: fixedregulator-3v3 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - baseboard_1v8: fixedregulator-1v8 { - /* TPS73701DCQ */ - compatible = "regulator-fixed"; - regulator-name = "baseboard_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vbat>; - regulator-always-on; - regulator-boot-on; - }; - - backlight_lcd: backlight-regulator { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */ - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "DA850-OMAPL138 EVM"; - simple-audio-card,widgets = - "Line", "Line In", - "Line", "Line Out"; - simple-audio-card,routing = - "LINE1L", "Line In", - "LINE1R", "Line In", - "Line Out", "LLOUT", - "Line Out", "RLOUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&link0_codec>; - simple-audio-card,frame-master = <&link0_codec>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - system-clock-frequency = <24576000>; - }; - - link0_codec: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24576000>; - }; - }; -}; - -&ecap2 { - status = "okay"; -}; - -&ref_clk { - clock-frequency = <24000000>; -}; - -&pmx_core { - status = "okay"; - - mcasp0_pins: pinmux_mcasp0_pins { - pinctrl-single,bits = < - /* - * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, - * AFSR, AMUTE - */ - 0x00 0x11111111 0xffffffff - /* AXR11, AXR12 */ - 0x04 0x00011000 0x000ff000 - >; - }; - nand_pins: nand_pins { - pinctrl-single,bits = < - /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ - 0x1c 0x10110110 0xf0ff0ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; -}; - -&sata { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&rtc0 { - status = "okay"; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - tps: tps@48 { - reg = <0x48>; - }; - tlv320aic3106: tlv320aic3106@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x18>; - status = "okay"; - - /* Regulators */ - IOVDD-supply = <&vdcdc2_reg>; - AVDD-supply = <&baseboard_3v3>; - DRVDD-supply = <&baseboard_3v3>; - DVDD-supply = <&baseboard_1v8>; - }; - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - tca6416_bb: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&wdt { - status = "okay"; -}; - -&mmc0 { - max-frequency = <50000000>; - bus-width = <4>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64"; - spi-max-frequency = <30000000>; - m25p,fast-read; - reg = <0>; - partition@0 { - label = "U-Boot-SPL"; - reg = <0x00000000 0x00010000>; - read-only; - }; - partition@1 { - label = "U-Boot"; - reg = <0x00010000 0x00080000>; - read-only; - }; - partition@2 { - label = "U-Boot-Env"; - reg = <0x00090000 0x00010000>; - read-only; - }; - partition@3 { - label = "Kernel"; - reg = <0x000a0000 0x00280000>; - }; - partition@4 { - label = "Filesystem"; - reg = <0x00320000 0x00400000>; - }; - partition@5 { - label = "MAC-Address"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - bus_freq = <2200000>; -}; - -ð0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mii_pins>; -}; - -&gpio { - status = "okay"; -}; - -/include/ "tps6507x.dtsi" - -&tps { - vdcdc1_2-supply = <&vbat>; - vdcdc3-supply = <&vbat>; - vldo1_2-supply = <&vbat>; - - regulators { - vdcdc1_reg: regulator@0 { - regulator-name = "VDCDC1_3.3V"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - }; - - vdcdc2_reg: regulator@1 { - regulator-name = "VDCDC2_3.3V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3450000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - vdcdc3_reg: regulator@2 { - regulator-name = "VDCDC3_1.2V"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - ti,defdcdc_default = <1>; - }; - - ldo1_reg: regulator@3 { - regulator-name = "LDO1_1.8V"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: regulator@4 { - regulator-name = "LDO2_1.2V"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1320000>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 0 0 - 0 0 0 0 - 0 0 0 1 - 2 0 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&edma0 { - ti,edma-reserved-slot-ranges = <32 50>; -}; - -&edma1 { - ti,edma-reserved-slot-ranges = <32 90>; -}; - -&aemif { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - status = "okay"; - cs3 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <3>; - - nand@2000000,0 { - compatible = "ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x02000000 0x02000000 - 1 0x00000000 0x00008000>; - - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&vpif { - pinctrl-names = "default"; - pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; - /* - * The vpif and the LCD are mutually exclusive. - * To enable VPIF, disable the ti,tilcdc,panel then - * change the status below to 'okay' - */ - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index e8020fec2dc35ba88a25a25d0828ea323a672c88..06db86598761e1b69947d284e7a0be2a6ee1779b 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -47,52 +47,6 @@ config = "pm-cfg_j7200.yaml"; }; -&binman { - tiboot3-j7200-hs-evm.bin { - filename = "tiboot3-j7200-hs-evm.bin"; - ti-secure-rom { - content = <&u_boot_spl_sr1>, <&ti_fs_enc_sr1>, <&combined_tifs_cfg_sr1>, - <&combined_dm_cfg_sr1>, <&sysfw_inner_cert_sr1>; - combined; - dm-data; - core-opts = <2>; - sysfw-inner-cert; - keyfile = "custMpk.pem"; - sw-rev = <1>; - content-sbl = <&u_boot_spl_sr1>; - content-sysfw = <&ti_fs_enc_sr1>; - content-sysfw-data = <&combined_tifs_cfg_sr1>; - content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; - content-dm-data = <&combined_dm_cfg_sr1>; - load = <0x41c00000>; - load-sysfw = <0x40000>; - load-sysfw-data = <0x7f000>; - load-dm-data = <0x41c80000>; - }; - u_boot_spl_sr1: u-boot-spl { - no-expanded; - }; - ti_fs_enc_sr1: ti-fs-enc.bin { - filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; - type = "blob-ext"; - optional; - }; - combined_tifs_cfg_sr1: combined-tifs-cfg.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - sysfw_inner_cert_sr1: sysfw-inner-cert { - filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; - type = "blob-ext"; - optional; - }; - combined_dm_cfg_sr1: combined-dm-cfg.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - &binman { tiboot3-j7200_sr2-hs-evm.bin { filename = "tiboot3-j7200_sr2-hs-evm.bin"; @@ -138,53 +92,6 @@ }; }; -&binman { - tiboot3-j7200-hs-fs-evm.bin { - filename = "tiboot3-j7200-hs-fs-evm.bin"; - ti-secure-rom { - content = <&u_boot_spl_fs_sr1>, <&ti_fs_enc_fs_sr1>, - <&combined_tifs_cfg_fs_sr1>, <&combined_dm_cfg_fs_sr1>, - <&sysfw_inner_cert_fs_sr1>; - combined; - dm-data; - core-opts = <2>; - sysfw-inner-cert; - keyfile = "custMpk.pem"; - sw-rev = <1>; - content-sbl = <&u_boot_spl_fs_sr1>; - content-sysfw = <&ti_fs_enc_fs_sr1>; - content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; - content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; - content-dm-data = <&combined_dm_cfg_fs_sr1>; - load = <0x41c00000>; - load-sysfw = <0x40000>; - load-sysfw-data = <0x7f000>; - load-dm-data = <0x41c80000>; - }; - u_boot_spl_fs_sr1: u-boot-spl { - no-expanded; - }; - ti_fs_enc_fs_sr1: ti-fs-enc.bin { - filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; - type = "blob-ext"; - optional; - }; - combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - sysfw_inner_cert_fs_sr1: sysfw-inner-cert { - filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; - type = "blob-ext"; - optional; - }; - combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - &binman { tiboot3-j7200_sr2-hs-fs-evm.bin { filename = "tiboot3-j7200_sr2-hs-fs-evm.bin"; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 1514d897634a6f5995d5e39309ee7174f0ed2f20..75a6e9599b9a64f6367e5ba78889670d21005e02 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-binman.dtsi" @@ -129,94 +129,6 @@ }; }; -&binman { - tiboot3-j721e_sr1_1-hs-fs-evm.bin { - filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin"; - ti-secure-rom { - content = <&u_boot_spl_fs_sr1_1>; - core = "public"; - core-opts = <2>; - load = ; - keyfile = "custMpk.pem"; - }; - u_boot_spl_fs_sr1_1: u-boot-spl { - no-expanded; - }; - }; - sysfw_fs_sr1_1 { - filename = "sysfw.bin_fs_sr1_1"; - ti-fs-cert-fs.bin { - filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; - type = "blob-ext"; - optional; - }; - ti-fs-firmware-j721e-hs-fs-enc.bin { - filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; - type = "blob-ext"; - optional; - }; - }; - itb_fs_sr1_1 { - filename = "sysfw-j721e_sr1_1-hs-fs-evm.itb"; - fit { - description = "SYSFW and Config fragments"; - #address-cells = <1>; - images { - sysfw.bin { - description = "sysfw"; - type = "firmware"; - arch = "arm"; - compression = "none"; - blob-ext { - filename = "sysfw.bin_fs_sr1_1"; - }; - }; - board-cfg.bin { - description = "board-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - board-cfg { - filename = "board-cfg.bin"; - type = "blob-ext"; - }; - - }; - pm-cfg.bin { - description = "pm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - pm-cfg { - filename = "pm-cfg.bin"; - type = "blob-ext"; - }; - }; - rm-cfg.bin { - description = "rm-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - rm-cfg { - filename = "rm-cfg.bin"; - type = "blob-ext"; - }; - }; - sec-cfg.bin { - description = "sec-cfg"; - type = "firmware"; - arch = "arm"; - compression = "none"; - sec-cfg { - filename = "sec-cfg.bin"; - type = "blob-ext"; - }; - }; - }; - }; - }; -}; - &binman { tiboot3-j721e_sr2-hs-fs-evm.bin { filename = "tiboot3-j721e_sr2-hs-fs-evm.bin"; diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi index 6f11852a33feb9297e3a614c371ab72a006e034d..d77fa38746fba1eb6ec4f20b045437bd438ae9bb 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi @@ -14,6 +14,8 @@ aliases { /delete-property/ serial1; /delete-property/ serial2; + /delete-property/ mmc1; + /delete-property/ mmc2; }; ethernet@08000000 { diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts deleted file mode 100644 index f690bc83bf53477d577595e7098922875f916a35..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 6f11852a33feb9297e3a614c371ab72a006e034d..d77fa38746fba1eb6ec4f20b045437bd438ae9bb 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -14,6 +14,8 @@ aliases { /delete-property/ serial1; /delete-property/ serial2; + /delete-property/ mmc1; + /delete-property/ mmc2; }; ethernet@08000000 { diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts deleted file mode 100644 index e28e9625bebb34aeac743a66fa9715004b081405..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-som-lv.dtsi" -#include "logicpd-som-lv-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; -}; - -&omap3_pmx_core2 { - - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi deleted file mode 100644 index 7d0468a237818ceca1ef0ab9c842907815d937da..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins>; - - sysboot2 { - label = "gpio3"; - gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &led_pins_wkup>; - - led1 { - label = "led1"; - gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ - linux,default-trigger = "none"; - }; - }; -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ - 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ - reg = <1 0 0xff>; - }; -}; - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&video_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - video_reg: video_reg { - compatible = "regulator-fixed"; - regulator-name = "fixed-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0: display { - /* This isn't the exact LCD, but the timings meet spec */ - compatible = "logicpd,type28"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_enable_pin>; - backlight = <&bl>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&twl_pwm 0 5000000>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 */ - OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ - >; - }; - - lcd_enable_pin: pinmux_lcd_enable_pin { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ - OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ - OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ - OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ - OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ - OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - >; - }; -}; - -&omap3_pmx_wkup { - led_pins_wkup: pinmux_led_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ - >; - }; -}; - - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi deleted file mode 100644 index 385bc8d793400e6f608a7ae01f816c2f2394e2ff..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-som-lv.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 3 0>; /* gpio_3 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vaux3>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb2_phy: hsusb2_phy { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ - #phy-cells = <0>; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &wl127x_gpio>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1273"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */ - ref-clock-frequency = <26000000>; - }; -}; - -&usbhshost { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>, <&hsusb2_2_pins>; - port2-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <0 &hsusb2_phy>; -}; - - -&omap3_pmx_core { - - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ - OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ - >; - }; - - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - - hsusb2_pins: pinmux_hsusb2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ - OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ - OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ - >; - }; - - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; -}; - -&omap3_pmx_wkup { - - hsusb2_reset_pin: pinmux_hsusb1_reset_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ - >; - }; - - wl127x_gpio: pinmux_wl127x_gpio_pin { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&vaux3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi index 4744872f7c54ae2bbd25f512b444ebfb976231c2..d14d68e458a0507af31beeb9de17eb9e35d7eac6 100644 --- a/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi @@ -14,6 +14,8 @@ aliases { /delete-property/ serial1; /delete-property/ serial2; + /delete-property/ mmc1; + /delete-property/ mmc2; }; ethernet@08000000 { diff --git a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts deleted file mode 100644 index cb08aa62d96715fa9d24f3def3b268d7d037bf5f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-torpedo-35xx-devkit.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap34xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" -#include "omap-gpmc-smsc9221.dtsi" - -/ { - model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; -}; - -&omap3_pmx_core { - isp1763_pins: pinmux_isp1763_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 2c343445046b79be58b5eb6e7315f96c9edfb567..8e8e2e4096f3b9fe36454fb1c8e54d8dbef2ffc0 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -10,6 +10,8 @@ aliases { /delete-property/ serial1; /delete-property/ serial2; + /delete-property/ mmc1; + /delete-property/ mmc2; }; ethernet@08000000 { diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts deleted file mode 100644 index 07ea822fe40528fd521ce856b56c4aaa43db058a..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "omap36xx.dtsi" -#include "logicpd-torpedo-som.dtsi" -#include "omap-gpmc-smsc9221.dtsi" -#include "logicpd-torpedo-baseboard.dtsi" - -/ { - model = "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit"; - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; - - wl12xx_vmmc: wl12xx_vmmc { - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio5 29 0>; /* gpio157 */ - startup-delay-us = <70000>; - enable-active-high; - vin-supply = <&vmmc2>; - }; -}; - -/* - * Only found on the wireless SOM. For the SOM without wireless, the pins for - * MMC3 can be routed with jumpers to the second MMC slot on the devkit and - * gpio157 is not connected. So this should be OK to keep common for now, - * probably device tree overlays is the way to go with the various SOM and - * jumpering combinations for the long run. - */ -&mmc3 { - interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>; - pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>; - pinctrl-names = "default"; - vmmc-supply = <&wl12xx_vmmc>; - non-removable; - bus-width = <4>; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1283"; - reg = <2>; - interrupt-parent = <&gpio5>; - interrupts = <24 IRQ_TYPE_EDGE_RISING>; /* gpio 152 */ - ref-clock-frequency = <26000000>; - tcxo-clock-frequency = <26000000>; - }; -}; - -&uart2 { - /delete-property/dma-names; - bluetooth { - compatible = "ti,wl1283-st"; - enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */ - max-speed = <3000000>; - }; -}; - -/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */ -&mt9p031_out { - pixel-clock-frequency = <90000000>; -}; - -&omap3_pmx_core { - mmc3_pins: pinmux_mm3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ - OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ - OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ - OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ - OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ - OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */ - >; - }; -}; - -&omap3_pmx_core2 { - mmc3_core2_pins: pinmux_mmc3_core2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */ - OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */ - >; - }; -}; - -/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ -&omap3_pmx_wkup { - isp1763_pins: pinmux_isp1763_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ - >; - }; -}; diff --git a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/dts/logicpd-torpedo-baseboard.dtsi deleted file mode 100644 index b4664ab002566b5f1173cdeeebc1de78ecfc98ba..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-torpedo-baseboard.dtsi +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/ { - gpio_keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_key_pins &gpio_key_pins_wkup>; - - sysboot2 { - label = "sysboot2"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* gpio2 */ - linux,code = ; - wakeup-source; - }; - - sysboot5 { - label = "sysboot5"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; /* gpio7 */ - linux,code = ; - wakeup-source; - }; - - gpio1 { - label = "gpio1"; - gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; /* gpio181 */ - linux,code = ; - wakeup-source; - }; - - gpio2 { - label = "gpio2"; - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; /* gpio178 */ - linux,code = ; - wakeup-source; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3logic"; - ti,mcbsp = <&mcbsp2>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led1 { - label = "led1"; - gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; /* gpio180 */ - linux,default-trigger = "cpu0"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>; /* gpio179 */ - linux,default-trigger = "none"; - }; - }; - - pwm10: dmtimer-pwm { - compatible = "ti,omap-dmtimer-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pins>; - ti,timers = <&timer10>; - #pwm-cells = <3>; - ti,clock-source = <0x01>; - }; - -}; - -&vaux1 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&vaux4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&mcbsp2 { - pinctrl-names = "default"; - pinctrl-0 = <&mcbsp2_pins>; - status = "okay"; -}; - -&charger { - ti,bb-uvolt = <3200000>; - ti,bb-uamp = <150>; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ - 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */ - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&lan9221_pins>; - interrupt-parent = <&gpio5>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ - reg = <1 0 0xff>; - }; - - usb@6,0 { - pinctrl-names = "default"; - pinctrl-0 = <&isp1763_pins>; - compatible = "nxp,usb-isp1763"; - reg = <0x6 0x0 0xff>; - interrupt-parent = <&gpio5>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host"; - bus-width = <16>; - dr_mode = "host"; - gpmc,mux-add-data = <0>; - gpmc,device-width = <2>; - gpmc,wait-pin = <0>; - gpmc,burst-length = <4>; - gpmc,cycle2cycle-samecsen = <1>; - gpmc,cycle2cycle-diffcsen = <1>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <45>; - gpmc,cs-wr-off-ns = <45>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <0>; - gpmc,adv-wr-off-ns = <0>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <45>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <25>; - gpmc,rd-cycle-ns = <60>; - gpmc,wr-cycle-ns = <45>; - gpmc,access-ns = <35>; - gpmc,page-burst-access-ns = <0>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <60>; - gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <5>; - gpmc,wr-access-ns = <20>; - }; -}; - -&hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; -}; - - -&vpll2 { - regulator-always-on; -}; - -&dss { - status = "okay"; - vdds_dsi-supply = <&vpll2>; - vdda_video-supply = <&vpll2>; - pinctrl-names = "default"; - pinctrl-0 = <&dss_dpi_pins1>; - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <16>; - }; - }; -}; - -/ { - aliases { - display0 = &lcd0; - }; - - lcd0: display { - /* This isn't the exact LCD, but the timings meet spec */ - compatible = "newhaven,nhd-4.3-480272ef-atxl"; - label = "15"; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pwr_pins>; - backlight = <&bl>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - - bl: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&backlight_pins>; - pwms = <&pwm10 0 5000000 0>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <7>; - enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ - }; -}; - -&mmc1 { - interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins &mmc1_cd>; - cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio127 */ - vmmc-supply = <&vmmc1>; - bus-width = <4>; - cap-power-off-card; -}; - -&omap3_pmx_core { - gpio_key_pins: pinmux_gpio_key_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_clk.gpio_178 */ - OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 */ - >; - }; - - hdq_pins: hdq_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */ - >; - }; - - pwm_pins: pinmux_pwm_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ - >; - }; - - led_pins: pinmux_led_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ - OMAP3_CORE1_IOPAD(0x21da, PIN_OUTPUT | MUX_MODE4) /* gpio_180 */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - tsc2004_pins: pinmux_tsc2004_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ - >; - }; - - backlight_pins: pinmux_backlight_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ - >; - }; - - isp_pins: pinmux_isp_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ - OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ - OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ - OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ - - OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ - OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ - OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ - OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ - OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ - OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ - OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ - OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ - >; - }; - - panel_pwr_pins: pinmux_panel_pwr_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ - >; - }; - - dss_dpi_pins1: pinmux_dss_dpi_pins1 { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ - >; - }; -}; - -&omap3_pmx_wkup { - gpio_key_pins_wkup: pinmux_gpio_key_pins_wkup { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot0.gpio_2 */ - OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot5.gpio_7 */ - >; - }; - - lan9221_pins: pinmux_lan9221_pins { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */ - >; - }; - - mmc1_cd: pinmux_mmc1_cd { - pinctrl-single,pins = < - OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ - >; - }; -}; - -&i2c2 { - mt9p031@48 { - compatible = "aptina,mt9p031"; - reg = <0x48>; - clocks = <&isp 0>; - vaa-supply = <&vaux4>; - vdd-supply = <&vaux4>; - vdd_io-supply = <&vaux4>; - port { - mt9p031_out: endpoint { - input-clock-frequency = <24000000>; - pixel-clock-frequency = <72000000>; - remote-endpoint = <&ccdc_ep>; - }; - }; - }; -}; - -&i2c3 { - touchscreen: tsc2004@48 { - compatible = "ti,tsc2004"; - reg = <0x48>; - vio-supply = <&vaux1>; - pinctrl-names = "default"; - pinctrl-0 = <&tsc2004_pins>; - interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */ - - touchscreen-fuzz-x = <4>; - touchscreen-fuzz-y = <7>; - touchscreen-fuzz-pressure = <2>; - touchscreen-size-x = <4096>; - touchscreen-size-y = <4096>; - touchscreen-max-pressure = <2048>; - - ti,x-plate-ohms = <280>; - ti,esd-recovery-timeout-ms = <8000>; - }; -}; - -&mcspi1 { - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; -}; - -&isp { - pinctrl-names = "default"; - pinctrl-0 = <&isp_pins>; - ports { - port@0 { - reg = <0>; - ccdc_ep: endpoint { - remote-endpoint = <&mt9p031_out>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - }; - }; - }; -}; - -&uart1 { - interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; -}; - -/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ -&usb_otg_hs { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb_otg_pins>; - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; diff --git a/arch/arm/dts/logicpd-torpedo-som.dtsi b/arch/arm/dts/logicpd-torpedo-som.dtsi deleted file mode 100644 index 3a5228562b0d4ea250fc9c23bbb85cb05269043d..0000000000000000000000000000000000000000 --- a/arch/arm/dts/logicpd-torpedo-som.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include - -/ { - chosen { - stdout-path = &uart1; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - leds { - compatible = "gpio-leds"; - user0 { - label = "user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - linux,default-trigger = "none"; - }; - }; - - /* fixed 26MHz oscillator */ - hfclk_26m: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; -}; - -/* The Torpedo doesn't route the USB host pins */ -&usbhshost { - status = "disabled"; -}; - -&gpmc { - ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - linux,mtd-name = "micron,mt29f4g16abbda3w"; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - gpmc,device-width = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - clocks = <&hfclk_26m>; - clock-names = "fck"; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - at24@50 { - compatible = "atmel,24c64"; - readonly; - reg = <0x50>; - }; -}; - -&omap3_pmx_core { - mcbsp2_pins: pinmux_mcbsp2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ - OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ - OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ - OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ - >; - }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ - >; - }; - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ - OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ - OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ - OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ - >; - }; - hsusb_otg_pins: pinmux_hsusb_otg_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ - OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ - OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ - OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ - - OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ - OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ - OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ - OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ - OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ - OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ - OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ - OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ - >; - }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - >; - }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - >; - }; - i2c3_pins: pinmux_i2c3_pins { - pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ - >; - }; -}; - -&uart2 { - interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&twl { - twl_power: power { - compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; - ti,use_poweroff; - }; -}; - -&twl_gpio { - ti,use-leds; -}; - -&twl_keypad { - status = "disabled"; -}; diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts deleted file mode 100644 index 24da6ee6eccd3f9a861b8d6601fa948e6fceb7b7..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "r8a774a1.dtsi" -#include "beacon-renesom-som.dtsi" -#include "beacon-renesom-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks RZ/G2M Development Kit"; - compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &iic_pmic; - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - ethernet0 = &avb; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts deleted file mode 100644 index a5ca86196a7b50bdd1603a9d7d54db0ff46717cf..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to - * sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", - "renesas,r8a774a1"; -}; - -/* SW43 should be OFF, if in ON state SATA port will be activated */ -&pciec1 { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts deleted file mode 100644 index 25ae255de0f22b454bf4cf4cc9d889a378e3a0cc..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774a1-hihope-rzg2m.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774a1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; - compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi deleted file mode 100644 index 9065dc243428f128bc65c4b4ce3d6f8d976d9973..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774a1.dtsi +++ /dev/null @@ -1,2865 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774a1 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774a1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774a1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774a1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774a1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774a1-cpg-mssr"; - reg = <0 0xe6150000 0 0x0bb0>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774a1-rst"; - reg = <0 0xe6160000 0 0x018c>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774a1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774a1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic_pmic: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774a1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774a1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774a1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774a1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774a1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774a1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774a1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a774a1-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774a1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774a1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774a1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774A1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774a1"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774a1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts deleted file mode 100644 index 8b9df6afffde71cb94fa7b54e5a7c9ee46a03ae9..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "r8a774b1.dtsi" -#include "beacon-renesom-som.dtsi" -#include "beacon-renesom-baseboard.dtsi" - -/ { - model = "Beacon Embedded Works RZ/G2N Development Kit"; - compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &iic_pmic; - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - serial6 = &scif4; - ethernet0 = &avb; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts deleted file mode 100644 index 60d7c8adea02c33845a01c7b959a771ece78e396..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to - * sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", - "renesas,r8a774b1"; -}; - -/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts deleted file mode 100644 index f1883cbd1a82781bef30906fa424b511a79d2905..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0 - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774b1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N main board based on r8a774b1"; - compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi deleted file mode 100644 index 75776decd2186f7dd586328dbba4cf44a5f538a7..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774b1.dtsi +++ /dev/null @@ -1,2716 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774b1 SoC - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774b1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774B1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774b1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774b1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774b1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774b1-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774b1-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774b1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774b1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic_pmic: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774b1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774b1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774b1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774B1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774b1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774b1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774b1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774b1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a774b1-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a774b1", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774b1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774b1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 611>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774b1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774B1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774b1"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774b1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a774c0-cat874.dts b/arch/arm/dts/r8a774c0-cat874.dts deleted file mode 100644 index 5a6ea08ffd2b2791ea80bec60cae2cac66c67963..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774c0-cat874.dts +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774c0.dtsi" -#include -#include - -/ { - model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; - compatible = "si-linux,cat874", "renesas,r8a774c0"; - - aliases { - serial0 = &scif2; - serial1 = &hscif2; - mmc0 = &sdhi0; - mmc1 = &sdhi3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&tda19988_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; - label = "LED0"; - }; - - led1 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - label = "LED1"; - }; - - led2 { - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - label = "LED2"; - }; - - led3 { - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "CAT874 HDMI sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - wlan_en_reg: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - x13_clk: x13 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - hs_ep: endpoint { - remote-endpoint = <&usb3_hs_ep>; - }; - }; - port@1 { - reg = <1>; - ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_in_ep>; - }; - }; - }; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x13_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - du_out_rgb: endpoint { - remote-endpoint = <&tda19988_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "host"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hscif2 { - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - hd3ss3220_in_ep: endpoint { - remote-endpoint = <&ss_ep>; - }; - }; - port@1 { - reg = <1>; - hd3ss3220_out_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; - - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - video-ports = <0x234501>; - - #sound-dai-cells = <0>; - audio-ports = ; - clocks = <&rcar_sound 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tda19988_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - tda19988_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@32 { - compatible = "epson,rx8571"; - reg = <0x32>; - }; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "host"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; -}; - -&pfc { - du_pins: du { - groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", - "du_clk_in_0"; - function = "du"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data_a", "hscif2_ctrl_a"; - function = "hscif2"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_b"; - function = "i2c1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clkout1_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data"; - function = "ssi"; - }; - - usb30_pins: usb30 { - groups = "usb30", "usb30_id"; - function = "usb30"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <11289600>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src0>, <&dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi3 { - status = "okay"; - pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&usb2_phy0 { - renesas,no-otg-pins; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; - usb-role-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - usb3_hs_ep: endpoint { - remote-endpoint = <&hs_ep>; - }; - }; - port@1 { - reg = <1>; - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_out_ep>; - }; - }; - }; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/dts/r8a774c0-ek874.dts b/arch/arm/dts/r8a774c0-ek874.dts deleted file mode 100644 index e7b6619ab224d6c4d8033fdf2c70e5d96223b019..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774c0-ek874.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774c0-cat874.dts" -#include "cat875.dtsi" - -/ { - model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)"; - compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; -}; diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi deleted file mode 100644 index ad2e87b039acd7ac07b4c544c00f1d8b9993f677..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774c0.dtsi +++ /dev/null @@ -1,2000 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2E (R8A774C0) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a774c0"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774C0_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774c0-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774c0"; - reg = <0 0xe6060000 0 0x508>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774c0-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774c0-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774c0-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774c0-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a774c0"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic_pmic: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774c0", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774c0", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774C0_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774c0", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774c0-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774c0", - "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774C0_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774c0", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774c0-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774c0", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a774c0-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774c0", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774c0-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774c0-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774c0"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts deleted file mode 100644 index 146f78cb6f19284ca75a106cb4ed6dbc70ffb523..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "r8a774e1.dtsi" -#include "beacon-renesom-som.dtsi" -#include "beacon-renesom-baseboard.dtsi" - -/ { - model = "Beacon Embedded Works RZ/G2H Development Kit"; - compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &iic_pmic; - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - serial6 = &scif4; - ethernet0 = &avb; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts deleted file mode 100644 index 81299593984197cfc75bc4a4459bfd2baf7f25c0..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774e1-hihope-rzg2h.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2H with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", - "renesas,r8a774e1"; -}; - -/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts deleted file mode 100644 index 9525d5ed6fce6324600da1b68e081bd92f52911f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H main board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774e1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; - compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi deleted file mode 100644 index 2acf4067ab2f23e2b6624d7d39742ee92cecb1be..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a774e1.dtsi +++ /dev/null @@ -1,2997 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774e1 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774e1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - core2 { - cpu = <&a57_2>; - }; - core3 { - cpu = <&a57_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774E1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A774E1_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774e1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774e1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774e1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774e1-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774e1-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774e1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774e1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - iic_pmic: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774e1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774e1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774e1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774e1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774e1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774e1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp0: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv2: iommu@fd960000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv3: iommu@fd970000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774E1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vc1: iommu@fe6f0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A774E1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@febe0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vp1: iommu@fe980000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774e1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774e1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774e1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774e1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774e1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774e1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774e1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774e1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a774e1-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a774e1", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 815>; - iommus = <&ipmmu_hc 2>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774e1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774e1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774e1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774e1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; - }; - - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 615>; - }; - - fcpf1: fcp@fe951000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe951000 0 0x200>; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 614>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 606>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 611>; - }; - - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 610>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774e1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774e1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774e1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774E1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774e1"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774e1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <6313>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <6313>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <6313>; - - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts deleted file mode 100644 index 5ad5349a50dc9b2630deafdb7911fb6910e3400f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7790-lager.dts +++ /dev/null @@ -1,947 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - * Copyright (C) 2015-2016 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Lager"; - compatible = "renesas,lager", "renesas,r8a7790"; - - aliases { - serial0 = &scif0; - serial1 = &scifa1; - i2c8 = &gpioi2c1; - i2c9 = &gpioi2c2; - i2c10 = &i2cexio0; - i2c11 = &i2cexio1; - i2c12 = &i2chdmi; - i2c13 = &i2cpwr; - mmc0 = &mmcif1; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@140000000 { - device_type = "memory"; - reg = <1 0x40000000 0 0xc0000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-8 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only. - * We use the I2C demuxer, so the desired IP core can be selected at runtime - * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0). - * Note: For testing the I2C slave feature, it is convenient to connect this - * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and - * instantiate the slave device at runtime according to the documentation. - * You can then communicate with the slave via IIC3. - * - * IIC0/I2C0 does not appear to support fallback to GPIO. - */ - i2cexio0: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic0>, <&i2c0>; - i2c-bus-name = "i2c-exio0"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA). - * This is similar to the arangement described for i2cexio0 (above) - * with a fallback to GPIO also provided. - */ - i2cexio1: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * IIC2 and I2C2 may be switched using pinmux. - * A fallback to GPIO is also provided. - */ - i2chdmi: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep0>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - }; - - /* - * IIC3 and I2C3 may be switched using pinmux. - * IIC3/I2C3 does not appear to support fallback to GPIO. - */ - i2cpwr: i2c-13 { - compatible = "i2c-demux-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - i2c-parent = <&iic3>, <&i2c3>; - i2c-bus-name = "i2c-pwr"; - #address-cells = <1>; - #size-cells = <0>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - scifa1_pins: scifa1 { - groups = "scifa1_data"; - function = "scifa1"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - mmc1_pins: mmc1 { - groups = "mmc1_data8", "mmc1_ctrl"; - function = "mmc1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof1_pins: msiof1 { - groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", - "msiof1_tx"; - function = "msiof1"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - iic0_pins: iic0 { - groups = "iic0"; - function = "iic0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - iic1_pins: iic1 { - groups = "iic1"; - function = "iic1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - iic2_pins: iic2 { - groups = "iic2"; - function = "iic2"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3"; - function = "i2c3"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - hsusb_pins: hsusb { - groups = "usb0_ovc_vbus"; - function = "usb0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; - bias-pull-up; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&msiof1 { - pinctrl-0 = <&msiof1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&iic0 { - pinctrl-0 = <&iic0_pins>; - pinctrl-names = "i2c-exio0"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&iic1 { - pinctrl-0 = <&iic1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&iic2 { - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&iic3 { - pinctrl-0 = <&iic3_pins>; - pinctrl-names = "i2c-pwr"; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&xhci { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&pci2 { - status = "okay"; - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&hsusb_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -/* HDMI video input */ -&vin0 { - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep0: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/dts/r8a7790-stout.dts b/arch/arm/dts/r8a7790-stout.dts deleted file mode 100644 index fe14727eefe1ec8caddc3a46d7c3eaef2f80d57c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7790-stout.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Stout board - * - * Copyright (C) 2018 Marek Vasut - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include -#include - -/ { - model = "Stout"; - compatible = "renesas,stout", "renesas,r8a7790"; - - aliases { - serial0 = &scifa0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; - led2 { - gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; - }; - led3 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - }; - led5 { - gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - }; - }; - - fixedregulator3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - osc4_clk: osc4-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, - <&osc1_clk>; - clock-names = "du.0", "du.1", "du.2", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector0: endpoint { - }; - }; - }; -}; - -&lvds1 { - ports { - port@1 { - lvds_connector1: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du_rgb888", "du_sync_1", "du_clk_out_0"; - function = "du"; - }; - - scifa0_pins: scifa0 { - groups = "scifa0_data_b"; - function = "scifa0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq1"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - iic2_pins: iic2 { - groups = "iic2_b"; - function = "iic2"; - }; - - iic3_pins: iic3 { - groups = "iic3"; - function = "iic3"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "uboot"; - reg = <0x00080000 0x00040000>; - read-only; - }; - partition@c0000 { - label = "uboot-env"; - reg = <0x000c0000 0x00040000>; - read-only; - }; - partition@100000 { - label = "flash"; - reg = <0x00100000 0x03f00000>; - }; - }; - }; -}; - -&scifa0 { - pinctrl-0 = <&scifa0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&iic2 { - status = "okay"; - pinctrl-0 = <&iic2_pins>; - pinctrl-names = "default"; - - clock-frequency = <100000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - clocks = <&osc4_clk>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&iic3 { - pinctrl-names = "default"; - pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd: regulator@70 { - compatible = "dlg,da9210"; - reg = <0x70>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi deleted file mode 100644 index 46fb81f5062ff6bc6a939ccde667bccdc101e59d..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7790.dtsi +++ /dev/null @@ -1,1965 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H2 (R8A77900) SoC - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7790"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &iic0; - i2c5 = &iic1; - i2c6 = &iic2; - i2c7 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - spi4 = &msiof3; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU2>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - clock-frequency = <1300000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - power-domains = <&sysc R8A7790_PD_CA15_CPU3>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - capacity-dmips-mhz = <1024>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1400000 1000000>, - <1225000 1000000>, - <1050000 1000000>, - < 875000 1000000>, - < 700000 1000000>, - < 350000 1000000>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x102>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU2>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x103>; - clock-frequency = <780000000>; - clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; - power-domains = <&sysc R8A7790_PD_CA7_CPU3>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - capacity-dmips-mhz = <539>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA7: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7790_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu-0 { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - pmu-1 { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7790-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7790", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7790"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7790", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7790-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7790-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7790-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7790", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7790", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7790", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - iic0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - iic1: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - iic2: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6520000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 300>; - dmas = <&dmac0 0x69>, <&dmac0 0x6a>, - <&dmac1 0x69>, <&dmac1 0x6a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7790", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7790", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7790", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7790-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7790", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7790", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7790", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7790", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e56000 { - compatible = "renesas,scif-r8a7790", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e56000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7790", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 0>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c90000 { - compatible = "renesas,msiof-r8a7790", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6c90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 215>; - dmas = <&dmac0 0x45>, <&dmac0 0x46>, - <&dmac1 0x45>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 215>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7790", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7790", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7790", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7790_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7790", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0b0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0b0000 0 0xc00>, - <0 0xee0a0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - }; - - pci2: pci@ee0d0000 { - compatible = "renesas,pci-r8a7790", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 703>; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - status = "disabled"; - - bus-range = <2 2>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x20800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x21000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7790", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,mmcif-r8a7790", - "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 305>; - dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, - <&dmac1 0xe1>, <&dmac1 0xe2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 305>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7790", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7790", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7790", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe920000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 130>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 130>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 117>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7790"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds@feb94000 { - compatible = "renesas,r8a7790-lvds"; - reg = <0 0xfeb94000 0 0x1c>; - clocks = <&cpg CPG_MOD 725>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 725>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts deleted file mode 100644 index 26a40782cc899bd0ebe74df0ca5f91f099dde72f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7791-koelsch.dts +++ /dev/null @@ -1,912 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Koelsch board - * - * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include -#include - -/ { - model = "Koelsch"; - compatible = "renesas,koelsch", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c2; - i2c11 = &gpioi2c4; - i2c12 = &i2cexio1; - i2c13 = &i2chdmi; - i2c14 = &i2cexio4; - mmc0 = &sdhi0; - mmc1 = &sdhi1; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - cec_clock: cec-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c2: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-11 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio1: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-exio1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-13 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cec_clock>; - clock-names = "cec"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - msiof0_pins: msiof0 { - groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", - "msiof0_tx"; - function = "msiof0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; - bias-pull-up; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash: flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpha; - spi-cpol; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00080000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x00580000>; - read-only; - }; - partition@600000 { - label = "flash"; - reg = <0x00600000 0x03a00000>; - }; - }; - }; -}; - -&msiof0 { - pinctrl-0 = <&msiof0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - pmic: pmic@0 { - compatible = "renesas,r2a11302ft"; - reg = <0>; - spi-max-frequency = <6000000>; - spi-cpol; - spi-cpha; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-exio1"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <100000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&hsusb { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - status = "okay"; - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts deleted file mode 100644 index ec0a20d5130d6f0491a75d737973d7ae67f47ca6..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7791-porter.dts +++ /dev/null @@ -1,523 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Porter board - * - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4642 - * - * JP3: 2-1: AK4642 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7791.dtsi" -#include - -/ { - model = "Porter"; - compatible = "renesas,porter", "renesas,r8a7791"; - - aliases { - serial0 = &scif0; - i2c9 = &gpioi2c2; - i2c10 = &i2chdmi; - mmc0 = &sdhi0; - mmc1 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - memory@200000000 { - device_type = "memory"; - reg = <2 0x00000000 0 0x40000000>; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x16_clk: x16-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x14_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4642>; - clocks = <&x14_clk>; - }; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4642: codec@12 { - compatible = "asahi-kasei,ak4642"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader_prg"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user_prg"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash_fs"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@5a { - compatible = "dlg,da9063l"; - reg = <0x5a>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&sata0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pci1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&hsusb { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x3_clk>, <&x16_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi deleted file mode 100644 index b9d34147628e120125fe85f451c666cc55442bf1..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7791.dtsi +++ /dev/null @@ -1,1891 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-W (R8A77910) SoC - * - * Copyright (C) 2013-2015 Renesas Electronics Corporation - * Copyright (C) 2013-2014 Renesas Solutions Corp. - * Copyright (C) 2014 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7791"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - spi3 = &msiof2; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - power-domains = <&sysc R8A7791_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7791_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7791-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7791", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7791"; - reg = <0 0xe6060000 0 0x250>; - }; - - tpu: pwm@e60f0000 { - compatible = "renesas,tpu-r8a7791", "renesas,tpu"; - reg = <0 0xe60f0000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7791-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7791-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7791-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7791", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7791", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7791", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7791", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7791", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7791", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7791", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7791-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7791", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7791", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7791", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7791", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7791", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6e00000 { - compatible = "renesas,msiof-r8a7791", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 205>; - dmas = <&dmac0 0x41>, <&dmac0 0x42>, - <&dmac1 0x41>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 205>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - adc: adc@e6e54000 { - compatible = "renesas,r8a7791-gyroadc", - "renesas,rcar-gyroadc"; - reg = <0 0xe6e54000 0 64>; - clocks = <&cpg CPG_MOD 901>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 901>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7791", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7791", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7791", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7791_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", "src.9", "src.8", - "src.7", "src.6", "src.5", "src.4", - "src.3", "src.2", "src.1", "src.0", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7791", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791", - "renesas,rcar-gen2-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 328>; - phys = <&usb2 1>; - phy-names = "usb"; - status = "disabled"; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7791", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7791", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7791", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - sata1: sata@ee500000 { - compatible = "renesas,sata-r8a7791", - "renesas,rcar-gen2-sata"; - reg = <0 0xee500000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 814>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7791", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", - "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, - <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7791"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7791-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7791-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7791-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/dts/r8a7792-blanche.dts b/arch/arm/dts/r8a7792-blanche.dts deleted file mode 100644 index 6a83923aa4612e712e7a703107475906dce531cb..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7792-blanche.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Blanche board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a7792.dtsi" -#include -#include - -/ { - model = "Blanche"; - compatible = "renesas,blanche", "renesas,r8a7792"; - - aliases { - serial0 = &scif0; - serial1 = &scif3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x1_clk: x1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x2_clk: x2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <65000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - key-2 { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - key-3 { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - key-4 { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - key-a { - linux,code = ; - label = "SW24"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - }; - key-b { - linux,code = ; - label = "SW25"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led17 { - gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; - }; - led18 { - gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; - }; - led19 { - gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; - }; - led20 { - gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&can_clk { - clock-frequency = <48000000>; -}; - -&pfc { - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif3_pins: scif3 { - groups = "scif3_data"; - function = "scif3"; - }; - - lan89218_pins: lan89218 { - intc { - groups = "intc_irq0"; - function = "intc"; - }; - lbsc { - groups = "lbsc_ex_cs0"; - function = "lbsc"; - }; - }; - - can0_pins: can0 { - groups = "can0_data", "can_clk"; - function = "can0"; - }; - - sdhi0_pins: sdhi0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp"; - function = "du1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2"; - bias-pull-up; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif3 { - pinctrl-0 = <&scif3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&irqc>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&iic3 { - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - interrupt-parent = <&irqc>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&du { - pinctrl-0 = <&du0_pins>, <&du1_pins>; - pinctrl-names = "default"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi deleted file mode 100644 index a6d9367f8fa047be028441f157ac81898b53db1b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7792.dtsi +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V2H (R8A77920) SoC - * - * Copyright (C) 2016 Cogent Embedded Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7792"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &iic3; - spi0 = &qspi; - spi1 = &msiof0; - spi2 = &msiof1; - vin0 = &vin0; - vin1 = &vin1; - vin2 = &vin2; - vin3 = &vin3; - vin4 = &vin4; - vin5 = &vin5; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; - power-domains = <&sysc R8A7792_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - power-domains = <&sysc R8A7792_PD_CA15_SCU>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7792-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055100 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055100 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055200 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055200 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - gpio8: gpio@e6055300 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055300 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 921>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 921>; - }; - - gpio9: gpio@e6055400 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 919>; - }; - - gpio10: gpio@e6055500 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055500 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 914>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 914>; - }; - - gpio11: gpio@e6055600 { - compatible = "renesas,gpio-r8a7792", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055600 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 352 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 913>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 913>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7792"; - reg = <0 0xe6060000 0 0x144>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7792-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7792-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7792-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7792-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7792", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* I2C doesn't need pinmux */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7792", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - iic3: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7792", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7792", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7792", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7792", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7792", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7792", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - msiof0: spi@e6e20000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 000>; - dmas = <&dmac0 0x51>, <&dmac0 0x52>, - <&dmac1 0x51>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6e10000 { - compatible = "renesas,msiof-r8a7792", - "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x55>, <&dmac0 0x56>, - <&dmac1 0x55>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7792", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 808>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 805>; - status = "disabled"; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7792", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 804>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7792", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - vsp@fe938000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe938000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 127>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 127>; - }; - - jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7792", - "renesas,rcar-gen2-jpu"; - reg = <0 0xfe980000 0 0x10300>; - interrupts = ; - clocks = <&cpg CPG_MOD 106>; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 106>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7792"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7792-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7792-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts deleted file mode 100644 index 79b537b24642662d2954a12dd06d2a88d5f28025..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7793-gose.dts +++ /dev/null @@ -1,818 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Gose board - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -/* - * SSI-AK4643 - * - * SW1: 1: AK4643 - * 2: CN22 - * 3: ADV7511 - * - * This command is required when Playback/Capture - * - * amixer set "LINEOUT Mixer DACL" on - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -/dts-v1/; -#include "r8a7793.dtsi" -#include -#include - -/ { - model = "Gose"; - compatible = "renesas,gose", "renesas,r8a7793"; - - aliases { - serial0 = &scif0; - serial1 = &scif1; - i2c9 = &gpioi2c2; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - mmc0 = &sdhi0; - mmc1 = &sdhi1; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW30"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW31"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW32"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW33"; - wakeup-source; - debounce-interval = <20>; - }; - key-e { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW34"; - wakeup-source; - debounce-interval = <20>; - }; - key-f { - gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW35"; - wakeup-source; - debounce-interval = <20>; - }; - key-g { - gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW36"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - led7 { - gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - label = "LED7"; - }; - led8 { - gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; - label = "LED8"; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi2: regulator-vcc-sdhi2 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI2 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi2: regulator-vccq-sdhi2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI2 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - audio_clock: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - rsnd_ak4643: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - composite-in { - compatible = "composite-video-connector"; - - port { - composite_con_in: endpoint { - remote-endpoint = <&adv7180_in>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c2: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C2. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c2>, <&gpioi2c2>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - adv7180_out: endpoint { - bus-width = <8>; - remote-endpoint = <&vin1ep>; - }; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio3>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-in@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - adv7612_out: endpoint { - remote-endpoint = <&vin0ep2>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-12 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4_c"; - function = "i2c4"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_d"; - function = "scif1"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq0"; - function = "intc"; - }; - - pmic_irq_pins: pmicirq { - groups = "intc_irq2"; - function = "intc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - sound_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a"; - function = "audio_clk"; - }; - - keyboard_pins: keyboard { - pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; - bias-pull-up; - }; - - vin0_pins: vin0 { - groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; - function = "vin0"; - }; - - vin1_pins: vin1 { - groups = "vin1_data8", "vin1_clk"; - function = "vin1"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&cpu0 { - cpu0-supply = <&vdd_dvfs>; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&sdhi2 { - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi2>; - vqmmc-supply = <&vccq_sdhi2>; - cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; - sd-uhs-sdr50; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "i2c-hdmi"; - - status = "okay"; - clock-frequency = <100000>; - -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins>; - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; - - vdd_dvfs: regulator@68 { - compatible = "dlg,da9210"; - reg = <0x68>; - interrupt-parent = <&irqc0>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>, <&src2>, <&dvc0>; - capture = <&ssi1>, <&src3>, <&dvc1>; - }; - }; -}; - -&ssi1 { - shared-pin; -}; - -/* HDMI video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep2: endpoint { - remote-endpoint = <&adv7612_out>; - bus-width = <24>; - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - data-active = <1>; - }; - }; -}; - -/* composite video input */ -&vin1 { - pinctrl-0 = <&vin1_pins>; - pinctrl-names = "default"; - - status = "okay"; - - port { - vin1ep: endpoint { - remote-endpoint = <&adv7180_out>; - bus-width = <8>; - }; - }; -}; diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi deleted file mode 100644 index f51bf687f4bd55d3e40bbc70fa3601dad9ca45a3..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7793.dtsi +++ /dev/null @@ -1,1470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M2-N (R8A77930) SoC - * - * Copyright (C) 2014-2015 Renesas Electronics Corporation - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7793"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - spi0 = &qspi; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU0>; - enable-method = "renesas,apmu"; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - clock-frequency = <1500000000>; - clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - power-domains = <&sysc R8A7793_PD_CA15_CPU1>; - enable-method = "renesas,apmu"; - voltage-tolerance = <1>; /* 1% */ - clock-latency = <300000>; /* 300 us */ - - /* kHz - uV - OPPs unknown yet */ - operating-points = <1500000 1000000>, - <1312500 1000000>, - <1125000 1000000>, - < 937500 1000000>, - < 750000 1000000>, - < 375000 1000000>; - next-level-cache = <&L2_CA15>; - }; - - L2_CA15: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7793_PD_CA15_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7793-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7793", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 904>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 904>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7793"; - reg = <0 0xe6060000 0 0x250>; - }; - - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6152000 { - compatible = "renesas,r8a7793-apmu", "renesas,apmu"; - reg = <0 0xe6152000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7793-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7793-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7793", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - thermal: thermal@e61f0000 { - compatible = "renesas,thermal-r8a7793", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xffc80000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7793", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 931>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 930>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 929>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7793", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 925>; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e60b0000 { - /* doesn't need pinmux */ - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - dmas = <&dmac0 0x77>, <&dmac0 0x78>, - <&dmac1 0x77>, <&dmac1 0x78>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 926>; - status = "disabled"; - }; - - i2c7: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - i2c8: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7793", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 323>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7793", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7793", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7793", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7793", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7793", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7793", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7793", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 809>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7793", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A7793_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>, - <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>, - <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>, - <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>, - <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>, - <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, - <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, - <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>, - <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>, - <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>, - <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7793", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7793", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7793", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - max-frequency = <97500000>; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7793", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 118>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7793"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7793-lvds"; - reg = <0 0xfeb90000 0 0x1c>; - clocks = <&cpg CPG_MOD 726>; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 726>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7793-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7793-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&thermal>; - - trips { - cpu-crit { - temperature = <95000>; - hysteresis = <0>; - type = "critical"; - }; - }; - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts deleted file mode 100644 index 4d93319674c6efcf8fed348436b435532a063db8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7794-alt.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Alt board - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include -#include - -/ { - model = "Alt"; - compatible = "renesas,alt", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &gpioi2c4; - i2c11 = &i2chdmi; - i2c12 = &i2cexio4; - mmc0 = &mmcif0; - mmc1 = &sdhi0; - mmc2 = &sdhi1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - one { - linux,code = ; - label = "SW2-1"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - }; - two { - linux,code = ; - label = "SW2-2"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - }; - three { - linux,code = ; - label = "SW2-3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - }; - four { - linux,code = ; - label = "SW2-4"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x13_clk: x13-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - }; - - gpioi2c4: i2c-10 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-11 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - - /* - * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). - * A fallback to GPIO is provided. - */ - i2cexio4: i2c-14 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c4>, <&gpioi2c4>; - i2c-bus-name = "i2c-exio4"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x13_clk>, <&x2_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - du_pins: du { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; - bias-pull-up; - }; -}; - -&cmt0 { - status = "okay"; -}; - -&pfc { - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "i2c-exio4"; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "system"; - reg = <0x00040000 0x00040000>; - read-only; - }; - partition@80000 { - label = "user"; - reg = <0x00080000 0x03f80000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts deleted file mode 100644 index b7af1befa126ba624b8391f0e7fe8dd2f4320cac..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7794-silk.dts +++ /dev/null @@ -1,578 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the SILK board - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Renesas Solutions Corp. - * Copyright (C) 2014-2015 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4643 - * - * SW1: 2-1: AK4643 - * 2-3: ADV7511 - * - * This command is required before playback/capture: - * - * amixer set "LINEOUT Mixer DACL" on - */ - -/dts-v1/; -#include "r8a7794.dtsi" -#include -#include - -/ { - model = "SILK"; - compatible = "renesas,silk", "renesas,r8a7794"; - - aliases { - serial0 = &scif2; - i2c9 = &gpioi2c1; - i2c10 = &i2chdmi; - mmc0 = &mmcif0; - mmc1 = &sdhi1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; - - keyboard { - compatible = "gpio-keys"; - - pinctrl-0 = <&keyboard_pins>; - pinctrl-names = "default"; - - key-3 { - gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4"; - wakeup-source; - debounce-interval = <20>; - }; - key-6 { - gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW6"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-d { - gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW12-4"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - d3_3v: regulator-d3-3v { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb1>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - x2_clk: x2-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - x3_clk: x3-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; - - x9_clk: audio_clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&soundcodec>; - simple-audio-card,frame-master = <&soundcodec>; - - simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - soundcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - clocks = <&x9_clk>; - }; - }; - - gpioi2c1: i2c-9 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - status = "disabled"; - scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <5>; - }; - - /* - * A fallback to GPIO is provided for I2C1. - */ - i2chdmi: i2c-10 { - compatible = "i2c-demux-pinctrl"; - i2c-parent = <&i2c1>, <&gpioi2c1>; - i2c-bus-name = "i2c-hdmi"; - #address-cells = <1>; - #size-cells = <0>; - - ak4643: codec@12 { - compatible = "asahi-kasei,ak4643"; - #sound-dai-cells = <0>; - reg = <0x12>; - }; - - composite-in@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - - port { - adv7180: endpoint { - bus-width = <8>; - remote-endpoint = <&vin0ep>; - }; - }; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio5>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&du_out_rgb0>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "renesas,r1ex24002", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; - - ether_pins: ether { - groups = "eth_link", "eth_mdio", "eth_rmii"; - function = "eth"; - }; - - phy1_pins: phy1 { - groups = "intc_irq8"; - function = "intc"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmcif0_pins: mmcif0 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - }; - - qspi_pins: qspi { - groups = "qspi_ctrl", "qspi_data4"; - function = "qspi"; - }; - - vin0_pins: vin0 { - groups = "vin0_data8", "vin0_clk"; - function = "vin0"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; - - du0_pins: du0 { - groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out"; - function = "du0"; - }; - - du1_pins: du1 { - groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; - function = "du1"; - }; - - keyboard_pins: keyboard { - pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; - bias-pull-up; - }; - - ssi_pins: sound { - groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - audio_clk_pins: audio_clk { - groups = "audio_clkc"; - function = "audio_clk"; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -ðer { - pinctrl-0 = <ðer_pins>, <&phy1_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy1>; - renesas,ether-link-active-low; - status = "okay"; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - interrupt-parent = <&irqc0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <1>; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "i2c-hdmi"; - - clock-frequency = <400000>; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <100000>; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio3>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - }; -}; - -&mmcif0 { - pinctrl-0 = <&mmcif0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&d3_3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <30000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x00000000 0x00040000>; - read-only; - }; - partition@40000 { - label = "user"; - reg = <0x00040000 0x00400000>; - read-only; - }; - partition@440000 { - label = "flash"; - reg = <0x00440000 0x03bc0000>; - }; - }; - }; -}; - -/* composite video input */ -&vin0 { - status = "okay"; - pinctrl-0 = <&vin0_pins>; - pinctrl-names = "default"; - - port { - vin0ep: endpoint { - remote-endpoint = <&adv7180>; - bus-width = <8>; - }; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; -}; - -&du { - pinctrl-0 = <&du0_pins>, <&du1_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&x2_clk>, <&x3_clk>; - clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - port@1 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&rcar_sound { - pinctrl-0 = <&ssi_pins>, <&audio_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0>; - capture = <&ssi1>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi deleted file mode 100644 index 371dd4715ddef83d9486564a87830e4684a752ea..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a7794.dtsi +++ /dev/null @@ -1,1437 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E2 (R8A77940) SoC - * - * Copyright (C) 2014 Renesas Electronics Corporation - * Copyright (C) 2014 Ulrich Hecht - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a7794"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - spi0 = &qspi; - vin0 = &vin0; - vin1 = &vin1; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU0>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <1>; - clock-frequency = <1000000000>; - clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; - power-domains = <&sysc R8A7794_PD_CA7_CPU1>; - enable-method = "renesas,apmu"; - next-level-cache = <&L2_CA7>; - }; - - L2_CA7: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7794-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7794", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7794"; - reg = <0 0xe6060000 0 0x11c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - apmu@e6151000 { - compatible = "renesas,r8a7794-apmu", "renesas,apmu"; - reg = <0 0xe6151000 0 0x188>; - cpus = <&cpu0>, <&cpu1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7794-rst"; - reg = <0 0xe6160000 0 0x0100>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7794-sysc"; - reg = <0 0xe6180000 0 0x0200>; - #power-domain-cells = <1>; - }; - - irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc-r8a7794", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - ipmmu_sy0: iommu@e6280000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6280000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_sy1: iommu@e6290000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6290000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe6740000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xec680000 0 0x1000>; - interrupts = ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mx: iommu@fe951000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_gp: iommu@e62a0000 { - compatible = "renesas,ipmmu-r8a7794", - "renesas,ipmmu-vmsa"; - reg = <0 0xe62a0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - icram0: sram@e63a0000 { - compatible = "mmio-sram"; - reg = <0 0xe63a0000 0 0x12000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63a0000 0x12000>; - }; - - icram1: sram@e63c0000 { - compatible = "mmio-sram"; - reg = <0 0xe63c0000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xe63c0000 0x1000>; - - smp-sram@0 { - compatible = "renesas,smp-sram"; - reg = <0 0x100>; - }; - }; - - /* The memory map in the User's Manual maps the cores to - * bus numbers - */ - i2c0: i2c@e6508000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 931>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6518000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6518000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 930>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6530000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6530000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 929>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e6540000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6540000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 928>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c4: i2c@e6520000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6520000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 927>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e6528000 { - compatible = "renesas,i2c-r8a7794", - "renesas,rcar-gen2-i2c"; - reg = <0 0xe6528000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 925>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 925>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e6500000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6500000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 318>; - dmas = <&dmac0 0x61>, <&dmac0 0x62>, - <&dmac1 0x61>, <&dmac1 0x62>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 318>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@e6510000 { - compatible = "renesas,iic-r8a7794", - "renesas,rcar-gen2-iic", - "renesas,rmobile-iic"; - reg = <0 0xe6510000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 323>; - dmas = <&dmac0 0x65>, <&dmac0 0x66>, - <&dmac1 0x65>, <&dmac1 0x66>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 323>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7794", - "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - renesas,buswait = <4>; - phys = <&usb0 1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: usb-phy-controller@e6590100 { - compatible = "renesas,usb-phy-r8a7794", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - - usb0: usb-phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <15>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7794", - "renesas,etheravb-rcar-gen2"; - reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 812>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - qspi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7794", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>, - <&dmac1 0x17>, <&dmac1 0x18>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 917>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, - <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scifa1: serial@e6c50000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>; - clock-names = "fck"; - dmas = <&dmac0 0x25>, <&dmac0 0x26>, - <&dmac1 0x25>, <&dmac1 0x26>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scifa2: serial@e6c60000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>; - clock-names = "fck"; - dmas = <&dmac0 0x27>, <&dmac0 0x28>, - <&dmac1 0x27>, <&dmac1 0x28>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - scifa3: serial@e6c70000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c70000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1106>; - clock-names = "fck"; - dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, - <&dmac1 0x1b>, <&dmac1 0x1c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1106>; - status = "disabled"; - }; - - scifa4: serial@e6c78000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c78000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1107>; - clock-names = "fck"; - dmas = <&dmac0 0x1f>, <&dmac0 0x20>, - <&dmac1 0x1f>, <&dmac1 0x20>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1107>; - status = "disabled"; - }; - - scifa5: serial@e6c80000 { - compatible = "renesas,scifa-r8a7794", - "renesas,rcar-gen2-scifa", "renesas,scifa"; - reg = <0 0xe6c80000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 1108>; - clock-names = "fck"; - dmas = <&dmac0 0x23>, <&dmac0 0x24>, - <&dmac1 0x23>, <&dmac1 0x24>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1108>; - status = "disabled"; - }; - - scifb0: serial@e6c20000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>; - clock-names = "fck"; - dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, - <&dmac1 0x3d>, <&dmac1 0x3e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scifb1: serial@e6c30000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>; - clock-names = "fck"; - dmas = <&dmac0 0x19>, <&dmac0 0x1a>, - <&dmac1 0x19>, <&dmac1 0x1a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scifb2: serial@e6ce0000 { - compatible = "renesas,scifb-r8a7794", - "renesas,rcar-gen2-scifb", "renesas,scifb"; - reg = <0 0xe6ce0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, - <&dmac1 0x1d>, <&dmac1 0x1e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 216>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, - <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 721>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, - <&dmac1 0x2d>, <&dmac1 0x2e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 720>; - status = "disabled"; - }; - - scif2: serial@e6e58000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6e58000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, - <&dmac1 0x2b>, <&dmac1 0x2c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 719>; - status = "disabled"; - }; - - scif3: serial@e6ea8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ea8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x2f>, <&dmac0 0x30>, - <&dmac1 0x2f>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 718>; - status = "disabled"; - }; - - scif4: serial@e6ee0000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee0000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, - <&dmac1 0xfb>, <&dmac1 0xfc>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - scif5: serial@e6ee8000 { - compatible = "renesas,scif-r8a7794", - "renesas,rcar-gen2-scif", "renesas,scif"; - reg = <0 0xe6ee8000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, - <&dmac1 0xfd>, <&dmac1 0xfe>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - hscif0: serial@e62c0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 717>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x3a>, - <&dmac1 0x39>, <&dmac1 0x3a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - hscif1: serial@e62c8000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62c8000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>, - <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, - <&dmac1 0x4d>, <&dmac1 0x4e>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - hscif2: serial@e62d0000 { - compatible = "renesas,hscif-r8a7794", - "renesas,rcar-gen2-hscif", "renesas,hscif"; - reg = <0 0xe62d0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, - <&dmac1 0x3b>, <&dmac1 0x3c>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6e88000 { - compatible = "renesas,can-r8a7794", - "renesas,rcar-gen2-can"; - reg = <0 0xe6e88000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 811>; - status = "disabled"; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7794", - "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 810>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7794", - "renesas,rcar_sound-gen2"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, - <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&cpg CPG_CORE R8A7794_CLK_M2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.6", "src.5", "src.4", "src.3", - "src.2", "src.1", - "ctu.0", "ctu.1", - "mix.0", "mix.1", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src-0 { - status = "disabled"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7794", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", - "ch12"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <13>; - }; - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee090000 0 0xc00>, - <0 0xee080000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - - pci1: pci@ee0d0000 { - compatible = "renesas,pci-r8a7794", - "renesas,pci-rcar-gen2"; - device_type = "pci"; - reg = <0 0xee0d0000 0 0xc00>, - <0 0xee0c0000 0 0x1100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - - bus-range = <1 1>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; - interrupt-map-mask = <0xf800 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x10800 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x11000 0 0 0 0>; - phys = <&usb2 0>; - phy-names = "usb"; - }; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi2: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7794", - "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - mmcif0: mmc@ee200000 { - compatible = "renesas,mmcif-r8a7794", - "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = ; - clocks = <&cpg CPG_MOD 315>; - dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, - <&dmac1 0xd1>, <&dmac1 0xd2>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 315>; - reg-io-width = <4>; - status = "disabled"; - }; - - ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794", - "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 813>; - phy-mode = "rmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x2000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vsp@fe928000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe928000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 131>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 131>; - }; - - vsp@fe930000 { - compatible = "renesas,vsp1"; - reg = <0 0xfe930000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 128>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 128>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 119>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7794"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb0: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_rgb1: endpoint { - }; - }; - }; - }; - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7794-cmt0", - "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 124>; - - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7794-cmt1", - "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; - resets = <&cpg 329>; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; -}; diff --git a/arch/arm/dts/r8a77950-salvator-x.dts b/arch/arm/dts/r8a77950-salvator-x.dts deleted file mode 100644 index c6ca61a8ed40eb9d2cc37e9a547b698311fe6fe9..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77950-salvator-x.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77950"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; diff --git a/arch/arm/dts/r8a77950-ulcb.dts b/arch/arm/dts/r8a77950-ulcb.dts deleted file mode 100644 index 5340579931e35f8c3ac9ef8bc4fabd7cfbd5c641..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77950-ulcb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77950"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; diff --git a/arch/arm/dts/r8a77950.dtsi b/arch/arm/dts/r8a77950.dtsi deleted file mode 100644 index 57eb88177e92880e194377d81a3ab1c79a79f444..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77950.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77950) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include "r8a77951.dtsi" - -#undef SOC_HAS_USB2_CH3 - -&audma0 { - iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, - <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, - <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, - <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, - <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, - <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, - <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, - <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; -}; - -&audma1 { - iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, - <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, - <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, - <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, - <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, - <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, - <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, - <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; - -&du { - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; -}; - -&fcpvb1 { - iommus = <&ipmmu_vp0 7>; -}; - -&fcpf1 { - iommus = <&ipmmu_vp0 1>; -}; - -&fcpvi1 { - iommus = <&ipmmu_vp0 9>; -}; - -&fcpvd2 { - iommus = <&ipmmu_vi0 10>; -}; - -&gpio1 { - gpio-ranges = <&pfc 0 32 28>; -}; - -&ipmmu_vi0 { - renesas,ipmmu-main = <&ipmmu_mm 11>; -}; - -&ipmmu_vp0 { - renesas,ipmmu-main = <&ipmmu_mm 12>; -}; - -&ipmmu_vc0 { - renesas,ipmmu-main = <&ipmmu_mm 9>; -}; - -&ipmmu_vc1 { - renesas,ipmmu-main = <&ipmmu_mm 10>; -}; - -&ipmmu_rt { - renesas,ipmmu-main = <&ipmmu_mm 7>; -}; - -&soc { - /delete-node/ dma-controller@e6460000; - /delete-node/ dma-controller@e6470000; - - ipmmu_mp1: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec680000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_sy: iommu@e7730000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7730000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - /delete-node/ iommu@fd950000; - /delete-node/ iommu@fd960000; - /delete-node/ iommu@fd970000; - /delete-node/ iommu@febe0000; - /delete-node/ iommu@fe980000; - - xhci1: usb@ee040000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee040000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 327>; - status = "disabled"; - }; - - /delete-node/ usb@e659c000; - /delete-node/ usb@ee0e0000; - /delete-node/ usb@ee0e0100; - - /delete-node/ usb-phy@ee0e0200; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 117>; - renesas,fcp = <&fcpf2>; - }; - - fcpf2: fcp@fe952000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe952000 0 0x200>; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 613>; - iommus = <&ipmmu_vp0 2>; - }; - - fcpvd3: fcp@fea3f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea3f000 0 0x200>; - clocks = <&cpg CPG_MOD 600>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 600>; - iommus = <&ipmmu_vi0 11>; - }; - - fcpvi2: fcp@fe9cf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9cf000 0 0x200>; - clocks = <&cpg CPG_MOD 609>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 609>; - iommus = <&ipmmu_vp0 10>; - }; - - vspd3: vsp@fea38000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 620>; - - renesas,fcp = <&fcpvd3>; - }; - - vspi2: vsp@fe9c0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9c0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 629>; - - renesas,fcp = <&fcpvi2>; - }; - - csi21: csi2@fea90000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea90000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi21vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi21>; - }; - csi21vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi21>; - }; - csi21vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi21>; - }; - csi21vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi21>; - }; - csi21vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi21>; - }; - csi21vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi21>; - }; - csi21vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi21>; - }; - csi21vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi21>; - }; - }; - }; - }; -}; - -&vin0 { - ports { - port@1 { - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin0>; - }; - }; - }; -}; - -&vin1 { - ports { - port@1 { - vin1csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin1>; - }; - }; - }; -}; - -&vin2 { - ports { - port@1 { - vin2csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin2>; - }; - }; - }; -}; - -&vin3 { - ports { - port@1 { - vin3csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin3>; - }; - }; - }; -}; - -&vin4 { - ports { - port@1 { - vin4csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin4>; - }; - }; - }; -}; - -&vin5 { - ports { - port@1 { - vin5csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin5>; - }; - }; - }; -}; - -&vin6 { - ports { - port@1 { - vin6csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin6>; - }; - }; - }; -}; - -&vin7 { - ports { - port@1 { - vin7csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin7>; - }; - }; - }; -}; diff --git a/arch/arm/dts/r8a77951.dtsi b/arch/arm/dts/r8a77951.dtsi deleted file mode 100644 index 6d15229d25ab101d32436950ecda3f589d7f953b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77951.dtsi +++ /dev/null @@ -1,3485 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77951) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - -#define SOC_HAS_HDMI1 -#define SOC_HAS_SATA -#define SOC_HAS_USB2_CH2 -#define SOC_HAS_USB2_CH3 - -/ { - compatible = "renesas,r8a7795"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - core2 { - cpu = <&a57_2>; - }; - core3 { - cpu = <&a57_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, - <&a53_1>, - <&a53_2>, - <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7795-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7795-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a7795", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a7795", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a7795", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a7795", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a7795", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>, <&cpg 700>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp0: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv2: iommu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv3: iommu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vc1: iommu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vp1: iommu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7795", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7795_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - mlp: mlp@ec520000 { - compatible = "renesas,r8a7795-mlp", - "renesas,rcar-gen3-mlp"; - reg = <0 0xec520000 0 0x800>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 802>; - status = "disabled"; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci2: usb@ee0c0100 { - compatible = "generic-ehci"; - reg = <0 0xee0c0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 2>; - phy-names = "usb"; - companion = <&ohci2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ehci3: usb@ee0e0100 { - compatible = "generic-ehci"; - reg = <0 0xee0e0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 2>; - phy-names = "usb"; - companion = <&ohci3>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; - clocks = <&cpg CPG_MOD 701>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a7795-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a7795-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a7795-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 822>; - }; - - imr-lx4@fe880000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe880000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 821>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 821>; - }; - - imr-lx4@fe890000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe890000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 820>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 820>; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; - }; - - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 615>; - iommus = <&ipmmu_vp0 0>; - }; - - fcpf1: fcp@fe951000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe951000 0 0x200>; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 614>; - iommus = <&ipmmu_vp1 1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 610>; - iommus = <&ipmmu_vp1 9>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - hdmi1: hdmi@feae0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfeae0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 728>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi1_in: endpoint { - remote-endpoint = <&du_out_hdmi1>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, - <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7795-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <6313>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <6313>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a77960-salvator-x.dts b/arch/arm/dts/r8a77960-salvator-x.dts deleted file mode 100644 index d5543f26c4720cea6a7d85594102c5eb1a4b4b75..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77960-salvator-x.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-W - * - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77960"; - compatible = "renesas,salvator-x", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm/dts/r8a77960-ulcb.dts b/arch/arm/dts/r8a77960-ulcb.dts deleted file mode 100644 index 4bfeb1df0488dc7aae25004db69f961787e3915e..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77960-ulcb.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3ULCB board based on r8a77960"; - compatible = "renesas,m3ulcb", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm/dts/r8a77960.dtsi b/arch/arm/dts/r8a77960.dtsi deleted file mode 100644 index 17062ec506beabd5a27a51b3958eda28577b09bf..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77960.dtsi +++ /dev/null @@ -1,3080 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-W (R8A77960) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - -/ { - compatible = "renesas,r8a7796"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7796-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7796"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7796-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7796-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7796-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7796-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a7796", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a7796", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a7796", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a7796", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a7796", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7796", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - mlp: mlp@ec520000 { - compatible = "renesas,r8a7796-mlp", - "renesas,rcar-gen3-mlp"; - reg = <0 0xec520000 0 0x800>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 802>; - status = "disabled"; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a7796-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7796"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7796-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a77965-salvator-x.dts b/arch/arm/dts/r8a77965-salvator-x.dts deleted file mode 100644 index f84c64ed4df7b0459fe43bb7f03770a1542eca86..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77965-salvator-x.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-N - * - * Copyright (C) 2018 Jacopo Mondi - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77965"; - compatible = "renesas,salvator-x", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/arch/arm/dts/r8a77965-ulcb.dts b/arch/arm/dts/r8a77965-ulcb.dts deleted file mode 100644 index 71704b67a20e13b187c182fddb2c018b19cf95d5..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77965-ulcb.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3NULCB board based on r8a77965"; - compatible = "renesas,m3nulcb", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi deleted file mode 100644 index c7582003849135cd0b981a150301e488ead6e864..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77965.dtsi +++ /dev/null @@ -1,2889 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-N (R8A77965) SoC - * - * Copyright (C) 2018 Jacopo Mondi - * - * Based on r8a7796.dtsi - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 - -#define SOC_HAS_SATA - -/ { - compatible = "renesas,r8a77965"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77965_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77965-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77965"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77965-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77965-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77965-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77965-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77965-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77965", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77965", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77965", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77965", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77965", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77965", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a77965-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77965_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77965_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77965", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77965-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77965", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a77965-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77965_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - mlp: mlp@ec520000 { - compatible = "renesas,r8a77965-mlp", - "renesas,rcar-gen3-mlp"; - reg = <0 0xec520000 0 0x800>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 802>; - status = "disabled"; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77965", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77965-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77965-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a77965", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 318>; - iommu-map = <0 &ipmmu_hc 1 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 611>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a77965-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A77965_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77965"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a77965-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - trips { - target: trip-point1 { - /* miliCelsius */ - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts deleted file mode 100644 index 405404c0843d9747aeffc014d52a07db5144415e..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77970-eagle.dts +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Eagle board with R-Car V3M - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" -#include - -/ { - model = "Renesas Eagle board based on r8a77970"; - compatible = "renesas,eagle", "renesas,r8a77970"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - serial0 = &scif0; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - d3p3: regulator-fixed { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - - vcc-supply = <&d3p3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - x1_clk: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - rx-internal-delay-ps = <1800>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max9286_out0>; - }; - }; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, <&x1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - gmsl0: gmsl-deserializer@48 { - compatible = "maxim,max9286"; - reg = <0x48>; - - maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; - enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - max9286_out0: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - }; - - i2c-mux { - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - status = "disabled"; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - status = "disabled"; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - status = "disabled"; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - status = "disabled"; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c3_pins: i2c3 { - groups = "i2c3_a"; - function = "i2c3"; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/arch/arm/dts/r8a77970-v3msk.dts b/arch/arm/dts/r8a77970-v3msk.dts deleted file mode 100644 index e36999e91af533263b22b0177d4f5ccc42fc89ba..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77970-v3msk.dts +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3M Starter Kit board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" -#include - -/ { - model = "Renesas V3M Starter Kit board"; - compatible = "renesas,v3msk", "renesas,r8a77970"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - serial0 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc_d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - osc5_clk: osc5-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc_d1_8v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_d3_3v: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_vddq_vin0: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "VCC_VDDQ_VIN0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - rx-internal-delay-ps = <1800>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc5_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc_d1_8v>; - dvdd-supply = <&vcc_d1_8v>; - pvdd-supply = <&vcc_d1_8v>; - bgvdd-supply = <&vcc_d1_8v>; - dvdd-3v-supply = <&vcc_d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_d3_3v>; - vqmmc-supply = <&vcc_vddq_vin0>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pfc { - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc_3_3v { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <3300>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi deleted file mode 100644 index ed6e2e47c60479efbb28f43679ebd222e936c9f1..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77970.dtsi +++ /dev/null @@ -1,1220 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3M (R8A77970) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77970"; - #address-cells = <2>; - #size-cells = <2>; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77970_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77970-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 6>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77970-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77970"; - reg = <0 0xe6190000 0 0x10>, - <0 0xe6190100 0 0x120>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac1 0x97>, <&dmac1 0x96>, - <&dmac2 0x97>, <&dmac2 0x96>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac1 0x99>, <&dmac1 0x98>, - <&dmac2 0x99>, <&dmac2 0x98>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77970-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77970_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77970", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 209>; - dmas = <&dmac1 0x45>, <&dmac1 0x44>, - <&dmac2 0x45>, <&dmac2 0x44>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 208>; - dmas = <&dmac1 0x47>, <&dmac1 0x46>, - <&dmac2 0x47>, <&dmac2 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77970", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77970-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77970-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77970"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77970-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts deleted file mode 100644 index 68d1f1d53b3a38b41d69609dbdf9e15072323b13..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77980-condor.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Condor board with R-Car V3H - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" -#include "condor-common.dtsi" - -/ { - model = "Renesas Condor board based on r8a77980"; - compatible = "renesas,condor", "renesas,r8a77980"; -}; - -&i2c0 { - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts deleted file mode 100644 index 77d22df25fffac6d41e9ca64c7f2fb39ee91580b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77980-v3hsk.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3H Starter Kit board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" -#include - -/ { - model = "Renesas V3H Starter Kit board"; - compatible = "renesas,v3hsk", "renesas,r8a77980"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc3v3_d5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc1v8_d4: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_D4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3_d5: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_D5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc1v8_d4>; - dvdd-supply = <&vcc1v8_d4>; - pvdd-supply = <&vcc1v8_d4>; - bgvdd-supply = <&vcc1v8_d4>; - dvdd-3v-supply = <&vcc3v3_d5>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi deleted file mode 100644 index 5ed2daaca1f006493f037e7e84a782161d904219..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77980.dtsi +++ /dev/null @@ -1,1625 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3H (R8A77980) SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77980"; - #address-cells = <2>; - #size-cells = <2>; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <2>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <3>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77980_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77980-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 25>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77980"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77980-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77980-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77980-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77980-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77980-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, - <&dmac2 0x9b>, <&dmac2 0x9a>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - pcie_phy: pcie-phy@e65d0000 { - compatible = "renesas,r8a77980-pcie-phy"; - reg = <0 0xe65d0000 0 0x8000>; - #phy-cells = <0>; - clocks = <&cpg CPG_MOD 319>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77980-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77980_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77980", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <2000>; - iommus = <&ipmmu_ds1 33>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77980", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - status = "disabled"; - renesas,id = <1>; - resets = <&cpg 810>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - vin8: video@e6ef8000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 628>; - renesas,id = <8>; - status = "disabled"; - }; - - vin9: video@e6ef9000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,id = <9>; - status = "disabled"; - }; - - vin10: video@e6efa000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efa000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 625>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 625>; - renesas,id = <10>; - status = "disabled"; - }; - - vin11: video@e6efb000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 618>; - renesas,id = <11>; - status = "disabled"; - }; - - vin12: video@e6efc000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 612>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 612>; - renesas,id = <12>; - status = "disabled"; - }; - - vin13: video@e6efd000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 608>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 608>; - renesas,id = <13>; - status = "disabled"; - }; - - vin14: video@e6efe000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efe000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 605>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 605>; - renesas,id = <14>; - status = "disabled"; - }; - - vin15: video@e6eff000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6eff000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 604>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 604>; - renesas,id = <15>; - status = "disabled"; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - gether: ethernet@e7400000 { - compatible = "renesas,gether-r8a77980"; - reg = <0 0xe7400000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 813>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77980_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip0: iommu@e7b00000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7b00000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip1: iommu@e7960000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 11>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77980", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77980-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a77980", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - phys = <&pcie_phy>; - phy-names = "pcie"; - iommu-map = <0 &ipmmu_vi0 5 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77980"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77980-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor1-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor2-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts deleted file mode 100644 index 9da0fd08f8c46b35f7846a942608a21f7cdc8ca8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Ebisu board with R-Car E3 - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77990.dtsi" -#include "ebisu.dtsi" - -/ { - model = "Renesas Ebisu board based on r8a77990"; - compatible = "renesas,ebisu", "renesas,r8a77990"; -}; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi deleted file mode 100644 index 4c545eff9b423267ca0de4815155cbc3404dc5c0..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77990.dtsi +++ /dev/null @@ -1,2154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E3 (R8A77990) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77990"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A77990_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A77990_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77990_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77990-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77990"; - reg = <0 0xe6060000 0 0x508>; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77990", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77990-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77990-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77990-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77990-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77990"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77990", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77990", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77990", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77990", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77990", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77990", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77990_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77990", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77990-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac0 0x28>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac0 0x2a>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac0 0x2c>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac0 0x2e>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - mlp: mlp@ec520000 { - compatible = "renesas,r8a77990-mlp", - "renesas,rcar-gen3-mlp"; - reg = <0 0xec520000 0 0x800>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 802>; - status = "disabled"; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77990", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77990-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77990", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77990-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77990", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR/IOMMU as inbound ranges */ - dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 319>; - iommu-map = <0 &ipmmu_hc 0 1>; - iommu-map-mask = <0>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77990-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77990"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts deleted file mode 100644 index 384825617fcff1ff6fb1d68d631689d47ce94a90..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77995-draak.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Draak board with R-Car D3 - * - * Copyright (C) 2016-2018 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -/dts-v1/; -#include "r8a77995.dtsi" -#include "draak.dtsi" - -/ { - model = "Renesas Draak board based on r8a77995"; - compatible = "renesas,draak", "renesas,r8a77995"; -}; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi deleted file mode 100644 index e25024a7b66ccbe3ec136c68032a6a1bdf01f45c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a77995.dtsi +++ /dev/null @@ -1,1473 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car D3 (R8A77995) SoC - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77995"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77995_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A77995_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77995-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 9>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 14>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77995-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77995-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77995-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77995-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77995-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77995-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77995-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77995"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77995", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77995", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77995", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77995", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77995", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77995", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77995-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77995", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <1800>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77995"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required if simple-card - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, - <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&cpg CPG_CORE R8A77995_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.4", "ssi.3", - "src.6", "src.5", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_i"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1011>, <&cpg 1012>; - reset-names = "ssi-all", - "ssi.4", "ssi.3"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - mlp: mlp@ec520000 { - compatible = "renesas,r8a77995-mlp", - "renesas,rcar-gen3-mlp"; - reg = <0 0xec520000 0 0x800>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 802>; - status = "disabled"; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77995", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; - clock-names = "core", "clkh"; - max-frequency = <200000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77995-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspbs: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77995"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm/dts/r8a779a0-falcon-cpu.dtsi b/arch/arm/dts/r8a779a0-falcon-cpu.dtsi deleted file mode 100644 index 99b73e21c82c2b18261fd98bc29be7982d926c09..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779a0-falcon-cpu.dtsi +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon CPU board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include - -#include "r8a779a0.dtsi" - -/ { - model = "Renesas Falcon CPU board"; - compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - serial0 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW47"; - wakeup-source; - debounce-interval = <20>; - }; - - key-2 { - gpios = <&gpio6 19 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW48"; - wakeup-source; - debounce-interval = <20>; - }; - - key-3 { - gpios = <&gpio6 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW49"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - led-2 { - gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - led-3 { - gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x80000000>; - }; - - mini-dp-con { - compatible = "dp-connector"; - label = "CN5"; - type = "mini"; - - port { - mini_dp_con_in: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - - reg_1p2v: regulator-1p2v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&dsi0 { - status = "okay"; - - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - bridge@2c { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - - clocks = <&sn65dsi86_refclk>; - clock-names = "refclk"; - - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - vccio-supply = <®_1p8v>; - vpll-supply = <®_1p8v>; - vcca-supply = <®_1p2v>; - vcc-supply = <®_1p2v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; - }; - }; - }; - }; -}; - -&i2c6 { - pinctrl-0 = <&i2c6_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - i2c6_pins: i2c6 { - groups = "i2c6"; - function = "i2c6"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - keys_pins: keys { - pins = "GP_6_18", "GP_6_19", "GP_6_20"; - bias-pull-up; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data", "scif0_ctrl"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x0 0xcc0000>; - read-only; - }; - user@cc0000 { - reg = <0xcc0000 0x3340000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi deleted file mode 100644 index dbc8dcab109d15db556bd079b66642b3af6dfa18..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon CSI/DSI sub-board - * - * Copyright (C) 2021 Glider bv - */ - -#include - -&csi40 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max96712_out0>; - }; - }; - }; -}; - -&csi42 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi42_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max96712_out1>; - }; - }; - }; -}; - -&csi43 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi43_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max96712_out2>; - }; - }; - }; -}; - -&i2c0 { - pca9654_a: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9654_b: gpio@22 { - compatible = "onnn,pca9654"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9654_c: gpio@23 { - compatible = "onnn,pca9654"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@52 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "csi-dsi-sub-board-id"; - reg = <0x52>; - pagesize = <8>; - }; -}; - -&i2c1 { - gmsl0: gmsl-deserializer@49 { - compatible = "maxim,max96712"; - reg = <0x49>; - enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - max96712_out0: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - }; - }; - - gmsl1: gmsl-deserializer@4b { - compatible = "maxim,max96712"; - reg = <0x4b>; - enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - max96712_out1: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - lane-polarities = <0 0 0 0 1>; - remote-endpoint = <&csi42_in>; - }; - }; - }; - }; - - gmsl2: gmsl-deserializer@6b { - compatible = "maxim,max96712"; - reg = <0x6b>; - enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - max96712_out2: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - lane-polarities = <0 0 0 0 1>; - remote-endpoint = <&csi43_in>; - }; - }; - }; - }; -}; - -&isp0 { - status = "okay"; -}; - -&isp2 { - status = "okay"; -}; - -&isp3 { - status = "okay"; -}; - -&vin00 { - status = "okay"; -}; - -&vin01 { - status = "okay"; -}; - -&vin02 { - status = "okay"; -}; - -&vin03 { - status = "okay"; -}; - -&vin04 { - status = "okay"; -}; - -&vin05 { - status = "okay"; -}; - -&vin06 { - status = "okay"; -}; - -&vin07 { - status = "okay"; -}; - -&vin16 { - status = "okay"; -}; - -&vin17 { - status = "okay"; -}; - -&vin18 { - status = "okay"; -}; - -&vin19 { - status = "okay"; -}; - -&vin20 { - status = "okay"; -}; - -&vin21 { - status = "okay"; -}; - -&vin22 { - status = "okay"; -}; - -&vin23 { - status = "okay"; -}; - -&vin24 { - status = "okay"; -}; - -&vin25 { - status = "okay"; -}; - -&vin26 { - status = "okay"; -}; - -&vin27 { - status = "okay"; -}; - -&vin28 { - status = "okay"; -}; - -&vin29 { - status = "okay"; -}; - -&vin30 { - status = "okay"; -}; - -&vin31 { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a779a0-falcon-ethernet.dtsi b/arch/arm/dts/r8a779a0-falcon-ethernet.dtsi deleted file mode 100644 index e11bf9ace7768d54c6fdb9b34345c744e6351aa0..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779a0-falcon-ethernet.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon Ethernet sub-board - * - * Copyright (C) 2021 Glider bv - */ - -&i2c0 { - eeprom@53 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "ethernet-sub-board-id"; - reg = <0x53>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts deleted file mode 100644 index 63db822e5f4662b659786568cd2288c1c331e18f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779a0-falcon.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779a0-falcon-cpu.dtsi" -#include "r8a779a0-falcon-csi-dsi.dtsi" -#include "r8a779a0-falcon-ethernet.dtsi" - -/ { - model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; - compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; - - aliases { - ethernet0 = &avb0; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - }; -}; - -&can_clk { - clock-frequency = <40000000>; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; - - channel1 { - status = "okay"; - }; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&pfc { - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - - }; - - can_clk_pins: can-clk { - groups = "can_clk"; - function = "can_clk"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - canfd1_pins: canfd1 { - groups = "canfd1_data"; - function = "canfd1"; - }; -}; diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi deleted file mode 100644 index 4e67a03564971b89a5b2fb7564b2eb93aa549819..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779a0.dtsi +++ /dev/null @@ -1,2915 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3U (R8A779A0) SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a779a0"; - #address-cells = <2>; - #size-cells = <2>; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a76_0: cpu@0 { - compatible = "arm,cortex-a76"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; - next-level-cache = <&L3_CA76_0>; - clocks = <&cpg CPG_CORE R8A779A0_CLK_Z0>; - }; - - L3_CA76_0: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A779A0_PD_A2E0D0>; - cache-unified; - cache-level = <3>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a779a0-wdt", - "renesas,rcar-gen4-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - status = "disabled"; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a779a0"; - reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, - <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, - <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, - <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, - <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; - }; - - gpio0: gpio@e6058180 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 28>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@e6050180 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 32 31>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@e6050980 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 64 25>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 96 17>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 128 27>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 160 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@e6068180 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6068180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 192 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@e6068980 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6068980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 224 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@e6069180 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6069180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 256 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio9: gpio@e6069980 { - compatible = "renesas,gpio-r8a779a0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6069980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 288 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a779a0-cmt0", - "renesas,rcar-gen4-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 910>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 911>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 912>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 913>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 913>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779a0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779a0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779a0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6190000 { - compatible = "renesas,r8a779a0-thermal"; - reg = <0 0xe6190000 0 0x200>, - <0 0xe6198000 0 0x200>, - <0 0xe61a0000 0 0x200>, - <0 0xe61a8000 0 0x200>, - <0 0xe61b0000 0 0x200>; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 713>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 714>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 715>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 716>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 717>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 521>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 521>; - dmas = <&dmac1 0x97>, <&dmac1 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - dmas = <&dmac1 0x99>, <&dmac1 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - dmas = <&dmac1 0x9b>, <&dmac1 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 524>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 524>; - dmas = <&dmac1 0x9d>, <&dmac1 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 514>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 515>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - canfd: can@e6660000 { - compatible = "renesas,r8a779a0-canfd", - "renesas,rcar-gen4-canfd"; - reg = <0 0xe6660000 0 0x8000>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 328>, - <&cpg CPG_CORE R8A779A0_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; - assigned-clock-rates = <80000000>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - - channel2 { - status = "disabled"; - }; - - channel3 { - status = "disabled"; - }; - - channel4 { - status = "disabled"; - }; - - channel5 { - status = "disabled"; - }; - - channel6 { - status = "disabled"; - }; - - channel7 { - status = "disabled"; - }; - }; - - avb0: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 211>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 211>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb1: ethernet@e6810000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 212>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 212>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb2: ethernet@e6820000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6820000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 213>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 213>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb3: ethernet@e6830000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6830000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 214>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 214>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb4: ethernet@e6840000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6840000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 215>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 215>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb5: ethernet@e6850000 { - compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6850000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 216>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 216>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a779a0", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 718>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 618>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 619>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 619>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 620>; - dmas = <&dmac1 0x45>, <&dmac1 0x44>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 621>; - dmas = <&dmac1 0x47>, <&dmac1 0x46>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof4: spi@e6c20000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 622>; - dmas = <&dmac1 0x49>, <&dmac1 0x48>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof5: spi@e6c28000 { - compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c28000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 623>; - dmas = <&dmac1 0x4b>, <&dmac1 0x4a>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin00: video@e6ef0000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 730>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 730>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin00isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin00>; - }; - }; - }; - }; - - vin01: video@e6ef1000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 731>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 731>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin01isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin01>; - }; - }; - }; - }; - - vin02: video@e6ef2000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 800>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 800>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin02isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin02>; - }; - }; - }; - }; - - vin03: video@e6ef3000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 801>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 801>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin03isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin03>; - }; - }; - }; - }; - - vin04: video@e6ef4000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 802>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin04isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin04>; - }; - }; - }; - }; - - vin05: video@e6ef5000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 803>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 803>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin05isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin05>; - }; - }; - }; - }; - - vin06: video@e6ef6000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin06isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin06>; - }; - }; - }; - }; - - vin07: video@e6ef7000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin07isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin07>; - }; - }; - }; - }; - - vin08: video@e6ef8000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <8>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin08isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin08>; - }; - }; - }; - }; - - vin09: video@e6ef9000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ef9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <9>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin09isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin09>; - }; - }; - }; - }; - - vin10: video@e6efa000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6efa000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <10>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin10isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin10>; - }; - }; - }; - }; - - vin11: video@e6efb000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6efb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <11>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin11isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin11>; - }; - }; - }; - }; - - vin12: video@e6efc000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6efc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <12>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin12isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin12>; - }; - }; - }; - }; - - vin13: video@e6efd000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6efd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <13>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin13isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin13>; - }; - }; - }; - }; - - vin14: video@e6efe000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6efe000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 812>; - renesas,id = <14>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin14isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin14>; - }; - }; - }; - }; - - vin15: video@e6eff000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6eff000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 813>; - renesas,id = <15>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin15isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin15>; - }; - }; - }; - }; - - vin16: video@e6ed0000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 814>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 814>; - renesas,id = <16>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin16isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin16>; - }; - }; - }; - }; - - vin17: video@e6ed1000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 815>; - renesas,id = <17>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin17isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin17>; - }; - }; - }; - }; - - vin18: video@e6ed2000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 816>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 816>; - renesas,id = <18>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin18isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin18>; - }; - }; - }; - }; - - vin19: video@e6ed3000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 817>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 817>; - renesas,id = <19>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin19isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin19>; - }; - }; - }; - }; - - vin20: video@e6ed4000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 818>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 818>; - renesas,id = <20>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin20isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin20>; - }; - }; - }; - }; - - vin21: video@e6ed5000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 819>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 819>; - renesas,id = <21>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin21isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin21>; - }; - }; - }; - }; - - vin22: video@e6ed6000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 820>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 820>; - renesas,id = <22>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin22isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin22>; - }; - }; - }; - }; - - vin23: video@e6ed7000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 821>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 821>; - renesas,id = <23>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin23isp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&isp2vin23>; - }; - }; - }; - }; - - vin24: video@e6ed8000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 822>; - renesas,id = <24>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin24isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin24>; - }; - }; - }; - }; - - vin25: video@e6ed9000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ed9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 823>; - renesas,id = <25>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin25isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin25>; - }; - }; - }; - }; - - vin26: video@e6eda000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6eda000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 824>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 824>; - renesas,id = <26>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin26isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin26>; - }; - }; - }; - }; - - vin27: video@e6edb000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6edb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 825>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 825>; - renesas,id = <27>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin27isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin27>; - }; - }; - }; - }; - - vin28: video@e6edc000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6edc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 826>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 826>; - renesas,id = <28>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin28isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin28>; - }; - }; - }; - }; - - vin29: video@e6edd000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6edd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 827>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 827>; - renesas,id = <29>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin29isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin29>; - }; - }; - }; - }; - - vin30: video@e6ede000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6ede000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 828>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 828>; - renesas,id = <30>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin30isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin30>; - }; - }; - }; - }; - - vin31: video@e6edf000 { - compatible = "renesas,vin-r8a779a0"; - reg = <0 0xe6edf000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 829>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 829>; - renesas,id = <31>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin31isp3: endpoint@3 { - reg = <3>; - remote-endpoint = <&isp3vin31>; - }; - }; - }; - }; - - dmac1: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779a0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7350000 0 0x1000>, - <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15"; - clocks = <&cpg CPG_MOD 709>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 709>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - dmac2: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779a0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7351000 0 0x1000>, - <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 710>; - clock-names = "fck"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 710>; - #dma-cells = <1>; - dma-channels = <8>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779a0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a779a0-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@eed80000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@eedc0000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeedc0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@eee80000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeee80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@eeec0000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeeec0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_3dg: iommu@eee00000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeee00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip0: iommu@eef00000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeef00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip1: iommu@eef40000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeef40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779a0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeefc0000 0 0x20000>; - interrupts = , - ; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = ; - }; - - fcpvd0: fcp@fea10000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea10000 0 0x200>; - clocks = <&cpg CPG_MOD 508>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 508>; - }; - - fcpvd1: fcp@fea11000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea11000 0 0x200>; - clocks = <&cpg CPG_MOD 509>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 509>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 830>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 830>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 831>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 831>; - - renesas,fcp = <&fcpvd1>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a779a0-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 331>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi40isp0: endpoint { - remote-endpoint = <&isp0csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a779a0-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 400>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 400>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi41isp1: endpoint { - remote-endpoint = <&isp1csi41>; - }; - }; - }; - }; - - csi42: csi2@fed60000 { - compatible = "renesas,r8a779a0-csi2"; - reg = <0 0xfed60000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 401>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 401>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi42isp2: endpoint { - remote-endpoint = <&isp2csi42>; - }; - }; - }; - }; - - csi43: csi2@fed70000 { - compatible = "renesas,r8a779a0-csi2"; - reg = <0 0xfed70000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi43isp3: endpoint { - remote-endpoint = <&isp3csi43>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a779a0"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 411>; - clock-names = "du.0"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 411>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_dsi0: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - du_out_dsi1: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - - isp0: isp@fed00000 { - compatible = "renesas,r8a779a0-isp"; - reg = <0 0xfed00000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 612>; - power-domains = <&sysc R8A779A0_PD_A3ISP01>; - resets = <&cpg 612>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp0csi40: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi40isp0>; - }; - }; - - port@1 { - reg = <1>; - isp0vin00: endpoint { - remote-endpoint = <&vin00isp0>; - }; - }; - - port@2 { - reg = <2>; - isp0vin01: endpoint { - remote-endpoint = <&vin01isp0>; - }; - }; - - port@3 { - reg = <3>; - isp0vin02: endpoint { - remote-endpoint = <&vin02isp0>; - }; - }; - - port@4 { - reg = <4>; - isp0vin03: endpoint { - remote-endpoint = <&vin03isp0>; - }; - }; - - port@5 { - reg = <5>; - isp0vin04: endpoint { - remote-endpoint = <&vin04isp0>; - }; - }; - - port@6 { - reg = <6>; - isp0vin05: endpoint { - remote-endpoint = <&vin05isp0>; - }; - }; - - port@7 { - reg = <7>; - isp0vin06: endpoint { - remote-endpoint = <&vin06isp0>; - }; - }; - - port@8 { - reg = <8>; - isp0vin07: endpoint { - remote-endpoint = <&vin07isp0>; - }; - }; - }; - }; - - isp1: isp@fed20000 { - compatible = "renesas,r8a779a0-isp"; - reg = <0 0xfed20000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A779A0_PD_A3ISP01>; - resets = <&cpg 613>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp1csi41: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi41isp1>; - }; - }; - - port@1 { - reg = <1>; - isp1vin08: endpoint { - remote-endpoint = <&vin08isp1>; - }; - }; - - port@2 { - reg = <2>; - isp1vin09: endpoint { - remote-endpoint = <&vin09isp1>; - }; - }; - - port@3 { - reg = <3>; - isp1vin10: endpoint { - remote-endpoint = <&vin10isp1>; - }; - }; - - port@4 { - reg = <4>; - isp1vin11: endpoint { - remote-endpoint = <&vin11isp1>; - }; - }; - - port@5 { - reg = <5>; - isp1vin12: endpoint { - remote-endpoint = <&vin12isp1>; - }; - }; - - port@6 { - reg = <6>; - isp1vin13: endpoint { - remote-endpoint = <&vin13isp1>; - }; - }; - - port@7 { - reg = <7>; - isp1vin14: endpoint { - remote-endpoint = <&vin14isp1>; - }; - }; - - port@8 { - reg = <8>; - isp1vin15: endpoint { - remote-endpoint = <&vin15isp1>; - }; - }; - }; - }; - - isp2: isp@fed30000 { - compatible = "renesas,r8a779a0-isp"; - reg = <0 0xfed30000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A779A0_PD_A3ISP23>; - resets = <&cpg 614>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp2csi42: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi42isp2>; - }; - }; - - port@1 { - reg = <1>; - isp2vin16: endpoint { - remote-endpoint = <&vin16isp2>; - }; - }; - - port@2 { - reg = <2>; - isp2vin17: endpoint { - remote-endpoint = <&vin17isp2>; - }; - }; - - port@3 { - reg = <3>; - isp2vin18: endpoint { - remote-endpoint = <&vin18isp2>; - }; - }; - - port@4 { - reg = <4>; - isp2vin19: endpoint { - remote-endpoint = <&vin19isp2>; - }; - }; - - port@5 { - reg = <5>; - isp2vin20: endpoint { - remote-endpoint = <&vin20isp2>; - }; - }; - - port@6 { - reg = <6>; - isp2vin21: endpoint { - remote-endpoint = <&vin21isp2>; - }; - }; - - port@7 { - reg = <7>; - isp2vin22: endpoint { - remote-endpoint = <&vin22isp2>; - }; - }; - - port@8 { - reg = <8>; - isp2vin23: endpoint { - remote-endpoint = <&vin23isp2>; - }; - }; - }; - }; - - isp3: isp@fed40000 { - compatible = "renesas,r8a779a0-isp"; - reg = <0 0xfed40000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A779A0_PD_A3ISP23>; - resets = <&cpg 615>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp3csi43: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi43isp3>; - }; - }; - - port@1 { - reg = <1>; - isp3vin24: endpoint { - remote-endpoint = <&vin24isp3>; - }; - }; - - port@2 { - reg = <2>; - isp3vin25: endpoint { - remote-endpoint = <&vin25isp3>; - }; - }; - - port@3 { - reg = <3>; - isp3vin26: endpoint { - remote-endpoint = <&vin26isp3>; - }; - }; - - port@4 { - reg = <4>; - isp3vin27: endpoint { - remote-endpoint = <&vin27isp3>; - }; - }; - - port@5 { - reg = <5>; - isp3vin28: endpoint { - remote-endpoint = <&vin28isp3>; - }; - }; - - port@6 { - reg = <6>; - isp3vin29: endpoint { - remote-endpoint = <&vin29isp3>; - }; - }; - - port@7 { - reg = <7>; - isp3vin30: endpoint { - remote-endpoint = <&vin30isp3>; - }; - }; - - port@8 { - reg = <8>; - isp3vin31: endpoint { - remote-endpoint = <&vin31isp3>; - }; - }; - }; - }; - - dsi0: dsi-encoder@fed80000 { - compatible = "renesas,r8a779a0-dsi-csi2-tx"; - reg = <0 0xfed80000 0 0x10000>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 415>, - <&cpg CPG_CORE R8A779A0_CLK_DSI>, - <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; - clock-names = "fck", "dsi", "pll"; - resets = <&cpg 415>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&du_out_dsi0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - dsi1: dsi-encoder@fed90000 { - compatible = "renesas,r8a779a0-dsi-csi2-tx"; - reg = <0 0xfed90000 0 0x10000>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 416>, - <&cpg CPG_CORE R8A779A0_CLK_DSI>, - <&cpg CPG_CORE R8A779A0_CLK_CL16MCK>; - clock-names = "fck", "dsi", "pll"; - resets = <&cpg 416>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&du_out_dsi1>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor1_thermal: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor2_thermal: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor3_thermal: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor4_thermal: sensor4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 3>; - - trips { - sensor4_crit: sensor4-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor5_thermal: sensor5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 4>; - - trips { - sensor5_crit: sensor5-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/r8a779f0-spider-cpu.dtsi b/arch/arm/dts/r8a779f0-spider-cpu.dtsi deleted file mode 100644 index 5cbde8e8fcd5cac30b7ef8c5109867b32fd4a2a8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779f0-spider-cpu.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the Spider CPU board - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include -#include - -#include "r8a779f0.dtsi" - -/ { - model = "Renesas Spider CPU board"; - compatible = "renesas,spider-cpu", "renesas,r8a779f0"; - - aliases { - serial0 = &hscif0; - serial1 = &scif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:1843200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-7 { - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <7>; - }; - - led-8 { - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <8>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - rc21012_ufs: clk-rc21012-ufs { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&extal_clk { - clock-frequency = <20000000>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - gpio_exp_20: gpio@20 { - compatible = "ti,tca9554"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -/* - * This board also has a microSD slot which we will not support upstream - * because we cannot directly switch voltages in software. - */ -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c4_pins: i2c4 { - groups = "i2c4"; - function = "i2c4"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - scif0_pins: scif0 { - groups = "scif0_data", "scif0_ctrl"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; -}; - -&ufs { - status = "okay"; -}; - -&ufs30_clk { - compatible = "gpio-gate-clock"; - clocks = <&rc21012_ufs>; - enable-gpios = <&gpio_exp_20 4 GPIO_ACTIVE_LOW>; - /delete-property/ clock-frequency; -}; diff --git a/arch/arm/dts/r8a779f0-spider-ethernet.dtsi b/arch/arm/dts/r8a779f0-spider-ethernet.dtsi deleted file mode 100644 index 33c1015e9ab38e97565acfae6df3df1f92ab025c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779f0-spider-ethernet.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Spider Ethernet sub-board - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -ð_serdes { - status = "okay"; -}; - -&i2c4 { - eeprom@52 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "ethernet-sub-board"; - reg = <0x52>; - pagesize = <8>; - }; -}; - -&pfc { - tsn0_pins: tsn0 { - groups = "tsn0_mdio_b", "tsn0_link_b"; - function = "tsn0"; - power-source = <1800>; - }; - - tsn1_pins: tsn1 { - groups = "tsn1_mdio_b", "tsn1_link_b"; - function = "tsn1"; - power-source = <1800>; - }; - - tsn2_pins: tsn2 { - groups = "tsn2_mdio_b", "tsn2_link_b"; - function = "tsn2"; - power-source = <1800>; - }; -}; - -&rswitch { - pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; - pinctrl-names = "default"; - status = "okay"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phy-handle = <&u101>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u101: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - port@1 { - reg = <1>; - phy-handle = <&u201>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u201: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupt-parent = <&gpio3>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - port@2 { - reg = <2>; - phy-handle = <&u301>; - phy-mode = "sgmii"; - phys = <ð_serdes 2>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u301: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupt-parent = <&gpio3>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/r8a779f0-spider.dts b/arch/arm/dts/r8a779f0-spider.dts deleted file mode 100644 index f139cc4feb37da51c74e565fc3233192125f10de..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779f0-spider.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the Spider CPU and BreakOut boards - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779f0-spider-cpu.dtsi" -#include "r8a779f0-spider-ethernet.dtsi" - -/ { - model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; - compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; -}; - -&i2c4 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi deleted file mode 100644 index ecdd5a523fa3443f3d6392acd2bca92158a9ef45..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779f0.dtsi +++ /dev/null @@ -1,1193 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a779f0"; - #address-cells = <2>; - #size-cells = <2>; - - cluster01_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - opp-suspend; - }; - }; - - cluster23_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a55_0>; - }; - core1 { - cpu = <&a55_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a55_2>; - }; - core1 { - cpu = <&a55_3>; - }; - }; - - cluster2 { - core0 { - cpu = <&a55_4>; - }; - core1 { - cpu = <&a55_5>; - }; - }; - - cluster3 { - core0 { - cpu = <&a55_6>; - }; - core1 { - cpu = <&a55_7>; - }; - }; - }; - - a55_0: cpu@0 { - compatible = "arm,cortex-a55"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; - next-level-cache = <&L3_CA55_0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; - operating-points-v2 = <&cluster01_opp>; - }; - - a55_1: cpu@100 { - compatible = "arm,cortex-a55"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; - next-level-cache = <&L3_CA55_0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; - operating-points-v2 = <&cluster01_opp>; - }; - - a55_2: cpu@10000 { - compatible = "arm,cortex-a55"; - reg = <0x10000>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; - next-level-cache = <&L3_CA55_1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; - operating-points-v2 = <&cluster01_opp>; - }; - - a55_3: cpu@10100 { - compatible = "arm,cortex-a55"; - reg = <0x10100>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; - next-level-cache = <&L3_CA55_1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; - operating-points-v2 = <&cluster01_opp>; - }; - - a55_4: cpu@20000 { - compatible = "arm,cortex-a55"; - reg = <0x20000>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; - next-level-cache = <&L3_CA55_2>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; - operating-points-v2 = <&cluster23_opp>; - }; - - a55_5: cpu@20100 { - compatible = "arm,cortex-a55"; - reg = <0x20100>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; - next-level-cache = <&L3_CA55_2>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; - operating-points-v2 = <&cluster23_opp>; - }; - - a55_6: cpu@30000 { - compatible = "arm,cortex-a55"; - reg = <0x30000>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; - next-level-cache = <&L3_CA55_3>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; - operating-points-v2 = <&cluster23_opp>; - }; - - a55_7: cpu@30100 { - compatible = "arm,cortex-a55"; - reg = <0x30100>; - device_type = "cpu"; - power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; - next-level-cache = <&L3_CA55_3>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; - operating-points-v2 = <&cluster23_opp>; - }; - - L3_CA55_0: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A779F0_PD_A2E0D0>; - cache-unified; - cache-level = <3>; - }; - - L3_CA55_1: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A779F0_PD_A2E0D1>; - cache-unified; - cache-level = <3>; - }; - - L3_CA55_2: cache-controller-2 { - compatible = "cache"; - power-domains = <&sysc R8A779F0_PD_A2E1D0>; - cache-unified; - cache-level = <3>; - }; - - L3_CA55_3: cache-controller-3 { - compatible = "cache"; - power-domains = <&sysc R8A779F0_PD_A2E1D1>; - cache-unified; - cache-level = <3>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a779f0-wdt", - "renesas,rcar-gen4-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - status = "disabled"; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a779f0"; - reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, - <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; - }; - - gpio0: gpio@e6050180 { - compatible = "renesas,gpio-r8a779f0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@e6050980 { - compatible = "renesas,gpio-r8a779f0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 32 25>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@e6051180 { - compatible = "renesas,gpio-r8a779f0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6051180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 64 17>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@e6051980 { - compatible = "renesas,gpio-r8a779f0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6051980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 96 19>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a779f0-cmt0", - "renesas,rcar-gen4-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 910>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a779f0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 911>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a779f0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 912>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a779f0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 913>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 913>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779f0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779f0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779f0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a779f0-thermal"; - /* The 4th sensor is in control domain and not for Linux */ - reg = <0 0xe6198000 0 0x200>, - <0 0xe61a0000 0 0x200>, - <0 0xe61a8000 0 0x200>; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 713>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 714>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 715>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 716>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 717>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - eth_serdes: phy@e6444000 { - compatible = "renesas,r8a779f0-ether-serdes"; - reg = <0 0xe6444000 0 0x2800>; - clocks = <&cpg CPG_MOD 1506>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 1506>; - #phy-cells = <1>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - dmas = <&dmac0 0x91>, <&dmac0 0x90>, - <&dmac1 0x91>, <&dmac1 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - dmas = <&dmac0 0x93>, <&dmac0 0x92>, - <&dmac1 0x93>, <&dmac1 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 520>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - dmas = <&dmac0 0x95>, <&dmac0 0x94>, - <&dmac1 0x95>, <&dmac1 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 521>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 521>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>, - <&dmac1 0x97>, <&dmac1 0x96>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>, - <&dmac1 0x99>, <&dmac1 0x98>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a779f0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, - <&dmac1 0x9b>, <&dmac1 0x9a>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a779f0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x31>, <&dmac0 0x30>, - <&dmac1 0x31>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 514>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a779f0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x33>, <&dmac0 0x32>, - <&dmac1 0x33>, <&dmac1 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 515>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a779f0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x35>, <&dmac0 0x34>, - <&dmac1 0x35>, <&dmac1 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a779f0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>, - <&dmac1 0x37>, <&dmac1 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - ufs: ufs@e6860000 { - compatible = "renesas,r8a779f0-ufs"; - reg = <0 0xe6860000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; - clock-names = "fck", "ref_clk"; - freq-table-hz = <200000000 200000000>, <38400000 38400000>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 1514>; - status = "disabled"; - }; - - rswitch: ethernet@e6880000 { - compatible = "renesas,r8a779f0-ether-switch"; - reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; - reg-names = "base", "secure_base"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "mfwd_error", "race_error", - "coma_error", "gwca0_error", - "gwca1_error", "etha0_error", - "etha1_error", "etha2_error", - "gptp0_status", "gptp1_status", - "mfwd_status", "race_status", - "coma_status", "gwca0_status", - "gwca1_status", "etha0_status", - "etha1_status", "etha2_status", - "rmac0_status", "rmac1_status", - "rmac2_status", - "gwca0_rxtx0", "gwca0_rxtx1", - "gwca0_rxtx2", "gwca0_rxtx3", - "gwca0_rxtx4", "gwca0_rxtx5", - "gwca0_rxtx6", "gwca0_rxtx7", - "gwca1_rxtx0", "gwca1_rxtx1", - "gwca1_rxtx2", "gwca1_rxtx3", - "gwca1_rxtx4", "gwca1_rxtx5", - "gwca1_rxtx6", "gwca1_rxtx7", - "gwca0_rxts0", "gwca0_rxts1", - "gwca1_rxts0", "gwca1_rxts1", - "rmac0_mdio", "rmac1_mdio", - "rmac2_mdio", - "rmac0_phy", "rmac1_phy", - "rmac2_phy"; - clocks = <&cpg CPG_MOD 1505>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 1505>; - status = "disabled"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - phys = <ð_serdes 0>; - }; - port@1 { - reg = <1>; - phys = <ð_serdes 1>; - }; - port@2 { - reg = <2>; - phys = <ð_serdes 2>; - }; - }; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a779f0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x51>, <&dmac0 0x50>, - <&dmac1 0x51>, <&dmac1 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a779f0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x53>, <&dmac0 0x52>, - <&dmac1 0x53>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a779f0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>, - <&dmac1 0x57>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a779f0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, - <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>, - <&dmac1 0x59>, <&dmac1 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a779f0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - dmas = <&dmac0 0x41>, <&dmac0 0x40>, - <&dmac1 0x41>, <&dmac1 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 618>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a779f0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 619>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>, - <&dmac1 0x43>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 619>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a779f0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>, - <&dmac1 0x45>, <&dmac1 0x44>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 620>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a779f0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>, - <&dmac1 0x47>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 621>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779f0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7350000 0 0x1000>, - <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15"; - clocks = <&cpg CPG_MOD 709>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 709>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779f0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7351000 0 0x1000>, - <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15"; - clocks = <&cpg CPG_MOD 710>; - clock-names = "fck"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 710>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, - <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, - <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, - <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, - <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, - <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, - <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, - <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779f0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779f0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779f0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779f0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779f0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779f0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeefc0000 0 0x20000>; - interrupts = , - ; - power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = ; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal_rtcore: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal_apcore0: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal_apcore4: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; - - ufs30_clk: ufs30-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; -}; diff --git a/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi b/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi deleted file mode 100644 index bb4a5270f71b6a75d8a637bbfd515172e41e9b28..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779g0-white-hawk-cpu.dtsi +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the White Hawk CPU board - * - * Copyright (C) 2022 Renesas Electronics Corp. - */ - -#include "r8a779g0.dtsi" - -#include -#include -#include - -/ { - model = "Renesas White Hawk CPU board"; - compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:921600n8"; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW47"; - wakeup-source; - debounce-interval = <20>; - }; - - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW48"; - wakeup-source; - debounce-interval = <20>; - }; - - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW49"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led-2 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led-3 { - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; - - mini-dp-con { - compatible = "dp-connector"; - label = "CN5"; - type = "mini"; - - port { - mini_dp_con_in: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - - reg_1p2v: regulator-1p2v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&dsi0 { - status = "okay"; - - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander_a: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - - clocks = <&sn65dsi86_refclk>; - clock-names = "refclk"; - - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - - vccio-supply = <®_1p8v>; - vpll-supply = <®_1p8v>; - vcca-supply = <®_1p2v>; - vcc-supply = <®_1p2v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; - }; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - - }; - hscif0_pins: hscif0 { - groups = "hscif0_data"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - keys_pins: keys { - pins = "GP_5_0", "GP_5_1", "GP_5_2"; - bias-pull-up; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x0 0x1200000>; - read-only; - }; - user@1200000 { - reg = <0x1200000 0x2e00000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi deleted file mode 100644 index f8537f7ea4defabad1c5327948a6749a694d427b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board - * - * Copyright (C) 2022 Glider bv - */ - -#include - -&csi40 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi40_in: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3>; - remote-endpoint = <&max96712_out0>; - }; - }; - }; -}; - -&csi41 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi41_in: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3>; - remote-endpoint = <&max96712_out1>; - }; - }; - }; -}; - -&i2c0 { - pca9654_a: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9654_b: gpio@22 { - compatible = "onnn,pca9654"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - eeprom@52 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "csi-dsi-sub-board-id"; - reg = <0x52>; - pagesize = <8>; - }; -}; - -&i2c1 { - gmsl0: gmsl-deserializer@49 { - compatible = "maxim,max96712"; - reg = <0x49>; - enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - max96712_out0: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3>; - remote-endpoint = <&csi40_in>; - }; - }; - }; - }; - - gmsl1: gmsl-deserializer@4b { - compatible = "maxim,max96712"; - reg = <0x4b>; - enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - max96712_out1: endpoint { - bus-type = ; - clock-lanes = <0>; - data-lanes = <1 2 3>; - remote-endpoint = <&csi41_in>; - }; - }; - }; - }; -}; - -&isp0 { - status = "okay"; -}; - -&isp1 { - status = "okay"; -}; - -&vin00 { - status = "okay"; -}; - -&vin01 { - status = "okay"; -}; - -&vin02 { - status = "okay"; -}; - -&vin03 { - status = "okay"; -}; - -&vin04 { - status = "okay"; -}; - -&vin05 { - status = "okay"; -}; - -&vin06 { - status = "okay"; -}; - -&vin07 { - status = "okay"; -}; - -&vin08 { - status = "okay"; -}; - -&vin09 { - status = "okay"; -}; - -&vin10 { - status = "okay"; -}; - -&vin11 { - status = "okay"; -}; - -&vin12 { - status = "okay"; -}; - -&vin13 { - status = "okay"; -}; - -&vin14 { - status = "okay"; -}; - -&vin15 { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi b/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi deleted file mode 100644 index 4f411f95c674bd51507ac7f6fe9ff0282850390a..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779g0-white-hawk-ethernet.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) - * sub-board - * - * Copyright (C) 2022 Glider bv - */ - -&i2c0 { - eeprom@53 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "ethernet-sub-board-id"; - reg = <0x53>; - pagesize = <8>; - }; -}; diff --git a/arch/arm/dts/r8a779g0-white-hawk.dts b/arch/arm/dts/r8a779g0-white-hawk.dts deleted file mode 100644 index eff1ef6e2cc83aba94d041996682b3616002c1be..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779g0-white-hawk.dts +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the White Hawk CPU and BreakOut boards - * - * Copyright (C) 2022 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779g0-white-hawk-cpu.dtsi" -#include "r8a779g0-white-hawk-csi-dsi.dtsi" -#include "r8a779g0-white-hawk-ethernet.dtsi" - -/ { - model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; - compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - can_transceiver0: can-phy0 { - compatible = "nxp,tjr1443"; - #phy-cells = <0>; - enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - max-bitrate = <5000000>; - }; -}; - -&can_clk { - clock-frequency = <40000000>; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - channel0 { - status = "okay"; - phys = <&can_transceiver0>; - }; - - channel1 { - status = "okay"; - }; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&pfc { - can_clk_pins: can-clk { - groups = "can_clk"; - function = "can_clk"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - canfd1_pins: canfd1 { - groups = "canfd1_data"; - function = "canfd1"; - }; -}; diff --git a/arch/arm/dts/r8a779g0.dtsi b/arch/arm/dts/r8a779g0.dtsi deleted file mode 100644 index d3d25e077c5d50531baf7d0dc2925f35f2dbc4c1..0000000000000000000000000000000000000000 --- a/arch/arm/dts/r8a779g0.dtsi +++ /dev/null @@ -1,2349 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car V4H (R8A779G0) SoC - * - * Copyright (C) 2022 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a779g0"; - #address-cells = <2>; - #size-cells = <2>; - - /* External Audio clock - to be overridden by boards that provide it */ - audio_clkin: audio_clkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <825000>; - clock-latency-ns = <500000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <825000>; - clock-latency-ns = <500000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <825000>; - clock-latency-ns = <500000>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <825000>; - clock-latency-ns = <500000>; - opp-suspend; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <880000>; - clock-latency-ns = <500000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a76_0>; - }; - core1 { - cpu = <&a76_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a76_2>; - }; - core1 { - cpu = <&a76_3>; - }; - }; - }; - - a76_0: cpu@0 { - compatible = "arm,cortex-a76"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; - next-level-cache = <&L3_CA76_0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; - operating-points-v2 = <&cluster0_opp>; - }; - - a76_1: cpu@100 { - compatible = "arm,cortex-a76"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; - next-level-cache = <&L3_CA76_0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; - operating-points-v2 = <&cluster0_opp>; - }; - - a76_2: cpu@10000 { - compatible = "arm,cortex-a76"; - reg = <0x10000>; - device_type = "cpu"; - power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; - next-level-cache = <&L3_CA76_1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; - operating-points-v2 = <&cluster0_opp>; - }; - - a76_3: cpu@10100 { - compatible = "arm,cortex-a76"; - reg = <0x10100>; - device_type = "cpu"; - power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; - next-level-cache = <&L3_CA76_1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; - operating-points-v2 = <&cluster0_opp>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - }; - - L3_CA76_0: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A779G0_PD_A2E0D0>; - cache-unified; - cache-level = <3>; - }; - - L3_CA76_1: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A779G0_PD_A2E0D1>; - cache-unified; - cache-level = <3>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a779g0-wdt", - "renesas,rcar-gen4-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - status = "disabled"; - }; - - pfc: pinctrl@e6050000 { - compatible = "renesas,pfc-r8a779g0"; - reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, - <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, - <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, - <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, - <0 0xe6068000 0 0x16c>; - }; - - gpio0: gpio@e6050180 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 0 19>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@e6050980 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6050980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 32 29>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@e6058180 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 64 20>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@e6058980 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6058980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 96 30>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@e6060180 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 128 25>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@e6060980 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6060980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 160 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@e6061180 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 192 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@e6061980 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6061980 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 917>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 224 21>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@e6068180 { - compatible = "renesas,gpio-r8a779g0", - "renesas,rcar-gen4-gpio"; - reg = <0 0xe6068180 0 0x54>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pfc 0 256 14>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a779g0-cmt0", - "renesas,rcar-gen4-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 910>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a779g0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 911>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a779g0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 912>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a779g0-cmt1", - "renesas,rcar-gen4-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 913>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 913>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779g0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779g0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779g0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a779g0-thermal"; - reg = <0 0xe6198000 0 0x200>, - <0 0xe61a0000 0 0x200>, - <0 0xe61a8000 0 0x200>, - <0 0xe61b0000 0 0x200>; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 611>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 713>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 714>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 715>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 716>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 717>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 717>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>; - dmas = <&dmac0 0x91>, <&dmac0 0x90>, - <&dmac1 0x91>, <&dmac1 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>; - dmas = <&dmac0 0x93>, <&dmac0 0x92>, - <&dmac1 0x93>, <&dmac1 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>; - dmas = <&dmac0 0x95>, <&dmac0 0x94>, - <&dmac1 0x95>, <&dmac1 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 521>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>, - <&dmac1 0x97>, <&dmac1 0x96>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 521>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 522>; - dma-names = "tx", "rx", "tx", "rx"; - dmas = <&dmac0 0x99>, <&dmac0 0x98>, - <&dmac1 0x99>, <&dmac1 0x98>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a779g0", - "renesas,rcar-gen4-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 523>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, - <&dmac1 0x9b>, <&dmac1 0x9a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a779g0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x31>, <&dmac0 0x30>, - <&dmac1 0x31>, <&dmac1 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 514>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a779g0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x33>, <&dmac0 0x32>, - <&dmac1 0x33>, <&dmac1 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 515>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a779g0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x35>, <&dmac0 0x34>, - <&dmac1 0x35>, <&dmac1 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a779g0", - "renesas,rcar-gen4-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>, - <&dmac1 0x37>, <&dmac1 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - canfd: can@e6660000 { - compatible = "renesas,r8a779g0-canfd", - "renesas,rcar-gen4-canfd"; - reg = <0 0xe6660000 0 0x8500>; - interrupts = , - ; - interrupt-names = "ch_int", "g_int"; - clocks = <&cpg CPG_MOD 328>, - <&cpg CPG_CORE R8A779G0_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>; - assigned-clock-rates = <80000000>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - - channel2 { - status = "disabled"; - }; - - channel3 { - status = "disabled"; - }; - - channel4 { - status = "disabled"; - }; - - channel5 { - status = "disabled"; - }; - - channel6 { - status = "disabled"; - }; - - channel7 { - status = "disabled"; - }; - }; - - avb0: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a779g0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15", "ch16", "ch17", - "ch18", "ch19", "ch20", "ch21", - "ch22", "ch23", "ch24"; - clocks = <&cpg CPG_MOD 211>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 211>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb1: ethernet@e6810000 { - compatible = "renesas,etheravb-r8a779g0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6810000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15", "ch16", "ch17", - "ch18", "ch19", "ch20", "ch21", - "ch22", "ch23", "ch24"; - clocks = <&cpg CPG_MOD 212>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 212>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - avb2: ethernet@e6820000 { - compatible = "renesas,etheravb-r8a779g0", - "renesas,etheravb-rcar-gen4"; - reg = <0 0xe6820000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15", "ch16", "ch17", - "ch18", "ch19", "ch20", "ch21", - "ch22", "ch23", "ch24"; - clocks = <&cpg CPG_MOD 213>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 213>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm7: pwm@e6e37000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e37000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm8: pwm@e6e38000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e38000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - pwm9: pwm@e6e39000 { - compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; - reg = <0 0xe6e39000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 628>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a779g0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x51>, <&dmac0 0x50>, - <&dmac1 0x51>, <&dmac1 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a779g0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x53>, <&dmac0 0x52>, - <&dmac1 0x53>, <&dmac1 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a779g0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>, - <&dmac1 0x57>, <&dmac1 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 704>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a779g0", - "renesas,rcar-gen4-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, - <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>, - <&dmac1 0x59>, <&dmac1 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 705>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 718>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 718>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - dmas = <&dmac0 0x41>, <&dmac0 0x40>, - <&dmac1 0x41>, <&dmac1 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 618>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 619>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>, - <&dmac1 0x43>, <&dmac1 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 619>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>, - <&dmac1 0x45>, <&dmac1 0x44>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 620>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>, - <&dmac1 0x47>, <&dmac1 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 621>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof4: spi@e6c20000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c20000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - dmas = <&dmac0 0x49>, <&dmac0 0x48>, - <&dmac1 0x49>, <&dmac1 0x48>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 622>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof5: spi@e6c28000 { - compatible = "renesas,msiof-r8a779g0", - "renesas,rcar-gen4-msiof"; - reg = <0 0xe6c28000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, - <&dmac1 0x4b>, <&dmac1 0x4a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 623>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin00: video@e6ef0000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 730>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 730>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin00isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin00>; - }; - }; - }; - }; - - vin01: video@e6ef1000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 731>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 731>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin01isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin01>; - }; - }; - }; - }; - - vin02: video@e6ef2000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 800>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 800>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin02isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin02>; - }; - }; - }; - }; - - vin03: video@e6ef3000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 801>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 801>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin03isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin03>; - }; - }; - }; - }; - - vin04: video@e6ef4000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 802>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 802>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin04isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin04>; - }; - }; - }; - }; - - vin05: video@e6ef5000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 803>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 803>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin05isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin05>; - }; - }; - }; - }; - - vin06: video@e6ef6000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin06isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin06>; - }; - }; - }; - }; - - vin07: video@e6ef7000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin07isp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0vin07>; - }; - }; - }; - }; - - vin08: video@e6ef8000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <8>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin08isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin08>; - }; - }; - }; - }; - - vin09: video@e6ef9000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6ef9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <9>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin09isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin09>; - }; - }; - }; - }; - - vin10: video@e6efa000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6efa000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <10>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin10isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin10>; - }; - }; - }; - }; - - vin11: video@e6efb000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6efb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <11>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin11isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin11>; - }; - }; - }; - }; - - vin12: video@e6efc000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6efc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <12>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin12isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin12>; - }; - }; - }; - }; - - vin13: video@e6efd000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6efd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <13>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin13isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin13>; - }; - }; - }; - }; - - vin14: video@e6efe000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6efe000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 812>; - renesas,id = <14>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin14isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin14>; - }; - }; - }; - }; - - vin15: video@e6eff000 { - compatible = "renesas,vin-r8a779g0"; - reg = <0 0xe6eff000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 813>; - renesas,id = <15>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vin15isp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&isp1vin15>; - }; - }; - }; - }; - - dmac0: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779g0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7350000 0 0x1000>, - <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15"; - clocks = <&cpg CPG_MOD 709>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 709>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779g0", - "renesas,rcar-gen4-dmac"; - reg = <0 0xe7351000 0 0x1000>, - <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", "ch4", - "ch5", "ch6", "ch7", "ch8", "ch9", - "ch10", "ch11", "ch12", "ch13", - "ch14", "ch15"; - clocks = <&cpg CPG_MOD 710>; - clock-names = "fck"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 710>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, - <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, - <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, - <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, - <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, - <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, - <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, - <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; - }; - - rcar_sound: sound@ec5a0000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4"; - reg = <0 0xec5a0000 0 0x020>, - <0 0xec540000 0 0x1000>, - <0 0xec541000 0 0x050>, - <0 0xec400000 0 0x40000>; - reg-names = "adg", "ssiu", "ssi", "sdmc"; - - clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; - clock-names = "ssiu.0", "ssi.0", "clkin"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 2926>, <&cpg 2927>; - reset-names = "ssiu.0", "ssi.0"; - status = "disabled"; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&dmac0 0x6e>, <&dmac0 0x6f>; - dma-names = "tx", "rx"; - }; - ssiu01: ssiu-1 { - dmas = <&dmac0 0x6c>, <&dmac0 0x6d>; - dma-names = "tx", "rx"; - }; - ssiu02: ssiu-2 { - dmas = <&dmac0 0x6a>, <&dmac0 0x6b>; - dma-names = "tx", "rx"; - }; - ssiu03: ssiu-3 { - dmas = <&dmac0 0x68>, <&dmac0 0x69>; - dma-names = "tx", "rx"; - }; - ssiu04: ssiu-4 { - dmas = <&dmac0 0x66>, <&dmac0 0x67>; - dma-names = "tx", "rx"; - }; - ssiu05: ssiu-5 { - dmas = <&dmac0 0x64>, <&dmac0 0x65>; - dma-names = "tx", "rx"; - }; - ssiu06: ssiu-6 { - dmas = <&dmac0 0x62>, <&dmac0 0x63>; - dma-names = "tx", "rx"; - }; - ssiu07: ssiu-7 { - dmas = <&dmac0 0x60>, <&dmac0 0x61>; - dma-names = "tx", "rx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - }; - }; - }; - - ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@eed80000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeed80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_vc: iommu@eedc0000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeedc0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_3dg: iommu@eee00000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeee00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@eee80000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeee80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@eeec0000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeeec0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip0: iommu@eef00000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeef00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip1: iommu@eef40000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeef40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779g0", - "renesas,rcar-gen4-ipmmu-vmsa"; - reg = <0 0xeefc0000 0 0x20000>; - interrupts = , - ; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779g0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779G0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a779g0-rpc-if", - "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = ; - }; - - csi40: csi2@fe500000 { - compatible = "renesas,r8a779g0-csi2"; - reg = <0 0xfe500000 0 0x40000>; - interrupts = ; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 331>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi40isp0: endpoint { - remote-endpoint = <&isp0csi40>; - }; - }; - }; - }; - - csi41: csi2@fe540000 { - compatible = "renesas,r8a779g0-csi2"; - reg = <0 0xfe540000 0 0x40000>; - interrupts = ; - clocks = <&cpg CPG_MOD 400>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 400>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - csi41isp1: endpoint { - remote-endpoint = <&isp1csi41>; - }; - }; - }; - }; - - fcpvd0: fcp@fea10000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea10000 0 0x200>; - clocks = <&cpg CPG_MOD 508>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 508>; - }; - - fcpvd1: fcp@fea11000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea11000 0 0x200>; - clocks = <&cpg CPG_MOD 509>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 509>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 830>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 830>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 831>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 831>; - - renesas,fcp = <&fcpvd1>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a779g0"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 411>; - clock-names = "du.0"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 411>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_dsi0: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - du_out_dsi1: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; - - isp0: isp@fed00000 { - compatible = "renesas,r8a779g0-isp"; - reg = <0 0xfed00000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 612>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 612>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp0csi40: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi40isp0>; - }; - }; - - port@1 { - reg = <1>; - isp0vin00: endpoint { - remote-endpoint = <&vin00isp0>; - }; - }; - - port@2 { - reg = <2>; - isp0vin01: endpoint { - remote-endpoint = <&vin01isp0>; - }; - }; - - port@3 { - reg = <3>; - isp0vin02: endpoint { - remote-endpoint = <&vin02isp0>; - }; - }; - - port@4 { - reg = <4>; - isp0vin03: endpoint { - remote-endpoint = <&vin03isp0>; - }; - }; - - port@5 { - reg = <5>; - isp0vin04: endpoint { - remote-endpoint = <&vin04isp0>; - }; - }; - - port@6 { - reg = <6>; - isp0vin05: endpoint { - remote-endpoint = <&vin05isp0>; - }; - }; - - port@7 { - reg = <7>; - isp0vin06: endpoint { - remote-endpoint = <&vin06isp0>; - }; - }; - - port@8 { - reg = <8>; - isp0vin07: endpoint { - remote-endpoint = <&vin07isp0>; - }; - }; - }; - }; - - isp1: isp@fed20000 { - compatible = "renesas,r8a779g0-isp"; - reg = <0 0xfed20000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 613>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - - isp1csi41: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi41isp1>; - }; - }; - - port@1 { - reg = <1>; - isp1vin08: endpoint { - remote-endpoint = <&vin08isp1>; - }; - }; - - port@2 { - reg = <2>; - isp1vin09: endpoint { - remote-endpoint = <&vin09isp1>; - }; - }; - - port@3 { - reg = <3>; - isp1vin10: endpoint { - remote-endpoint = <&vin10isp1>; - }; - }; - - port@4 { - reg = <4>; - isp1vin11: endpoint { - remote-endpoint = <&vin11isp1>; - }; - }; - - port@5 { - reg = <5>; - isp1vin12: endpoint { - remote-endpoint = <&vin12isp1>; - }; - }; - - port@6 { - reg = <6>; - isp1vin13: endpoint { - remote-endpoint = <&vin13isp1>; - }; - }; - - port@7 { - reg = <7>; - isp1vin14: endpoint { - remote-endpoint = <&vin14isp1>; - }; - }; - - port@8 { - reg = <8>; - isp1vin15: endpoint { - remote-endpoint = <&vin15isp1>; - }; - }; - }; - }; - - dsi0: dsi-encoder@fed80000 { - compatible = "renesas,r8a779g0-dsi-csi2-tx"; - reg = <0 0xfed80000 0 0x10000>; - clocks = <&cpg CPG_MOD 415>, - <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, - <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; - clock-names = "fck", "dsi", "pll"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 415>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&du_out_dsi0>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - dsi1: dsi-encoder@fed90000 { - compatible = "renesas,r8a779g0-dsi-csi2-tx"; - reg = <0 0xfed90000 0 0x10000>; - clocks = <&cpg CPG_MOD 416>, - <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, - <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; - clock-names = "fck", "dsi", "pll"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 416>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&du_out_dsi1>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal_cr52: sensor1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal_cnn: sensor2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal_ca76: sensor3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal_ddr1: sensor4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 3>; - - trips { - sensor4_crit: sensor4-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi index 717cb3dc816ee641b4942a15d00f8ecc564fac13..793951655b73b84812c8ac78898b299858514712 100644 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/dts/rk3288-vmarc-som.dtsi @@ -231,11 +231,43 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio5>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + &i2c5 { status = "okay"; }; +&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; + status = "okay"; +}; + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; }; @@ -251,6 +283,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins = @@ -282,6 +320,16 @@ }; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts deleted file mode 100644 index 184b84fdde075a751b063e4b7784eea77b7efec0..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3308-evb.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -/dts-v1/; -#include -#include "rk3308.dtsi" - -/ { - model = "Rockchip RK3308 EVB"; - compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; - - chosen { - stdout-path = "serial4:1500000n8"; - }; - - adc-keys0 { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-func { - linux,code = ; - label = "function"; - press-threshold-microvolt = <18000>; - }; - }; - - adc-keys1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - - button-esc { - linux,code = ; - label = "micmute"; - press-threshold-microvolt = <1130000>; - }; - - button-home { - linux,code = ; - label = "mode"; - press-threshold-microvolt = <901000>; - }; - - button-menu { - linux,code = ; - label = "play"; - press-threshold-microvolt = <624000>; - }; - - button-down { - linux,code = ; - label = "volume down"; - press-threshold-microvolt = <300000>; - }; - - button-up { - linux,code = ; - label = "volume up"; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - key-power { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - debounce-interval = <100>; - wakeup-source; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vccio_sdio: vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vccio_flash: vccio-flash { - compatible = "regulator-fixed"; - regulator-name = "vccio_flash"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&usb_drv>; - regulator-name = "vbus_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-always-on; - regulator-boot-on; - regulator-settling-time-up-us = <250>; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_1v0: vdd-1v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>; - }; - }; - - usb { - usb_drv: usb-drv { - rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts deleted file mode 100644 index 9232357f4fec9c77c1ee7b8dca798b3e739f9f71..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3308-roc-cc.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3308.dtsi" - -/ { - model = "Firefly ROC-RK3308-CC board"; - compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - ir_tx { - compatible = "pwm-ir-tx"; - pwms = <&pwm5 0 25000 0>; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:red:power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - user_led: led-1 { - label = "firefly:blue:user"; - linux,default-trigger = "ir-user-click"; - default-state = "off"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - }; - - typec_vcc5v: typec-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "typec_vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&typec_vcc5v>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sdmmc: vcc-sdmmc { - compatible = "regulator-gpio"; - regulator-name = "vcc_sdmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_sd: vcc-sd { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - pwm-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&pwm5 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm5_pin_pull_down>; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwr_key: pwr-key { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&sdmmc { - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <300>; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdmmc>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308-rock-pi-s.dts b/arch/arm/dts/rk3308-rock-pi-s.dts deleted file mode 100644 index b47fe02c33fbdc33d6d9b2ac116381a007043e72..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3308-rock-pi-s.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Jagan Teki - */ - -/dts-v1/; -#include "rk3308.dtsi" - -/ { - model = "Radxa ROCK Pi S"; - compatible = "radxa,rockpis", "rockchip,rk3308"; - - aliases { - ethernet0 = &gmac; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; - - green-led { - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - label = "rockpis:green:power"; - linux,default-trigger = "default-on"; - }; - - blue-led { - default-state = "on"; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - label = "rockpis:blue:user"; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-0 = <&wifi_enable_h>; - pinctrl-names = "default"; - reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - }; - - vcc_1v8: vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_ddr: vcc-ddr { - compatible = "regulator-fixed"; - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_core: vdd-core { - compatible = "pwm-regulator"; - pwms = <&pwm0 0 5000 1>; - pwm-supply = <&vcc5v0_sys>; - regulator-name = "vdd_core"; - regulator-min-microvolt = <827000>; - regulator-max-microvolt = <1340000>; - regulator-settling-time-up-us = <250>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_core>; -}; - -&emmc { - bus-width = <4>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_io>; - status = "okay"; -}; - -&gmac { - clock_in_out = "output"; - phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /* GPIO0_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_B0 - B7 */ - "", "", "", "header1-pin3 [GPIO0_B3]", - "header1-pin5 [GPIO0_B4]", "", "", - "header1-pin11 [GPIO0_B7]", - /* GPIO0_C0 - C7 */ - "header1-pin13 [GPIO0_C0]", - "header1-pin15 [GPIO0_C1]", "", "", "", - "", "", "", - /* GPIO0_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = - /* GPIO1_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_C0 - C7 */ - "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]", - "header1-pin19 [GPIO1_C7]", - /* GPIO1_D0 - D7 */ - "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", - "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - /* GPIO2_A0 - A7 */ - "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", - "", "", - "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]", - "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]", - /* GPIO2_B0 - B7 */ - "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]", - "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]", - "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]", - "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]", - /* GPIO2_C0 - C7 */ - "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "", - /* GPIO2_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - /* GPIO3_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_B0 - B7 */ - "", "", "header2-pin42 [GPIO3_B2]", - "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]", - "header2-pin39 [GPIO3_B5]", "", "", - /* GPIO3_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&rtc_32k>; - - leds { - green_led_gio: green-led-gpio { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - heartbeat_led_gpio: heartbeat-led-gpio { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake: wifi-host-wake { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_pin_pull_down>; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdio { - #address-cells = <1>; - #size-cells = <0>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <1000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; - - u2phy_otg: otg-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart4 { - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - }; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3308.dtsi b/arch/arm/dts/rk3308.dtsi deleted file mode 100644 index cfc0a87b5195930d0527ba49a8b2995042538184..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3308.dtsi +++ /dev/null @@ -1,1888 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3308"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&l2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1340000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1025000 1025000 1340000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1125000 1125000 1340000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a35-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - mac_clkin: external-mac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "mac_clkin"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - grf: grf@ff000000 { - compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x08000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x500>; - mode-bootloader = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - mode-fastboot = ; - }; - }; - - usb2phy_grf: syscon@ff008000 { - compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff008000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2phy@100 { - compatible = "rockchip,rk3308-usb2phy"; - reg = <0x100 0x10>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - clocks = <&cru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - detect_grf: syscon@ff00b000 { - compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00b000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - core_grf: syscon@ff00c000 { - compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff00c000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - i2c0: i2c@ff040000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff050000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff050000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff060000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff060000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff070000 { - compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff070000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@ff080000 { - compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; - reg = <0x0 0xff080000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@ff0b0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff0c0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff0d0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff0e0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - spi0: spi@ff120000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff120000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; - status = "disabled"; - }; - - spi1: spi@ff130000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff130000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; - status = "disabled"; - }; - - spi2: spi@ff140000 { - compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 16>, <&dmac1 17>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; - status = "disabled"; - }; - - pwm8: pwm@ff160000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160000 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm8_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@ff160010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160010 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm9_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@ff160020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160020 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm10_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@ff160030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff160030 0x0 0x10>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm11_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@ff170000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170000 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@ff170010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170010 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@ff170020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170020 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@ff170030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff170030 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm0: pwm@ff180000 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180000 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff180010 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180010 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff180020 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180020 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff180030 { - compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff180030 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rktimer: rktimer@ff1a0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff1a0000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - saradc: saradc@ff1e0000 { - compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff1e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - #io-channel-cells = <1>; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - dmac0: dma-controller@ff2c0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2c0000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@ff2d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff2d0000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2s_2ch_0: i2s@ff350000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff350000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 8>, <&dmac1 9>; - dma-names = "tx", "rx"; - resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; - reset-names = "reset-m", "reset-h"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s_2ch_0_sclk - &i2s_2ch_0_lrck - &i2s_2ch_0_sdi - &i2s_2ch_0_sdo>; - status = "disabled"; - }; - - i2s_2ch_1: i2s@ff360000 { - compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff360000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1 11>; - dma-names = "rx"; - resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; - reset-names = "reset-m", "reset-h"; - status = "disabled"; - }; - - spdif_tx: spdif-tx@ff3a0000 { - compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff3a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1 13>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_out>; - status = "disabled"; - }; - - usb20_otg: usb@ff400000 { - compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@ff440000 { - compatible = "generic-ehci"; - reg = <0x0 0xff440000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@ff450000 { - compatible = "generic-ohci"; - reg = <0x0 0xff450000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@ff480000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff480000 0x0 0x4000>; - interrupts = ; - bus-width = <4>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - status = "disabled"; - }; - - emmc: mmc@ff490000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff490000 0x0 0x4000>; - interrupts = ; - bus-width = <8>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff4a0000 { - compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff4a0000 0x0 0x4000>; - interrupts = ; - bus-width = <4>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - status = "disabled"; - }; - - nfc: nand-controller@ff4b0000 { - compatible = "rockchip,rk3308-nfc", - "rockchip,rv1108-nfc"; - reg = <0x0 0xff4b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - assigned-clocks = <&cru SCLK_NANDC>; - assigned-clock-rates = <150000000>; - pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 - &flash_rdn &flash_rdy &flash_wrn>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@ff4e0000 { - compatible = "rockchip,rk3308-gmac"; - reg = <0x0 0xff4e0000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, - <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC>, <&cru ACLK_MAC>, - <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac", "clk_mac_speed"; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; - resets = <&cru SRST_MAC_A>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - sfc: spi@ff4c0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xff4c0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; - pinctrl-names = "default"; - status = "disabled"; - }; - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru SCLK_RTC32K>; - assigned-clock-rates = <32768>; - }; - - gic: interrupt-controller@ff580000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff581000 0x0 0x1000>, - <0x0 0xff582000 0x0 0x2000>, - <0x0 0xff584000 0x0 0x2000>, - <0x0 0xff586000 0x0 0x2000>; - interrupts = ; - #interrupt-cells = <3>; - interrupt-controller; - #address-cells = <0>; - }; - - sram: sram@fff80000 { - compatible = "mmio-sram"; - reg = <0x0 0xfff80000 0x0 0x40000>; - ranges = <0 0x0 0xfff80000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - - /* reserved for ddr dvfs and system suspend/resume */ - ddr-sram@0 { - reg = <0x0 0x8000>; - }; - - /* reserved for vad audio buffer */ - vad_sram: vad-sram@8000 { - reg = <0x8000 0x38000>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3308-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff250000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; - }; - - emmc_rstn: emmc-rstn { - rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up_8ma>, - <3 RK_PA1 2 &pcfg_pull_up_8ma>, - <3 RK_PA2 2 &pcfg_pull_up_8ma>, - <3 RK_PA3 2 &pcfg_pull_up_8ma>, - <3 RK_PA4 2 &pcfg_pull_up_8ma>, - <3 RK_PA5 2 &pcfg_pull_up_8ma>, - <3 RK_PA6 2 &pcfg_pull_up_8ma>, - <3 RK_PA7 2 &pcfg_pull_up_8ma>; - }; - }; - - flash { - flash_csn0: flash-csn0 { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_up_12ma>, - <3 RK_PA1 1 &pcfg_pull_up_12ma>, - <3 RK_PA2 1 &pcfg_pull_up_12ma>, - <3 RK_PA3 1 &pcfg_pull_up_12ma>, - <3 RK_PA4 1 &pcfg_pull_up_12ma>, - <3 RK_PA5 1 &pcfg_pull_up_12ma>, - <3 RK_PA6 1 &pcfg_pull_up_12ma>, - <3 RK_PA7 1 &pcfg_pull_up_12ma>; - }; - }; - - sfc { - sfc_bus4: sfc-bus4 { - rockchip,pins = - <3 RK_PA0 3 &pcfg_pull_none>, - <3 RK_PA1 3 &pcfg_pull_none>, - <3 RK_PA2 3 &pcfg_pull_none>, - <3 RK_PA3 3 &pcfg_pull_none>; - }; - - sfc_bus2: sfc-bus2 { - rockchip,pins = - <3 RK_PA0 3 &pcfg_pull_none>, - <3 RK_PA1 3 &pcfg_pull_none>; - }; - - sfc_cs0: sfc-cs0 { - rockchip,pins = - <3 RK_PA4 3 &pcfg_pull_none>; - }; - - sfc_clk: sfc-clk { - rockchip,pins = - <3 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_txen */ - <1 RK_PC1 3 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <1 RK_PC3 3 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PC2 3 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <1 RK_PC4 3 &pcfg_pull_none>, - /* mac_rxd1 */ - <1 RK_PC5 3 &pcfg_pull_none>, - /* mac_rxer */ - <1 RK_PB7 3 &pcfg_pull_none>, - /* mac_rxdv */ - <1 RK_PC0 3 &pcfg_pull_none>, - /* mac_mdio */ - <1 RK_PB6 3 &pcfg_pull_none>, - /* mac_mdc */ - <1 RK_PB5 3 &pcfg_pull_none>; - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - gmac-m1 { - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_txen */ - <4 RK_PB7 2 &pcfg_pull_none_12ma>, - /* mac_txd1 */ - <4 RK_PA5 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <4 RK_PA4 2 &pcfg_pull_none_12ma>, - /* mac_rxd0 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* mac_rxd1 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* mac_rxer */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* mac_rxdv */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* mac_mdio */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* mac_mdc */ - <4 RK_PB5 2 &pcfg_pull_none>; - }; - - macm1_refclk_12ma: macm1-refclk-12ma { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none_12ma>; - }; - - macm1_refclk: macm1-refclk { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PD0 2 &pcfg_pull_none_smt>, - <1 RK_PD1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <0 RK_PB3 1 &pcfg_pull_none_smt>, - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PA2 3 &pcfg_pull_none_smt>, - <2 RK_PA3 3 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m0 { - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - <0 RK_PB7 2 &pcfg_pull_none_smt>, - <0 RK_PC0 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m1 { - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none_smt>, - <3 RK_PB5 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3-m2 { - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - <2 RK_PA1 3 &pcfg_pull_none_smt>, - <2 RK_PA0 3 &pcfg_pull_none_smt>; - }; - }; - - i2s_2ch_0 { - i2s_2ch_0_mclk: i2s-2ch-0-mclk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sclk: i2s-2ch-0-sclk { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_lrck: i2s-2ch-0-lrck { - rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdo: i2s-2ch-0-sdo { - rockchip,pins = - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_2ch_0_sdi: i2s-2ch-0-sdi { - rockchip,pins = - <4 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_0 { - i2s_8ch_0_mclk: i2s-8ch-0-mclk { - rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { - rockchip,pins = - <2 RK_PA5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { - rockchip,pins = - <2 RK_PA6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { - rockchip,pins = - <2 RK_PA7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { - rockchip,pins = - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { - rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { - rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { - rockchip,pins = - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { - rockchip,pins = - <2 RK_PB6 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m0 { - i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { - rockchip,pins = - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { - rockchip,pins = - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { - rockchip,pins = - <1 RK_PA4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { - rockchip,pins = - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { - rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - i2s_8ch_1_m1 { - i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { - rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { - rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { - rockchip,pins = - <1 RK_PC0 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { - rockchip,pins = - <1 RK_PC1 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { - rockchip,pins = - <1 RK_PC2 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { - rockchip,pins = - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { - rockchip,pins = - <1 RK_PC4 2 &pcfg_pull_none>; - }; - - i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - pdm_m0 { - pdm_m0_clk: pdm-m0-clk { - rockchip,pins = - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi0: pdm-m0-sdi0 { - rockchip,pins = - <1 RK_PB3 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi1: pdm-m0-sdi1 { - rockchip,pins = - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi2: pdm-m0-sdi2 { - rockchip,pins = - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - pdm_m0_sdi3: pdm-m0-sdi3 { - rockchip,pins = - <1 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm_m1 { - pdm_m1_clk: pdm-m1-clk { - rockchip,pins = - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi0: pdm-m1-sdi0 { - rockchip,pins = - <1 RK_PC5 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi1: pdm-m1-sdi1 { - rockchip,pins = - <1 RK_PC4 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi2: pdm-m1-sdi2 { - rockchip,pins = - <1 RK_PC3 4 &pcfg_pull_none>; - }; - - pdm_m1_sdi3: pdm-m1-sdi3 { - rockchip,pins = - <1 RK_PC2 4 &pcfg_pull_none>; - }; - }; - - pdm_m2 { - pdm_m2_clkm: pdm-m2-clkm { - rockchip,pins = - <2 RK_PA4 3 &pcfg_pull_none>; - }; - - pdm_m2_clk: pdm-m2-clk { - rockchip,pins = - <2 RK_PA6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi0: pdm-m2-sdi0 { - rockchip,pins = - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi1: pdm-m2-sdi1 { - rockchip,pins = - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi2: pdm-m2-sdi2 { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - pdm_m2_sdi3: pdm-m2-sdi3 { - rockchip,pins = - <2 RK_PC0 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - pwm0_pin_pull_down: pwm0-pin-pull-down { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_down>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - pwm1_pin_pull_down: pwm1-pin-pull-down { - rockchip,pins = - <0 RK_PB6 1 &pcfg_pull_down>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - pwm2_pin_pull_down: pwm2-pin-pull-down { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_down>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - pwm3_pin_pull_down: pwm3-pin-pull-down { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_down>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - pwm4_pin_pull_down: pwm4-pin-pull-down { - rockchip,pins = - <0 RK_PA1 2 &pcfg_pull_down>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_none>; - }; - - pwm5_pin_pull_down: pwm5-pin-pull-down { - rockchip,pins = - <0 RK_PC1 2 &pcfg_pull_down>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; - }; - - pwm6_pin_pull_down: pwm6-pin-pull-down { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_down>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>; - }; - - pwm7_pin_pull_down: pwm7-pin-pull-down { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_down>; - }; - }; - - pwm8 { - pwm8_pin: pwm8-pin { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; - }; - - pwm8_pin_pull_down: pwm8-pin-pull-down { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_down>; - }; - }; - - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_none>; - }; - - pwm9_pin_pull_down: pwm9-pin-pull-down { - rockchip,pins = - <2 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_none>; - }; - - pwm10_pin_pull_down: pwm10-pin-pull-down { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_down>; - }; - }; - - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - pwm11_pin_pull_down: pwm11-pin-pull-down { - rockchip,pins = - <2 RK_PC0 4 &pcfg_pull_down>; - }; - }; - - rtc { - rtc_32k: rtc-32k { - rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PD5 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PD4 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_det: sdmmc-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - <4 RK_PD6 1 &pcfg_pull_none_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PD0 1 &pcfg_pull_up_4ma>, - <4 RK_PD1 1 &pcfg_pull_up_4ma>, - <4 RK_PD2 1 &pcfg_pull_up_4ma>, - <4 RK_PD3 1 &pcfg_pull_up_4ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = - <4 RK_PA5 1 &pcfg_pull_none_8ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = - <4 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdio_pwren: sdio-pwren { - rockchip,pins = - <0 RK_PA2 1 &pcfg_pull_none_8ma>; - }; - - sdio_wrpt: sdio-wrpt { - rockchip,pins = - <0 RK_PA1 1 &pcfg_pull_none_8ma>; - }; - - sdio_intn: sdio-intn { - rockchip,pins = - <0 RK_PA0 1 &pcfg_pull_none_8ma>; - }; - - sdio_bus1: sdio-bus1 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>, - <4 RK_PA1 1 &pcfg_pull_up_8ma>, - <4 RK_PA2 1 &pcfg_pull_up_8ma>, - <4 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - }; - - spdif_in { - spdif_in: spdif-in { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - spdif_out { - spdif_out: spdif-out { - rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <2 RK_PA2 2 &pcfg_pull_up_4ma>; - }; - - spi0_csn0: spi0-csn0 { - rockchip,pins = - <2 RK_PA3 2 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB3 3 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB2 3 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - }; - - spi1-m1 { - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <2 RK_PA4 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <2 RK_PA5 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <2 RK_PA7 2 &pcfg_pull_up_4ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <2 RK_PB1 2 &pcfg_pull_up_4ma>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <1 RK_PD0 3 &pcfg_pull_up_4ma>; - }; - - spi2_csn0: spi2-csn0 { - rockchip,pins = - <1 RK_PD1 3 &pcfg_pull_up_4ma>; - }; - - spi2_miso: spi2-miso { - rockchip,pins = - <1 RK_PC6 3 &pcfg_pull_up_4ma>; - }; - - spi2_mosi: spi2-mosi { - rockchip,pins = - <1 RK_PC7 3 &pcfg_pull_up_4ma>; - }; - }; - - tsadc { - tsadc_otp_pin: tsadc-otp-pin { - rockchip,pins = - <0 RK_PB2 0 &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PA1 1 &pcfg_pull_up>, - <2 RK_PA0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - uart0_rts_pin: uart0-rts-pin { - rockchip,pins = - <2 RK_PA3 0 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PD1 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <1 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 RK_PC7 2 &pcfg_pull_up>, - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <4 RK_PD3 2 &pcfg_pull_up>, - <4 RK_PD2 2 &pcfg_pull_up>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB5 4 &pcfg_pull_up>, - <3 RK_PB4 4 &pcfg_pull_up>; - }; - }; - - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - <0 RK_PC2 3 &pcfg_pull_up>, - <0 RK_PC1 3 &pcfg_pull_up>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - uart4_rts_pin: uart4-rts-pin { - rockchip,pins = - <4 RK_PA7 0 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts deleted file mode 100644 index 1eef5504445fa9eaffd135980e955309ef8c2126..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-evb.dts +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Rockchip RK3328 EVB"; - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2phy; - mmc0 = &sdmmc; - mmc1 = &sdio; - mmc2 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; -}; - -&gmac2phy { - phy-supply = <&vcc_phy>; - clock_in_out = "output"; - assigned-clock-rate = <50000000>; - assigned-clocks = <&cru SCLK_MAC2PHY>; - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - max-frequency = <150000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts deleted file mode 100644 index 16a1958e457277eb8794f71975a8e9ff87b9892b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3328-nanopi-r2c.dts" - -/ { - model = "FriendlyElec NanoPi R2C Plus"; - compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; - - aliases { - mmc1 = &emmc; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io_33>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts deleted file mode 100644 index a07a26b944a0b30464b42d5622df789f15dbf478..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2c.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2021-2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3328-nanopi-r2s.dts" - -/ { - model = "FriendlyElec NanoPi R2C"; - compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8521s>; - tx_delay = <0x22>; - rx_delay = <0x12>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8521s: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 4fa170eeaf8d768fee192c1bf534ae65497daf51..d8c79600b659f72ad0d14aca7205cd70c73fde6a 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -12,7 +12,7 @@ }; &sdio_vcc_pin { - bootph-all; + bootph-pre-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts deleted file mode 100644 index a4399da7d8b1ad4652060b53f00f05ae2c9c33e7..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 David Bauer - */ - -/dts-v1/; - -#include -#include -#include "rk3328.dtsi" - -/ { - model = "FriendlyElec NanoPi R2S"; - compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &rtl8153; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clk: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&reset_button_pin>; - pinctrl-names = "default"; - - key-reset { - label = "reset"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <50>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; - - lan_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:green:lan"; - }; - - sys_led: led-1 { - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - label = "nanopi-r2s:green:wan"; - }; - }; - - vcc_io_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - enable-active-high; - gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&sdio_vcc_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_io_sdio"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-settling-time-us = <5000>; - regulator-type = "voltage"; - startup-delay-us = <2000>; - states = <1800000 0x1>, - <3300000 0x0>; - vin-supply = <&vcc_io_33>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io_33>; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_5v_lan: vdd-5v-lan { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lan_vdd_pin>; - pinctrl-names = "default"; - regulator-name = "vdd_5v_lan"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "disabled"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io_33>; - pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; - rx_delay = <0x18>; - snps,aal; - tx_delay = <0x24>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vdd_5v>; - vcc2-supply = <&vdd_5v>; - vcc3-supply = <&vdd_5v>; - vcc4-supply = <&vdd_5v>; - vcc5-supply = <&vcc_io_33>; - vcc6-supply = <&vdd_5v>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io_33: DCDC_REG4 { - regulator-name = "vcc_io_33"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - pmuio-supply = <&vcc_io_33>; - vccio1-supply = <&vcc_io_33>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io_33>; - vccio6-supply = <&vcc_io_33>; - status = "okay"; -}; - -&pinctrl { - button { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac2io { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lan { - lan_vdd_pin: lan-vdd-pin { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sd { - sdio_vcc_pin: sdio-vcc-pin { - rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_io_sdio>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Second port is for USB 3.0 */ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index 0a9423cd9c7e00d46ff07e593a77badc16ea6766..b50c1332b8364cfa43ed5890704c3fd037b029e1 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -8,9 +8,6 @@ #include "rk3328-sdram-lpddr3-666.dtsi" &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -19,18 +16,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts deleted file mode 100644 index 4237f2ee8fee3370711d376313c7f966ab597995..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Xunlong Software. Co., Ltd. - * (http://www.orangepi.org) - * - * Copyright (c) 2021-2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3328-orangepi-r1-plus.dts" - -/ { - model = "Xunlong Orange Pi R1 Plus LTS"; - compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -}; - -&gmac2io { - phy-handle = <&yt8531c>; - tx_delay = <0x19>; - rx_delay = <0x05>; - - mdio { - /delete-node/ ethernet-phy@1; - - yt8531c: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - - motorcomm,auto-sleep-disabled; - motorcomm,clk-out-frequency-hz = <125000000>; - motorcomm,keep-pll-enabled; - motorcomm,rx-clk-drv-microamp = <5020>; - motorcomm,rx-data-drv-microamp = <5020>; - - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <15000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 1096821fc5d367f094d47c61a3fc1acc7e0416e6..8ae003bbefd1f2278af54e9f073eb5f8c7867131 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -8,9 +8,6 @@ #include "rk3328-sdram-ddr4-666.dtsi" &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -19,18 +16,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts deleted file mode 100644 index f20662929c7713c918c43a8633853571ce8b1274..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts +++ /dev/null @@ -1,374 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Based on rk3328-nanopi-r2s.dts, which is: - * Copyright (c) 2020 David Bauer - */ - -/dts-v1/; - -#include -#include -#include "rk3328.dtsi" - -/ { - model = "Xunlong Orange Pi R1 Plus"; - compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &rtl8153; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clk: gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - pinctrl-names = "default"; - - led-0 { - function = LED_FUNCTION_LAN; - color = ; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - function = LED_FUNCTION_WAN; - color = ; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; - }; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc0m1_pin>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_5v_lan: vdd-5v-lan-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&lan_vdd_pin>; - pinctrl-names = "default"; - regulator-name = "vdd_5v_lan"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&display_subsystem { - status = "disabled"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io>; - pinctrl-0 = <&rgmiim1_pins>; - pinctrl-names = "default"; - snps,aal; - rx_delay = <0x18>; - tx_delay = <0x24>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-0 = <&pmic_int_l>; - pinctrl-names = "default"; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&io_domains { - pmuio-supply = <&vcc_io>; - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - status = "okay"; -}; - -&pinctrl { - gmac2io { - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lan { - lan_vdd_pin: lan-vdd-pin { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Second port is for USB 3.0 */ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts deleted file mode 100644 index 414897a57e757045e5d5a036568f56d004dcba99..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ /dev/null @@ -1,384 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Firefly roc-rk3328-cc"; - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-boot-on; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - vcc_sdio: sdmmcio-regulator { - compatible = "regulator-gpio"; - gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1>, - <3300000 0x0>; - regulator-name = "vcc_sdio"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - label = "firefly:blue:power"; - linux,default-trigger = "heartbeat"; - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user_led: led-1 { - label = "firefly:yellow:user"; - linux,default-trigger = "mmc1"; - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_io>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_sdio>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts deleted file mode 100644 index 3cda6c627b681e7b470643372148651878e38165..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * (C) Copyright 2020 Chen-Yu Tsai - * - * Based on ./rk3328-rock64.dts, which is - * - * Copyright (c) 2017 PINE64 - */ - -/dts-v1/; - -#include -#include -#include -#include - -#include "rk3328.dtsi" - -/ { - model = "Radxa ROCK Pi E"; - compatible = "radxa,rockpi-e", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1750000>; - - /* This button is unpopulated out of the factory. */ - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pin>; - pinctrl-names = "default"; - - led-0 { - color = ; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; - - vcc_host_5v: vcc-host-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_drv>; - enable-active-high; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_wifi: vcc-wifi-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en>; - regulator-name = "vcc_wifi"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_io>; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc_io>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,aal; - snps,rxpbl = <0x4>; - snps,txpbl = <0x4>; - tx_delay = <0x26>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <ð_phy_int_pin>, <ð_phy_reset_pin>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gmac2phy { - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - /* GPIO0_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO0_D0 - D7 */ - "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = - /* GPIO1_A0 - A7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_B0 - B7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO1_D0 - D7 */ - "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - /* GPIO2_A0 - A7 */ - "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", - "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", - "pin-33 [GPIO2_A6]", "", - /* GPIO2_B0 - B7 */ - "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", - /* GPIO2_C0 - C7 */ - "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", - "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", - "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", - /* GPIO2_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - /* GPIO3_A0 - A7 */ - "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", - "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", - /* GPIO3_B0 - B7 */ - "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", - /* GPIO3_C0 - C7 */ - "", "", "", "", "", "", "", "", - /* GPIO3_D0 - D7 */ - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - pmuio-supply = <&vcc_io>; - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_io>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - status = "okay"; -}; - -&pinctrl { - ephy { - eth_phy_int_pin: eth-phy-int-pin { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - eth_phy_reset_pin: eth-phy-reset-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - led_pin: led-pin { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb3 { - usb30_host_drv: usb30-host-drv { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_en: wifi-en { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 551cff6f24f614ad6a3d08aef7f7409ebd5f452f..22f128090f8447079a41796898897724a698e7d4 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -30,9 +30,6 @@ }; &spi0 { - bootph-pre-ram; - bootph-some-ram; - flash@0 { bootph-pre-ram; bootph-some-ram; @@ -41,18 +38,22 @@ &spi0m2_clk { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_cs0 { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_rx { bootph-pre-ram; + bootph-some-ram; }; &spi0m2_tx { bootph-pre-ram; + bootph-some-ram; }; &usb20_otg { diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts deleted file mode 100644 index 229fe9da9c2ddc1e31ac662a6996424efe78d64e..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328-rock64.dts +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 PINE64 - */ - -/dts-v1/; -#include "rk3328.dtsi" - -/ { - model = "Pine64 Rock64"; - compatible = "pine64,rock64", "rockchip,rk3328"; - - aliases { - ethernet0 = &gmac2io; - mmc0 = &sdmmc; - mmc1 = &emmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_pin>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_io>; - }; - - /* Common enable line for all of the rails mentioned in the labels */ - vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - leds { - compatible = "gpio-leds"; - - power_led: led-0 { - gpios = <&rk805 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - standby_led: led-1 { - gpios = <&rk805 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; -}; - -&analog_sound { - status = "okay"; -}; - -&codec { - mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc18_emmc>; - status = "okay"; -}; - -&gmac2io { - assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; - assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_io>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins>; - snps,force_thresh_dma_mode; - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x24>; - rx_delay = <0x18>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&hdmiphy { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rk805: pmic@18 { - compatible = "rockchip,rk805"; - reg = <0x18>; - interrupt-parent = <&gpio2>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk805-clkout2"; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_io>; - vcc6-supply = <&vcc_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1450000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_18: LDO_REG1 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_emmc: LDO_REG2 { - regulator-name = "vcc18_emmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_10: LDO_REG3 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vcc_io>; - vccio2-supply = <&vcc18_emmc>; - vccio3-supply = <&vcc_io>; - vccio4-supply = <&vcc_18>; - vccio5-supply = <&vcc_io>; - vccio6-supply = <&vcc_io>; - pmuio-supply = <&vcc_io>; -}; - -&pinctrl { - ir { - ir_int: ir-int { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - usb20_host_drv: usb20-host-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* maximum speed for Rockchip SPI */ - spi-max-frequency = <50000000>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&usb20_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index d3608bd0e2b2f16b07e9091b39e171d2809a7ead..0135bc08d4913df45533662b7bd93a3e9db616b6 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -17,7 +17,6 @@ }; dmc: dmc { - bootph-all; compatible = "rockchip,rk3328-dmc"; reg = <0x0 0xff400000 0x0 0x1000 0x0 0xff780000 0x0 0x3000 @@ -25,6 +24,7 @@ 0x0 0xff440000 0x0 0x1000 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; + bootph-all; }; }; @@ -42,14 +42,17 @@ &emmc_bus8 { bootph-pre-ram; + bootph-some-ram; }; &emmc_clk { bootph-pre-ram; + bootph-some-ram; }; &emmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &gpio0 { @@ -66,10 +69,12 @@ &pcfg_pull_none_8ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_none_12ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up { @@ -78,19 +83,21 @@ &pcfg_pull_up_4ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up_8ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up_12ma { bootph-pre-ram; + bootph-some-ram; }; &pinctrl { - bootph-pre-ram; - bootph-some-ram; + bootph-all; }; &sdmmc { @@ -103,18 +110,22 @@ &sdmmc0_bus4 { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0_dectn { bootph-pre-ram; + bootph-some-ram; }; &sdmmc0m1_pin { @@ -127,7 +138,8 @@ }; &uart2m1_xfer { - bootph-all; + bootph-pre-sram; + bootph-pre-ram; }; &vop { diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi deleted file mode 100644 index fb5dcf6e93272180bfd60b8e251a61e61f0e9155..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3328.dtsi +++ /dev/null @@ -1,1944 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3328"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - dynamic-power-coefficient = <120>; - enable-method = "psci"; - next-level-cache = <&l2>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <40000>; - }; - }; - - analog_sound: analog-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "Analog"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "HDMI"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s0>; - }; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - i2s0: i2s@ff000000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff000000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 11>, <&dmac 12>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@ff010000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff010000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 14>, <&dmac 15>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@ff020000 { - compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff020000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 0>, <&dmac 1>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: spdif@ff030000 { - compatible = "rockchip,rk3328-spdif"; - reg = <0x0 0xff030000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm2_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@ff040000 { - compatible = "rockchip,pdm"; - reg = <0x0 0xff040000 0x0 0x1000>; - clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac 16>; - dma-names = "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-1 = <&pdmm0_clk_sleep - &pdmm0_sdi0_sleep - &pdmm0_sdi1_sleep - &pdmm0_sdi2_sleep - &pdmm0_sdi3_sleep>; - status = "disabled"; - }; - - grf: syscon@ff100000 { - compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff100000 0x0 0x1000>; - - io_domains: io-domains { - compatible = "rockchip,rk3328-io-voltage-domain"; - status = "disabled"; - }; - - grf_gpio: gpio { - compatible = "rockchip,rk3328-grf-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - power: power-controller { - compatible = "rockchip,rk3328-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3328_PD_HEVC { - reg = ; - #power-domain-cells = <0>; - }; - power-domain@RK3328_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - #power-domain-cells = <0>; - }; - power-domain@RK3328_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x5c8>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - uart0: serial@ff110000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff110000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 2>, <&dmac 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@ff120000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff120000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 4>, <&dmac 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@ff130000 { - compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff130000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 6>, <&dmac 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@ff150000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@ff160000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff170000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff180000 { - compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@ff190000 { - compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff190000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 8>, <&dmac 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; - status = "disabled"; - }; - - wdt: watchdog@ff1a0000 { - compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; - reg = <0x0 0xff1a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_WDT>; - }; - - pwm0: pwm@ff1b0000 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0000 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff1b0010 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0010 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff1b0020 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0020 0x0 0x10>; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff1b0030 { - compatible = "rockchip,rk3328-pwm"; - reg = <0x0 0xff1b0030 0x0 0x10>; - interrupts = ; - clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwmir_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - dmac: dma-controller@ff1f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff1f0000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - - }; - - tsadc: tsadc@ff250000 { - compatible = "rockchip,rk3328-tsadc"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <50000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <100000>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - efuse: efuse@ff260000 { - compatible = "rockchip,rk3328-efuse"; - reg = <0x0 0xff260000 0x0 0x50>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru SCLK_EFUSE>; - clock-names = "pclk_efuse"; - rockchip,efuse-size = <0x20>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - logic_leakage: logic-leakage@19 { - reg = <0x19 0x1>; - }; - efuse_cpu_version: cpu-version@1a { - reg = <0x1a 0x1>; - bits = <3 3>; - }; - }; - - saradc: adc@ff280000 { - compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - gpu: gpu@ff300000 { - compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x30000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - resets = <&cru SRST_GPU_A>; - }; - - h265e_mmu: iommu@ff330200 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff330200 0 0x100>; - interrupts = ; - clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vepu_mmu: iommu@ff340800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff340800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - vpu: video-codec@ff350000 { - compatible = "rockchip,rk3328-vpu"; - reg = <0x0 0xff350000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3328_PD_VPU>; - }; - - vpu_mmu: iommu@ff350800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff350800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3328_PD_VPU>; - }; - - vdec: video-codec@ff360000 { - compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; - reg = <0x0 0xff360000 0x0 0x480>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <400000000>, <400000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3328_PD_VIDEO>; - }; - - vdec_mmu: iommu@ff360480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3328_PD_VIDEO>; - }; - - vop: vop@ff370000 { - compatible = "rockchip,rk3328-vop"; - reg = <0x0 0xff370000 0x0 0x3efc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@ff373f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff373f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@ff3c0000 { - compatible = "rockchip,rk3328-dw-hdmi"; - reg = <0x0 0xff3c0000 0x0 0x20000>; - reg-io-width = <4>; - interrupts = , - ; - clocks = <&cru PCLK_HDMI>, - <&cru SCLK_HDMI_SFC>, - <&cru SCLK_RTC32K>; - clock-names = "iahb", - "isfr", - "cec"; - phys = <&hdmiphy>; - phy-names = "hdmi"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - hdmi_in: port { - hdmi_in_vop: endpoint { - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - codec: codec@ff410000 { - compatible = "rockchip,rk3328-codec"; - reg = <0x0 0xff410000 0x0 0x1000>; - clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; - clock-names = "pclk", "mclk"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmiphy: phy@ff430000 { - compatible = "rockchip,rk3328-hdmi-phy"; - reg = <0x0 0xff430000 0x0 0x10000>; - interrupts = ; - clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - clock-output-names = "hdmi_phy"; - #clock-cells = <0>; - nvmem-cells = <&efuse_cpu_version>; - nvmem-cell-names = "cpu-version"; - #phy-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - /* - * CPLL should run at 1200, but that is to high for - * the initial dividers of most of its children. - * We need set cpll child clk div first, - * and then set the cpll frequency. - */ - <&cru DCLK_LCDC>, <&cru SCLK_PDM>, - <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, - <&cru SCLK_UART1>, <&cru SCLK_UART2>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, - <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, - <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, - <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, - <&cru SCLK_SDIO>, <&cru SCLK_TSP>, - <&cru SCLK_WIFI>, <&cru ARMCLK>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, - <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru SCLK_RTC32K>; - assigned-clock-parents = - <&cru HDMIPHY>, <&cru PLL_APLL>, - <&cru PLL_GPLL>, <&xin24m>, - <&xin24m>, <&xin24m>; - assigned-clock-rates = - <0>, <61440000>, - <0>, <24000000>, - <24000000>, <24000000>, - <15000000>, <15000000>, - <100000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <100000000>, - <100000000>, <100000000>, - <50000000>, <50000000>, - <50000000>, <50000000>, - <24000000>, <600000000>, - <491520000>, <1200000000>, - <150000000>, <75000000>, - <75000000>, <150000000>, - <75000000>, <75000000>, - <32768>; - }; - - usb2phy_grf: syscon@ff450000 { - compatible = "rockchip,rk3328-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xff450000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2phy@100 { - compatible = "rockchip,rk3328-usb2phy"; - reg = <0x100 0x10>; - clocks = <&xin24m>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - }; - - sdmmc: mmc@ff500000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff500000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - sdio: mmc@ff510000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff510000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - emmc: mmc@ff520000 { - compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff520000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - status = "disabled"; - }; - - gmac2io: ethernet@ff540000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff540000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, - <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, - <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, - <&cru PCLK_MAC2IO>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC2IO_A>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - tx-fifo-depth = <2048>; - rx-fifo-depth = <4096>; - snps,txpbl = <0x4>; - status = "disabled"; - }; - - gmac2phy: ethernet@ff550000 { - compatible = "rockchip,rk3328-gmac"; - reg = <0x0 0xff550000 0x0 0x10000>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, - <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, - <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, - <&cru SCLK_MAC2PHY_OUT>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "aclk_mac", "pclk_mac", - "clk_macphy"; - resets = <&cru SRST_GMAC2PHY_A>; - reset-names = "stmmaceth"; - phy-mode = "rmii"; - phy-handle = <&phy>; - tx-fifo-depth = <2048>; - rx-fifo-depth = <4096>; - snps,txpbl = <0x4>; - clock_in_out = "output"; - status = "disabled"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - clocks = <&cru SCLK_MAC2PHY_OUT>; - resets = <&cru SRST_MACPHY>; - pinctrl-names = "default"; - pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; - phy-is-integrated; - }; - }; - }; - - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff5d0000 { - compatible = "generic-ohci"; - reg = <0x0 0xff5d0000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usbdrd3: usb@ff600000 { - compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; - reg = <0x0 0xff600000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, - <&cru ACLK_USB3OTG>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - snps,dis-del-phy-power-chg-quirk; - snps,dis_enblslpm_quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff811000 0 0x1000>, - <0x0 0xff812000 0 0x2000>, - <0x0 0xff814000 0 0x2000>, - <0x0 0xff816000 0 0x2000>; - interrupts = ; - }; - - crypto: crypto@ff060000 { - compatible = "rockchip,rk3328-crypto"; - reg = <0x0 0xff060000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, - <&cru SCLK_CRYPTO>; - clock-names = "hclk_master", "hclk_slave", "sclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3328-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff210000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff210000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff220000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff220000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff230000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff230000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff240000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff240000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, - <2 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, - <0 RK_PA6 2 &pcfg_pull_none>; - }; - i2c3_pins: i2c3-pins { - rockchip,pins = - <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pdm-0 { - pdmm0_clk: pdmm0-clk { - rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; - }; - - pdmm0_fsync: pdmm0-fsync { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; - }; - - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; - }; - - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; - }; - - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; - }; - - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; - }; - - pdmm0_clk_sleep: pdmm0-clk-sleep { - rockchip,pins = - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { - rockchip,pins = - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { - rockchip,pins = - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { - rockchip,pins = - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { - rockchip,pins = - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdmm0_fsync_sleep: pdmm0-fsync-sleep { - rockchip,pins = - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB0 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart0_rts_pin: uart0-rts-pin { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, - <3 RK_PA6 4 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; - }; - - uart1_rts_pin: uart1-rts-pin { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart2-0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, - <1 RK_PA1 2 &pcfg_pull_up>; - }; - }; - - uart2-1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_up>; - }; - }; - - spi0-0 { - spi0m0_clk: spi0m0-clk { - rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; - }; - - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; - }; - - spi0m0_tx: spi0m0-tx { - rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; - }; - - spi0m0_rx: spi0m0-rx { - rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; - }; - - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi0-1 { - spi0m1_clk: spi0m1-clk { - rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; - }; - - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; - }; - - spi0m1_tx: spi0m1-tx { - rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; - }; - - spi0m1_rx: spi0m1-rx { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; - }; - - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; - }; - }; - - spi0-2 { - spi0m2_clk: spi0m2-clk { - rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; - }; - - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; - }; - - spi0m2_tx: spi0m2-tx { - rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; - }; - - spi0m2_rx: spi0m2-rx { - rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_mclk: i2s1-mclk { - rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; - }; - - i2s1_sclk: i2s1-sclk { - rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; - }; - - i2s1_lrckrx: i2s1-lrckrx { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; - }; - - i2s1_lrcktx: i2s1-lrcktx { - rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; - }; - - i2s1_sdi: i2s1-sdi { - rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; - }; - - i2s1_sdo: i2s1-sdo { - rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s1_sdio1: i2s1-sdio1 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; - }; - - i2s1_sdio2: i2s1-sdio2 { - rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s1_sdio3: i2s1-sdio3 { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s1_sleep: i2s1-sleep { - rockchip,pins = - <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-0 { - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; - }; - - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; - }; - - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; - }; - - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; - }; - - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; - }; - - i2s2m0_sleep: i2s2m0-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, - <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s2-1 { - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrckrx: i2sm1-lrckrx { - rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; - }; - - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; - }; - - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; - }; - - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; - }; - - i2s2m1_sleep: i2s2m1-sleep { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - spdif-0 { - spdifm0_tx: spdifm0-tx { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - spdif-1 { - spdifm1_tx: spdifm1-tx { - rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - spdif-2 { - spdifm2_tx: spdifm2-tx { - rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - sdmmc0-0 { - sdmmc0m0_pwren: sdmmc0m0-pwren { - rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0m0_pin: sdmmc0m0-pin { - rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0-1 { - sdmmc0m1_pwren: sdmmc0m1-pwren { - rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0m1_pin: sdmmc0m1-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0 { - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; - }; - - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_dectn: sdmmc0-dectn { - rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_wrprt: sdmmc0-wrprt { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - sdmmc0_bus1: sdmmc0-bus1 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, - <1 RK_PA1 1 &pcfg_pull_up_8ma>, - <1 RK_PA2 1 &pcfg_pull_up_8ma>, - <1 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_pins: sdmmc0-pins { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc0ext { - sdmmc0ext_clk: sdmmc0ext-clk { - rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; - }; - - sdmmc0ext_cmd: sdmmc0ext-cmd { - rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_wrprt: sdmmc0ext-wrprt { - rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_dectn: sdmmc0ext-dectn { - rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus1: sdmmc0ext-bus1 { - rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_bus4: sdmmc0ext-bus4 { - rockchip,pins = - <3 RK_PA4 3 &pcfg_pull_up_4ma>, - <3 RK_PA5 3 &pcfg_pull_up_4ma>, - <3 RK_PA6 3 &pcfg_pull_up_4ma>, - <3 RK_PA7 3 &pcfg_pull_up_4ma>; - }; - - sdmmc0ext_pins: sdmmc0ext-pins { - rockchip,pins = - <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - sdmmc1 { - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; - }; - - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_wrprt: sdmmc1-wrprt { - rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_dectn: sdmmc1-dectn { - rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus1: sdmmc1-bus1 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, - <1 RK_PB7 1 &pcfg_pull_up_8ma>, - <1 RK_PC0 1 &pcfg_pull_up_8ma>, - <1 RK_PC1 1 &pcfg_pull_up_8ma>; - }; - - sdmmc1_pins: sdmmc1-pins { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, - <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <0 RK_PA7 2 &pcfg_pull_up_12ma>, - <2 RK_PD4 2 &pcfg_pull_up_12ma>, - <2 RK_PD5 2 &pcfg_pull_up_12ma>, - <2 RK_PD6 2 &pcfg_pull_up_12ma>, - <2 RK_PD7 2 &pcfg_pull_up_12ma>, - <3 RK_PC0 2 &pcfg_pull_up_12ma>, - <3 RK_PC1 2 &pcfg_pull_up_12ma>, - <3 RK_PC2 2 &pcfg_pull_up_12ma>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pwmir { - pwmir_pin: pwmir-pin { - rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - gmac-1 { - rgmiim1_pins: rgmiim1-pins { - rockchip,pins = - /* mac_txclk */ - <1 RK_PB4 2 &pcfg_pull_none_8ma>, - /* mac_rxclk */ - <1 RK_PB5 2 &pcfg_pull_none_4ma>, - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_4ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_8ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_4ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_4ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_4ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_4ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_8ma>, - /* mac_rxd3 */ - <1 RK_PB6 2 &pcfg_pull_none_4ma>, - /* mac_rxd2 */ - <1 RK_PB7 2 &pcfg_pull_none_4ma>, - /* mac_txd3 */ - <1 RK_PC0 2 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <1 RK_PC1 2 &pcfg_pull_none_8ma>, - - /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none_8ma>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none_8ma>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none_4ma>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none_8ma>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none_8ma>, - /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none_8ma>, - /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none_8ma>; - }; - - rmiim1_pins: rmiim1-pins { - rockchip,pins = - /* mac_mdio */ - <1 RK_PC3 2 &pcfg_pull_none_2ma>, - /* mac_txen */ - <1 RK_PD1 2 &pcfg_pull_none_12ma>, - /* mac_clk */ - <1 RK_PC5 2 &pcfg_pull_none_2ma>, - /* mac_rxer */ - <1 RK_PD0 2 &pcfg_pull_none_2ma>, - /* mac_rxdv */ - <1 RK_PC6 2 &pcfg_pull_none_2ma>, - /* mac_mdc */ - <1 RK_PC7 2 &pcfg_pull_none_2ma>, - /* mac_rxd1 */ - <1 RK_PB2 2 &pcfg_pull_none_2ma>, - /* mac_rxd0 */ - <1 RK_PB3 2 &pcfg_pull_none_2ma>, - /* mac_txd1 */ - <1 RK_PB0 2 &pcfg_pull_none_12ma>, - /* mac_txd0 */ - <1 RK_PB1 2 &pcfg_pull_none_12ma>, - - /* mac_mdio */ - <0 RK_PB3 1 &pcfg_pull_none>, - /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, - /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, - /* mac_mdc */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, - /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - gmac2phy { - fephyled_speed10: fephyled-speed10 { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - - fephyled_duplex: fephyled-duplex { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - - fephyled_rxm1: fephyled-rxm1 { - rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; - }; - - fephyled_txm1: fephyled-txm1 { - rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; - }; - - fephyled_linkm1: fephyled-linkm1 { - rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - tsadc_pin { - tsadc_int: tsadc-int { - rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; - }; - tsadc_pin: tsadc-pin { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; - }; - }; - - cif-0 { - dvp_d2d9_m0:dvp-d2d9-m0 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m0 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* cif_d6m0 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* cif_d7m0 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm0 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - - cif-1 { - dvp_d2d9_m1:dvp-d2d9-m1 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* cif_d5m1 */ - <2 RK_PC0 4 &pcfg_pull_none>, - /* cif_d6m1 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* cif_d7m1 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* cif_href */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* cif_vsync */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* cif_clkoutm1 */ - <2 RK_PB7 4 &pcfg_pull_none>, - /* cif_clkin */ - <3 RK_PA2 2 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi index a3f27566e438cd5987eed0443f01d766bcda4884..6c07de98fa01d949a0d1ddfb9a3f9ac62e9ab9fd 100644 --- a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi +++ b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi @@ -9,7 +9,6 @@ / { chosen { stdout-path = "serial2:1500000n8"; - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; }; diff --git a/arch/arm/dts/rk3399-eaidk-610.dts b/arch/arm/dts/rk3399-eaidk-610.dts deleted file mode 100644 index d1f343345f67499a737d83b3d791b47efce32deb..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-eaidk-610.dts +++ /dev/null @@ -1,939 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "OPEN AI LAB EAIDK-610"; - compatible = "openailab,eaidk-610", "rockchip,rk3399"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - key-power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>, <&user_led_pin>, - <&heartbeat_led_pin>, <&wlan_active_led_pin>, - <&bt_active_led_pin>; - - work_led: led-0 { - label = "blue:work"; - default-state = "on"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - - user_led: led-1 { - label = "read:user"; - default-state = "off"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - }; - - heartbeat_led: led-2 { - label = "green:heartbeat"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - }; - - wlan_active_led: led-3 { - label = "yellow:wlan"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led: led-4 { - label = "blue:bt"; - gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - rt5651-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "realtek,rt5651-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - simple-audio-card,codec { - sound-dai = <&rt5651>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - /* For USB3.0 Port1/2 */ - vcc5v0_host1: vcc5v0-host1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host1_en>; - regulator-name = "vcc5v0_host1"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - /* For USB2.0 Port1/2 */ - vcc5v0_host3: vcc5v0-host3-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host3_en>; - regulator-name = "vcc5v0_host3"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc3v3_sys>; - }; - - vdd_log: vdd-log { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG2 { - regulator-name = "vcc2v8_dvp"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - rt5651: audio-codec@1a { - compatible = "rockchip,rt5651"; - reg = <0x1a>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; - spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; - -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = <&tcphy0_typec_ss>; - }; - }; - }; - }; - }; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - work_led_pin: work-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led_pin: user-led-pin { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - heartbeat_led_pin: heartbeat-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_active_led_pin: wlan-led-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_active_led_pin: bt-led-pin { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rt5651 { - rt5651_hpcon: rt5640-hpcon { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host3_en: vcc5v0-host3-en { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_host1_en: vcc5v0-host1-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - /* WiFi & BT combo module AMPAK AP6255 */ - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy0_usb3 { - orientation-switch; - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host3>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host3>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - usb-role-switch; - - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index dfce63e4d428fe7019291a2ceaf1fa9bebb18869..3fa5fc0c9ddb4191c07e807aecec60f90998a3cb 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -9,16 +9,18 @@ / { chosen { stdout-path = "serial2:1500000n8"; - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; }; -&i2c0 { - bootph-all; -}; - -&rk808 { - bootph-all; +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; }; &tcphy1 { @@ -37,16 +39,3 @@ &vdd_center { regulator-init-microvolt = <900000>; }; - -&sdmmc { - bootph-all; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts deleted file mode 100644 index 7b717ebec8ffa0f5565035e23ec1f8c709a3b916..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-evb.dts +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" - -/ { - model = "Rockchip RK3399 Evaluation Board"; - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - - aliases { - mmc0 = &sdhci; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - pwms = <&pwm0 0 25000 0>; - }; - - edp_panel: edp-panel { - compatible ="lg,lp079qx1-sp0v"; - backlight = <&backlight>; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - power-supply = <&vcc3v3_s0>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vdd_center: vdd-center { - compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 0>; - regulator-name = "vdd_center"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - status = "okay"; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - -}; - -&edp { - status = "okay"; - force-hpd; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&pcie_phy { - status = "disabled"; -}; - -&pcie0 { - ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "disabled"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index 38e0897db91dd3d1306c3ce0c30b40939ab6e220..ac924d6dc592d9e81dce07c8a996c2c48a5ce045 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -6,8 +6,12 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; +&pcfg_pull_none_18ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; }; diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts deleted file mode 100644 index 1ce85a5816e4514519ff975fae4bbb26511fd10a..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-ficus.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - * - * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw - */ - -/dts-v1/; -#include "rk3399-rock960.dtsi" - -/ { - model = "96boards RK3399 Ficus"; - compatible = "vamrs,ficus", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, - <&user_led3_pin>, <&user_led4_pin>, - <&wlan_led_pin>, <&bt_led_pin>; - - user_led1: led-1 { - label = "red:user1"; - gpios = <&gpio4 25 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2: led-2 { - label = "red:user2"; - gpios = <&gpio4 26 0>; - linux,default-trigger = "mmc0"; - }; - - user_led3: led-3 { - label = "red:user3"; - gpios = <&gpio4 30 0>; - linux,default-trigger = "mmc1"; - }; - - user_led4: led-4 { - label = "red:user4"; - gpios = <&gpio1 0 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led: led-5 { - label = "red:wlan"; - gpios = <&gpio1 1 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led: led-6 { - label = "red:bt"; - gpios = <&gpio1 4 0>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_sys>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl { - gmac { - rgmii_sleep_pins: rgmii-sleep-pins { - rockchip,pins = - <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - user_led1_pin: user-led1-pin { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led2_pin: user-led2-pin { - rockchip,pins = - <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led3_pin: user-led3-pin { - rockchip,pins = - <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led4_pin: user-led4-pin { - rockchip,pins = - <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_led_pin: wlan-led-pin { - rockchip,pins = - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_led_pin: bt-led-pin { - rockchip,pins = - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spi1 { - /* On both Low speed and High speed expansion */ - cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&vcc3v3_pcie { - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; -}; - -&vcc5v0_host { - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index c58ad95d120a91f9ad988eb535c68eb06d87455e..1f5fda1d0f1d6fbe867b4834aabb03a89626dc01 100644 --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts deleted file mode 100644 index c4dd2a6b4836830e99e63569f54255637637ff58..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-firefly.dts +++ /dev/null @@ -1,937 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Firefly-RK3399 Board"; - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; - - work_led: led-0 { - label = "work"; - default-state = "on"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - }; - - diy_led: led-1 { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - }; - }; - - rt5640-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,rt5640-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&rt5640>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - sound-dit { - compatible = "audio-graph-card"; - label = "SPDIF"; - dais = <&spdif_p0>; - }; - - spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; - }; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc_12v>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <430000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sys>; - vcc10-supply = <&vcc_sys>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG2 { - regulator-name = "vcc2v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <0>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - rt5640: rt5640@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - realtek,in1-differential; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rt5640_hpcon>; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - - connector { - compatible = "usb-c-connector"; - data-role = "host"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = - <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = - <&tcphy0_typec_ss>; - }; - }; - }; - }; - }; - - accelerometer@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = ; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - work_led_pin: work-led-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_pin: diy-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_3g_drv: pcie-3g-drv { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rt5640 { - rt5640_hpcon: rt5640-hpcon { - rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - /* WiFi & BT combo module Ampak AP6356S */ - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - - /* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ - - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdif_bus_1>; - status = "okay"; - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts deleted file mode 100644 index e6c1c94c8d69c5e4be895b4d91d7ec38c3c37f22..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Bob Rev 4+ board device tree source - * - * Copyright 2018 Google, Inc - */ - -/dts-v1/; -#include "rk3399-gru-chromebook.dtsi" - -/ { - model = "Google Bob"; - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - - edp_panel: edp-panel { - compatible = "boe,nv101wxmn51"; - backlight = <&backlight>; - power-supply = <&pp3300_disp>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; -}; - -&ap_i2c_ts { - touchscreen: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio3>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int_l &touch_reset_l>; - reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - }; -}; - -&ap_i2c_tp { - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int_l>; - wakeup-source; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_alert1 { - temperature = <70000>; -}; - -&spi0 { - status = "okay"; - - cr50@0 { - compatible = "google,cr50"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <5 IRQ_TYPE_EDGE_RISING>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_int_od_l>; - spi-max-frequency = <800000>; - }; -}; - -&pinctrl { - tpm { - h1_int_od_l: h1-int-od-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi deleted file mode 100644 index 1384dabbdf4067b38af92ccf017f6afc9c6fec11..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ /dev/null @@ -1,400 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Chromebook shared properties - * - * Copyright 2018 Google, Inc - */ - -#include "rk3399-gru.dtsi" - -/ { - pp900_ap: pp900-ap { - compatible = "regulator-fixed"; - regulator-name = "pp900_ap"; - - /* EC turns on w/ pp900_ap_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - - /* EC turns on w/ pp900_usb_en */ - pp900_usb: pp900-ap { - }; - - /* EC turns on w/ pp900_pcie_en */ - pp900_pcie: pp900-ap { - }; - - pp3000: pp3000 { - compatible = "regulator-fixed"; - regulator-name = "pp3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3000_en>; - - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - vin-supply = <&ppvar_sys>; - }; - - ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_centerlogic_pwm"; - - pwms = <&pwm3 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - }; - - ppvar_centerlogic: ppvar-centerlogic { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_centerlogic"; - - regulator-min-microvolt = <799434>; - regulator-max-microvolt = <1049925>; - - ctrl-supply = <&ppvar_centerlogic_pwm>; - ctrl-voltage-range = <799434 1049925>; - - regulator-settling-time-up-us = <378>; - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; - }; - - /* Schematics call this PPVAR even though it's fixed */ - ppvar_logic: ppvar-logic { - compatible = "regulator-fixed"; - regulator-name = "ppvar_logic"; - - /* EC turns on w/ ppvar_logic_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - vin-supply = <&ppvar_sys>; - }; - - pp1800_audio: pp1800-audio { - compatible = "regulator-fixed"; - regulator-name = "pp1800_audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1800_audio_en>; - - enable-active-high; - gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp1800>; - }; - - /* gpio is shared with pp3300_wifi_bt */ - pp1800_pcie: pp1800-pcie { - compatible = "regulator-fixed"; - regulator-name = "pp1800_pcie"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_pd_l>; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - /* - * Need to wait 1ms + ramp-up time before we can power on WiFi. - * This has been approximated as 8ms total. - */ - regulator-enable-ramp-delay = <8000>; - - vin-supply = <&pp1800>; - }; - - /* Always on; plain and simple */ - pp3000_ap: pp3000_emmc: pp3000 { - }; - - pp1500_ap_io: pp1500-ap-io { - compatible = "regulator-fixed"; - regulator-name = "pp1500_ap_io"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1500_en>; - - enable-active-high; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - vin-supply = <&pp1800>; - }; - - pp3300_disp: pp3300-disp { - compatible = "regulator-fixed"; - regulator-name = "pp3300_disp"; - pinctrl-names = "default"; - pinctrl-0 = <&pp3300_disp_en>; - - enable-active-high; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - - startup-delay-us = <2000>; - vin-supply = <&pp3300>; - }; - - /* EC turns on w/ pp3300_usb_en_l */ - pp3300_usb: pp3300 { - }; - - /* gpio is shared with pp1800_pcie and pinctrl is set there */ - pp3300_wifi_bt: pp3300-wifi-bt { - compatible = "regulator-fixed"; - regulator-name = "pp3300_wifi_bt"; - - enable-active-high; - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp3300>; - }; - - /* - * This is a bit of a hack. The WiFi module should be reset at least - * 1ms after its regulators have ramped up (max rampup time is ~7ms). - * With some stretching of the imagination, we can call the 1.8V - * regulator a supply. - */ - wlan_pd_n: wlan-pd-n { - compatible = "regulator-fixed"; - regulator-name = "wlan_pd_n"; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_module_reset_l>; - - enable-active-high; - gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp1800_pcie>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - power-supply = <&pp3300_disp>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwm-delay-us = <10000>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>; - - wake_on_bt: wake-on-bt { - label = "Wake-on-Bluetooth"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; -}; - -&ppvar_bigcpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&ppvar_litcpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&ppvar_gpu { - min-slew-down-rate = <225>; - ovp-threshold-percent = <16>; -}; - -&cdn_dp { - extcon = <&usbc_extcon0>, <&usbc_extcon1>; -}; - -&edp { - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -ap_i2c_mic: &i2c1 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - headsetcodec: rt5514@57 { - compatible = "realtek,rt5514"; - reg = <0x57>; - realtek,dmic-init-delay-ms = <20>; - }; -}; - -ap_i2c_tp: &i2c5 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - /* - * Note strange pullup enable. Apparently this avoids leakage but - * still allows us to get nice 4.7K pullups for high speed i2c - * transfers. Basically we want the pullup on whenever the ap is - * alive, so the "en" pin just gets set to output high. - */ - pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; -}; - -&cros_ec { - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - usbc_extcon1: extcon1 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <1>; - }; -}; - -&sound { - rockchip,codec = <&max98357a &headsetcodec - &codec &wacky_spi_audio &cdn_dp>; -}; - -&spi2 { - wacky_spi_audio: spi2@0 { - compatible = "realtek,rt5514"; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mic_int>; - /* May run faster once verified. */ - spi-max-frequency = <10000000>; - wakeup-source; - }; -}; - -&pci_rootport { - mvl_wifi: wifi@0,0 { - compatible = "pci1b4b,2b42"; - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_host_wake_l>; - wakeup-source; - }; -}; - -&tcphy1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - -&u2phy1 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; - extcon = <&usbc_extcon1>; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&pinctrl { - discrete-regulators { - pp1500_en: pp1500-en { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp1800_audio_en: pp1800-audio-en { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO - &pcfg_pull_down>; - }; - - pp3000_en: pp3000-en { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - pp3300_disp_en: pp3300-disp-en { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - wlan_module_pd_l: wlan-module-pd-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO - &pcfg_pull_down>; - }; - }; -}; - -&wifi { - wifi_perst_l: wifi-perst-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; -}; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts deleted file mode 100644 index 2bbef9fcbe2704065b2999d0b113b4cf34b318a2..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru-Kevin Rev 6+ board device tree source - * - * Copyright 2016-2017 Google, Inc - */ - -/dts-v1/; -#include "rk3399-gru-chromebook.dtsi" -#include - -/* - * Kevin-specific things - * - * Things in this section should use names from Kevin schematic since no - * equivalent exists in Gru schematic. If referring to signals that exist - * in Gru we use the Gru names, though. Confusing enough for you? - */ -/ { - model = "Google Kevin"; - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - - /* Power tree */ - - p3_3v_dig: p3-3v-dig { - compatible = "regulator-fixed"; - regulator-name = "p3.3v_dig"; - pinctrl-names = "default"; - pinctrl-0 = <&cpu3_pen_pwr_en>; - - enable-active-high; - gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; - vin-supply = <&pp3300>; - }; - - edp_panel: edp-panel { - compatible = "sharp,lq123p1jx31"; - backlight = <&backlight>; - power-supply = <&pp3300_disp>; - - panel-timing { - clock-frequency = <266666667>; - hactive = <2400>; - hfront-porch = <48>; - hback-porch = <84>; - hsync-len = <32>; - hsync-active = <0>; - vactive = <1600>; - vfront-porch = <3>; - vback-porch = <120>; - vsync-len = <10>; - vsync-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <25500>; - pulldown-ohm = <0>; - io-channels = <&saradc 2>; - #thermal-sensor-cells = <0>; - }; - - thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { - compatible = "murata,ncp15wb473"; - pullup-uv = <1800000>; - pullup-ohm = <25500>; - pulldown-ohm = <0>; - io-channels = <&saradc 3>; - #thermal-sensor-cells = <0>; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 1>; -}; - -&gpio_keys { - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; - - pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; -}; - -&thermal_zones { - bigcpu_reg_thermal: bigcpu-reg-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermistor_ppvar_bigcpu 0>; - sustainable-power = <4000>; - - ppvar_bigcpu_trips: trips { - ppvar_bigcpu_on: ppvar-bigcpu-on { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_bigcpu_alert: ppvar-bigcpu-alert { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_bigcpu_crit: ppvar-bigcpu-crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&ppvar_bigcpu_alert>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - map1 { - trip = <&ppvar_bigcpu_alert>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - }; - }; - - litcpu_reg_thermal: litcpu-reg-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&thermistor_ppvar_litcpu 0>; - sustainable-power = <4000>; - - ppvar_litcpu_trips: trips { - ppvar_litcpu_on: ppvar-litcpu-on { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_litcpu_alert: ppvar-litcpu-alert { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ppvar_litcpu_crit: ppvar-litcpu-crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - }; -}; - -ap_i2c_tpm: &i2c0 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times. */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -ap_i2c_dig: &i2c2 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times. */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - digitizer: digitizer@9 { - /* wacom,w9013 */ - compatible = "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; - - vdd-supply = <&p3_3v_dig>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&gpio2>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -/* Adjustments to things in the gru baseboard */ - -&ap_i2c_tp { - trackpad@4a { - compatible = "atmel,maxtouch"; - reg = <0x4a>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int_l>; - interrupt-parent = <&gpio1>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - linux,gpio-keymap = ; - wakeup-source; - }; -}; - -&ap_i2c_ts { - touchscreen@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int_l>; - interrupt-parent = <&gpio3>; - interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ppvar_bigcpu_pwm { - regulator-min-microvolt = <798674>; - regulator-max-microvolt = <1302172>; -}; - -&ppvar_bigcpu { - regulator-min-microvolt = <798674>; - regulator-max-microvolt = <1302172>; - ctrl-voltage-range = <798674 1302172>; -}; - -&ppvar_litcpu_pwm { - regulator-min-microvolt = <799065>; - regulator-max-microvolt = <1303738>; -}; - -&ppvar_litcpu { - regulator-min-microvolt = <799065>; - regulator-max-microvolt = <1303738>; - ctrl-voltage-range = <799065 1303738>; -}; - -&ppvar_gpu_pwm { - regulator-min-microvolt = <785782>; - regulator-max-microvolt = <1217729>; -}; - -&ppvar_gpu { - regulator-min-microvolt = <785782>; - regulator-max-microvolt = <1217729>; - ctrl-voltage-range = <785782 1217729>; -}; - -&ppvar_centerlogic_pwm { - regulator-min-microvolt = <800069>; - regulator-max-microvolt = <1049692>; -}; - -&ppvar_centerlogic { - regulator-min-microvolt = <800069>; - regulator-max-microvolt = <1049692>; - ctrl-voltage-range = <800069 1049692>; -}; - -&saradc { - status = "okay"; - vref-supply = <&pp1800_ap_io>; -}; - -&mvl_wifi { - marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ -}; - -&pinctrl { - digitizer { - /* Has external pullup */ - cpu1_dig_irq_l: cpu1-dig-irq-l { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - /* Has external pullup */ - cpu1_dig_pdct_l: cpu1-dig-pdct-l { - rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - discrete-regulators { - cpu3_pen_pwr_en: cpu3-pen-pwr-en { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pen { - cpu1_pen_eject: cpu1-pen-eject { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index b1604a6872c018fc7261f82781c86f32c6389aea..6bdc892bd913a86927a8c223b70203a338ef3a0f 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -54,12 +54,38 @@ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; +&sdhci { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_bus4 { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_cd { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_clk { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_cmd { + /delete-property/ bootph-pre-ram; +}; + +&spi1 { + spi_flash: flash@0 { + bootph-all; + }; +}; + &spi5 { spi-activate-delay = <100>; spi-max-frequency = <3000000>; spi-deactivate-delay = <200>; }; - -&spi_flash { - bootph-all; -}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi deleted file mode 100644 index b80f19066b5764ac8c60724fe2853908c990e522..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-gru.dtsi +++ /dev/null @@ -1,829 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Gru (and derivatives) board device tree source - * - * Copyright 2016-2017 Google, Inc - */ - -#include -#include "rk3399.dtsi" -#include "rk3399-op1-opp.dtsi" - -/ { - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - /* - * Power Tree - * - * In general an attempt is made to include all rails called out by - * the schematic as long as those rails interact in some way with - * the AP. AKA: - * - Rails that only connect to the EC (or devices that the EC talks to) - * are not included. - * - Rails _are_ included if the rails go to the AP even if the AP - * doesn't currently care about them / they are always on. The idea - * here is that it makes it easier to map to the schematic or extend - * later. - * - * If two rails are substantially the same from the AP's point of - * view, though, we won't create a full fixed regulator. We'll just - * put the child rail as an alias of the parent rail. Sometimes rails - * look the same to the AP because one of these is true: - * - The EC controls the enable and the EC always enables a rail as - * long as the AP is running. - * - The rails are actually connected to each other by a jumper and - * the distinction is just there to add clarity/flexibility to the - * schematic. - */ - - ppvar_sys: ppvar-sys { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - pp1200_lpddr: pp1200-lpddr { - compatible = "regulator-fixed"; - regulator-name = "pp1200_lpddr"; - - /* EC turns on w/ lpddr_pwr_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - vin-supply = <&ppvar_sys>; - }; - - pp1800: pp1800 { - compatible = "regulator-fixed"; - regulator-name = "pp1800"; - - /* Always on when ppvar_sys shows power good */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300: pp3300 { - compatible = "regulator-fixed"; - regulator-name = "pp3300"; - - /* Always on; plain and simple */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&ppvar_sys>; - }; - - pp5000: pp5000 { - compatible = "regulator-fixed"; - regulator-name = "pp5000"; - - /* EC turns on w/ pp5000_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_bigcpu_pwm"; - - pwms = <&pwm1 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800107>; - regulator-max-microvolt = <1302232>; - }; - - ppvar_bigcpu: ppvar-bigcpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_bigcpu"; - - regulator-min-microvolt = <800107>; - regulator-max-microvolt = <1302232>; - - ctrl-supply = <&ppvar_bigcpu_pwm>; - ctrl-voltage-range = <800107 1302232>; - - regulator-settling-time-up-us = <322>; - }; - - ppvar_litcpu_pwm: ppvar-litcpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_litcpu_pwm"; - - pwms = <&pwm2 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <797743>; - regulator-max-microvolt = <1307837>; - }; - - ppvar_litcpu: ppvar-litcpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_litcpu"; - - regulator-min-microvolt = <797743>; - regulator-max-microvolt = <1307837>; - - ctrl-supply = <&ppvar_litcpu_pwm>; - ctrl-voltage-range = <797743 1307837>; - - regulator-settling-time-up-us = <384>; - }; - - ppvar_gpu_pwm: ppvar-gpu-pwm { - compatible = "pwm-regulator"; - regulator-name = "ppvar_gpu_pwm"; - - pwms = <&pwm0 0 3337 0>; - pwm-supply = <&ppvar_sys>; - pwm-dutycycle-range = <100 0>; - pwm-dutycycle-unit = <100>; - - /* EC turns on w/ ap_core_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <786384>; - regulator-max-microvolt = <1217747>; - }; - - ppvar_gpu: ppvar-gpu { - compatible = "vctrl-regulator"; - regulator-name = "ppvar_gpu"; - - regulator-min-microvolt = <786384>; - regulator-max-microvolt = <1217747>; - - ctrl-supply = <&ppvar_gpu_pwm>; - ctrl-voltage-range = <786384 1217747>; - - regulator-settling-time-up-us = <390>; - }; - - /* EC turns on w/ pp900_ddrpll_en */ - pp900_ddrpll: pp900-ap { - }; - - /* EC turns on w/ pp900_pll_en */ - pp900_pll: pp900-ap { - }; - - /* EC turns on w/ pp900_pmu_en */ - pp900_pmu: pp900-ap { - }; - - /* EC turns on w/ pp1800_s0_en_l */ - pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { - }; - - /* EC turns on w/ pp1800_avdd_en_l */ - pp1800_avdd: pp1800 { - }; - - /* EC turns on w/ pp1800_lid_en_l */ - pp1800_lid: pp1800_mic: pp1800 { - }; - - /* EC turns on w/ lpddr_pwr_en */ - pp1800_lpddr: pp1800 { - }; - - /* EC turns on w/ pp1800_pmu_en_l */ - pp1800_pmu: pp1800 { - }; - - /* EC turns on w/ pp1800_usb_en_l */ - pp1800_usb: pp1800 { - }; - - pp3000_sd_slot: pp3000-sd-slot { - compatible = "regulator-fixed"; - regulator-name = "pp3000_sd_slot"; - pinctrl-names = "default"; - pinctrl-0 = <&sd_slot_pwr_en>; - - enable-active-high; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - - vin-supply = <&pp3000>; - }; - - /* - * Technically, this is a small abuse of 'regulator-gpio'; this - * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are - * always on though, so it is sufficient to simply control the mux - * here. - */ - ppvar_sd_card_io: ppvar-sd-card-io { - compatible = "regulator-gpio"; - regulator-name = "ppvar_sd_card_io"; - pinctrl-names = "default"; - pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; - - enable-active-high; - enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; - gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1>, - <3000000 0x0>; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - - /* EC turns on w/ pp3300_trackpad_en_l */ - pp3300_trackpad: pp3300-trackpad { - }; - - /* EC turns on w/ usb_a_en */ - pp5000_usb_a_vbus: pp5000 { - }; - - ap_rtc_clk: ap-rtc-clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - max98357a: max98357a { - compatible = "maxim,max98357a"; - pinctrl-names = "default"; - pinctrl-0 = <&sdmode_en>; - sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - sdmode-delay = <2>; - #sound-dai-cells = <0>; - status = "okay"; - }; - - sound: sound { - compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0 &i2s2>; - }; -}; - -&cdn_dp { - status = "okay"; -}; - -/* - * Set some suspend operating points to avoid OVP in suspend - * - * When we go into S3 ARM Trusted Firmware will transition our PWM regulators - * from wherever they're at back to the "default" operating point (whatever - * voltage we get when we set the PWM pins to "input"). - * - * This quick transition under light load has the possibility to trigger the - * regulator "over voltage protection" (OVP). - * - * To make extra certain that we don't hit this OVP at suspend time, we'll - * transition to a voltage that's much closer to the default (~1.0 V) so that - * there will not be a big jump. Technically we only need to get within 200 mV - * of the default voltage, but the speed here should be fast enough and we need - * suspend/resume to be rock solid. - */ - -&cluster0_opp { - opp05 { - opp-suspend; - }; -}; - -&cluster1_opp { - opp06 { - opp-suspend; - }; -}; - -&cpu_l0 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l1 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l2 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_l3 { - cpu-supply = <&ppvar_litcpu>; -}; - -&cpu_b0 { - cpu-supply = <&ppvar_bigcpu>; -}; - -&cpu_b1 { - cpu-supply = <&ppvar_bigcpu>; -}; - - -&cru { - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, - <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, - <&cru PCLK_PERIHP>, - <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>, <&cru ACLK_HDCP>, - <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; - assigned-clock-rates = - <600000000>, <800000000>, - <1000000000>, - <150000000>, <75000000>, - <37500000>, - <100000000>, <100000000>, - <50000000>, <800000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, - <200000000>, - <200000000>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gpu { - mali-supply = <&ppvar_gpu>; - status = "okay"; -}; - -ap_i2c_ts: &i2c3 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; -}; - -ap_i2c_audio: &i2c8 { - status = "okay"; - - clock-frequency = <400000>; - - /* These are relatively safe rise/fall times */ - i2c-scl-falling-time-ns = <50>; - i2c-scl-rising-time-ns = <300>; - - codec: da7219@1a { - compatible = "dlg,da7219"; - reg = <0x1a>; - interrupt-parent = <&gpio1>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - dlg,micbias-lvl = <2600>; - dlg,mic-amp-in-sel = "diff"; - pinctrl-names = "default"; - pinctrl-0 = <&headset_int_l>; - VDD-supply = <&pp1800>; - VDDMIC-supply = <&pp3300>; - VDDIO-supply = <&pp1800>; - - da7219_aad { - dlg,adc-1bit-rpt = <1>; - dlg,btn-avg = <4>; - dlg,btn-cfg = <50>; - dlg,mic-det-thr = <500>; - dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; - dlg,jack-rem-deb = <1>; - - dlg,a-d-btn-thr = <0xa>; - dlg,d-b-btn-thr = <0x16>; - dlg,b-c-btn-thr = <0x21>; - dlg,c-mic-btn-thr = <0x3E>; - }; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ - bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ - gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ - sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ -}; - -&pcie0 { - status = "okay"; - - ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; - vpcie3v3-supply = <&pp3300_wifi_bt>; - vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ - vpcie0v9-supply = <&pp900_pcie>; - - pci_rootport: pcie@0,0 { - reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - status = "okay"; - - pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdhci { - /* - * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the - * same (or nearly the same) performance for all eMMC that are intended - * to be used. - */ - assigned-clock-rates = <150000000>; - - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - - /* - * Note: configure "sdmmc_cd" as card detect even though it's actually - * hooked to ground. Because we specified "cd-gpios" below dw_mmc - * should be ignoring card detect anyway. Specifying the pin as - * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) - * turned on that the system will still make sure the port is - * configured as SDMMC and not JTAG. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin - &sdmmc_bus4>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&pp3000_sd_slot>; - vqmmc-supply = <&ppvar_sd_card_io>; -}; - -&spi1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&spi1_sleep>; - - spi_flash: spiflash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* May run faster once verified. */ - spi-max-frequency = <10000000>; - }; -}; - -&spi2 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbc_extcon0: extcon0 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <0>; - }; - }; -}; - -&tsadc { - status = "okay"; - - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ -}; - -&tcphy0 { - status = "okay"; - extcon = <&usbc_extcon0>; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - status = "okay"; -}; - -&u2phy1_host { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; - extcon = <&usbc_extcon0>; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -#include -#include - -&pinctrl { - /* - * pinctrl settings for pins that have no real owners. - * - * At the moment settings are identical for S0 and S3, but if we later - * need to configure things differently for S3 we'll adjust here. - */ - pinctrl-names = "default"; - pinctrl-0 = < - &ap_pwroff /* AP will auto-assert this when in S3 */ - &clk_32k /* This pin is always 32k on gru boards */ - >; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - backlight-enable { - bl_en: bl-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cros-ec { - ec_ap_int_l: ec-ap-int-l { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - discrete-regulators { - sd_io_pwr_en: sd-io-pwr-en { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - sd_pwr_1800_sel: sd-pwr-1800-sel { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - - sd_slot_pwr_en: sd-slot-pwr-en { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO - &pcfg_pull_none>; - }; - }; - - codec { - /* Has external pullup */ - headset_int_l: headset-int-l { - rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mic_int: mic-int { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - max98357a { - sdmode_en: sdmode-en { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - pcie { - pcie_clkreqn_cpm: pci-clkreqn-cpm { - /* - * Since our pcie doesn't support ClockPM(CPM), we want - * to hack this as gpio, so the EP could be able to - * de-assert it along and make ClockPM(CPM) work. - */ - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * We run sdmmc at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_none_8ma>, - <4 RK_PB1 1 &pcfg_pull_none_8ma>, - <4 RK_PB2 1 &pcfg_pull_none_8ma>, - <4 RK_PB3 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_none_8ma>; - }; - - /* - * In our case the official card detect is hooked to ground - * to avoid getting access to JTAG just by sticking something - * in the SD card slot (see the force_jtag bit in the TRM). - * - * We still configure it as card detect because it doesn't - * hurt and dw_mmc will ignore it. We make sure to disable - * the pull though so we don't burn needless power. - */ - sdmmc_cd: sdmmc-cd { - rockchip,pins = - <0 RK_PA7 1 &pcfg_pull_none>; - }; - - /* This is where we actually hook up CD; has external pull */ - sdmmc_cd_pin: sdmmc-cd-pin { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - spi1 { - spi1_sleep: spi1-sleep { - /* - * Pull down SPI1 CLK/CS/RX/TX during suspend, to - * prevent leakage. - */ - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, - <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - touchscreen { - touch_int_l: touch-int-l { - rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - touch_reset_l: touch-reset-l { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - trackpad { - ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; - }; - - trackpad_int_l: trackpad-int-l { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wifi: wifi { - wlan_module_reset_l: wlan-module-reset-l { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - /* Kevin has an external pull up, but Gru does not */ - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - write-protect { - ap_fw_wp: ap-fw-wp { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts deleted file mode 100644 index 8302e51def52a382ef9a442509f6dab44d414c71..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-khadas-edge-captain.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge-Captain"; - compatible = "khadas,edge-captain", "rockchip,rk3399"; -}; - -&gmac { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi index a7039d74a0167b44be29473e3e670a9a5514fc14..dd7a84d2b4a8697bad8b9bc0b078dd8389832631 100644 --- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -6,10 +6,9 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; +&spiflash { + bootph-pre-ram; + bootph-some-ram; }; &vdd_log { diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts deleted file mode 100644 index f5dcb99dc3495a571ee44ec68ce5f78c37cdb126..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-khadas-edge-v.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge-V"; - compatible = "khadas,edge-v", "rockchip,rk3399"; -}; - -&gmac { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-khadas-edge.dts b/arch/arm/dts/rk3399-khadas-edge.dts deleted file mode 100644 index 31616e7ad89dc49bb4012f75e6ac0d23e676f5dd..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-khadas-edge.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include "rk3399-khadas-edge.dtsi" - -/ { - model = "Khadas Edge"; - compatible = "khadas,edge", "rockchip,rk3399"; -}; diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi deleted file mode 100644 index d5c7648c841dc7d12ca42aae4d0ab85b774caa3f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ /dev/null @@ -1,837 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. - * (https://www.khadas.com) - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vsys_5v0>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vsys_3v3>; - }; - - vsys: vsys { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: vsys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys>; - }; - - vsys_5v0: vsys-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vsys>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - linux,rc-map-name = "rc-khadas"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>, <&user_led_pin>; - - sys_led: led-0 { - label = "sys_led"; - linux,default-trigger = "heartbeat"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - - user_led: led-1 { - label = "user_led"; - default-state = "off"; - gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 150 200 255>; - #cooling-cells = <2>; - fan-supply = <&vsys_5v0>; - pwms = <&pwm0 0 40000 0>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_thermal { - trips { - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gpu_thermal { - trips { - gpu_warm: gpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - gpu_hot: gpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&gpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map2 { - trip = <&gpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vsys_3v3>; - vcc2-supply = <&vsys_3v3>; - vcc3-supply = <&vsys_3v3>; - vcc4-supply = <&vsys_3v3>; - vcc6-supply = <&vsys_3v3>; - vcc7-supply = <&vsys_3v3>; - vcc8-supply = <&vsys_3v3>; - vcc9-supply = <&vsys_3v3>; - vcc10-supply = <&vsys_3v3>; - vcc11-supply = <&vsys_3v3>; - vcc12-supply = <&vsys_3v3>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_apio2: LDO_REG1 { - regulator-name = "vcc1v8_apio2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_vldo2: LDO_REG2 { - regulator-name = "vcc_vldo2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_vldo5: LDO_REG5 { - regulator-name = "vcc_vldo5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc1v8_codec: LDO_REG7 { - regulator-name = "vcc1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vsys_3v3>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_apio2>; - audio-supply = <&vcc1v8_codec>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_rx: ir-rx { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led_pin: user-led-pin { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - /* WiFi & BT combo module Ampak AP6356S */ - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - vqmmc-supply = <&vcc1v8_s3>; - vmmc-supply = <&vccio_sd>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - brcm,drive-strength = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spiflash: flash@0 { - compatible = "winbond,w25q128fw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - max-speed = <4000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; - vbat-supply = <&vsys_3v3>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi index c638ce25973129f7dcfdb2d8fe2624a26542734b..03b59685063543e7c4389dbe30bc4cd35526d756 100644 --- a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts deleted file mode 100644 index 7c93f840bc64f9f2cca0f1bb7fae3eff9a452b23..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ /dev/null @@ -1,651 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Andy Yan - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Leez RK3399 P710"; - compatible = "leez,p710", "rockchip,rk3399"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - dc5v_adp: dc5v-adp { - compatible = "regulator-fixed"; - regulator-name = "dc5v_adapter"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_lan: vcc3v3-lan { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host0: vcc5v0_host1: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host3: vcc5v0-host3 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host3"; - enable-active-high; - gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host3_en>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc5v_adp>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c7>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG4 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_1v8>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - bt { - bt_reg_on_h: bt-reg-on-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - usb2 { - vcc5v0_host3_en: vcc5v0-host3-en { - rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_reg_on_h: wifi-reg-on-h { - rockchip,pins = - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - status = "okay"; - - vref-supply = <&vcc_1v8>; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host0>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host1>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts deleted file mode 100644 index 452728b82e42c64788974e23894443a281e9f232..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPC-T4 board device tree source - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <12000000>; - regulator-min-microvolt = <12000000>; - regulator-name = "vcc12v0_sys"; - }; - - vcc5v0_host0: vcc5v0-host0 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_host0"; - vin-supply = <&vcc5v0_sys>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx>; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* - * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels - * work out to 0, ~1200, ~3000, and 5000RPM respectively. - */ - cooling-levels = <0 12 18 255>; - #cooling-cells = <2>; - fan-supply = <&vcc12v0_sys>; - pwms = <&pwm1 0 50000 0>; - }; -}; - -&cpu_thermal { - trips { - cpu_warm: cpu_warm { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu_hot { - temperature = <65000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map2 { - trip = <&cpu_warm>; - cooling-device = <&fan THERMAL_NO_LIMIT 1>; - }; - - map3 { - trip = <&cpu_hot>; - cooling-device = <&fan 2 THERMAL_NO_LIMIT>; - }; - }; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - vpcie3v3-supply = <&vcc3v3_sys>; -}; - -&pinctrl { - ir { - ir_rx: ir-rx { - /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; -}; - -&sdhci { - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host0>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host0>; -}; - -&vcc5v0_sys { - vin-supply = <&vcc12v0_sys>; -}; - -&vcc3v3_sys { - vin-supply = <&vcc12v0_sys>; -}; - -&vbus_typec { - enable-active-high; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; -}; diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts index 60358ab8c7dfcc7d0b061cdc2f299f99342c4535..e9cf71f224a323c24f654e2219e5ddd27f8c7b9a 100644 --- a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -10,57 +10,4 @@ */ /dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi M4"; - compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb2"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; +#include "rk3399-nanopi-m4.dts" diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts b/arch/arm/dts/rk3399-nanopi-m4.dts deleted file mode 100644 index 60358ab8c7dfcc7d0b061cdc2f299f99342c4535..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopi-m4.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPi M4 board device tree source - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi M4"; - compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb2"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts b/arch/arm/dts/rk3399-nanopi-m4b.dts deleted file mode 100644 index 72182c58cc46aa17a644381aa7ab7890cb727541..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopi-m4b.dts +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPi M4B board device tree source - * - * Copyright (c) 2020 Chen-Yu Tsai - */ - -/dts-v1/; -#include "rk3399-nanopi-m4.dts" - -/ { - model = "FriendlyElec NanoPi M4B"; - compatible = "friendlyarm,nanopi-m4b", "rockchip,rk3399"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1500000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; -}; - -/* No USB type-C PD power manager */ -/delete-node/ &fusb0; - -&i2c4 { - status = "disabled"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&u2phy0_otg { - phy-supply = <&vbus_typec>; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_usb1>; -}; - -&vbus_typec { - enable-active-high; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/rk3399-nanopi-neo4.dts b/arch/arm/dts/rk3399-nanopi-neo4.dts deleted file mode 100644 index 195410b089b94a9f74a8d209a88474c654efeb06..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopi-neo4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Amarula Solutions B.V. - * Author: Jagan Teki - */ - -/dts-v1/; - -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyARM NanoPi NEO4"; - compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts deleted file mode 100644 index cef4d18b599dd10b161a33f9b3a15702534757b6..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopi-r4s.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * FriendlyElec NanoPC-T4 board device tree source - * - * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * - * Copyright (c) 2020 Jensen Huang - * Copyright (c) 2020 Marty Jones - * Copyright (c) 2021 Tianling Shen - */ - -/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - - /delete-node/ display-subsystem; - - gpio-leds { - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; - - /delete-node/ led-0; - - lan_led: led-lan { - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; - }; - - sys_led: led-sys { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:power"; - default-state = "on"; - }; - - wan_led: led-wan { - gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; - }; - }; - - gpio-keys { - pinctrl-0 = <&reset_button_pin>; - - /delete-node/ power; - - reset { - debounce-interval = <50>; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&emmc_phy { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&pcie0 { - max-link-speed = <1>; - num-lanes = <1>; - vpcie3v3-supply = <&vcc3v3_sys>; -}; - -&pinctrl { - gpio-leds { - /delete-node/ status-led-pin; - - lan_led_pin: lan-led-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - sys_led_pin: sys-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rockchip-key { - /delete-node/ power-key; - - reset_button_pin: reset-button-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&sdhci { - status = "disabled"; -}; - -&sdio0 { - status = "disabled"; -}; - -&u2phy0_host { - phy-supply = <&vdd_5v>; -}; - -&u2phy1_host { - status = "disabled"; -}; - -&uart0 { - status = "disabled"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_sys>; -}; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index a9d10592d573fba875f99f878b28a90e8123364d..7573612499681a139702845cd9d59c6cd3e38d87 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -5,12 +5,22 @@ #include "rk3399-u-boot.dtsi" -/{ - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; +&gpio0 { + bootph-pre-ram; }; &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; }; + +&sdmmc0_pwr_h { + bootph-pre-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; +}; + +&vcc_sdio { + regulator-init-microvolt = <3000000>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi deleted file mode 100644 index 8c0ff6c96e03789ad7a99c471e62f9a950e5fbb8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * RK3399-based FriendlyElec boards device tree source - * - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - * - * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) - * - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2019 Arm Ltd. - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_sys"; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vcc5v0_sys"; - vin-supply = <&vdd_5v>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_s3"; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - /* - * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only - * drives the enable pin, but we can't quite model that. - */ - vcca0v9_s3: vcca0v9-s3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vcca0v9_s3"; - vin-supply = <&vcc1v8_s3>; - }; - - /* As above, actually supplied by vcc3v3_sys */ - vcca1v8_s3: vcca1v8-s3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_s3"; - vin-supply = <&vcc1v8_s3>; - }; - - vbus_typec: vbus-typec { - compatible = "regulator-fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vbus_typec"; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&power_key>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&status_led_pin>; - - status_led: led-0 { - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clock-parents = <&clkin_gmac>; - assigned-clocks = <&cru SCLK_RMII_SRC>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; - phy-handle = <&rtl8211e>; - phy-mode = "rgmii"; - phy-supply = <&vcc3v3_s3>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c7>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_cpu_b"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd_gpu"; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - clock-output-names = "xin32k", "rtc_clko_wifi"; - #clock-cells = <1>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_center"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_cpu_l"; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_cam: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_cam"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc3v0_touch"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_pmupll"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <3000000>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sdio"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcca3v0_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc_1v5"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_codec"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc_3v0"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s3"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <200000>; - i2c-scl-rising-time-ns = <150>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <160>; - i2c-scl-falling-time-ns = <30>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vbus_typec>; - }; -}; - -&i2c7 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pcie_phy { - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - status = "okay"; -}; - -&pcie0 { - num-lanes = <2>; - vpcie0v9-supply = <&vcca0v9_s3>; - vpcie1v8-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&pinctrl { - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - status_led_pin: status-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - gmac { - phy_intb: phy-intb { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rstb: phy-rstb { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - power_key: power-key { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio { - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - /* external pullup to VCC1V8_PMUPLL */ - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_reg_on_h: wifi-reg_on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc0_det_l: sdmmc0-det-l { - rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm2_pin_pull_down>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_host { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy1_host { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <4000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi deleted file mode 100644 index 69cc9b05baa572344d78d8176ebe895652f4a9af..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/ { - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <900000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <975000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1100000>; - }; - opp06 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1150000>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <800000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <850000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <900000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <975000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1050000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1150000>; - }; - opp08 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <1250000>; - }; - }; - - gpu_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <800000>; - }; - opp01 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <800000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <850000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000>; - }; - opp05 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1075000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi deleted file mode 100644 index da41cd81ebb77c76bd50f0a0db90347df2878bde..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-opp.dtsi +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -/ { - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <825000 825000 1250000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000 825000 1250000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000 850000 1250000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000 925000 1250000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000 1000000 1250000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1125000 1125000 1250000>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <825000 825000 1250000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000 825000 1250000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <825000 825000 1250000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <875000 875000 1250000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000 950000 1250000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000 1025000 1250000>; - }; - opp06 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000 1100000 1250000>; - }; - opp07 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1200000 1200000 1250000>; - }; - }; - - gpu_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000 825000 1150000>; - }; - opp01 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <825000 825000 1150000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000 825000 1150000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <875000 875000 1150000>; - }; - opp04 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <925000 925000 1150000>; - }; - opp05 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1100000 1100000 1150000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi index d4327ea607c4360244253bc678b6638265baf329..b7452eca22548477cde863e2e5161d58bc343dac 100644 --- a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi +++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi @@ -6,6 +6,18 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1333.dtsi" +&gpio0 { + bootph-pre-ram; +}; + +&sdmmc0_pwr_h { + bootph-pre-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; +}; + &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts deleted file mode 100644 index 04b54abea3cc070511fd082e7a2f26e06e97338b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-orangepi.dts +++ /dev/null @@ -1,894 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/input/input.h" -#include "dt-bindings/usb/pd.h" -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Orange Pi RK3399 Board"; - compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <100000>; - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <300000>; - }; - - back { - label = "Back"; - linux,code = ; - press-threshold-microvolt = <985000>; - }; - - menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <1314000>; - }; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - linux,input-type = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_btn>; - wakeup-source; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-boot-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc3v0_sd"; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus_typec"; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_s3>; - phy-mode = "rgmii"; - phy-handle = <&rtl8211e>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - rtl8211e: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_tp: LDO_REG2 { - regulator-name = "vcc3v0_tp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3400000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&cpu_b_sleep>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpu_sleep>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - ak09911@c { - compatible = "asahi-kasei,ak09911"; - reg = <0x0c>; - vdd-supply = <&vcc3v3_s3>; - vid-supply = <&vcc3v3_s3>; - }; - - mpu6500@68 { - compatible = "invensense,mpu6500"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int_l>; - vddio-supply = <&vcc3v3_s3>; - }; - - lsm6ds3@6a { - compatible = "st,lsm6ds3"; - reg = <0x6a>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&gyr_int_l>; - vdd-supply = <&vcc3v3_s3>; - vddio-supply = <&vcc3v3_s3>; - }; - - cm32181@10 { - compatible = "capella,cm32181"; - reg = <0x10>; - interrupt-parent = <&gpio4>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&light_int_l>; - vdd-supply = <&vcc3v3_s3>; - }; - - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&chg_cc_int_l>; - vbus-supply = <&vbus_typec>; - - typec_con: connector { - compatible = "usb-c-connector"; - data-role = "host"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - typec_hs: endpoint { - remote-endpoint = <&u2phy0_typec_hs>; - }; - }; - port@1 { - reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&tcphy0_typec_ss>; - }; - }; - port@2 { - reg = <2>; - typec_dp: endpoint { - remote-endpoint = <&tcphy0_typec_dp>; - }; - }; - }; - }; - }; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcc_3v0>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_3v0>; -}; - -&pinctrl { - buttons { - pwr_btn: pwr-btn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gmac { - phy_intb: phy-intb { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rstb: phy-rstb { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - cpu_b_sleep: cpu-b-sleep { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - gpu_sleep: gpu-sleep { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sd { - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = - <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_reg_on_h: wifi-reg-on-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - bluetooth { - bt_reg_on_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - mpu6500 { - gsensor_int_l: gsensor-int-l { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lsm6ds3 { - gyr_int_l: gyr-int-l { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cm32181 { - light_int_l: light-int-l { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb302 { - chg_cc_int_l: chg-cc-int-l { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - clock-frequency = <50000000>; - disable-wp; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - clock-frequency = <150000000>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy0_dp { - port { - tcphy0_typec_dp: endpoint { - remote-endpoint = <&typec_dp>; - }; - }; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vbus_typec>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 88a77cad8d43cbe53b72d5f678d2a3f19b74e2fe..2341db444ef358de087d5c1f3ca907090668057c 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -6,28 +6,33 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; - }; -}; - &edp { rockchip,panel = <&edp_panel>; }; +&gpio0 { + bootph-pre-ram; +}; + &sdhci { max-frequency = <25000000>; - bootph-all; }; &sdmmc { max-frequency = <20000000>; - bootph-all; +}; + +&sdmmc0_pwr_h_pin { + bootph-pre-ram; }; &spiflash { - bootph-all; + bootph-pre-ram; + bootph-some-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; }; &vdd_log { diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts deleted file mode 100644 index d6b68d77d63a5f2d1ea77e6df8fb9f5f631c4ed8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ /dev/null @@ -1,1121 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2020 Tobias Schramm - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Pine64 Pinebook Pro"; - compatible = "pine64,pinebook-pro", "rockchip,rk3399"; - chassis-type = "laptop"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: edp-backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_12v>; - pwms = <&pwm0 0 740740 0>; - }; - - bat: battery { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <9800000>; - voltage-max-design-microvolt = <4350000>; - voltage-min-design-microvolt = <3000000>; - }; - - edp_panel: edp-panel { - compatible = "boe,nv140fhmn49"; - backlight = <&backlight>; - enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_en_pin>; - power-supply = <&vcc3v3_panel>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_in_edp: endpoint@0 { - reg = <0>; - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - }; - - /* - * Use separate nodes for gpio-keys to allow for selective deactivation - * of wakeup sources via sysfs without disabling the whole key - */ - gpio-key-lid { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&lidbtn_pin>; - - lid { - debounce-interval = <20>; - gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; - label = "Lid"; - linux,code = ; - linux,input-type = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - gpio-key-power { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn_pin>; - - power { - debounce-interval = <20>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_led_pin &slp_led_pin>; - - green_led: led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - label = "green:power"; - }; - - red_led: led-1 { - color = ; - default-state = "off"; - function = LED_FUNCTION_STANDBY; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "red:standby"; - panic-indicator; - retain-state-suspended; - }; - }; - - /* Power sequence for SDIO WiFi module */ - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h_pin>; - post-power-on-delay-ms = <100>; - power-off-delay-us = <500000>; - - /* WL_REG_ON on module */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - /* Audio components */ - es8316-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det_pin>; - simple-audio-card,name = "rockchip,es8316-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MIC1", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker Amplifier INL", "HPOL", - "Speaker Amplifier INR", "HPOR", - "Speaker", "Speaker Amplifier OUTL", - "Speaker", "Speaker Amplifier OUTR"; - - simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - simple-audio-card,aux-devs = <&speaker_amp>; - simple-audio-card,pin-switches = "Speaker"; - - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - - simple-audio-card,codec { - sound-dai = <&es8316>; - }; - }; - - speaker_amp: speaker-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Speaker Amplifier"; - VCC-supply = <&pa_5v>; - }; - - /* Power tree */ - /* Root power source */ - vcc_sysin: vcc-sysin { - compatible = "regulator-fixed"; - regulator-name = "vcc_sysin"; - regulator-always-on; - regulator-boot-on; - }; - - /* Regulators supplied by vcc_sysin */ - /* LCD backlight supply */ - vcc_12v: vcc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc_sysin>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Main 3.3 V supply */ - vcc3v3_sys: wifi_bat: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sysin>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* 5 V USB power supply */ - vcc5v0_usb: pa_5v: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_5v_pin>; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sysin>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* RK3399 logic supply */ - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sysin>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - /* Regulators supplied by vcc3v3_sys */ - /* 0.9 V supply, always on */ - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* S3 1.8 V supply, switched by vcc1v8_s3 */ - vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcca1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* micro SD card power */ - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h_pin>; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* LCD panel power, called VCC3V3_S0 in schematic */ - vcc3v3_panel: vcc3v3-panel { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcdvcc_en_pin>; - regulator-name = "vcc3v3_panel"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <100000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* M.2 adapter power, switched by vcc1v8_s3 */ - vcc3v3_ssd: vcc3v3-ssd { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ssd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* Regulators supplied by vcc5v0_usb */ - /* USB 3 port power supply regulator */ - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en_pin>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Regulators supplied by vcc5v0_usb */ - /* Type C port power supply regulator */ - vbus_5vout: vbus_typec: vbus-5vout { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en_pin>; - regulator-name = "vbus_5vout"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Regulators supplied by vcc_1v8 */ - /* Primary 0.9 V LDO */ - vcca0v9_s3: vcca0v9-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc0v9_s3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_1v8>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - mains_charger: dc-charger { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; - - /* Also triggered by USB charger */ - pinctrl-names = "default"; - pinctrl-0 = <&dc_det_pin>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&edp { - force-hpd; - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - status = "okay"; - - ports { - edp_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&emmc_phy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <4>; - i2c-scl-rising-time-ns = <168>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l_pin>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sysin>; - vcc2-supply = <&vcc_sysin>; - vcc3-supply = <&vcc_sysin>; - vcc4-supply = <&vcc_sysin>; - vcc6-supply = <&vcc_sysin>; - vcc7-supply = <&vcc_sysin>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc_sysin>; - vcc10-supply = <&vcc_sysin>; - vcc11-supply = <&vcc_sysin>; - vcc12-supply = <&vcc3v3_sys>; - - regulators { - /* rk3399 center logic supply */ - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: vcc_wl: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* not used */ - LDO_REG1 { - }; - - /* not used */ - LDO_REG2 { - }; - - vcc1v8_pmupll: LDO_REG3 { - regulator-name = "vcc1v8_pmupll"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc_1v8>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - vin-supply = <&vcc_1v8>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - i2c-scl-falling-time-ns = <4>; - i2c-scl-rising-time-ns = <168>; - status = "okay"; - - es8316: es8316@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; -}; - -&i2c3 { - i2c-scl-falling-time-ns = <15>; - i2c-scl-rising-time-ns = <450>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-falling-time-ns = <20>; - i2c-scl-rising-time-ns = <600>; - status = "okay"; - - fusb0: fusb30x@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int_pin>; - vbus-supply = <&vbus_typec>; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc_hs: endpoint { - remote-endpoint = - <&u2phy0_typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usbc_ss: endpoint { - remote-endpoint = - <&tcphy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - - usbc_dp: endpoint { - remote-endpoint = - <&tcphy0_typec_dp>; - }; - }; - }; - }; - }; - - cw2015@62 { - compatible = "cellwise,cw2015"; - reg = <0x62>; - cellwise,battery-profile = /bits/ 8 < - 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 - 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 - 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 - 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 - 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 - 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D - 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB - 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 - >; - cellwise,monitor-interval-ms = <5000>; - monitored-battery = <&bat>; - power-supplies = <&mains_charger>, <&fusb0>; - }; -}; - -&i2s1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; - rockchip,capture-channels = <8>; - rockchip,playback-channels = <8>; - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - bus-scan-delay-ms = <1000>; - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - vpcie0v9-supply = <&vcca0v9_s3>; - vpcie1v8-supply = <&vcca1v8_s3>; - vpcie3v3-supply = <&vcc3v3_ssd>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn_pin: pwrbtn-pin { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - lidbtn_pin: lidbtn-pin { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - dc-charger { - dc_det_pin: dc-det-pin { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - es8316 { - hp_det_pin: hp-det-pin { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int_pin: fusb0-int-pin { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { - rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - lcd-panel { - lcdvcc_en_pin: lcdvcc-en-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - panel_en_pin: panel-en-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lcd_panel_reset_pin: lcd-panel-reset-pin { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - pwr_led_pin: pwr-led-pin { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - slp_led_pin: slp-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l_pin: pmic-int-l-pin { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdcard { - sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - }; - - sdio-pwrseq { - wifi_enable_h_pin: wifi-enable-h-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - pwr_5v_pin: pwr-5v-pin { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_host_en_pin: vcc5v0-host-en-pin { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - bt_wake_pin: bt-wake-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_pin: bt-host-wake-pin { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_pin: bt-reset-pin { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&spi1 { - max-freq = <10000000>; - status = "okay"; - - spiflash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - m25p,fast-read; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy0_dp { - port { - tcphy0_typec_dp: endpoint { - remote-endpoint = <&usbc_dp>; - }; - }; -}; - -&tcphy0_usb3 { - port { - tcphy0_typec_ss: endpoint { - remote-endpoint = <&usbc_ss>; - }; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; - - port { - u2phy0_typec_hs: endpoint { - remote-endpoint = <&usbc_hs>; - }; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_otg>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - vbat-supply = <&wifi_bat>; - vddio-supply = <&vcc_wl>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index cabf0a9dae89d054c655e50b94084c00c6b8ea81..037cec10ce363df5aece1533928e86e90e7b5d83 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,22 +6,22 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - -&rng { - status = "okay"; -}; - &sdhci { max-frequency = <25000000>; - bootph-all; }; &sdmmc { max-frequency = <20000000>; - bootph-all; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <10000000>; + }; }; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts deleted file mode 100644 index 04403a76238b83358957c00663d314074687c466..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-pinephone-pro.dts +++ /dev/null @@ -1,474 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Martijn Braam - * Copyright (c) 2021 Kamil Trzciński - */ - -/* - * PinePhone Pro datasheet: - * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Pine64 PinePhonePro"; - compatible = "pine64,pinephone-pro", "rockchip,rk3399"; - chassis-type = "handset"; - - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn_pin>; - - key-power { - debounce-interval = <20>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = ; - wakeup-source; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcca1v8_s3: vcc1v8-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcca1v8_s3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - regulator-always-on; - regulator-boot-on; - }; - - vcc1v8_codec: vcc1v8-codec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc1v8_codec_en>; - regulator-name = "vcc1v8_codec"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - wifi_pwrseq: sdio-wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk818 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h_pin>; - /* - * Wait between power-on and SDIO access for CYP43455 - * POR circuit. - */ - post-power-on-delay-ms = <110>; - /* - * Wait between consecutive toggles for CYP43455 CBUCK - * regulator discharge. - */ - power-off-delay-us = <10000>; - - /* WL_REG_ON on module */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_cpu_l: DCDC_REG1 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <975000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_center: DCDC_REG2 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1000000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcca3v0_codec: LDO_REG1 { - regulator-name = "vcca3v0_codec"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - vcca1v8_codec: LDO_REG3 { - regulator-name = "vcca1v8_codec"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - rk818_pwr_on: LDO_REG4 { - regulator-name = "rk818_pwr_on"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v0: LDO_REG5 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc1v8_dvp: LDO_REG7 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc3v3_s3: LDO_REG8 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG9 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - vcc3v3_s0: SWITCH_REG { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <975000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&cluster0_opp { - opp04 { - status = "disabled"; - }; - - opp05 { - status = "disabled"; - }; -}; - -&cluster1_opp { - opp06 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1100000 1100000 1150000>; - }; - - opp07 { - status = "disabled"; - }; -}; - -&io_domains { - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcca1v8_codec>; - sdmmc-supply = <&vccio_sd>; - gpio1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwrbtn_pin: pwrbtn-pin { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h_pin: wifi-enable-h-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - vcc1v8_codec_en: vcc1v8-codec-en { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-bluetooth { - bt_wake_pin: bt-wake-pin { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_pin: bt-host-wake-pin { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_pin: bt-reset-pin { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk818 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 2b3ea6da88dbc2206d5e7bde85b279c926d6647d..5a9bd320ec462b86b522cac59c685fd69e70a710 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -30,18 +30,6 @@ aliases { spi5 = &spi5; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - vin-supply = <&vcc5v0_sys>; - }; }; &binman { @@ -88,25 +76,30 @@ }; &norflash { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; -&pcfg_pull_none { +&uart0 { bootph-all; + clock-frequency = <24000000>; }; -&pcfg_pull_up { - bootph-all; +&uart0_cts { + bootph-pre-sram; + bootph-pre-ram; }; -&sdmmc_bus4 { - bootph-all; +&uart0_rts { + bootph-pre-sram; + bootph-pre-ram; }; -&sdmmc_clk { - bootph-all; +&uart0_xfer { + bootph-pre-sram; + bootph-pre-ram; }; -&sdmmc_cmd { - bootph-all; +&vdd_log { + regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts deleted file mode 100644 index 115c14c0a3c68c44be5c2ed1dc772c5d1496910b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include "rk3399-puma.dtsi" - -/ { - model = "Theobroma Systems RK3399-Q7 SoM"; - compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; - - aliases { - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; - - sd_card_led: led-1 { - label = "sd_card_led"; - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - }; - }; - - i2s0-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Haikou,I2S-codec"; - simple-audio-card,mclk-fs = <512>; - - simple-audio-card,codec { - clocks = <&sgtl5000_clk>; - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,cpu { - bitclock-master; - frame-master; - sound-dai = <&i2s0>; - }; - }; - - sgtl5000_clk: sgtl5000-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_baseboard: vcc3v3-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_baseboard: vcc5v0-baseboard { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_baseboard"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc5v0_otg"; - regulator-always-on; - }; - - vdda_codec: vdda-codec { - compatible = "regulator-fixed"; - regulator-name = "vdda_codec"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_baseboard>; - }; - - vddd_codec: vddd-codec { - compatible = "regulator-fixed"; - regulator-name = "vddd_codec"; - regulator-boot-on; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1600000>; - vin-supply = <&vcc5v0_baseboard>; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - clocks = <&sgtl5000_clk>; - #sound-dai-cells = <0>; - VDDA-supply = <&vdda_codec>; - VDDIO-supply = <&vdda_codec>; - VDDD-supply = <&vddd_codec>; - status = "okay"; - }; -}; - -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&haikou_pin_hog>; - - hog { - haikou_pin_hog: haikou-pin-hog { - rockchip,pins = - /* LID_BTN */ - <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - /* BATLOW# */ - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, - /* SLP_BTN# */ - <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ - <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - sd_card_led_pin: sd-card-led-pin { - rockchip,pins = - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <40000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - vmmc-supply = <&vcc3v3_baseboard>; - status = "okay"; -}; - -&spi5 { - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - extcon = <&extcon_usb3>; - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi deleted file mode 100644 index aa3e21bd6c8f44ff5f9b249dd43b56316dbc2a60..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-puma.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - aliases { - mmc0 = &sdhci; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&module_led_pin>; - - module_led: led-0 { - label = "module_led"; - gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - extcon_usb3: extcon-usb3 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_id>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc1v2_phy: vcc1v2-phy { - compatible = "regulator-fixed"; - regulator-name = "vcc1v2_phy"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc5v0_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; - drive-impedance-ohm = <33>; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc1v2_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x10>; - rx_delay = <0x10>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc1v8_pmu>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_ldo1: LDO_REG1 { - regulator-name = "vcc_ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_ldo5: LDO_REG5 { - regulator-name = "vcc_ldo5"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ldo6: LDO_REG6 { - regulator-name = "vcc_ldo6"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc0v9_hdmi: LDO_REG7 { - regulator-name = "vcc0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_efuse: LDO_REG8 { - regulator-name = "vcc_efuse"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_gpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&i2c7 { - status = "okay"; - clock-frequency = <400000>; - - fan: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c8 { - status = "okay"; - clock-frequency = <400000>; - - vdd_cpu_b: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - vin-supply = <&vcc5v0_sys>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1230000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_2ch_bus>; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -/* - * As Q7 does not specify neither a global nor a RX clock for I2S these - * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. - * Therefore we have to redefine the i2s0_2ch_bus definition to prevent - * conflicts. - */ -&i2s0_2ch_bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcc_1v8>; - audio-supply = <&vcc_1v8>; - sdmmc-supply = <&vcc_sd>; - gpio1830-supply = <&vcc_1v8>; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; -}; - -&pwm2 { - status = "okay"; -}; - -&pinctrl { - i2c8 { - i2c8_xfer_a: i2c8-xfer { - rockchip,pins = - <1 RK_PC4 1 &pcfg_pull_up>, - <1 RK_PC5 1 &pcfg_pull_up>; - }; - }; - - leds { - module_led_pin: module-led-pin { - rockchip,pins = - <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = - <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb3 { - usb3_id: usb3-id { - rockchip,pins = - <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdhci { - /* - * Signal integrity isn't great at 200MHz but 100MHz has proven stable - * enough. - */ - max-frequency = <100000000>; - - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - vqmmc-supply = <&vcc_sd>; -}; - -&spi1 { - status = "okay"; - - norflash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts b/arch/arm/dts/rk3399-roc-pc-mezzanine.dts deleted file mode 100644 index 9447c8724b65a98bafe9ea319814dbb7c077991c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-roc-pc-mezzanine.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - * Copyright (c) 2019 Markus Reichl - */ - -/dts-v1/; -#include "rk3399-roc-pc.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Mezzanine Board"; - compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; - - aliases { - mmc2 = &sdio0; - }; - - /* MP8009 PoE PD */ - poe_12v: poe-12v { - compatible = "regulator-fixed"; - regulator-name = "poe_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_ngff: vcc3v3-ngff { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ngff"; - enable-active-high; - gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_ngff_en>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&sys_12v>; - }; - - vcc3v3_pcie: vcc3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - enable-active-high; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&sys_12v>; - }; -}; - -&sys_12v { - vin-supply = <&poe_12v>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie3v3-supply = <&vcc3v3_pcie>; - vpcie1v8-supply = <&vcc1v8_pmu>; - vpcie0v9-supply = <&vcca_0v9>; - status = "okay"; -}; - -&pinctrl { - ngff { - vcc3v3_ngff_en: vcc3v3-ngff-en { - rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - vcc3v3_pcie_en: vcc3v3-pcie-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_perst: pcie-perst { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_ngff>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index c8f4418a7389ac4d46153309bac56043234aded1..aecf7dbe383c90fb40c1cf4bda2c3f0870c748d9 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc; - }; - vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -36,25 +32,38 @@ vin-supply = <&vcc_vbus_typec0>; }; +&gpio4 { + bootph-pre-ram; +}; + &spi1 { - spi_flash: flash@0 { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; }; }; -&vdd_log { - regulator-min-microvolt = <430000>; - regulator-init-microvolt = <950000>; +&vcc3v0_sd { + bootph-pre-ram; +}; + +&vcc3v0_sd_en { + bootph-pre-ram; }; &vcc5v0_host { regulator-always-on; }; -&vcc_sys { +&vcc_sdio { regulator-always-on; }; -&vcc_sdio { +&vcc_sys { regulator-always-on; }; + +&vdd_log { + regulator-min-microvolt = <430000>; + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts deleted file mode 100644 index cd419542530973450975ecfdb64eec2ddce229ae..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-roc-pc.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include "rk3399-roc-pc.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Board"; - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; -}; diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi deleted file mode 100644 index d1aaf8e83391aef16070df29c9d96c4cb38a0bde..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ /dev/null @@ -1,843 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd - */ - -/dts-v1/; -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Firefly ROC-RK3399-PC Board"; - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1500000>; - poll-interval = <100>; - - recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <18000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_l>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>; - - work_led: led-0 { - label = "green:work"; - gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - diy_led: led-1 { - label = "red:diy"; - gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc2"; - }; - - yellow_led: led-2 { - label = "yellow:yellow-led"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc1"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc_vbus_typec0: vcc-vbus-typec0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_vbus_typec0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - sys_12v: sys-12v { - compatible = "regulator-fixed"; - regulator-name = "sys_12v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&dc_12v>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v0_sd_en>; - regulator-name = "vcc3v0_sd"; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&sys_12v>; - }; - - vcca_0v9: vcca-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcca_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en &hub_rst>; - regulator-name = "vcc5v0_host"; - vin-supply = <&vcc_sys>; - }; - - vcc_vbus_typec1: vcc-vbus-typec1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_vbus_typec1_en>; - regulator-name = "vcc_vbus_typec1"; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sys: vcc-sys { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_sys_en>; - regulator-name = "vcc_sys"; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&sys_12v>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <450000>; - regulator-max-microvolt = <1400000>; - pwm-supply = <&vcc3v3_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - vcc10-supply = <&vcc3v3_sys>; - vcc11-supply = <&vcc3v3_sys>; - vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_3v0>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_codec: LDO_REG1 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_pmu: LDO_REG3 { - regulator-name = "vcc1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb1: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb1_int>; - vbus-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; -}; - -&i2c7 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - mp8859: regulator@66 { - compatible = "mps,mp8859"; - reg = <0x66>; - dc_12v: mp8859_dcdc { - regulator-name = "dc_12v"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_vbus_typec0>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <12000000>; - }; - }; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - buttons { - pwr_key_l: pwr-key-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd-panel { - lcd_panel_reset: lcd-panel-reset { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - diy_led_pin: diy-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led_pin: work-led-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - yellow_led_pin: yellow-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - vcc3v0_sd_en: vcc3v0-sd-en { - rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc_sys_en: vcc-sys-en { - rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hub_rst: hub-rst { - rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb-typec { - vcc_vbus_typec1_en: vcc-vbus-typec1-en { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fusb30x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - fusb1_int: fusb1-int { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vcc_vbus_typec0>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_vbus_typec1>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 5c1c451b8f85f720292dba40947d4b1b19945000..5ec15a845c1a898efa0789a5294ff073ed1c0f52 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -3,3 +3,25 @@ * Copyright (c) 2023 Radxa Limited */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +&pcfg_pull_none_18ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts deleted file mode 100644 index 8bfd5f88d1ef61d9ce45d617d4fc5d199d4b84cc..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ /dev/null @@ -1,708 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2022 Amarula Solutions(India) - */ - -/dts-v1/; -#include -#include "rk3399.dtsi" -#include "rk3399-t-opp.dtsi" - -/ { - model = "Radxa ROCK 4C+"; - compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led1 &user_led2>; - - /* USER_LED1 */ - led-0 { - function = LED_FUNCTION_POWER; - color = ; - gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - /* USER_LED2 */ - led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc_3v3: vcc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_phy1: vcc3v3-phy1-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_phy1"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - - vcc5v0_host1: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_host0_s0>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec0_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_log: vdd-log-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_phy1>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x2a>; - rx_delay = <0x21>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vcc_0v9_s0>; - avdd-1v8-supply = <&vcc_1v8_s0>; - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - i2c-scl-falling-time-ns = <30>; - i2c-scl-rising-time-ns = <180>; - clock-frequency = <400000>; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5_s3>; - vcc6-supply = <&vcc_buck5_s3>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_center"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_cpu_l"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc3v3_sys"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_buck5_s3: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_buck5_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_0v9_s3: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vcc_0v9_s3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_0v9_s0: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vcc_0v9_s0"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_1v8_s0: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_mipi: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc_mipi"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5_s0: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc_1v5_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0_s0: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc_3v0_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sdio_s0: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_sdio_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_cam: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_cam"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v0_host0_s0: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_host0_s0"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - lcd_3v3: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "lcd_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-compatible = "fan53555-reg"; - pinctrl-0 = <&vsel1_gpio>; - vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-compatible = "fan53555-reg"; - pinctrl-0 = <&vsel2_gpio>; - vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcc_1v8_s0>; - bt656-supply = <&vcc_3v0_s0>; - gpio1830-supply = <&vcc_3v0_s0>; - sdmmc-supply = <&vcc_sdio_s0>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - user_led1: user-led1 { - rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led2: user-led2 { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_gpio: vsel1-gpio { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_gpio: vsel2-gpio { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, - <4 9 1 &pcfg_pull_up_8ma>, - <4 10 1 &pcfg_pull_up_8ma>, - <4 11 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; - }; - }; - - usb-typec { - vcc5v0_typec0_en: vcc5v0-typec-en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wifi { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0_s0>; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s3>; -}; - -&sdhci { - max-frequency = <150000000>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <800>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&vcc_sdio_s0>; - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host1>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host1>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8_s3>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi index 85ee5770add0ea5c0a65c740bc52f325f64cda3b..f9ad518d3adbd96680042215036a8386b8ec7057 100644 --- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -4,3 +4,15 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-4se.dts b/arch/arm/dts/rk3399-rock-4se.dts deleted file mode 100644 index 7cfc198bbae74ecfd07baef1bc7258b60fd5b384..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock-4se.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/dts-v1/; -#include "rk3399-rock-pi-4.dtsi" -#include "rk3399-t-opp.dtsi" - -/ { - model = "Radxa ROCK 4SE"; - compatible = "radxa,rock-4se", "rockchip,rk3399"; - - aliases { - mmc2 = &sdio0; - }; -}; - -&pinctrl { - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdio0 { - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&uart0 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&vcc5v0_host { - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; -}; diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 60122f3bcd6cd87ef7cf1f75a0dbf6a936abc1b8..b3bfc77f7569af25cdfaa6c69b33985008e68b18 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi deleted file mode 100644 index b1b7f4ffb1d4a09152f9d69e33d488c81a64bbb3..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ /dev/null @@ -1,790 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/dts-v1/; -#include -#include -#include -#include "rk3399.dtsi" - -/ { - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led2>; - - /* USER_LED2 */ - led-0 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - sound: sound { - compatible = "audio-graph-card"; - label = "Analog"; - dais = <&i2s0_p0>; - }; - - sound-dit { - compatible = "audio-graph-card"; - label = "SPDIF"; - dais = <&spdif_p0>; - }; - - spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; - }; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vbus_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc12v_dcin: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_lan: vcc3v3-lan-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lan"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc5v0_sys>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc3v3_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vcca0v9_hdmi>; - avdd-1v8-supply = <&vcca1v8_hdmi>; - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_codec: LDO_REG1 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_cam: SWITCH_REG1 { - regulator-name = "vcc_cam"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_mipi: SWITCH_REG2 { - regulator-name = "vcc_mipi"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; - - es8316: codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_p0_0>; - }; - }; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; -}; - -&i2s0 { - pinctrl-0 = <&i2s0_2ch_bus>; - rockchip,capture-channels = <2>; - rockchip,playback-channels = <2>; - status = "okay"; - - i2s0_p0: port { - i2s0_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca1v8_codec>; - bt656-supply = <&vcc_3v0>; - gpio1830-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqnb_cpm>; - pinctrl-names = "default"; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcc_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - es8316 { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - hp_int: hp-int { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - user_led2: user-led2 { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio0 { - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, - <2 RK_PC5 1 &pcfg_pull_up_20ma>, - <2 RK_PC6 1 &pcfg_pull_up_20ma>, - <2 RK_PC7 1 &pcfg_pull_up_20ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0-typec-en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - status = "okay"; - - vref-supply = <&vcc_1v8>; -}; - -&sdhci { - max-frequency = <150000000>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&sdio0 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; - status = "okay"; -}; - -&spdif { - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - status = "okay"; - - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts deleted file mode 100644 index d5df8939a65819b2fe764c8fb004fb1757110df9..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock-pi-4a.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Akash Gajjar - * Copyright (c) 2019 Pragnesh Patel - */ - -/dts-v1/; -#include "rk3399-rock-pi-4.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Radxa ROCK Pi 4A"; - compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi index 85ee5770add0ea5c0a65c740bc52f325f64cda3b..38385621deb106cc5f9085714a0292e97cb2e612 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi @@ -4,3 +4,10 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +&spi1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts deleted file mode 100644 index d32efab74e94345830265ad6ee8985b8e8cdecdd..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3399-rock-pi-4.dtsi" -#include "rk3399-opp.dtsi" - -/ { - model = "Radxa ROCK Pi 4C"; - compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; - - aliases { - mmc2 = &sdio0; - }; -}; - -&es8316 { - pinctrl-0 = <&hp_detect &hp_int>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = ; -}; - -&sdio0 { - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sound { - hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -}; - -&uart0 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - max-speed = <1500000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&vcc5v0_host { - gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; -}; - -&vcc5v0_host_en { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -}; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index c190089e26431b6a0535fba927a56f12289973f2..ef08d8987cee8fce093592b5de8342a96174cd14 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr3-2GB-1600.dtsi" / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; - vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; @@ -22,5 +18,14 @@ regulator-init-microvolt = <950000>; vin-supply = <&vcc5v0_sys>; }; +}; + +&pcfg_pull_none_18ma { + bootph-pre-ram; + bootph-some-ram; +}; +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; }; diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts deleted file mode 100644 index 1a23e8f3cdf65d9dbbcc1beb2249b937c59101e0..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock960.dts +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Linaro Ltd. - */ - -/dts-v1/; -#include "rk3399-rock960.dtsi" - -/ { - model = "96boards Rock960"; - compatible = "vamrs,rock960", "rockchip,rk3399"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, - <&user_led3_pin>, <&user_led4_pin>, - <&wlan_led_pin>, <&bt_led_pin>; - - user_led1: led-1 { - label = "green:user1"; - gpios = <&gpio4 RK_PC2 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2: led-2 { - label = "green:user2"; - gpios = <&gpio4 RK_PC6 0>; - linux,default-trigger = "mmc0"; - }; - - user_led3: led-3 { - label = "green:user3"; - gpios = <&gpio4 RK_PD0 0>; - linux,default-trigger = "mmc1"; - }; - - user_led4: led-4 { - label = "green:user4"; - gpios = <&gpio4 RK_PD4 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led: led-5 { - label = "yellow:wlan"; - gpios = <&gpio4 RK_PD5 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led: led-6 { - label = "blue:bt"; - gpios = <&gpio4 RK_PD6 0>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - -}; - -&cpu_alert0 { - temperature = <65000>; -}; - -&cpu_thermal { - sustainable-power = <1550>; - - cooling-maps { - map0 { - trip = <&cpu_alert1>; - }; - }; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl { - leds { - user_led1_pin: user-led1-pin { - rockchip,pins = - <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led2_pin: user-led2-pin { - rockchip,pins = - <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led3_pin: user-led3-pin { - rockchip,pins = - <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led4_pin: user-led4-pin { - rockchip,pins = - <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_led_pin: wlan-led-pin { - rockchip,pins = - <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_led_pin: bt-led-pin { - rockchip,pins = - <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_drv: pcie-drv { - rockchip,pins = - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - host_vbus_drv: host-vbus-drv { - rockchip,pins = - <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spi0 { - /* On Low speed expansion (LS-SPI0) */ - status = "okay"; -}; - -&spi4 { - /* On High speed expansion (HS-SPI1) */ - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&vcc3v3_pcie { - gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; -}; - -&vcc5v0_host { - gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi deleted file mode 100644 index 25dc61c26a9431b7da05180533bba210eff5e059..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ /dev/null @@ -1,670 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Collabora Ltd. - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Linaro Ltd. - */ - -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc1v8_s0: vcc1v8-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_drv>; - regulator-boot-on; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_0v9: vcc-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - status = "okay"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio1>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_hdmi: LDO_REG2 { - regulator-name = "vcca1v8_hdmi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sd: LDO_REG4 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v0_sd: LDO_REG5 { - regulator-name = "vcc3v0_sd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca0v9_hdmi: LDO_REG7 { - regulator-name = "vcca0v9_hdmi"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ - audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ - sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ - gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - vpcie0v9-supply = <&vcc_0v9>; - vpcie1v8-supply = <&vcca_1v8>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up_8ma>, - <4 RK_PB1 1 &pcfg_pull_up_8ma>, - <4 RK_PB2 1 &pcfg_pull_up_8ma>, - <4 RK_PB3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none_18ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_up_8ma>; - }; - }; - - sdio0 { - sdio0_bus4: sdio0-bus4 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up_20ma>, - <2 RK_PC5 1 &pcfg_pull_up_20ma>, - <2 RK_PC6 1 &pcfg_pull_up_20ma>, - <2 RK_PC7 1 &pcfg_pull_up_20ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = - <2 RK_PD0 1 &pcfg_pull_up_20ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = - <2 RK_PD1 1 &pcfg_pull_none_20ma>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = - <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - clock-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - clock-frequency = <100000000>; - max-frequency = <100000000>; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vcc_sd>; - card-detect-delay = <800>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - rockchip,hw-tshut-temp = <110000>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 089732524a76364c61e615814d2e39426468aee5..43b67991fe5aca1e5e7422e44b2a27ab18003a5a 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; smbios { @@ -29,8 +26,10 @@ }; }; }; +}; - +&gpio0 { + bootph-pre-ram; }; &sdhci { @@ -38,12 +37,21 @@ mmc-ddr-1_8v; }; +&sdmmc0_pwr_h { + bootph-pre-ram; +}; + &spi1 { - spi_flash: flash@0 { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; }; }; +&vcc3v0_sd { + bootph-pre-ram; +}; + &vdd_center { regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>; diff --git a/arch/arm/dts/rk3399-rockpro64.dts b/arch/arm/dts/rk3399-rockpro64.dts deleted file mode 100644 index 4b42717800f777278802941f743c681c5c4c8465..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rockpro64.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - * Copyright (c) 2019 Katsuhiro Suzuki - */ - -/dts-v1/; -#include "rk3399-rockpro64.dtsi" - -/ { - model = "Pine64 RockPro64 v2.1"; - compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; -}; - -&i2c1 { - es8316: codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru SCLK_I2S_8CH_OUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi deleted file mode 100644 index 6bff8db7d33e8a76aef6d3c3f5b92e09f0e776da..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-rockpro64.dtsi +++ /dev/null @@ -1,870 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - * Copyright (c) 2018 Akash Gajjar - */ - -#include -#include -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" - -/ { - aliases { - mmc0 = &sdio0; - mmc1 = &sdmmc; - mmc2 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - wakeup-source; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&ir_int>; - pinctrl-names = "default"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; - - work_led: led-0 { - label = "work"; - default-state = "on"; - gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - }; - - diy_led: led-1 { - label = "diy"; - default-state = "off"; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - fan-supply = <&vcc12v_dcin>; - pwms = <&pwm1 0 50000 0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk808 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "audio-graph-card"; - label = "Analog"; - dais = <&i2s1_p0>; - }; - - sound-dit { - compatible = "audio-graph-card"; - label = "SPDIF"; - dais = <&spdif_p0>; - }; - - spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* switched by pmic_sleep */ - vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8>; - }; - - /* micro SD card power */ - vcc3v0_sd: vcc3v0-sd { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_pwr_h>; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr_en>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_typec: vcc5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_typec_en>; - regulator-name = "vcc5v0_typec"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_b>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_b>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; - status = "okay"; -}; - -&hdmi_sound { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-rising-time-ns = <168>; - i2c-scl-falling-time-ns = <4>; - status = "okay"; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio3>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc5v0_sys>; - vcc12-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca_1v8>; - - regulators { - vdd_center: DCDC_REG1 { - regulator-name = "vdd_center"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG4 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc1v8_dvp: LDO_REG1 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v0_touch: LDO_REG2 { - regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8: LDO_REG3 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_sdio: LDO_REG4 { - regulator-name = "vcc_sdio"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcca3v0_codec: LDO_REG5 { - regulator-name = "vcca3v0_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - }; - }; - - vcca1v8_codec: LDO_REG7 { - regulator-name = "vcca1v8_codec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v0: LDO_REG8 { - regulator-name = "vcc_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - vcc3v3_s3: vcc_lan: SWITCH_REG1 { - regulator-name = "vcc3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_s0: SWITCH_REG2 { - regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu_b: regulator@40 { - compatible = "silergy,syr827"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel1_pin>; - regulator-name = "vdd_cpu_b"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: regulator@41 { - compatible = "silergy,syr828"; - reg = <0x41>; - fcs,suspend-voltage-selector = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&vsel2_pin>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&i2c4 { - i2c-scl-rising-time-ns = <600>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - - fusb0: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb0_int>; - vbus-supply = <&vcc5v0_typec>; - status = "okay"; - }; -}; - -&i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - status = "okay"; -}; - -&i2s1 { - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - status = "okay"; - - i2s1_p0: port { - i2s1_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&i2s2 { - status = "okay"; -}; - -&io_domains { - status = "okay"; - - bt656-supply = <&vcc1v8_dvp>; - audio-supply = <&vcc_3v0>; - sdmmc-supply = <&vcc_sdio>; - gpio1830-supply = <&vcc_3v0>; -}; - -&pcie0 { - ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_perst>; - vpcie12v-supply = <&vcc12v_dcin>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pmu_io_domains { - pmu1830-supply = <&vcc_3v0>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - fusb302x { - fusb0_int: fusb0-int { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - work_led_pin: work-led-pin { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_pin: diy-led-pin { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_perst: pcie-perst { - rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vsel1_pin: vsel1-pin { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - vsel2_pin: vsel2-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdcard { - sdmmc0_pwr_h: sdmmc0-pwr-h { - rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - vcc5v0_typec_en: vcc5v0_typec_en { - rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca1v8_s3>; - status = "okay"; -}; - -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - vmmc-supply = <&vcc3v0_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&spdif { - pinctrl-0 = <&spdif_bus_1>; - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; -}; - -&spi1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&tcphy0 { - status = "okay"; -}; - -&tcphy1 { - status = "okay"; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk808 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; - dr_mode = "host"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3399-t-opp.dtsi b/arch/arm/dts/rk3399-t-opp.dtsi deleted file mode 100644 index 1ababadda9df638fe65b490c1ce0740513746db7..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399-t-opp.dtsi +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2022 Radxa Limited - */ - -/ { - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <875000 875000 1250000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <875000 875000 1250000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1250000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <975000 975000 1250000>; - }; - }; - - cluster1_opp: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <875000 875000 1250000>; - clock-latency-ns = <40000>; - }; - opp01 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <875000 875000 1250000>; - }; - opp02 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <875000 875000 1250000>; - }; - opp03 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <925000 925000 1250000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000 1000000 1250000>; - }; - opp05 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1075000 1075000 1250000>; - }; - opp06 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1150000 1150000 1250000>; - }; - }; - - gpu_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp00 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <875000 875000 1150000>; - }; - opp01 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <875000 875000 1150000>; - }; - opp02 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000 875000 1150000>; - }; - opp03 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000 975000 1150000>; - }; - }; -}; - -&cpu_l0 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l1 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l2 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_l3 { - operating-points-v2 = <&cluster0_opp>; -}; - -&cpu_b0 { - operating-points-v2 = <&cluster1_opp>; -}; - -&cpu_b1 { - operating-points-v2 = <&cluster1_opp>; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table>; -}; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 87b173e59579c48edf38c38c1b771edcc52841b0..b6b43271172e96259fcd48f60f1f896ccb205e93 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /* * Copyright (C) 2019 Jagan Teki */ -#define USB_CLASS_HUB 9 - #include "rockchip-u-boot.dtsi" / { @@ -14,50 +12,21 @@ spi1 = &spi1; }; - cic: syscon@ff620000 { - bootph-all; - compatible = "rockchip,rk3399-cic", "syscon"; - reg = <0x0 0xff620000 0x0 0x100>; - }; - - dfi: dfi@ff630000 { - bootph-all; - reg = <0x00 0xff630000 0x00 0x4000>; - compatible = "rockchip,rk3399-dfi"; - rockchip,pmu = <&pmugrf>; - clocks = <&cru PCLK_DDR_MON>; - clock-names = "pclk_ddr_mon"; - }; - - rng: rng@ff8b8000 { - compatible = "rockchip,rk3399-crypto"; - reg = <0x0 0xff8b8000 0x0 0x1000>; - status = "okay"; - }; - - dmc: dmc { - bootph-all; - compatible = "rockchip,rk3399-dmc"; - devfreq-events = <&dfi>; - interrupts = ; - clocks = <&cru SCLK_DDRCLK>; - clock-names = "dmc_clk"; - reg = <0x0 0xffa80000 0x0 0x0800 - 0x0 0xffa80800 0x0 0x1800 - 0x0 0xffa82000 0x0 0x2000 - 0x0 0xffa84000 0x0 0x1000 - 0x0 0xffa88000 0x0 0x0800 - 0x0 0xffa88800 0x0 0x1800 - 0x0 0xffa8a000 0x0 0x2000 - 0x0 0xffa8c000 0x0 0x1000>; + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; pmusgrf: syscon@ff330000 { - bootph-all; compatible = "rockchip,rk3399-pmusgrf", "syscon"; reg = <0x0 0xff330000 0x0 0xe3d4>; + bootph-all; }; + cic: syscon@ff620000 { + compatible = "rockchip,rk3399-cic", "syscon"; + reg = <0x0 0xff620000 0x0 0x100>; + bootph-all; + }; }; #if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) @@ -89,23 +58,41 @@ bootph-all; }; -&emmc_phy { +&dfi { + bootph-all; +}; + +&dmc { + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; bootph-all; + status = "okay"; +}; + +&emmc_phy { + bootph-pre-ram; + bootph-some-ram; }; &grf { bootph-all; }; -&pinctrl { +&pcfg_pull_none { bootph-all; }; -&pmu { +&pcfg_pull_up { bootph-all; }; -&pmugrf { +&pinctrl { bootph-all; }; @@ -117,35 +104,85 @@ bootph-all; }; +&pmugrf { + bootph-all; +}; + &sdhci { + bootph-pre-ram; + bootph-some-ram; max-frequency = <200000000>; - bootph-all; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; }; &sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; }; -&spi1 { - bootph-all; +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; }; -&uart0 { - bootph-all; +&sdmmc_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi1_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi1_cs0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi1_rx { + bootph-pre-ram; + bootph-some-ram; +}; + +&spi1_tx { + bootph-pre-ram; + bootph-some-ram; }; &uart2 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart2c_xfer { + bootph-pre-sram; + bootph-pre-ram; }; &vopb { - bootph-all; + bootph-some-ram; }; &vopl { + bootph-some-ram; +}; + +&xin24m { bootph-all; }; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi deleted file mode 100644 index 3871c7fd83b00549844e2938f1e85cdbf6934a34..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399.dtsi +++ /dev/null @@ -1,2714 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3399"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_l3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&cru ARMCLKL>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <100>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_b0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&cru ARMCLKB>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <436>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - cpu_b1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&cru ARMCLKB>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <436>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - pmu_a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - pcie0: pcie@f8000000 { - compatible = "rockchip,rk3399-pcie"; - reg = <0x0 0xf8000000 0x0 0x2000000>, - <0x0 0xfd000000 0x0 0x1000000>; - reg-names = "axi-base", "apb-base"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - aspm-no-l0s; - bus-range = <0x0 0x1f>; - clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, - <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; - clock-names = "aclk", "aclk-perf", - "hclk", "pm"; - interrupts = , - , - ; - interrupt-names = "sys", "legacy", "client"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - max-link-speed = <1>; - msi-map = <0x0 &its 0x0 0x1000>; - phys = <&pcie_phy 0>, <&pcie_phy 1>, - <&pcie_phy 2>, <&pcie_phy 3>; - phy-names = "pcie-phy-0", "pcie-phy-1", - "pcie-phy-2", "pcie-phy-3"; - ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, - <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; - resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, - <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, - <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, - <&cru SRST_A_PCIE>; - reset-names = "core", "mgmt", "mgmt-sticky", "pipe", - "pm", "pclk", "aclk"; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - gmac: ethernet@fe300000 { - compatible = "rockchip,rk3399-gmac"; - reg = <0x0 0xfe300000 0x0 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, - <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - power-domains = <&power RK3399_PD_GMAC>; - resets = <&cru SRST_A_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,txpbl = <0x4>; - status = "disabled"; - }; - - sdio0: mmc@fe310000 { - compatible = "rockchip,rk3399-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc: mmc@fe320000 { - compatible = "rockchip,rk3399-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - assigned-clocks = <&cru HCLK_SD>; - assigned-clock-rates = <200000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - power-domains = <&power RK3399_PD_SD>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - sdhci: mmc@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - arasan,soc-ctl-syscon = <&grf>; - assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; - clock-output-names = "emmc_cardclock"; - #clock-cells = <0>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - power-domains = <&power RK3399_PD_EMMC>; - disable-cqe-dcmd; - status = "disabled"; - }; - - usb_host0_ehci: usb@fe380000 { - compatible = "generic-ehci"; - reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, - <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fe3a0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, - <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fe3c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, - <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fe3e0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, - <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usbdrd3_0: usb@fe800000 { - compatible = "rockchip,rk3399-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; - resets = <&cru SRST_A_USB3_OTG0>; - reset-names = "usb3-otg"; - status = "disabled"; - - usbdrd_dwc3_0: usb@fe800000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe800000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, - <&cru SCLK_USB3OTG0_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&tcphy0_usb3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; - }; - - usbdrd3_1: usb@fe900000 { - compatible = "rockchip,rk3399-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; - resets = <&cru SRST_A_USB3_OTG1>; - reset-names = "usb3-otg"; - status = "disabled"; - - usbdrd_dwc3_1: usb@fe900000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfe900000 0x0 0x100000>; - interrupts = ; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, - <&cru SCLK_USB3OTG1_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&tcphy1_usb3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; - status = "disabled"; - }; - }; - - cdn_dp: dp@fec00000 { - compatible = "rockchip,rk3399-cdn-dp"; - reg = <0x0 0xfec00000 0x0 0x100000>; - interrupts = ; - assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; - assigned-clock-rates = <100000000>, <200000000>; - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; - clock-names = "core-clk", "pclk", "spdif", "grf"; - phys = <&tcphy0_dp>, <&tcphy1_dp>; - power-domains = <&power RK3399_PD_HDCP>; - resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, - <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; - reset-names = "spdif", "dptx", "apb", "core"; - rockchip,grf = <&grf>; - #sound-dai-cells = <1>; - status = "disabled"; - - ports { - dp_in: port { - #address-cells = <1>; - #size-cells = <0>; - - dp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dp>; - }; - - dp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dp>; - }; - }; - }; - }; - - gic: interrupt-controller@fee00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - - reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ - <0x0 0xfef00000 0 0xc0000>, /* GICR */ - <0x0 0xfff00000 0 0x10000>, /* GICC */ - <0x0 0xfff10000 0 0x10000>, /* GICH */ - <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = ; - its: interrupt-controller@fee20000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xfee20000 0x0 0x20000>; - }; - - ppi-partitions { - ppi_cluster0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_cluster1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1>; - }; - }; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,rk3399-saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c1: i2c@ff110000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff110000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C1>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff120000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff120000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C2>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff130000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff130000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C3>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@ff140000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C5>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@ff150000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C6>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@ff160000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - assigned-clocks = <&cru SCLK_I2C7>; - assigned-clock-rates = <200000000>; - clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff1a0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1a0000 0x0 0x100>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2c_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - spi0: spi@ff1c0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1c0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 10>, <&dmac_peri 11>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff1d0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 12>, <&dmac_peri 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff1e0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1e0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 14>, <&dmac_peri 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@ff1f0000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1f0000 0x0 0x1000>; - clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_peri 18>, <&dmac_peri 19>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@ff200000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff200000 0x0 0x1000>; - clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - dmas = <&dmac_bus 8>, <&dmac_bus 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff260000 { - compatible = "rockchip,rk3399-tsadc"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <750000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - qos_emmc: qos@ffa58000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa58000 0x0 0x20>; - }; - - qos_gmac: qos@ffa5c000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa5c000 0x0 0x20>; - }; - - qos_pcie: qos@ffa60080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa60080 0x0 0x20>; - }; - - qos_usb_host0: qos@ffa60100 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa60100 0x0 0x20>; - }; - - qos_usb_host1: qos@ffa60180 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa60180 0x0 0x20>; - }; - - qos_usb_otg0: qos@ffa70000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa70000 0x0 0x20>; - }; - - qos_usb_otg1: qos@ffa70080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa70080 0x0 0x20>; - }; - - qos_sd: qos@ffa74000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa74000 0x0 0x20>; - }; - - qos_sdioaudio: qos@ffa76000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa76000 0x0 0x20>; - }; - - qos_hdcp: qos@ffa90000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa90000 0x0 0x20>; - }; - - qos_iep: qos@ffa98000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffa98000 0x0 0x20>; - }; - - qos_isp0_m0: qos@ffaa0000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_isp0_m1: qos@ffaa0080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_isp1_m0: qos@ffaa8000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffaa8000 0x0 0x20>; - }; - - qos_isp1_m1: qos@ffaa8080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffaa8080 0x0 0x20>; - }; - - qos_rga_r: qos@ffab0000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffab0000 0x0 0x20>; - }; - - qos_rga_w: qos@ffab0080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffab0080 0x0 0x20>; - }; - - qos_video_m0: qos@ffab8000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffab8000 0x0 0x20>; - }; - - qos_video_m1_r: qos@ffac0000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffac0000 0x0 0x20>; - }; - - qos_video_m1_w: qos@ffac0080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffac0080 0x0 0x20>; - }; - - qos_vop_big_r: qos@ffac8000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffac8000 0x0 0x20>; - }; - - qos_vop_big_w: qos@ffac8080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffac8080 0x0 0x20>; - }; - - qos_vop_little: qos@ffad0000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_perihp: qos@ffad8080 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffad8080 0x0 0x20>; - }; - - qos_gpu: qos@ffae0000 { - compatible = "rockchip,rk3399-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - pmu: power-management@ff310000 { - compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff310000 0x0 0x1000>; - - /* - * Note: RK3399 supports 6 voltage domains including VD_CORE_L, - * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. - * Some of the power domains are grouped together for every - * voltage domain. - * The detail contents as below. - */ - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_CENTER */ - power-domain@RK3399_PD_IEP { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru HCLK_IEP>; - pm_qos = <&qos_iep>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_RGA { - reg = ; - clocks = <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_VCODEC { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video_m0>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_VDU { - reg = ; - clocks = <&cru ACLK_VDU>, - <&cru HCLK_VDU>; - pm_qos = <&qos_video_m1_r>, - <&qos_video_m1_w>; - #power-domain-cells = <0>; - }; - - /* These power domains are grouped by VD_GPU */ - power-domain@RK3399_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3399_PD_EDP { - reg = ; - clocks = <&cru PCLK_EDP_CTRL>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_EMMC { - reg = ; - clocks = <&cru ACLK_EMMC>; - pm_qos = <&qos_emmc>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_GMAC { - reg = ; - clocks = <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - pm_qos = <&qos_gmac>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_SD { - reg = ; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sd>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_SDIOAUDIO { - reg = ; - clocks = <&cru HCLK_SDIO>; - pm_qos = <&qos_sdioaudio>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_TCPD0 { - reg = ; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_TCPD1 { - reg = ; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_USB3 { - reg = ; - clocks = <&cru ACLK_USB3>; - pm_qos = <&qos_usb_otg0>, - <&qos_usb_otg1>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_VIO { - reg = ; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3399_PD_HDCP { - reg = ; - clocks = <&cru ACLK_HDCP>, - <&cru HCLK_HDCP>, - <&cru PCLK_HDCP>; - pm_qos = <&qos_hdcp>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_ISP0 { - reg = ; - clocks = <&cru ACLK_ISP0>, - <&cru HCLK_ISP0>; - pm_qos = <&qos_isp0_m0>, - <&qos_isp0_m1>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_ISP1 { - reg = ; - clocks = <&cru ACLK_ISP1>, - <&cru HCLK_ISP1>; - pm_qos = <&qos_isp1_m0>, - <&qos_isp1_m1>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_VO { - reg = ; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3399_PD_VOPB { - reg = ; - clocks = <&cru ACLK_VOP0>, - <&cru HCLK_VOP0>; - pm_qos = <&qos_vop_big_r>, - <&qos_vop_big_w>; - #power-domain-cells = <0>; - }; - power-domain@RK3399_PD_VOPL { - reg = ; - clocks = <&cru ACLK_VOP1>, - <&cru HCLK_VOP1>; - pm_qos = <&qos_vop_little>; - #power-domain-cells = <0>; - }; - }; - }; - }; - }; - - pmugrf: syscon@ff320000 { - compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff320000 0x0 0x1000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3399-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - spi3: spi@ff350000 { - compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff350000 0x0 0x1000>; - clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@ff370000 { - compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff370000 0x0 0x100>; - clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - i2c0: i2c@ff3c0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3c0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C0_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@ff3d0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3d0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C4_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@ff3e0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3e0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C8_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@ff420000 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - status = "disabled"; - }; - - pwm1: pwm@ff420010 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - status = "disabled"; - }; - - pwm2: pwm@ff420020 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - status = "disabled"; - }; - - pwm3: pwm@ff420030 { - compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; - reg = <0x0 0xff420030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3a_pin>; - clocks = <&pmucru PCLK_RKPWM_PMU>; - status = "disabled"; - }; - - vpu: video-codec@ff650000 { - compatible = "rockchip,rk3399-vpu"; - reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3399_PD_VCODEC>; - }; - - vpu_mmu: iommu@ff650800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff650800 0x0 0x40>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_VCODEC>; - }; - - vdec: video-codec@ff660000 { - compatible = "rockchip,rk3399-vdec"; - reg = <0x0 0xff660000 0x0 0x400>; - interrupts = ; - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, - <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; - }; - - vdec_mmu: iommu@ff660480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; - interrupts = ; - interrupt-names = "vdec_mmu"; - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VDU>; - #iommu-cells = <0>; - }; - - iep_mmu: iommu@ff670800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@ff680000 { - compatible = "rockchip,rk3399-rga"; - reg = <0x0 0xff680000 0x0 0x10000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; - clock-names = "aclk", "hclk", "sclk"; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; - reset-names = "core", "axi", "ahb"; - power-domains = <&power RK3399_PD_RGA>; - }; - - efuse0: efuse@ff690000 { - compatible = "rockchip,rk3399-efuse"; - reg = <0x0 0xff690000 0x0 0x80>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE1024NS>; - clock-names = "pclk_efuse"; - - /* Data cells */ - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpub_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - gpu_leakage: gpu-leakage@18 { - reg = <0x18 0x1>; - }; - center_leakage: center-leakage@19 { - reg = <0x19 0x1>; - }; - cpul_leakage: cpu-leakage@1a { - reg = <0x1a 0x1>; - }; - logic_leakage: logic-leakage@1b { - reg = <0x1b 0x1>; - }; - wafer_info: wafer-info@1c { - reg = <0x1c 0x1>; - }; - }; - - dmac_bus: dma-controller@ff6d0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0_PERILP>; - clock-names = "apb_pclk"; - }; - - dmac_peri: dma-controller@ff6e0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1_PERILP>; - clock-names = "apb_pclk"; - }; - - pmucru: pmu-clock-controller@ff750000 { - compatible = "rockchip,rk3399-pmucru"; - reg = <0x0 0xff750000 0x0 0x1000>; - rockchip,grf = <&pmugrf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&pmucru PLL_PPLL>; - assigned-clock-rates = <676000000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3399-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, - <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, - <&cru PCLK_PERIHP>, - <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, - <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, - <&cru ACLK_VIO>, <&cru ACLK_HDCP>, - <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; - assigned-clock-rates = - <594000000>, <800000000>, - <1000000000>, - <150000000>, <75000000>, - <37500000>, - <100000000>, <100000000>, - <50000000>, <600000000>, - <100000000>, <50000000>, - <400000000>, <400000000>, - <200000000>, - <200000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3399-io-voltage-domain"; - status = "disabled"; - }; - - mipi_dphy_rx0: mipi-dphy-rx0 { - compatible = "rockchip,rk3399-mipi-dphy-rx0"; - clocks = <&cru SCLK_MIPIDPHY_REF>, - <&cru SCLK_DPHY_RX0_CFG>, - <&cru PCLK_VIO_GRF>; - clock-names = "dphy-ref", "dphy-cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0: usb2phy@e450 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe450 0x10>; - clocks = <&cru SCLK_USB2PHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy0_480m"; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@e460 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe460 0x10>; - clocks = <&cru SCLK_USB2PHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy1_480m"; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - emmc_phy: phy@f780 { - compatible = "rockchip,rk3399-emmc-phy"; - reg = <0xf780 0x24>; - clocks = <&sdhci>; - clock-names = "emmcclk"; - #phy-cells = <0>; - status = "disabled"; - }; - - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - #phy-cells = <1>; - resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; - reset-names = "phy"; - status = "disabled"; - }; - }; - - tcphy0: phy@ff7c0000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; - assigned-clock-rates = <50000000>; - power-domains = <&power RK3399_PD_TCPD0>; - resets = <&cru SRST_UPHY0>, - <&cru SRST_UPHY0_PIPE_L00>, - <&cru SRST_P_UPHY0_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,grf = <&grf>; - status = "disabled"; - - tcphy0_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy0_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - tcphy1: phy@ff800000 { - compatible = "rockchip,rk3399-typec-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - clock-names = "tcpdcore", "tcpdphy-ref"; - assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; - assigned-clock-rates = <50000000>; - power-domains = <&power RK3399_PD_TCPD1>; - resets = <&cru SRST_UPHY1>, - <&cru SRST_UPHY1_PIPE_L00>, - <&cru SRST_P_UPHY1_TCPHY>; - reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,grf = <&grf>; - status = "disabled"; - - tcphy1_dp: dp-port { - #phy-cells = <0>; - }; - - tcphy1_usb3: usb3-port { - #phy-cells = <0>; - }; - }; - - watchdog@ff848000 { - compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; - reg = <0x0 0xff848000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - }; - - rktimer: rktimer@ff850000 { - compatible = "rockchip,rk3399-timer"; - reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; - clock-names = "pclk", "timer"; - }; - - spdif: spdif@ff870000 { - compatible = "rockchip,rk3399-spdif"; - reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 7>; - dma-names = "tx"; - clock-names = "mclk", "hclk"; - clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s0: i2s@ff880000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff880000 0x0 0x1000>; - rockchip,grf = <&grf>; - interrupts = ; - dmas = <&dmac_bus 0>, <&dmac_bus 1>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_8ch_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@ff890000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 2>, <&dmac_bus 3>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_bus>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@ff8a0000 { - compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac_bus 4>, <&dmac_bus 5>; - dma-names = "tx", "rx"; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; - power-domains = <&power RK3399_PD_SDIOAUDIO>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff8f0000 { - compatible = "rockchip,rk3399-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - assigned-clock-rates = <400000000>, <100000000>; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - iommus = <&vopl_mmu>; - power-domains = <&power RK3399_PD_VOPL>; - resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_mipi: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopl>; - }; - - vopl_out_dp: endpoint@4 { - reg = <4>; - remote-endpoint = <&dp_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff8f3f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPL>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopb: vop@ff900000 { - compatible = "rockchip,rk3399-vop-big"; - reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; - assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - assigned-clock-rates = <400000000>, <100000000>; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - iommus = <&vopb_mmu>; - power-domains = <&power RK3399_PD_VOPB>; - resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_edp: endpoint@0 { - reg = <0>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@1 { - reg = <1>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_hdmi: endpoint@2 { - reg = <2>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_mipi1: endpoint@3 { - reg = <3>; - remote-endpoint = <&mipi1_in_vopb>; - }; - - vopb_out_dp: endpoint@4 { - reg = <4>; - remote-endpoint = <&dp_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff903f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPB>; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp0: isp0@ff910000 { - compatible = "rockchip,rk3399-cif-isp"; - reg = <0x0 0xff910000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_ISP0>, - <&cru ACLK_ISP0_WRAPPER>, - <&cru HCLK_ISP0_WRAPPER>; - clock-names = "isp", "aclk", "hclk"; - iommus = <&isp0_mmu>; - phys = <&mipi_dphy_rx0>; - phy-names = "dphy"; - power-domains = <&power RK3399_PD_ISP0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - isp0_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_ISP0>; - rockchip,disable-mmu-reset; - }; - - isp1_mmu: iommu@ff924000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3399_PD_ISP1>; - rockchip,disable-mmu-reset; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "hdmi-sound"; - status = "disabled"; - - simple-audio-card,cpu { - sound-dai = <&i2s2>; - }; - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - }; - - hdmi: hdmi@ff940000 { - compatible = "rockchip,rk3399-dw-hdmi"; - reg = <0x0 0xff940000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, - <&cru SCLK_HDMI_SFR>, - <&cru PLL_VPLL>, - <&cru PCLK_VIO_GRF>, - <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "vpll", "grf", "cec"; - power-domains = <&power RK3399_PD_HDCP>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - mipi_dsi: mipi@ff960000 { - compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; - clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; - clock-names = "ref", "pclk", "phy_cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - resets = <&cru SRST_P_MIPI_DSI0>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - }; - }; - - mipi_dsi1: mipi@ff968000 { - compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff968000 0x0 0x8000>; - interrupts = ; - clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; - clock-names = "ref", "pclk", "phy_cfg", "grf"; - power-domains = <&power RK3399_PD_VIO>; - resets = <&cru SRST_P_MIPI_DSI1>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi1_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi1>; - }; - - mipi1_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi1>; - }; - }; - }; - }; - - edp: edp@ff970000 { - compatible = "rockchip,rk3399-edp"; - reg = <0x0 0xff970000 0x0 0x8000>; - interrupts = ; - clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; - clock-names = "dp", "pclk", "grf"; - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; - power-domains = <&power RK3399_PD_EDP>; - resets = <&cru SRST_P_EDP_CTRL>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - gpu: gpu@ff9a0000 { - compatible = "rockchip,rk3399-mali", "arm,mali-t860"; - reg = <0x0 0xff9a0000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - #cooling-cells = <2>; - power-domains = <&power RK3399_PD_GPU>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3399-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff720000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff720000 0x0 0x100>; - clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio1: gpio1@ff730000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff730000 0x0 0x100>; - clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio2: gpio2@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - clocks = <&cru PCLK_GPIO2>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio3: gpio3@ff788000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff788000 0x0 0x100>; - clocks = <&cru PCLK_GPIO3>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - gpio4: gpio4@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - clocks = <&cru PCLK_GPIO4>; - interrupts = ; - - gpio-controller; - #gpio-cells = <0x2>; - - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_none_13ma: pcfg-pull-none-13ma { - bias-disable; - drive-strength = <13>; - }; - - pcfg_pull_none_18ma: pcfg-pull-none-18ma { - bias-disable; - drive-strength = <18>; - }; - - pcfg_pull_none_20ma: pcfg-pull-none-20ma { - bias-disable; - drive-strength = <20>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_up_18ma: pcfg-pull-up-18ma { - bias-pull-up; - drive-strength = <18>; - }; - - pcfg_pull_up_20ma: pcfg-pull-up-20ma { - bias-pull-up; - drive-strength = <20>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_down_8ma: pcfg-pull-down-8ma { - bias-pull-down; - drive-strength = <8>; - }; - - pcfg_pull_down_12ma: pcfg-pull-down-12ma { - bias-pull-down; - drive-strength = <12>; - }; - - pcfg_pull_down_18ma: pcfg-pull-down-18ma { - bias-pull-down; - drive-strength = <18>; - }; - - pcfg_pull_down_20ma: pcfg-pull-down-20ma { - bias-pull-down; - drive-strength = <20>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - clock { - clk_32k: clk-32k { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = - <4 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = - /* mac_txclk */ - <3 RK_PC1 1 &pcfg_pull_none_13ma>, - /* mac_rxclk */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* mac_mdio */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* mac_txen */ - <3 RK_PB4 1 &pcfg_pull_none_13ma>, - /* mac_clk */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* mac_rxdv */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* mac_mdc */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* mac_rxd1 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* mac_rxd0 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* mac_txd1 */ - <3 RK_PA5 1 &pcfg_pull_none_13ma>, - /* mac_txd0 */ - <3 RK_PA4 1 &pcfg_pull_none_13ma>, - /* mac_rxd3 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* mac_rxd2 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* mac_txd3 */ - <3 RK_PA1 1 &pcfg_pull_none_13ma>, - /* mac_txd2 */ - <3 RK_PA0 1 &pcfg_pull_none_13ma>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = - /* mac_mdio */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* mac_txen */ - <3 RK_PB4 1 &pcfg_pull_none_13ma>, - /* mac_clk */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* mac_rxer */ - <3 RK_PB2 1 &pcfg_pull_none>, - /* mac_rxdv */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* mac_mdc */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* mac_rxd1 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* mac_rxd0 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* mac_txd1 */ - <3 RK_PA5 1 &pcfg_pull_none_13ma>, - /* mac_txd0 */ - <3 RK_PA4 1 &pcfg_pull_none_13ma>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none>, - <1 RK_PC0 2 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <4 RK_PA2 1 &pcfg_pull_none>, - <4 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PA1 2 &pcfg_pull_none_12ma>, - <2 RK_PA0 2 &pcfg_pull_none_12ma>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - <4 RK_PC1 1 &pcfg_pull_none>, - <4 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_none>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>, - <3 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - i2c6 { - i2c6_xfer: i2c6-xfer { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>, - <2 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - i2c7 { - i2c7_xfer: i2c7-xfer { - rockchip,pins = - <2 RK_PB0 2 &pcfg_pull_none>, - <2 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - i2c8 { - i2c8_xfer: i2c8-xfer { - rockchip,pins = - <1 RK_PC5 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_2ch_bus: i2s0-2ch-bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD1 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>, - <4 RK_PA0 1 &pcfg_pull_none>; - }; - - i2s0_8ch_bus: i2s0-8ch-bus { - rockchip,pins = - <3 RK_PD0 1 &pcfg_pull_none>, - <3 RK_PD1 1 &pcfg_pull_none>, - <3 RK_PD2 1 &pcfg_pull_none>, - <3 RK_PD3 1 &pcfg_pull_none>, - <3 RK_PD4 1 &pcfg_pull_none>, - <3 RK_PD5 1 &pcfg_pull_none>, - <3 RK_PD6 1 &pcfg_pull_none>, - <3 RK_PD7 1 &pcfg_pull_none>, - <4 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - i2s1 { - i2s1_2ch_bus: i2s1-2ch-bus { - rockchip,pins = - <4 RK_PA3 1 &pcfg_pull_none>, - <4 RK_PA4 1 &pcfg_pull_none>, - <4 RK_PA5 1 &pcfg_pull_none>, - <4 RK_PA6 1 &pcfg_pull_none>, - <4 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_up>, - <2 RK_PC5 1 &pcfg_pull_up>, - <2 RK_PC6 1 &pcfg_pull_up>, - <2 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = - <2 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = - <2 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = - <2 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = - <2 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = - <2 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <4 RK_PB0 1 &pcfg_pull_up>, - <4 RK_PB1 1 &pcfg_pull_up>, - <4 RK_PB2 1 &pcfg_pull_up>, - <4 RK_PB3 1 &pcfg_pull_up>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <4 RK_PB5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = - <0 RK_PA7 1 &pcfg_pull_up>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = - <0 RK_PB0 1 &pcfg_pull_up>; - }; - }; - - suspend { - ap_pwroff: ap-pwroff { - rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_bus: spdif-bus { - rockchip,pins = - <4 RK_PC5 1 &pcfg_pull_none>; - }; - - spdif_bus_1: spdif-bus-1 { - rockchip,pins = - <3 RK_PC0 3 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <3 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = - <3 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = - <3 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = - <3 RK_PA4 2 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_clk: spi2-clk { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = - <2 RK_PB1 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = - <2 RK_PB2 1 &pcfg_pull_up>; - }; - }; - - spi3 { - spi3_clk: spi3-clk { - rockchip,pins = - <1 RK_PC1 1 &pcfg_pull_up>; - }; - spi3_cs0: spi3-cs0 { - rockchip,pins = - <1 RK_PC2 1 &pcfg_pull_up>; - }; - spi3_rx: spi3-rx { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_up>; - }; - spi3_tx: spi3-tx { - rockchip,pins = - <1 RK_PC0 1 &pcfg_pull_up>; - }; - }; - - spi4 { - spi4_clk: spi4-clk { - rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_up>; - }; - spi4_cs0: spi4-cs0 { - rockchip,pins = - <3 RK_PA3 2 &pcfg_pull_up>; - }; - spi4_rx: spi4-rx { - rockchip,pins = - <3 RK_PA0 2 &pcfg_pull_up>; - }; - spi4_tx: spi4-tx { - rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_up>; - }; - }; - - spi5 { - spi5_clk: spi5-clk { - rockchip,pins = - <2 RK_PC6 2 &pcfg_pull_up>; - }; - spi5_cs0: spi5-cs0 { - rockchip,pins = - <2 RK_PC7 2 &pcfg_pull_up>; - }; - spi5_rx: spi5-rx { - rockchip,pins = - <2 RK_PC4 2 &pcfg_pull_up>; - }; - spi5_tx: spi5-tx { - rockchip,pins = - <2 RK_PC5 2 &pcfg_pull_up>; - }; - }; - - testclk { - test_clkout0: test-clkout0 { - rockchip,pins = - <0 RK_PA0 1 &pcfg_pull_none>; - }; - - test_clkout1: test-clkout1 { - rockchip,pins = - <2 RK_PD1 2 &pcfg_pull_none>; - }; - - test_clkout2: test-clkout2 { - rockchip,pins = - <0 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_up>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <2 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_up>, - <3 RK_PB5 2 &pcfg_pull_none>; - }; - }; - - uart2a { - uart2a_xfer: uart2a-xfer { - rockchip,pins = - <4 RK_PB0 2 &pcfg_pull_up>, - <4 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - uart2b { - uart2b_xfer: uart2b-xfer { - rockchip,pins = - <4 RK_PC0 2 &pcfg_pull_up>, - <4 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart2c { - uart2c_xfer: uart2c-xfer { - rockchip,pins = - <4 RK_PC3 1 &pcfg_pull_up>, - <4 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = - <3 RK_PB6 2 &pcfg_pull_up>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <1 RK_PA7 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - uarthdcp { - uarthdcp_xfer: uarthdcp-xfer { - rockchip,pins = - <4 RK_PC5 2 &pcfg_pull_up>, - <4 RK_PC6 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <4 RK_PC2 1 &pcfg_pull_none>; - }; - - pwm0_pin_pull_down: pwm0-pin-pull-down { - rockchip,pins = - <4 RK_PC2 1 &pcfg_pull_down>; - }; - - vop0_pwm_pin: vop0-pwm-pin { - rockchip,pins = - <4 RK_PC2 2 &pcfg_pull_none>; - }; - - vop1_pwm_pin: vop1-pwm-pin { - rockchip,pins = - <4 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <4 RK_PC6 1 &pcfg_pull_none>; - }; - - pwm1_pin_pull_down: pwm1-pin-pull-down { - rockchip,pins = - <4 RK_PC6 1 &pcfg_pull_down>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_none>; - }; - - pwm2_pin_pull_down: pwm2-pin-pull-down { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_down>; - }; - }; - - pwm3a { - pwm3a_pin: pwm3a-pin { - rockchip,pins = - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - pwm3b { - pwm3b_pin: pwm3b-pin { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_i2c_xfer: hdmi-i2c-xfer { - rockchip,pins = - <4 RK_PC1 3 &pcfg_pull_none>, - <4 RK_PC0 3 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = - <4 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pcie { - pcie_clkreqn_cpm: pci-clkreqn-cpm { - rockchip,pins = - <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_clkreqnb_cpm: pci-clkreqnb-cpm { - rockchip,pins = - <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - }; -}; diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi index 7c66e1145a50e2a285403cebfad251b8c9e12572..946a0230dbb4b88153df32fbbf89d4d6fff8c3ec 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -5,9 +5,3 @@ #include "rk3399pro-u-boot.dtsi" #include "rk3399-sdram-lpddr3-4GB-1600.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts deleted file mode 100644 index bf026786fa92716351da249ddb8df83a3ba8002b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399pro-rock-pi-n10.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Radxa Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -/dts-v1/; -#include "rk3399.dtsi" -#include "rk3399-opp.dtsi" -#include -#include "rk3399pro-vmarc-som.dtsi" - -/ { - model = "Radxa ROCK Pi N10"; - compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", - "rockchip,rk3399pro"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi deleted file mode 100644 index e1cb426f2aa53543890b73b71eb851a4ce7b1c37..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi +++ /dev/null @@ -1,467 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - * Copyright (c) 2019 Vamrs Limited - * Copyright (c) 2019 Amarula Solutions(India) - */ - -#include -#include -#include - -/ { - compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; - - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; - - vcc3v3_pcie: vcc-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwr>; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_l>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_l>; -}; - -&emmc_phy { - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_RMII_SRC>; - phy-supply = <&vcc_lan>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -}; - -&hdmi { - ddc-i2c-bus = <&i2c3>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec>; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <30>; - i2c-scl-rising-time-ns = <180>; - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5>; - vcc6-supply = <&vcc_buck5>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc5v0_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_cpu_l: DCDC_REG2 { - regulator-name = "vdd_cpu_l"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_buck5: DCDC_REG5 { - regulator-name = "vcc_buck5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2200000>; - }; - }; - - vcca_0v9: LDO_REG1 { - regulator-name = "vcca_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_0v9: LDO_REG3 { - regulator-name = "vcc_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcca_1v8: LDO_REG4 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1850000>; - }; - }; - - /* - * As per BSP, but schematic not showing any regulator - * pin for LD05. - */ - vdd1v5_dvp: LDO_REG5 { - regulator-name = "vdd1v5_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v5: LDO_REG6 { - regulator-name = "vcc_1v5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_3v0: LDO_REG7 { - regulator-name = "vccio_3v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG8 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* - * As per BSP, but schematic not showing any regulator - * pin for LD09. - */ - vcc_sd: LDO_REG9 { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v0_usb2: SWITCH_REG1 { - regulator-name = "vcc5v0_usb2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <5000000>; - }; - }; - - vccio_3v3: vcc_lan: SWITCH_REG2 { - regulator-name = "vccio_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c1 { - i2c-scl-falling-time-ns = <30>; - i2c-scl-rising-time-ns = <140>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio4>; - interrupts = ; - }; -}; - -&i2c3 { - i2c-scl-rising-time-ns = <450>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - bt656-supply = <&vcca_1v8>; - gpio1830-supply = <&vccio_3v0>; - sdmmc-supply = <&vccio_sd>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pcie0 { - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-0 = <&pcie_clkreqnb_cpm>; - pinctrl-names = "default"; - vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ - vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; - - pcie { - pcie_pwr: pcie-pwr { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - vbus_typec { - usb0_en_oc: usb0-en-oc { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - pmu1830-supply = <&vcc_1v8>; -}; - -&sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - status = "okay"; -}; - -&sdmmc { - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - max-frequency = <150000000>; -}; - -&tcphy0 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <1>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - phy-supply = <&vbus_typec>; - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vbus_host>; - status = "okay"; - }; -}; - - -&u2phy1 { - status = "okay"; - - u2phy1_host: host-port { - phy-supply = <&vbus_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - status = "okay"; -}; - -&vbus_host { - enable-active-high; - gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_oc>; -}; - -&vbus_typec { - enable-active-high; - gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_oc>; -}; diff --git a/arch/arm/dts/rk3399pro.dtsi b/arch/arm/dts/rk3399pro.dtsi deleted file mode 100644 index bb5ebf6608b98e1afbf4bdd47c86d56f2e625f74..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3399pro.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. - -#include "rk3399.dtsi" - -/ { - compatible = "rockchip,rk3399pro"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie_phy { - status = "okay"; -}; - -/* Default to enabled since AP talk to NPU part over pcie */ -&pcie0 { - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - num-lanes = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreqn_cpm>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi deleted file mode 100644 index 8cbf3d9a4f22ee975fe45616c31c71f351597b0b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi +++ /dev/null @@ -1,788 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "rk3566.dtsi" - -/ { - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-joystick { - compatible = "adc-joystick"; - io-channels = <&adc_mux 0>, - <&adc_mux 1>, - <&adc_mux 2>, - <&adc_mux 3>; - pinctrl-0 = <&joy_mux_en>; - pinctrl-names = "default"; - poll-interval = <60>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = ; - }; - - axis@1 { - reg = <1>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = ; - }; - - axis@2 { - reg = <2>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <15 1023>; - linux,code = ; - }; - - axis@3 { - reg = <3>; - abs-flat = <32>; - abs-fuzz = <32>; - abs-range = <1023 15>; - linux,code = ; - }; - }; - - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <60>; - - /* - * Button is mapped to F key in BSP kernel, but - * according to input guidelines it should be mode. - */ - button-mode { - label = "MODE"; - linux,code = ; - press-threshold-microvolt = <1750>; - }; - }; - - adc_mux: adc-mux { - compatible = "io-channel-mux"; - channels = "left_x", "right_x", "left_y", "right_y"; - #io-channel-cells = <1>; - io-channels = <&saradc 3>; - io-channel-names = "parent"; - mux-controls = <&gpio_mux>; - settle-time-us = <100>; - }; - - gpio_keys_control: gpio-keys-control { - compatible = "gpio-keys"; - pinctrl-0 = <&btn_pins_ctrl>; - pinctrl-names = "default"; - - button-b { - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; - label = "SOUTH"; - linux,code = ; - }; - - button-down { - gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - label = "DPAD-DOWN"; - linux,code = ; - }; - - button-l1 { - gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; - label = "TL"; - linux,code = ; - }; - - button-l2 { - gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - label = "TL2"; - linux,code = ; - }; - - button-select { - gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; - label = "SELECT"; - linux,code = ; - }; - - button-start { - gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; - label = "START"; - linux,code = ; - }; - - button-thumbl { - gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - label = "THUMBL"; - linux,code = ; - }; - - button-thumbr { - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; - label = "THUMBR"; - linux,code = ; - }; - - button-up { - gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; - label = "DPAD-UP"; - linux,code = ; - }; - - button-x { - gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - label = "NORTH"; - linux,code = ; - }; - }; - - gpio_keys_vol: gpio-keys-vol { - compatible = "gpio-keys"; - autorepeat; - pinctrl-0 = <&btn_pins_vol>; - pinctrl-names = "default"; - - button-vol-down { - gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - label = "VOLUMEDOWN"; - linux,code = ; - }; - - button-vol-up { - gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - label = "VOLUMEUP"; - linux,code = ; - }; - }; - - gpio_mux: mux-controller { - compatible = "gpio-mux"; - mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, - <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - #mux-control-cells = <0>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - ddc-i2c-bus = <&i2c5>; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds: pwm-leds { - compatible = "pwm-leds"; - - green_led: led-0 { - color = ; - default-state = "on"; - function = LED_FUNCTION_POWER; - max-brightness = <255>; - pwms = <&pwm6 0 25000 0>; - }; - - amber_led: led-1 { - color = ; - function = LED_FUNCTION_CHARGING; - max-brightness = <255>; - pwms = <&pwm7 0 25000 0>; - }; - - red_led: led-2 { - color = ; - default-state = "off"; - function = LED_FUNCTION_STATUS; - max-brightness = <255>; - pwms = <&pwm0 0 25000 0>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk817 1>; - clock-names = "ext_clock"; - pinctrl-0 = <&wifi_enable_h>; - pinctrl-names = "default"; - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; - }; - - vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-0 = <&vcc_lcd_h>; - pinctrl-names = "default"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_lcd0_n"; - vin-supply = <&vcc_3v3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_sys: regulator-vcc-sys { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-name = "vcc_sys"; - }; - - vcc_wifi: regulator-vcc-wifi { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc_wifi_h>; - pinctrl-names = "default"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_wifi"; - }; - - vibrator: pwm-vibrator { - compatible = "pwm-vibrator"; - pwm-names = "enable"; - pwms = <&pwm5 0 1000000000 0>; - }; -}; - -&combphy1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - pinctrl-0 = <&hdmitxm0_cec>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&dcdc_boost>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_logic"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca1v8_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc1v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc2v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - dcdc_boost: BOOST { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4700000>; - regulator-max-microvolt = <5400000>; - regulator-name = "boost"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - otg_switch: OTG_SWITCH { - regulator-name = "otg_switch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - vdd_cpu: regulator@40 { - compatible = "fcs,fan53555"; - reg = <0x40>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-name = "vdd_cpu"; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_sys>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - /* Unknown/unused device at 0x3c */ - status = "disabled"; -}; - -&i2c5 { - pinctrl-0 = <&i2c5m1_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_lrcktx - &i2s1m0_sdi0 - &i2s1m0_sdo0>; - pinctrl-names = "default"; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&pinctrl { - gpio-btns { - btn_pins_ctrl: btn-pins-ctrl { - rockchip,pins = - <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - btn_pins_vol: btn-pins-vol { - rockchip,pins = - <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - joy-mux { - joy_mux_en: joy-mux-en { - rockchip,pins = - <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc3v3-lcd { - vcc_lcd_h: vcc-lcd-h { - rockchip,pins = - <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc-wifi { - vcc_wifi_h: vcc-wifi-h { - rockchip,pins = - <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc1v8_dvp>; - vccio7-supply = <&vcc_3v3>; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm5 { - status = "okay"; -}; - -&pwm6 { - status = "okay"; -}; - -&pwm7 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - pinctrl-names = "default"; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>; - pinctrl-names = "default"; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc1v8_dvp>; - status = "okay"; -}; - -&sdmmc2 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_wifi>; - vqmmc-supply = <&vcca1v8_pmu>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart1 { - pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart2 { - status = "okay"; -}; - -/* - * Lack the schematics to verify, but port works as a peripheral - * (and not a host or OTG port). - */ -&usb_host0_xhci { - dr_mode = "peripheral"; - phys = <&usb2phy0_otg>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - phy-names = "usb2-phy", "usb3-phy"; - phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts deleted file mode 100644 index 59843a7a199c24a2ceabcd9a15c9a990525cb31c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-quartz64-a.dts +++ /dev/null @@ -1,838 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "Pine64 RK3566 Quartz64-A Board"; - compatible = "pine64,quartz64-a", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - fan: gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = - < 0 0>, - <4500 1>; - pinctrl-names = "default"; - pinctrl-0 = <&fan_en_h>; - #cooling-cells = <2>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-work { - label = "work-led"; - default-state = "off"; - gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_enable_h>; - retain-state-suspended; - }; - - led-diy { - label = "diy-led"; - default-state = "on"; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&diy_led_enable_h>; - retain-state-suspended; - }; - }; - - rk817-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK817"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk817 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - post-power-on-delay-ms = <100>; - power-off-delay-us = <5000000>; - reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; - }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; - - vcc12v_dcin: vcc12v_dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* vbus feeds the rk817 usb input. - * With no battery attached, also feeds vcc_bat+ - * via ON/OFF_BAT jumper - */ - vbus: vbus { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie_p"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - - vcc5v0_usb: vcc5v0_usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* all four ports are controlled by one gpio - * the host ports are sourced from vcc5v0_usb - * the otg port is sourced from vcc5v0_midu - */ - vcc5v0_usb20_host: vcc5v0_usb20_host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb20_host_en>; - regulator-name = "vcc5v0_usb20_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb20_otg: vcc5v0_usb20_otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc5v0_usb20_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dcdc_boost>; - }; - - vcc3v3_sd: vcc3v3_sd { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_sd_h>; - regulator-boot-on; - regulator-name = "vcc3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - - /* sourced from vbus and vcc_bat+ via rk817 sw5 */ - vcc_sys: vcc_sys { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - vin-supply = <&vbus>; - }; - - /* sourced from vcc_sys, sdio module operates internally at 3.3v */ - vcc_wl: vcc_wl { - compatible = "regulator-fixed"; - regulator-name = "vcc_wl"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu_thermal { - trips { - cpu_hot: cpu_hot { - temperature = <55000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - map1 { - trip = <&cpu_hot>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_3v3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_clkinout - &gmac1m0_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda_0v9>; - avdd-1v8-supply = <&vcc_1v8>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&dcdc_boost>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_logic"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc2v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - dcdc_boost: BOOST { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "boost"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - otg_switch: OTG_SWITCH { - regulator-name = "otg_switch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -/* i2c3 is exposed on con40 - * pin 3 - i2c3_sda_m0, pullup to vcc_3v3 - * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 - */ -&i2c3 { - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_lrcktx - &i2s1m0_sdi0 - &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_p>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fan { - fan_en_h: fan-en-h { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - work_led_enable_h: work-led-enable-h { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_enable_h: diy-led-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb2 { - vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc_sd { - vcc_sd_h: vcc-sd-h { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc1v8_dvp>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - sd-uhs-sdr104; - vmmc-supply = <&vcc_wl>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sfc { - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -/* spdif is exposed on con40 pin 18 */ -&spdif { - status = "okay"; -}; - -/* spi1 is exposed on con40 - * pin 11 - spi1_mosi_m1 - * pin 13 - spi1_miso_m1 - * pin 15 - spi1_clk_m1 - * pin 17 - spi1_cs0_m1 - */ -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; -}; - -&tsadc { - /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-mode = <1>; - /* tshut polarity 0:LOW 1:HIGH */ - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -/* uart0 is exposed on con40 - * pin 12 - uart0_tx - * pin 14 - uart0_rx - */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk817 1>; - clock-names = "lpo"; - host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc_sys>; - vddio-supply = <&vcca1v8_pmu>; - max-speed = <3000000>; - }; -}; - -/* uart2 is exposed on con40 - * pin 8 - uart2_tx_m0_debug - * pin 10 - uart2_rx_m0_debug - */ -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -/* usb3 controller is muxed with sata1 */ -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb20_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts deleted file mode 100644 index 2d92713be2a09f97ca603cbb64bdc49fd4fc00db..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-quartz64-b.dts +++ /dev/null @@ -1,737 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "Pine64 RK3566 Quartz64-B Board"; - compatible = "pine64,quartz64-b", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - mmc2 = &sdmmc1; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-user { - label = "user-led"; - default-state = "on"; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_enable_h>; - retain-state-suspended; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <100>; - power-off-delay-us = <5000000>; - }; - - vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie_p"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3>; - }; - - vcc5v0_in: vcc5v0-in-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_in"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_in>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_host"; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb30_host_en_h>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_otg"; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en_h>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-mode = "rgmii"; - phy-supply = <&vcc_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_clkinout - &gmac1m1_rgmii_bus>; - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x4f>; - rx_delay = <0x24>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - wakeup-source; - #clock-cells = <1>; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_log: DCDC_REG1 { - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-boot-on; - regulator-name = "vcc_3v3"; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - }; - }; - }; -}; - -/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m1_xfer>; - status = "okay"; -}; - -/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m1_xfer>; - status = "okay"; -}; - -/* - * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 - * pin 27 - i2c4_sda_m0 - * pin 28 - i2c4_scl_m0 - */ -&i2c4 { - status = "okay"; -}; - -/* - * i2c5_m0 is exposed on PI40 - * pin 29 - i2c5_scl_m0 - * pin 31 - i2c5_sda_m0 - */ -&i2c5 { - status = "disabled"; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_lrcktx - &i2s1m0_sdi0 - &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_p>; - status = "okay"; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - user_led_enable_h: user-led-enable-h { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - status = "okay"; - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcca1v8_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcca1v8_pmu>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcca1v8_pmu>; - status = "okay"; -}; - -&sfc { - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - status = "okay"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca1v8_pmu>; - }; -}; - -/* - * uart2_m0 is exposed on PI40 - * pin 8 - uart2_tx_m0 - * pin 10 - uart2_rx_m0 - */ -&uart2 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts deleted file mode 100644 index 3ae24e39450a2d30e4101ae0fe44bd97395781ec..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ /dev/null @@ -1,281 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Radxa Limited - * Copyright (c) 2022 Amarula Solutions(India) - */ - -/dts-v1/; -#include -#include "rk3566.dtsi" -#include "rk3566-radxa-cm3.dtsi" - -/ { - model = "Radxa Compute Module 3(CM3) IO Board"; - compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - mmc1 = &sdmmc0; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_ACTIVITY; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&pi_nled_activity>; - }; - }; - - vcc5v0_usb30: vcc5v0-usb30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30"; - enable-active-high; - gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb30_en_h>; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_sys>; - }; - - vcca1v8_image: vcca1v8-image-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8_p>; - }; - - vdda0v9_image: vdda0v9-image-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcca0v9_image"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vdda_0v9>; - }; -}; - -&combphy1 { - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "input"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_rgmii_bus - &gmac1m0_clkinout>; - snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x46>; - rx_delay = <0x2e>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pinctrl { - gmac1 { - gmac1m0_miim: gmac1m0-miim { - rockchip,pins = - /* gmac1_mdcm0 */ - <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_mdiom0 */ - <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>; - }; - - gmac1m0_rx_bus2: gmac1m0-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m0 */ - <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_rxd1m0 */ - <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_rxdvcrsm0 */ - <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>; - }; - - gmac1m0_tx_bus2: gmac1m0-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>; - }; - - gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>; - }; - - gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>; - }; - - gmac1m0_clkinout: gmac1m0-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm0 */ - <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>; - }; - }; - - leds { - pi_nled_activity: pi-nled-activity { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdcard { - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb30_en_h: vcc5v0-host-en-h { - rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb30>; - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3566-radxa-cm3.dtsi b/arch/arm/dts/rk3566-radxa-cm3.dtsi deleted file mode 100644 index 45de2630bb503ae1d20fe6bc998477f73800ca7d..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-radxa-cm3.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Radxa Limited - * Copyright (c) 2022 Amarula Solutions(India) - */ - -#include -#include - -/ { - compatible = "radxa,cm3", "rockchip,rk3566"; - - aliases { - mmc0 = &sdhci; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - linux,default-trigger = "timer"; - default-state = "on"; - pinctrl-names = "default"; - pinctrl-0 = <&user_led2>; - }; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v8: vcc-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8_p>; - }; - - vcc_3v3: vcc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcca_1v8: vcca-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_1v8_p>; - }; - - sdio_pwrseq: pwrseq-sdio { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk817 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_h>; - reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu_npu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - #clock-cells = <1>; - clock-output-names = "rk817-clkout1", "rk817-clkout2"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu_npu: DCDC_REG2 { - regulator-name = "vdd_gpu_npu"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca1v8_pmu: LDO_REG1 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8_p: LDO_REG7 { - regulator-name = "vcc_1v8_p"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-name = "vcc1v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG9 { - regulator-name = "vcc2v8_dvp"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - }; - }; -}; - -&pinctrl { - bluetooth { - bt_host_wake_h: bt-host-wake-h { - rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reg_on_h: bt-reg-on-h { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_host_h: bt-wake-host-h { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - user_led2: user-led2 { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - wifi_reg_on_h: wifi-reg-on-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_host_wake_h: wifi-host-wake-h { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc_3v3>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdmmc1 { - #address-cells = <1>; - #size-cells = <0>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm43455-fmac"; - reg = <1>; - interrupt-parent = <&gpio2>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_h>; - }; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rk817 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>; - vbat-supply = <&vcc_3v3>; - vddio-supply = <&vcc_1v8>; - }; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts deleted file mode 100644 index fdbf1c78324229b81715279e4182e39bb3cde176..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-soquartz-blade.dts +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include - -#include "rk3566-soquartz.dtsi" - -/ { - model = "PINE64 RK3566 SOQuartz on Blade carrier board"; - compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - }; - - /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ - vcc3v0_sd: vcc3v0-sd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* labeled VCC_SSD in schematic */ - vcc3v3_pcie_p: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie_p"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vbus>; - }; - - vcc5v_dcin: vcc5v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&combphy2 { - phy-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -&gmac1 { - status = "okay"; -}; - -/* - * i2c1 is exposed on CM1 / Module1A - * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu - * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu - */ -&i2c1 { - status = "okay"; - -}; - -/* - * i2c2 is exposed on CM1 / Module1A - to PI40 - * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch - * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 - */ -&i2c2 { - status = "disabled"; -}; - -/* - * i2c3 is exposed on CM1 / Module1A - to PI40 - * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 - * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 - */ -&i2c3 { - status = "disabled"; -}; - -/* - * i2c4 is exposed on CM2 / Module1B - to PI40 - * pin 45 - GPIO24 - i2c4_scl_m1 - * pin 47 - GPIO23 - i2c4_sda_m1 - */ -&i2c4 { - status = "disabled"; -}; - -/* - * i2s1_8ch is exposed on CM1 / Module1A - to PI40 - * pin 24 - GPIO26 - i2s1_sdi1_m1 - * pin 25 - GPIO21 - i2s1_sdo0_m1 - * pin 26 - GPIO19 - i2s1_lrck_tx_m1 - * pin 27 - GPIO20 - i2s1_sdi0_m1 - * pin 29 - GPIO16 - i2s1_sdi3_m1 - * pin 30 - GPIO6 - i2s1_sdi2_m1 - * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 - * pin 41 - GPIO25 - i2s1_sdo2_m1 - * pin 49 - GPIO18 - i2s1_sclk_tx_m1 - * pin 50 - GPIO17 - i2s1_mclk_m1 - * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 - */ -&i2s1_8ch { - status = "disabled"; -}; - -&led_diy { - color = ; - function = LED_FUNCTION_DISK_ACTIVITY; - linux,default-trigger = "disk-activity"; - status = "okay"; -}; - -&led_work { - color = ; - function = LED_FUNCTION_STATUS; - linux,default-trigger = "heartbeat"; - status = "okay"; -}; - -&pcie2x1 { - vpcie3v3-supply = <&vcc3v3_pcie_p>; - status = "okay"; -}; - -&rgmii_phy1 { - status = "okay"; -}; - -/* - * saradc is exposed on CM1 / Module1A - to J2 - * pin 94 - AIN1 - saradc_vin3 - * pin 96 - AIN0 - saradc_vin2 - */ -&saradc { - status = "disabled"; -}; - -&sdmmc0 { - vmmc-supply = <&vcc3v0_sd>; - status = "okay"; -}; - -/* - * spi3 is exposed on CM1 / Module1A - to PI40 - * pin 37 - GPIO7 - spi3_cs1_m0 - * pin 38 - GPIO11 - spi3_clk_m0 - * pin 39 - GPIO8 - spi3_cs0_m0 - * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch - * pin 44 - GPIO10 - spi3_mosi_m0 - */ -&spi3 { - status = "disabled"; -}; - -/* - * uart2 is exposed on CM1 / Module1A - to PI40 - * pin 51 - GPIO15 - uart2_rx_m0 - * pin 55 - GPIO14 - uart2_tx_m0 - */ -&uart2 { - status = "okay"; -}; - -/* - * uart7 is exposed on CM1 / Module1A - to PI40 - * pin 46 - GPIO22 - uart7_tx_m2 - * pin 47 - GPIO23 - uart7_rx_m2 - */ -&uart7 { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vbus>; - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&vbus { - vin-supply = <&vcc5v_dcin>; -}; diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts deleted file mode 100644 index 6ed3fa4aee34f22a0b09f189000800331a49b2aa..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-soquartz-cm4.dts +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3566-soquartz.dtsi" - -/ { - model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; - compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - }; - - /* labeled +12v in schematic */ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* labeled +5v in schematic */ - vcc_5v: vcc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_sd_pwr: vcc-sd-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sd_pwr"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -/* phy for pcie */ -&combphy2 { - phy-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -&gmac1 { - status = "okay"; -}; - -/* - * i2c1 is exposed on CM1 / Module1A - * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu - * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu - */ -&i2c1 { - status = "okay"; - - /* - * the rtc interrupt is tied to PMIC_PWRON, - * it will force reset the board if triggered. - */ - pcf85063: rtc@51 { - compatible = "nxp,pcf85063"; - reg = <0x51>; - }; -}; - -/* - * i2c2 is exposed on CM1 / Module1A - to PI40 - * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch - * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 - */ -&i2c2 { - status = "disabled"; -}; - -/* - * i2c3 is exposed on CM1 / Module1A - to PI40 - * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 - * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 - */ -&i2c3 { - status = "disabled"; -}; - -/* - * i2c4 is exposed on CM2 / Module1B - to PI40 - * pin 45 - GPIO24 - i2c4_scl_m1 - * pin 47 - GPIO23 - i2c4_sda_m1 - */ -&i2c4 { - status = "disabled"; -}; - -/* - * i2s1_8ch is exposed on CM1 / Module1A - to PI40 - * pin 24 - GPIO26 - i2s1_sdi1_m1 - * pin 25 - GPIO21 - i2s1_sdo0_m1 - * pin 26 - GPIO19 - i2s1_lrck_tx_m1 - * pin 27 - GPIO20 - i2s1_sdi0_m1 - * pin 29 - GPIO16 - i2s1_sdi3_m1 - * pin 30 - GPIO6 - i2s1_sdi2_m1 - * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 - * pin 41 - GPIO25 - i2s1_sdo2_m1 - * pin 49 - GPIO18 - i2s1_sclk_tx_m1 - * pin 50 - GPIO17 - i2s1_mclk_m1 - * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 - */ -&i2s1_8ch { - status = "disabled"; -}; - -&led_diy { - status = "okay"; -}; - -&led_work { - status = "okay"; -}; - -&pcie2x1 { - vpcie3v3-supply = <&vcc_3v3>; - status = "okay"; -}; - -&rgmii_phy1 { - status = "okay"; -}; - -/* - * saradc is exposed on CM1 / Module1A - to J2 - * pin 94 - AIN1 - saradc_vin3 - * pin 96 - AIN0 - saradc_vin2 - */ -&saradc { - status = "disabled"; -}; - -&sdmmc0 { - vmmc-supply = <&vcc_sd_pwr>; - status = "okay"; -}; - -/* - * spi3 is exposed on CM1 / Module1A - to PI40 - * pin 37 - GPIO7 - spi3_cs1_m0 - * pin 38 - GPIO11 - spi3_clk_m0 - * pin 39 - GPIO8 - spi3_cs0_m0 - * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch - * pin 44 - GPIO10 - spi3_mosi_m0 - */ -&spi3 { - status = "disabled"; -}; - -/* - * uart2 is exposed on CM1 / Module1A - to PI40 - * pin 51 - GPIO15 - uart2_rx_m0 - * pin 55 - GPIO14 - uart2_tx_m0 - */ -&uart2 { - status = "okay"; -}; - -/* - * uart7 is exposed on CM1 / Module1A - to PI40 - * pin 46 - GPIO22 - uart7_tx_m2 - * pin 47 - GPIO23 - uart7_rx_m2 - */ -&uart7 { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc_5v>; - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&vbus { - vin-supply = <&vcc_5v>; -}; diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts deleted file mode 100644 index f2095dfa4eaf6efe2d4c46d2dd78f68fa266ff7f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-soquartz-model-a.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3566-soquartz.dtsi" - -/ { - model = "PINE64 RK3566 SOQuartz on Model A carrier board"; - compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; - - aliases { - ethernet0 = &gmac1; - }; - - /* labeled DCIN_12V in schematic */ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* - * Labelled VCC3V0_SD in schematic to not conflict with PMIC - * regulator, it's 3.3v in actuality - */ - vcc3v0_sd: vcc3v0-sd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v0_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc12v_pcie: vcc12v-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_pcie"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&vcc12v_dcin>; - }; -}; - -/* phy for pcie */ -&combphy2 { - phy-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -&gmac1 { - status = "okay"; -}; - -/* - * i2c1 is exposed on CM1 / Module1A - * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu - * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu - */ -&i2c1 { - status = "okay"; - - /* - * the rtc interrupt is tied to PMIC_PWRON, - * it will force reset the board if triggered. - */ - pcf85063: rtc@51 { - compatible = "nxp,pcf85063"; - reg = <0x51>; - }; -}; - -/* - * i2c2 is exposed on CM1 / Module1A - to PI40 - * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch - * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 - */ -&i2c2 { - status = "disabled"; -}; - -/* - * i2c3 is exposed on CM1 / Module1A - to PI40 - * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 - * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 - */ -&i2c3 { - status = "disabled"; -}; - -/* - * i2c4 is exposed on CM2 / Module1B - to PI40 - * pin 45 - GPIO24 - i2c4_scl_m1 - * pin 47 - GPIO23 - i2c4_sda_m1 - */ -&i2c4 { - status = "disabled"; -}; - -/* - * i2s1_8ch is exposed on CM1 / Module1A - to PI40 - * pin 24 - GPIO26 - i2s1_sdi1_m1 - * pin 25 - GPIO21 - i2s1_sdo0_m1 - * pin 26 - GPIO19 - i2s1_lrck_tx_m1 - * pin 27 - GPIO20 - i2s1_sdi0_m1 - * pin 29 - GPIO16 - i2s1_sdi3_m1 - * pin 30 - GPIO6 - i2s1_sdi2_m1 - * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 - * pin 41 - GPIO25 - i2s1_sdo2_m1 - * pin 49 - GPIO18 - i2s1_sclk_tx_m1 - * pin 50 - GPIO17 - i2s1_mclk_m1 - * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 - */ -&i2s1_8ch { - status = "disabled"; -}; - -&led_diy { - status = "okay"; -}; - -&led_work { - status = "okay"; -}; - -&pcie2x1 { - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&rgmii_phy1 { - status = "okay"; -}; - -&rgmii_phy1 { - status = "okay"; -}; - -/* - * saradc is exposed on CM1 / Module1A - to J2 - * pin 94 - AIN1 - saradc_vin3 - * pin 96 - AIN0 - saradc_vin2 - */ -&saradc { - status = "disabled"; -}; - -/* - * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ - * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, - * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. - */ -&sdmmc0 { - vmmc-supply = <&vcc3v3_sd>; - status = "okay"; -}; - -/* - * spi3 is exposed on CM1 / Module1A - to PI40 - * pin 37 - GPIO7 - spi3_cs1_m0 - * pin 38 - GPIO11 - spi3_clk_m0 - * pin 39 - GPIO8 - spi3_cs0_m0 - * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch - * pin 44 - GPIO10 - spi3_mosi_m0 - */ -&spi3 { - status = "disabled"; -}; - -/* - * uart2 is exposed on CM1 / Module1A - to PI40 - * pin 51 - GPIO15 - uart2_rx_m0 - * pin 55 - GPIO14 - uart2_tx_m0 - */ -&uart2 { - status = "okay"; -}; - -/* - * uart7 is exposed on CM1 / Module1A - to PI40 - * pin 46 - GPIO22 - uart7_tx_m2 - * pin 47 - GPIO23 - uart7_rx_m2 - */ -&uart7 { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb>; - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&vbus { - vin-supply = <&vcc5v0_usb>; -}; - -&vcc3v3_sd { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi deleted file mode 100644 index bfb7b952f4c5e849ed243c53ff3abef5cfb3c4d8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566-soquartz.dtsi +++ /dev/null @@ -1,684 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3566.dtsi" - -/ { - model = "Pine64 RK3566 SoQuartz SOM"; - compatible = "pine64,soquartz", "rockchip,rk3566"; - - aliases { - mmc0 = &sdmmc0; - mmc1 = &sdhci; - mmc2 = &sdmmc1; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_diy: led-diy { - label = "diy-led"; - default-state = "on"; - gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&diy_led_enable_h>; - retain-state-suspended; - status = "disabled"; - }; - - led_work: led-work { - label = "work-led"; - default-state = "off"; - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&work_led_enable_h>; - retain-state-suspended; - status = "disabled"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - status = "okay"; - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; - }; - - vbus: vbus-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - /* sourced from vbus, vbus is provided by the carrier board */ - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vbus>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-supply = <&vcc_3v3>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m0_miim - &gmac1m0_tx_bus2 - &gmac1m0_rx_bus2 - &gmac1m0_rgmii_clk - &gmac1m0_clkinout - &gmac1m0_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - phy-handle = <&rgmii_phy1>; - status = "disabled"; -}; - -&gpio0 { - nextrst-hog { - gpio-hog; - /* - * GPIO_ACTIVE_LOW + output-low here means that the pin is set - * to high, because output-low decides the value pre-inversion. - */ - gpios = ; - line-name = "nEXTRST"; - output-low; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_image"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - status = "disabled"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - }; - }; -}; - -/* - * i2c1 is exposed on CM1 / Module1A - * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu - * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu - */ -&i2c1 { - status = "disabled"; -}; - -/* - * i2c2 is exposed on CM1 / Module1A - * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch - * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 - */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m1_xfer>; - status = "disabled"; -}; - -/* - * i2c3 is exposed on CM1 / Module1A - * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 - * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 - */ -&i2c3 { - status = "disabled"; -}; - -/* - * i2c4 is exposed on CM2 / Module1B - * pin 45 - i2c4_scl_m1 - * pin 47 - i2c4_sda_m1 - */ -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "disabled"; -}; - -&i2s0_8ch { - status = "okay"; -}; - -/* - * i2s1_8ch is exposed on CM1 / Module1A - * pin 24 - i2s1_sdi1_m1 - * pin 25 - i2s1_sdo0_m1 - * pin 26 - i2s1_lrck_tx_m1 - * pin 27 - i2s1_sdi0_m1 - * pin 29 - i2s1_sdi3_m1 - * pin 30 - i2s1_sdi2_m1 - * pin 40 - i2s1_sdo1_m1, shared with spi3 - * pin 41 - i2s1_sdo2_m1 - * pin 49 - i2s1_sclk_tx_m1 - * pin 50 - i2s1_mclk_m1 - * pin 56 - i2s1_sdo3_m1, shared with i2c2 - */ -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx - &i2s1m1_lrcktx &i2s1m1_lrckrx - &i2s1m1_sdi0 &i2s1m1_sdi1 - &i2s1m1_sdi2 &i2s1m1_sdi3 - &i2s1m1_sdo0 &i2s1m1_sdo1 - &i2s1m1_sdo2 &i2s1m1_sdo3>; - status = "disabled"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - status = "disabled"; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -}; - -&pinctrl { - bt { - bt_enable_h: bt-enable-h { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake_l: bt-host-wake-l { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake_l: bt-wake-l { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - work_led_enable_h: work-led-enable-h { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_enable_h: diy-led-enable-h { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_clkreq_h: pcie-clkreq-h { - rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - pcie_reset_h: pcie-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -/* - * saradc is exposed on CM1 / Module1A - * pin 94 - saradc_vin3 - * pin 96 - saradc_vin2 - */ -&saradc { - vref-supply = <&vcca_1v8>; - status = "disabled"; -}; - -&sdhci { - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - broken-cd; - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - vqmmc-supply = <&vccio_sd>; - status = "disabled"; -}; - -&sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; - sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -/* - * spi3 is exposed on CM1 / Module1A - * pin 37 - spi3_cs1_m0 - * pin 38 - spi3_clk_m0 - * pin 39 - spi3_cs0_m0 - * pin 40 - spi3_miso_m0, shared with i2s1_8ch - * pin 44 - spi3_mosi_m0 - */ -&spi3 { - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcca1v8_pmu>; - }; -}; - -/* - * uart2 is exposed on CM1 / Module1A - * pin 51 - uart2_rx_m0 - * pin 55 - uart2_tx_m0 - */ -&uart2 { - status = "disabled"; -}; - -/* - * uart7 is exposed on CM1 / Module1A - * pin 46 - uart7_tx_m2 - * pin 47 - uart7_rx_m2 - */ -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7m2_xfer>; - status = "disabled"; -}; - -/* dwc3_otg is the only usb port available */ -&usb2phy0 { - status = "disabled"; -}; - -&usb2phy0_otg { - status = "disabled"; -}; - -&usb_host0_xhci { - status = "disabled"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3566.dtsi b/arch/arm/dts/rk3566.dtsi deleted file mode 100644 index 6c4b17d27bdc526ffacc1d991a09f3982434e9f3..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3566.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3566"; -}; - -&pipegrf { - compatible = "rockchip,rk3566-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>; - phy-names = "usb2-phy"; - extcon = <&usb2phy0>; - maximum-speed = "high-speed"; -}; - -&vop { - compatible = "rockchip,rk3566-vop"; -}; diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts deleted file mode 100644 index f9127ddfbb7dfdaa9b2bfd6040ef9ed2ab1986b3..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-bpi-r2-pro.dts +++ /dev/null @@ -1,852 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Author: Frank Wunderlich - * - */ - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; - compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin &green_led_pin>; - - blue_led: led-0 { - color = ; - default-state = "off"; - function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - }; - - green_led: led-1 { - color = ; - default-state = "on"; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_receiver_pin>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* pi6c pcie clock generator feeds both ports */ - vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ - vcc3v3_minipcie: vcc3v3-minipcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_minipcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_enable_h>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pi6c_05>; - }; - - /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ - vcc3v3_ngff: vcc3v3-ngff-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ngff"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ngffpcie_enable_h>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pi6c_05>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; -}; - -&combphy0 { - /* used for USB3 */ - status = "okay"; -}; - -&combphy1 { - /* used for USB3 */ - status = "okay"; -}; - -&combphy2 { - /* used for SATA */ - status = "okay"; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - clock_in_out = "input"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - tx_delay = <0x4f>; - rx_delay = <0x0f>; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - - snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - tx_delay = <0x3c>; - rx_delay = <0x2f>; - - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2c5 { - /* pin 3 (SDA) + 4 (SCL) of header con2 */ - status = "disabled"; -}; - -&i2s0_8ch { - /* hdmi sound */ - status = "okay"; -}; - -&mdio0 { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - }; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&pcie30phy { - data-lanes = <1 2>; - phy-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; - -&pcie3x1 { - /* M.2 slot */ - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&ngffpcie_reset_h>; - reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_ngff>; - status = "okay"; -}; - -&pcie3x2 { - /* mPCIe slot */ - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_minipcie>; - status = "okay"; -}; - -&pinctrl { - leds { - blue_led_pin: blue-led-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - green_led_pin: green-led-pin { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - minipcie_enable_h: minipcie-enable-h { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; - }; - - ngffpcie_enable_h: ngffpcie-enable-h { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; - }; - - minipcie_reset_h: minipcie-reset-h { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; - }; - - ngffpcie_reset_h: ngffpcie-reset-h { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm8 { - /* fan 5v - gnd - pwm */ - status = "okay"; -}; - -&pwm10 { - /* pin 7 of header con2 */ - status = "disabled"; -}; - -&pwm11 { - /* pin 15 of header con2 */ - status = "disabled"; -}; - -&pwm12 { - /* pin 21 of header con2 */ - /* shared with uart9 + spi3 */ - pinctrl-0 = <&pwm12m1_pins>; - status = "disabled"; -}; - -&pwm13 { - /* pin 24 of header con2 */ - /* shared with uart9 */ - pinctrl-0 = <&pwm13m1_pins>; - status = "disabled"; -}; - -&pwm14 { - /* pin 23 of header con2 */ - /* shared with spi3 */ - pinctrl-0 = <&pwm14m1_pins>; - status = "disabled"; -}; - -&pwm15 { - /* pin 19 of header con2 */ - /* shared with spi3 */ - pinctrl-0 = <&pwm15m1_pins>; - status = "disabled"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&spi3 { - /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */ - /* shared with pwm12/14/15 and uart9 */ - pinctrl-0 = <&spi3m1_pins>; - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart0 { - /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */ - status = "disabled"; -}; - -&uart2 { - /* debug-uart */ - status = "okay"; -}; - -&uart7 { - /* pin 11 (TX) + 13 (RX) of header con2 */ - pinctrl-0 = <&uart7m1_xfer>; - status = "disabled"; -}; - -&uart9 { - /* pin 21 (TX) + 24 (RX) of header con2 */ - /* shared with pwm13 and pwm12/spi3 */ - pinctrl-0 = <&uart9m1_xfer>; - status = "disabled"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - /* USB for PCIe/M2 */ - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts deleted file mode 100644 index 19f8fc369b1308cdfe8bfaa3b49e6f6b5134bb27..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-evb.dts +++ /dev/null @@ -1,689 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; - compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led_work: led-0 { - gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_work_en>; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc3v3_lcd0_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc3v3_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_lcd0_n_en>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_lcd1_n: vcc3v3-lcd1-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd1_n"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc3v3_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_lcd1_n_en>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - status = "okay"; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - codec { - mic-in-differential; - }; - }; -}; - -&i2c1 { - status = "okay"; - - touchscreen0: goodix@14 { - compatible = "goodix,gt1151"; - reg = <0x14>; - interrupt-parent = <&gpio0>; - interrupts = ; - AVDD28-supply = <&vcc3v3_lcd0_n>; - irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_int &touch_rst>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - VDDIO-supply = <&vcc3v3_lcd0_n>; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - display { - vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en { - rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>; - }; - vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en { - rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; - }; - }; - - leds { - led_work_en: led_work_en { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touchscreen { - touch_int: touch_int { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - touch_rst: touch_rst { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts deleted file mode 100644 index a8a4cc190eb32e2cf18d9ab7f8549a96c12a6465..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-lubancat-2.dts +++ /dev/null @@ -1,730 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2022 EmbedFire - */ - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "EmbedFire LubanCat 2"; - compatible = "embedfire,lubancat-2", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - - user_led: user-led { - label = "user_led"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_pin>; - }; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - dc_5v: dc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_5v>; - }; - - vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "m2_pcie_3v3"; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc3v3_m2_pcie_en>; - pinctrl-names = "default"; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "minipcie_3v3"; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc3v3_mini_pcie_en>; - pinctrl-names = "default"; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb20_host"; - enable-active-high; - gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc5v0_usb20_host_en>; - pinctrl-names = "default"; - }; - - vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_host"; - enable-active-high; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc5v0_usb30_host_en>; - pinctrl-names = "default"; - }; - - vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg_vbus"; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&vcc5v0_otg_vbus_en>; - pinctrl-names = "default"; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&gmac0 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x22>; - rx_delay = <0x0e>; - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&gmac1 { - phy-mode = "rgmii"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - - tx_delay = <0x21>; - rx_delay = <0x0e>; - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - }; -}; - -&gic { - mbi-ranges = <94 31>, <229 31>, <289 31>; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x2 { - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_m2_pcie>; - status = "okay"; -}; - -&pcie2x1 { - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_mini_pcie>; - status = "okay"; -}; - -&pmu_io_domains { - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm8 { - status = "okay"; -}; - -&pwm9 { - status = "disabled"; -}; - -&pwm10 { - status = "disabled"; -}; - -&pwm14 { - status = "disabled"; -}; - -&spi3 { - pinctrl-0 = <&spi3m1_pins>; - status = "disabled"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3m1_xfer>; - status = "disabled"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&sdhci { - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs200-1_8v; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; - supports-emmc; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -/* USB OTG/USB Host_1 USB 2.0 Comb */ -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_otg_vbus>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -/* USB Host_2/USB Host_3 USB 2.0 Comb */ -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ -&usb_host0_xhci { - phys = <&usb2phy0_otg>; - phy-names = "usb2-phy"; - extcon = <&usb2phy0>; - maximum-speed = "high-speed"; - dr_mode = "host"; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -/* USB3.0 Host */ -&usb_host1_xhci { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; - -&pinctrl { - leds { - user_led_pin: user-status-led-pin { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { - rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts deleted file mode 100644 index c718b8dbb9c6bc0b5055aafa6286a2925efe4d1c..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-nanopi-r5c.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyelec.com) - * - * Copyright (c) 2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3568-nanopi-r5s.dtsi" - -/ { - model = "FriendlyElec NanoPi R5C"; - compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&reset_button_pin>; - - button-reset { - debounce-interval = <50>; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - label = "reset"; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; - - led-lan { - color = ; - function = LED_FUNCTION_LAN; - gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; - linux,default-trigger = "heartbeat"; - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - color = ; - function = LED_FUNCTION_WAN; - gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; - }; - - led-wlan { - color = ; - function = LED_FUNCTION_WLAN; - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie20_reset_pin>; - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - lan_led_pin: lan-led-pin { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - power_led_pin: power-led-pin { - rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wlan_led_pin: wlan-led-pin { - rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie20_reset_pin: pcie20-reset-pin { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rockchip-key { - reset_button_pin: reset-button-pin { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts deleted file mode 100644 index b6ad8328c7ebc4102552d6374ea548b5bcd8c9d5..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-nanopi-r5s.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyelec.com) - * - * Copyright (c) 2023 Tianling Shen - */ - -/dts-v1/; -#include "rk3568-nanopi-r5s.dtsi" - -/ { - model = "FriendlyElec NanoPi R5S"; - compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; - - led-lan1 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <1>; - gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; - }; - - led-lan2 { - color = ; - function = LED_FUNCTION_LAN; - function-enumerator = <2>; - gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; - }; - - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; - linux,default-trigger = "heartbeat"; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - }; - - led-wan { - color = ; - function = LED_FUNCTION_WAN; - gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 15ms, 50ms for rtl8211f */ - snps,reset-delays-us = <0 15000 50000>; - tx_delay = <0x3c>; - rx_delay = <0x2f>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - pinctrl-0 = <ð_phy0_reset_pin>; - pinctrl-names = "default"; - }; -}; - -&pcie2x1 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - num-ib-windows = <8>; - num-ob-windows = <8>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - gmac0 { - eth_phy0_reset_pin: eth-phy0-reset-pin { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - gpio-leds { - lan1_led_pin: lan1-led-pin { - rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lan2_led_pin: lan2-led-pin { - rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - power_led_pin: power-led-pin { - rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wan_led_pin: wan-led-pin { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi deleted file mode 100644 index 93189f830640066a3f979fb6b84a36f67b9ffbd5..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-nanopi-r5s.dtsi +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyelec.com) - * - * Copyright (c) 2023 Tianling Shen - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - aliases { - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vdd_usbc: vdd-usbc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd_usbc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - }; -}; - -&i2c5 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0-usb-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts deleted file mode 100644 index a337f547caf538105a6e1644466ba62af44bc395..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-odroid-m1.dts +++ /dev/null @@ -1,741 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Hardkernel Co., Ltd. - * - */ - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Hardkernel ODROID-M1"; - compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac0; - i2c0 = &i2c3; - i2c3 = &i2c0; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - serial0 = &uart1; - serial1 = &uart0; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_receiver_pin>; - }; - - leds { - compatible = "gpio-leds"; - - led_power: led-0 { - gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_POWER; - color = ; - default-state = "keep"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_power_pin>; - }; - led_work: led-1 { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_work_pin>; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det_pin>; - simple-audio-card,name = "Analog RK817"; - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker", "SPKO"; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - enable-active-high; - gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en_pin>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_host"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en_pin>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_otg"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0 { - /* Used for USB3 */ - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&combphy1 { - /* Used for USB3 */ - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&combphy2 { - /* used for SATA */ - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac0 { - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii"; - phy-supply = <&vcc3v3_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - status = "okay"; - - tx_delay = <0x4f>; - rx_delay = <0x2d>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pin>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - fspi { - fspi_dual_io_pins: fspi-dual-io-pins { - rockchip,pins = - /* fspi_clk */ - <1 RK_PD0 1 &pcfg_pull_none>, - /* fspi_cs0n */ - <1 RK_PD3 1 &pcfg_pull_none>, - /* fspi_d0 */ - <1 RK_PD1 1 &pcfg_pull_none>, - /* fspi_d1 */ - <1 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - /* external pullup to VCC3V3_SYS */ - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_power_pin: led-power-pin { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - led_work_pin: led-work-pin { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_reset_pin: pcie-reset-pin { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { - rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rk809 { - hp_det_pin: hp-det-pin { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sfc { - /* Dual I/O mode as the D2 pin conflicts with the eMMC */ - pinctrl-0 = <&fspi_dual_io_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0x0 0xe0000>; - }; - partition@e0000 { - label = "U-Boot Env"; - reg = <0xe0000 0x20000>; - }; - partition@100000 { - label = "U-Boot"; - reg = <0x100000 0x200000>; - }; - partition@300000 { - label = "splash"; - reg = <0x300000 0x100000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0xc00000>; - }; - }; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi deleted file mode 100644 index 0a979bfb63d9d8770a685a2c135393a2421ca194..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-pinctrl.dtsi +++ /dev/null @@ -1,3214 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - acodec { - /omit-if-no-ref/ - acodec_pins: acodec-pins { - rockchip,pins = - /* acodec_adc_sync */ - <1 RK_PB1 5 &pcfg_pull_none>, - /* acodec_adcclk */ - <1 RK_PA1 5 &pcfg_pull_none>, - /* acodec_adcdata */ - <1 RK_PA0 5 &pcfg_pull_none>, - /* acodec_dac_datal */ - <1 RK_PA7 5 &pcfg_pull_none>, - /* acodec_dac_datar */ - <1 RK_PB0 5 &pcfg_pull_none>, - /* acodec_dacclk */ - <1 RK_PA3 5 &pcfg_pull_none>, - /* acodec_dacsync */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - }; - - audiopwm { - /omit-if-no-ref/ - audiopwm_lout: audiopwm-lout { - rockchip,pins = - /* audiopwm_lout */ - <1 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutn: audiopwm-loutn { - rockchip,pins = - /* audiopwm_loutn */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_loutp: audiopwm-loutp { - rockchip,pins = - /* audiopwm_loutp */ - <1 RK_PA0 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_rout: audiopwm-rout { - rockchip,pins = - /* audiopwm_rout */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routn: audiopwm-routn { - rockchip,pins = - /* audiopwm_routn */ - <1 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - audiopwm_routp: audiopwm-routp { - rockchip,pins = - /* audiopwm_routp */ - <1 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - bt656 { - /omit-if-no-ref/ - bt656m0_pins: bt656m0-pins { - rockchip,pins = - /* bt656_clkm0 */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* bt656_d0m0 */ - <2 RK_PD0 2 &pcfg_pull_none>, - /* bt656_d1m0 */ - <2 RK_PD1 2 &pcfg_pull_none>, - /* bt656_d2m0 */ - <2 RK_PD2 2 &pcfg_pull_none>, - /* bt656_d3m0 */ - <2 RK_PD3 2 &pcfg_pull_none>, - /* bt656_d4m0 */ - <2 RK_PD4 2 &pcfg_pull_none>, - /* bt656_d5m0 */ - <2 RK_PD5 2 &pcfg_pull_none>, - /* bt656_d6m0 */ - <2 RK_PD6 2 &pcfg_pull_none>, - /* bt656_d7m0 */ - <2 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - bt656m1_pins: bt656m1-pins { - rockchip,pins = - /* bt656_clkm1 */ - <4 RK_PB4 5 &pcfg_pull_none>, - /* bt656_d0m1 */ - <3 RK_PC6 5 &pcfg_pull_none>, - /* bt656_d1m1 */ - <3 RK_PC7 5 &pcfg_pull_none>, - /* bt656_d2m1 */ - <3 RK_PD0 5 &pcfg_pull_none>, - /* bt656_d3m1 */ - <3 RK_PD1 5 &pcfg_pull_none>, - /* bt656_d4m1 */ - <3 RK_PD2 5 &pcfg_pull_none>, - /* bt656_d5m1 */ - <3 RK_PD3 5 &pcfg_pull_none>, - /* bt656_d6m1 */ - <3 RK_PD4 5 &pcfg_pull_none>, - /* bt656_d7m1 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clk */ - <3 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <3 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <3 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <3 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <3 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <3 RK_PB1 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <3 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <3 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <3 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <3 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <3 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <3 RK_PC1 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <3 RK_PC2 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - cam { - /omit-if-no-ref/ - cam_clkout0: cam-clkout0 { - rockchip,pins = - /* cam_clkout0 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cam_clkout1: cam-clkout1 { - rockchip,pins = - /* cam_clkout1 */ - <4 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rxm0 */ - <0 RK_PB4 2 &pcfg_pull_none>, - /* can0_txm0 */ - <0 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rxm1 */ - <2 RK_PA2 4 &pcfg_pull_none>, - /* can0_txm1 */ - <2 RK_PA1 4 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rxm0 */ - <1 RK_PA0 3 &pcfg_pull_none>, - /* can1_txm0 */ - <1 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rxm1 */ - <4 RK_PC2 3 &pcfg_pull_none>, - /* can1_txm1 */ - <4 RK_PC3 3 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rxm0 */ - <4 RK_PB4 3 &pcfg_pull_none>, - /* can2_txm0 */ - <4 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rxm1 */ - <2 RK_PB1 4 &pcfg_pull_none>, - /* can2_txm1 */ - <2 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PC1 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB6 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PD6 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PD7 1 &pcfg_pull_none>, - /* cif_d10 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d11 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d12 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d13 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d14 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d15 */ - <4 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d1 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d2 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d3 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d4 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d5 */ - <3 RK_PD3 1 &pcfg_pull_none>, - /* cif_d6 */ - <3 RK_PD4 1 &pcfg_pull_none>, - /* cif_d7 */ - <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_avs */ - <0 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - ebc { - /omit-if-no-ref/ - ebc_extern: ebc-extern { - rockchip,pins = - /* ebc_sdce1 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* ebc_sdce2 */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* ebc_sdce3 */ - <4 RK_PB1 2 &pcfg_pull_none>, - /* ebc_sdshr */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* ebc_vcom */ - <4 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - ebc_pins: ebc-pins { - rockchip,pins = - /* ebc_gdclk */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* ebc_gdoe */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* ebc_gdsp */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* ebc_sdce0 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* ebc_sdclk */ - <4 RK_PC1 2 &pcfg_pull_none>, - /* ebc_sddo0 */ - <3 RK_PC6 2 &pcfg_pull_none>, - /* ebc_sddo1 */ - <3 RK_PC7 2 &pcfg_pull_none>, - /* ebc_sddo2 */ - <3 RK_PD0 2 &pcfg_pull_none>, - /* ebc_sddo3 */ - <3 RK_PD1 2 &pcfg_pull_none>, - /* ebc_sddo4 */ - <3 RK_PD2 2 &pcfg_pull_none>, - /* ebc_sddo5 */ - <3 RK_PD3 2 &pcfg_pull_none>, - /* ebc_sddo6 */ - <3 RK_PD4 2 &pcfg_pull_none>, - /* ebc_sddo7 */ - <3 RK_PD5 2 &pcfg_pull_none>, - /* ebc_sddo8 */ - <3 RK_PD6 2 &pcfg_pull_none>, - /* ebc_sddo9 */ - <3 RK_PD7 2 &pcfg_pull_none>, - /* ebc_sddo10 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* ebc_sddo11 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* ebc_sddo12 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* ebc_sddo13 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* ebc_sddo14 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* ebc_sddo15 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* ebc_sdle */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* ebc_sdoe */ - <4 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - edpdp { - /omit-if-no-ref/ - edpdpm0_pins: edpdpm0-pins { - rockchip,pins = - /* edpdp_hpdinm0 */ - <4 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - edpdpm1_pins: edpdpm1-pins { - rockchip,pins = - /* edpdp_hpdinm1 */ - <0 RK_PC2 2 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_datastrobe: emmc-datastrobe { - rockchip,pins = - /* emmc_datastrobe */ - <1 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko25m */ - <2 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1m0_pins: eth1m0-pins { - rockchip,pins = - /* eth1_refclko25mm0 */ - <3 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - eth1m1_pins: eth1m1-pins { - rockchip,pins = - /* eth1_refclko25mm1 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - flash { - /omit-if-no-ref/ - flash_pins: flash-pins { - rockchip,pins = - /* flash_ale */ - <1 RK_PD0 2 &pcfg_pull_none>, - /* flash_cle */ - <1 RK_PC6 3 &pcfg_pull_none>, - /* flash_cs0n */ - <1 RK_PD3 2 &pcfg_pull_none>, - /* flash_cs1n */ - <1 RK_PD4 2 &pcfg_pull_none>, - /* flash_d0 */ - <1 RK_PB4 2 &pcfg_pull_none>, - /* flash_d1 */ - <1 RK_PB5 2 &pcfg_pull_none>, - /* flash_d2 */ - <1 RK_PB6 2 &pcfg_pull_none>, - /* flash_d3 */ - <1 RK_PB7 2 &pcfg_pull_none>, - /* flash_d4 */ - <1 RK_PC0 2 &pcfg_pull_none>, - /* flash_d5 */ - <1 RK_PC1 2 &pcfg_pull_none>, - /* flash_d6 */ - <1 RK_PC2 2 &pcfg_pull_none>, - /* flash_d7 */ - <1 RK_PC3 2 &pcfg_pull_none>, - /* flash_dqs */ - <1 RK_PC5 2 &pcfg_pull_none>, - /* flash_rdn */ - <1 RK_PD2 2 &pcfg_pull_none>, - /* flash_rdy */ - <1 RK_PD1 2 &pcfg_pull_none>, - /* flash_volsel */ - <0 RK_PA7 1 &pcfg_pull_none>, - /* flash_wpn */ - <1 RK_PC7 3 &pcfg_pull_none>, - /* flash_wrn */ - <1 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspi_pins: fspi-pins { - rockchip,pins = - /* fspi_clk */ - <1 RK_PD0 1 &pcfg_pull_none>, - /* fspi_cs0n */ - <1 RK_PD3 1 &pcfg_pull_none>, - /* fspi_d0 */ - <1 RK_PD1 1 &pcfg_pull_none>, - /* fspi_d1 */ - <1 RK_PD2 1 &pcfg_pull_none>, - /* fspi_d2 */ - <1 RK_PC7 2 &pcfg_pull_none>, - /* fspi_d3 */ - <1 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - fspi_cs1: fspi-cs1 { - rockchip,pins = - /* fspi_cs1n */ - <1 RK_PC6 2 &pcfg_pull_up>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <2 RK_PC3 2 &pcfg_pull_none>, - /* gmac0_mdio */ - <2 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <2 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_er: gmac0-rx-er { - rockchip,pins = - /* gmac0_rxer */ - <2 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PB7 2 &pcfg_pull_none>, - /* gmac0_rxdvcrs */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1m0_miim: gmac1m0-miim { - rockchip,pins = - /* gmac1_mdcm0 */ - <3 RK_PC4 3 &pcfg_pull_none>, - /* gmac1_mdiom0 */ - <3 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_clkinout: gmac1m0-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm0 */ - <3 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_er: gmac1m0-rx-er { - rockchip,pins = - /* gmac1_rxerm0 */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rx_bus2: gmac1m0-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m0 */ - <3 RK_PB1 3 &pcfg_pull_none>, - /* gmac1_rxd1m0 */ - <3 RK_PB2 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm0 */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2: gmac1m0-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_miim: gmac1m1-miim { - rockchip,pins = - /* gmac1_mdcm1 */ - <4 RK_PB6 3 &pcfg_pull_none>, - /* gmac1_mdiom1 */ - <4 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_clkinout: gmac1m1-clkinout { - rockchip,pins = - /* gmac1_mclkinoutm1 */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_er: gmac1m1-rx-er { - rockchip,pins = - /* gmac1_rxerm1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rx_bus2: gmac1m1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0m1 */ - <4 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_rxd1m1 */ - <4 RK_PB0 3 &pcfg_pull_none>, - /* gmac1_rxdvcrsm1 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2: gmac1m1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC0 2 &pcfg_pull_none>, - /* gpu_pwren */ - <0 RK_PA6 4 &pcfg_pull_none>; - }; - }; - - hdmitx { - /omit-if-no-ref/ - hdmitxm0_cec: hdmitxm0-cec { - rockchip,pins = - /* hdmitxm0_cec */ - <4 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitxm1_cec: hdmitxm1-cec { - rockchip,pins = - /* hdmitxm1_cec */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_scl: hdmitx-scl { - rockchip,pins = - /* hdmitx_scl */ - <4 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmitx_sda: hdmitx-sda { - rockchip,pins = - /* hdmitx_sda */ - <4 RK_PD0 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0_xfer: i2c0-xfer { - rockchip,pins = - /* i2c0_scl */ - <0 RK_PB1 1 &pcfg_pull_none_smt>, - /* i2c0_sda */ - <0 RK_PB2 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1_xfer: i2c1-xfer { - rockchip,pins = - /* i2c1_scl */ - <0 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c1_sda */ - <0 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_sclm0 */ - <0 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam0 */ - <0 RK_PB6 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_sclm1 */ - <4 RK_PB5 1 &pcfg_pull_none_smt>, - /* i2c2_sdam1 */ - <4 RK_PB4 1 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_sclm0 */ - <1 RK_PA1 1 &pcfg_pull_none_smt>, - /* i2c3_sdam0 */ - <1 RK_PA0 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_sclm1 */ - <3 RK_PB5 4 &pcfg_pull_none_smt>, - /* i2c3_sdam1 */ - <3 RK_PB6 4 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_sclm0 */ - <4 RK_PB3 1 &pcfg_pull_none_smt>, - /* i2c4_sdam0 */ - <4 RK_PB2 1 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_sclm1 */ - <2 RK_PB2 2 &pcfg_pull_none_smt>, - /* i2c4_sdam1 */ - <2 RK_PB1 2 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_sclm0 */ - <3 RK_PB3 4 &pcfg_pull_none_smt>, - /* i2c5_sdam0 */ - <3 RK_PB4 4 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_sclm1 */ - <4 RK_PC7 2 &pcfg_pull_none_smt>, - /* i2c5_sdam1 */ - <4 RK_PD0 2 &pcfg_pull_none_smt>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrckrx: i2s1m0-lrckrx { - rockchip,pins = - /* i2s1m0_lrckrx */ - <1 RK_PA6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_lrcktx: i2s1m0-lrcktx { - rockchip,pins = - /* i2s1m0_lrcktx */ - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclkrx: i2s1m0-sclkrx { - rockchip,pins = - /* i2s1m0_sclkrx */ - <1 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclktx: i2s1m0-sclktx { - rockchip,pins = - /* i2s1m0_sclktx */ - <1 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <1 RK_PA7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <1 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrckrx: i2s1m1-lrckrx { - rockchip,pins = - /* i2s1m1_lrckrx */ - <4 RK_PA7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_lrcktx: i2s1m1-lrcktx { - rockchip,pins = - /* i2s1m1_lrcktx */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <3 RK_PC6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclkrx: i2s1m1-sclkrx { - rockchip,pins = - /* i2s1m1_sclkrx */ - <4 RK_PA6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclktx: i2s1m1-sclktx { - rockchip,pins = - /* i2s1m1_sclktx */ - <3 RK_PC7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <3 RK_PD2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <3 RK_PD4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <3 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <4 RK_PB0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrckrx: i2s1m2-lrckrx { - rockchip,pins = - /* i2s1m2_lrckrx */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_lrcktx: i2s1m2-lrcktx { - rockchip,pins = - /* i2s1m2_lrcktx */ - <2 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_mclk: i2s1m2-mclk { - rockchip,pins = - /* i2s1m2_mclk */ - <2 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclkrx: i2s1m2-sclkrx { - rockchip,pins = - /* i2s1m2_sclkrx */ - <3 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sclktx: i2s1m2-sclktx { - rockchip,pins = - /* i2s1m2_sclktx */ - <2 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi0: i2s1m2-sdi0 { - rockchip,pins = - /* i2s1m2_sdi0 */ - <2 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi1: i2s1m2-sdi1 { - rockchip,pins = - /* i2s1m2_sdi1 */ - <2 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi2: i2s1m2-sdi2 { - rockchip,pins = - /* i2s1m2_sdi2 */ - <2 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdi3: i2s1m2-sdi3 { - rockchip,pins = - /* i2s1m2_sdi3 */ - <2 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo0: i2s1m2-sdo0 { - rockchip,pins = - /* i2s1m2_sdo0 */ - <2 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo1: i2s1m2-sdo1 { - rockchip,pins = - /* i2s1m2_sdo1 */ - <3 RK_PA0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo2: i2s1m2-sdo2 { - rockchip,pins = - /* i2s1m2_sdo2 */ - <3 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m2_sdo3: i2s1m2-sdo3 { - rockchip,pins = - /* i2s1m2_sdo3 */ - <3 RK_PC2 5 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrckrx: i2s2m0-lrckrx { - rockchip,pins = - /* i2s2m0_lrckrx */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_lrcktx: i2s2m0-lrcktx { - rockchip,pins = - /* i2s2m0_lrcktx */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclkrx: i2s2m0-sclkrx { - rockchip,pins = - /* i2s2m0_sclkrx */ - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclktx: i2s2m0-sclktx { - rockchip,pins = - /* i2s2m0_sclktx */ - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrckrx: i2s2m1-lrckrx { - rockchip,pins = - /* i2s2m1_lrckrx */ - <4 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrcktx: i2s2m1-lrcktx { - rockchip,pins = - /* i2s2m1_lrcktx */ - <4 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclkrx: i2s2m1-sclkrx { - rockchip,pins = - /* i2s2m1_sclkrx */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclktx: i2s2m1-sclktx { - rockchip,pins = - /* i2s2m1_sclktx */ - <4 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <4 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <4 RK_PB3 5 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3m0_lrck: i2s3m0-lrck { - rockchip,pins = - /* i2s3m0_lrck */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_mclk: i2s3m0-mclk { - rockchip,pins = - /* i2s3m0_mclk */ - <3 RK_PA2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sclk: i2s3m0-sclk { - rockchip,pins = - /* i2s3m0_sclk */ - <3 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdi: i2s3m0-sdi { - rockchip,pins = - /* i2s3m0_sdi */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m0_sdo: i2s3m0-sdo { - rockchip,pins = - /* i2s3m0_sdo */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_lrck: i2s3m1-lrck { - rockchip,pins = - /* i2s3m1_lrck */ - <4 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_mclk: i2s3m1-mclk { - rockchip,pins = - /* i2s3m1_mclk */ - <4 RK_PC2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sclk: i2s3m1-sclk { - rockchip,pins = - /* i2s3m1_sclk */ - <4 RK_PC3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdi: i2s3m1-sdi { - rockchip,pins = - /* i2s3m1_sdi */ - <4 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3m1_sdo: i2s3m1-sdo { - rockchip,pins = - /* i2s3m1_sdo */ - <4 RK_PC5 5 &pcfg_pull_none>; - }; - }; - - isp { - /omit-if-no-ref/ - isp_pins: isp-pins { - rockchip,pins = - /* isp_flashtrigin */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* isp_flashtrigout */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* isp_prelighttrig */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtag_pins: jtag-pins { - rockchip,pins = - /* jtag_tck */ - <1 RK_PD7 2 &pcfg_pull_none>, - /* jtag_tms */ - <2 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - lcdc { - /omit-if-no-ref/ - lcdc_ctl: lcdc-ctl { - rockchip,pins = - /* lcdc_clk */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* lcdc_d0 */ - <2 RK_PD0 1 &pcfg_pull_none>, - /* lcdc_d1 */ - <2 RK_PD1 1 &pcfg_pull_none>, - /* lcdc_d2 */ - <2 RK_PD2 1 &pcfg_pull_none>, - /* lcdc_d3 */ - <2 RK_PD3 1 &pcfg_pull_none>, - /* lcdc_d4 */ - <2 RK_PD4 1 &pcfg_pull_none>, - /* lcdc_d5 */ - <2 RK_PD5 1 &pcfg_pull_none>, - /* lcdc_d6 */ - <2 RK_PD6 1 &pcfg_pull_none>, - /* lcdc_d7 */ - <2 RK_PD7 1 &pcfg_pull_none>, - /* lcdc_d8 */ - <3 RK_PA1 1 &pcfg_pull_none>, - /* lcdc_d9 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PA4 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* lcdc_d16 */ - <3 RK_PB1 1 &pcfg_pull_none>, - /* lcdc_d17 */ - <3 RK_PB2 1 &pcfg_pull_none>, - /* lcdc_d18 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* lcdc_d19 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* lcdc_d20 */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* lcdc_d21 */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* lcdc_d22 */ - <3 RK_PB7 1 &pcfg_pull_none>, - /* lcdc_d23 */ - <3 RK_PC0 1 &pcfg_pull_none>, - /* lcdc_den */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_hsync */ - <3 RK_PC1 1 &pcfg_pull_none>, - /* lcdc_vsync */ - <3 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcu_pins: mcu-pins { - rockchip,pins = - /* mcu_jtagtck */ - <0 RK_PB4 4 &pcfg_pull_none>, - /* mcu_jtagtdi */ - <0 RK_PC1 4 &pcfg_pull_none>, - /* mcu_jtagtdo */ - <0 RK_PB3 4 &pcfg_pull_none>, - /* mcu_jtagtms */ - <0 RK_PC2 4 &pcfg_pull_none>, - /* mcu_jtagtrstn */ - <0 RK_PC3 4 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - pcie20 { - /omit-if-no-ref/ - pcie20m0_pins: pcie20m0-pins { - rockchip,pins = - /* pcie20_clkreqnm0 */ - <0 RK_PA5 3 &pcfg_pull_none>, - /* pcie20_perstnm0 */ - <0 RK_PB6 3 &pcfg_pull_none>, - /* pcie20_wakenm0 */ - <0 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m1_pins: pcie20m1-pins { - rockchip,pins = - /* pcie20_clkreqnm1 */ - <2 RK_PD0 4 &pcfg_pull_none>, - /* pcie20_perstnm1 */ - <3 RK_PC1 4 &pcfg_pull_none>, - /* pcie20_wakenm1 */ - <2 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20m2_pins: pcie20m2-pins { - rockchip,pins = - /* pcie20_clkreqnm2 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie20_perstnm2 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie20_wakenm2 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20_buttonrstn: pcie20-buttonrstn { - rockchip,pins = - /* pcie20_buttonrstn */ - <0 RK_PB4 3 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_clkreqnm0 */ - <0 RK_PA4 3 &pcfg_pull_none>, - /* pcie30x1_perstnm0 */ - <0 RK_PC3 3 &pcfg_pull_none>, - /* pcie30x1_wakenm0 */ - <0 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_clkreqnm1 */ - <2 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x1_perstnm1 */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* pcie30x1_wakenm1 */ - <2 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_clkreqnm2 */ - <1 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_perstnm2 */ - <1 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_wakenm2 */ - <1 RK_PA3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_buttonrstn: pcie30x1-buttonrstn { - rockchip,pins = - /* pcie30x1_buttonrstn */ - <0 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqnm0 */ - <0 RK_PA6 2 &pcfg_pull_none>, - /* pcie30x2_perstnm0 */ - <0 RK_PC6 3 &pcfg_pull_none>, - /* pcie30x2_wakenm0 */ - <0 RK_PC5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqnm1 */ - <2 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_perstnm1 */ - <2 RK_PD6 4 &pcfg_pull_none>, - /* pcie30x2_wakenm1 */ - <2 RK_PD5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqnm2 */ - <4 RK_PC2 4 &pcfg_pull_none>, - /* pcie30x2_perstnm2 */ - <4 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x2_wakenm2 */ - <4 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_buttonrstn: pcie30x2-buttonrstn { - rockchip,pins = - /* pcie30x2_buttonrstn */ - <0 RK_PB0 3 &pcfg_pull_none>; - }; - }; - - pdm { - /omit-if-no-ref/ - pdmm0_clk: pdmm0-clk { - rockchip,pins = - /* pdm_clk0m0 */ - <1 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_clk1: pdmm0-clk1 { - rockchip,pins = - /* pdmm0_clk1 */ - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi0: pdmm0-sdi0 { - rockchip,pins = - /* pdmm0_sdi0 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi1: pdmm0-sdi1 { - rockchip,pins = - /* pdmm0_sdi1 */ - <1 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi2: pdmm0-sdi2 { - rockchip,pins = - /* pdmm0_sdi2 */ - <1 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm0_sdi3: pdmm0-sdi3 { - rockchip,pins = - /* pdmm0_sdi3 */ - <1 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk: pdmm1-clk { - rockchip,pins = - /* pdm_clk0m1 */ - <3 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_clk1: pdmm1-clk1 { - rockchip,pins = - /* pdmm1_clk1 */ - <4 RK_PA0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi0: pdmm1-sdi0 { - rockchip,pins = - /* pdmm1_sdi0 */ - <3 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi1: pdmm1-sdi1 { - rockchip,pins = - /* pdmm1_sdi1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi2: pdmm1-sdi2 { - rockchip,pins = - /* pdmm1_sdi2 */ - <4 RK_PA2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm1_sdi3: pdmm1-sdi3 { - rockchip,pins = - /* pdmm1_sdi3 */ - <4 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_clk1: pdmm2-clk1 { - rockchip,pins = - /* pdmm2_clk1 */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi0: pdmm2-sdi0 { - rockchip,pins = - /* pdmm2_sdi0 */ - <3 RK_PB3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi1: pdmm2-sdi1 { - rockchip,pins = - /* pdmm2_sdi1 */ - <3 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi2: pdmm2-sdi2 { - rockchip,pins = - /* pdmm2_sdi2 */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdmm2_sdi3: pdmm2-sdi3 { - rockchip,pins = - /* pdmm2_sdi3 */ - <3 RK_PC0 5 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_sleep */ - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug0 */ - <0 RK_PA5 4 &pcfg_pull_none>, - /* pmu_debug1 */ - <0 RK_PA6 3 &pcfg_pull_none>, - /* pmu_debug2 */ - <0 RK_PC4 4 &pcfg_pull_none>, - /* pmu_debug3 */ - <0 RK_PC5 4 &pcfg_pull_none>, - /* pmu_debug4 */ - <0 RK_PC6 4 &pcfg_pull_none>, - /* pmu_debug5 */ - <0 RK_PC7 4 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <0 RK_PB5 4 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <0 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3_pins: pwm3-pins { - rockchip,pins = - /* pwm3_ir */ - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4_pins: pwm4-pins { - rockchip,pins = - /* pwm4 */ - <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5_pins: pwm5-pins { - rockchip,pins = - /* pwm5 */ - <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6_pins: pwm6-pins { - rockchip,pins = - /* pwm6 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7_pins: pwm7-pins { - rockchip,pins = - /* pwm7_ir */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PB1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <1 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <1 RK_PD6 4 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <2 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_irm0 */ - <3 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_irm1 */ - <4 RK_PC0 3 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_irm0 */ - <3 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_irm1 */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_ou */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cpdet */ - <0 RK_PA4 2 &pcfg_pull_none>, - /* sata_cppod */ - <0 RK_PA6 1 &pcfg_pull_none>, - /* sata_mpswitch */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0_pins: sata0-pins { - rockchip,pins = - /* sata0_actled */ - <4 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1_pins: sata1-pins { - rockchip,pins = - /* sata1_actled */ - <4 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2_pins: sata2-pins { - rockchip,pins = - /* sata2_actled */ - <4 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - scr { - /omit-if-no-ref/ - scr_pins: scr-pins { - rockchip,pins = - /* scr_clk */ - <1 RK_PA2 3 &pcfg_pull_none>, - /* scr_det */ - <1 RK_PA7 3 &pcfg_pull_up>, - /* scr_io */ - <1 RK_PA3 3 &pcfg_pull_up>, - /* scr_rst */ - <1 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - sdmmc0 { - /omit-if-no-ref/ - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - /* sdmmc0_d0 */ - <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d1 */ - <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d2 */ - <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc0_d3 */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - /* sdmmc0_clk */ - <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - /* sdmmc0_cmd */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc0_det: sdmmc0-det { - rockchip,pins = - /* sdmmc0_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc0_pwren: sdmmc0-pwren { - rockchip,pins = - /* sdmmc0_pwren */ - <0 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - sdmmc1 { - /omit-if-no-ref/ - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - /* sdmmc1_d0 */ - <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d1 */ - <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d2 */ - <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc1_d3 */ - <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - /* sdmmc1_clk */ - <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - /* sdmmc1_cmd */ - <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc1_det: sdmmc1-det { - rockchip,pins = - /* sdmmc1_det */ - <2 RK_PB2 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc1_pwren: sdmmc1-pwren { - rockchip,pins = - /* sdmmc1_pwren */ - <2 RK_PB1 1 &pcfg_pull_none>; - }; - }; - - sdmmc2 { - /omit-if-no-ref/ - sdmmc2m0_bus4: sdmmc2m0-bus4 { - rockchip,pins = - /* sdmmc2_d0m0 */ - <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m0 */ - <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m0 */ - <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m0 */ - <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_clk: sdmmc2m0-clk { - rockchip,pins = - /* sdmmc2_clkm0 */ - <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_cmd: sdmmc2m0-cmd { - rockchip,pins = - /* sdmmc2_cmdm0 */ - <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m0_det: sdmmc2m0-det { - rockchip,pins = - /* sdmmc2_detm0 */ - <3 RK_PD4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m0_pwren: sdmmc2m0-pwren { - rockchip,pins = - /* sdmmc2m0_pwren */ - <3 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sdmmc2m1_bus4: sdmmc2m1-bus4 { - rockchip,pins = - /* sdmmc2_d0m1 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d1m1 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d2m1 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, - /* sdmmc2_d3m1 */ - <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_clk: sdmmc2m1-clk { - rockchip,pins = - /* sdmmc2_clkm1 */ - <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_cmd: sdmmc2m1-cmd { - rockchip,pins = - /* sdmmc2_cmdm1 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc2m1_det: sdmmc2m1-det { - rockchip,pins = - /* sdmmc2_detm1 */ - <3 RK_PA7 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc2m1_pwren: sdmmc2m1-pwren { - rockchip,pins = - /* sdmmc2m1_pwren */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - }; - - spdif { - /omit-if-no-ref/ - spdifm0_tx: spdifm0-tx { - rockchip,pins = - /* spdifm0_tx */ - <1 RK_PA4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm1_tx: spdifm1-tx { - rockchip,pins = - /* spdifm1_tx */ - <3 RK_PC5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdifm2_tx: spdifm2-tx { - rockchip,pins = - /* spdifm2_tx */ - <4 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_none>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_none>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_none>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_none>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_none>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_none>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_none>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_none>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_none>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_none>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_none>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_none>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_none>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_none>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_none>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm0_shut: tsadcm0-shut { - rockchip,pins = - /* tsadcm0_shut */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shutorg: tsadc-shutorg { - rockchip,pins = - /* tsadc_shutorg */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0_xfer: uart0-xfer { - rockchip,pins = - /* uart0_rx */ - <0 RK_PC0 3 &pcfg_pull_up>, - /* uart0_tx */ - <0 RK_PC1 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PC7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rxm0 */ - <2 RK_PB3 2 &pcfg_pull_up>, - /* uart1_txm0 */ - <2 RK_PB4 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PB5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rxm1 */ - <3 RK_PD7 4 &pcfg_pull_up>, - /* uart1_txm1 */ - <3 RK_PD6 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <4 RK_PC1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <4 RK_PB6 4 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rxm0 */ - <0 RK_PD0 1 &pcfg_pull_up>, - /* uart2_txm0 */ - <0 RK_PD1 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rxm1 */ - <1 RK_PD6 2 &pcfg_pull_up>, - /* uart2_txm1 */ - <1 RK_PD5 2 &pcfg_pull_up>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rxm0 */ - <1 RK_PA0 2 &pcfg_pull_up>, - /* uart3_txm0 */ - <1 RK_PA1 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m0_ctsn: uart3m0-ctsn { - rockchip,pins = - /* uart3m0_ctsn */ - <1 RK_PA3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m0_rtsn: uart3m0-rtsn { - rockchip,pins = - /* uart3m0_rtsn */ - <1 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rxm1 */ - <3 RK_PC0 4 &pcfg_pull_up>, - /* uart3_txm1 */ - <3 RK_PB7 4 &pcfg_pull_up>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rxm0 */ - <1 RK_PA4 2 &pcfg_pull_up>, - /* uart4_txm0 */ - <1 RK_PA6 2 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m0_ctsn: uart4m0-ctsn { - rockchip,pins = - /* uart4m0_ctsn */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m0_rtsn: uart4m0-rtsn { - rockchip,pins = - /* uart4m0_rtsn */ - <1 RK_PA5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rxm1 */ - <3 RK_PB1 4 &pcfg_pull_up>, - /* uart4_txm1 */ - <3 RK_PB2 4 &pcfg_pull_up>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rxm0 */ - <2 RK_PA1 3 &pcfg_pull_up>, - /* uart5_txm0 */ - <2 RK_PA2 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <1 RK_PD7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <2 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rxm1 */ - <3 RK_PC3 4 &pcfg_pull_up>, - /* uart5_txm1 */ - <3 RK_PC2 4 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rxm0 */ - <2 RK_PA3 3 &pcfg_pull_up>, - /* uart6_txm0 */ - <2 RK_PA4 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rxm1 */ - <1 RK_PD6 3 &pcfg_pull_up>, - /* uart6_txm1 */ - <1 RK_PD5 3 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rxm0 */ - <2 RK_PA5 3 &pcfg_pull_up>, - /* uart7_txm0 */ - <2 RK_PA6 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <2 RK_PC2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <2 RK_PC1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rxm1 */ - <3 RK_PC5 4 &pcfg_pull_up>, - /* uart7_txm1 */ - <3 RK_PC4 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rxm2 */ - <4 RK_PA3 4 &pcfg_pull_up>, - /* uart7_txm2 */ - <4 RK_PA2 4 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rxm0 */ - <2 RK_PC6 2 &pcfg_pull_up>, - /* uart8_txm0 */ - <2 RK_PC5 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <2 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <2 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rxm1 */ - <3 RK_PA0 4 &pcfg_pull_up>, - /* uart8_txm1 */ - <2 RK_PD7 4 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rxm0 */ - <2 RK_PA7 3 &pcfg_pull_up>, - /* uart9_txm0 */ - <2 RK_PB0 3 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <2 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <2 RK_PC3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rxm1 */ - <4 RK_PC6 4 &pcfg_pull_up>, - /* uart9_txm1 */ - <4 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rxm2 */ - <4 RK_PA5 4 &pcfg_pull_up>, - /* uart9_txm2 */ - <4 RK_PA4 4 &pcfg_pull_up>; - }; - }; - - vop { - /omit-if-no-ref/ - vopm0_pins: vopm0-pins { - rockchip,pins = - /* vop_pwmm0 */ - <0 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - vopm1_pins: vopm1-pins { - rockchip,pins = - /* vop_pwmm1 */ - <3 RK_PC4 2 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - spi0-hs { - /omit-if-no-ref/ - spi0m0_pins_hs: spi0m0-pins { - rockchip,pins = - /* spi0_clkm0 */ - <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_misom0 */ - <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim0 */ - <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0_hs: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0m0 */ - <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1_hs: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1m0 */ - <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_pins_hs: spi0m1-pins { - rockchip,pins = - /* spi0_clkm1 */ - <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, - /* spi0_misom1 */ - <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, - /* spi0_mosim1 */ - <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0_hs: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0m1 */ - <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1-hs { - /omit-if-no-ref/ - spi1m0_pins_hs: spi1m0-pins { - rockchip,pins = - /* spi1_clkm0 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom0 */ - <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim0 */ - <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0_hs: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0m0 */ - <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1_hs: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1m0 */ - <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_pins_hs: spi1m1-pins { - rockchip,pins = - /* spi1_clkm1 */ - <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, - /* spi1_misom1 */ - <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, - /* spi1_mosim1 */ - <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0_hs: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0m1 */ - <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2-hs { - /omit-if-no-ref/ - spi2m0_pins_hs: spi2m0-pins { - rockchip,pins = - /* spi2_clkm0 */ - <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, - /* spi2_misom0 */ - <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim0 */ - <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0_hs: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0m0 */ - <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1_hs: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1m0 */ - <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins_hs: spi2m1-pins { - rockchip,pins = - /* spi2_clkm1 */ - <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, - /* spi2_misom1 */ - <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, - /* spi2_mosim1 */ - <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0_hs: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0m1 */ - <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1_hs: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1m1 */ - <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3-hs { - /omit-if-no-ref/ - spi3m0_pins_hs: spi3m0-pins { - rockchip,pins = - /* spi3_clkm0 */ - <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, - /* spi3_misom0 */ - <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim0 */ - <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0_hs: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0m0 */ - <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1_hs: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1m0 */ - <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_pins_hs: spi3m1-pins { - rockchip,pins = - /* spi3_clkm1 */ - <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, - /* spi3_misom1 */ - <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, - /* spi3_mosim1 */ - <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0_hs: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0m1 */ - <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1_hs: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1m1 */ - <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; - }; - }; - - gmac-txd-level3 { - /omit-if-no-ref/ - gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd1 */ - <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, - /* gmac0_txen */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA3 2 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, - /* gmac0_txd3 */ - <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m0 */ - <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m0 */ - <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm0 */ - <3 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m0 */ - <3 RK_PA4 3 &pcfg_pull_none>, - /* gmac1_rxd3m0 */ - <3 RK_PA5 3 &pcfg_pull_none>, - /* gmac1_txd2m0 */ - <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m0 */ - <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; - }; - - /omit-if-no-ref/ - gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { - rockchip,pins = - /* gmac1_txd0m1 */ - <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd1m1 */ - <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txenm1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { - rockchip,pins = - /* gmac1_rxd2m1 */ - <4 RK_PA1 3 &pcfg_pull_none>, - /* gmac1_rxd3m1 */ - <4 RK_PA2 3 &pcfg_pull_none>, - /* gmac1_txd2m1 */ - <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, - /* gmac1_txd3m1 */ - <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; - }; - }; - - gmac-txc-level2 { - /omit-if-no-ref/ - gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm0 */ - <3 RK_PA7 3 &pcfg_pull_none>, - /* gmac1_txclkm0 */ - <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; - }; - - /omit-if-no-ref/ - gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { - rockchip,pins = - /* gmac1_rxclkm1 */ - <4 RK_PA3 3 &pcfg_pull_none>, - /* gmac1_txclkm1 */ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadc_pin: tsadc-pin { - rockchip,pins = - /* tsadc_pin */ - <0 RK_PA1 0 &pcfg_pull_none>; - }; - }; - - lcdc { - /omit-if-no-ref/ - lcdc_clock: lcdc-clock { - rockchip,pins = - /* lcdc_clk */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* lcdc_den */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_hsync */ - <3 RK_PC1 1 &pcfg_pull_none>, - /* lcdc_vsync */ - <3 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - lcdc_data16: lcdc-data16 { - rockchip,pins = - /* lcdc_d3 */ - <2 RK_PD3 1 &pcfg_pull_none>, - /* lcdc_d4 */ - <2 RK_PD4 1 &pcfg_pull_none>, - /* lcdc_d5 */ - <2 RK_PD5 1 &pcfg_pull_none>, - /* lcdc_d6 */ - <2 RK_PD6 1 &pcfg_pull_none>, - /* lcdc_d7 */ - <2 RK_PD7 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PA4 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* lcdc_d19 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* lcdc_d20 */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* lcdc_d21 */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* lcdc_d22 */ - <3 RK_PB7 1 &pcfg_pull_none>, - /* lcdc_d23 */ - <3 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - lcdc_data18: lcdc-data18 { - rockchip,pins = - /* lcdc_d2 */ - <2 RK_PD2 1 &pcfg_pull_none>, - /* lcdc_d3 */ - <2 RK_PD3 1 &pcfg_pull_none>, - /* lcdc_d4 */ - <2 RK_PD4 1 &pcfg_pull_none>, - /* lcdc_d5 */ - <2 RK_PD5 1 &pcfg_pull_none>, - /* lcdc_d6 */ - <2 RK_PD6 1 &pcfg_pull_none>, - /* lcdc_d7 */ - <2 RK_PD7 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PA4 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PA6 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* lcdc_d18 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* lcdc_d19 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* lcdc_d20 */ - <3 RK_PB5 1 &pcfg_pull_none>, - /* lcdc_d21 */ - <3 RK_PB6 1 &pcfg_pull_none>, - /* lcdc_d22 */ - <3 RK_PB7 1 &pcfg_pull_none>, - /* lcdc_d23 */ - <3 RK_PC0 1 &pcfg_pull_none>; - }; - }; - -}; diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi deleted file mode 100644 index 45b03dcbbad455d5c02d62bbbd09eb1d5f2e4e2f..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-radxa-cm3i.dtsi +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include "rk3568.dtsi" - -/ { - compatible = "radxa,cm3i", "rockchip,rk3568"; - - aliases { - mmc0 = &sdhci; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led_user: led-0 { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; - }; - - pcie30_avdd0v9: pcie30-avdd0v9-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v_input>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v_input>; - }; - - /* labeled +5v_input in schematic */ - vcc5v_input: vcc5v-input-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v_input"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&display_subsystem { - status = "disabled"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v_input>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - wakeup-source; - - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&pinctrl { - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; -}; diff --git a/arch/arm/dts/rk3568-radxa-e25.dts b/arch/arm/dts/rk3568-radxa-e25.dts deleted file mode 100644 index 72ad74c38a2b40f5f8cde02b9f4bc740b321aff8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-radxa-e25.dts +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include "rk3568-radxa-cm3i.dtsi" - -/ { - model = "Radxa E25 Carrier Board"; - compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568"; - - aliases { - mmc1 = &sdmmc0; - }; - - pwm-leds { - compatible = "pwm-leds-multicolor"; - - multi-led { - color = ; - max-brightness = <255>; - - led-red { - color = ; - pwms = <&pwm1 0 1000000 0>; - }; - - led-green { - color = ; - pwms = <&pwm2 0 1000000 0>; - }; - - led-blue { - color = ; - pwms = <&pwm12 0 1000000 0>; - }; - }; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vbus_typec_en>; - regulator-name = "vbus_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* actually fed by vcc5v0_sys, dependent - * on pi6c clock generator - */ - vcc3v3_minipcie: vcc3v3-minipcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_enable_h>; - regulator-name = "vcc3v3_minipcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_pi6c_05>; - }; - - vcc3v3_ngff: vcc3v3-ngff-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ngffpcie_enable_h>; - regulator-name = "vcc3v3_ngff"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1_enable_h>; - regulator-name = "vcc3v3_pcie30x1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy1 { - phy-supply = <&vcc3v3_pcie30x1>; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie20_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; - -&pcie30phy { - data-lanes = <1 2>; - status = "okay"; -}; - -&pcie3x1 { - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1m0_pins>; - reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_minipcie>; - status = "okay"; -}; - -&pcie3x2 { - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; - -&pinctrl { - pcie { - pcie20_reset_h: pcie20-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie30x1_enable_h: pcie30x1-enable-h { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie30x2_reset_h: pcie30x2-reset-h { - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - minipcie_enable_h: minipcie-enable-h { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - ngffpcie_enable_h: ngffpcie-enable-h { - rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vbus_typec_en: vbus_typec_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm12 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - /* Also used in pcie30x1_clkreqnm0 */ - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vbus_typec>; - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc3v3_minipcie>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc3v3_ngff>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts deleted file mode 100644 index a5e974ea659e2eb274d5ee65ebbecc61300db164..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ /dev/null @@ -1,859 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include -#include -#include -#include -#include "rk3568.dtsi" - -/ { - model = "Radxa ROCK3 Model A"; - compatible = "radxa,rock3a", "rockchip,rk3568"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc2; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - leds { - compatible = "gpio-leds"; - - led_user: led-0 { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; - }; - - rk809-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "Analog RK809"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk809>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable>; - post-power-on-delay-ms = <100>; - power-off-delay-us = <5000000>; - reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - }; - - pcie30_avdd0v9: pcie30-avdd0v9-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - - /* pi6c pcie clock generator */ - vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pi6c_03"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_hub_en>; - regulator-name = "vcc5v0_usb_hub"; - regulator-always-on; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc_cam: vcc-cam-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam_en>; - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_mipi: vcc-mipi-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_mipi_en>; - regulator-name = "vcc_mipi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; - clock_in_out = "input"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; - phy-supply = <&vcc_3v3>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_clkinout - &gmac1m1_rgmii_bus>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - #clock-cells = <1>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - codec { - mic-in-differential; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m1_xfer>; - status = "disabled"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "disabled"; -}; - -&i2c5 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&i2s2_2ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pcie30phy { - phy-supply = <&vcc3v3_pi6c_03>; - status = "okay"; -}; - -&pcie3x2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2m1_pins>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&pinctrl { - cam { - vcc_cam_en: vcc_cam_en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - display { - vcc_mipi_en: vcc_mipi_en { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ethernet { - eth_phy_rst: eth_phy_rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_user_en: led_user_en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_enable_h: pcie-enable-h { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0_usb_host_en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - bt { - bt_enable: bt-enable { - rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake: bt-host-wake { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bt_wake: bt-wake { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable: wifi-enable { - rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - sd-uhs-sdr50; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc2 { - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sys>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6e8307e3bdf60a6b8afd48275ccc637394c505c0 --- /dev/null +++ b/arch/arm/dts/rk3568-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi deleted file mode 100644 index f1be76a54ceb0cb0730f444c69c3da73e07194c9..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3568.dtsi +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "rk356x.dtsi" - -/ { - compatible = "rockchip,rk3568"; - - sata0: sata@fc000000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc000000 0 0x1000>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, - <&cru CLK_SATA0_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - qos_pcie3x1: qos@fe190080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190080 0x0 0x20>; - }; - - qos_pcie3x2: qos@fe190100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190100 0x0 0x20>; - }; - - qos_sata0: qos@fe190200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190200 0x0 0x20>; - }; - - pcie30_phy_grf: syscon@fdcb8000 { - compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfdcb8000 0x0 0x10000>; - }; - - pcie30phy: phy@fe8c0000 { - compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, - <&cru PCLK_PCIE30PHY>; - clock-names = "refclk_m", "refclk_n", "pclk"; - resets = <&cru SRST_PCIE30PHY>; - reset-names = "phy"; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; - - pcie3x1: pcie@fe270000 { - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, - <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, - <0 0 0 2 &pcie3x1_intc 1>, - <0 0 0 3 &pcie3x1_intc 2>, - <0 0 0 4 &pcie3x1_intc 3>; - linux,pci-domain = <1>; - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; - msi-map = <0x0 &gic 0x1000 0x1000>; - num-lanes = <1>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - reg = <0x3 0xc0400000 0x0 0x00400000>, - <0x0 0xfe270000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE30X1_POWERUP>; - reset-names = "pipe"; - /* bifurcation; lane1 when using 1+1 */ - status = "disabled"; - - pcie3x1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, - <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <2>; - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <3>; - msi-map = <0x0 &gic 0x2000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - reg = <0x3 0xc0800000 0x0 0x00400000>, - <0x0 0xfe280000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE30X2_POWERUP>; - reset-names = "pipe"; - /* bifurcation; lane0 when using 1+1 */ - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - combphy0: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, - <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY0>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - #phy-cells = <1>; - status = "disabled"; - }; -}; - -&cpu0_opp_table { - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; -}; - -&pipegrf { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; -}; - -&power { - power-domain@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_pcie3x1>, - <&qos_pcie3x2>, - <&qos_sata0>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - #power-domain-cells = <0>; - }; -}; - -&usb_host0_xhci { - phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; -}; - -&vop { - compatible = "rockchip,rk3568-vop"; -}; diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi deleted file mode 100644 index c19c0f1b3778fe79f68d3657cb2b6512f70913f2..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk356x.dtsi +++ /dev/null @@ -1,1886 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1150000>; - clock-latency-ns = <40000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1150000>; - opp-suspend; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <975000 975000 1150000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1050000 1050000 1150000>; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - }; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <825000>; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <825000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <825000>; - }; - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - }; - }; - - hdmi_sound: hdmi-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "HDMI"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - status = "disabled"; - - simple-audio-card,codec { - sound-dai = <&hdmi>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - pinctrl-0 = <&clk32k_out0>; - pinctrl-names = "default"; - #clock-cells = <0>; - }; - - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - sata1: sata@fc400000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc400000 0 0x1000>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, - <&cru CLK_SATA1_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - sata2: sata@fc800000 { - compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfc800000 0 0x1000>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, - <&cru CLK_SATA2_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - phys = <&combphy2 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - usb_host0_xhci: usb@fcc00000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "otg"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG0>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - usb_host1_xhci: usb@fd000000 { - compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = ; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; - dr_mode = "host"; - phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG1>; - snps,dis_u2_susphy_quirk; - status = "disabled"; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd410000>; - mbi-ranges = <296 24>; - msi-controller; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&usb2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3568-pmu-io-voltage-domain"; - status = "disabled"; - }; - }; - - pipegrf: syscon@fdc50000 { - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <32768>, <1200000000>, <200000000>; - assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; - rockchip,grf = <&grf>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - interrupts = ; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fdd90000 { - compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfdd90000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3568-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_GPU */ - power-domain@RK3568_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU_PRE>, - <&cru PCLK_GPU_PRE>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3568_PD_VI { - reg = ; - clocks = <&cru HCLK_VI>, - <&cru PCLK_VI>; - pm_qos = <&qos_isp>, - <&qos_vicap0>, - <&qos_vicap1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VO { - reg = ; - clocks = <&cru HCLK_VO>, - <&cru PCLK_VO>, - <&cru ACLK_VOP_PRE>; - pm_qos = <&qos_hdcp>, - <&qos_vop_m0>, - <&qos_vop_m1>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RGA { - reg = ; - clocks = <&cru HCLK_RGA_PRE>, - <&cru PCLK_RGA_PRE>; - pm_qos = <&qos_ebc>, - <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc>, - <&qos_rga_rd>, - <&qos_rga_wr>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_VPU { - reg = ; - clocks = <&cru HCLK_VPU_PRE>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVDEC { - clocks = <&cru HCLK_RKVDEC_PRE>; - reg = ; - pm_qos = <&qos_rkvdec>; - #power-domain-cells = <0>; - }; - - power-domain@RK3568_PD_RKVENC { - reg = ; - clocks = <&cru HCLK_RKVENC_PRE>; - pm_qos = <&qos_rkvenc_rd_m0>, - <&qos_rkvenc_rd_m1>, - <&qos_rkvenc_wr_m0>; - #power-domain-cells = <0>; - }; - }; - }; - - gpu: gpu@fde60000 { - compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; - reg = <0x0 0xfde60000 0x0 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; - clock-names = "gpu", "bus"; - #cooling-cells = <2>; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3568_PD_GPU>; - status = "disabled"; - }; - - vpu: video-codec@fdea0400 { - compatible = "rockchip,rk3568-vpu"; - reg = <0x0 0xfdea0000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vdpu_mmu>; - power-domains = <&power RK3568_PD_VPU>; - }; - - vdpu_mmu: iommu@fdea0800 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfdea0800 0x0 0x40>; - interrupts = ; - clock-names = "aclk", "iface"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - power-domains = <&power RK3568_PD_VPU>; - #iommu-cells = <0>; - }; - - rga: rga@fdeb0000 { - compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; - reg = <0x0 0xfdeb0000 0x0 0x180>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; - clock-names = "aclk", "hclk", "sclk"; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; - reset-names = "core", "axi", "ahb"; - power-domains = <&power RK3568_PD_RGA>; - }; - - vepu: video-codec@fdee0000 { - compatible = "rockchip,rk3568-vepu"; - reg = <0x0 0xfdee0000 0x0 0x800>; - interrupts = ; - clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; - clock-names = "aclk", "hclk"; - iommus = <&vepu_mmu>; - power-domains = <&power RK3568_PD_RGA>; - }; - - vepu_mmu: iommu@fdee0800 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfdee0800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3568_PD_RGA>; - #iommu-cells = <0>; - }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,rd_osr_lmt = <8>; - snps,wr_osr_lmt = <4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - vop: vop@fe040000 { - reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; - iommus = <&vop_mmu>; - power-domains = <&power RK3568_PD_VO>; - rockchip,grf = <&grf>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp1: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - vp2: port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - vop_mmu: iommu@fe043e00 { - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - dsi0: dsi@fe060000 { - compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x00 0xfe060000 0x00 0x10000>; - interrupts = ; - clock-names = "pclk"; - clocks = <&cru PCLK_DSITX_0>; - phy-names = "dphy"; - phys = <&dsi_dphy0>; - power-domains = <&power RK3568_PD_VO>; - reset-names = "apb"; - resets = <&cru SRST_P_DSITX_0>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dsi0_in: port@0 { - reg = <0>; - }; - - dsi0_out: port@1 { - reg = <1>; - }; - }; - }; - - dsi1: dsi@fe070000 { - compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xfe070000 0x0 0x10000>; - interrupts = ; - clock-names = "pclk"; - clocks = <&cru PCLK_DSITX_1>; - phy-names = "dphy"; - phys = <&dsi_dphy1>; - power-domains = <&power RK3568_PD_VO>; - reset-names = "apb"; - resets = <&cru SRST_P_DSITX_1>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dsi1_in: port@0 { - reg = <0>; - }; - - dsi1_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi: hdmi@fe0a0000 { - compatible = "rockchip,rk3568-dw-hdmi"; - reg = <0x0 0xfe0a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_HOST>, - <&cru CLK_HDMI_SFR>, - <&cru CLK_HDMI_CEC>, - <&pmucru CLK_HDMI_REF>, - <&cru HCLK_VO>; - clock-names = "iahb", "isfr", "cec", "ref"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - power-domains = <&power RK3568_PD_VO>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - qos_gpu: qos@fe128000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; - }; - - qos_rkvenc_rd_m0: qos@fe138080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138080 0x0 0x20>; - }; - - qos_rkvenc_rd_m1: qos@fe138100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138100 0x0 0x20>; - }; - - qos_rkvenc_wr_m0: qos@fe138180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe138180 0x0 0x20>; - }; - - qos_isp: qos@fe148000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148000 0x0 0x20>; - }; - - qos_vicap0: qos@fe148080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148080 0x0 0x20>; - }; - - qos_vicap1: qos@fe148100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe148100 0x0 0x20>; - }; - - qos_vpu: qos@fe150000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe150000 0x0 0x20>; - }; - - qos_ebc: qos@fe158000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158000 0x0 0x20>; - }; - - qos_iep: qos@fe158100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158100 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fe158180 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158180 0x0 0x20>; - }; - - qos_jpeg_enc: qos@fe158200 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158200 0x0 0x20>; - }; - - qos_rga_rd: qos@fe158280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158280 0x0 0x20>; - }; - - qos_rga_wr: qos@fe158300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe158300 0x0 0x20>; - }; - - qos_npu: qos@fe180000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe180000 0x0 0x20>; - }; - - qos_pcie2x1: qos@fe190000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190000 0x0 0x20>; - }; - - qos_sata1: qos@fe190280 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190280 0x0 0x20>; - }; - - qos_sata2: qos@fe190300 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190300 0x0 0x20>; - }; - - qos_usb3_0: qos@fe190380 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190380 0x0 0x20>; - }; - - qos_usb3_1: qos@fe190400 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190400 0x0 0x20>; - }; - - qos_rkvdec: qos@fe198000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe198000 0x0 0x20>; - }; - - qos_hdcp: qos@fe1a8000 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8000 0x0 0x20>; - }; - - qos_vop_m0: qos@fe1a8080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8080 0x0 0x20>; - }; - - qos_vop_m1: qos@fe1a8100 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; - - dfi: dfi@fe230000 { - compatible = "rockchip,rk3568-dfi"; - reg = <0x00 0xfe230000 0x00 0x400>; - interrupts = ; - rockchip,pmu = <&pmugrf>; - }; - - pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie"; - reg = <0x3 0xc0000000 0x0 0x00400000>, - <0x0 0xfe260000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - linux,pci-domain = <0>; - num-ib-windows = <6>; - num-ob-windows = <2>; - max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: mmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sfc: spi@fe300000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe300000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&fspi_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe400000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe400000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 0>; - dma-names = "tx"; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe410000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe410000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; - assigned-clock-rates = <1188000000>, <1188000000>; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, - <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 3>, <&dmac1 2>; - dma-names = "rx", "tx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx - &i2s1m0_lrcktx &i2s1m0_lrckrx - &i2s1m0_sdi0 &i2s1m0_sdi1 - &i2s1m0_sdi2 &i2s1m0_sdi3 - &i2s1m0_sdo0 &i2s1m0_sdo1 - &i2s1m0_sdo2 &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe420000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe420000 0x0 0x1000>; - interrupts = ; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-rates = <1188000000>; - clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 4>, <&dmac1 5>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S2_2CH>; - reset-names = "m"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m0_sclktx - &i2s2m0_lrcktx - &i2s2m0_sdi - &i2s2m0_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe430000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe430000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, - <&cru HCLK_I2S3_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 6>, <&dmac1 7>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pdm: pdm@fe440000 { - compatible = "rockchip,rk3568-pdm"; - reg = <0x0 0xfe440000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac1 9>; - dma-names = "rx"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_clk1 - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - pinctrl-names = "default"; - resets = <&cru SRST_M_PDM>; - reset-names = "pdm-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: spdif@fe460000 { - compatible = "rockchip,rk3568-spdif"; - reg = <0x0 0xfe460000 0x0 0x1000>; - interrupts = ; - clock-names = "mclk", "hclk"; - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; - dmas = <&dmac1 1>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@fe600000 { - compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - interrupts = ; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - }; - - spi0: spi@fe610000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe610000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 20>, <&dmac0 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@fe620000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe620000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 22>, <&dmac0 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@fe630000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe630000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 24>, <&dmac0 25>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@fe640000 { - compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfe640000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 26>, <&dmac0 27>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; - polling-delay = <1000>; - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - gpu_threshold: gpu-threshold { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_target: gpu-target { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_target>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@fe710000 { - compatible = "rockchip,rk3568-tsadc"; - reg = <0x0 0xfe710000 0x0 0x100>; - interrupts = ; - assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; - assigned-clock-rates = <17000000>, <700000>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, - <&cru SRST_TSADCPHY>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_pin>; - pinctrl-1 = <&tsadc_shutorg>; - pinctrl-2 = <&tsadc_pin>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = ; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - combphy1: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, - <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY1>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - #phy-cells = <1>; - status = "disabled"; - }; - - combphy2: phy@fe840000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe840000 0x0 0x100>; - clocks = <&pmucru CLK_PCIEPHY2_REF>, - <&cru PCLK_PIPEPHY2>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_PIPEPHY2>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf2>; - #phy-cells = <1>; - status = "disabled"; - }; - - csi_dphy: phy@fe870000 { - compatible = "rockchip,rk3568-csi-dphy"; - reg = <0x0 0xfe870000 0x0 0x10000>; - clocks = <&cru PCLK_MIPICSIPHY>; - clock-names = "pclk"; - #phy-cells = <0>; - resets = <&cru SRST_P_MIPICSIPHY>; - reset-names = "apb"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - dsi_dphy0: mipi-dphy@fe850000 { - compatible = "rockchip,rk3568-dsi-dphy"; - reg = <0x0 0xfe850000 0x0 0x10000>; - clock-names = "ref", "pclk"; - clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; - #phy-cells = <0>; - power-domains = <&power RK3568_PD_VO>; - reset-names = "apb"; - resets = <&cru SRST_P_MIPIDSIPHY0>; - status = "disabled"; - }; - - dsi_dphy1: mipi-dphy@fe860000 { - compatible = "rockchip,rk3568-dsi-dphy"; - reg = <0x0 0xfe860000 0x0 0x10000>; - clock-names = "ref", "pclk"; - clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; - #phy-cells = <0>; - power-domains = <&power RK3568_PD_VO>; - reset-names = "apb"; - resets = <&cru SRST_P_MIPIDSIPHY1>; - status = "disabled"; - }; - - usb2phy0: usb2phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy0_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy0_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - clock-output-names = "clk_usbphy1_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy1_grf>; - #clock-cells = <0>; - status = "disabled"; - - usb2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usb2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts deleted file mode 100644 index a4946cdc3bb34ef7bc084f74ae0a4ac8424994df..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include "rk3588-coolpi-cm5.dtsi" - -/ { - model = "RK3588 CoolPi CM5 EVB"; - compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; - - backlight: backlight { - compatible = "pwm-backlight"; - enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - power-supply = <&vcc12v_dcin>; - pwms = <&pwm2 0 25000 0>; - }; - - leds: leds { - compatible = "gpio-leds"; - - green_led: led-0 { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_lcd: vcc3v3-lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd"; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&lcdpwr_en>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_host_pwren>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - regulator-boot-on; - regulator-always-on; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_otg_pwren>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -/* M.2 E-Key */ -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -/* Standard pcie */ -&pcie3x2 { - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -/* M.2 M-Key ssd */ -&pcie3x4 { - num-lanes = <2>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_sys>; - status = "okay"; -}; - -&pinctrl { - lcd { - lcdpwr_en: lcdpwr-en { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - bl_en: bl-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - usb_host_pwren: usb-host-pwren { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - usb_otg_pwren: usb-otg-pwren { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wifi { - bt_pwron: bt-pwron { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pcie_clkreq: pcie-clkreq { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pcie_rst: pcie-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wifi_pwron: wifi-pwron { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pcie_wake: pcie-wake { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_usb_host1>; - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_usb_host2>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5.dtsi b/arch/arm/dts/rk3588-coolpi-cm5.dtsi deleted file mode 100644 index 9cb6d566da6e6d17df4254b52311d78d084e3448..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-coolpi-cm5.dtsi +++ /dev/null @@ -1,649 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3588.dtsi" - -/ { - compatible = "coolpi,pi-cm5", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - analog-sound { - compatible = "audio-graph-card"; - dais = <&i2s0_8ch_p0>; - label = "rk3588-es8316"; - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - avdd0v85_pcie20: avdd0v85-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd0v85_pcie20"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - avdd1v8_pcie20: avdd1v8-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd1v8_pcie20"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - avdd0v75_pcie30: avdd0v75-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd0v75_pcie30"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: avdd1v8-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2c7 { - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* YT8531C/H */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&yt8531_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - }; -}; - -/* ethernet */ -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&yt6801_isolate>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - yt6801 { - yt6801_isolate: yt6801-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - yt8531 { - yt8531_rst: yt8531-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - no-sdio; - no-sd; - non-removable; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_2v0_pldo_s3>; - vcc14-supply = <&vcc_2v0_pldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts deleted file mode 100644 index be6a4f4f90f68bb98decaf12070e5f8a9670b500..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. - */ - -/dts-v1/; -#include "rk3588.dtsi" -#include "rk3588-edgeble-neu6a.dtsi" - -/ { - model = "Edgeble Neu6A IO Board"; - compatible = "edgeble,neural-compute-module-6a-io", - "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi deleted file mode 100644 index 727580aaa105b29454e7cc165216f7b448deddb8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. - */ - -/ { - compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts deleted file mode 100644 index 070baeb63431f960345f5622e1a1ee3a3df1b1ca..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. - */ - -/dts-v1/; -#include "rk3588j.dtsi" -#include "rk3588-edgeble-neu6b.dtsi" - -/ { - model = "Edgeble Neu6B IO Board"; - compatible = "edgeble,neural-compute-module-6a-io", - "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -/* FAN */ -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* RS232 */ -&uart6 { - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* RS485 */ -&uart7 { - pinctrl-0 = <&uart7m2_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi deleted file mode 100644 index 017559bba37f7d5e2445fc418f08475051256316..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. - */ - -/ { - compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts deleted file mode 100644 index ac7c677b0fb9c3d6af9e7b8bcd399d9d24ef0b84..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ /dev/null @@ -1,1080 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 V10 Board"; - compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdhci; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-vol-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - button-vol-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - button-menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - button-escape { - label = "Escape"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; - }; - - analog-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "RK3588 EVB1 Audio"; - simple-audio-card,aux-devs = <&_headphone>, <&_speaker>; - simple-audio-card,bitclock-master = <&masterdai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&masterdai>; - simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,pin-switches = "Headphones", "Speaker"; - simple-audio-card,routing = - "Speaker Amplifier INL", "LOUT2", - "Speaker Amplifier INR", "ROUT2", - "Speaker", "Speaker Amplifier OUTL", - "Speaker", "Speaker Amplifier OUTR", - "Headphones Amplifier INL", "LOUT1", - "Headphones Amplifier INR", "ROUT1", - "Headphones", "Headphones Amplifier OUTL", - "Headphones", "Headphones Amplifier OUTR", - "LINPUT1", "Onboard Microphone", - "RINPUT1", "Onboard Microphone", - "LINPUT2", "Microphone Jack", - "RINPUT2", "Microphone Jack"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone", - "Headphone", "Headphones", - "Speaker", "Speaker"; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - - masterdai: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - - amp_headphone: headphone-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&headphone_amplifier_en>; - sound-name-prefix = "Headphones Amplifier"; - }; - - amp_speaker: speaker-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&speaker_amplifier_en>; - sound-name-prefix = "Speaker Amplifier"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc12v_dcin>; - pwms = <&pwm2 0 25000 0>; - }; - - pcie20_avdd0v85: pcie20-avdd0v85-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8388: audio-codec@11 { - compatible = "everest,es8388"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - AVDD-supply = <&avcc_1v8_codec_s0>; - DVDD-supply = <&avcc_1v8_codec_s0>; - HPVDD-supply = <&vcc_3v3_s0>; - PVDD-supply = <&vcc_3v3_s0>; - #sound-dai-cells = <0>; - }; -}; - -&i2s0_8ch { - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - audio { - hp_detect: headphone-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - headphone_amplifier_en: headphone-amplifier-en { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - speaker_amplifier_en: speaker-amplifier-en { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie2 { - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_reset: pcie3-reset { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_pcie30_en: vcc3v3-pcie30-en { - rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <2>; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - #gpio-cells = <2>; - gpio-controller; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc5v0_sys>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vdd_gpu_mem_s0: dcdc-reg5 { - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - regulator-name = "vdd_gpu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vdd_npu_mem_s0: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vdd_vdenc_mem_s0: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd2_ddr_s3: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v1_nldo_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd1_1v8_ddr_s3: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd1_1v8_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_codec_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_1v8_codec_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s3: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_1v8_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd2l_0v9_ddr_s3: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd2l_0v9_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_0v75_hdmi_edp_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_hdmi_edp_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v75_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - pmic@1 { - compatible = "rockchip,rk806"; - reg = <0x01>; - #gpio-cells = <2>; - gpio-controller; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, - <&rk806_slave_dvs3_null>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_2v0_pldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - rk806_slave_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_slave_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_cpu_big1_s0: dcdc-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big0_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_mem_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - - vdd_cpu_big0_mem_s0: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_mem_s0: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_cam_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd1v8_ddr_pll_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd1v8_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_1v8_pll_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_1v8_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_sd_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_2v8_cam_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_2v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_pll_s0: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_cam_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&sata0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index 225dfa0b682a4b3dd4199fba37762309ac6fca84..f67301d87a6e2301c1454288d0c9a1a61d6a107e 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -14,10 +14,6 @@ status = "okay"; }; -&usbdp_phy0_u3 { - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "peripheral"; maximum-speed = "high-speed"; diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts deleted file mode 100644 index 4ce70fb75a307ba34fdd8ad5a72d56401de0118e..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-jaguar.dts +++ /dev/null @@ -1,803 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Theobroma Systems RK3588-SBC Jaguar"; - compatible = "tsd,rk3588-jaguar", "rockchip,rk3588"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */ - button-bios-disable { - label = "BIOS_DISABLE"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdhci; - mmc1 = &sdmmc; - rtc0 = &rtc_twi; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - /* DCIN is 12-24V but standard is 12V */ - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - pinctrl-0 = <&emmc_reset>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led1_pin>; - status = "okay"; - - /* LED1 on PCB */ - led-1 { - gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - color = ; - }; - }; - - pps { - compatible = "pps-gpio"; - gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v2_s3: vcc-1v2-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v2_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc5v0_sys>; - }; - - /* Exposed on P14 and P15 */ - vcc_2v8_s3: vcc-2v8-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_2v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_5v0_usb_a: vcc-5v0-usb-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "usb_a_vcc"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator { - compatible = "regulator-fixed"; - regulator-name = "5v_usbc1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator { - compatible = "regulator-fixed"; - regulator-name = "5v_usbc2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc3v3_mdot2: vcc3v3-mdot2-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_mdot2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy1_ps { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; - phy-supply = <&vcc_1v2_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_rx_bus2 - &gmac0_tx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - ð0_pins - ð_reset>; - tx_delay = <0x10>; - rx_delay = <0x10>; - snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 100000>; - - status = "okay"; -}; - -&gpio1 { - mdot2e-w-disable1-n-hog { - gpios = ; - output-low; - line-name = "m.2 E-key W_DISABLE1#"; - gpio-hog; - }; -}; - -&gpio4 { - mdot2e-w-disable2-n-hog { - gpios = ; - output-low; - line-name = "m.2 E-key W_DISABLE2#"; - gpio-hog; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - }; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rtc_twi: rtc@6f { - compatible = "isil,isl1208"; - reg = <0x6f>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1m4_xfer>; -}; - -&i2c6 { - pinctrl-0 = <&i2c6m4_xfer>; -}; - -&i2c7 { - status = "okay"; - - /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */ - - /* Also on 0x55 */ - eeprom@54 { - compatible = "st,24c04", "atmel,24c04"; - reg = <0x54>; - pagesize = <16>; - vcc-supply = <&vcc_3v3_s3>; - }; -}; - -&i2c8 { - pinctrl-0 = <&i2c8m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@6 { - /* KSZ9031 or KSZ9131 */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x6>; - clocks = <&cru REFCLKO25M_ETH0_OUT>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */ - vpcie3v3-supply = <&vcc3v3_mdot2>; - status = "okay"; -}; - -&pinctrl { - emmc { - emmc_reset: emmc-reset { - rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - ethernet { - eth_reset: eth-reset { - rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led1_pin: led1-pin { - rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - mmc-pwrseq = <&emmc_pwrseq>; - no-sdio; - no-sd; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; - supports-cqe; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vcc_1v8_s3>; - status = "okay"; -}; - -&sdmmc { - broken-cd; - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - system-power-controller; - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca_1v8_s0: pldo-reg1 { - regulator-name = "vcca_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdda_1v2_s0: pldo-reg3 { - regulator-name = "vdda_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_3v3_s0: pldo-reg4 { - regulator-name = "vcca_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdda_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdda_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdda_0v75_s0: nldo-reg3 { - regulator-name = "vdda_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v85_s0: nldo-reg4 { - regulator-name = "vdda_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc_5v0_usb_a>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -/* Mule-ATtiny debug UART; typically baudrate 9600 */ -&uart0 { - pinctrl-0 = <&uart0m0_xfer>; - status = "okay"; -}; - -/* Main debug interface on P20 micro-USB B port and P21 header */ -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* RS485 on P19 */ -&uart3 { - pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -/* Mule-ATtiny UPDI flashing UART */ -&uart7 { - pinctrl-0 = <&uart7m0_xfer>; - status = "okay"; -}; - -/* host0 on P10 USB-A */ -&usb_host0_ehci { - status = "okay"; -}; - -/* host0 on P10 USB-A */ -&usb_host0_ohci { - status = "okay"; -}; - -/* host1 on M.2 E-key */ -&usb_host1_ehci { - status = "okay"; -}; - -/* host1 on M.2 E-key */ -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts deleted file mode 100644 index d7722772ecd8a0afb7e844ffb168fa9a7462cb03..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-nanopc-t6.dts +++ /dev/null @@ -1,916 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Thomas McKahan - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "FriendlyElec NanoPC-T6"; - compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - - sys_led: led-0 { - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - label = "system-led"; - linux,default-trigger = "heartbeat"; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - usr_led: led-1 { - gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; - label = "user-led"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pin>; - }; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - - simple-audio-card,name = "realtek,rt5616-codec"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - simple-audio-card,hp-pin-name = "Headphones"; - - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "Headphones", "HPOL", - "Headphones", "HPOR", - "MIC1", "Microphone Jack", - "Microphone Jack", "micbias1"; - - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&rt5616>; - }; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - /* vcc5v0_sys powers peripherals */ - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - /* vcc4v0_sys powers the RK806, RK860's */ - vcc4v0_sys: vcc4v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc4v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <4000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc-1v1-nldo-s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc4v0_sys>; - }; - - vcc_3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pcie20"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vbus5v0_typec: vbus5v0-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_m2_1_pwren>; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_m2_0_pwren>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_b0{ - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1{ - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2{ - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3{ - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&gpio0 { - gpio-line-names = /* GPIO0 A0-A7 */ - "", "", "", "", - "", "", "", "", - /* GPIO0 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO0 C0-C7 */ - "", "", "", "", - "HEADER_10", "HEADER_08", "HEADER_32", "", - /* GPIO0 D0-D7 */ - "", "", "", "", - "", "", "", ""; -}; - -&gpio1 { - gpio-line-names = /* GPIO1 A0-A7 */ - "HEADER_27", "HEADER_28", "", "", - "", "", "", "HEADER_15", - /* GPIO1 B0-B7 */ - "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", - "HEADER_24", "HEADER_22", "", "", - /* GPIO1 C0-C7 */ - "", "", "", "", - "", "", "", "", - /* GPIO1 D0-D7 */ - "", "", "", "", - "", "", "HEADER_05", "HEADER_03"; -}; - -&gpio2 { - gpio-line-names = /* GPIO2 A0-A7 */ - "", "", "", "", - "", "", "", "", - /* GPIO2 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO2 C0-C7 */ - "", "CSI1_11", "CSI1_12", "", - "", "", "", "", - /* GPIO2 D0-D7 */ - "", "", "", "", - "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = /* GPIO3 A0-A7 */ - "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", - "HEADER_37", "", "DSI0_12", "", - /* GPIO3 B0-B7 */ - "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", - "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", - /* GPIO3 C0-C7 */ - "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", - "", "", "", "", - /* GPIO3 D0-D7 */ - "", "", "", "", - "", "DSI1_10", "", ""; -}; - -&gpio4 { - gpio-line-names = /* GPIO4 A0-A7 */ - "DSI1_08", "DSI1_14", "", "DSI1_12", - "", "", "", "", - /* GPIO4 B0-B7 */ - "", "", "", "", - "", "", "", "", - /* GPIO4 C0-C7 */ - "", "", "", "", - "CSI0_11", "CSI0_12", "", "", - /* GPIO4 D0-D7 */ - "", "", "", "", - "", "", "", ""; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - rockchip,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc4v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - clock-frequency = <200000>; - status = "okay"; - - fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-0 = <&usbc0_int>; - pinctrl-names = "default"; - vbus-supply = <&vbus5v0_typec>; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <1000000>; - }; - }; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - clock-frequency = <200000>; - status = "okay"; - - rt5616: codec@1b { - compatible = "realtek,rt5616"; - reg = <0x1b>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - - port { - rt5616_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; - - /* connected with MIPI-CSI1 */ -}; - -&i2c8 { - pinctrl-0 = <&i2c8m2_xfer>; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&rt5616_p0_0>; - }; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - gpio-leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usr_led_pin: usr-led-pin { - rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_1_rst: pcie2-1-rst { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_m2_0_pwren: pcie-m20-pwren { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_m2_1_pwren: pcie-m21-pwren { - rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - pinctrl-0 = <&pwm1m1_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc4v0_sys>; - vcc2-supply = <&vcc4v0_sys>; - vcc3-supply = <&vcc4v0_sys>; - vcc4-supply = <&vcc4v0_sys>; - vcc5-supply = <&vcc4v0_sys>; - vcc6-supply = <&vcc4v0_sys>; - vcc7-supply = <&vcc4v0_sys>; - vcc8-supply = <&vcc4v0_sys>; - vcc9-supply = <&vcc4v0_sys>; - vcc10-supply = <&vcc4v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc4v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc4v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus.dts b/arch/arm/dts/rk3588-orangepi-5-plus.dts deleted file mode 100644 index 3e660ff6cd5ff3d966356667e5b7db80a298da3b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-orangepi-5-plus.dts +++ /dev/null @@ -1,847 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Ondřej Jirman - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Xunlong Orange Pi 5 Plus"; - compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys-0 { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-maskrom { - label = "Mask Rom"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - adc-keys-1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - speaker_amp: speaker-audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Speaker Amp"; - }; - - headphone_amp: headphones-audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Headphones Amp"; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_receiver_pin>; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin>; - - led { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 70 75 80 100>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm3 0 50000 0>; - #cooling-cells = <2>; - }; - - pwm-leds { - compatible = "pwm-leds"; - - led { - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - max-brightness = <255>; - pwms = <&pwm2 0 25000 0>; - }; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "Analog"; - simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; - simple-audio-card,bitclock-master = <&daicpu>; - simple-audio-card,frame-master = <&daicpu>; - /*TODO: SARADC_IN3 is used as MIC detection / key input */ - - simple-audio-card,widgets = - "Microphone", "Onboard Microphone", - "Microphone", "Microphone Jack", - "Speaker", "Speaker", - "Headphone", "Headphones"; - - simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - - "Headphones", "Headphones Amp OUTL", - "Headphones", "Headphones Amp OUTR", - "Headphones Amp INL", "LOUT1", - "Headphones Amp INR", "ROUT1", - - "Speaker", "Speaker Amp OUTL", - "Speaker", "Speaker Amp OUTR", - "Speaker Amp INL", "LOUT2", - "Speaker Amp INR", "ROUT2", - - /* single ended signal to LINPUT1 */ - "LINPUT1", "Microphone Jack", - "RINPUT1", "Microphone Jack", - /* differential signal */ - "LINPUT2", "Onboard Microphone", - "RINPUT2", "Onboard Microphone"; - - daicpu: simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - system-clock-frequency = <12288000>; - }; - - daicodec: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { - compatible = "regulator-fixed"; - gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; - regulator-name = "vcc3v3_pcie_eth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_wf: vcc3v3-wf-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_wf"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_usb20: vcc5v0-usb20-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb20_en>; - regulator-name = "vcc5v0_usb20"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - clock-frequency = <400000>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ - es8388: audio-codec@11 { - compatible = "everest,es8388"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - AVDD-supply = <&vcc_1v8_s0>; - DVDD-supply = <&vcc_1v8_s0>; - HPVDD-supply = <&vcc_3v3_s0>; - PVDD-supply = <&vcc_3v3_s0>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; -}; - -&i2s2_2ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m0_lrck - &i2s2m0_sclk - &i2s2m0_sdi - &i2s2m0_sdo>; - status = "okay"; -}; - -/* phy1 - M.KEY socket */ -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_wf>; - status = "okay"; -}; - -/* phy2 - right ethernet port */ -&pcie2x1l1 { - reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_eth>; - status = "okay"; -}; - -/* phy0 - left ethernet port */ -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie_eth>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - blue_led_pin: blue-led { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir-receiver { - ir_receiver_pin: ir-receiver-pin { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_usb20_en: vcc5v0-usb20-en { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim1_pins>; - status = "okay"; - - spi_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vdd2_ddr_s3>; - vcc14-supply = <&vdd2_ddr_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-enable-ramp-delay = <400>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <825000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <825000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - /* shorted to avcc_1v8_s0 on the board */ - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - /* - * The schematic mentions that actual setting - * should be 0.8375V. RK3588 datasheet specifies - * maximum as 0.825V. So we set datasheet max - * here. - */ - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <825000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_usb20>; - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_usb20>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&uart9 { - pinctrl-0 = <&uart9m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-pinctrl.dtsi b/arch/arm/dts/rk3588-pinctrl.dtsi deleted file mode 100644 index 244c66faa1614f6136435e30c9484f1ce8de562e..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-pinctrl.dtsi +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - clk32k { - /omit-if-no-ref/ - clk32k_out1: clk32k-out1 { - rockchip,pins = - /* clk32k_out1 */ - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - }; - - eth0 { - /omit-if-no-ref/ - eth0_pins: eth0-pins { - rockchip,pins = - /* eth0_refclko_25m */ - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - }; - - fspi { - /omit-if-no-ref/ - fspim1_pins: fspim1-pins { - rockchip,pins = - /* fspi_clk_m1 */ - <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m1 */ - <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m1 */ - <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m1 */ - <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m1 */ - <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m1 */ - <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim1_cs1: fspim1-cs1 { - rockchip,pins = - /* fspi_cs1n_m1 */ - <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac0 { - /omit-if-no-ref/ - gmac0_miim: gmac0-miim { - rockchip,pins = - /* gmac0_mdc */ - <4 RK_PC4 1 &pcfg_pull_none>, - /* gmac0_mdio */ - <4 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_clkinout: gmac0-clkinout { - rockchip,pins = - /* gmac0_mclkinout */ - <4 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rx_bus2: gmac0-rx-bus2 { - rockchip,pins = - /* gmac0_rxd0 */ - <2 RK_PC1 1 &pcfg_pull_none>, - /* gmac0_rxd1 */ - <2 RK_PC2 1 &pcfg_pull_none>, - /* gmac0_rxdv_crs */ - <4 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_tx_bus2: gmac0-tx-bus2 { - rockchip,pins = - /* gmac0_txd0 */ - <2 RK_PB6 1 &pcfg_pull_none>, - /* gmac0_txd1 */ - <2 RK_PB7 1 &pcfg_pull_none>, - /* gmac0_txen */ - <2 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_clk: gmac0-rgmii-clk { - rockchip,pins = - /* gmac0_rxclk */ - <2 RK_PB0 1 &pcfg_pull_none>, - /* gmac0_txclk */ - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_rgmii_bus: gmac0-rgmii-bus { - rockchip,pins = - /* gmac0_rxd2 */ - <2 RK_PA6 1 &pcfg_pull_none>, - /* gmac0_rxd3 */ - <2 RK_PA7 1 &pcfg_pull_none>, - /* gmac0_txd2 */ - <2 RK_PB1 1 &pcfg_pull_none>, - /* gmac0_txd3 */ - <2 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppsclk: gmac0-ppsclk { - rockchip,pins = - /* gmac0_ppsclk */ - <2 RK_PC4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ppstring: gmac0-ppstring { - rockchip,pins = - /* gmac0_ppstring */ - <2 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_ptp_refclk: gmac0-ptp-refclk { - rockchip,pins = - /* gmac0_ptp_refclk */ - <2 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac0_txer: gmac0-txer { - rockchip,pins = - /* gmac0_txer */ - <4 RK_PC6 1 &pcfg_pull_none>; - }; - - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_tx1_cec: hdmim0-tx1-cec { - rockchip,pins = - /* hdmim0_tx1_cec */ - <2 RK_PC4 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_scl: hdmim0-tx1-scl { - rockchip,pins = - /* hdmim0_tx1_scl */ - <2 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_sda: hdmim0-tx1-sda { - rockchip,pins = - /* hdmim0_tx1_sda */ - <2 RK_PB4 4 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m1_xfer: i2c0m1-xfer { - rockchip,pins = - /* i2c0_scl_m1 */ - <4 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c0_sda_m1 */ - <4 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2_scl_m1 */ - <2 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m1 */ - <2 RK_PC0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m3_xfer: i2c3m3-xfer { - rockchip,pins = - /* i2c3_scl_m3 */ - <2 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m3 */ - <2 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m1_xfer: i2c4m1-xfer { - rockchip,pins = - /* i2c4_scl_m1 */ - <2 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m1 */ - <2 RK_PB4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m4_xfer: i2c5m4-xfer { - rockchip,pins = - /* i2c5_scl_m4 */ - <2 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m4 */ - <2 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m2_xfer: i2c6m2-xfer { - rockchip,pins = - /* i2c6_scl_m2 */ - <2 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m2 */ - <2 RK_PC2 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m1_xfer: i2c7m1-xfer { - rockchip,pins = - /* i2c7_scl_m1 */ - <4 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m1 */ - <4 RK_PC4 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m1_xfer: i2c8m1-xfer { - rockchip,pins = - /* i2c8_scl_m1 */ - <2 RK_PB0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m1 */ - <2 RK_PB1 9 &pcfg_pull_none_smt>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m2_pins: pwm2m2-pins { - rockchip,pins = - /* pwm2_m2 */ - <4 RK_PC2 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m1_pins: pwm4m1-pins { - rockchip,pins = - /* pwm4_m1 */ - <4 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m2_pins: pwm5m2-pins { - rockchip,pins = - /* pwm5_m2 */ - <4 RK_PC4 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m2_pins: pwm6m2-pins { - rockchip,pins = - /* pwm6_m2 */ - <4 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m3_pins: pwm7m3-pins { - rockchip,pins = - /* pwm7_ir_m3 */ - <4 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom0_pins: sdiom0-pins { - rockchip,pins = - /* sdio_clk_m0 */ - <2 RK_PB3 2 &pcfg_pull_none>, - /* sdio_cmd_m0 */ - <2 RK_PB2 2 &pcfg_pull_none>, - /* sdio_d0_m0 */ - <2 RK_PA6 2 &pcfg_pull_none>, - /* sdio_d1_m0 */ - <2 RK_PA7 2 &pcfg_pull_none>, - /* sdio_d2_m0 */ - <2 RK_PB0 2 &pcfg_pull_none>, - /* sdio_d3_m0 */ - <2 RK_PB1 2 &pcfg_pull_none>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m0_pins: spi1m0-pins { - rockchip,pins = - /* spi1_clk_m0 */ - <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m0 */ - <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m0 */ - <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs0: spi1m0-cs0 { - rockchip,pins = - /* spi1_cs0_m0 */ - <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m0_cs1: spi1m0-cs1 { - rockchip,pins = - /* spi1_cs1_m0 */ - <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m0_pins: spi3m0-pins { - rockchip,pins = - /* spi3_clk_m0 */ - <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m0 */ - <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m0 */ - <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs0: spi3m0-cs0 { - rockchip,pins = - /* spi3_cs0_m0 */ - <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m0_cs1: spi3m0-cs1 { - rockchip,pins = - /* spi3_cs1_m0 */ - <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rx_m0 */ - <2 RK_PB6 10 &pcfg_pull_up>, - /* uart1_tx_m0 */ - <2 RK_PB7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m0_ctsn: uart1m0-ctsn { - rockchip,pins = - /* uart1m0_ctsn */ - <2 RK_PC1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m0_rtsn: uart1m0-rtsn { - rockchip,pins = - /* uart1m0_rtsn */ - <2 RK_PC0 10 &pcfg_pull_none>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m0_xfer: uart6m0-xfer { - rockchip,pins = - /* uart6_rx_m0 */ - <2 RK_PA6 10 &pcfg_pull_up>, - /* uart6_tx_m0 */ - <2 RK_PA7 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m0_ctsn: uart6m0-ctsn { - rockchip,pins = - /* uart6m0_ctsn */ - <2 RK_PB1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m0_rtsn: uart6m0-rtsn { - rockchip,pins = - /* uart6m0_rtsn */ - <2 RK_PB0 10 &pcfg_pull_none>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m0_xfer: uart7m0-xfer { - rockchip,pins = - /* uart7_rx_m0 */ - <2 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m0 */ - <2 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m0_ctsn: uart7m0-ctsn { - rockchip,pins = - /* uart7m0_ctsn */ - <4 RK_PC6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m0_rtsn: uart7m0-rtsn { - rockchip,pins = - /* uart7m0_rtsn */ - <4 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m0_ctsn: uart9m0-ctsn { - rockchip,pins = - /* uart9m0_ctsn */ - <4 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m0_rtsn: uart9m0-rtsn { - rockchip,pins = - /* uart9m0_rtsn */ - <4 RK_PC4 10 &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts deleted file mode 100644 index 87a0abf95f7d4f9ac0846c61a7ad18ba6cdabea1..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-quartzpro64.dts +++ /dev/null @@ -1,1137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Ondřej Jirman - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "rk3588.dtsi" - -/ { - model = "PINE64 QuartzPro64"; - compatible = "pine64,quartzpro64", "rockchip,rk3588"; - - aliases { - ethernet0 = &gmac0; - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys-0 { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-maskrom { - label = "Mask Rom"; - linux,code = ; - press-threshold-microvolt = <393>; - }; - }; - - adc-keys-1 { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-volume-up { - label = "V+/REC"; - linux,code = ; - press-threshold-microvolt = <17821>; - }; - - button-volume-down { - label = "V-"; - linux,code = ; - press-threshold-microvolt = <415384>; - }; - - button-menu { - label = "MENU"; - linux,code = ; - press-threshold-microvolt = <890909>; - }; - - button-esc { - label = "ESC"; - linux,code = ; - press-threshold-microvolt = <1233962>; - }; - }; - - headphone_amp: audio-amplifier-headphone { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Headphones Amp"; - }; - - speaker_amp: audio-amplifier-speaker { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Speaker Amp"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - led-1 { - color = ; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "Analog"; - simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - simple-audio-card,bitclock-master = <&daicpu>; - simple-audio-card,frame-master = <&daicpu>; - /* SARADC_IN3 is used as MIC detection / key input */ - - simple-audio-card,widgets = - "Microphone", "Onboard Microphone", - "Microphone", "Microphone Jack", - "Speaker", "Speaker", - "Headphone", "Headphones"; - - simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - - "Headphones", "Headphones Amp OUTL", - "Headphones", "Headphones Amp OUTR", - "Headphones Amp INL", "LOUT1", - "Headphones Amp INR", "ROUT1", - - "Speaker", "Speaker Amp OUTL", - "Speaker", "Speaker Amp OUTR", - "Speaker Amp INL", "LOUT2", - "Speaker Amp INR", "ROUT2", - - /* single ended signal to LINPUT1 */ - "LINPUT1", "Microphone Jack", - "RINPUT1", "Microphone Jack", - /* differential signal */ - "LINPUT2", "Onboard Microphone", - "RINPUT2", "Onboard Microphone"; - - daicpu: simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - system-clock-frequency = <12288000>; - }; - - daicodec: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_bt: vcc3v3-bt-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_bt"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc_3v3_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_wf: vcc3v3-wf-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_wf"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc_3v3_s0>; - }; - - vcc4v0_sys: vcc4v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc4v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <4000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8388: audio-codec@11 { - compatible = "everest,es8388"; - reg = <0x11>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - AVDD-supply = <&avcc_1v8_codec_s0>; - DVDD-supply = <&avcc_1v8_codec_s0>; - HPVDD-supply = <&vcc_3v3_s0>; - PVDD-supply = <&vcc_3v3_s0>; - #sound-dai-cells = <0>; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - led_pins: led-pins { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -/* WIFI */ -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_wf>; - status = "okay"; -}; - -/* GMAC1 */ -&pcie2x1l1 { - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <150000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <2>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - #gpio-cells = <2>; - gpio-controller; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc4v0_sys>; - vcc2-supply = <&vcc4v0_sys>; - vcc3-supply = <&vcc4v0_sys>; - vcc4-supply = <&vcc4v0_sys>; - vcc5-supply = <&vcc4v0_sys>; - vcc6-supply = <&vcc4v0_sys>; - vcc7-supply = <&vcc4v0_sys>; - vcc8-supply = <&vcc4v0_sys>; - vcc9-supply = <&vcc4v0_sys>; - vcc10-supply = <&vcc4v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc4v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc4v0_sys>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-enable-ramp-delay = <400>; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_s0: dcdc-reg2 { - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vdd_gpu_mem_s0: dcdc-reg5 { - regulator-name = "vdd_gpu_mem_s0"; - regulator-boot-on; - regulator-enable-ramp-delay = <400>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vdd_npu_mem_s0: dcdc-reg6 { - regulator-name = "vdd_npu_mem_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vdd_vdenc_mem_s0: dcdc-reg8 { - regulator-name = "vdd_vdenc_mem_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd2_ddr_s3: dcdc-reg9 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v1_nldo_s3: dcdc-reg10 { - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd1_1v8_ddr_s3: pldo-reg2 { - regulator-name = "vdd1_1v8_ddr_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_codec_s0: pldo-reg3 { - regulator-name = "avcc_1v8_codec_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s3: pldo-reg4 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: pldo-reg6 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - /* reserved for LPDDR5, unused? */ - vdd2l_0v9_ddr_s3: nldo-reg2 { - regulator-name = "vdd2l_0v9_ddr_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_0v75_hdmi_edp_s0: nldo-reg3 { - regulator-name = "vdd_0v75_hdmi_edp_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v75_s0: nldo-reg4 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg5 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - pmic@1 { - compatible = "rockchip,rk806"; - reg = <0x01>; - #gpio-cells = <2>; - gpio-controller; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, - <&rk806_slave_dvs3_null>; - pinctrl-names = "default"; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc4v0_sys>; - vcc2-supply = <&vcc4v0_sys>; - vcc3-supply = <&vcc4v0_sys>; - vcc4-supply = <&vcc4v0_sys>; - vcc5-supply = <&vcc4v0_sys>; - vcc6-supply = <&vcc4v0_sys>; - vcc7-supply = <&vcc4v0_sys>; - vcc8-supply = <&vcc4v0_sys>; - vcc9-supply = <&vcc4v0_sys>; - vcc10-supply = <&vcc4v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc4v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_2v0_pldo_s3>; - vcca-supply = <&vcc4v0_sys>; - - rk806_slave_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_slave_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_cpu_big1_s0: dcdc-reg1 { - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big0_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg3 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: dcdc-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_mem_s0: dcdc-reg5 { - regulator-name = "vdd_cpu_big1_mem_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - - vdd_cpu_big0_mem_s0: dcdc-reg6 { - regulator-name = "vdd_cpu_big0_mem_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: dcdc-reg7 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_mem_s0: dcdc-reg8 { - regulator-name = "vdd_cpu_lit_mem_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg10 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* reserved, unused? */ - vcc_1v8_cam_s0: pldo-reg1 { - regulator-name = "vcc_1v8_cam_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd1v8_ddr_pll_s0: pldo-reg2 { - regulator-name = "avdd1v8_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_1v8_pll_s0: pldo-reg3 { - regulator-name = "vdd_1v8_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* reserved, unused? */ - vcc_3v3_sd_s0: pldo-reg4 { - regulator-name = "vcc_3v3_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* reserved, unused? */ - vcc_2v8_cam_s0: pldo-reg5 { - regulator-name = "vcc_2v8_cam_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* unused */ - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_pll_s0: nldo-reg1 { - regulator-name = "vdd_0v75_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: nldo-reg3 { - regulator-name = "avdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* reserved, unused */ - avdd_1v2_cam_s0: nldo-reg4 { - regulator-name = "avdd_1v2_cam_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_s0: nldo-reg5 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index d6020ca790f64f8e16b27a5fcf9696c3305fbd26..8e318e624a857e513be524665c2fca0b0eeda0c3 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,32 +4,12 @@ */ #include "rk3588-u-boot.dtsi" -#include - -/ { - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; -}; &fspim2_pins { bootph-pre-ram; bootph-some-ram; }; -&pinctrl { - usb { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; @@ -71,106 +51,17 @@ status = "okay"; }; -&usbdp_phy1_u3 { - status = "okay"; -}; - &usbdp_phy0 { - orientation-switch; - mode-switch; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usbdp_phy0_typec_ss: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_ss>; - }; - - usbdp_phy0_typec_sbu: endpoint@1 { - reg = <1>; - remote-endpoint = <&usbc0_sbu>; - }; - }; -}; - -&usbdp_phy0_u3 { status = "okay"; }; &usb_host0_xhci { - usb-role-switch; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usb_host0_xhci_drd_sw: endpoint { - remote-endpoint = <&usbc0_hs>; - }; - }; }; &usb_host1_xhci { + dr_mode = "host"; status = "okay"; }; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vcc12v_dcin>; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "sink"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - , - ; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_hs: endpoint { - remote-endpoint = <&usb_host0_xhci_drd_sw>; - }; - }; - - port@1 { - reg = <1>; - usbc0_ss: endpoint { - remote-endpoint = <&usbdp_phy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - usbc0_sbu: endpoint { - remote-endpoint = <&usbdp_phy0_typec_sbu>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts deleted file mode 100644 index a0e303c3a1dc6d839528188571cb53c2759535fa..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ /dev/null @@ -1,776 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include "rk3588.dtsi" - -/ { - model = "Radxa ROCK 5 Model B"; - compatible = "radxa,rock-5b", "rockchip,rk3588"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - analog-sound { - compatible = "audio-graph-card"; - label = "rk3588-es8316"; - - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_rgb_b>; - - led_rgb_b { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; - }; - - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_vcc3v3_en>; - regulator-name = "vcc3v3_pcie2x1l0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie2x1l2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&pcie2x1l0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; - status = "okay"; -}; - -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - led_rgb_b: led-rgb-b { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_detect: hp-detect { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie2 { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_0_vcc3v3_en: pcie2-0-vcc-en { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&sdio { - max-frequency = <200000000>; - no-sd; - no-mmc; - non-removable; - bus-width = <4>; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - wakeup-source; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_pcie2x1l0>; - vqmmc-supply = <&vcc_1v8_s3>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl1"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - /* connected to USB hub, which is powered by vcc5v0_sys */ - phy-supply = <&vcc5v0_sys>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-turing-rk1.dts b/arch/arm/dts/rk3588-turing-rk1.dts deleted file mode 100644 index 7bcad28d73b84b369736841b98770f98bf70a746..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-turing-rk1.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * This device tree covers the common case where the RK1 is used as a - * "compute node" system, where the carrier board is functioning more like a - * generic backplane (with no non-autoenumerable peripherals of its own) than - * like a device that the SoM is meant to enable. - * - * Copyright (c) 2023 Sam Edwards - */ - -/dts-v1/; -#include "rk3588-turing-rk1.dtsi" - -/ { - model = "Turing Machines RK1"; - compatible = "turing,rk1", "rockchip,rk3588"; - - chosen { - stdout-path = "serial9:115200n8"; - }; -}; diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi deleted file mode 100644 index dc08da518a76d13cc4841c44a8844a348785f023..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588-turing-rk1.dtsi +++ /dev/null @@ -1,612 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree definitions for the Turing RK1 SoM. - * - * Copyright (c) 2023 Sam Edwards - * - * Based on RK3588-EVB1 devicetree - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; -#include -#include -#include "rk3588.dtsi" - -/ { - compatible = "turing,rk1", "rockchip,rk3588"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 25 95 145 195 255>; - fan-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0m2_pins &fan_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - pwms = <&pwm0 0 50000 0>; - #cooling-cells = <2>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie30_en>; - startup-delay-us = <5000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&mdio1 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <15000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l1 { - linux,pci-domain = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_reset>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - linux,pci-domain = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - fan { - fan_int: fan-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie2 { - pcie2_reset: pcie2-reset { - rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie3 { - pcie3_reset: pcie3-reset { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_pcie30_en: pcie3-reg { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - pmic@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&uart9 { - pinctrl-0 = <&uart9m0_xfer>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 992f7b5d66378627cb5976d2fb4fd69198692f4d..4623580c610206ad63eee219312223928d36c79f 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -13,8 +13,8 @@ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, <&cru ACLK_USB3OTG1>; clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "host"; - phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; power-domains = <&power RK3588_PD_USB>; @@ -32,22 +32,21 @@ }; usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", - "simple-mfd"; + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d4000 0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; - u2phy1: usb2-phy@4000 { + u2phy1: usb2phy@4000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x4000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy1_otg: otg-port { @@ -60,10 +59,7 @@ usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; + #phy-cells = <1>; clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, <&cru CLK_USBDP_PHY1_IMMORTAL>, <&cru PCLK_USBDPPHY1>, @@ -75,16 +71,10 @@ <&cru SRST_USBDP_COMBO_PHY1_PCS>, <&cru SRST_P_USBDPPHY1>; reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; status = "disabled"; - - usbdp_phy1_dp: dp-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usbdp_phy1_u3: usb3-port { - #phy-cells = <0>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi deleted file mode 100644 index 5519c1430cb7a92df91765243ac29fc7e1a2407b..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include "rk3588s.dtsi" -#include "rk3588-pinctrl.dtsi" - -/ { - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; - }; - - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 22>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S8_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s6_8ch: i2s@fddf4000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf4000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 4>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S6_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s7_8ch: i2s@fddf8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf8000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 21>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S7_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s10_8ch: i2s@fde00000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfde00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 24>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S10_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0x0f>; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, - <0 0 0 2 &pcie3x4_intc 1>, - <0 0 0 3 &pcie3x4_intc 2>, - <0 0 0 4 &pcie3x4_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <3>; - msi-map = <0x0000 &its1 0x0000 0x1000>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x4_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x2: pcie@fe160000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, - <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, - <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <1>; - max-link-speed = <3>; - msi-map = <0x1000 &its1 0x1000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, - <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, - <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, - <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, - <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, - <0 0 0 2 &pcie2x1l0_intc 1>, - <0 0 0 3 &pcie2x1l0_intc 2>, - <0 0 0 4 &pcie2x1l0_intc 3>; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its0 0x2000 0x1000>; - num-lanes = <1>; - phys = <&combphy1_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, - <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, - <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata1: sata@fe220000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe220000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, - <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy1_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; - - pcie30phy: phy@fee80000 { - compatible = "rockchip,rk3588-pcie3-phy"; - reg = <0x0 0xfee80000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; - resets = <&cru SRST_PCIE30_PHY>; - reset-names = "phy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/rk3588j.dtsi b/arch/arm/dts/rk3588j.dtsi deleted file mode 100644 index 38b9dbf38a21853d3693813c0eb835ecb83c5cab..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588j.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588.dtsi" diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts b/arch/arm/dts/rk3588s-coolpi-4b.dts deleted file mode 100644 index e037bf9db75af0402dccd26b82b50922823fe9f7..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588s-coolpi-4b.dts +++ /dev/null @@ -1,812 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction - * - */ - -/dts-v1/; - -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "RK3588S CoolPi 4 Model B"; - compatible = "coolpi,pi-4b", "rockchip,rk3588s"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc; - mmc2 = &sdio; - }; - - analog-sound { - compatible = "audio-graph-card"; - dais = <&i2s0_8ch_p0>; - label = "rk3588-es8316"; - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led0: led-green { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led1: led-red { - color = ; - default-state = "off"; - function = LED_FUNCTION_WLAN; - gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - avdd0v85_pcie20: avdd0v85-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd0v85_pcie20"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - avdd1v8_pcie20: avdd1v8-pcie20-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd1v8_pcie20"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc3v3_mipi: vcc3v3-mipi-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_mipi"; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_u3host_en>; - regulator-name = "vcc5v0_otg"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - pinctrl-0 = <&i2c6m3_xfer>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - }; -}; - -&i2c7 { - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - led { - gpio_leds: gpio-leds { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, - <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - vcc5v0_u3host_en: vcc5v0-u3host-en { - rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - bt_reset_gpio: bt-reset-pin { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-pin { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_host_irq: bt-wake-host-irq { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_pin: wifi-poweren-pin { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - pinctrl-0 = <&pwm2m1_pins>; - status = "okay"; -}; - -&pwm13 { - pinctrl-names = "active"; - pinctrl-0 = <&pwm13m2_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - no-sdio; - no-sd; - non-removable; - status = "okay"; -}; - -&sdio { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - disable-wp; - keep-power-in-suspend; - max-frequency = <150000000>; - mmc-pwrseq = <&sdio_pwrseq>; - no-sd; - no-mmc; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - status = "okay"; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -/* bt */ -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts deleted file mode 100644 index 25de4362af386747983e810d650d74c2afaa67fd..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588s-orangepi-5.dts +++ /dev/null @@ -1,667 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Xunlong Orange Pi 5"; - compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-recovery { - label = "Recovery"; - linux,code = ; - press-threshold-microvolt = <1800>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_gpio>; - - led-1 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - label = "status_led"; - linux,default-trigger = "heartbeat"; - }; - }; - - vbus_typec: vbus-typec-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-name = "vbus_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - enable-active-low; - gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - regulator-name = "vcc3v3_pcie20"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <50000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pinctrl { - gpio-func { - leds_gpio: leds-gpio { - rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - max-frequency = <150000000>; - no-mmc; - no-sdio; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim0_pins>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - system-power-controller; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi deleted file mode 100644 index 30db12c4fc82b54ca90eefafa4720bda57e0f9e4..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ /dev/null @@ -1,3447 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include "rockchip-pinconf.dtsi" - -/* - * This file is auto generated by pin2dts tool, please keep these code - * by adding changes at end of this file. - */ -&pinctrl { - auddsm { - /omit-if-no-ref/ - auddsm_pins: auddsm-pins { - rockchip,pins = - /* auddsm_ln */ - <3 RK_PA1 4 &pcfg_pull_none>, - /* auddsm_lp */ - <3 RK_PA2 4 &pcfg_pull_none>, - /* auddsm_rn */ - <3 RK_PA3 4 &pcfg_pull_none>, - /* auddsm_rp */ - <3 RK_PA4 4 &pcfg_pull_none>; - }; - }; - - bt1120 { - /omit-if-no-ref/ - bt1120_pins: bt1120-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none>, - /* bt1120_d8 */ - <4 RK_PB2 2 &pcfg_pull_none>, - /* bt1120_d9 */ - <4 RK_PB3 2 &pcfg_pull_none>, - /* bt1120_d10 */ - <4 RK_PB4 2 &pcfg_pull_none>, - /* bt1120_d11 */ - <4 RK_PB5 2 &pcfg_pull_none>, - /* bt1120_d12 */ - <4 RK_PB6 2 &pcfg_pull_none>, - /* bt1120_d13 */ - <4 RK_PB7 2 &pcfg_pull_none>, - /* bt1120_d14 */ - <4 RK_PC0 2 &pcfg_pull_none>, - /* bt1120_d15 */ - <4 RK_PC1 2 &pcfg_pull_none>; - }; - }; - - can0 { - /omit-if-no-ref/ - can0m0_pins: can0m0-pins { - rockchip,pins = - /* can0_rx_m0 */ - <0 RK_PC0 11 &pcfg_pull_none>, - /* can0_tx_m0 */ - <0 RK_PB7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can0m1_pins: can0m1-pins { - rockchip,pins = - /* can0_rx_m1 */ - <4 RK_PD5 9 &pcfg_pull_none>, - /* can0_tx_m1 */ - <4 RK_PD4 9 &pcfg_pull_none>; - }; - }; - - can1 { - /omit-if-no-ref/ - can1m0_pins: can1m0-pins { - rockchip,pins = - /* can1_rx_m0 */ - <3 RK_PB5 9 &pcfg_pull_none>, - /* can1_tx_m0 */ - <3 RK_PB6 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can1m1_pins: can1m1-pins { - rockchip,pins = - /* can1_rx_m1 */ - <4 RK_PB2 12 &pcfg_pull_none>, - /* can1_tx_m1 */ - <4 RK_PB3 12 &pcfg_pull_none>; - }; - }; - - can2 { - /omit-if-no-ref/ - can2m0_pins: can2m0-pins { - rockchip,pins = - /* can2_rx_m0 */ - <3 RK_PC4 9 &pcfg_pull_none>, - /* can2_tx_m0 */ - <3 RK_PC5 9 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - can2m1_pins: can2m1-pins { - rockchip,pins = - /* can2_rx_m1 */ - <0 RK_PD4 10 &pcfg_pull_none>, - /* can2_tx_m1 */ - <0 RK_PD5 10 &pcfg_pull_none>; - }; - }; - - cif { - /omit-if-no-ref/ - cif_clk: cif-clk { - rockchip,pins = - /* cif_clkout */ - <4 RK_PB4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_clk: cif-dvp-clk { - rockchip,pins = - /* cif_clkin */ - <4 RK_PB0 1 &pcfg_pull_none>, - /* cif_href */ - <4 RK_PB2 1 &pcfg_pull_none>, - /* cif_vsync */ - <4 RK_PB3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus16: cif-dvp-bus16 { - rockchip,pins = - /* cif_d8 */ - <3 RK_PC4 1 &pcfg_pull_none>, - /* cif_d9 */ - <3 RK_PC5 1 &pcfg_pull_none>, - /* cif_d10 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* cif_d11 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* cif_d12 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* cif_d13 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* cif_d14 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* cif_d15 */ - <3 RK_PD3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - cif_dvp_bus8: cif-dvp-bus8 { - rockchip,pins = - /* cif_d0 */ - <4 RK_PA0 1 &pcfg_pull_none>, - /* cif_d1 */ - <4 RK_PA1 1 &pcfg_pull_none>, - /* cif_d2 */ - <4 RK_PA2 1 &pcfg_pull_none>, - /* cif_d3 */ - <4 RK_PA3 1 &pcfg_pull_none>, - /* cif_d4 */ - <4 RK_PA4 1 &pcfg_pull_none>, - /* cif_d5 */ - <4 RK_PA5 1 &pcfg_pull_none>, - /* cif_d6 */ - <4 RK_PA6 1 &pcfg_pull_none>, - /* cif_d7 */ - <4 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - clk32k { - /omit-if-no-ref/ - clk32k_in: clk32k-in { - rockchip,pins = - /* clk32k_in */ - <0 RK_PB2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - clk32k_out0: clk32k-out0 { - rockchip,pins = - /* clk32k_out0 */ - <0 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - cpu { - /omit-if-no-ref/ - cpu_pins: cpu-pins { - rockchip,pins = - /* cpu_big0_avs */ - <0 RK_PD1 2 &pcfg_pull_none>, - /* cpu_big1_avs */ - <0 RK_PD5 2 &pcfg_pull_none>; - }; - }; - - ddrphych0 { - /omit-if-no-ref/ - ddrphych0_pins: ddrphych0-pins { - rockchip,pins = - /* ddrphych0_dtb0 */ - <4 RK_PA0 7 &pcfg_pull_none>, - /* ddrphych0_dtb1 */ - <4 RK_PA1 7 &pcfg_pull_none>, - /* ddrphych0_dtb2 */ - <4 RK_PA2 7 &pcfg_pull_none>, - /* ddrphych0_dtb3 */ - <4 RK_PA3 7 &pcfg_pull_none>; - }; - }; - - ddrphych1 { - /omit-if-no-ref/ - ddrphych1_pins: ddrphych1-pins { - rockchip,pins = - /* ddrphych1_dtb0 */ - <4 RK_PA4 7 &pcfg_pull_none>, - /* ddrphych1_dtb1 */ - <4 RK_PA5 7 &pcfg_pull_none>, - /* ddrphych1_dtb2 */ - <4 RK_PA6 7 &pcfg_pull_none>, - /* ddrphych1_dtb3 */ - <4 RK_PA7 7 &pcfg_pull_none>; - }; - }; - - ddrphych2 { - /omit-if-no-ref/ - ddrphych2_pins: ddrphych2-pins { - rockchip,pins = - /* ddrphych2_dtb0 */ - <4 RK_PB0 7 &pcfg_pull_none>, - /* ddrphych2_dtb1 */ - <4 RK_PB1 7 &pcfg_pull_none>, - /* ddrphych2_dtb2 */ - <4 RK_PB2 7 &pcfg_pull_none>, - /* ddrphych2_dtb3 */ - <4 RK_PB3 7 &pcfg_pull_none>; - }; - }; - - ddrphych3 { - /omit-if-no-ref/ - ddrphych3_pins: ddrphych3-pins { - rockchip,pins = - /* ddrphych3_dtb0 */ - <4 RK_PB4 7 &pcfg_pull_none>, - /* ddrphych3_dtb1 */ - <4 RK_PB5 7 &pcfg_pull_none>, - /* ddrphych3_dtb2 */ - <4 RK_PB6 7 &pcfg_pull_none>, - /* ddrphych3_dtb3 */ - <4 RK_PB7 7 &pcfg_pull_none>; - }; - }; - - dp0 { - /omit-if-no-ref/ - dp0m0_pins: dp0m0-pins { - rockchip,pins = - /* dp0_hpdin_m0 */ - <4 RK_PB4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m1_pins: dp0m1-pins { - rockchip,pins = - /* dp0_hpdin_m1 */ - <0 RK_PC4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp0m2_pins: dp0m2-pins { - rockchip,pins = - /* dp0_hpdin_m2 */ - <1 RK_PA0 5 &pcfg_pull_none>; - }; - }; - - dp1 { - /omit-if-no-ref/ - dp1m0_pins: dp1m0-pins { - rockchip,pins = - /* dp1_hpdin_m0 */ - <3 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m1_pins: dp1m1-pins { - rockchip,pins = - /* dp1_hpdin_m1 */ - <0 RK_PC5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - dp1m2_pins: dp1m2-pins { - rockchip,pins = - /* dp1_hpdin_m2 */ - <1 RK_PA1 5 &pcfg_pull_none>; - }; - }; - - emmc { - /omit-if-no-ref/ - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <2 RK_PA3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d1 */ - <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d2 */ - <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d3 */ - <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d4 */ - <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d5 */ - <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d6 */ - <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, - /* emmc_d7 */ - <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_cmd: emmc-cmd { - rockchip,pins = - /* emmc_cmd */ - <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - emmc_data_strobe: emmc-data-strobe { - rockchip,pins = - /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_down>; - }; - }; - - eth1 { - /omit-if-no-ref/ - eth1_pins: eth1-pins { - rockchip,pins = - /* eth1_refclko_25m */ - <3 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - fspi { - /omit-if-no-ref/ - fspim0_pins: fspim0-pins { - rockchip,pins = - /* fspi_clk_m0 */ - <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m0 */ - <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m0 */ - <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m0 */ - <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m0 */ - <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m0 */ - <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim0_cs1: fspim0-cs1 { - rockchip,pins = - /* fspi_cs1n_m0 */ - <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_pins: fspim2-pins { - rockchip,pins = - /* fspi_clk_m2 */ - <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, - /* fspi_cs0n_m2 */ - <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, - /* fspi_d0_m2 */ - <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d1_m2 */ - <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d2_m2 */ - <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, - /* fspi_d3_m2 */ - <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - fspim2_cs1: fspim2-cs1 { - rockchip,pins = - /* fspi_cs1n_m2 */ - <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; - }; - }; - - gmac1 { - /omit-if-no-ref/ - gmac1_miim: gmac1-miim { - rockchip,pins = - /* gmac1_mdc */ - <3 RK_PC2 1 &pcfg_pull_none>, - /* gmac1_mdio */ - <3 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_clkinout: gmac1-clkinout { - rockchip,pins = - /* gmac1_mclkinout */ - <3 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rx_bus2: gmac1-rx-bus2 { - rockchip,pins = - /* gmac1_rxd0 */ - <3 RK_PA7 1 &pcfg_pull_none>, - /* gmac1_rxd1 */ - <3 RK_PB0 1 &pcfg_pull_none>, - /* gmac1_rxdv_crs */ - <3 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_tx_bus2: gmac1-tx-bus2 { - rockchip,pins = - /* gmac1_txd0 */ - <3 RK_PB3 1 &pcfg_pull_none>, - /* gmac1_txd1 */ - <3 RK_PB4 1 &pcfg_pull_none>, - /* gmac1_txen */ - <3 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_clk: gmac1-rgmii-clk { - rockchip,pins = - /* gmac1_rxclk */ - <3 RK_PA5 1 &pcfg_pull_none>, - /* gmac1_txclk */ - <3 RK_PA4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_rgmii_bus: gmac1-rgmii-bus { - rockchip,pins = - /* gmac1_rxd2 */ - <3 RK_PA2 1 &pcfg_pull_none>, - /* gmac1_rxd3 */ - <3 RK_PA3 1 &pcfg_pull_none>, - /* gmac1_txd2 */ - <3 RK_PA0 1 &pcfg_pull_none>, - /* gmac1_txd3 */ - <3 RK_PA1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppsclk: gmac1-ppsclk { - rockchip,pins = - /* gmac1_ppsclk */ - <3 RK_PC1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ppstrig: gmac1-ppstrig { - rockchip,pins = - /* gmac1_ppstrig */ - <3 RK_PC0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { - rockchip,pins = - /* gmac1_ptp_ref_clk */ - <3 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - gmac1_txer: gmac1-txer { - rockchip,pins = - /* gmac1_txer */ - <3 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - gpu { - /omit-if-no-ref/ - gpu_pins: gpu-pins { - rockchip,pins = - /* gpu_avs */ - <0 RK_PC5 2 &pcfg_pull_none>; - }; - }; - - hdmi { - /omit-if-no-ref/ - hdmim0_rx_cec: hdmim0-rx-cec { - rockchip,pins = - /* hdmim0_rx_cec */ - <4 RK_PB5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_hpdin: hdmim0-rx-hpdin { - rockchip,pins = - /* hdmim0_rx_hpdin */ - <4 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_scl: hdmim0-rx-scl { - rockchip,pins = - /* hdmim0_rx_scl */ - <0 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_rx_sda: hdmim0-rx-sda { - rockchip,pins = - /* hdmim0_rx_sda */ - <0 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_cec: hdmim0-tx0-cec { - rockchip,pins = - /* hdmim0_tx0_cec */ - <4 RK_PC1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_hpd: hdmim0-tx0-hpd { - rockchip,pins = - /* hdmim0_tx0_hpd */ - <1 RK_PA5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_scl: hdmim0-tx0-scl { - rockchip,pins = - /* hdmim0_tx0_scl */ - <4 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx0_sda: hdmim0-tx0-sda { - rockchip,pins = - /* hdmim0_tx0_sda */ - <4 RK_PC0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim0_tx1_hpd: hdmim0-tx1-hpd { - rockchip,pins = - /* hdmim0_tx1_hpd */ - <1 RK_PA6 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim1_rx_cec: hdmim1-rx-cec { - rockchip,pins = - /* hdmim1_rx_cec */ - <3 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_hpdin: hdmim1-rx-hpdin { - rockchip,pins = - /* hdmim1_rx_hpdin */ - <3 RK_PD4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_scl: hdmim1-rx-scl { - rockchip,pins = - /* hdmim1_rx_scl */ - <3 RK_PD2 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_rx_sda: hdmim1-rx-sda { - rockchip,pins = - /* hdmim1_rx_sda */ - <3 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_cec: hdmim1-tx0-cec { - rockchip,pins = - /* hdmim1_tx0_cec */ - <0 RK_PD1 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_hpd: hdmim1-tx0-hpd { - rockchip,pins = - /* hdmim1_tx0_hpd */ - <3 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_scl: hdmim1-tx0-scl { - rockchip,pins = - /* hdmim1_tx0_scl */ - <0 RK_PD5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx0_sda: hdmim1-tx0-sda { - rockchip,pins = - /* hdmim1_tx0_sda */ - <0 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_cec: hdmim1-tx1-cec { - rockchip,pins = - /* hdmim1_tx1_cec */ - <0 RK_PD2 13 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_hpd: hdmim1-tx1-hpd { - rockchip,pins = - /* hdmim1_tx1_hpd */ - <3 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_scl: hdmim1-tx1-scl { - rockchip,pins = - /* hdmim1_tx1_scl */ - <3 RK_PC6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim1_tx1_sda: hdmim1-tx1-sda { - rockchip,pins = - /* hdmim1_tx1_sda */ - <3 RK_PC5 5 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - hdmim2_rx_cec: hdmim2-rx-cec { - rockchip,pins = - /* hdmim2_rx_cec */ - <1 RK_PB7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_hpdin: hdmim2-rx-hpdin { - rockchip,pins = - /* hdmim2_rx_hpdin */ - <1 RK_PB6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_scl: hdmim2-rx-scl { - rockchip,pins = - /* hdmim2_rx_scl */ - <1 RK_PD6 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_rx_sda: hdmim2-rx-sda { - rockchip,pins = - /* hdmim2_rx_sda */ - <1 RK_PD7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_scl: hdmim2-tx0-scl { - rockchip,pins = - /* hdmim2_tx0_scl */ - <3 RK_PC7 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx0_sda: hdmim2-tx0-sda { - rockchip,pins = - /* hdmim2_tx0_sda */ - <3 RK_PD0 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_cec: hdmim2-tx1-cec { - rockchip,pins = - /* hdmim2_tx1_cec */ - <3 RK_PC4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_scl: hdmim2-tx1-scl { - rockchip,pins = - /* hdmim2_tx1_scl */ - <1 RK_PA4 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmim2_tx1_sda: hdmim2-tx1-sda { - rockchip,pins = - /* hdmim2_tx1_sda */ - <1 RK_PA3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug0: hdmi-debug0 { - rockchip,pins = - /* hdmi_debug0 */ - <1 RK_PA7 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug1: hdmi-debug1 { - rockchip,pins = - /* hdmi_debug1 */ - <1 RK_PB0 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug2: hdmi-debug2 { - rockchip,pins = - /* hdmi_debug2 */ - <1 RK_PB1 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug3: hdmi-debug3 { - rockchip,pins = - /* hdmi_debug3 */ - <1 RK_PB2 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug4: hdmi-debug4 { - rockchip,pins = - /* hdmi_debug4 */ - <1 RK_PB3 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug5: hdmi-debug5 { - rockchip,pins = - /* hdmi_debug5 */ - <1 RK_PB4 7 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - hdmi_debug6: hdmi-debug6 { - rockchip,pins = - /* hdmi_debug6 */ - <1 RK_PA0 7 &pcfg_pull_none>; - }; - }; - - i2c0 { - /omit-if-no-ref/ - i2c0m0_xfer: i2c0m0-xfer { - rockchip,pins = - /* i2c0_scl_m0 */ - <0 RK_PB3 2 &pcfg_pull_none_smt>, - /* i2c0_sda_m0 */ - <0 RK_PA6 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c0m2_xfer: i2c0m2-xfer { - rockchip,pins = - /* i2c0_scl_m2 */ - <0 RK_PD1 3 &pcfg_pull_none_smt>, - /* i2c0_sda_m2 */ - <0 RK_PD2 3 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - /omit-if-no-ref/ - i2c1m0_xfer: i2c1m0-xfer { - rockchip,pins = - /* i2c1_scl_m0 */ - <0 RK_PB5 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m0 */ - <0 RK_PB6 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m1_xfer: i2c1m1-xfer { - rockchip,pins = - /* i2c1_scl_m1 */ - <0 RK_PB0 2 &pcfg_pull_none_smt>, - /* i2c1_sda_m1 */ - <0 RK_PB1 2 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m2_xfer: i2c1m2-xfer { - rockchip,pins = - /* i2c1_scl_m2 */ - <0 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m2 */ - <0 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m3_xfer: i2c1m3-xfer { - rockchip,pins = - /* i2c1_scl_m3 */ - <2 RK_PD4 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m3 */ - <2 RK_PD5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c1m4_xfer: i2c1m4-xfer { - rockchip,pins = - /* i2c1_scl_m4 */ - <1 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c1_sda_m4 */ - <1 RK_PD3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - /omit-if-no-ref/ - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2_scl_m0 */ - <0 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m0 */ - <0 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m2_xfer: i2c2m2-xfer { - rockchip,pins = - /* i2c2_scl_m2 */ - <2 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m2 */ - <2 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m3_xfer: i2c2m3-xfer { - rockchip,pins = - /* i2c2_scl_m3 */ - <1 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m3 */ - <1 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c2m4_xfer: i2c2m4-xfer { - rockchip,pins = - /* i2c2_scl_m4 */ - <1 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c2_sda_m4 */ - <1 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - /omit-if-no-ref/ - i2c3m0_xfer: i2c3m0-xfer { - rockchip,pins = - /* i2c3_scl_m0 */ - <1 RK_PC1 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m0 */ - <1 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m1_xfer: i2c3m1-xfer { - rockchip,pins = - /* i2c3_scl_m1 */ - <3 RK_PB7 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m1 */ - <3 RK_PC0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m2_xfer: i2c3m2-xfer { - rockchip,pins = - /* i2c3_scl_m2 */ - <4 RK_PA4 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m2 */ - <4 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c3m4_xfer: i2c3m4-xfer { - rockchip,pins = - /* i2c3_scl_m4 */ - <4 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c3_sda_m4 */ - <4 RK_PD1 9 &pcfg_pull_none_smt>; - }; - }; - - i2c4 { - /omit-if-no-ref/ - i2c4m0_xfer: i2c4m0-xfer { - rockchip,pins = - /* i2c4_scl_m0 */ - <3 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m0 */ - <3 RK_PA5 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m2_xfer: i2c4m2-xfer { - rockchip,pins = - /* i2c4_scl_m2 */ - <0 RK_PC5 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m2 */ - <0 RK_PC4 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m3_xfer: i2c4m3-xfer { - rockchip,pins = - /* i2c4_scl_m3 */ - <1 RK_PA3 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m3 */ - <1 RK_PA2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c4m4_xfer: i2c4m4-xfer { - rockchip,pins = - /* i2c4_scl_m4 */ - <1 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c4_sda_m4 */ - <1 RK_PC6 9 &pcfg_pull_none_smt>; - }; - }; - - i2c5 { - /omit-if-no-ref/ - i2c5m0_xfer: i2c5m0-xfer { - rockchip,pins = - /* i2c5_scl_m0 */ - <3 RK_PC7 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m0 */ - <3 RK_PD0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m1_xfer: i2c5m1-xfer { - rockchip,pins = - /* i2c5_scl_m1 */ - <4 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m1 */ - <4 RK_PB7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m2_xfer: i2c5m2-xfer { - rockchip,pins = - /* i2c5_scl_m2 */ - <4 RK_PA6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m2 */ - <4 RK_PA7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c5m3_xfer: i2c5m3-xfer { - rockchip,pins = - /* i2c5_scl_m3 */ - <1 RK_PB6 9 &pcfg_pull_none_smt>, - /* i2c5_sda_m3 */ - <1 RK_PB7 9 &pcfg_pull_none_smt>; - }; - }; - - i2c6 { - /omit-if-no-ref/ - i2c6m0_xfer: i2c6m0-xfer { - rockchip,pins = - /* i2c6_scl_m0 */ - <0 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m0 */ - <0 RK_PC7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m1_xfer: i2c6m1-xfer { - rockchip,pins = - /* i2c6_scl_m1 */ - <1 RK_PC3 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m1 */ - <1 RK_PC2 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m3_xfer: i2c6m3-xfer { - rockchip,pins = - /* i2c6_scl_m3 */ - <4 RK_PB1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m3 */ - <4 RK_PB0 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c6m4_xfer: i2c6m4-xfer { - rockchip,pins = - /* i2c6_scl_m4 */ - <3 RK_PA1 9 &pcfg_pull_none_smt>, - /* i2c6_sda_m4 */ - <3 RK_PA0 9 &pcfg_pull_none_smt>; - }; - }; - - i2c7 { - /omit-if-no-ref/ - i2c7m0_xfer: i2c7m0-xfer { - rockchip,pins = - /* i2c7_scl_m0 */ - <1 RK_PD0 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m0 */ - <1 RK_PD1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m2_xfer: i2c7m2-xfer { - rockchip,pins = - /* i2c7_scl_m2 */ - <3 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m2 */ - <3 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c7m3_xfer: i2c7m3-xfer { - rockchip,pins = - /* i2c7_scl_m3 */ - <4 RK_PB2 9 &pcfg_pull_none_smt>, - /* i2c7_sda_m3 */ - <4 RK_PB3 9 &pcfg_pull_none_smt>; - }; - }; - - i2c8 { - /omit-if-no-ref/ - i2c8m0_xfer: i2c8m0-xfer { - rockchip,pins = - /* i2c8_scl_m0 */ - <4 RK_PD2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m0 */ - <4 RK_PD3 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m2_xfer: i2c8m2-xfer { - rockchip,pins = - /* i2c8_scl_m2 */ - <1 RK_PD6 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m2 */ - <1 RK_PD7 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m3_xfer: i2c8m3-xfer { - rockchip,pins = - /* i2c8_scl_m3 */ - <4 RK_PC0 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m3 */ - <4 RK_PC1 9 &pcfg_pull_none_smt>; - }; - - /omit-if-no-ref/ - i2c8m4_xfer: i2c8m4-xfer { - rockchip,pins = - /* i2c8_scl_m4 */ - <3 RK_PC2 9 &pcfg_pull_none_smt>, - /* i2c8_sda_m4 */ - <3 RK_PC3 9 &pcfg_pull_none_smt>; - }; - }; - - i2s0 { - /omit-if-no-ref/ - i2s0_lrck: i2s0-lrck { - rockchip,pins = - /* i2s0_lrck */ - <1 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_mclk: i2s0-mclk { - rockchip,pins = - /* i2s0_mclk */ - <1 RK_PC2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sclk: i2s0-sclk { - rockchip,pins = - /* i2s0_sclk */ - <1 RK_PC3 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi0: i2s0-sdi0 { - rockchip,pins = - /* i2s0_sdi0 */ - <1 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi1: i2s0-sdi1 { - rockchip,pins = - /* i2s0_sdi1 */ - <1 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi2: i2s0-sdi2 { - rockchip,pins = - /* i2s0_sdi2 */ - <1 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdi3: i2s0-sdi3 { - rockchip,pins = - /* i2s0_sdi3 */ - <1 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo0: i2s0-sdo0 { - rockchip,pins = - /* i2s0_sdo0 */ - <1 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo1: i2s0-sdo1 { - rockchip,pins = - /* i2s0_sdo1 */ - <1 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo2: i2s0-sdo2 { - rockchip,pins = - /* i2s0_sdo2 */ - <1 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s0_sdo3: i2s0-sdo3 { - rockchip,pins = - /* i2s0_sdo3 */ - <1 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - i2s1 { - /omit-if-no-ref/ - i2s1m0_lrck: i2s1m0-lrck { - rockchip,pins = - /* i2s1m0_lrck */ - <4 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_mclk: i2s1m0-mclk { - rockchip,pins = - /* i2s1m0_mclk */ - <4 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sclk: i2s1m0-sclk { - rockchip,pins = - /* i2s1m0_sclk */ - <4 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi0: i2s1m0-sdi0 { - rockchip,pins = - /* i2s1m0_sdi0 */ - <4 RK_PA5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi1: i2s1m0-sdi1 { - rockchip,pins = - /* i2s1m0_sdi1 */ - <4 RK_PA6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi2: i2s1m0-sdi2 { - rockchip,pins = - /* i2s1m0_sdi2 */ - <4 RK_PA7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdi3: i2s1m0-sdi3 { - rockchip,pins = - /* i2s1m0_sdi3 */ - <4 RK_PB0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo0: i2s1m0-sdo0 { - rockchip,pins = - /* i2s1m0_sdo0 */ - <4 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo1: i2s1m0-sdo1 { - rockchip,pins = - /* i2s1m0_sdo1 */ - <4 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo2: i2s1m0-sdo2 { - rockchip,pins = - /* i2s1m0_sdo2 */ - <4 RK_PB3 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m0_sdo3: i2s1m0-sdo3 { - rockchip,pins = - /* i2s1m0_sdo3 */ - <4 RK_PB4 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - i2s1m1_lrck: i2s1m1-lrck { - rockchip,pins = - /* i2s1m1_lrck */ - <0 RK_PB7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_mclk: i2s1m1-mclk { - rockchip,pins = - /* i2s1m1_mclk */ - <0 RK_PB5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sclk: i2s1m1-sclk { - rockchip,pins = - /* i2s1m1_sclk */ - <0 RK_PB6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi0: i2s1m1-sdi0 { - rockchip,pins = - /* i2s1m1_sdi0 */ - <0 RK_PC5 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi1: i2s1m1-sdi1 { - rockchip,pins = - /* i2s1m1_sdi1 */ - <0 RK_PC6 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi2: i2s1m1-sdi2 { - rockchip,pins = - /* i2s1m1_sdi2 */ - <0 RK_PC7 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdi3: i2s1m1-sdi3 { - rockchip,pins = - /* i2s1m1_sdi3 */ - <0 RK_PD0 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo0: i2s1m1-sdo0 { - rockchip,pins = - /* i2s1m1_sdo0 */ - <0 RK_PD1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo1: i2s1m1-sdo1 { - rockchip,pins = - /* i2s1m1_sdo1 */ - <0 RK_PD2 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo2: i2s1m1-sdo2 { - rockchip,pins = - /* i2s1m1_sdo2 */ - <0 RK_PD4 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s1m1_sdo3: i2s1m1-sdo3 { - rockchip,pins = - /* i2s1m1_sdo3 */ - <0 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2s2 { - /omit-if-no-ref/ - i2s2m0_lrck: i2s2m0-lrck { - rockchip,pins = - /* i2s2m0_lrck */ - <2 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_mclk: i2s2m0-mclk { - rockchip,pins = - /* i2s2m0_mclk */ - <2 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sclk: i2s2m0-sclk { - rockchip,pins = - /* i2s2m0_sclk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdi: i2s2m0-sdi { - rockchip,pins = - /* i2s2m0_sdi */ - <2 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m0_sdo: i2s2m0-sdo { - rockchip,pins = - /* i2s2m0_sdo */ - <4 RK_PC3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_lrck: i2s2m1-lrck { - rockchip,pins = - /* i2s2m1_lrck */ - <3 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_mclk: i2s2m1-mclk { - rockchip,pins = - /* i2s2m1_mclk */ - <3 RK_PB4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sclk: i2s2m1-sclk { - rockchip,pins = - /* i2s2m1_sclk */ - <3 RK_PB5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdi: i2s2m1-sdi { - rockchip,pins = - /* i2s2m1_sdi */ - <3 RK_PB2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s2m1_sdo: i2s2m1-sdo { - rockchip,pins = - /* i2s2m1_sdo */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - }; - - i2s3 { - /omit-if-no-ref/ - i2s3_lrck: i2s3-lrck { - rockchip,pins = - /* i2s3_lrck */ - <3 RK_PA2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_mclk: i2s3-mclk { - rockchip,pins = - /* i2s3_mclk */ - <3 RK_PA0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sclk: i2s3-sclk { - rockchip,pins = - /* i2s3_sclk */ - <3 RK_PA1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdi: i2s3-sdi { - rockchip,pins = - /* i2s3_sdi */ - <3 RK_PA4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - i2s3_sdo: i2s3-sdo { - rockchip,pins = - /* i2s3_sdo */ - <3 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - jtag { - /omit-if-no-ref/ - jtagm0_pins: jtagm0-pins { - rockchip,pins = - /* jtag_tck_m0 */ - <4 RK_PD2 5 &pcfg_pull_none>, - /* jtag_tms_m0 */ - <4 RK_PD3 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm1_pins: jtagm1-pins { - rockchip,pins = - /* jtag_tck_m1 */ - <4 RK_PD0 5 &pcfg_pull_none>, - /* jtag_tms_m1 */ - <4 RK_PD1 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - jtagm2_pins: jtagm2-pins { - rockchip,pins = - /* jtag_tck_m2 */ - <0 RK_PB5 2 &pcfg_pull_none>, - /* jtag_tms_m2 */ - <0 RK_PB6 2 &pcfg_pull_none>; - }; - }; - - litcpu { - /omit-if-no-ref/ - litcpu_pins: litcpu-pins { - rockchip,pins = - /* litcpu_avs */ - <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - mcu { - /omit-if-no-ref/ - mcum0_pins: mcum0-pins { - rockchip,pins = - /* mcu_jtag_tck_m0 */ - <4 RK_PD4 5 &pcfg_pull_none>, - /* mcu_jtag_tms_m0 */ - <4 RK_PD5 5 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mcum1_pins: mcum1-pins { - rockchip,pins = - /* mcu_jtag_tck_m1 */ - <3 RK_PD4 6 &pcfg_pull_none>, - /* mcu_jtag_tms_m1 */ - <3 RK_PD5 6 &pcfg_pull_none>; - }; - }; - - mipi { - /omit-if-no-ref/ - mipim0_camera0_clk: mipim0-camera0-clk { - rockchip,pins = - /* mipim0_camera0_clk */ - <4 RK_PB1 1 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera1_clk: mipim0-camera1-clk { - rockchip,pins = - /* mipim0_camera1_clk */ - <1 RK_PB6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera2_clk: mipim0-camera2-clk { - rockchip,pins = - /* mipim0_camera2_clk */ - <1 RK_PB7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera3_clk: mipim0-camera3-clk { - rockchip,pins = - /* mipim0_camera3_clk */ - <1 RK_PD6 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim0_camera4_clk: mipim0-camera4-clk { - rockchip,pins = - /* mipim0_camera4_clk */ - <1 RK_PD7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera0_clk: mipim1-camera0-clk { - rockchip,pins = - /* mipim1_camera0_clk */ - <3 RK_PA5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera1_clk: mipim1-camera1-clk { - rockchip,pins = - /* mipim1_camera1_clk */ - <3 RK_PA6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera2_clk: mipim1-camera2-clk { - rockchip,pins = - /* mipim1_camera2_clk */ - <3 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera3_clk: mipim1-camera3-clk { - rockchip,pins = - /* mipim1_camera3_clk */ - <3 RK_PB0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipim1_camera4_clk: mipim1-camera4-clk { - rockchip,pins = - /* mipim1_camera4_clk */ - <3 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te0: mipi-te0 { - rockchip,pins = - /* mipi_te0 */ - <3 RK_PC2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - mipi_te1: mipi-te1 { - rockchip,pins = - /* mipi_te1 */ - <3 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - npu { - /omit-if-no-ref/ - npu_pins: npu-pins { - rockchip,pins = - /* npu_avs */ - <0 RK_PC6 2 &pcfg_pull_none>; - }; - }; - - pcie20x1 { - /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m0 */ - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { - rockchip,pins = - /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, - /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, - /* pcie20x1_2_waken_m1 */ - <4 RK_PC0 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { - rockchip,pins = - /* pcie20x1_2_button_rstn */ - <4 RK_PB3 4 &pcfg_pull_none>; - }; - }; - - pcie30phy { - /omit-if-no-ref/ - pcie30phy_pins: pcie30phy-pins { - rockchip,pins = - /* pcie30phy_dtb0 */ - <1 RK_PC4 4 &pcfg_pull_none>, - /* pcie30phy_dtb1 */ - <1 RK_PD1 4 &pcfg_pull_none>; - }; - }; - - pcie30x1 { - /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, - /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, - /* pcie30x1_1_waken_m0 */ - <0 RK_PB6 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m1 */ - <4 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { - rockchip,pins = - /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, - /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, - /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, - /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, - /* pcie30x1_1_waken_m2 */ - <1 RK_PA1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { - rockchip,pins = - /* pcie30x1_0_button_rstn */ - <4 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { - rockchip,pins = - /* pcie30x1_1_button_rstn */ - <4 RK_PB2 4 &pcfg_pull_none>; - }; - }; - - pcie30x2 { - /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, - /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, - /* pcie30x2_waken_m0 */ - <0 RK_PD2 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x2_waken_m1 */ - <4 RK_PA7 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, - /* pcie30x2_waken_m2 */ - <3 RK_PD3 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { - rockchip,pins = - /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, - /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, - /* pcie30x2_waken_m3 */ - <1 RK_PB6 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x2_button_rstn: pcie30x2-button-rstn { - rockchip,pins = - /* pcie30x2_button_rstn */ - <3 RK_PC1 4 &pcfg_pull_none>; - }; - }; - - pcie30x4 { - /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, - /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, - /* pcie30x4_waken_m0 */ - <0 RK_PC7 12 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m1 */ - <4 RK_PB5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, - /* pcie30x4_waken_m2 */ - <3 RK_PC5 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { - rockchip,pins = - /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, - /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, - /* pcie30x4_waken_m3 */ - <1 RK_PB1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pcie30x4_button_rstn: pcie30x4-button-rstn { - rockchip,pins = - /* pcie30x4_button_rstn */ - <3 RK_PD5 4 &pcfg_pull_none>; - }; - }; - - pdm0 { - /omit-if-no-ref/ - pdm0m0_clk: pdm0m0-clk { - rockchip,pins = - /* pdm0_clk0_m0 */ - <1 RK_PC6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_clk1: pdm0m0-clk1 { - rockchip,pins = - /* pdm0m0_clk1 */ - <1 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi0: pdm0m0-sdi0 { - rockchip,pins = - /* pdm0m0_sdi0 */ - <1 RK_PD5 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi1: pdm0m0-sdi1 { - rockchip,pins = - /* pdm0m0_sdi1 */ - <1 RK_PD1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi2: pdm0m0-sdi2 { - rockchip,pins = - /* pdm0m0_sdi2 */ - <1 RK_PD2 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m0_sdi3: pdm0m0-sdi3 { - rockchip,pins = - /* pdm0m0_sdi3 */ - <1 RK_PD3 3 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm0m1_clk: pdm0m1-clk { - rockchip,pins = - /* pdm0_clk0_m1 */ - <0 RK_PC0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_clk1: pdm0m1-clk1 { - rockchip,pins = - /* pdm0m1_clk1 */ - <0 RK_PC4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi0: pdm0m1-sdi0 { - rockchip,pins = - /* pdm0m1_sdi0 */ - <0 RK_PC7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi1: pdm0m1-sdi1 { - rockchip,pins = - /* pdm0m1_sdi1 */ - <0 RK_PD0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi2: pdm0m1-sdi2 { - rockchip,pins = - /* pdm0m1_sdi2 */ - <0 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm0m1_sdi3: pdm0m1-sdi3 { - rockchip,pins = - /* pdm0m1_sdi3 */ - <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pdm1 { - /omit-if-no-ref/ - pdm1m0_clk: pdm1m0-clk { - rockchip,pins = - /* pdm1_clk0_m0 */ - <4 RK_PD5 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_clk1: pdm1m0-clk1 { - rockchip,pins = - /* pdm1m0_clk1 */ - <4 RK_PD4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi0: pdm1m0-sdi0 { - rockchip,pins = - /* pdm1m0_sdi0 */ - <4 RK_PD3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi1: pdm1m0-sdi1 { - rockchip,pins = - /* pdm1m0_sdi1 */ - <4 RK_PD2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi2: pdm1m0-sdi2 { - rockchip,pins = - /* pdm1m0_sdi2 */ - <4 RK_PD1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m0_sdi3: pdm1m0-sdi3 { - rockchip,pins = - /* pdm1m0_sdi3 */ - <4 RK_PD0 2 &pcfg_pull_none>; - }; - /omit-if-no-ref/ - pdm1m1_clk: pdm1m1-clk { - rockchip,pins = - /* pdm1_clk0_m1 */ - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_clk1: pdm1m1-clk1 { - rockchip,pins = - /* pdm1m1_clk1 */ - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi0: pdm1m1-sdi0 { - rockchip,pins = - /* pdm1m1_sdi0 */ - <1 RK_PA7 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi1: pdm1m1-sdi1 { - rockchip,pins = - /* pdm1m1_sdi1 */ - <1 RK_PB0 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi2: pdm1m1-sdi2 { - rockchip,pins = - /* pdm1m1_sdi2 */ - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pdm1m1_sdi3: pdm1m1-sdi3 { - rockchip,pins = - /* pdm1m1_sdi3 */ - <1 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - pmic { - /omit-if-no-ref/ - pmic_pins: pmic-pins { - rockchip,pins = - /* pmic_int_l */ - <0 RK_PA7 0 &pcfg_pull_up>, - /* pmic_sleep1 */ - <0 RK_PA2 1 &pcfg_pull_none>, - /* pmic_sleep2 */ - <0 RK_PA3 1 &pcfg_pull_none>, - /* pmic_sleep3 */ - <0 RK_PC1 1 &pcfg_pull_none>, - /* pmic_sleep4 */ - <0 RK_PC2 1 &pcfg_pull_none>, - /* pmic_sleep5 */ - <0 RK_PC3 1 &pcfg_pull_none>, - /* pmic_sleep6 */ - <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pmu { - /omit-if-no-ref/ - pmu_pins: pmu-pins { - rockchip,pins = - /* pmu_debug */ - <0 RK_PA5 3 &pcfg_pull_none>; - }; - }; - - pwm0 { - /omit-if-no-ref/ - pwm0m0_pins: pwm0m0-pins { - rockchip,pins = - /* pwm0_m0 */ - <0 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m1_pins: pwm0m1-pins { - rockchip,pins = - /* pwm0_m1 */ - <1 RK_PD2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm0m2_pins: pwm0m2-pins { - rockchip,pins = - /* pwm0_m2 */ - <1 RK_PA2 11 &pcfg_pull_none>; - }; - }; - - pwm1 { - /omit-if-no-ref/ - pwm1m0_pins: pwm1m0-pins { - rockchip,pins = - /* pwm1_m0 */ - <0 RK_PC0 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m1_pins: pwm1m1-pins { - rockchip,pins = - /* pwm1_m1 */ - <1 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm1m2_pins: pwm1m2-pins { - rockchip,pins = - /* pwm1_m2 */ - <1 RK_PA3 11 &pcfg_pull_none>; - }; - }; - - pwm2 { - /omit-if-no-ref/ - pwm2m0_pins: pwm2m0-pins { - rockchip,pins = - /* pwm2_m0 */ - <0 RK_PC4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm2m1_pins: pwm2m1-pins { - rockchip,pins = - /* pwm2_m1 */ - <3 RK_PB1 11 &pcfg_pull_none>; - }; - }; - - pwm3 { - /omit-if-no-ref/ - pwm3m0_pins: pwm3m0-pins { - rockchip,pins = - /* pwm3_ir_m0 */ - <0 RK_PD4 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m1_pins: pwm3m1-pins { - rockchip,pins = - /* pwm3_ir_m1 */ - <3 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m2_pins: pwm3m2-pins { - rockchip,pins = - /* pwm3_ir_m2 */ - <1 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm3m3_pins: pwm3m3-pins { - rockchip,pins = - /* pwm3_ir_m3 */ - <1 RK_PA7 11 &pcfg_pull_none>; - }; - }; - - pwm4 { - /omit-if-no-ref/ - pwm4m0_pins: pwm4m0-pins { - rockchip,pins = - /* pwm4_m0 */ - <0 RK_PC5 11 &pcfg_pull_none>; - }; - }; - - pwm5 { - /omit-if-no-ref/ - pwm5m0_pins: pwm5m0-pins { - rockchip,pins = - /* pwm5_m0 */ - <0 RK_PB1 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm5m1_pins: pwm5m1-pins { - rockchip,pins = - /* pwm5_m1 */ - <0 RK_PC6 11 &pcfg_pull_none>; - }; - }; - - pwm6 { - /omit-if-no-ref/ - pwm6m0_pins: pwm6m0-pins { - rockchip,pins = - /* pwm6_m0 */ - <0 RK_PC7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm6m1_pins: pwm6m1-pins { - rockchip,pins = - /* pwm6_m1 */ - <4 RK_PC1 11 &pcfg_pull_none>; - }; - }; - - pwm7 { - /omit-if-no-ref/ - pwm7m0_pins: pwm7m0-pins { - rockchip,pins = - /* pwm7_ir_m0 */ - <0 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m1_pins: pwm7m1-pins { - rockchip,pins = - /* pwm7_ir_m1 */ - <4 RK_PD4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm7m2_pins: pwm7m2-pins { - rockchip,pins = - /* pwm7_ir_m2 */ - <1 RK_PC3 11 &pcfg_pull_none>; - }; - }; - - pwm8 { - /omit-if-no-ref/ - pwm8m0_pins: pwm8m0-pins { - rockchip,pins = - /* pwm8_m0 */ - <3 RK_PA7 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m1_pins: pwm8m1-pins { - rockchip,pins = - /* pwm8_m1 */ - <4 RK_PD0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm8m2_pins: pwm8m2-pins { - rockchip,pins = - /* pwm8_m2 */ - <3 RK_PD0 11 &pcfg_pull_none>; - }; - }; - - pwm9 { - /omit-if-no-ref/ - pwm9m0_pins: pwm9m0-pins { - rockchip,pins = - /* pwm9_m0 */ - <3 RK_PB0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m1_pins: pwm9m1-pins { - rockchip,pins = - /* pwm9_m1 */ - <4 RK_PD1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm9m2_pins: pwm9m2-pins { - rockchip,pins = - /* pwm9_m2 */ - <3 RK_PD1 11 &pcfg_pull_none>; - }; - }; - - pwm10 { - /omit-if-no-ref/ - pwm10m0_pins: pwm10m0-pins { - rockchip,pins = - /* pwm10_m0 */ - <3 RK_PA0 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m1_pins: pwm10m1-pins { - rockchip,pins = - /* pwm10_m1 */ - <4 RK_PD3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm10m2_pins: pwm10m2-pins { - rockchip,pins = - /* pwm10_m2 */ - <3 RK_PD3 11 &pcfg_pull_none>; - }; - }; - - pwm11 { - /omit-if-no-ref/ - pwm11m0_pins: pwm11m0-pins { - rockchip,pins = - /* pwm11_ir_m0 */ - <3 RK_PA1 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m1_pins: pwm11m1-pins { - rockchip,pins = - /* pwm11_ir_m1 */ - <4 RK_PB4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m2_pins: pwm11m2-pins { - rockchip,pins = - /* pwm11_ir_m2 */ - <1 RK_PC4 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm11m3_pins: pwm11m3-pins { - rockchip,pins = - /* pwm11_ir_m3 */ - <3 RK_PD5 11 &pcfg_pull_none>; - }; - }; - - pwm12 { - /omit-if-no-ref/ - pwm12m0_pins: pwm12m0-pins { - rockchip,pins = - /* pwm12_m0 */ - <3 RK_PB5 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm12m1_pins: pwm12m1-pins { - rockchip,pins = - /* pwm12_m1 */ - <4 RK_PB5 11 &pcfg_pull_none>; - }; - }; - - pwm13 { - /omit-if-no-ref/ - pwm13m0_pins: pwm13m0-pins { - rockchip,pins = - /* pwm13_m0 */ - <3 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m1_pins: pwm13m1-pins { - rockchip,pins = - /* pwm13_m1 */ - <4 RK_PB6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm13m2_pins: pwm13m2-pins { - rockchip,pins = - /* pwm13_m2 */ - <1 RK_PB7 11 &pcfg_pull_none>; - }; - }; - - pwm14 { - /omit-if-no-ref/ - pwm14m0_pins: pwm14m0-pins { - rockchip,pins = - /* pwm14_m0 */ - <3 RK_PC2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m1_pins: pwm14m1-pins { - rockchip,pins = - /* pwm14_m1 */ - <4 RK_PB2 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm14m2_pins: pwm14m2-pins { - rockchip,pins = - /* pwm14_m2 */ - <1 RK_PD6 11 &pcfg_pull_none>; - }; - }; - - pwm15 { - /omit-if-no-ref/ - pwm15m0_pins: pwm15m0-pins { - rockchip,pins = - /* pwm15_ir_m0 */ - <3 RK_PC3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m1_pins: pwm15m1-pins { - rockchip,pins = - /* pwm15_ir_m1 */ - <4 RK_PB3 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m2_pins: pwm15m2-pins { - rockchip,pins = - /* pwm15_ir_m2 */ - <1 RK_PC6 11 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - pwm15m3_pins: pwm15m3-pins { - rockchip,pins = - /* pwm15_ir_m3 */ - <1 RK_PD7 11 &pcfg_pull_none>; - }; - }; - - refclk { - /omit-if-no-ref/ - refclk_pins: refclk-pins { - rockchip,pins = - /* refclk_out */ - <0 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - sata { - /omit-if-no-ref/ - sata_pins: sata-pins { - rockchip,pins = - /* sata_cp_pod */ - <0 RK_PC6 13 &pcfg_pull_none>, - /* sata_cpdet */ - <0 RK_PD4 13 &pcfg_pull_none>, - /* sata_mp_switch */ - <0 RK_PD5 13 &pcfg_pull_none>; - }; - }; - - sata0 { - /omit-if-no-ref/ - sata0m0_pins: sata0m0-pins { - rockchip,pins = - /* sata0_act_led_m0 */ - <4 RK_PB6 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata0m1_pins: sata0m1-pins { - rockchip,pins = - /* sata0_act_led_m1 */ - <1 RK_PB3 6 &pcfg_pull_none>; - }; - }; - - sata1 { - /omit-if-no-ref/ - sata1m0_pins: sata1m0-pins { - rockchip,pins = - /* sata1_act_led_m0 */ - <4 RK_PB5 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata1m1_pins: sata1m1-pins { - rockchip,pins = - /* sata1_act_led_m1 */ - <1 RK_PA1 6 &pcfg_pull_none>; - }; - }; - - sata2 { - /omit-if-no-ref/ - sata2m0_pins: sata2m0-pins { - rockchip,pins = - /* sata2_act_led_m0 */ - <4 RK_PB1 6 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - sata2m1_pins: sata2m1-pins { - rockchip,pins = - /* sata2_act_led_m1 */ - <1 RK_PB7 6 &pcfg_pull_none>; - }; - }; - - sdio { - /omit-if-no-ref/ - sdiom1_pins: sdiom1-pins { - rockchip,pins = - /* sdio_clk_m1 */ - <3 RK_PA5 2 &pcfg_pull_none>, - /* sdio_cmd_m1 */ - <3 RK_PA4 2 &pcfg_pull_none>, - /* sdio_d0_m1 */ - <3 RK_PA0 2 &pcfg_pull_none>, - /* sdio_d1_m1 */ - <3 RK_PA1 2 &pcfg_pull_none>, - /* sdio_d2_m1 */ - <3 RK_PA2 2 &pcfg_pull_none>, - /* sdio_d3_m1 */ - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - /omit-if-no-ref/ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - /* sdmmc_d0 */ - <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d1 */ - <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d2 */ - <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, - /* sdmmc_d3 */ - <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_clk: sdmmc-clk { - rockchip,pins = - /* sdmmc_clk */ - <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - /* sdmmc_cmd */ - <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; - }; - - /omit-if-no-ref/ - sdmmc_det: sdmmc-det { - rockchip,pins = - /* sdmmc_det */ - <0 RK_PA4 1 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = - /* sdmmc_pwren */ - <0 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - spdif0 { - /omit-if-no-ref/ - spdif0m0_tx: spdif0m0-tx { - rockchip,pins = - /* spdif0m0_tx */ - <1 RK_PB6 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif0m1_tx: spdif0m1-tx { - rockchip,pins = - /* spdif0m1_tx */ - <4 RK_PB4 6 &pcfg_pull_none>; - }; - }; - - spdif1 { - /omit-if-no-ref/ - spdif1m0_tx: spdif1m0-tx { - rockchip,pins = - /* spdif1m0_tx */ - <1 RK_PB7 3 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m1_tx: spdif1m1-tx { - rockchip,pins = - /* spdif1m1_tx */ - <4 RK_PB1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - spdif1m2_tx: spdif1m2-tx { - rockchip,pins = - /* spdif1m2_tx */ - <4 RK_PC1 3 &pcfg_pull_none>; - }; - }; - - spi0 { - /omit-if-no-ref/ - spi0m0_pins: spi0m0-pins { - rockchip,pins = - /* spi0_clk_m0 */ - <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m0 */ - <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m0 */ - <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs0: spi0m0-cs0 { - rockchip,pins = - /* spi0_cs0_m0 */ - <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m0_cs1: spi0m0-cs1 { - rockchip,pins = - /* spi0_cs1_m0 */ - <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m1_pins: spi0m1-pins { - rockchip,pins = - /* spi0_clk_m1 */ - <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m1 */ - <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m1 */ - <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs0: spi0m1-cs0 { - rockchip,pins = - /* spi0_cs0_m1 */ - <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m1_cs1: spi0m1-cs1 { - rockchip,pins = - /* spi0_cs1_m1 */ - <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m2_pins: spi0m2-pins { - rockchip,pins = - /* spi0_clk_m2 */ - <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m2 */ - <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m2 */ - <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs0: spi0m2-cs0 { - rockchip,pins = - /* spi0_cs0_m2 */ - <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m2_cs1: spi0m2-cs1 { - rockchip,pins = - /* spi0_cs1_m2 */ - <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; - }; - /omit-if-no-ref/ - spi0m3_pins: spi0m3-pins { - rockchip,pins = - /* spi0_clk_m3 */ - <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi0_miso_m3 */ - <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, - /* spi0_mosi_m3 */ - <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs0: spi0m3-cs0 { - rockchip,pins = - /* spi0_cs0_m3 */ - <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi0m3_cs1: spi0m3-cs1 { - rockchip,pins = - /* spi0_cs1_m3 */ - <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi1 { - /omit-if-no-ref/ - spi1m1_pins: spi1m1-pins { - rockchip,pins = - /* spi1_clk_m1 */ - <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m1 */ - <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m1 */ - <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs0: spi1m1-cs0 { - rockchip,pins = - /* spi1_cs0_m1 */ - <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m1_cs1: spi1m1-cs1 { - rockchip,pins = - /* spi1_cs1_m1 */ - <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_pins: spi1m2-pins { - rockchip,pins = - /* spi1_clk_m2 */ - <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, - /* spi1_miso_m2 */ - <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi1_mosi_m2 */ - <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs0: spi1m2-cs0 { - rockchip,pins = - /* spi1_cs0_m2 */ - <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi1m2_cs1: spi1m2-cs1 { - rockchip,pins = - /* spi1_cs1_m2 */ - <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi2 { - /omit-if-no-ref/ - spi2m0_pins: spi2m0-pins { - rockchip,pins = - /* spi2_clk_m0 */ - <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m0 */ - <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m0 */ - <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs0: spi2m0-cs0 { - rockchip,pins = - /* spi2_cs0_m0 */ - <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m0_cs1: spi2m0-cs1 { - rockchip,pins = - /* spi2_cs1_m0 */ - <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_pins: spi2m1-pins { - rockchip,pins = - /* spi2_clk_m1 */ - <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m1 */ - <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m1 */ - <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs0: spi2m1-cs0 { - rockchip,pins = - /* spi2_cs0_m1 */ - <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m1_cs1: spi2m1-cs1 { - rockchip,pins = - /* spi2_cs1_m1 */ - <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_pins: spi2m2-pins { - rockchip,pins = - /* spi2_clk_m2 */ - <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, - /* spi2_miso_m2 */ - <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, - /* spi2_mosi_m2 */ - <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs0: spi2m2-cs0 { - rockchip,pins = - /* spi2_cs0_m2 */ - <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi2m2_cs1: spi2m2-cs1 { - rockchip,pins = - /* spi2_cs1_m2 */ - <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi3 { - /omit-if-no-ref/ - spi3m1_pins: spi3m1-pins { - rockchip,pins = - /* spi3_clk_m1 */ - <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m1 */ - <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m1 */ - <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs0: spi3m1-cs0 { - rockchip,pins = - /* spi3_cs0_m1 */ - <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m1_cs1: spi3m1-cs1 { - rockchip,pins = - /* spi3_cs1_m1 */ - <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_pins: spi3m2-pins { - rockchip,pins = - /* spi3_clk_m2 */ - <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m2 */ - <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m2 */ - <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs0: spi3m2-cs0 { - rockchip,pins = - /* spi3_cs0_m2 */ - <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m2_cs1: spi3m2-cs1 { - rockchip,pins = - /* spi3_cs1_m2 */ - <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_pins: spi3m3-pins { - rockchip,pins = - /* spi3_clk_m3 */ - <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, - /* spi3_miso_m3 */ - <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, - /* spi3_mosi_m3 */ - <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs0: spi3m3-cs0 { - rockchip,pins = - /* spi3_cs0_m3 */ - <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi3m3_cs1: spi3m3-cs1 { - rockchip,pins = - /* spi3_cs1_m3 */ - <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - spi4 { - /omit-if-no-ref/ - spi4m0_pins: spi4m0-pins { - rockchip,pins = - /* spi4_clk_m0 */ - <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m0 */ - <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m0 */ - <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs0: spi4m0-cs0 { - rockchip,pins = - /* spi4_cs0_m0 */ - <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m0_cs1: spi4m0-cs1 { - rockchip,pins = - /* spi4_cs1_m0 */ - <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_pins: spi4m1-pins { - rockchip,pins = - /* spi4_clk_m1 */ - <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m1 */ - <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m1 */ - <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs0: spi4m1-cs0 { - rockchip,pins = - /* spi4_cs0_m1 */ - <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m1_cs1: spi4m1-cs1 { - rockchip,pins = - /* spi4_cs1_m1 */ - <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_pins: spi4m2-pins { - rockchip,pins = - /* spi4_clk_m2 */ - <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, - /* spi4_miso_m2 */ - <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, - /* spi4_mosi_m2 */ - <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; - }; - - /omit-if-no-ref/ - spi4m2_cs0: spi4m2-cs0 { - rockchip,pins = - /* spi4_cs0_m2 */ - <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; - }; - }; - - tsadc { - /omit-if-no-ref/ - tsadcm1_shut: tsadcm1-shut { - rockchip,pins = - /* tsadcm1_shut */ - <0 RK_PA2 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut: tsadc-shut { - rockchip,pins = - /* tsadc_shut */ - <0 RK_PA1 2 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - tsadc_shut_org: tsadc-shut-org { - rockchip,pins = - /* tsadc_shut_org */ - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - uart0 { - /omit-if-no-ref/ - uart0m0_xfer: uart0m0-xfer { - rockchip,pins = - /* uart0_rx_m0 */ - <0 RK_PC4 4 &pcfg_pull_up>, - /* uart0_tx_m0 */ - <0 RK_PC5 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m1_xfer: uart0m1-xfer { - rockchip,pins = - /* uart0_rx_m1 */ - <0 RK_PB0 4 &pcfg_pull_up>, - /* uart0_tx_m1 */ - <0 RK_PB1 4 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0m2_xfer: uart0m2-xfer { - rockchip,pins = - /* uart0_rx_m2 */ - <4 RK_PA4 10 &pcfg_pull_up>, - /* uart0_tx_m2 */ - <4 RK_PA3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart0_ctsn: uart0-ctsn { - rockchip,pins = - /* uart0_ctsn */ - <0 RK_PD1 4 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart0_rtsn: uart0-rtsn { - rockchip,pins = - /* uart0_rtsn */ - <0 RK_PC6 4 &pcfg_pull_none>; - }; - }; - - uart1 { - /omit-if-no-ref/ - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rx_m1 */ - <1 RK_PB7 10 &pcfg_pull_up>, - /* uart1_tx_m1 */ - <1 RK_PB6 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m1_ctsn: uart1m1-ctsn { - rockchip,pins = - /* uart1m1_ctsn */ - <1 RK_PD7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m1_rtsn: uart1m1-rtsn { - rockchip,pins = - /* uart1m1_rtsn */ - <1 RK_PD6 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_xfer: uart1m2-xfer { - rockchip,pins = - /* uart1_rx_m2 */ - <0 RK_PD2 10 &pcfg_pull_up>, - /* uart1_tx_m2 */ - <0 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart1m2_ctsn: uart1m2-ctsn { - rockchip,pins = - /* uart1m2_ctsn */ - <0 RK_PD0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart1m2_rtsn: uart1m2-rtsn { - rockchip,pins = - /* uart1m2_rtsn */ - <0 RK_PC7 10 &pcfg_pull_none>; - }; - }; - - uart2 { - /omit-if-no-ref/ - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rx_m0 */ - <0 RK_PB6 10 &pcfg_pull_up>, - /* uart2_tx_m0 */ - <0 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rx_m1 */ - <4 RK_PD1 10 &pcfg_pull_up>, - /* uart2_tx_m1 */ - <4 RK_PD0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2m2_xfer: uart2m2-xfer { - rockchip,pins = - /* uart2_rx_m2 */ - <3 RK_PB2 10 &pcfg_pull_up>, - /* uart2_tx_m2 */ - <3 RK_PB1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart2_ctsn: uart2-ctsn { - rockchip,pins = - /* uart2_ctsn */ - <3 RK_PB4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart2_rtsn: uart2-rtsn { - rockchip,pins = - /* uart2_rtsn */ - <3 RK_PB3 10 &pcfg_pull_none>; - }; - }; - - uart3 { - /omit-if-no-ref/ - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rx_m0 */ - <1 RK_PC0 10 &pcfg_pull_up>, - /* uart3_tx_m0 */ - <1 RK_PC1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - /* uart3_rx_m1 */ - <3 RK_PB6 10 &pcfg_pull_up>, - /* uart3_tx_m1 */ - <3 RK_PB5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3m2_xfer: uart3m2-xfer { - rockchip,pins = - /* uart3_rx_m2 */ - <4 RK_PA6 10 &pcfg_pull_up>, - /* uart3_tx_m2 */ - <4 RK_PA5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart3_ctsn: uart3-ctsn { - rockchip,pins = - /* uart3_ctsn */ - <1 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart3_rtsn: uart3-rtsn { - rockchip,pins = - /* uart3_rtsn */ - <1 RK_PC2 10 &pcfg_pull_none>; - }; - }; - - uart4 { - /omit-if-no-ref/ - uart4m0_xfer: uart4m0-xfer { - rockchip,pins = - /* uart4_rx_m0 */ - <1 RK_PD3 10 &pcfg_pull_up>, - /* uart4_tx_m0 */ - <1 RK_PD2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m1_xfer: uart4m1-xfer { - rockchip,pins = - /* uart4_rx_m1 */ - <3 RK_PD0 10 &pcfg_pull_up>, - /* uart4_tx_m1 */ - <3 RK_PD1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4m2_xfer: uart4m2-xfer { - rockchip,pins = - /* uart4_rx_m2 */ - <1 RK_PB2 10 &pcfg_pull_up>, - /* uart4_tx_m2 */ - <1 RK_PB3 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart4_ctsn: uart4-ctsn { - rockchip,pins = - /* uart4_ctsn */ - <1 RK_PC7 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart4_rtsn: uart4-rtsn { - rockchip,pins = - /* uart4_rtsn */ - <1 RK_PC5 10 &pcfg_pull_none>; - }; - }; - - uart5 { - /omit-if-no-ref/ - uart5m0_xfer: uart5m0-xfer { - rockchip,pins = - /* uart5_rx_m0 */ - <4 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m0 */ - <4 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m0_ctsn: uart5m0-ctsn { - rockchip,pins = - /* uart5m0_ctsn */ - <4 RK_PD2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m0_rtsn: uart5m0-rtsn { - rockchip,pins = - /* uart5m0_rtsn */ - <4 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_xfer: uart5m1-xfer { - rockchip,pins = - /* uart5_rx_m1 */ - <3 RK_PC5 10 &pcfg_pull_up>, - /* uart5_tx_m1 */ - <3 RK_PC4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart5m1_ctsn: uart5m1-ctsn { - rockchip,pins = - /* uart5m1_ctsn */ - <2 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m1_rtsn: uart5m1-rtsn { - rockchip,pins = - /* uart5m1_rtsn */ - <2 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart5m2_xfer: uart5m2-xfer { - rockchip,pins = - /* uart5_rx_m2 */ - <2 RK_PD4 10 &pcfg_pull_up>, - /* uart5_tx_m2 */ - <2 RK_PD5 10 &pcfg_pull_up>; - }; - }; - - uart6 { - /omit-if-no-ref/ - uart6m1_xfer: uart6m1-xfer { - rockchip,pins = - /* uart6_rx_m1 */ - <1 RK_PA0 10 &pcfg_pull_up>, - /* uart6_tx_m1 */ - <1 RK_PA1 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart6m1_ctsn: uart6m1-ctsn { - rockchip,pins = - /* uart6m1_ctsn */ - <1 RK_PA3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m1_rtsn: uart6m1-rtsn { - rockchip,pins = - /* uart6m1_rtsn */ - <1 RK_PA2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart6m2_xfer: uart6m2-xfer { - rockchip,pins = - /* uart6_rx_m2 */ - <1 RK_PD1 10 &pcfg_pull_up>, - /* uart6_tx_m2 */ - <1 RK_PD0 10 &pcfg_pull_up>; - }; - }; - - uart7 { - /omit-if-no-ref/ - uart7m1_xfer: uart7m1-xfer { - rockchip,pins = - /* uart7_rx_m1 */ - <3 RK_PC1 10 &pcfg_pull_up>, - /* uart7_tx_m1 */ - <3 RK_PC0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart7m1_ctsn: uart7m1-ctsn { - rockchip,pins = - /* uart7m1_ctsn */ - <3 RK_PC3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m1_rtsn: uart7m1-rtsn { - rockchip,pins = - /* uart7m1_rtsn */ - <3 RK_PC2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart7m2_xfer: uart7m2-xfer { - rockchip,pins = - /* uart7_rx_m2 */ - <1 RK_PB4 10 &pcfg_pull_up>, - /* uart7_tx_m2 */ - <1 RK_PB5 10 &pcfg_pull_up>; - }; - }; - - uart8 { - /omit-if-no-ref/ - uart8m0_xfer: uart8m0-xfer { - rockchip,pins = - /* uart8_rx_m0 */ - <4 RK_PB1 10 &pcfg_pull_up>, - /* uart8_tx_m0 */ - <4 RK_PB0 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m0_ctsn: uart8m0-ctsn { - rockchip,pins = - /* uart8m0_ctsn */ - <4 RK_PB3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m0_rtsn: uart8m0-rtsn { - rockchip,pins = - /* uart8m0_rtsn */ - <4 RK_PB2 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_xfer: uart8m1-xfer { - rockchip,pins = - /* uart8_rx_m1 */ - <3 RK_PA3 10 &pcfg_pull_up>, - /* uart8_tx_m1 */ - <3 RK_PA2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart8m1_ctsn: uart8m1-ctsn { - rockchip,pins = - /* uart8m1_ctsn */ - <3 RK_PA5 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8m1_rtsn: uart8m1-rtsn { - rockchip,pins = - /* uart8m1_rtsn */ - <3 RK_PA4 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart8_xfer: uart8-xfer { - rockchip,pins = - /* uart8_rx_ */ - <4 RK_PB1 10 &pcfg_pull_up>; - }; - }; - - uart9 { - /omit-if-no-ref/ - uart9m0_xfer: uart9m0-xfer { - rockchip,pins = - /* uart9_rx_m0 */ - <2 RK_PC4 10 &pcfg_pull_up>, - /* uart9_tx_m0 */ - <2 RK_PC2 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_xfer: uart9m1-xfer { - rockchip,pins = - /* uart9_rx_m1 */ - <4 RK_PB5 10 &pcfg_pull_up>, - /* uart9_tx_m1 */ - <4 RK_PB4 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m1_ctsn: uart9m1-ctsn { - rockchip,pins = - /* uart9m1_ctsn */ - <4 RK_PA1 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m1_rtsn: uart9m1-rtsn { - rockchip,pins = - /* uart9m1_rtsn */ - <4 RK_PA0 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_xfer: uart9m2-xfer { - rockchip,pins = - /* uart9_rx_m2 */ - <3 RK_PD4 10 &pcfg_pull_up>, - /* uart9_tx_m2 */ - <3 RK_PD5 10 &pcfg_pull_up>; - }; - - /omit-if-no-ref/ - uart9m2_ctsn: uart9m2-ctsn { - rockchip,pins = - /* uart9m2_ctsn */ - <3 RK_PD3 10 &pcfg_pull_none>; - }; - - /omit-if-no-ref/ - uart9m2_rtsn: uart9m2-rtsn { - rockchip,pins = - /* uart9m2_rtsn */ - <3 RK_PD2 10 &pcfg_pull_none>; - }; - }; - - vop { - /omit-if-no-ref/ - vop_pins: vop-pins { - rockchip,pins = - /* vop_post_empty */ - <1 RK_PA2 1 &pcfg_pull_none>; - }; - }; -}; - -/* - * This part is edited handly. - */ -&pinctrl { - bt656 { - /omit-if-no-ref/ - bt656_pins: bt656-pins { - rockchip,pins = - /* bt1120_clkout */ - <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d0 */ - <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d1 */ - <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d2 */ - <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d3 */ - <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d4 */ - <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d5 */ - <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d6 */ - <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, - /* bt1120_d7 */ - <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; - }; - }; - - gpio-func { - /omit-if-no-ref/ - tsadc_gpio_func: tsadc-gpio-func { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts deleted file mode 100644 index 2002fd0221fa30cf2b81afcab5bf600dd8328ae1..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588s-rock-5a.dts +++ /dev/null @@ -1,744 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include -#include -#include "rk3588s.dtsi" - -/ { - model = "Radxa ROCK 5 Model A"; - compatible = "radxa,rock-5a", "rockchip,rk3588s"; - - aliases { - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc; - }; - - analog-sound { - compatible = "audio-graph-card"; - label = "rk3588-es8316"; - - widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones"; - - routing = "MIC2", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR"; - - dais = <&i2s0_8ch_p0>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&io_led>; - - io-led { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; - fan-supply = <&vcc_5v0>; - pwms = <&pwm3 0 50000 0>; - #cooling-cells = <2>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_5v0: vcc-5v0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_5v0_en>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b1 { - cpu-supply = <&vdd_cpu_big0_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_b3 { - cpu-supply = <&vdd_cpu_big1_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - vdd_cpu_big0_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: regulator@43 { - compatible = "rockchip,rk8603", "rockchip,rk8602"; - reg = <0x43>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: regulator@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_npu_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - eeprom: eeprom@50 { - compatible = "belling,bl24c16a", "atmel,24c16"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m2_xfer>; -}; - -&i2c7 { - status = "okay"; - - es8316: audio-codec@11 { - compatible = "everest,es8316"; - reg = <0x11>; - clocks = <&cru I2S0_8CH_MCLKOUT>; - clock-names = "mclk"; - assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - - port { - es8316_p0_0: endpoint { - remote-endpoint = <&i2s0_8ch_p0_0>; - }; - }; - }; -}; - -&i2s0_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_mclk - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; - status = "okay"; - - i2s0_8ch_p0: port { - i2s0_8ch_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&es8316_p0_0>; - }; - }; -}; - -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x3a>; - rx_delay = <0x3e>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&pinctrl { - leds { - io_led: io-led { - rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - power { - vcc_5v0_en: vcc-5v0-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifibt { - wl_reset: wl-reset { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - wl_dis: wl-dis { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; - }; - - wl_wake_host: wl-wake-host { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - bt_dis: bt-dis { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; - }; - - bt_wake_host: bt-wake-host { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&saradc { - vref-supply = <&avcc_1v8_s0>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - max-frequency = <150000000>; - no-sdio; - no-mmc; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - - pmic@0 { - compatible = "rockchip,rk806"; - reg = <0x0>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, - <&rk806_dvs2_null>, <&rk806_dvs3_null>; - spi-max-frequency = <1000000>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_null: dvs2-null-pins { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs3_null: dvs3-null-pins { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_xhci { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index d3c257983ecbac9c49983abf1edfdbce676e8995..e9d38d5c83b0a718c276879cc12020033398fc4b 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -27,7 +27,7 @@ <&cru ACLK_USB3OTG0>; clock-names = "ref_clk", "suspend_clk", "bus_clk"; dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; power-domains = <&power RK3588_PD_USB>; @@ -58,22 +58,21 @@ }; usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", - "simple-mfd"; + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d0000 0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; - u2phy0: usb2-phy@0 { + u2phy0: usb2phy@0 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x0 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy0_otg: otg-port { @@ -91,10 +90,7 @@ usbdp_phy0: phy@fed80000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed80000 0x0 0x10000>; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; + #phy-cells = <1>; clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, <&cru CLK_USBDP_PHY0_IMMORTAL>, <&cru PCLK_USBDPPHY0>, @@ -106,17 +102,11 @@ <&cru SRST_USBDP_COMBO_PHY0_PCS>, <&cru SRST_P_USBDPPHY0>; reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; status = "disabled"; - - usbdp_phy0_dp: dp-port { - #phy-cells = <0>; - status = "disabled"; - }; - - usbdp_phy0_u3: usb3-port { - #phy-cells = <0>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi deleted file mode 100644 index 36b1b7acfe6a15042600a595875054744d48f257..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rk3588s.dtsi +++ /dev/null @@ -1,2485 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "rockchip,rk3588"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu_b2>; - }; - core1 { - cpu = <&cpu_b3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_b0: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b0>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b1: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b1>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b2: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b2>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b3: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b3>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l2: l2-cache-l2 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l3: l2-cache-l3 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b0: l2-cache-b0 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b1: l2-cache-b1 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b2: l2-cache-b2 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b3: l2-cache-b3 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - spll: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <702000000>; - clock-output-names = "spll"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; - - xin24m: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = ; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; - }; - - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - - vop_grf: syscon@fd5a4000 { - compatible = "rockchip,rk3588-vop-grf", "syscon"; - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; - }; - - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - - pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - - pipe_phy2_grf: syscon@fd5c4000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2-phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; - #clock-cells = <0>; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2-phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; - #clock-cells = <0>; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; - }; - - system_sram1: sram@fd600000 { - compatible = "mmio-sram"; - reg = <0x0 0xfd600000 0x0 0x100000>; - ranges = <0x0 0x0 0xfd600000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - cru: clock-controller@fd7c0000 { - compatible = "rockchip,rk3588-cru"; - reg = <0x0 0xfd7c0000 0x0 0x5c000>; - assigned-clocks = - <&cru PLL_PPLL>, <&cru PLL_AUPLL>, - <&cru PLL_NPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CENTER_ROOT>, - <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, - <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, - <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, - <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, - <&cru CLK_GPU>; - assigned-clock-rates = - <1100000000>, <786432000>, - <850000000>, <1188000000>, - <702000000>, - <400000000>, <500000000>, - <800000000>, <100000000>, - <400000000>, <100000000>, - <200000000>, <500000000>, - <375000000>, <150000000>, - <200000000>; - rockchip,grf = <&php_grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@fd880000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfd880000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart0m1_xfer>; - pinctrl-names = "default"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pwm0: pwm@fd8b0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0000 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fd8b0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0010 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fd8b0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0020 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fd8b0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0030 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fd8d8000 { - compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfd8d8000 0x0 0x400>; - - power: power-controller { - compatible = "rockchip,rk3588-power-controller"; - #address-cells = <1>; - #power-domain-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPUTOP { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>, - <&cru HCLK_NPU_CM0_ROOT>; - pm_qos = <&qos_npu0_mwr>, - <&qos_npu0_mro>, - <&qos_mcu_npu>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPU1 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_NPU2 { - reg = ; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu2>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { - reg = ; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - pm_qos = <&qos_gpu_m0>, - <&qos_gpu_m1>, - <&qos_gpu_m2>, - <&qos_gpu_m3>; - #power-domain-cells = <0>; - }; - /* These power domains are grouped by VD_VCODEC */ - power-domain@RK3588_PD_VCODEC { - reg = ; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>, - <&cru ACLK_RKVDEC_CCU>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC1>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VENC0 { - reg = ; - clocks = <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>; - pm_qos = <&qos_rkvenc0_m0ro>, - <&qos_rkvenc0_m1ro>, - <&qos_rkvenc0_m2wo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VENC1 { - reg = ; - clocks = <&cru HCLK_RKVENC1>, - <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>, - <&cru ACLK_RKVENC1>; - pm_qos = <&qos_rkvenc1_m0ro>, - <&qos_rkvenc1_m1ro>, - <&qos_rkvenc1_m2wo>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3588_PD_VDPU { - reg = ; - clocks = <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_LOW_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_JPEG_DECODER_ROOT>, - <&cru ACLK_IEP2P0>, - <&cru HCLK_IEP2P0>, - <&cru ACLK_JPEG_ENCODER0>, - <&cru HCLK_JPEG_ENCODER0>, - <&cru ACLK_JPEG_ENCODER1>, - <&cru HCLK_JPEG_ENCODER1>, - <&cru ACLK_JPEG_ENCODER2>, - <&cru HCLK_JPEG_ENCODER2>, - <&cru ACLK_JPEG_ENCODER3>, - <&cru HCLK_JPEG_ENCODER3>, - <&cru ACLK_JPEG_DECODER>, - <&cru HCLK_JPEG_DECODER>, - <&cru ACLK_RGA2>, - <&cru HCLK_RGA2>; - pm_qos = <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc0>, - <&qos_jpeg_enc1>, - <&qos_jpeg_enc2>, - <&qos_jpeg_enc3>, - <&qos_rga2_mro>, - <&qos_rga2_mwo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - - power-domain@RK3588_PD_AV1 { - reg = ; - clocks = <&cru PCLK_AV1>, - <&cru ACLK_AV1>, - <&cru HCLK_VDPU_ROOT>; - pm_qos = <&qos_av1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC0 { - reg = ; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = ; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RGA30 { - reg = ; - clocks = <&cru ACLK_RGA3_0>, - <&cru HCLK_RGA3_0>; - pm_qos = <&qos_rga3_0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VOP { - reg = ; - clocks = <&cru PCLK_VOP_ROOT>, - <&cru HCLK_VOP_ROOT>, - <&cru ACLK_VOP>; - pm_qos = <&qos_vop_m0>, - <&qos_vop_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VO0 { - reg = ; - clocks = <&cru PCLK_VO0_ROOT>, - <&cru PCLK_VO0_S_ROOT>, - <&cru HCLK_VO0_S_ROOT>, - <&cru ACLK_VO0_ROOT>, - <&cru HCLK_HDCP0>, - <&cru ACLK_HDCP0>, - <&cru HCLK_VOP_ROOT>; - pm_qos = <&qos_hdcp0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VO1 { - reg = ; - clocks = <&cru PCLK_VO1_ROOT>, - <&cru PCLK_VO1_S_ROOT>, - <&cru HCLK_VO1_S_ROOT>, - <&cru HCLK_HDCP1>, - <&cru ACLK_HDCP1>, - <&cru ACLK_HDMIRX_ROOT>, - <&cru HCLK_VO1USB_TOP_ROOT>; - pm_qos = <&qos_hdcp1>, - <&qos_hdmirx>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VI { - reg = ; - clocks = <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>, - <&cru HCLK_ISP0>, - <&cru ACLK_ISP0>, - <&cru HCLK_VICAP>, - <&cru ACLK_VICAP>; - pm_qos = <&qos_isp0_mro>, - <&qos_isp0_mwo>, - <&qos_vicap_m0>, - <&qos_vicap_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_ISP1 { - reg = ; - clocks = <&cru HCLK_ISP1>, - <&cru ACLK_ISP1>, - <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_isp1_mwo>, - <&qos_isp1_mro>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_FEC { - reg = ; - clocks = <&cru HCLK_FISHEYE0>, - <&cru ACLK_FISHEYE0>, - <&cru HCLK_FISHEYE1>, - <&cru ACLK_FISHEYE1>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_fisheye0>, - <&qos_fisheye1>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_RGA31 { - reg = ; - clocks = <&cru HCLK_RGA3_1>, - <&cru ACLK_RGA3_1>; - pm_qos = <&qos_rga3_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_USB { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_USB_ROOT>, - <&cru ACLK_USB>, - <&cru HCLK_USB_ROOT>, - <&cru HCLK_HOST0>, - <&cru HCLK_HOST_ARB0>, - <&cru HCLK_HOST1>, - <&cru HCLK_HOST_ARB1>; - pm_qos = <&qos_usb3_0>, - <&qos_usb3_1>, - <&qos_usb2host_0>, - <&qos_usb2host_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_GMAC { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_PCIE { - reg = ; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDIO { - reg = ; - clocks = <&cru HCLK_SDIO>, - <&cru HCLK_NVM_ROOT>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_AUDIO { - reg = ; - clocks = <&cru HCLK_AUDIO_ROOT>, - <&cru PCLK_AUDIO_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDMMC { - reg = ; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - }; - }; - - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 0>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S4_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s5_8ch: i2s@fddf0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 2>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S5_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s9_8ch: i2s@fddfc000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddfc000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 23>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S9_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; - }; - - qos_gpu_m1: qos@fdf35200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35200 0x0 0x20>; - }; - - qos_gpu_m2: qos@fdf35400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35400 0x0 0x20>; - }; - - qos_gpu_m3: qos@fdf35600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35600 0x0 0x20>; - }; - - qos_rga3_1: qos@fdf36000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf36000 0x0 0x20>; - }; - - qos_sdio: qos@fdf39000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf39000 0x0 0x20>; - }; - - qos_sdmmc: qos@fdf3d800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3d800 0x0 0x20>; - }; - - qos_usb3_1: qos@fdf3e000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e000 0x0 0x20>; - }; - - qos_usb3_0: qos@fdf3e200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e200 0x0 0x20>; - }; - - qos_usb2host_0: qos@fdf3e400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e400 0x0 0x20>; - }; - - qos_usb2host_1: qos@fdf3e600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e600 0x0 0x20>; - }; - - qos_fisheye0: qos@fdf40000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40000 0x0 0x20>; - }; - - qos_fisheye1: qos@fdf40200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40200 0x0 0x20>; - }; - - qos_isp0_mro: qos@fdf40400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40400 0x0 0x20>; - }; - - qos_isp0_mwo: qos@fdf40500 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40500 0x0 0x20>; - }; - - qos_vicap_m0: qos@fdf40600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40600 0x0 0x20>; - }; - - qos_vicap_m1: qos@fdf40800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40800 0x0 0x20>; - }; - - qos_isp1_mwo: qos@fdf41000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41000 0x0 0x20>; - }; - - qos_isp1_mro: qos@fdf41100 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41100 0x0 0x20>; - }; - - qos_rkvenc0_m0ro: qos@fdf60000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60000 0x0 0x20>; - }; - - qos_rkvenc0_m1ro: qos@fdf60200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60200 0x0 0x20>; - }; - - qos_rkvenc0_m2wo: qos@fdf60400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60400 0x0 0x20>; - }; - - qos_rkvenc1_m0ro: qos@fdf61000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61000 0x0 0x20>; - }; - - qos_rkvenc1_m1ro: qos@fdf61200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61200 0x0 0x20>; - }; - - qos_rkvenc1_m2wo: qos@fdf61400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61400 0x0 0x20>; - }; - - qos_rkvdec0: qos@fdf62000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf62000 0x0 0x20>; - }; - - qos_rkvdec1: qos@fdf63000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf63000 0x0 0x20>; - }; - - qos_av1: qos@fdf64000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf64000 0x0 0x20>; - }; - - qos_iep: qos@fdf66000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66000 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fdf66200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66200 0x0 0x20>; - }; - - qos_jpeg_enc0: qos@fdf66400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66400 0x0 0x20>; - }; - - qos_jpeg_enc1: qos@fdf66600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66600 0x0 0x20>; - }; - - qos_jpeg_enc2: qos@fdf66800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66800 0x0 0x20>; - }; - - qos_jpeg_enc3: qos@fdf66a00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66a00 0x0 0x20>; - }; - - qos_rga2_mro: qos@fdf66c00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66c00 0x0 0x20>; - }; - - qos_rga2_mwo: qos@fdf66e00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66e00 0x0 0x20>; - }; - - qos_rga3_0: qos@fdf67000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67000 0x0 0x20>; - }; - - qos_vdpu: qos@fdf67200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67200 0x0 0x20>; - }; - - qos_npu1: qos@fdf70000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf70000 0x0 0x20>; - }; - - qos_npu2: qos@fdf71000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf71000 0x0 0x20>; - }; - - qos_npu0_mwr: qos@fdf72000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72000 0x0 0x20>; - }; - - qos_npu0_mro: qos@fdf72200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72200 0x0 0x20>; - }; - - qos_mcu_npu: qos@fdf72400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72400 0x0 0x20>; - }; - - qos_hdcp0: qos@fdf80000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf80000 0x0 0x20>; - }; - - qos_hdcp1: qos@fdf81000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81000 0x0 0x20>; - }; - - qos_hdmirx: qos@fdf81200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81200 0x0 0x20>; - }; - - qos_vop_m0: qos@fdf82000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82000 0x0 0x20>; - }; - - qos_vop_m1: qos@fdf82200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; - clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, - <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, - <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, - <0 0 0 2 &pcie2x1l1_intc 1>, - <0 0 0 3 &pcie2x1l1_intc 2>, - <0 0 0 4 &pcie2x1l1_intc 3>; - linux,pci-domain = <3>; - max-link-speed = <2>; - msi-map = <0x3000 &its0 0x3000 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, - <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, - <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &its0 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = , - , - , - ; - rockchip,pmu = <&pmu1grf>; - }; - - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, - <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata0: sata@fe210000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe210000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, - <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy0_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sata2: sata@fe230000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe230000 0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, - <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = ; - phys = <&combphy2_psu PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power RK3588_PD_SDMMC>; - status = "disabled"; - }; - - sdio: mmc@fe2d0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x00 0xfe2d0000 0x00 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - power-domains = <&power RK3588_PD_SDIO>; - status = "disabled"; - }; - - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; - pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, - <&emmc_cmd>, <&emmc_data_strobe>; - pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdi2 - &i2s0_sdi3 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe480000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe480000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_lrck - &i2s1m0_sclk - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe490000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe490000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 0>, <&dmac1 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe4a0000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe4a0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi - &i2s3_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe600000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = ; - interrupt-controller; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; - ranges; - #address-cells = <2>; - #interrupt-cells = <4>; - #size-cells = <2>; - - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_partition1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; - }; - }; - }; - - dmac0: dma-controller@fea10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fea30000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea30000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fea90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfea90000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c1m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@feaa0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeaa0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@feab0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeab0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@feac0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeac0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fead0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfead0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@feae0000 { - compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfeae0000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = ; - }; - - spi0: spi@feb00000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb00000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@feb10000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb10000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@feb20000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@feb30000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb30000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 17>, <&dmac1 18>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@feb40000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb40000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@feb50000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb50000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@feb60000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb60000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@feb70000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb70000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 9>, <&dmac1 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@feb80000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb80000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 11>, <&dmac1 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@feb90000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb90000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 13>, <&dmac1 14>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@feba0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeba0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 7>, <&dmac2 8>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@febb0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebb0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 9>, <&dmac2 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@febc0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebc0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 11>, <&dmac2 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@febd0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@febd0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@febd0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@febd0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@febe0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@febe0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@febe0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@febe0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@febf0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@febf0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@febf0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@febf0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; - interrupts = ; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC>; - assigned-clock-rates = <2000000>; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; - reset-names = "tsadc-apb", "tsadc"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shut>; - pinctrl-names = "gpio", "otpout"; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: adc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c6: i2c@fec80000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec80000 0x0 0x1000>; - clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c6m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@fec90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec90000 0x0 0x1000>; - clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c7m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@feca0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeca0000 0x0 0x1000>; - clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-0 = <&i2c8m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@fecb0000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfecb0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac2 13>, <&dmac2 14>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - otp: efuse@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, - <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; - clock-names = "otp", "apb_pclk", "phy", "arb"; - resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, - <&cru SRST_OTPC_ARB>; - reset-names = "otp", "apb", "arb"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - - otp_id: id@7 { - reg = <0x07 0x10>; - }; - - cpub0_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - - cpub1_leakage: cpu-leakage@18 { - reg = <0x18 0x1>; - }; - - cpul_leakage: cpu-leakage@19 { - reg = <0x19 0x1>; - }; - - log_leakage: log-leakage@1a { - reg = <0x1a 0x1>; - }; - - gpu_leakage: gpu-leakage@1b { - reg = <0x1b 0x1>; - }; - - otp_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - - npu_leakage: npu-leakage@28 { - reg = <0x28 0x1>; - }; - - codec_leakage: codec-leakage@29 { - reg = <0x29 0x1>; - }; - }; - - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; - interrupts = , - ; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; - - combphy2_psu: phy@fee20000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee20000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy2_grf>; - status = "disabled"; - }; - - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3588-pinctrl"; - ranges; - rockchip,grf = <&ioc>; - #address-cells = <2>; - #size-cells = <2>; - - gpio0: gpio@fd8a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfd8a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fec20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec20000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fec30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec30000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fec40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec40000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fec50000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec50000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; -}; - -#include "rk3588s-pinctrl.dtsi" diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac470688dcc8f7a1eed38a87ac881e156c..da1d548b7330cd8d4cf97f36b7c305f6c527ecff 100644 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -78,6 +86,19 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts deleted file mode 100644 index 83e8b3183847cdb9b7cb608b4aaca0be95466c8d..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rv1108-elgin-r1.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Elgin RV1108 R1 board"; - compatible = "elgin,rv1108-elgin", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_otg: otg-port { - status = "okay"; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer_pullup>; - status = "okay"; -}; - -&usb20_otg { - status = "okay"; -}; - -&pinctrl { - uart2m0 { - uart2m0_xfer_pullup: uart2m0-xfer-pullup { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - }; -}; diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts deleted file mode 100644 index c91776bc106eb355f81f060de203f81bcde7eecf..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rv1108-evb.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RV1108 Evaluation board"; - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&gmac { - status = "okay"; - clock_in_out = <0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; -}; - -&saradc { - status = "okay"; -}; - -&sfc { - status = "okay"; - flash@0 { - compatible = "gd25q256","jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <96000000>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb20_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi deleted file mode 100644 index 215d88522587accd3c8ab3a80f6edf9e7ad22ac8..0000000000000000000000000000000000000000 --- a/arch/arm/dts/rv1108.dtsi +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rv1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; - reg = <0x10300000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rv1108-usb2phy"; - reg = <0x100 0x0c>; - clocks = <&cru SCLK_USBPHY>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usbphy"; - rockchip,usbgrf = <&usbgrf>; - status = "disabled"; - - u2phy_otg: otg-port { - interrupts = ; - interrupt-names = "otg-mux"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - saradc: saradc@1038c000 { - compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; - reg = <0x1038c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clock-frequency = <1000000>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - status = "disabled"; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rv1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - usbgrf: syscon@202a0000 { - compatible = "rockchip,rv1108-usbgrf", "syscon"; - reg = <0x202a0000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - usb_host_ehci: usb@30140000 { - compatible = "generic-ehci"; - reg = <0x30140000 0x20000>; - interrupts = ; - status = "disabled"; - }; - - usb_host_ohci: usb@30160000 { - compatible = "generic-ohci"; - reg = <0x30160000 0x20000>; - interrupts = ; - status = "disabled"; - }; - - usb20_otg: usb@30180000 { - compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - sfc: sfc@301c0000 { - compatible = "rockchip,sfc"; - reg = <0x301c0000 0x200>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rv1108-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - max-speed = <100>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, - <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, - <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sfc { - sfc_pins: sfc-pins { - rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, - <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart01rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h b/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h deleted file mode 100644 index 683e3d412ce0f3c9fb457e86c9d2e9723cc4d56a..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-adi/sc5xx/sc5xx.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ -#ifndef ARCH_ADI_SC5XX_SC5XX_H -#define ARCH_ADI_SC5XX_SC5XX_H - -#include - -#define TWI0_CLKDIV 0x31001400 // TWI0 SCL Clock Divider Register -#define TWI1_CLKDIV 0x31001500 // TWI1 SCL Clock Divider Register -#define TWI2_CLKDIV 0x31001600 // TWI2 SCL Clock Divider Register - -const char *sc5xx_get_boot_mode(u32 *bmode); -void sc5xx_enable_rgmii(void); - -void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base); -void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end); -void sc5xx_enable_pmu(void); - -/** - * Per-SoC init function to be used to initialize hw-specific things. Examples: - * enable PMU on armv7, enable coresight timer on armv8, etc. - */ -void sc5xx_soc_init(void); - -/* - * Reconfigure SPI memory map region for OSPI use. The adi-spi3 driver - * does not use the memory map, while the OSPI driver requires it. Only - * available on sc59x and sc59x-64 - */ -void sc59x_remap_ospi(void); - -#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/soc.h b/arch/arm/include/asm/arch-adi/sc5xx/soc.h deleted file mode 100644 index 430dbe2dae48422b1673f89cc72984b1e81af94f..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-adi/sc5xx/soc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef BOARD_ADI_COMMON_SOC_H -#define BOARD_ADI_COMMON_SOC_H - -#include - -void fixup_dp83867_phy(struct phy_device *phydev); - -#endif diff --git a/arch/arm/include/asm/arch-adi/sc5xx/spl.h b/arch/arm/include/asm/arch-adi/sc5xx/spl.h deleted file mode 100644 index c215e6b892a39a626783a49d1e3e099e2da984c3..0000000000000000000000000000000000000000 --- a/arch/arm/include/asm/arch-adi/sc5xx/spl.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ -#ifndef ARCH_ADI_SC5XX_SPL_H -#define ARCH_ADI_SC5XX_SPL_H - -#include - -struct adi_boot_args { - phys_addr_t addr; - u32 flags; - u32 cmd; -}; - -extern u32 bmode; - -/** - * This table stores the arguments to the rom boot function per bootmode, - * and it is populated per SoC in the corresponding SoC support file (sc7x, sc58x, - * and so on). - */ -extern const struct adi_boot_args adi_rom_boot_args[8]; - -/** - * Struct layout for the boot config is also specific to an SoC, so you should - * only access it inside an SoC-specific boot hook function, which will be called - * from the boot rom while going from SPL to proper u-boot - */ -struct ADI_ROM_BOOT_CONFIG; -int32_t adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *cfg, int32_t cause); - -typedef void (*adi_rom_boot_fn)(void *address, uint32_t flags, int32_t count, - void *hook, uint32_t command); - -extern adi_rom_boot_fn adi_rom_boot; - -#endif diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h index 393bc7a6a8a5d738d3aa12bbb0dabf59ed0c97b5..8e3d55f3e7632f7f6c4d155715be871d1aefbe33 100644 --- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -10,8 +10,6 @@ #ifndef __CLK_SYNTHESIZER_H #define __CLK_SYNTHESIZER_H -#include - #define CLK_SYNTHESIZER_ID_REG 0x0 #define CLK_SYNTHESIZER_XCSEL 0x05 #define CLK_SYNTHESIZER_MUX_REG 0x14 diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index a415693de6ea34d24c039aadb6a721b41cb9b50b..50d6a6bc7605d8d4c17ffc9acccfe1ccb4d3b8ff 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -140,7 +140,6 @@ #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) #ifndef __ASSEMBLY__ -#include struct ast2500_clk_priv { struct ast2500_scu *scu; diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h index a2c8852db842d6877f3bda6e5257c347a97063f4..251bfa269bf43f9d0c7509531514be08906e7842 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -125,8 +125,6 @@ #define SCU_MISC_CTRL1_UART5_DIV BIT(12) #ifndef __ASSEMBLY__ -#include - struct ast2600_scu { uint32_t prot_key1; /* 0x000 */ uint32_t chip_id1; /* 0x004 */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index a02bec9371c09ccda3e8819d9948214a25232fbe..9e29350ca4ba894b54834e012366b8d8ee53b1f2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -7,8 +7,6 @@ #ifndef __FSL_SERDES_H__ #define __FSL_SERDES_H__ -#include - #ifdef CONFIG_FSL_LSCH3 enum srds_prtcl { /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 147ca2f99de69f93f39193b7053ccc85a8916e34..9794db044996578a6ff2a792eb459b6aba35b4fb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -6,7 +6,6 @@ #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ #define __ARCH_FSL_LSCH2_IMMAP_H__ -#include #include #ifndef __ASSEMBLY__ #include diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 1f81d91977c805fc1b017b791c99dd129ae90ab6..c14855d177ecbed336b6b5a2f58d2e292c37b416 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -8,7 +8,7 @@ #include #include -#include +#include #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR_0 0x3f400000 diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 35e3ec7a9878de55770c618a46c8912f48504ff1..9244e0a78fd341c7b3e9ee5c5265e249a390d959 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -6,8 +6,6 @@ #ifndef __FSL_SERDES_H #define __FSL_SERDES_H -#include - enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 58013a85951ac449fe9897b95ee44bd55b4f148c..d585b5cf4b2232fc174cd78e9dfae3f9e6427dd0 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -7,8 +7,6 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H -#include - #ifdef CONFIG_SYS_MX5_HCLK #define MXC_HCLK CONFIG_SYS_MX5_HCLK #else diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h index 5da0037b2c6b3acbaeed461baffbdb9fa48032a2..634736cc09cdd5b5b61e964bc2e7b1d2c86f06fd 100644 --- a/arch/arm/include/asm/arch-mx7/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h @@ -7,8 +7,6 @@ #include -struct wdog_regs; - void set_wdog_reset(struct wdog_regs *wdog); #endif /* __SYS_PROTO_IMX7_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index e736772fda755a5b8f96d6605a0bb989fb95e697..ecf3b4e7428c465ab67b280868c8f6ad4648a0af 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -7,8 +7,6 @@ #ifndef _ASM_ARCH_BOOTROM_H #define _ASM_ARCH_BOOTROM_H -#include - /* * Saved Stack pointer address. * Access might be needed in some special cases. diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 73e5283108b146ca2d80d39bddc02aaaee921df4..f01c5aeb71cb5de24a0ba6ca455565cdc7b199c7 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -6,8 +6,6 @@ #ifndef _ASM_ARCH_CLOCK_H #define _ASM_ARCH_CLOCK_H -#include - struct udevice; /* define pll mode */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h index f4bbc2401310a52a8dddac624505d6a0affc43eb..a995bb950d975711f2a6776d75242fb5ac9620cb 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3308.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h @@ -5,8 +5,6 @@ #ifndef _ASM_ARCH_GRF_rk3308_H #define _ASM_ARCH_GRF_rk3308_H -#include - struct rk3308_grf { unsigned int gpio0a_iomux; unsigned int reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h index e26459fdd3bfdab64f23d309748d694e6285ab21..5ab9b2809f29ee151fa9fc410ae07cb5cec99039 100644 --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h +++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h @@ -8,8 +8,6 @@ #ifndef _SUNXI_PMIC_BUS_H #define _SUNXI_PMIC_BUS_H -#include - int pmic_bus_init(void); int pmic_bus_read(u8 reg, u8 *data); int pmic_bus_write(u8 reg, u8 data); diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h index 4fbb4b91c86b8c6b9879e173455a2d5a34265710..46cd87e79e8da080339ef109dee1a7cf65e5f2af 100644 --- a/arch/arm/include/asm/arch-sunxi/tve.h +++ b/arch/arm/include/asm/arch-sunxi/tve.h @@ -9,8 +9,6 @@ #ifndef _TVE_H #define _TVE_H -#include - enum tve_mode { tve_mode_vga, tve_mode_composite_pal, diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index b922b2d30ea0f98bde84cf015bcdec33623585c8..78aeb25ac78e37c7ce1658c2a2985f1000745773 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -4,7 +4,6 @@ * NVIDIA Corporation */ #include -#include /* Stabilization delays, in usec */ #define PLL_STABILIZATION_DELAY (300) diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h index d0ba83ae8bc8e3d9e479656c109147f9e4a72330..4e1da98d1f2105bc61ce8849b482e14efe1c31b6 100644 --- a/arch/arm/include/asm/arch-tegra/cboot.h +++ b/arch/arm/include/asm/arch-tegra/cboot.h @@ -6,8 +6,6 @@ #ifndef _TEGRA_CBOOT_H_ #define _TEGRA_CBOOT_H_ -#include -#include #include #ifdef CONFIG_ARM64 diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index 3c1838cf1372dace41b2c0fd0174fa1a3e240453..fe7b3a50e0d9d8b2f68d296c882f6bd0d514aeeb 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,7 +6,6 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ -#include #include #define TEGRA_GPIOS_PER_PORT 8 diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index dc8db39122192fddb3450a8c1c6e57c2638fd309..afec6bbdda339174d7e69d9df3069a31447f4ad5 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -10,7 +10,6 @@ #include #include -#include struct udevice; diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h index 99488730998ee2c59e6d9c2f75177fec272ed93e..f19e4e726a19ab07bcc637b39c27b5294f017549 100644 --- a/arch/arm/include/asm/esr.h +++ b/arch/arm/include/asm/esr.h @@ -7,7 +7,6 @@ #ifndef __ASM_ESR_H #define __ASM_ESR_H -#include #include #include diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 45401d5e3c8a42714cd246f22b1d6154a4230031..452bcd1b8fd91d42f62f69e4a624d3c458320064 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -12,7 +12,6 @@ #include #include -#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h index 25763526f5f6c6d0155b3778df9b9fdba3559321..1b7c9cd524993cb293760d7fe097ca39b55aadcd 100644 --- a/arch/arm/include/asm/mach-imx/gpio.h +++ b/arch/arm/include/asm/mach-imx/gpio.h @@ -9,8 +9,6 @@ #define __ASM_ARCH_IMX_GPIO_H #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include - /* GPIO registers */ struct gpio_regs { u32 gpio_dr; /* data */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index 84fe01e3b712360f30cc3a25dae2044461d14d6b..38a1a6ea0d7b38b09ce9489957d2344b0c4dc017 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -9,7 +9,6 @@ #ifndef _DAVINCI_NAND_H_ #define _DAVINCI_NAND_H_ -#include #include #define NAND_READ_START 0x00 diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 9afd837599961aca706371da9adfffb4a872a799..181a8ac4c27f4add7972409f687c85d43f5a3d48 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -16,6 +16,7 @@ * Abdellatif El Khlifi */ +#include #include #include diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 7c49462c8eb4ff1cd110f4dd5fe73a8a150c31ed..b88b01eefdcd351b343377624764bb68b19a5e7a 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf5e71ac95214f374955c370497590a..29020bd1c6bc84c76dd3cc6bca38a78ef77df3dc 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -14,6 +14,7 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ +#include #include #ifdef CONFIG_ARMV7_NONSEC #include diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 192c120a7d2ebe8a2c57f92b424c1699fd8e0e35..f30a483ed8b47b62a4e987a9f05f31005bf08aaa 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -11,6 +11,7 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ +#include #include #include #include diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f29963d0663b02b77c348a17098df6fd77..0893915b3004927ad2230dc799c8f1041421d53e 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 0afd3880447f62a54ca577deee9f2324e4a59d0e..d05314ee57fc1fc03d5e6fd79ae1200b26206c97 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -9,6 +9,7 @@ #include #include #include +#include struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b2ae74a59f102a6c1d83a3b1ded795404fb6aa9a..7a160158671195df67d708274945d02063c0806b 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -6,7 +6,7 @@ /* for now: just dummy functions to satisfy the linker */ -#include +#include #include #include #include diff --git a/arch/arm/lib/cmd_boot.c b/arch/arm/lib/cmd_boot.c index 5df5bc305a2fa4742b2230db8baed82f7c9ec7dd..c905ecc4bd943f0cc164009eba09ab9c4332d444 100644 --- a/arch/arm/lib/cmd_boot.c +++ b/arch/arm/lib/cmd_boot.c @@ -17,6 +17,7 @@ * Copyright 2015 Konsulko Group, Matt Porter */ +#include #include /* diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 0a96ba1355f84300a823a3c9d143153654ee272e..f7029918d4fb86e81205474dd8bae3f0d6efce2c 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -5,9 +5,7 @@ * (C) Copyright 2009 Wolfgang Denk */ -#include -#include -#include +#include int raise (int signum) { diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index 2cc0a32f9d47f1f3def290a08f70183206057e47..f4bbd21da915e8c0f57ac84b08bef74bc5bddfd7 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -2,6 +2,7 @@ /* * Copyright 2019 Broadcom. */ +#include #include #include #include diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c86769417692d890a7dd8e4699555f2..e394c1ad90934f60493bfa604f1d1584cbe0e910 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 333a5026a469bec3cbddbbe0bbdebee72ef0e124..9961472f69f76098faf61fc4b04faf6c6f22d7dc 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -18,6 +18,7 @@ * Philippe Robin, ARM Ltd. */ +#include #include #include #include diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index b3024ba514ec363bfc3b957df203fc784278037e..125dc0bb390bb1fa4404d0f892572b4424c700b9 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -4,6 +4,7 @@ * David Feng */ +#include #include #include #include diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index b977961bde8a2792054a9c679abe49a9b04c8f4f..277854aa878c2fbf6ffe3f05c6a60e8228fd7c49 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -4,10 +4,9 @@ * Kamil Lulko, */ -#include +#include #include #include -#include /* * Upon exception entry ARMv7-M processors automatically save stack diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index be800a3bc9ebbfad81d6ecb6e9c7ff647edd7282..903b3357048aa0d0dcdefbab91a9e3fa038edd8a 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -3,6 +3,7 @@ * Copyright 2016 NXP Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index c9796a4435c6fb9fab89307d20be6711487b5a65..3e051e36f12dd0739934d4b7c2ece9fdb7ecb06f 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -20,6 +20,7 @@ * (C) Copyright 2004 Texas Insturments */ +#include #include #include #include diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c index 4357acaef6c4315b46c7a1bbe8fea0609ae61994..b286bac9bf0082fc737bc9ca158b449e7ad9009c 100644 --- a/arch/arm/lib/save_prev_bl_data.c +++ b/arch/arm/lib/save_prev_bl_data.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index c43a63f1819e700e2773e648d8fcc7683ca016ae..b13897495daebaa60c5005036b6f7c7f6101738b 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -7,6 +7,7 @@ * Tom Rini */ +#include #include #include #include diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index ea1b937add76fb591d499d7d6848c8b70d6723db..656084c7e519486bc606db7f29781aab2554580d 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -10,6 +10,7 @@ * Sysgo Real-Time Solutions, GmbH * Marius Groeger */ +#include #include #include #include diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 51287251b3f6a078822f3d76c58c36f53434c771..45e9c4506a97b9def389c595ed9f8fa0f405bc79 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -6,6 +6,7 @@ * bootz code: * Copyright (C) 2012 Marek Vasut */ +#include #include #define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 8bace3005eb567ad40f6e8d8a2a0d4c1d885933c..7a6151a97223cdd5be6401edc97d4f867a356748 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Mark Kettenis */ +#include #include #include #include diff --git a/arch/arm/mach-apple/rtkit.c b/arch/arm/mach-apple/rtkit.c index b8f4771e5e71928db9152a3dec301730ae8195d8..a550b553b663bcde0ac70fbd56a51d11b4823cb4 100644 --- a/arch/arm/mach-apple/rtkit.c +++ b/arch/arm/mach-apple/rtkit.c @@ -4,14 +4,13 @@ * (C) Copyright 2021 Copyright The Asahi Linux Contributors */ +#include #include #include #include #include #include -#include -#include #define APPLE_RTKIT_EP_MGMT 0 #define APPLE_RTKIT_EP_CRASHLOG 1 diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index 531c2ad1562c98839217e935cb618f4228d979a9..bae10271844add321ed488950d51ecba93449fae 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c index 50d7f99b2643927487e4a3a5e59e8045296cb0cf..02bd3f67c96aeee166f641101ce2d15f51f57537 100644 --- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 4c0b705ea88dc0ebcca17f28db564188ec28737a..dc6cdc35d15ca2b538914d74881cc8d4618e0ed1 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -2,7 +2,7 @@ /* * Copyright (c) Aspeed Technology Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 05390c16f3aff42c388c7de453b5899beac61546..0952e73a45729e18f0aea24edf24cb7cba57cf42 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -2,6 +2,7 @@ /* * Copyright (c) Aspeed Technology Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c index c420940d1cb917633a6f89c67664eceb36d0836e..5bc442ef33ce2a21af3881aa7361c30f738b9e4f 100644 --- a/arch/arm/mach-aspeed/ast_wdt.c +++ b/arch/arm/mach-aspeed/ast_wdt.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index 459edadb5876c299458b354d75c2380ba22e5215..c849885bc2bb2a8706fef1c32d3cf4362da1bd0a 100644 --- a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -10,6 +10,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index ac55a61be64766c63a4b01080bf6b8c3e4995276..09ac66d619d24a0fff2b98685deda2a97db32f91 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -7,7 +7,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 579e76b339d8495d3cbcb2890283085f4a750c60..9bf03fd68ecc6e8704d3f8899f1de33cd0ded45c 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -10,7 +10,7 @@ * Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c index 7582cef417fff842f9ff840763b1442ed76fe0c2..91e375146ad7ff51d2f35e29027acae4d4b621c1 100644 --- a/arch/arm/mach-at91/arm920t/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -13,6 +13,7 @@ * Alex Zuepke */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index f7b4116344ca5adf40ec92f4cd7ce27c81493795..8ef5764e3153acfdf634d594fb5e51a942a4f5f7 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -13,7 +13,7 @@ * Alex Zuepke */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index 201c99ade4ec95c1bbc3e0f12e7de5ebf4b57f6d..c10571fa28a0386dabbe6e890a13f0a3819d2f93 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index b8d209cbec843566d2a3625cb15b16e6f47f3008..0c2b9f2ecc9bb764a32861f5634802eee73d4aa5 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 1749662dae9cee4dcbcf30ee0a1d9ca84e5eddd0..3b8a4623866cb88aec23245561f49b2986da5c08 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -9,6 +9,7 @@ * esd electronic system design gmbh */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 4c481484c3d28d734f682628c2ec5280f1eed062..d517810c991ad9edf97afe4ebd4b4469ec7f7211 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 4dc6e51aba831bf568bd3d091970211ed38fc3fa..9f98ce7a45ca932e102904ffc188c2aa0ebdce09 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -4,6 +4,7 @@ * Josh Wu */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index 4f5bafb8c2e84363c24891a2d3a0add2d95fb594..b4002eb75046de2a677365a56e0a0a8904e8d8f0 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 40c8a58b5635489a7e9e1f8072c81279f165eb11..f44760bed31b6603a8babd6c314809762432620b 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 Atmel Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index 241de6a5378837dd91ea6379da975706bb75f6e6..013daf43b742469be895b459185eda00d34430b7 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -7,8 +7,7 @@ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index e476cd5bcf3d2c1bb16fe4c0015d227199d4390c..5e84b0a40e1388b5e430e377a83c459c9839ecfc 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -6,7 +6,7 @@ * Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index bb66700566e5f4f0eedf10e30d5f3bdc573b25db..aade13cc014b83fbdc2bb0a457a9482aee6612d3 100644 --- a/arch/arm/mach-at91/arm926ejs/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -42,6 +42,7 @@ * someone puts a jffs2 into them) * do a read-modify-write for partially programmed pages */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index 01b2663f96c9288395b14d0209ff332ac527b976..6acbfa33011dfefd430a214b587a575b4d3d390c 100644 --- a/arch/arm/mach-at91/arm926ejs/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c index 97c572deaaf0e30af984f682c4b0283b0d744b27..e3d3dd880cad2446e5d11242209095551f2af46f 100644 --- a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c +++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries */ +#include #include #include #include diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index 137a5e5b8fd0bd36ccd2d9201ffaf9d9c9381432..a8cf0e4bd7992aa9a05414ee761141f3da70301e 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -5,6 +5,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 5357b4cffc2cc711f732b1314bd2a221e4e39f05..6bfa02d1d0a3ac06e646f964f3fe3e6c1b41f16b 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -9,7 +9,7 @@ * Copyright (C) 2015 Wenyou Yang */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index f4b2f4f351cb85e374f7e068093a673909e4a1f1..5ea7e2609f59df55fb808a02c14769bfe088769b 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -8,7 +8,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 469c221176651ff952a8b3e1f900cdcd320d2193..edc20574c31bb03b3e699f6bd533fbb341970e19 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -4,6 +4,7 @@ * Wenyou Yang */ +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 67b63208edaa4c1f59f1c8fd4cd4bcf2dbe55c2f..04b700a94d734c42415b43b148838245acd7a3f5 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -4,6 +4,7 @@ * Bo Shen */ +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index 76fff9cd466c1abe5dc590dc18157aaa494c8e08..e68ae994078858e11d1dfe5e550b28e32fd3b883 100644 --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -4,6 +4,7 @@ * Bo Shen */ +#include #include #include #include diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index bfdb75ce39a9d551c66ed9861d8bf51ac3345981..1f54c5dcad987522d2b0206cf2a45cd9a87e6d74 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -8,6 +8,7 @@ * Bo Shen */ +#include #include #include #include diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 019ef930022ffba30263192743a0ca199ff1b008..62108d2bd0a5db43ae42ab539170041efb8d99b8 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -4,7 +4,7 @@ * Wenyou Yang */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 442b822fe77f4b568e1f4ca6150e9c0601ef3946..8344daeb39a24eebd181e8991c40b1d1d30dbfc7 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -4,8 +4,8 @@ * Wenyou Yang */ +#include #include -#include #include #include #include diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index 683e539b1b3c63e8adb9292323c5b0b8bb8bae29..f7b411cf7dfa59ca239a373649b43a5f0dd9fc10 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -8,8 +8,6 @@ #ifndef AT91_COMMON_H #define AT91_COMMON_H -#include - void at91_can_hw_init(void); void at91_gmac_hw_init(void); void at91_macb_hw_init(void); diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c index 3bef5648d4a1ff0350244cb7aff168e12da43bee..2fa8493a0bd6a552ceb497d138eab8ecbce2a894 100644 --- a/arch/arm/mach-at91/matrix.c +++ b/arch/arm/mach-at91/matrix.c @@ -4,6 +4,7 @@ * Wenyou Yang */ +#include #include #include #include diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index ac6a719d9c08b282d1a8402f3c619c7093f97313..5422c05456e03c5aaa3837f045087e5728cb93be 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -7,6 +7,7 @@ * Wenyou Yang */ +#include #include #include #include diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c index ec38f5bc9315225736117f1112c2f0b0ae90f471..f4484a77c7de525d7dc65533cf8c316152c10908 100644 --- a/arch/arm/mach-at91/phy.c +++ b/arch/arm/mach-at91/phy.c @@ -11,7 +11,7 @@ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/sdram.c b/arch/arm/mach-at91/sdram.c index be3e91c7dbad5388e7349164e60c9a1f56b0b060..6638aa82bb6439e1bb6e2ea3af3c052ad00597f8 100644 --- a/arch/arm/mach-at91/sdram.c +++ b/arch/arm/mach-at91/sdram.c @@ -9,6 +9,7 @@ * Lead Tech Design */ +#include #include #include #include diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 5feb8f735511a45dd37ee04bb3742f57d8f2e067..8d537998c984fa858498117048fe05e5a9ae79f7 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -4,6 +4,7 @@ * Bo Shen */ +#include #include #include #include diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index cde1700a28396e5dd18dfbf28b0939b7a09af0ff..dfba9f730c12a9a22efad578433e794bf41e4bd7 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -8,7 +8,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 62a7df8a195f9ea1332204d31eb1a302bde3df96..a30c4f6c075f2ad1e13093b111b2463af047a7c0 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 6ce278c6d29678c7062f406530ffc8fb26bd4fa7..b3287ce8bcea9d6cf5af272ba08bc7dd44e559b1 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -163,7 +163,6 @@ config TARGET_RPI_4_32B This option creates a build targeting the ARMv7/AArch32 ISA. select BCM2711_32B - imply OF_HAS_PRIOR_STAGE config TARGET_RPI_4 bool "Raspberry Pi 4 64-bit build" @@ -189,7 +188,6 @@ config TARGET_RPI_4 This option creates a build targeting the ARMv8/AArch64 ISA. select BCM2711_64B - imply OF_HAS_PRIOR_STAGE config TARGET_RPI_ARM64 bool "Raspberry Pi one binary 64-bit build" @@ -197,7 +195,6 @@ config TARGET_RPI_ARM64 Support for all armv8 based Raspberry Pi variants, such as the RPi 4 model B, in AArch64 (64-bit) mode. select ARM64 - imply OF_HAS_PRIOR_STAGE endchoice diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 1b459707bc63a4f2ca5821121e020b11aaafbbe9..016bc1eb412951ef01bed599cf29f5237b490b29 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -6,6 +6,7 @@ * project. */ +#include #include #include #include diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c index c7cbfa72ffcce0998cc082ce58b94a82d5963b02..da9faafe1ddc64d21bf6354f4684d7a7b89e023a 100644 --- a/arch/arm/mach-bcm283x/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c @@ -3,9 +3,9 @@ * (C) Copyright 2012 Stephen Warren */ +#include #include #include -#include #include #include #include diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c index 4993c0bdb81905c72e41fc4c73dd36b2983e4ea9..2188b38d84b4a098c96e449bdd96d45400d30f26 100644 --- a/arch/arm/mach-bcm283x/msg.c +++ b/arch/arm/mach-bcm283x/msg.c @@ -3,6 +3,7 @@ * (C) Copyright 2012 Stephen Warren */ +#include #include #include #include diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index 9199234917f7d2e49829c13f31cad714562f0006..f13ac0c63757db3494caa1d578dd83b3c162782d 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -6,7 +6,7 @@ * project. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c index ca403bae99128efe2f2ba43c257e500c6092f837..5ab04083cc6c95d8f7b85ca67f93412564591d60 100644 --- a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c index b11effe06678032a62301bdfedaa8c5c5a5f0f31..52a53a2c76d08089ac5ed9ca40f9437c4eff2865 100644 --- a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c index a883e74ac00547cef3cb729f374e564b709a3b63..c6b7a54fbdfa16661de69586ab898cba5d76d065 100644 --- a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c index eb3cc3e5aec20c8ed2f67c20e50dd836e190e449..fe7efb30e22beb35a05e85a4c86e1885c60590da 100644 --- a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c index 458624e87aa9d9d74bc9c4f28ca18bbf76ec7e7d..eb736bf7d5085681874e9a8a6b879bd3a13b46d2 100644 --- a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c index 83c07727573ab0ea4e57ee38869dafb237e7b51d..8e53b4929eb81aa53cf1686c9761be42338e253c 100644 --- a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c index 82aba326dcb393a8a0fd718e3446e313863976cc..898291075f5e22779fb7fce76a101d33597e0b67 100644 --- a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c +++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c @@ -2,6 +2,7 @@ /* * Copyright 2022 Broadcom Ltd. */ +#include #include #include diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 25c5db49915bc4e98eb8fded9daee1ea20176b4f..8fa2660a0cdcc786ea01ffb54d20adb0836ab28a 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -9,6 +9,7 @@ config TARGET_DA850EVM select MACH_DAVINCI_DA850_EVM select SOC_DA850 select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index 7c0a2638977569a884cf865058d64b6a06d740ed..dae60262f5b7b86ab51e7cc0075ddfc98bc0b3cf 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 David Brownell */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 936b5e11667975a55619d126fc7581b6da41e680..08c8f59252437296cf062973101732d51c1128ba 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c index 4ee3cd0d5b34fd2d0c01c8182c41392e0f6f5f81..f2536c8dd6d6de02e370591cb9ef8cbfee0c942f 100644 --- a/arch/arm/mach-davinci/da850_pinmux.c +++ b/arch/arm/mach-davinci/da850_pinmux.c @@ -5,6 +5,7 @@ * Copyright (C) 2011 OMICRON electronics GmbH */ +#include #include #include #include diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 0d0ad1e593e1f248c8a09e0204921b00b24203b6..1133a23bdee321b9db8802da1b9b5e391e6ae016 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -6,7 +6,6 @@ #ifndef __MISC_H #define __MISC_H -#include #include /* pin muxer definitions */ diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 6c97e5810cdbae139a952455175608d3c7245e73..cfad28c43d0ad405f6758519e329efb1fb468947 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -8,7 +8,7 @@ * Copyright (C) 2004 Texas Instruments. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c index 5ecb434b03b6469df367615d56d00398d048a9bd..7904257b4a4224427cae6103ddd4d075e6815864 100644 --- a/arch/arm/mach-davinci/pinmux.c +++ b/arch/arm/mach-davinci/pinmux.c @@ -8,6 +8,7 @@ * Copyright (C) 2004 Texas Instruments. */ +#include #include #include #include diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 90b817860a62bd7bb00d5dd855380f241bac863a..dae10aa03bbb29c79d364efbb7d3bcdb41d504bd 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -7,6 +7,7 @@ * Copyright (C) 2004 Texas Instruments. */ +#include #include #include diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c index e3e2c56a6760ad3962f34e277bac7e17ab6ac919..0d59eb6e3cef6f1988403de43fe87122b62439b0 100644 --- a/arch/arm/mach-davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c @@ -6,6 +6,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ +#include #include #include #include diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 8c6cf9c219257d9f1799d48613693f03bebc88b4..5f5b9ebbf97aa9f0a8ac7cd271e408105ee9899a 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -3,10 +3,12 @@ * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ +#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index f2990f7187734f686124ad9ae42abfc2d18ed779..83c190b620e79163dc98c9a287eb3b1cc7582999 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -20,7 +20,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index ee71b95237df6b5a2d3c9e6f023cc602b8aa6b3e..f91f2ee862de25f5a3d868df5d8f3ff1d867c5ba 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -4,10 +4,9 @@ * Minkyu Kang */ +#include #include #include -#include -#include #include #include #include diff --git a/arch/arm/mach-exynos/clock_init_exynos4.c b/arch/arm/mach-exynos/clock_init_exynos4.c index 95ed1956a077594a95fed5c60f99fccf5c5b12b5..584e4bac09fcc0fe44fce035643a0c09aee5d709 100644 --- a/arch/arm/mach-exynos/clock_init_exynos4.c +++ b/arch/arm/mach-exynos/clock_init_exynos4.c @@ -23,6 +23,7 @@ * MA 02111-1307 USA */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index 232a2482dc656cefebc13fa74f75267cf96a370e..1cb8d391e7c92f9adb160784cc90a03c178b6b83 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -5,6 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 4f56160ee50a2d7f0bf02121821857181ae953e9..d7f02231fdfa0d3f3470703a9dd7f83e6f14450d 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -23,8 +23,6 @@ * MA 02111-1307 USA */ -#include -#include #include #define DMC_OFFSET 0x10000 diff --git a/arch/arm/mach-exynos/dmc_common.c b/arch/arm/mach-exynos/dmc_common.c index a96ded443b9a689c651a0486e8f652f080cb6992..44923dd5520f61a70d586721c512c2f1f643b5f0 100644 --- a/arch/arm/mach-exynos/dmc_common.c +++ b/arch/arm/mach-exynos/dmc_common.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include "clock_init.h" diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index 193de4c3a595f71ab048fc2cefc0e1bbdbb542c0..cad8ccc5315f79f30f7f19774a780c4a6dc20561 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -5,6 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index 4e508edba0c6b49d7ea0fe580f51b07c2c3175e8..e9874a8c1b24dda1e0481e95a776e6b386d2b6b9 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -8,7 +8,6 @@ #ifndef _SMDK5250_SETUP_H #define _SMDK5250_SETUP_H -#include #include #define NOT_AVAILABLE 0 diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index 757e1586bde4deb0dd0def4ae5855b0d29baa69a..a3d8974dcb5b054211556b653fb986aa3b8d4907 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -8,8 +8,6 @@ #define __ASM_ARM_ARCH_POWER_H_ #ifndef __ASSEMBLY__ -#include - struct exynos4_power { unsigned int om_stat; unsigned char res1[0x8]; diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 0967ab995a93ad7107758f4974cedf4e446a4993..c57b8aee798937adc31987cba8fd18f2691ddf7e 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -23,6 +23,7 @@ * MA 02111-1307 USA */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index e2f32547adfc5ba27a8e5a4efd2be47a08929fc9..30e522804fbf379822f2af34a8cc8f1f92a36816 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -4,6 +4,7 @@ * Thomas Abraham */ +#include #include #include diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 4061dd4aafaea117b6289cc38fc3bacdb5fe3dea..ad3fbf2da7a86d1089bfddb67994c36d7f05fdc7 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -4,6 +4,7 @@ * Abhilash Kesavan */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 599d3ccff60326fe5dd1afb6680cb35393a4738b..f2a6c00dd629cfdd48146abdee06eb1cea6f572d 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -4,7 +4,7 @@ * Donghwa Lee */ -#include +#include #include #include diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index be18f181a7aac67de9c833bbc8b2e5a10985df5e..aff2b5e1b6e863f46952b30a1a152d3e4d39bb03 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -4,6 +4,7 @@ * Minkyu Kang */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index bd5a06447b9c8977e06da9f26068921c0e7ac4bb..553dac75b61d6faa8c4cb23cd1c718c4d6da91db 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 Samsung Electronics */ +#include #include #include #include diff --git a/arch/arm/mach-exynos/system.c b/arch/arm/mach-exynos/system.c index f5090613c0d8779e15434a8e2424312fe6321ee1..12d0d8fd34a673cbbccd9c0a7939b1c8a823914a 100644 --- a/arch/arm/mach-exynos/system.c +++ b/arch/arm/mach-exynos/system.c @@ -4,7 +4,7 @@ * Donghwa Lee */ -#include +#include #include #include diff --git a/arch/arm/mach-exynos/tzpc.c b/arch/arm/mach-exynos/tzpc.c index 320a0cf351365a97f56d5b4c41325d165fecac9d..abe8e7f4589848243751997f074f88f253b2dcd1 100644 --- a/arch/arm/mach-exynos/tzpc.c +++ b/arch/arm/mach-exynos/tzpc.c @@ -5,7 +5,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include diff --git a/arch/arm/mach-highbank/timer.c b/arch/arm/mach-highbank/timer.c index 32ec6f0ac0e2fecb5a6cea7deb0ee785daffbc74..2423a0e378555efbc0982f1cefc41588a6f0cbb5 100644 --- a/arch/arm/mach-highbank/timer.c +++ b/arch/arm/mach-highbank/timer.c @@ -5,6 +5,7 @@ * Based on arm926ejs/mx27/timer.c */ +#include #include #include #include diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c index 84d02c9aca21321ecbed06d1c1213da65ab1b179..a26c2066e02887953005399ab8e01a6c94e5273b 100644 --- a/arch/arm/mach-histb/board_common.c +++ b/arch/arm/mach-histb/board_common.c @@ -5,6 +5,7 @@ * (C) Copyright 2023 Yang Xiwen */ +#include #include #include #include diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c index 76414558379f2c5eeedbe9ace9a96688fc1e7581..83a2bb94179906282a0f6f57160aa49f92270e91 100644 --- a/arch/arm/mach-histb/sysmap-histb.c +++ b/arch/arm/mach-histb/sysmap-histb.c @@ -5,6 +5,7 @@ * (C) Copyright 2023 Yang Xiwen */ +#include #include static struct mm_region histb_mem_map[] = { diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index b368db49fce562b913424117cc73d3d6df80760f..ab9b621a2a6284d76a00b0cf76b9695efb234e1a 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_bmode.c b/arch/arm/mach-imx/cmd_bmode.c index c20e80725f8ba93fafa8346acbd8088faddda326..5b2f4686230c195ffac433cb38fd6de0f5277272 100644 --- a/arch/arm/mach-imx/cmd_bmode.c +++ b/arch/arm/mach-imx/cmd_bmode.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index c7962ead2d54c565854077ae8988e8ad9b300a7a..2f389dbe8df0a02ff2addfebad255388c5b1f699 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -6,7 +6,7 @@ * Command for encapsulating DEK blob */ -#include +#include #include #include #include @@ -17,7 +17,6 @@ #include #include #include -#include #ifdef CONFIG_IMX_SECO_DEK_ENCAP #include #include diff --git a/arch/arm/mach-imx/cmd_hdmidet.c b/arch/arm/mach-imx/cmd_hdmidet.c index 8104ab26b08f2cbc1ea21726d5b342ac74c3aa45..e2571adfb0062326549bd76fed46ca58673724c9 100644 --- a/arch/arm/mach-imx/cmd_hdmidet.c +++ b/arch/arm/mach-imx/cmd_hdmidet.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 9925c9922687e47e441cb109b35a3dac47856f66..9576b48dde30f99ef4dbc14416d62ed51dd07f53 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index c2e452b69270cf83011bfc1f876f7f363b7f7cfc..70a213a49dd06b5eeccf6038c6a209d63361dfb5 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -11,6 +11,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index ceee31eecd7923a0b31c43e25ffb56fc24b5972e..488638c9058518a40116273eb99dbf57cef31eef 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-imx/ddrmc-vf610-calibration.c b/arch/arm/mach-imx/ddrmc-vf610-calibration.c index 2cf684322ea3f8206e57175e2a0c7f76e29f7cf4..7d787d0459807ea003d60be2c452314014b879af 100644 --- a/arch/arm/mach-imx/ddrmc-vf610-calibration.c +++ b/arch/arm/mach-imx/ddrmc-vf610-calibration.c @@ -7,6 +7,7 @@ * */ /* #define DEBUG */ +#include #include #include #include diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c index e449fa6f552d9500c46103f319e36f6b7ebb501b..7895ee66f8a8b7121485e9e6e540da09767586ed 100644 --- a/arch/arm/mach-imx/ddrmc-vf610.c +++ b/arch/arm/mach-imx/ddrmc-vf610.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index c13d9f0e00e3957a688534f3d869f3ac9f05badc..d02316ed6cb11b6f15c85bd1f6caaa1e8d8cd555 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -3,6 +3,7 @@ * Copyright 2022 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 85d90686f68043eae0b1eeb1136dd0412c3cabb9..27e053ef701c2f0660695cc4f046e235b617df05 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -3,6 +3,7 @@ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index 256db150818a98753a26591bd8ca259bb4f46f4c..a5866cf9f7034a39c2f93b4fbe201dcaf5c57ab9 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -2,8 +2,8 @@ /* * Copyright (C) 2012 Boundary Devices Inc. */ +#include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index e2388e3fef86116da2cb990a8a55abdf7610f081..35da0ae04258dbd31ed8778c9a2a80087078af21 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index ed44df394b154bd2a7d371594ca740b461b7cbfa..1c072f6af11d41a8df8a732545e2e24322bd8cc4 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -3,6 +3,7 @@ * Copyright 2018-2019, 2022 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 4e49b5bf3755a91ec89eeb7416c857c4a87393c2..9941b57b4be5160525b2f845ec1db5498945b5de 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 627baa1d83fdc29b98610ec4cbf44508634115d9..6e643188f4028394ec575c726e358887eee5dcf2 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -3,6 +3,7 @@ * Copyright 2018, 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index 6d0585f5cc67c2d513edfd347e068646e91af649..c2bed3e0c1fb61aaac5bf0502e9b4f9a6d8f6f29 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index 3e27d75827a5f4469275d3ffc6906afb538fd3c5..e4f7651bd1d4b6d3163342ff1e9ff19c29ead3d9 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index c77104d0338fa6107ed8b7a08d70025a154ae367..0ce3036818b66355612290b07ff97a8dc9eeb2a0 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index f13dfc1551652afa4cf969a48b71c96f1c086974..1eaa68f8d5ff88e3bbd1eb9b23b73994772b5273 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index de630e940c906fac615005e3dcb0aff795a01281..47219957b58c028ba46f438cd3fa966832636544 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 7e6c37487163613107c6f655e23c7d8edb07a1f8..9db62b944e4cb9e89157b01b23ce662c7f07e912 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 7cfdc46d349ede08fd53882f6d34a3464f48f168..b5ed27a923e07c323b5730c25df8553ebd9f4842 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c index f5644c642bd66e4de4247594b113488a0f37bb67..62f0b768cfa44cc1fb9855123044326ee608e7bb 100644 --- a/arch/arm/mach-imx/imx8m/psci.c +++ b/arch/arm/mach-imx/imx8m/psci.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index be38ca52885027831cefbc57af66872956b1b06b..0c49fb9cd48805371f7b18662dc804f5967c5ee2 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index f9d8ed5b048b616cac1b1398f906444beed09ae2..d2fadb4877c95466c9580ec33845f9c4762bcf88 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index fadf165ece2749d1385b20d7cf4c57a5ac56e92e..36d12943a05912d38058e37619e7c23772b52803 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c b/arch/arm/mach-imx/imx8ulp/iomux.c index 43f856bf732476eaaffedccf97066634d478bb06..c6d20f546809a6b7b6ea968c1da05589a24ea24b 100644 --- a/arch/arm/mach-imx/imx8ulp/iomux.c +++ b/arch/arm/mach-imx/imx8ulp/iomux.c @@ -3,6 +3,7 @@ * Copyright 2020-2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index 449e496521f10442c054ec4ef14fa2f4cc8ad321..e3c6d6760be202883adb70ff40dc20471cc4aab6 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index ca657748ed9a0865dbf32ccf7b89be98ff25e57b..cfc09e79cbd53838a51c52f038a00da1feb60eb6 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -3,8 +3,7 @@ * Copyright 2021 NXP */ -#include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 0abf4579a1e0e07678fee305a3085be1f9ffaa9c..75d92af036a1e520dd384b2c8bea6063bd0c094a 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 47106fffefba6794ebaf5f75131efe19e4779a55..7d7ae865946f3b232276b7cbdb17ddc586307bfa 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 73f2e72263d6edd8d6873fae952c72bcc0959858..6afb59e05159aa84a887a5326830d573afbcad33 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -3,12 +3,11 @@ * Copyright 2022 NXP */ +#include #include #include #include -#include #include -#include int arch_auxiliary_core_check_up(u32 core_id) { diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 32208220b207d4edc243f0b67f1bc052da0cce5d..2117489f23206e67592b98810b505e6ced493d22 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -5,7 +5,7 @@ * Peng Fan */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c index 8cdb28459a36685bf0716af6b0b7003358e064cf..d0f855bb1bc13bc1e41eb7deec31829cd39f99e2 100644 --- a/arch/arm/mach-imx/imx9/trdc.c +++ b/arch/arm/mach-imx/imx9/trdc.c @@ -3,8 +3,8 @@ * Copyright 2022 NXP */ +#include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 26374fdc33eca986c2cf7a661a1225ef0bf06f30..f7b14ca38d94263bebf7bf8dc5855921e6b6c1c4 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -3,18 +3,15 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include -#include #include #include #include #include #include -#include #include #include -#include -#include #include #ifndef CONFIG_IMX8 diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index 3028957953bdaff2d7feef10f1082b27d69154ad..34162a3976fbf1120ece470a4de396376717cfcf 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index c134e95ed78059fda725c65eb5f8cbed4deaa79d..18131a20f43800e52d27a550235ddb68821abcf8 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -7,6 +7,7 @@ * * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c index e739fd14c89820fee8a4641b50e607fccd3a37e9..9bb63d25b48833cd7a7716d9c871d4c518ee2e35 100644 --- a/arch/arm/mach-imx/mac.c +++ b/arch/arm/mach-imx/mac.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 7452b82f110557726d66c458f4cd69589118b525..09a758ff6e893286ae388b2450fc0a0529e0d962 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -3,6 +3,7 @@ * Copyright 2013 Stefan Roese */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 34a7d1706f3d75b8460ae18ebd3d1fe27470545e..9c822f721c600c1733e23fb6f6f59f7c84f0220f 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c index 2b1d203f8635f4c527209889f2cfe31d2282a965..41a5af6bd3077d911eddc72acde6f16966d0f7f6 100644 --- a/arch/arm/mach-imx/mmdc_size.c +++ b/arch/arm/mach-imx/mmdc_size.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #if defined(CONFIG_MX53) diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 0b8a10fd729448aa862f59989f5ec0a7df528762..bbaddd5a33faf3bb9ca21086d0ac9a45b196700a 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -6,6 +6,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435156ebb37295ae9b9c047547b2ba89..f74414419470653913606d75b88787801a2a6b07 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -4,6 +4,7 @@ * Patrick Bruenn */ +#include #include #include diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c index 4df5f9c164169e2f8ecba358cc26c9fec9855342..47f531dc856cd5cd6f5beaed5f803fdbb5d37cdb 100644 --- a/arch/arm/mach-imx/mx5/soc.c +++ b/arch/arm/mach-imx/mx5/soc.c @@ -6,6 +6,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index fb9f56d2e63ca5760638253ef7a97d39b5ba64d2..e0da9c2395841997cf54e01336cd8d3570a5cf5b 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -3,10 +3,10 @@ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 5a1258e002d2e7eb2416bb5bcca473f0101a7d17..3c87c577737b302fe7b099eba0a06d39de57daa7 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -4,6 +4,7 @@ * Author: Tim Harvey */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index ab5de2665778cbe69397d4d66c7aff1b261583be..2ba3245e226ca20c0105a7f814f4266e46d4c2d0 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 8b23d48a854cfb33e6d1327dd930c162f5c89b75..b58f11c1e562b338b30b38c41ddc33cb02d76ce9 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c index 091a37238316ab8ce173e70837eec023f216ac32..de9ace083ce8e7d26f6de40e5f68f22de8b339bb 100644 --- a/arch/arm/mach-imx/mx6/mp.c +++ b/arch/arm/mach-imx/mx6/mp.c @@ -6,6 +6,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 340e6147b63823ac48827d491f62ccebea51a2ad..38ead8ace20ce5f4dc8065c3a46e21ffc75aa8df 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 3a3e01f3d0aafe97c116178afe548491800544ea..c2875e727c946994cdf43b301af4164a5f5775cf 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -7,6 +7,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index a8606fa9b24b10bda8a6d7ff79dc064ad4be7cf9..4e232385afc36e809ccdd9ace1cdb18aa091ca55 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -6,12 +6,11 @@ * Peng Fan */ -#include +#include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/clock_slice.c b/arch/arm/mach-imx/mx7/clock_slice.c index 2a1304fc11283028bcce083788acb5be0ae602b6..dd731d94962144f613c2006aa32d818970fc111a 100644 --- a/arch/arm/mach-imx/mx7/clock_slice.c +++ b/arch/arm/mach-imx/mx7/clock_slice.c @@ -6,6 +6,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index c4a90be3945b5d55859d6f6bf429192c995f2dc3..cf25569765ea8a2a8e902ec35378418d47613acd 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -12,6 +12,7 @@ #include #include #include +#include #include /* diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 12d6a63b9255de37cf0e5294ea7f1e94378815b1..0b71fa4034462818cd0a9531aae5831456c3758c 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #define GPC_LPCR_A7_BSC 0x0 diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 16c77cbf7beee4a7876145d80eed1d64e12f7068..689dbefe8ee09344a8404c276c397c3d28710245 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -4,6 +4,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index fb19c62a520013d99f7c8a859e0a805f29acd8ce..37d8565c20fc689eec55fd4a0a19ec25a4065322 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/iomux.c b/arch/arm/mach-imx/mx7ulp/iomux.c index 2c87a8c18b9645b3f4342340391c538a80df8933..05ddeed2a64b4b196c29aa76e0c5bdae16703f5f 100644 --- a/arch/arm/mach-imx/mx7ulp/iomux.c +++ b/arch/arm/mach-imx/mx7ulp/iomux.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/pcc.c b/arch/arm/mach-imx/mx7ulp/pcc.c index 0bfd8f71815a5e6e530a15955d3a9890a2586401..aa7ea86a443e89a4cc4bec328d820552c6a4a1e5 100644 --- a/arch/arm/mach-imx/mx7ulp/pcc.c +++ b/arch/arm/mach-imx/mx7ulp/pcc.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index d4fb5389cacbca1793133cfb4a296dc06fb7a578..4c066557c1cafbebfd1520278d49cee5fe3752c5 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 198ae2d919c96168de711dee6a4acfabfbdabdf3..217b7c45867d35cf48d1b0dbc3cbd931f554a8cc 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 65924483bc890ddad00358277c80123561c29c42..5b022d5c8201f74063dce23e1871fbf8e18205b4 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -11,6 +11,7 @@ */ #include +#include #include #include diff --git a/arch/arm/mach-imx/rdc-sema.c b/arch/arm/mach-imx/rdc-sema.c index 56725cc109f0cae07a34e170b04fb95ed6f89362..e683673753e14cf8db41030e5442ab855b150420 100644 --- a/arch/arm/mach-imx/rdc-sema.c +++ b/arch/arm/mach-imx/rdc-sema.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c index 98a42b22f9cc9f9ba8a159dff1bd8c14298d0194..0e81cc880a1a15b0415f0c7b9fc105a87983a36c 100644 --- a/arch/arm/mach-imx/speed.c +++ b/arch/arm/mach-imx/speed.c @@ -7,7 +7,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index bc291dcd1296c3dbfdc308eaf8fd6444e829e14f..b30cd9625538f39bbbc185f92e1f84e72d8173c7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -6,7 +6,7 @@ * Author: Tim Harvey */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 9a86f5c133f73fa8943d4ad1b96a6b81bf682a11..b9ff9bb83b3ce213639ae8213f5935db276e805c 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 922f851c56b7fdccd8cf161aaf0473b8a6e8e751..16df1186759e9a0393ded38c1ffd7719dfc74555 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -5,7 +5,7 @@ * The file use ls102xa/timer.c as a reference. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index 5ac8f28e670d8a46be2d4a8bf253540ccef5fdf5..fcd45f09f1815b12551cc32fe84da6f5f9fe874f 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -6,6 +6,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 6cbb49da53cc1c6d26eb4ae315dcbf96580f2eb7..1bc9b7cc7e1591061afbea0b3cc8a6ba8682b475 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include -#include #include #ifdef CONFIG_IMX_HDMI diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index d0b286276c8d147793f4b4dc4e28612bc4e12494..59ec43e79051e7837e7bcf3fb11c7a5f798ff76c 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_SPL_BUILD) += am642_init.o -obj-y += boot.o diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 41812b7dbf74fa3fc0510911e7a00b57dca63679..e55582011637b28bb895ea57cc7193b5559cd727 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -286,7 +286,97 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) } } +static u32 __get_backup_bootmedia(u32 main_devstat) +{ + u32 bkup_bootmode = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 main_devstat) +{ + u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = + (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_NAND: + return BOOT_DEVICE_NAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + u32 spl_boot_device(void) { - return get_boot_device(); + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + + if (bootindex == K3_PRIMARY_BOOTMODE) + return __get_primary_bootmedia(devstat); + else + return __get_backup_bootmedia(devstat); } diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c deleted file mode 100644 index ce8ae941be6f598b562d121ed92b0a4733b12a09..0000000000000000000000000000000000000000 --- a/arch/arm/mach-k3/am64x/boot.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include - -static u32 __get_backup_bootmedia(u32 main_devstat) -{ - u32 bkup_bootmode = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; - u32 bkup_bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; - - switch (bkup_bootmode) { - case BACKUP_BOOT_DEVICE_UART: - return BOOT_DEVICE_UART; - - case BACKUP_BOOT_DEVICE_DFU: - if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BACKUP_BOOT_DEVICE_ETHERNET: - return BOOT_DEVICE_ETHERNET; - - case BACKUP_BOOT_DEVICE_MMC: - if (bkup_bootmode_cfg) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BACKUP_BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BACKUP_BOOT_DEVICE_I2C: - return BOOT_DEVICE_I2C; - }; - - return BOOT_DEVICE_RAM; -} - -static u32 __get_primary_bootmedia(u32 main_devstat) -{ - u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; - u32 bootmode_cfg = - (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - - switch (bootmode) { - case BOOT_DEVICE_OSPI: - fallthrough; - case BOOT_DEVICE_QSPI: - fallthrough; - case BOOT_DEVICE_XSPI: - fallthrough; - case BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BOOT_DEVICE_ETHERNET_RGMII: - fallthrough; - case BOOT_DEVICE_ETHERNET_RMII: - return BOOT_DEVICE_ETHERNET; - - case BOOT_DEVICE_EMMC: - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_NAND: - return BOOT_DEVICE_NAND; - - case BOOT_DEVICE_MMC: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> - MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_DFU: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BOOT_DEVICE_NOBOOT: - return BOOT_DEVICE_RAM; - } - - return bootmode; -} - -u32 get_boot_device(void) -{ - u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - u32 bootmode = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); - u32 bootmedia; - - if (bootmode == K3_PRIMARY_BOOTMODE) - bootmedia = __get_primary_bootmedia(devstat); - else - bootmedia = __get_backup_bootmedia(devstat); - - debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n", - __func__, devstat, bootmedia, bootmode); - - return bootmedia; -} diff --git a/arch/arm/mach-kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c index acd2e8b1145e7b9a33d1391d901adf9b801db9c3..009b7deeca64bd007bfd3c29c04bfae87e0bcb57 100644 --- a/arch/arm/mach-kirkwood/cache.c +++ b/arch/arm/mach-kirkwood/cache.c @@ -3,6 +3,7 @@ * Copyright (c) 2012 Michael Walle * Michael Walle */ +#include #include #include diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index a432abe615d37691d91c407d2d5df4b5ec736255..2b493b36c20d73b7c5b36fdc287a071205ed85ae 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -5,6 +5,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index e2757942590b404312c872047ef8f99dc412099a..4d1f58c0cbdf2626ad63f4682080bf26d1be76a6 100644 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -8,8 +8,6 @@ #ifndef __KIRKWOOD_MPP_H #define __KIRKWOOD_MPP_H -#include - #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ /* MPP number */ ((_num) & 0xff) | \ /* MPP select value */ (((_sel) & 0xf) << 8) | \ diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7938820e513f2bb9cda41ff5724ff93b654015ef..4fdad99cadef54c0acc63b761b1a44176e5f1dff 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -9,6 +9,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/clk.c b/arch/arm/mach-lpc32xx/clk.c index 2e11903e7e07a930a1bfe269ec01231d13e5939b..cb2344d79fec1a0e3b5a73eda3acc1584e93c628 100644 --- a/arch/arm/mach-lpc32xx/clk.c +++ b/arch/arm/mach-lpc32xx/clk.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 by Vladimir Zapolskiy */ +#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 80f5e7c88eb47dd3c05a5df50d312ff701eac0ec..a97f9a1958ab35370806e961523f7daefbcb3fd6 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2011-2015 by Vladimir Zapolskiy */ +#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 49308d6d4be0127c1f25321fc35df786ab8cb16a..6a67a3591aa6e981c7d86daa2b14e6ffa724594d 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -3,7 +3,7 @@ * Copyright (C) 2011 by Vladimir Zapolskiy */ -#include +#include #include #include diff --git a/arch/arm/mach-lpc32xx/dram.c b/arch/arm/mach-lpc32xx/dram.c index ab7c13512a5a88391a87daf1eafde7d57f3a46d2..160223792353ef244c8e27ff1cc3b3eea5244f34 100644 --- a/arch/arm/mach-lpc32xx/dram.c +++ b/arch/arm/mach-lpc32xx/dram.c @@ -10,6 +10,7 @@ * This code runs from SRAM. */ +#include #include #include #include diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 523f9cfc8c488b04c5854e14a3f3342eeb18071b..90183e3014ebbb737c3d9d42e6c5cbe07d05749f 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 Vladimir Zapolskiy */ +#include #include #include #include diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index ff1fdee5c8da2bc81916da02bc3b84974a7042ff..82018bd9d3e3fec0a7e88707680f8f62a7c538af 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -23,7 +23,6 @@ config TARGET_MT7622 config TARGET_MT7623 bool "MediaTek MT7623 SoC" select CPU_V7A - select MMC_SUPPORTS_TUNING help The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-450 graphics, several DDR3 options, diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c index 8e8bc4f9ceaa336bf1acf5ce4eed19ea02896701..c329e7cc98a87c8932c95bdfd73ede7c23227be5 100644 --- a/arch/arm/mach-mediatek/cpu.c +++ b/arch/arm/mach-mediatek/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 6e970acf8b052f6c3b2fbcfe44d8caded3fb1b83..00d3eb9ce7a47503f8ca78e8a3cf9709cd3e8341 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 3d6ba3f383c535e82b947366416b116dec02f718..988b057e5984fe1deeb46187169ae606459debb5 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index 7cb8b72c364c0ba88059ac04908c87e127616783..0130554ff35c66542a4fc678f7e66f3c8738f7dd 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 07da58971904393e0babb03c1d7c9c8b189385ac..862f0ca4793d5f5776bd6e2ac94c55bc1dc12620 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index a521c95bd9d39d0d06e608082fd942e871f1b2b4..905a3ab4e2721c331eacd6c8d2d12aa51f48bb59 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 2efc8c6a88fe88c4711f3573fce41b204d21ef49..082f12bf65e5bb5dde30f5a520f36050ca118629 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -8,6 +8,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-mediatek/mt8183/init.c b/arch/arm/mach-mediatek/mt8183/init.c index 37243547da81f4ecde9593e396e08eccb9a93587..7496029705f61ea4a76831a090af9a6e68e1b946 100644 --- a/arch/arm/mach-mediatek/mt8183/init.c +++ b/arch/arm/mach-mediatek/mt8183/init.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index 3b48caf5196c5dacff1b4f7e5dfe2ec3ea7c4a1e..5a21e9a4485c799cdd49aca1cb104071236bd32d 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 892bd441a33bd1a630f33576c5ec8b8d3ecf74cc..3460dcc249437a70e779d5dda3294f671469df6e 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index c04bcb6351780d077f67e7c47701e833a4656b8d..f7e03de36507e1c8feb18b07e5b6f3ae878c87df 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index 247d7ee6f1db43d88ebb9a57e47eeed0809da759..d3cda94617e1a7925d7cad17224d2330d429da88 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c index f848c0f068edcf1ae14963ca08d6139c47efa5d7..967bb671822ef701e7c9a537476822f635506d5d 100644 --- a/arch/arm/mach-meson/board-a1.c +++ b/arch/arm/mach-meson/board-a1.c @@ -3,12 +3,12 @@ * (C) Copyright 2023 SberDevices, Inc. */ +#include #include #include #include #include #include -#include #include phys_size_t get_effective_memsize(void) diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 6535539184ccfbb4cb891f5510a8c63ad274d602..fdf18752cdd05a6bf46578161c98b82b2c71ad3b 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -4,6 +4,7 @@ * (C) Copyright 2018 Neil Armstrong */ +#include #include #include #include diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 39774c43049a40ed11578086603717571bedd23b..7ceba7cede85c6e8bca409823a3ee488cbb569b6 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Beniamino Galvani */ +#include #include #include #include diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index dc4abe1e107469c8cdd3917fcecbcbb774632449..d5a830fb1db8de9c67db41f7013ccc9515f70f4c 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -4,6 +4,7 @@ * (C) Copyright 2018 Neil Armstrong */ +#include #include #include #include diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index 0370ed57e205073f431175eea9911e0d31861dab..c3fbdfffeae83687d627e4410e5c434332c6b136 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -4,6 +4,7 @@ * (C) Copyright 2018 Neil Armstrong */ +#include #include #include #include diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index b4058f593234e940fc2c00b82cdf9bd758cef567..d51d9b8f064512aa5445f5bb47c5d6d53a095dcc 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -4,6 +4,7 @@ * (C) Copyright 2019 Neil Armstrong */ +#include #include #include #include diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index 4d9f83d3b38d54e20d7d2bec997793cca5d7f0e4..914fd11c9894a5dace2bbceaf1489db61abf90ed 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -5,6 +5,7 @@ * Secure monitor calls. */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf902e17490816e7d55ce5a39e718029..0f72ae1709be37b4dcf1edf30e3d7fb385cbadf2 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marvell International Ltd. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/alleycat5/soc.c b/arch/arm/mach-mvebu/alleycat5/soc.c index 98e66735eb9eb546bbb3bbe20c54489589293e89..734b0a87dd498eb9dbf47a61d52cd340b7982559 100644 --- a/arch/arm/mach-mvebu/alleycat5/soc.c +++ b/arch/arm/mach-mvebu/alleycat5/soc.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Marvell International Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 63a12f7d77439b5fff8d25208cb20a34668ed6a6..4c67f1aba4defc99baf6de63022d885c143b5c3a 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e6828b7e5a8e940e15f8a1d5c7085f96..ab72b304e5daaedd829cee80e2a1b34aef53f597 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -4,6 +4,7 @@ * Copyright (C) 2020 Marek Behún */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c b/arch/arm/mach-mvebu/armada3700/efuse.c index 84a1e388c11b628cdff8a0dec4e2f764dbb2a2b9..07d5f394354c323da718e2d640cef6d2f36163ee 100644 --- a/arch/arm/mach-mvebu/armada3700/efuse.c +++ b/arch/arm/mach-mvebu/armada3700/efuse.c @@ -5,10 +5,9 @@ */ #include +#include #include #include -#include -#include #include #include diff --git a/arch/arm/mach-mvebu/armada3700/mbox.c b/arch/arm/mach-mvebu/armada3700/mbox.c index 5ac543abce5b664b9c94cdea70645f8fa48e1d88..6555b8673ce0648d72efadb6291aa53b7a2bf9b2 100644 --- a/arch/arm/mach-mvebu/armada3700/mbox.c +++ b/arch/arm/mach-mvebu/armada3700/mbox.c @@ -4,11 +4,11 @@ * Copyright (C) 2021 Pali Rohár */ +#include #include #include #include #include -#include #include #define RWTM_BASE (MVEBU_REGISTER(0xb0000)) diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 7908f75809c5eb3d5a8bc22c659c364195d3f1f3..939abce000f6ec2ed5c9b8c0ec391ef3cba21d2a 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e32b2e15c5d86e4a79e086d8878b7be..6c801bfa1db73131e26ddf97b838f5f3dc891f56 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index e603ab9ffb759097e4562acd8c0953f10d99a41e..7c62a5dbb6a00b4b988b1ea67cee963bdc45e3eb 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -3,7 +3,7 @@ * Copyright (C) 2014-2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc2c3bf60462d76d198a5d6c49d0fe6..d398d0f7676a68bc9e8b020a73a1350b795a1678 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index 475687955e059e535bd6057fc7fafbb38e30f053..be5dc0e07d9bcab8707efb4631e1fc22b80bad7c 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/gpio.c b/arch/arm/mach-mvebu/gpio.c index 587cbb00e7fc02294066a12c2b4288f62e846f14..1d1e3df8ba90f22cf898e8f5523080fb93f9f4da 100644 --- a/arch/arm/mach-mvebu/gpio.c +++ b/arch/arm/mach-mvebu/gpio.c @@ -5,6 +5,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 9baeece3c850724a77ac2a397542fa4499198004..959ca8e92602840c148711170dea3f9aa7c85cf5 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -46,7 +46,7 @@ * mvebu_mbus_del_window(). */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c index 4582871556d960023f397a2f13d96de264407ee1..12596ec2d8bdd1987aefd535e30071a2f181417b 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec-38x.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index efc31d5218ac6c2c5b921b4738f91579c5e2dd6e..3349f4eb54917e477a9cdcf6054695f7f4c38c83 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c index 9a1bbba7f2f4db97210672b590323385ef49a35c..2a51b7113ce4e2aa347c9394352b761cb375ed32 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/seq_exec.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index 8290b861c0795f92de9a567a04ed201cb174ce68..fb8ec11dfb95c6f8bf7c4b057896a8887af42c58 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 61b7f168697bb09f8f9ea46169d0b5c3b19bfa9c..68f8eade27221b24481035c9e07bf21e49e16902 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -3,7 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ -#include +#include #include #include #include diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c index 9b7bb2c38511cb096a9450a6e2b41405e67a4def..539d237623a14e1721b87d47773758165db7393d 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 4f4f7e00e3cff2f7449c270162cdb1f6801d01cd..79f8877745b35e1d6fdf84c0f6d329889aa8545c 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -3,6 +3,7 @@ * Copyright (C) 2014-2016 Stefan Roese */ +#include #include #include #include diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index d94bde0777c8df024efad78e8b13ce70e347bcb7..682431ee11d93471ff978538b16d3c2dc975e6a5 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -4,6 +4,7 @@ * Copyright (C) 2024 Marek Behún */ +#include #include #include #include diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 3082f6077b730961e9cd1944f1d5c7c3fc7a1323..59ffa26255f509073e975db1d918be934a21c257 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -4,8 +4,8 @@ * Hyunseok, Jung */ +#include #include -#include #include #include #include diff --git a/arch/arm/mach-nexell/include/mach/mipi_display.h b/arch/arm/mach-nexell/include/mach/mipi_display.h index 9183ffdd9c3d0e6d01447bb66fd560c035496e68..f3fdec64647c46582d8f2e9c4f30fecc6568ac1a 100644 --- a/arch/arm/mach-nexell/include/mach/mipi_display.h +++ b/arch/arm/mach-nexell/include/mach/mipi_display.h @@ -11,8 +11,6 @@ #ifndef MIPI_DISPLAY_H #define MIPI_DISPLAY_H -#include - /* MIPI DSI Processor-to-Peripheral transaction types */ enum { MIPI_DSI_V_SYNC_START = 0x01, diff --git a/arch/arm/mach-nexell/include/mach/reset.h b/arch/arm/mach-nexell/include/mach/reset.h index 0c6a13043f913d1698c19d63123ef6bf374d356b..e1301d4e53d334c2c0d8ef2f2a5636b080d822ca 100644 --- a/arch/arm/mach-nexell/include/mach/reset.h +++ b/arch/arm/mach-nexell/include/mach/reset.h @@ -7,8 +7,6 @@ #ifndef __NEXELL_RESET__ #define __NEXELL_RESET__ -#include - #define NUMBER_OF_RESET_MODULE_PIN 69 enum rstcon { diff --git a/arch/arm/mach-nexell/reset.c b/arch/arm/mach-nexell/reset.c index 627f568270b61af8822ddc9c41022aa48aeb52ec..1f732a3d373243bb731900f94825e55587a80d1f 100644 --- a/arch/arm/mach-nexell/reset.c +++ b/arch/arm/mach-nexell/reset.c @@ -8,6 +8,7 @@ *FIXME : Not support device tree & reset control driver. * will remove after support device tree & reset control driver. */ +#include #include #include #include diff --git a/arch/arm/mach-nexell/tieoff.c b/arch/arm/mach-nexell/tieoff.c index 51cca6744d6fb138704ed6587096695a4db312e3..5a4744c296a2d4aeaad63a31c1413955b7aa89ad 100644 --- a/arch/arm/mach-nexell/tieoff.c +++ b/arch/arm/mach-nexell/tieoff.c @@ -4,6 +4,7 @@ * Youngbok, Park */ +#include #include #include #include diff --git a/arch/arm/mach-nexell/timer.c b/arch/arm/mach-nexell/timer.c index b35c7b1bb33a77127be66572593e3a3ce0ec544d..3b311fd22a56f627dd80d7a05ea9d34d6550a5af 100644 --- a/arch/arm/mach-nexell/timer.c +++ b/arch/arm/mach-nexell/timer.c @@ -4,6 +4,7 @@ * Hyunseok, Jung */ +#include #include #include diff --git a/arch/arm/mach-npcm/npcm7xx/cpu.c b/arch/arm/mach-npcm/npcm7xx/cpu.c index 47d51cab5c7656cc0c9debd40e399fd6aa878081..dd74bb9e08719812262a7d036db375f12d95c4aa 100644 --- a/arch/arm/mach-npcm/npcm7xx/cpu.c +++ b/arch/arm/mach-npcm/npcm7xx/cpu.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index df80687c857198b58389c24e3dd3f0b9b327d338..ed4b1ca5c9833483d63e83ab488a2f31a7de7899 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -3,7 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include +#include #include #include diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index a1fb400b2645c7db22bdc35b1f6bff03bc0cf8ef..af594526094c5433a62d802bc10fa6e7edaee924 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/arch/arm/mach-npcm/npcm8xx/reset.c b/arch/arm/mach-npcm/npcm8xx/reset.c index e28b4ae7ae4bcba17aeec2a640bb0f765ff5e2e2..6954e6c6a17f68df968eaa0efb343a0781481718 100644 --- a/arch/arm/mach-npcm/npcm8xx/reset.c +++ b/arch/arm/mach-npcm/npcm8xx/reset.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c index ffdee8799fb6dec48a75377756f42275ac404d69..9da21077ecdcb7824dede7744b1e09aa218bda8a 100644 --- a/arch/arm/mach-octeontx/clock.c +++ b/arch/arm/mach-octeontx/clock.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c index 90454edca257e28220367a5ee8c0970cac8ca6f7..aa5f4585c6f50ce94ad04f7c1ff0d579143e708d 100644 --- a/arch/arm/mach-octeontx/cpu.c +++ b/arch/arm/mach-octeontx/cpu.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/arch/arm/mach-octeontx2/clock.c b/arch/arm/mach-octeontx2/clock.c index ffdee8799fb6dec48a75377756f42275ac404d69..9da21077ecdcb7824dede7744b1e09aa218bda8a 100644 --- a/arch/arm/mach-octeontx2/clock.c +++ b/arch/arm/mach-octeontx2/clock.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c index 0a44af71a40dea282a0cb79d4598de667c156fab..723deef719b6d31883fd76f4248c95c01b5f6221 100644 --- a/arch/arm/mach-octeontx2/cpu.c +++ b/arch/arm/mach-octeontx2/cpu.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/abb.c b/arch/arm/mach-omap2/abb.c index ce33d2fe129744a06d0822eec6e2473d1d1b6e88..722e6db0566d3f023bc8ad41850d41d820ac2c01 100644 --- a/arch/arm/mach-omap2/abb.c +++ b/arch/arm/mach-omap2/abb.c @@ -8,6 +8,7 @@ * Andrii Tseglytskyi */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 78c1e965c9f54f789cb75c5ff07a04abcc342184..09659da5867db74fb683ae1d746e4d6a5efe74c5 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 4765ce0adeeaea587224d6175f698d8527710625..d4f2abe17a97b8f16ef7b2e07f9ff99e36f8cc8f 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -4,6 +4,7 @@ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c index b75eb58ee827ad4b77eed0d9dfb3e4d0df4ec23e..0969a404bf69416697db2321b6c1d356c9738ef1 100644 --- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -7,7 +7,8 @@ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include + +#include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index f07003c95bc2954c56b69ee64a9f0d3fb831d2a4..3273632c648dbfded39d1cbf508e3b577a46da0c 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -7,6 +7,7 @@ * * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index c33d974dccdd60509c31da39904a8bba2a59989b..d39e7e4fed13d826007f48f197f3a4bdbd88de44 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -7,6 +7,7 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c index abd65ffd77fc90e64b887ff4eaa0e0c60ca351fa..8039bc2fe751714b880116a588e41ea92835d748 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -8,6 +8,7 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 41eec005cb1bfec1a31c91162dc977042f89474e..61b95c937338536c1c559c4bc2bc308141b4e48c 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index f19c66822d209bad38c6c8b829f2f621ec9ff2b5..b29250b8d2074c6c5153b29881e012a2b4042e4a 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -7,6 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/fdt.c b/arch/arm/mach-omap2/am33xx/fdt.c index 3e81616cb7465aecd296a9e81d5a216c5925dc6e..2ec30b1f9c38459ccac7ce9298ade3d5d5902b8b 100644 --- a/arch/arm/mach-omap2/am33xx/fdt.c +++ b/arch/arm/mach-omap2/am33xx/fdt.c @@ -3,6 +3,7 @@ * Copyright 2017 Texas Instruments, Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c index 06b08e89e7fb75751dea467bd0aee325a41f393e..49605593979854fcb7072c59932ed6197383e517 100644 --- a/arch/arm/mach-omap2/am33xx/mux.c +++ b/arch/arm/mach-omap2/am33xx/mux.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 87afc096602df185284000c31827ba04b482c4ef..390d540e85a0ce211040a85ae44f3739134a4bbf 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -11,6 +11,7 @@ * Syed Mohammed Khasim */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index e1ea3515ac10804d6e25c915a85dceb75e705b4c..aa0ab13d5fb14d08400f44a3e4ddd1f2e952a401 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -7,6 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 2a0c22841d03f898b8da988a9f11895ab687fe82..390d1f2a649b9eb3c5c4b4a0907d6138422892cd 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -12,6 +12,7 @@ * Santosh Shilimkar * Rajendra Nayak */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 4d431e20779d8f620046c5c2c64c574abdeff02f..9daaeef731900da386b7627044e515ecc5baf6f7 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -8,7 +8,7 @@ * Aneesh V */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c index c6b4c03b5085224815d0eaa637672571d4c7c683..e90d5776703d06c77e54ab3f2ee5d259133ce691 100644 --- a/arch/arm/mach-omap2/fdt-common.c +++ b/arch/arm/mach-omap2/fdt-common.c @@ -3,7 +3,7 @@ * Copyright 2016-2017 Texas Instruments, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 138501602c357ed75a83e113a6c2a21596f9cf41..0e4572ca41a77e490635178c9f6ed2bf481ee09b 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -10,6 +10,7 @@ * Aneesh V * Steve Sakoman */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 00f144eb747b5ae2d79d9485c114fea42ec3219e..19197482aa42352b215eb5c262463970fe365653 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -12,7 +12,7 @@ * Syed Mohammed Khasim */ -#include +#include #include #include #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c83e8a749ecbefe0a3c5b82d002d4e3..36db5882433949455a08653b3705eedfeca842df 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -11,9 +11,9 @@ * Steve Sakoman */ +#include #include #include -#include #include #include diff --git a/arch/arm/mach-omap2/omap3/am35x_musb.c b/arch/arm/mach-omap2/omap3/am35x_musb.c index d3807623bc640eba1ef10ffb0a77b047a38ffbea..1121acc0058997667fb5949217d3f753b82e8ad3 100644 --- a/arch/arm/mach-omap2/omap3/am35x_musb.c +++ b/arch/arm/mach-omap2/omap3/am35x_musb.c @@ -8,8 +8,8 @@ * Hema HK */ +#include #include -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index c5ada607f9786d98cdffc513cc5f083bb74db64c..c76a95dd5d09a0ef4e2a07fa7ce22ce658f6a235 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -15,6 +15,7 @@ * Syed Mohammed Khasim * */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/boot.c b/arch/arm/mach-omap2/omap3/boot.c index 2a36a25e27999c5745bd6d383b488be3f3b0225a..ea26115b71189678f8190c0fc10ef7336c6e3a76 100644 --- a/arch/arm/mach-omap2/omap3/boot.c +++ b/arch/arm/mach-omap2/omap3/boot.c @@ -5,6 +5,7 @@ * Copyright (C) 2015 Paul Kocialkowski */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index 417d1eb846f34f829df2707783b8ccf4927bbb0a..13685e0567afa18799e20aa284feacf9189979c1 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -11,12 +11,11 @@ * Syed Mohammed Khasim */ -#include +#include #include #include #include #include -#include #include #include diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c index 7348e92cabdfe9392821f3eb6e16d70492491c7f..d0d0b7a75a610db70f535b25b03ef02c1db07faa 100644 --- a/arch/arm/mach-omap2/omap3/emac.c +++ b/arch/arm/mach-omap2/omap3/emac.c @@ -6,6 +6,7 @@ * (C) Copyright 2011, Ilya Yanok, Emcraft Systems */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65b7919ec0b899fb26bd5ca249670ec..4fbfb387ab085b4536e077fc8880e365363d0ede 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -9,7 +9,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 404333689f60d09b2a94c0e3a78b690f326884b0..4d27d82c7881eb90ae723d6b4a620d65690437a6 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -21,6 +21,7 @@ * Manikandan Pillai */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c index d4712629d9deabacdc2ad9750c44c5c702597819..84a0b0ade931956883cc639a9b820ef08d502a31 100644 --- a/arch/arm/mach-omap2/omap3/spl_id_nand.c +++ b/arch/arm/mach-omap2/omap3/spl_id_nand.c @@ -11,6 +11,7 @@ * Jian Zhang */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index 1e3fcd5979680d5324d00ab5bce9abb47ab5a5a0..5f535e2782770690c1de56a37e091a7c8c9bbca6 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -11,10 +11,9 @@ * Syed Mohammed Khasim */ -#include +#include #include #include /* get mem tables */ -#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c index a60249f7fd62a9901eaac07defb12c58aba44891..90b5380ae39866c66c1b06d702e3152712c16b48 100644 --- a/arch/arm/mach-omap2/omap4/boot.c +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -5,6 +5,7 @@ * Copyright (C) 2015 Paul Kocialkowski */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/emif.c b/arch/arm/mach-omap2/omap4/emif.c index 5b0d3b5c78a0b06c13747047eebf4e486f88ec58..35a51645be7fd3ca6308f0e3472219a3d43d9ff2 100644 --- a/arch/arm/mach-omap2/omap4/emif.c +++ b/arch/arm/mach-omap2/omap4/emif.c @@ -8,6 +8,7 @@ * Aneesh V */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c index a81d7655494998d4591499c209e30f0bf18de40e..d587a4d4def02fac763509faaab0ce40d84f977f 100644 --- a/arch/arm/mach-omap2/omap4/hw_data.c +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -8,6 +8,7 @@ * * Sricharan R */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c index e3e6cc8e57858cdeffa5ccc8da1c5ca742464464..27dfa9142dcd7be5091ea3ca772e2f00ce84dbe6 100644 --- a/arch/arm/mach-omap2/omap4/hwinit.c +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -10,6 +10,7 @@ * Aneesh V * Steve Sakoman */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c index a29a264016ed2eeb77507e03739a2e20a608db3a..2a18cf0215d9f76a5320081a1652121021e52760 100644 --- a/arch/arm/mach-omap2/omap4/sdram_elpida.c +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -9,6 +9,7 @@ * Aneesh V */ +#include #include #include diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 21da0b11661d85736d652d90e6ffa988ecbb2141..2f9f8e65d03e6f11b503f855fc303a0e5cca3ff1 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -8,7 +8,7 @@ * Andrii Tseglytskyi */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/boot.c b/arch/arm/mach-omap2/omap5/boot.c index 5b479a87516be24d2dfc4632eb0509f090b2d873..15d6836c6eaef0337d820daf69cf432207dd6ccb 100644 --- a/arch/arm/mach-omap2/omap5/boot.c +++ b/arch/arm/mach-omap2/omap5/boot.c @@ -5,6 +5,7 @@ * Copyright (C) 2015 Paul Kocialkowski */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index d50452b5a30b2a881525d63ffbe73b3a72721dd5..8569eff31ab5c3c45f2575c3c17efadb2f0fe013 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -6,7 +6,7 @@ * Lokesh Vutla */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/emif.c b/arch/arm/mach-omap2/omap5/emif.c index d243ff3bd8f05a0bc4ec137049d95874308e42a7..2de36b6feca6e1138e7566438771fb7a2ef72f3d 100644 --- a/arch/arm/mach-omap2/omap5/emif.c +++ b/arch/arm/mach-omap2/omap5/emif.c @@ -8,6 +8,7 @@ * Aneesh V for OMAP4 */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c index f75ec47d821037f2ec7cfb59866b03b6feaf8f7b..0ca02e664c4bc64ed7bd03af13ba14f31862320b 100644 --- a/arch/arm/mach-omap2/omap5/fdt.c +++ b/arch/arm/mach-omap2/omap5/fdt.c @@ -3,7 +3,7 @@ * Copyright 2016 Texas Instruments, Inc. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index e65727026effeae85bf236c1e5e48d2935d00391..b39132222ee5b820c8a68d2d903904d268f1d8b7 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -8,6 +8,7 @@ * * Sricharan R */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 7f41e85c4a6735ef4a5e4fed0ef78637c1d9fa7c..edab9a92982e4c5b2211c21285d57e9b8767c156 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -11,6 +11,7 @@ * Steve Sakoman * Sricharan */ +#include #include #include #include diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 6bf4cf4a75825867cff2eeac7b6ff35efd779184..786da45fac8321a8749581095b4390e8e6dd889a 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -10,6 +10,7 @@ * Sricharan R */ +#include #include #include diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 16bbc93f4a35cff74811f317ae3a3156d0327e34..64560b21e3f51112c07ec91b97721d1215a493d5 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -12,7 +12,7 @@ * Andrew F. Davis */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index ed0620e7b63f4f6aac10ee8721970df5ea7328f8..71fdf5bf487c79b1ebb90923bd253bd0577e1663 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -15,7 +15,7 @@ * Gary Jennejohn, DENX Software Engineering, */ -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 2326d153b12fefaa1e0bbff53bad7d696abe5032..0623281a3c7d12b531a886930daf8e8c904b2049 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -3,9 +3,9 @@ * Copyright 2011 Linaro Limited * Aneesh V */ +#include #include #include -#include #include #include #include diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index cb377aa12723fca9b77b1786e65ada0da460124c..054782efbdbd4b8ff935c0b7dc8161862b4f71b4 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index 58ee67eca50f32c086f0e1d689674732cbb644b5..ffae9a01e37c06cf5bd7081c93c3ba1c9921b81a 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -8,6 +8,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index 228a3f7ad07560bd479b24d9f9700956a449d2f0..5647f847d78fefc6e9eb221d07d12717619c15af 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -8,6 +8,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index 85736f04e6728304f19e178c07825aece81930f1..b373e59e6fe3cc06a7cab5046bfb8cbd68e6a0a7 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -7,7 +7,7 @@ * Written-by: Prafulla Wadaskar */ -#include +#include #include #include #include diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678258e9d6e2969122583facdf2a9df7..f0f46f2dcb74e134e64df514c1b71945cd43adf1 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -5,13 +5,13 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ -#include #include #include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c index 6f0a220320e4b9178ad2f4f7b97a38fd0c03abe9..81f6ca2e49195841c65135de178464c5955eb86c 100644 --- a/arch/arm/mach-owl/sysmap-owl.c +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ +#include #include static struct mm_region owl_mem_map[] = { diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index c50700df078d4514d82c0c62b92076a9030bb5ec..4dff9e07629dfae93710a0c0e62a7a0555e297b8 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -7,6 +7,7 @@ #include #include +#include #include #define GEN3_NR_REGIONS 16 diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9a0422d8cfbc84702ab815cf0e0cde..9934a775220b4ecd20f55d2417ce1e4cf4689ab9 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -8,6 +8,7 @@ #include #include +#include #include #define RZG2L_NR_REGIONS 16 diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 67d3b28d058f4435deb7748073e6fb5ccec962c0..ec3697f35824e79fa9b6f9782a7b2aac11b0fcd0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -166,6 +166,7 @@ config ROCKCHIP_RK3308 imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply OF_UPSTREAM imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_OTP @@ -196,6 +197,7 @@ config ROCKCHIP_RK3328 imply MISC imply MISC_INIT_R imply OF_LIVE + imply OF_UPSTREAM imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE @@ -251,7 +253,6 @@ config ROCKCHIP_RK3399 select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL - select SPL_DRIVERS_MISC select CLK select FIT select PINCTRL @@ -261,30 +262,40 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply BOOTSTD_FULL + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply DM_RNG + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply OF_UPSTREAM imply PARTITION_TYPE_GUID + imply PHY_GIGE if GMAC_ROCKCHIP imply PRE_CONSOLE_BUFFER + imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply TPL_CLK + imply TPL_DM imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT - imply TPL_SYS_MALLOC_SIMPLE - imply TPL_DRIVERS_MISC imply TPL_OF_CONTROL - imply TPL_DM + imply TPL_RAM imply TPL_REGMAP + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + imply TPL_SYS_MALLOC_SIMPLE imply TPL_SYSCON - imply TPL_RAM - imply TPL_CLK imply TPL_TINY_MEMSET - imply TPL_ROCKCHIP_COMMON_BOARD - imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT - imply BOOTSTD_FULL - imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT - imply MISC - imply ROCKCHIP_EFUSE - imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -311,6 +322,7 @@ config ROCKCHIP_RK3568 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply OF_UPSTREAM imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD @@ -343,6 +355,7 @@ config ROCKCHIP_RK3588 imply MISC_INIT_R imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP imply OF_LIBFDT_OVERLAY + imply OF_UPSTREAM imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD @@ -361,6 +374,7 @@ config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A imply ROCKCHIP_COMMON_BOARD + imply OF_UPSTREAM help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 8a57b8217ff2683749068777e6be99d915c105f2..cd226844b638773da19b2b325f3e60cfa15f08f2 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -8,7 +8,7 @@ * Based on puma-rk3399.c: * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index 55e9456668ae727a1afbc7e976e2218f1c362ad3..f9be396aa558f8fb560e8d9b766d9396fe087028 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 82a0b3efef927bff730d77bd0f0a430cb3b84fe5..b36e559e8719eba9dcfcf94609cf0e7f1cf179d0 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Google, Inc */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 14c7331e1ab2ee47a701a18fb71f7763840789ae..a62ff53c6a0484b251aedff71d78f04752f6cdf5 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index f0b3c5f83f47868869ffcd97e9b4ae161f23a6f3..db368a7b8c23b001a47555c201bdcd83f675f33a 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/clk_px30.c b/arch/arm/mach-rockchip/px30/clk_px30.c index 410134769f8cf44470cfc3396b90da6dc99623a2..7edf1321feb339f882139e9e48a5fd4933da8417 100644 --- a/arch/arm/mach-rockchip/px30/clk_px30.c +++ b/arch/arm/mach-rockchip/px30/clk_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8b1509e55f2102d5d131aa82fb0265d884d07500..2ec3289d75b7d012088c185cca037b88b5073e41 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/px30/syscon_px30.c b/arch/arm/mach-rockchip/px30/syscon_px30.c index c9de57493d8cf89bad64edafc1dde8ae9e90055c..37e88f5ccb912c2648da7cc3bb1d829ff87eb237 100644 --- a/arch/arm/mach-rockchip/px30/syscon_px30.c +++ b/arch/arm/mach-rockchip/px30/syscon_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 64e100172fac5f3383733dee0aac19395332d222..73f6d241a1cef1068f001ba7cdd00a5592aaed63 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -3,6 +3,7 @@ * (C) Copyright 2015-2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 9046601a75e81f34022431cbddb866cd35f25143..116dccd7b87a7a8cdee5ae4d83728bd8191a4038 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 6c92b31dc84647f69ff736a756ef6b09c9fdbca4..e8130abdd777891cbccd8e9e9e68e722f893b998 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 308b9e6b8a8a769f8a31677e0fb8d64b511b2c38..07cd29a33e69ff46739c35e392997e66893fb620 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c index 23b75269d507c8f2588744dc464ed14f5e71de1f..c2fd16079902950043e0bf45fa93c1d9cf2645e5 100644 --- a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c index 88057fad05014b49013d4724ae6212fd63cbcc13..c47526dca5dec8be0849bd33d1fd1dc283372b24 100644 --- a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 70b55ca8abf6c98173a5a332d4d5b81603d9bc13..9a95ff85041794d23393e8e57822463e4343bd5d 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c index ff269b53b542434fef78452a46f96c08f7320b93..a598f6400de345f81308e640548fcd3e03e8f840 100644 --- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index ae552af3ff598f7e16bdaaa3e9db9cbe0915f7d2..a1b038c64866f1d013267e32c802ed73b46c4ce1 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c index f81c57a48beef257dac69bfe27b40a955d23e5c2..1406d5d0d325d2aa6df49088ed9f3aee1aef3c70 100644 --- a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index c0e71c3fa90679a37c2afe77cc03202e5600123a..94d1d23e1f457b82ad6adf0483acdebb144d11a0 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 53b2eaa2d5345c629a199f3a18d45e65ef6cf6d1..ffdcaa49a1e5245a5f17d2a019b53ce0d091ed23 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index 6df054e5b27dd656f568b5298ddb12322f58874e..917ff37c0fc15bb2ae5f645fc0525dca5144b20e 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index 4703125392eb6875e2a7acb4fbd3da887f425d54..2e57672b246d438bca3dc793d4d9b96d38b0c7f9 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index c471a4c9fb74e8522f6c789a908a13e6f65a8f6c..0d9dca8173cd466af636ad9be3554460fef76d13 100644 --- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index af6c5d1f59b243241939c7b26db1bfce821dd702..fb4c0891d0dcdb957ece5ef172dbc0a62dbd98cf 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d1170f7e23d07cd339a4b93e838b6ea57726a5eb..70cf500291214ab96c3e5cc97e46b0799f1aa67d 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index 6413d0a88a16a90817b615886d3d51fb175884d6..8b2c2f323a71d1bbb9bc78cc14efa1f9572e5ffd 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c index 557e21f8199eb9e9f8d8180f51c0ac69de56f467..201bf661f9bb107cbc7a41fe0d7c4eddd9082fbb 100644 --- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f88638d15698bc7621fd489298ce2f155b6498d..a0915c72bfa0c51212c3bf19a61fe039741853ac 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -2,6 +2,7 @@ /* *Copyright (c) 2018 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c index 2d7e9711015271202eb10a0c39fa414a14cff23f..b380ff5723361129e2911e74a4ed3c061a91fdb8 100644 --- a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index b0c5af53da687d5208440998f33bb5ba59689891..70c0eb6f98e7419610229c786c0e1df1fb4002f9 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index c86d11943d6dbb42f4a56a601a0f2c470f977162..ca3fa81e1278b8b37c4e6ec856a6233c4b4dfa02 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index 02ed366d8b6fddc0f3f2e16ec6bf977f9922d5de..d2f267e63534dd6a722d525bf81909f7908df397 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index c4d41e52af08c80786f91e2cbbfaedd8657683af..b075319720d9230e59b1996b637cdad216a2ca88 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -4,6 +4,7 @@ * Author: Andy Yan */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f589bf67328d821cba8bf385c3d9c1ed80cf0537..8f5ca1dfa7c9c39099c171ed20bb412c202ba4d3 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -4,6 +4,7 @@ * Copyright (c) 2016 Andreas Färber */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index 7389c02836412074072c4026a35c55dec8fde1c6..dc2d831dd84fb7a1dab27b3f28eee7e8099f2d28 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -5,6 +5,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index de552b5903b5ca41ffdf4437ba00dbec4bce4f1b..9d9a837fc7489e09ce66ffa29f4619d913b359bb 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 2d7d0f82a2f13a434c77046fe07594d60b39ff67..7fa1d7c7b7af93bc2fa5457356fb8a677f2b7063 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index b92ad54ede5cf91229f2b5c5ba2bb447b254b2ae..2b5746cb31bba2e0b6ec8932de4d2e11481fe615 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c index 1c6b2ece602b59eeae7988e3f95a4642c2204796..8917edcbd304e1c72c3839cebeb84ead38be4b07 100644 --- a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 1b3e40074e3b427e1d1ef97b97d2b7a9bb4025cd..b30ea04f737a33ce55a17bbe2125a03009fab99b 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c index 255259eabfdaceca07928014621e7979cfe67652..5407e7827f5234fa999106199ea9dc91ca5e3a06 100644 --- a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c index 250ec423bd24b6ecca7855237f15b47d53bef1d6..3df0bf223e3016e2c37157830df96167b7b2247f 100644 --- a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c @@ -3,6 +3,7 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index d3162d3447e03d69851a9904c889e0793a802a7c..eb65dafe3a241b2136b3b71978b90373ceb315fe 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index f86567fcaf4ff4f7f0938467bffbc8c1cb90aeb1..7b2cf37d9da1e36f435a050a8e614047ca4b038d 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index 5659ae03d711769652a4f4f7a03d5f6e02b00a1d..44b53c407a78ca5839a8d24a6d154aad765b4d40 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -4,6 +4,7 @@ * Author: Andy Yan */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c index d68fbf1bd2514e11181e48041a539f5db09e10ab..babdf5720b248eb992a2f254b06f3cbbfc43472e 100644 --- a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c index 3d64fcd45949b242713583eb958734e24b79375d..bd8902718f203daa6bb10e5b8655573cf31afecb 100644 --- a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 1c10e9b9f2335ee77c77ab679f62426959894473..40eb9eb7b1967e169a61b306a0f8241628c0bc39 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c index 67d2f18a8d0f598f27ca55bede96e7caeb0bbd1d..599ea66e3d67d7761188de389a13f3fbd0e518fe 100644 --- a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1fb01e1c4b131ceb876711983675b73aaccad41f..f2a3d6b1400153c14b70a374d0f6757839423240 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -3,7 +3,7 @@ * Copyright (C) 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 3dce9b30898d49a86ec1963846ffdddea521e201..3543267aa574341023a7764918488592e5eec98d 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 50f04f9474a0d16da36c88a57ab7a39299ddfd5a..2c3e9789cc897e00f048a73a3d82dac84e046605 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index f0aec7c0fe02dbed6a02b05e6cc0ca6ee87fae87..b390bdf8278408e5ed7b40fd43ca702bbc1d2f70 100644 --- a/arch/arm/mach-s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c @@ -7,6 +7,7 @@ * based on arch/arm/cpu/armv7/omap3/cache.S */ +#include #include #include diff --git a/arch/arm/mach-s5pc1xx/clock.c b/arch/arm/mach-s5pc1xx/clock.c index b92ce1152f66baeee5c6bfb33e5274e2e4ec703c..c90c341b5082eb224dbcec8d9f74905084605e19 100644 --- a/arch/arm/mach-s5pc1xx/clock.c +++ b/arch/arm/mach-s5pc1xx/clock.c @@ -5,7 +5,7 @@ * Heungjun Kim */ -#include +#include #include #include #include diff --git a/arch/arm/mach-s5pc1xx/pinmux.c b/arch/arm/mach-s5pc1xx/pinmux.c index 23b9252827ae958007ca5ecb7c412956683ee98a..818d75164dee1204e32c335112db36bec1d62ac7 100644 --- a/arch/arm/mach-s5pc1xx/pinmux.c +++ b/arch/arm/mach-s5pc1xx/pinmux.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include int exynos_pinmux_config(int peripheral, int flags) diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig deleted file mode 100644 index 3846b4fd5b6efa77fc66428a904226182d8c69d6..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/Kconfig +++ /dev/null @@ -1,475 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -# All 32-bit platforms require SYS_ARM_CACHE_WRITETHROUGH -# But it is ignored if selected here, so it must be in the defconfig - -if ARCH_SC5XX - -config SC57X - bool - select SUPPORT_SPL - select CPU_V7A - select PANIC_HANG - select COMMON_CLK_ADI_SC57X - select TIMER - select ADI_SC5XX_TIMER - -config SC58X - bool - select SUPPORT_SPL - select CPU_V7A - select PANIC_HANG - select COMMON_CLK_ADI_SC58X - select TIMER - select ADI_SC5XX_TIMER - -config SC59X - bool - select SUPPORT_SPL - select CPU_V7A - select PANIC_HANG - select COMMON_CLK_ADI_SC594 - select TIMER - select ADI_SC5XX_TIMER - select NOP_PHY - -config SC59X_64 - bool - select SUPPORT_SPL - select PANIC_HANG - select MMC_SDHCI_ADMA_FORCE_32BIT - select ARM64 - select DM - select DM_SERIAL - select COMMON_CLK_ADI_SC598 - select GICV3 - select GIC_600_CLEAR_RDPD - select NOP_PHY - -config SC_BOOT_MODE - int "SC5XX boot mode select" - default 1 - range 0 7 - help - Mode 0: do nothing, just idle - Mode 1: boot ldr out of serial flash - Mode 7: boot ldr over uart - -config SC_BOOT_SPI_BUS - int "sc5xx spi boot bus" - default 2 - range 0 4 - help - This is the SPI peripheral number to use for booting, X in the - expression `sf probe X:Y` - -config SC_BOOT_SPI_SSEL - int "sc5xx spi boot chipselect" - default 1 - range 0 6 - help - This is the SPI chip select number to use for booting, Y in the - expression `sf probe X:Y` - -config SC_BOOT_OSPI_BUS - int "sc5xx ospi boot bus" - default 0 - help - This is the OSPI peripheral number to use for booting, X in the - expression `sf probe X:Y` - -config SC_BOOT_OSPI_SSEL - int "sc5xx ospi boot chipselect" - default 0 - help - This is the OSPI chip select number to use for booting, Y in the - expression `sf probe X:Y` - -config SYS_FLASH_BASE - hex - default 0x60000000 - -config UART_CONSOLE - int - default 0 - -config UART4_SERIAL - bool - depends on DM_SERIAL - default y - -config WDT_ADI - bool - default y - -config WATCHDOG_TIMEOUT_MSECS - int - default 30000 - -config DW_PORTS - int - default 1 - -config ADI_BUG_EZKHW21 - bool "SC584 EZKIT phy bug workaround" - depends on SC58X - help - This workaround affects the SC584 EZKIT and addresses bug EZKHW21. - It disables gigabit ethernet mode and limits the board to 100 Mbps - -config ADI_CARRIER_SOMCRR_EZKIT - bool "Support the EV-SOMCRR-EZKIT" - depends on (SC59X || SC59X_64) - help - Say y to include support for the EV-SOMCRR-EZKIT carrier board, - which is compatible with the SC594 and SC598 SOMs. The EZKIT is - mutually incompatible with the EZLITE. - -config ADI_CARRIER_SOMCRR_EZLITE - bool "Support the EV-SOMCRR-EZLITE" - depends on (SC59X || SC59X_64) - help - Say y to include support for the EV-SOMCRR-EZLITE carrier board, - which is compatible with the SC594 and SC598 SOMs. The EZLITE is - mutually incompatible with the EZKIT. - -config ADI_SPL_FORCE_BMODE - int "Force the SPL to use this BMODE device during next boot stage" - default 0 - range 0 9 - depends on SPL - help - Force the SPL to use this BMODE device during next boot stage. - For example, if booting via QSPI, we can force the second stage - Of the boot process to use other peripherals via: - 1 = QSPI -> QSPI - 5 = QSPI -> OSPI - 6 = QSPI -> eMMC - -config ADI_USE_DMC0 - bool "Configure DMC0" - default y - help - During hardware initialization, channel 0 of the DMC will be - initialized. Select this if you have DMC0 connected to external - DDR memory. This is expected to be true for every board using - an SC5xx SoC. - -config ADI_USE_DMC1 - bool "Configure DMC1" - help - During hardware initialization, channel 1 of the DMC will be - initialized. Not all processors have a DMC1. Select this if your - SoC has DMC1 and you have it connected to external DDR memory. - -config ADI_USE_DDR2 - bool "Configure DMC for DDR2 mode" - help - Configure the DMC in DDR2 mode. The default is DDR3 and not all - parts may actually support DDR2. Please consult the manual for - the SoC that you are using to determine if DDR2 mode is supported. - This also requires that DDR2 memory is present on the board or it - will probably cause strange failure. - -menu "Clock configuration" - -config CGU0_DF_DIV - int "CGU0_DF_DIV" - range 0 1 - help - Select 0 to pass CLKIN to PLL - Select 1 to pass CLKIN/2 to PLL - -config CGU0_VCO_MULT - int "CGU0_VCO_MULT" - range 0 127 - help - VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL - A value of 0 means 128 - -config CGU0_CCLK_DIV - int "CGU0_CCLK_DIV" - range 0 31 - help - CCLK_DIV controls the core clock divider - A value of 0 means 32 - CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV - -config CGU0_SCLK_DIV - int "CGU0_SCLK_DIV" - range 0 31 - help - SCLK_DIV controls the system clock divider - A value of 0 means 32 - SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV - -config CGU0_SCLK0_DIV - int "CGU0_SCLK0_DIV" - range 0 7 - help - A value of 0 means 8 - SCLK0 = SCLK / SCLK0_DIV - -config CGU0_SCLK1_DIV - int "CGU0_SCLK1_DIV" - depends on (SC57X || SC58X) - range 0 7 - help - A value of 0 means 8 - SCLK1 = SCLK / SCLK1_DIV - -config CGU0_DCLK_DIV - int "CGU0_DCLK_DIV" - range 0 31 - help - DCLK_DIV controls the DDR clock divider - A value of 0 means 32 - DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV - -config CGU0_OCLK_DIV - int "CGU0_OCLK_DIV" - range 0 127 - help - OCLK_DIV controls the output clock divider - A value of 0 means 128 - OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV - -config CGU0_DIV_S1SELEX - int "CGU0_DIV_S1SELEX" - depends on !SC57X && !SC58X - range 0 255 - help - CGU0 SCLK1 Extended divisor register. - A value of 0 means 256. - SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX - -config CGU0_CLKOUTSEL - int "CGU0_CLKOUTSEL" - default 0 - range 0 31 - help - Select signal driven through CLKOUT pin multiplexer. - This value varies on each SOC. Refer to - CGU_CLKOUTSEL.CLKOUTSEL in the Hardware Reference Manual - for values applicable to each SOC. - Commonly, values 0 and 1 select CLKIN0 or CLKIN1 respectively. - -config CGU1_PLL3_DDRCLK - bool "DDRCLK From 3rd PLL" - depends on SC59X_64 - help - 3rd PLL output is connected to DMC block when set. - When cleared, DDR clock is CLKO3 output of CDU. - -config CGU1_PLL3_VCO_MSEL - int "CGU0_PLL3_VCO_MSEL" - depends on CGU1_PLL3_DDRCLK - range 1 128 - help - PLL multiplier value for the 3rd PLL. - DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV - -config CGU1_PLL3_DCLK_DIV - int "CGU0_PLL3_DCLK_DIV" - depends on CGU1_PLL3_DDRCLK - range 1 32 - help - PLL divider value for the 3rd PLL. - DCLK = (CLKIN * PLL3_VCO_MSEL) / PLL3_DCLK_DIV - -config CGU1_DF_DIV - int "CGU1_DF_DIV" - range 0 1 - help - Select 0 to pass CLKIN to PLL - Select 1 to pass CLKIN/2 to PLL - -config CGU1_VCO_MULT - int "CGU1_VCO_MULT" - range 0 127 - help - VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL - A value of 0 means 128 - -config CGU1_CCLK_DIV - int "CGU1_CCLK_DIV" - range 0 31 - help - CCLK_DIV controls the core clock divider - A value of 0 means 32 - CCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / CCLK_DIV - -config CGU1_SCLK_DIV - int "CGU1_SCLK_DIV" - range 0 31 - help - SCLK_DIV controls the system clock divider - A value of 0 means 32 - SCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / SYSCLK_DIV - -config CGU1_SCLK0_DIV - int "CGU1_SCLK0_DIV" - depends on (SC57X || SC58X || SC59X) - range 0 7 - help - A value of 0 means 8 - SCLK0 = SCLK / SCLK0_DIV - -config CGU1_SCLK1_DIV - int "CGU1_SCLK1_DIV" - depends on (SC57X || SC58X) - range 0 7 - help - A value of 0 means 8 - SCLK1 = SCLK / SCLK1_DIV - -config CGU1_DCLK_DIV - int "CGU1_DCLK_DIV" - range 0 31 - help - DCLK_DIV controls the DDR clock divider - A value of 0 means 32 - DCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / DCLK_DIV - -config CGU1_OCLK_DIV - int "CGU1_OCLK_DIV" - range 0 127 - help - OCLK_DIV controls the output clock divider - A value of 0 means 128 - OCLK = ((CLKIN / (1 + DF)) * VCO_MULT) / OCLK_DIV - -config CGU1_DIV_S0SELEX - int "CGU1_DIV_S0SELEX" - depends on !SC57X && !SC58X && !SC59X - range 0 255 - help - CGU1 SCLK0 Extended divisor register. - A value of 0 means 256. - SCLK0 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S0SELEX - -config CGU1_DIV_S1SELEX - int "CGU1_DIV_S1SELEX" - depends on !SC57X && !SC58X - range 0 255 - help - CGU1 SCLK1 Extended divisor register. - A value of 0 means 256. - SCLK1 = ((CLKIN / (1 + DF)) * VCO_MULT) / DIV_S1SELEX - -config CDU0_CGU1_CLKIN - int "CDU0 CGU1 CLKINn Select" - default 0 - range 0 1 - help - Selects source clock for CGU1. - 0 for CLKIN0 - 1 for CLKIN1 - -config CDU0_CLKO0 - int "CDU0_CLKO0" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO1 - int "CDU0_CLKO1" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO2 - int "CDU0_CLKO2" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO3 - int "CDU0_CLKO3" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO4 - int "CDU0_CLKO4" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO5 - int "CDU0_CLKO5" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO6 - int "CDU0_CLKO6" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO7 - int "CDU0_CLKO7" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO8 - int "CDU0_CLKO8" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO9 - int "CDU0_CLKO9" - range 1 7 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO10 - int "CDU0_CLKO10" - range 1 7 - depends on (SC59X || SC59X_64) - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO12 - int "CDU0_CLKO12" - range 1 7 - depends on (SC59X || SC59X_64) - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO13 - int "CDU0_CLKO13" - range 1 7 - depends on SC59X_64 - help - Clock source select. Refer to SOC Hardware Reference Manual - -config CDU0_CLKO14 - int "CDU0_CLKO14" - range 1 7 - depends on SC59X_64 - help - Clock source select. Refer to SOC Hardware Reference Manual - -endmenu - -config ADI_GPIO - bool - default y - -config PINCTRL_ADI - bool - default y - -endif diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile deleted file mode 100644 index eeb56c078b32ae169c4295dcb90f5c945bdfd7d2..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -obj-y += soc.o init/ - -obj-$(CONFIG_SC57X) += sc57x.o -obj-$(CONFIG_SC58X) += sc58x.o -obj-$(CONFIG_SC59X) += sc59x.o -obj-$(CONFIG_SC59X_64) += sc59x_64.o - -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk deleted file mode 100644 index 580964e559c0cb24ba165b0978dc8f5d00af89c3..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -ifdef CONFIG_SPL_BUILD -INPUTS-y += $(obj)/u-boot-spl.ldr -endif - -LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE) -LDR_FLAGS += --use-vmas diff --git a/arch/arm/mach-sc5xx/init/Makefile b/arch/arm/mach-sc5xx/init/Makefile deleted file mode 100644 index 9d4920fe0763d6e957b9ee93d2142a43daf58ef2..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -obj-y += dmcinit.o clkinit.o diff --git a/arch/arm/mach-sc5xx/init/clkinit.c b/arch/arm/mach-sc5xx/init/clkinit.c deleted file mode 100644 index ae53cd61efd8d67ea7aca2c45d82bed6b872bbfe..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/clkinit.c +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include -#include "clkinit.h" -#include "dmcinit.h" - -#ifdef CONFIG_CGU0_SCLK0_DIV - #define VAL_CGU0_SCLK0_DIV CONFIG_CGU0_SCLK0_DIV -#else - #define VAL_CGU0_SCLK0_DIV 1 -#endif -#ifdef CONFIG_CGU0_SCLK1_DIV - #define VAL_CGU0_SCLK1_DIV CONFIG_CGU0_SCLK1_DIV -#else - #define VAL_CGU0_SCLK1_DIV 1 -#endif -#ifdef CONFIG_CGU0_DIV_S0SELEX - #define VAL_CGU0_DIV_S0SELEX CONFIG_CGU0_DIV_S0SELEX -#else - #define VAL_CGU0_DIV_S0SELEX -1 -#endif -#ifdef CONFIG_CGU0_DIV_S1SELEX - #define VAL_CGU0_DIV_S1SELEX CONFIG_CGU0_DIV_S1SELEX -#else - #define VAL_CGU0_DIV_S1SELEX -1 -#endif -#ifdef CONFIG_CGU0_CLKOUTSEL - #define VAL_CGU0_CLKOUTSEL CONFIG_CGU0_CLKOUTSEL -#else - #define VAL_CGU0_CLKOUTSEL -1 -#endif -#ifdef CONFIG_CGU1_SCLK0_DIV - #define VAL_CGU1_SCLK0_DIV CONFIG_CGU1_SCLK0_DIV -#else - #define VAL_CGU1_SCLK0_DIV 1 -#endif -#ifdef CONFIG_CGU1_SCLK1_DIV - #define VAL_CGU1_SCLK1_DIV CONFIG_CGU1_SCLK1_DIV -#else - #define VAL_CGU1_SCLK1_DIV 1 -#endif -#ifdef CONFIG_CGU1_DIV_S0SELEX - #define VAL_CGU1_DIV_S0SELEX CONFIG_CGU1_DIV_S0SELEX -#else - #define VAL_CGU1_DIV_S0SELEX -1 -#endif -#ifdef CONFIG_CGU1_DIV_S1SELEX - #define VAL_CGU1_DIV_S1SELEX CONFIG_CGU1_DIV_S1SELEX -#else - #define VAL_CGU1_DIV_S1SELEX -1 -#endif -#ifdef CONFIG_CGU1_CLKOUTSEL - #define VAL_CGU1_CLKOUTSEL CONFIG_CGU1_CLKOUTSEL -#else - #define VAL_CGU1_CLKOUTSEL -1 -#endif - -#define REG_MISC_REG10_tst_addr 0x310A902C - -#define CGU0_REGBASE 0x3108D000 -#define CGU1_REGBASE 0x3108E000 - -#define CGU_CTL 0x00 // CGU0 Control Register -#define CGU_PLLCTL 0x04 // CGU0 PLL Control Register -#define CGU_STAT 0x08 // CGU0 Status Register -#define CGU_DIV 0x0C // CGU0 Clocks Divisor Register -#define CGU_CLKOUTSEL 0x10 // CGU0 CLKOUT Select Register -#define CGU_DIVEX 0x40 // CGU0 DIV Register Extension - -#define BITP_CGU_DIV_OSEL 22 // OUTCLK Divisor -#define BITP_CGU_DIV_DSEL 16 // DCLK Divisor -#define BITP_CGU_DIV_S1SEL 13 // SCLK 1 Divisor -#define BITP_CGU_DIV_SYSSEL 8 // SYSCLK Divisor -#define BITP_CGU_DIV_S0SEL 5 // SCLK 0 Divisor -#define BITP_CGU_DIV_CSEL 0 // CCLK Divisor - -#define BITP_CGU_CTL_MSEL 8 // Multiplier Select -#define BITP_CGU_CTL_DF 0 // Divide Frequency - -#define BITM_CGU_STAT_CLKSALGN 0x00000008 -#define BITM_CGU_STAT_PLOCK 0x00000004 -#define BITM_CGU_STAT_PLLBP 0x00000002 -#define BITM_CGU_STAT_PLLEN 0x00000001 - -/* PLL Multiplier and Divisor Selections (Required Value, Bit Position) */ -/* PLL Multiplier Select */ -#define MSEL(X) (((X) << BITP_CGU_CTL_MSEL) & \ - BITM_CGU_CTL_MSEL) -/* Divide frequency[true or false] */ -#define DF(X) (((X) << BITP_CGU_CTL_DF) & \ - BITM_CGU_CTL_DF) -/* Core Clock Divisor Select */ -#define CSEL(X) (((X) << BITP_CGU_DIV_CSEL) & \ - BITM_CGU_DIV_CSEL) -/* System Clock Divisor Select */ -#define SYSSEL(X) (((X) << BITP_CGU_DIV_SYSSEL) & \ - BITM_CGU_DIV_SYSSEL) -/* SCLK0 Divisor Select */ -#define S0SEL(X) (((X) << BITP_CGU_DIV_S0SEL) & \ - BITM_CGU_DIV_S0SEL) -/* SCLK1 Divisor Select */ -#define S1SEL(X) (((X) << BITP_CGU_DIV_S1SEL) & \ - BITM_CGU_DIV_S1SEL) -/* DDR Clock Divisor Select */ -#define DSEL(X) (((X) << BITP_CGU_DIV_DSEL) & \ - BITM_CGU_DIV_DSEL) -/* OUTCLK Divisor Select */ -#define OSEL(X) (((X) << BITP_CGU_DIV_OSEL) & \ - BITM_CGU_DIV_OSEL) -/* CLKOUT select */ -#define CLKOUTSEL(X) (((X) << BITP_CGU_CLKOUTSEL_CLKOUTSEL) & \ - BITM_CGU_CLKOUTSEL_CLKOUTSEL) -#define S0SELEX(X) (((X) << BITP_CGU_DIVEX_S0SELEX) & \ - BITM_CGU_DIVEX_S0SELEX) -#define S1SELEX(X) (((X) << BITP_CGU_DIVEX_S1SELEX) & \ - BITM_CGU_DIVEX_S1SELEX) - -struct CGU_Settings { - phys_addr_t rbase; - u32 ctl_MSEL:7; - u32 ctl_DF:1; - u32 div_CSEL:5; - u32 div_SYSSEL:5; - u32 div_S0SEL:3; - u32 div_S1SEL:3; - u32 div_DSEL:5; - u32 div_OSEL:7; - s16 divex_S0SELEX; - s16 divex_S1SELEX; - s8 clkoutsel; -}; - -/* CGU Registers */ -#define BITM_CGU_CTL_LOCK 0x80000000 /* Lock */ - -#define BITM_CGU_CTL_MSEL 0x00007F00 /* Multiplier Select */ -#define BITM_CGU_CTL_DF 0x00000001 /* Divide Frequency */ -#define BITM_CGU_CTL_S1SELEXEN 0x00020000 /* SCLK1 Extension Divider Enable */ -#define BITM_CGU_CTL_S0SELEXEN 0x00010000 /* SCLK0 Extension Divider Enable */ - -#define BITM_CGU_DIV_LOCK 0x80000000 /* Lock */ -#define BITM_CGU_DIV_UPDT 0x40000000 /* Update Clock Divisors */ -#define BITM_CGU_DIV_ALGN 0x20000000 /* Align */ -#define BITM_CGU_DIV_OSEL 0x1FC00000 /* OUTCLK Divisor */ -#define BITM_CGU_DIV_DSEL 0x001F0000 /* DCLK Divisor */ -#define BITM_CGU_DIV_S1SEL 0x0000E000 /* SCLK 1 Divisor */ -#define BITM_CGU_DIV_SYSSEL 0x00001F00 /* SYSCLK Divisor */ -#define BITM_CGU_DIV_S0SEL 0x000000E0 /* SCLK 0 Divisor */ -#define BITM_CGU_DIV_CSEL 0x0000001F /* CCLK Divisor */ - -#define BITP_CGU_DIVEX_S0SELEX 0 -#define BITM_CGU_DIVEX_S0SELEX 0x000000FF /* SCLK 0 Extension Divisor */ - -#define BITP_CGU_DIVEX_S1SELEX 16 -#define BITM_CGU_DIVEX_S1SELEX 0x00FF0000 /* SCLK 1 Extension Divisor */ - -#define BITM_CGU_PLLCTL_PLLEN 0x00000008 /* PLL Enable */ -#define BITM_CGU_PLLCTL_PLLBPCL 0x00000002 /* PLL Bypass Clear */ -#define BITM_CGU_PLLCTL_PLLBPST 0x00000001 /* PLL Bypass Set */ - -#define BITP_CGU_CLKOUTSEL_CLKOUTSEL 0 /* CLKOUT Select */ -#define BITM_CGU_CLKOUTSEL_CLKOUTSEL 0x0000001F /* CLKOUT Select */ - -#define CGU_STAT_MASK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK | \ - BITM_CGU_STAT_CLKSALGN) -#define CGU_STAT_ALGN_LOCK (BITM_CGU_STAT_PLLEN | BITM_CGU_STAT_PLOCK) - -/* Clock Distribution Unit Registers */ -#define REG_CDU0_CFG0 0x3108F000 -#define REG_CDU0_CFG1 0x3108F004 -#define REG_CDU0_CFG2 0x3108F008 -#define REG_CDU0_CFG3 0x3108F00C -#define REG_CDU0_CFG4 0x3108F010 -#define REG_CDU0_CFG5 0x3108F014 -#define REG_CDU0_CFG6 0x3108F018 -#define REG_CDU0_CFG7 0x3108F01C -#define REG_CDU0_CFG8 0x3108F020 -#define REG_CDU0_CFG9 0x3108F024 -#define REG_CDU0_CFG10 0x3108F028 -#define REG_CDU0_CFG11 0x3108F02C -#define REG_CDU0_CFG12 0x3108F030 -#define REG_CDU0_CFG13 0x3108F034 -#define REG_CDU0_CFG14 0x3108F038 -#define REG_CDU0_STAT 0x3108F040 -#define REG_CDU0_CLKINSEL 0x3108F044 -#define REG_CDU0_REVID 0x3108F048 - -#define BITM_REG10_MSEL3 0x000007F0 -#define BITP_REG10_MSEL3 4 - -#define BITM_REG10_DSEL3 0x0001F000 -#define BITP_REG10_DSEL3 12 - -/* Selected clock macros */ -#define CGUn_MULT(cgu) ((CONFIG_CGU##cgu##_VCO_MULT == 0) ? \ - 128 : CONFIG_CGU##cgu##_VCO_MULT) -#define CGUn_DIV(clkname, cgu) ((CONFIG_CGU##cgu##_##clkname##_DIV == 0) ? \ - 32 : CONFIG_CGU##cgu##_##clkname##_DIV) -#define CCLK1_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ - (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ - CGUn_DIV(CCLK, cgu)) -#define CCLK2_n_RATIO(cgu) (((CGUn_MULT(cgu) * 2) / 3) / \ - (1 + CONFIG_CGU##cgu##_DF_DIV)) -#define DCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ - (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ - CGUn_DIV(DCLK, cgu)) -#define SYSCLK_n_RATIO(cgu) (((CGUn_MULT(cgu)) / \ - (1 + CONFIG_CGU##cgu##_DF_DIV)) / \ - CGUn_DIV(SCLK, cgu)) -#define PLL3_RATIO ((CONFIG_CGU1_PLL3_VCO_MSEL) / \ - (CONFIG_CGU1_PLL3_DCLK_DIV)) - -#if (1 == CONFIG_CDU0_CLKO2) - #define ARMCLK_IN 0 - #define ARMCLK_RATIO CCLK1_n_RATIO(0) -#elif (3 == CONFIG_CDU0_CLKO2) && \ - (defined(CONFIG_SC57X) || defined(CONFIG_SC58X)) - #define ARMCLK_IN 0 - #define ARMCLK_RATIO SYSCLK_n_RATIO(0) -#elif (5 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) - #define ARMCLK_IN 0 - #define ARMCLK_RATIO CCLK2_n_RATIO(0) -#elif (7 == CONFIG_CDU0_CLKO2) && defined(CONFIG_SC59X_64) - #define ARMCLK_IN CDU0_CGU1_CLKIN - #define ARMCLK_RATIO CCLK2_n_RATIO(1) -#endif - -#ifdef CONFIG_CGU1_PLL3_DDRCLK - #define DDRCLK_IN CDU0_CGU1_CLKIN - #define DDRCLK_RATIO PLL3_RATIO -#elif (1 == CONFIG_CDU0_CLKO3) - #define DDRCLK_IN 0 - #define DDRCLK_RATIO DCLK_n_RATIO(0) -#elif (3 == CONFIG_CDU0_CLKO3) - #define DDRCLK_IN CDU0_CGU1_CLKIN - #define DDRCLK_RATIO DCLK_n_RATIO(1) -#endif - -#ifndef ARMCLK_RATIO - #error Invalid/unknown ARMCLK selection! -#endif -#ifndef DDRCLK_RATIO - #error Invalid/unknown DDRCLK selection! -#endif - -#define ARMDDR_CLK_RATIO_FPERCISION 1000 - -#if ARMCLK_IN != DDRCLK_IN - #ifndef CUSTOM_ARMDDR_CLK_RATIO - /** - * SYS_CLKINx are defined within the device tree, not configs. - * Thus, we can only determine cross-CGU clock ratios if they - * use the same SYS_CLKINx. - */ - #error Define CUSTOM_ARMDDR_CLK_RATIO for different SYS_CLKINs - #else - #define ARMDDR_CLK_RATIO CUSTOM_ARMDDR_CLK_RATIO - #endif -#else - #define ARMDDR_CLK_RATIO (ARMDDR_CLK_RATIO_FPERCISION *\ - ARMCLK_RATIO / DDRCLK_RATIO) -#endif - -void dmcdelay(uint32_t delay) -{ - /* There is no zero-overhead loop on ARM, so assume each iteration - * takes 4 processor cycles (based on examination of -O3 and -Ofast - * output). - */ - u32 i, remainder; - - /* Convert DDR cycles to core clock cycles */ - u32 f = delay * ARMDDR_CLK_RATIO; - - delay = f + 500; - delay /= ARMDDR_CLK_RATIO_FPERCISION; - - /* Round up to multiple of 4 */ - remainder = delay % 4; - if (remainder != 0u) - delay += (4u - remainder); - - for (i = 0; i < delay; i += 4) - asm("nop"); -} - -static void program_cgu(const struct CGU_Settings *cgu) -{ - const uintptr_t b = cgu->rbase; - const bool use_extension0 = cgu->divex_S0SELEX >= 0; - const bool use_extension1 = cgu->divex_S1SELEX >= 0; - u32 temp; - - temp = OSEL(cgu->div_OSEL); - temp |= SYSSEL(cgu->div_SYSSEL); - temp |= CSEL(cgu->div_CSEL); - temp |= DSEL(cgu->div_DSEL); - temp |= (S0SEL(cgu->div_S0SEL)); - temp |= (S1SEL(cgu->div_S1SEL)); - temp &= ~BITM_CGU_DIV_LOCK; - - //Put PLL in to Bypass Mode - writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPST, - b + CGU_PLLCTL); - while (!(readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP)) - ; - - while (!((readl(b + CGU_STAT) & CGU_STAT_MASK) == CGU_STAT_ALGN_LOCK)) - ; - - dmcdelay(1000); - - writel(temp & (~BITM_CGU_DIV_ALGN) & (~BITM_CGU_DIV_UPDT), - b + CGU_DIV); - - dmcdelay(1000); - - temp = MSEL(cgu->ctl_MSEL) | DF(cgu->ctl_DF); - if (use_extension0) - temp |= BITM_CGU_CTL_S0SELEXEN; - if (use_extension1) - temp |= BITM_CGU_CTL_S1SELEXEN; - - writel(temp & (~BITM_CGU_CTL_LOCK), b + CGU_CTL); - - if (use_extension0 || use_extension1) { - u32 mask = BITM_CGU_CTL_S1SELEXEN | BITM_CGU_CTL_S0SELEXEN; - - while (!(readl(b + CGU_CTL) & mask)) - ; - - temp = readl(b + CGU_DIVEX); - - if (use_extension0) { - temp &= ~BITM_CGU_DIVEX_S0SELEX; - temp |= S0SELEX(cgu->divex_S0SELEX); - } - - if (use_extension1) { - temp &= ~BITM_CGU_DIVEX_S1SELEX; - temp |= S1SELEX(cgu->divex_S1SELEX); - } - - writel(temp, b + CGU_DIVEX); - } - - dmcdelay(1000); - - //Take PLL out of Bypass Mode - writel(BITM_CGU_PLLCTL_PLLEN | BITM_CGU_PLLCTL_PLLBPCL, - b + CGU_PLLCTL); - while ((readl(b + CGU_STAT) & - (BITM_CGU_STAT_PLLBP | BITM_CGU_STAT_CLKSALGN))) - ; - - dmcdelay(1000); - - if (cgu->clkoutsel >= 0) { - temp = readl(b + CGU_CLKOUTSEL); - temp &= ~BITM_CGU_CLKOUTSEL_CLKOUTSEL; - temp |= CLKOUTSEL(cgu->clkoutsel); - writel(temp, b + CGU_CLKOUTSEL); - } -} - -void adi_config_third_pll(void) -{ -#if defined(CONFIG_CGU1_PLL3_VCO_MSEL) && defined(CONFIG_CGU1_PLL3_DCLK_DIV) - u32 temp; - - u32 msel = CONFIG_CGU1_PLL3_VCO_MSEL - 1; - u32 dsel = CONFIG_CGU1_PLL3_DCLK_DIV - 1; - - temp = readl(REG_MISC_REG10_tst_addr); - temp &= 0xFFFE0000; - writel(temp, REG_MISC_REG10_tst_addr); - - dmcdelay(4000u); - - //update MSEL [10:4] - temp = readl(REG_MISC_REG10_tst_addr); - temp |= ((msel << BITP_REG10_MSEL3) & BITM_REG10_MSEL3); - writel(temp, REG_MISC_REG10_tst_addr); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x2; - writel(temp, REG_MISC_REG10_tst_addr); - - dmcdelay(100000u); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x1; - writel(temp, REG_MISC_REG10_tst_addr); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x800; - writel(temp, REG_MISC_REG10_tst_addr); - - temp = readl(REG_MISC_REG10_tst_addr); - temp &= 0xFFFFF7F8; - writel(temp, REG_MISC_REG10_tst_addr); - - dmcdelay(4000u); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= ((dsel << BITP_REG10_DSEL3) & BITM_REG10_DSEL3); - writel(temp, REG_MISC_REG10_tst_addr); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x4; - writel(temp, REG_MISC_REG10_tst_addr); - - dmcdelay(100000u); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x1; - writel(temp, REG_MISC_REG10_tst_addr); - - temp = readl(REG_MISC_REG10_tst_addr); - temp |= 0x800; - writel(temp, REG_MISC_REG10_tst_addr); -#endif -} - -static void Active_To_Fullon(const struct CGU_Settings *pCGU) -{ - u32 tmp; - - while (1) { - tmp = readl(pCGU->rbase + CGU_STAT); - if ((tmp & BITM_CGU_STAT_PLLEN) && - (tmp & BITM_CGU_STAT_PLLBP)) - break; - } - - writel(BITM_CGU_PLLCTL_PLLBPCL, pCGU->rbase + CGU_PLLCTL); - - while (1) { - tmp = readl(pCGU->rbase + CGU_STAT); - if ((tmp & BITM_CGU_STAT_PLLEN) && - ~(tmp & BITM_CGU_STAT_PLLBP) && - ~(tmp & BITM_CGU_STAT_CLKSALGN)) - break; - } -} - -static void CGU_Init(const struct CGU_Settings *pCGU) -{ - const uintptr_t b = pCGU->rbase; - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLEN) - writel(BITM_CGU_PLLCTL_PLLEN, b + CGU_PLLCTL); - - dmcdelay(1000); -#endif - - /* Check if processor is in Active mode */ - if (readl(b + CGU_STAT) & BITM_CGU_STAT_PLLBP) - Active_To_Fullon(pCGU); - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - dmcdelay(1000); -#endif - - program_cgu(pCGU); -} - -void cgu_init(void) -{ - const struct CGU_Settings dividers0 = { - .rbase = CGU0_REGBASE, - .ctl_MSEL = CONFIG_CGU0_VCO_MULT, - .ctl_DF = CONFIG_CGU0_DF_DIV, - .div_CSEL = CONFIG_CGU0_CCLK_DIV, - .div_SYSSEL = CONFIG_CGU0_SCLK_DIV, - .div_S0SEL = VAL_CGU0_SCLK0_DIV, - .div_S1SEL = VAL_CGU0_SCLK1_DIV, - .div_DSEL = CONFIG_CGU0_DCLK_DIV, - .div_OSEL = CONFIG_CGU0_OCLK_DIV, - .divex_S0SELEX = VAL_CGU0_DIV_S0SELEX, - .divex_S1SELEX = VAL_CGU0_DIV_S1SELEX, - .clkoutsel = VAL_CGU0_CLKOUTSEL, - }; - const struct CGU_Settings dividers1 = { - .rbase = CGU1_REGBASE, - .ctl_MSEL = CONFIG_CGU1_VCO_MULT, - .ctl_DF = CONFIG_CGU1_DF_DIV, - .div_CSEL = CONFIG_CGU1_CCLK_DIV, - .div_SYSSEL = CONFIG_CGU1_SCLK_DIV, - .div_S0SEL = VAL_CGU1_SCLK0_DIV, - .div_S1SEL = VAL_CGU1_SCLK1_DIV, - .div_DSEL = CONFIG_CGU1_DCLK_DIV, - .div_OSEL = CONFIG_CGU1_OCLK_DIV, - .divex_S0SELEX = VAL_CGU1_DIV_S0SELEX, - .divex_S1SELEX = VAL_CGU1_DIV_S1SELEX, - .clkoutsel = VAL_CGU1_CLKOUTSEL, - }; - - CGU_Init(÷rs0); - CGU_Init(÷rs1); -} - -#define CONFIGURE_CDU0(a, b, c) \ - writel(a, b); \ - while (readl(REG_CDU0_STAT) & (1 << (c))) - -void cdu_init(void) -{ - while (readl(REG_CDU0_STAT) & 0xffff) - ; - writel((CONFIG_CDU0_CGU1_CLKIN & 0x1), REG_CDU0_CLKINSEL); - - CONFIGURE_CDU0(CONFIG_CDU0_CLKO0, REG_CDU0_CFG0, 0); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO1, REG_CDU0_CFG1, 1); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO2, REG_CDU0_CFG2, 2); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO3, REG_CDU0_CFG3, 3); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO4, REG_CDU0_CFG4, 4); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO5, REG_CDU0_CFG5, 5); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO6, REG_CDU0_CFG6, 6); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO7, REG_CDU0_CFG7, 7); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO8, REG_CDU0_CFG8, 8); - CONFIGURE_CDU0(CONFIG_CDU0_CLKO9, REG_CDU0_CFG9, 9); -#ifdef CONFIG_CDU0_CLKO10 - CONFIGURE_CDU0(CONFIG_CDU0_CLKO10, REG_CDU0_CFG10, 10); -#endif -#ifdef CONFIG_CDU0_CLKO12 - CONFIGURE_CDU0(CONFIG_CDU0_CLKO12, REG_CDU0_CFG12, 12); -#endif -#ifdef CONFIG_CDU0_CLKO13 - CONFIGURE_CDU0(CONFIG_CDU0_CLKO13, REG_CDU0_CFG13, 13); -#endif -#ifdef CONFIG_CDU0_CLKO14 - CONFIGURE_CDU0(CONFIG_CDU0_CLKO14, REG_CDU0_CFG14, 14); -#endif -} - -void clks_init(void) -{ - adi_dmc_reset_lanes(true); - - cdu_init(); - cgu_init(); - - adi_config_third_pll(); - - adi_dmc_reset_lanes(false); -} diff --git a/arch/arm/mach-sc5xx/init/clkinit.h b/arch/arm/mach-sc5xx/init/clkinit.h deleted file mode 100644 index b05f4325bfca8275faf40abfbfbd5ddcbafeb58b..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/clkinit.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef CLKINIT_H_ -#define CLKINIT_H_ - -void clks_init(void); - -void dmcdelay(uint32_t delay); - -#endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c deleted file mode 100644 index e375b5c9dfa14a7adc61b1328309494003754431..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ /dev/null @@ -1,954 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include -#include "clkinit.h" -#include "dmcinit.h" - -#define REG_DMC0_BASE 0x31070000 -#define REG_DMC1_BASE 0x31073000 - -#define REG_DMC_CTL 0x0004 // Control Register -#define REG_DMC_STAT 0x0008 // Status Register -#define REG_DMC_CFG 0x0040 // Configuration Register -#define REG_DMC_TR0 0x0044 // Timing 0 Register -#define REG_DMC_TR1 0x0048 // Timing 1 Register -#define REG_DMC_TR2 0x004C // Timing 2 Register -#define REG_DMC_MR 0x0060 // Shadow MR Register (DDR3) -#define REG_DMC_EMR1 0x0064 // Shadow EMR1 Register -#define REG_DMC_EMR2 0x0068 // Shadow EMR2 Register -#define REG_DMC_EMR3 0x006C -#define REG_DMC_DLLCTL 0x0080 // DLL Control Register -#define REG_DMC_DT_CALIB_ADDR 0x0090 // Data Calibration Address Register -#define REG_DMC_CPHY_CTL 0x01C0 // Controller to PHY Interface Register - -/* SC57x && SC58x DMC REGs */ -#define REG_DMC_PHY_CTL0 0x1000 // PHY Control 0 Register -#define REG_DMC_PHY_CTL1 0x1004 // PHY Control 1 Register -#define REG_DMC_PHY_CTL2 0x1008 // PHY Control 2 Register -#define REG_DMC_PHY_CTL3 0x100c // PHY Control 3 Register -#define REG_DMC_PHY_CTL4 0x1010 // PHY Control 4 Register -#define REG_DMC_CAL_PADCTL0 0x1034 // CALIBRATION PAD CTL 0 Register -#define REG_DMC_CAL_PADCTL2 0x103C // CALIBRATION PAD CTL2 Register -/* END */ - -/* SC59x DMC REGs */ -#define REG_DMC_DDR_LANE0_CTL0 0x1000 // Data Lane 0 Control Register 0 -#define REG_DMC_DDR_LANE0_CTL1 0x1004 // Data Lane 0 Control Register 1 -#define REG_DMC_DDR_LANE1_CTL0 0x100C // Data Lane 1 Control Register 0 -#define REG_DMC_DDR_LANE1_CTL1 0x1010 // Data Lane 1 Control Register 1 -#define REG_DMC_DDR_ROOT_CTL 0x1018 // DDR ROOT Module Control Register -#define REG_DMC_DDR_ZQ_CTL0 0x1034 // DDR Calibration Control Register 0 -#define REG_DMC_DDR_ZQ_CTL1 0x1038 // DDR Calibration Control Register 1 -#define REG_DMC_DDR_ZQ_CTL2 0x103C // DDR Calibration Control Register 2 -#define REG_DMC_DDR_CA_CTL 0x1068 // DDR CA Lane Control Register -/* END */ - -#define REG_DMC_DDR_SCRATCH_2 0x1074 -#define REG_DMC_DDR_SCRATCH_3 0x1078 -#define REG_DMC_DDR_SCRATCH_6 0x1084 -#define REG_DMC_DDR_SCRATCH_7 0x1088 - -#define REG_DMC_DDR_SCRATCH_STAT0 0x107C -#define REG_DMC_DDR_SCRATCH_STAT1 0x1080 - -#define DMC0_DATA_CALIB_ADD 0x80000000 -#define DMC1_DATA_CALIB_ADD 0xC0000000 - -#define BITM_DMC_CFG_EXTBANK 0x0000F000 /* External Banks */ -#define ENUM_DMC_CFG_EXTBANK1 0x00000000 /* EXTBANK: 1 External Bank */ -#define BITM_DMC_CFG_SDRSIZE 0x00000F00 /* SDRAM Size */ -#define ENUM_DMC_CFG_SDRSIZE64 0x00000000 /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */ -#define ENUM_DMC_CFG_SDRSIZE128 0x00000100 /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */ -#define ENUM_DMC_CFG_SDRSIZE256 0x00000200 /* SDRSIZE: 256M Bit SDRAM */ -#define ENUM_DMC_CFG_SDRSIZE512 0x00000300 /* SDRSIZE: 512M Bit SDRAM */ -#define ENUM_DMC_CFG_SDRSIZE1G 0x00000400 /* SDRSIZE: 1G Bit SDRAM */ -#define ENUM_DMC_CFG_SDRSIZE2G 0x00000500 /* SDRSIZE: 2G Bit SDRAM */ -#define ENUM_DMC_CFG_SDRSIZE4G 0x00000600 /* SDRSIZE: 4G Bit SDRAM */ -#define ENUM_DMC_CFG_SDRSIZE8G 0x00000700 /* SDRSIZE: 8G Bit SDRAM */ -#define BITM_DMC_CFG_SDRWID 0x000000F0 /* SDRAM Width */ -#define ENUM_DMC_CFG_SDRWID16 0x00000020 /* SDRWID: 16-Bit Wide SDRAM */ -#define BITM_DMC_CFG_IFWID 0x0000000F /* Interface Width */ -#define ENUM_DMC_CFG_IFWID16 0x00000002 /* IFWID: 16-Bit Wide Interface */ - -#define BITM_DMC_CTL_DDR3EN 0x00000001 -#define BITM_DMC_CTL_INIT 0x00000004 -#define BITP_DMC_STAT_INITDONE 2 /* Initialization Done */ -#define BITM_DMC_STAT_INITDONE 0x00000004 - -#define BITP_DMC_CTL_AL_EN 27 -#define BITP_DMC_CTL_ZQCL 25 /* ZQ Calibration Long */ -#define BITP_DMC_CTL_ZQCS 24 /* ZQ Calibration Short */ -#define BITP_DMC_CTL_DLLCAL 13 /* DLL Calibration Start */ -#define BITP_DMC_CTL_PPREF 12 /* Postpone Refresh */ -#define BITP_DMC_CTL_RDTOWR 9 /* Read-to-Write Cycle */ -#define BITP_DMC_CTL_ADDRMODE 8 /* Addressing (Page/Bank) Mode */ -#define BITP_DMC_CTL_RESET 7 /* Reset SDRAM */ -#define BITP_DMC_CTL_PREC 6 /* Precharge */ -#define BITP_DMC_CTL_DPDREQ 5 /* Deep Power Down Request */ -#define BITP_DMC_CTL_PDREQ 4 /* Power Down Request */ -#define BITP_DMC_CTL_SRREQ 3 /* Self Refresh Request */ -#define BITP_DMC_CTL_INIT 2 /* Initialize DRAM Start */ -#define BITP_DMC_CTL_LPDDR 1 /* Low Power DDR Mode */ -#define BITP_DMC_CTL_DDR3EN 0 /* DDR3 Mode */ - -#ifdef CONFIG_TARGET_SC584_EZKIT - #define DMC_PADCTL2_VALUE 0x0078283C -#elif CONFIG_TARGET_SC573_EZKIT - #define DMC_PADCTL2_VALUE 0x00782828 -#elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT - #define DMC_PADCTL2_VALUE 0x00783C3C -#elif defined(CONFIG_SC57X) || defined(CONFIG_SC58X) - #error "PADCTL2 not specified for custom board!" -#else - //Newer DMC. Legacy calibration obsolete - #define DMC_PADCTL2_VALUE 0x0 -#endif - -#define DMC_CPHYCTL_VALUE 0x0000001A - -#define BITP_DMC_MR1_QOFF 12 /* Output Buffer Enable */ -#define BITP_DMC_MR1_TDQS 11 /* Termination Data Strobe */ -#define BITP_DMC_MR1_RTT2 9 /* Rtt_nom */ -#define BITP_DMC_MR1_WL 7 /* Write Leveling Enable. */ -#define BITP_DMC_MR1_RTT1 6 /* Rtt_nom */ -#define BITP_DMC_MR1_DIC1 5 /* Output Driver Impedance Control */ -#define BITP_DMC_MR1_AL 3 /* Additive Latency */ -#define BITP_DMC_MR1_RTT0 2 /* Rtt_nom */ -#define BITP_DMC_MR1_DIC0 1 /* Output Driver Impedance control */ -#define BITP_DMC_MR1_DLLEN 0 /* DLL Enable */ - -#define BITP_DMC_MR2_CWL 3 /* CAS write Latency */ - -#define BITP_DMC_TR0_TMRD 28 /* Timing Mode Register Delay */ -#define BITP_DMC_TR0_TRC 20 /* Timing Row Cycle */ -#define BITP_DMC_TR0_TRAS 12 /* Timing Row Active Time */ -#define BITP_DMC_TR0_TRP 8 /* Timing RAS Precharge. */ -#define BITP_DMC_TR0_TWTR 4 /* Timing Write to Read */ -#define BITP_DMC_TR0_TRCD 0 /* Timing RAS to CAS Delay */ - -#define BITP_DMC_TR1_TRRD 28 /* Timing Read-Read Delay */ -#define BITP_DMC_TR1_TRFC 16 /* Timing Refresh-to-Command */ -#define BITP_DMC_TR1_TREF 0 /* Timing Refresh Interval */ - -#define BITP_DMC_TR2_TCKE 20 /* Timing Clock Enable */ -#define BITP_DMC_TR2_TXP 16 /* Timing Exit Powerdown */ -#define BITP_DMC_TR2_TWR 12 /* Timing Write Recovery */ -#define BITP_DMC_TR2_TRTP 8 /* Timing Read-to-Precharge */ -#define BITP_DMC_TR2_TFAW 0 /* Timing Four-Activated-Window */ - -#define BITP_DMC_MR_PD 12 /* Active Powerdown Mode */ -#define BITP_DMC_MR_WRRECOV 9 /* Write Recovery */ -#define BITP_DMC_MR_DLLRST 8 /* DLL Reset */ -#define BITP_DMC_MR_CL 4 /* CAS Latency */ -#define BITP_DMC_MR_CL0 2 /* CAS Latency */ -#define BITP_DMC_MR_BLEN 0 /* Burst Length */ - -#define BITP_DMC_DLLCTL_DATACYC 8 /* Data Cycles */ -#define BITP_DMC_DLLCTL_DLLCALRDCNT 0 /* DLL Calibration RD Count */ - -#define BITM_DMC_DLLCTL_DATACYC 0x00000F00 /* Data Cycles */ -#define BITM_DMC_DLLCTL_DLLCALRDCNT 0x000000FF /* DLL Calib RD Count */ - -#define BITP_DMC_STAT_PHYRDPHASE 20 /* PHY Read Phase */ - -#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ -#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT 0x08000000 /* Rst Data Pads */ -#define BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ -#define BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE 0x00000002 /* Compute Dcycle */ -#define BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ -#define BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL 0x00000100 /* Rst Lane DLL */ -#define BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE 10 /* Pipeline offset for PHYC_DATACYCLE */ -#define BITM_DMC_DDR_ROOT_CTL_SW_REFRESH 0x00002000 /* Refresh Lane DLL Code */ -#define BITM_DMC_DDR_CA_CTL_SW_REFRESH 0x00004000 /* Refresh Lane DLL Code */ - -#define BITP_DMC_CTL_RL_DQS 26 /* RL_DQS */ -#define BITM_DMC_CTL_RL_DQS 0x04000000 /* RL_DQS */ -#define BITP_DMC_EMR3_MPR 2 /* Multi Purpose Read Enable (Read Leveling)*/ -#define BITM_DMC_EMR3_MPR 0x00000004 /* Multi Purpose Read Enable (Read Leveling)*/ -#define BITM_DMC_MR1_WL 0x00000080 /* Write Leveling Enable.*/ -#define BITM_DMC_STAT_PHYRDPHASE 0x00F00000 /* PHY Read Phase */ - -#define BITP_DMC_DDR_LANE0_CTL1_BYPCODE 10 -#define BITM_DMC_DDR_LANE0_CTL1_BYPCODE 0x00007C00 -#define BITP_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 15 -#define BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN 0x00008000 - -#define DMC_ZQCTL0_VALUE 0x00785A64 -#define DMC_ZQCTL1_VALUE 0 -#define DMC_ZQCTL2_VALUE 0x70000000 - -#define DMC_TRIG_CALIB 0 -#define DMC_OFSTDCYCLE 2 - -#define BITP_DMC_CAL_PADCTL0_RTTCALEN 31 /* RTT Calibration Enable */ -#define BITP_DMC_CAL_PADCTL0_PDCALEN 30 /* PULLDOWN Calib Enable */ -#define BITP_DMC_CAL_PADCTL0_PUCALEN 29 /* PULLUP Calib Enable */ -#define BITP_DMC_CAL_PADCTL0_CALSTRT 28 /* Start New Calib ( Hardware Cleared) */ -#define BITM_DMC_CAL_PADCTL0_RTTCALEN 0x80000000 /* RTT Calibration Enable */ -#define BITM_DMC_CAL_PADCTL0_PDCALEN 0x40000000 /* PULLDOWN Calib Enable */ -#define BITM_DMC_CAL_PADCTL0_PUCALEN 0x20000000 /* PULLUP Calib Enable */ -#define BITM_DMC_CAL_PADCTL0_CALSTRT 0x10000000 /* Start New Calib ( Hardware Cleared) */ -#define ENUM_DMC_PHY_CTL4_DDR3 0x00000000 /* DDRMODE: DDR3 Mode */ -#define ENUM_DMC_PHY_CTL4_DDR2 0x00000001 /* DDRMODE: DDR2 Mode */ -#define ENUM_DMC_PHY_CTL4_LPDDR 0x00000003 /* DDRMODE: LPDDR Mode */ - -#define BITP_DMC_DDR_ZQ_CTL0_IMPRTT 16 /* Data/DQS ODT */ -#define BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ 8 /* Data/DQS/DM/CLK Drive Strength */ -#define BITP_DMC_DDR_ZQ_CTL0_IMPWRADD 0 /* Address/Command Drive Strength */ -#define BITM_DMC_DDR_ZQ_CTL0_IMPRTT 0x00FF0000 /* Data/DQS ODT */ -#define BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ 0x0000FF00 /* Data/DQS/DM/CLK Drive Strength */ -#define BITM_DMC_DDR_ZQ_CTL0_IMPWRADD 0x000000FF /* Address/Command Drive Strength */ - -#define BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL 0x00200000 /* All Lane Read Status */ - -#if defined(CONFIG_ADI_USE_DDR2) - #define DMC_MR0_VALUE \ - ((DMC_BL / 4 + 1) << BITP_DMC_MR_BLEN) | \ - (DMC_CL << BITP_DMC_MR_CL) | \ - (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) - - #define DMC_MR1_VALUE \ - (DMC_MR1_AL << BITP_DMC_MR1_AL | 0x04) \ - - #define DMC_MR2_VALUE 0 - #define DMC_MR3_VALUE 0 - - #define DMC_CTL_VALUE \ - (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ - (1 << BITP_DMC_CTL_DLLCAL) | \ - (BITM_DMC_CTL_INIT) -#else - #define DMC_MR0_VALUE \ - (0 << BITP_DMC_MR_BLEN) | \ - (DMC_CL0 << BITP_DMC_MR_CL0) | \ - (DMC_CL123 << BITP_DMC_MR_CL) | \ - (DMC_WRRECOV << BITP_DMC_MR_WRRECOV) | \ - (1 << BITP_DMC_MR_DLLRST) - - #define DMC_MR1_VALUE \ - (DMC_MR1_DLLEN << BITP_DMC_MR1_DLLEN) | \ - (DMC_MR1_DIC0 << BITP_DMC_MR1_DIC0) | \ - (DMC_MR1_RTT0 << BITP_DMC_MR1_RTT0) | \ - (DMC_MR1_AL << BITP_DMC_MR1_AL) | \ - (DMC_MR1_DIC1 << BITP_DMC_MR1_DIC1) | \ - (DMC_MR1_RTT1 << BITP_DMC_MR1_RTT1) | \ - (DMC_MR1_RTT2 << BITP_DMC_MR1_RTT2) | \ - (DMC_MR1_WL << BITP_DMC_MR1_WL) | \ - (DMC_MR1_TDQS << BITP_DMC_MR1_TDQS) | \ - (DMC_MR1_QOFF << BITP_DMC_MR1_QOFF) - - #define DMC_MR2_VALUE \ - ((DMC_WL) << BITP_DMC_MR2_CWL) - - #define DMC_MR3_VALUE \ - ((DMC_WL) << BITP_DMC_MR2_CWL) - - #define DMC_CTL_VALUE \ - (DMC_RDTOWR << BITP_DMC_CTL_RDTOWR) | \ - (BITM_DMC_CTL_INIT) | \ - (BITM_DMC_CTL_DDR3EN) | \ - (DMC_CTL_AL_EN << BITP_DMC_CTL_AL_EN) -#endif - -#define DMC_DLLCTL_VALUE \ - (DMC_DATACYC << BITP_DMC_DLLCTL_DATACYC) | \ - (DMC_DLLCALRDCNT << BITP_DMC_DLLCTL_DLLCALRDCNT) - -#define DMC_CFG_VALUE \ - ENUM_DMC_CFG_IFWID16 | \ - ENUM_DMC_CFG_SDRWID16 | \ - SDR_CHIP_SIZE | \ - ENUM_DMC_CFG_EXTBANK1 - -#define DMC_TR0_VALUE \ - (DMC_TRCD << BITP_DMC_TR0_TRCD) | \ - (DMC_TWTR << BITP_DMC_TR0_TWTR) | \ - (DMC_TRP << BITP_DMC_TR0_TRP) | \ - (DMC_TRAS << BITP_DMC_TR0_TRAS) | \ - (DMC_TRC << BITP_DMC_TR0_TRC) | \ - (DMC_TMRD << BITP_DMC_TR0_TMRD) - -#define DMC_TR1_VALUE \ - (DMC_TREF << BITP_DMC_TR1_TREF) | \ - (DMC_TRFC << BITP_DMC_TR1_TRFC) | \ - (DMC_TRRD << BITP_DMC_TR1_TRRD) - -#define DMC_TR2_VALUE \ - (DMC_TFAW << BITP_DMC_TR2_TFAW) | \ - (DMC_TRTP << BITP_DMC_TR2_TRTP) | \ - (DMC_TWR << BITP_DMC_TR2_TWR) | \ - (DMC_TXP << BITP_DMC_TR2_TXP) | \ - (DMC_TCKE << BITP_DMC_TR2_TCKE) - -enum DDR_MODE { - DDR3_MODE, - DDR2_MODE, - LPDDR_MODE, -}; - -enum CALIBRATION_MODE { - CALIBRATION_LEGACY, - CALIBRATION_METHOD1, - CALIBRATION_METHOD2, -}; - -static struct dmc_param { - phys_addr_t reg; - u32 ddr_mode; - u32 padctl2_value; - u32 dmc_cphyctl_value; - u32 dmc_cfg_value; - u32 dmc_dllctl_value; - u32 dmc_ctl_value; - u32 dmc_tr0_value; - u32 dmc_tr1_value; - u32 dmc_tr2_value; - u32 dmc_mr0_value; - u32 dmc_mr1_value; - u32 dmc_mr2_value; - u32 dmc_mr3_value; - u32 dmc_zqctl0_value; - u32 dmc_zqctl1_value; - u32 dmc_zqctl2_value; - u32 dmc_data_calib_add_value; - bool phy_init_required; - bool anomaly_20000037_applicable; - enum CALIBRATION_MODE calib_mode; -} dmc; - -#ifdef CONFIG_SC59X_64 -#define DQS_DEFAULT_DELAY 3ul - -#define DELAYTRIM 1 -#define LANE0_DQS_DELAY 1 -#define LANE1_DQS_DELAY 1 - -#define CLKDIR 0ul - -#define DQSTRIM 0 -#define DQSCODE 0ul - -#define CLKTRIM 0 -#define CLKCODE 0ul -#endif - -static inline void calibration_legacy(void) -{ - u32 temp; - - /* 1. Set DDR mode to DDR3/DDR2/LPDDR in DMCx_PHY_CTL4 register */ - if (dmc.ddr_mode == DDR3_MODE) - writel(ENUM_DMC_PHY_CTL4_DDR3, dmc.reg + REG_DMC_PHY_CTL4); - else if (dmc.ddr_mode == DDR2_MODE) - writel(ENUM_DMC_PHY_CTL4_DDR2, dmc.reg + REG_DMC_PHY_CTL4); - else if (dmc.ddr_mode == LPDDR_MODE) - writel(ENUM_DMC_PHY_CTL4_LPDDR, dmc.reg + REG_DMC_PHY_CTL4); - - /* - * 2. Make sure that the bits 6, 7, 25, and 27 of the DMC_PHY_ - * CTL3 register are set - */ - writel(0x0A0000C0, dmc.reg + REG_DMC_PHY_CTL3); - - /* - * 3. For DDR2/DDR3 mode, make sure that the bits 0, 1, 2, 3 of - * the DMC_PHY_CTL0 register and the bits 26, 27, 28, 29, 30, 31 - * of the DMC_PHY_CTL2 are set. - */ - if (dmc.ddr_mode == DDR3_MODE || - dmc.ddr_mode == DDR2_MODE) { - writel(0XFC000000, dmc.reg + REG_DMC_PHY_CTL2); - writel(0x0000000f, dmc.reg + REG_DMC_PHY_CTL0); - } - - writel(0x00000000, dmc.reg + REG_DMC_PHY_CTL1); - - /* 4. For DDR3 mode, set bit 1 and configure bits [5:2] of the - * DMC_CPHY_CTL register with WL=CWL+AL in DCLK cycles. - */ - if (dmc.ddr_mode == DDR3_MODE) - writel(dmc.dmc_cphyctl_value, dmc.reg + REG_DMC_CPHY_CTL); - /* 5. Perform On Die Termination(ODT) & Driver Impedance Calibration */ - if (dmc.ddr_mode == LPDDR_MODE) { - /* Bypass processor ODT */ - writel(0x80000, dmc.reg + REG_DMC_PHY_CTL1); - } else { - /* Set bits RTTCALEN, PDCALEN, PUCALEN of register */ - temp = BITM_DMC_CAL_PADCTL0_RTTCALEN | - BITM_DMC_CAL_PADCTL0_PDCALEN | - BITM_DMC_CAL_PADCTL0_PUCALEN; - writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); - /* Configure ODT and drive impedance values in the - * DMCx_CAL_PADCTL2 register - */ - writel(dmc.padctl2_value, dmc.reg + REG_DMC_CAL_PADCTL2); - /* start calibration */ - temp |= BITM_DMC_CAL_PADCTL0_CALSTRT; - writel(temp, dmc.reg + REG_DMC_CAL_PADCTL0); - /* Wait for PAD calibration to complete - 300 DCLK cycle. - * Worst case: CCLK=450 MHz, DCLK=125 MHz - */ - dmcdelay(300); - } -} - -static inline void calibration_method1(void) -{ -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_ZQ_CTL0); - writel(dmc.dmc_zqctl1_value, dmc.reg + REG_DMC_DDR_ZQ_CTL1); - writel(dmc.dmc_zqctl2_value, dmc.reg + REG_DMC_DDR_ZQ_CTL2); - - /* Generate the trigger */ - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x00010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(8000u); - - /* The [31:26] bits may change if pad ring changes */ - writel(0x0C000001ul | DMC_TRIG_CALIB, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(8000u); - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); -#endif -} - -static inline void calibration_method2(void) -{ -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - u32 stat_value = 0x0u; - u32 drv_pu, drv_pd, odt_pu, odt_pd; - u32 ro_dt, clk_dqs_drv_impedance; - u32 temp; - - /* Reset trigger */ - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - - /* Writing internal registers in calib pad to zero. Calib mode set - * to 1 [26], trig M1 S1 write [16], this enables usage of scratch - * registers instead of ZQCTL registers - */ - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - - /* TRIGGER FOR M2-S2 WRITE -> slave id 31:26 trig m2,s2 write - * bit 1->1 slave1 address is 4 - */ - writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - - /* reset Trigger */ - writel(0x0u, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - - /* write to slave 1, make the power down bit high */ - writel(0x1ul << 12, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - dmcdelay(2500u); - - /* Calib mode set to 1 [26], trig M1 S1 write [16] */ - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - - writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x0, dmc.reg + REG_DMC_DDR_SCRATCH_3); - - /* for slave 0 */ - writel(dmc.dmc_zqctl0_value, dmc.reg + REG_DMC_DDR_SCRATCH_2); - - /* Calib mode set to 1 [26], trig M1 S1 write [16] */ - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - - writel(0x0C000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - - /* writing to slave 1 - * calstrt is 0, but other programming is done - * - * make power down LOW again, to kickstart BIAS circuit - */ - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x30000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - - /* write to ca_ctl lane, calib mode set to 1 [26], - * trig M1 S1 write [16] - */ - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - - /* copies data to lane controller slave - * TRIGGER FOR M2-S2 WRITE -> slave id 31:26 - * trig m2,s2 write bit 1->1 - * slave1 address is 4 - */ - writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - - /* reset Trigger */ - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - writel(0x0ul, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(0x0ul, dmc.reg + REG_DMC_DDR_SCRATCH_3); - writel(0x50000000ul, dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(0x04010000ul, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x10000002ul, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x0C000004u, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - writel(BITM_DMC_DDR_ROOT_CTL_TRIG_RD_XFER_ALL, - dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - // calculate ODT PU and PD values - stat_value = ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_7) & 0x0000FFFFu) << - 16); - stat_value |= ((readl(dmc.reg + REG_DMC_DDR_SCRATCH_6) & 0xFFFF0000u) >> - 16); - clk_dqs_drv_impedance = ((dmc.dmc_zqctl0_value) & - BITM_DMC_DDR_ZQ_CTL0_IMPWRDQ) >> BITP_DMC_DDR_ZQ_CTL0_IMPWRDQ; - ro_dt = ((dmc.dmc_zqctl0_value) & BITM_DMC_DDR_ZQ_CTL0_IMPRTT) >> - BITP_DMC_DDR_ZQ_CTL0_IMPRTT; - drv_pu = stat_value & 0x0000003Fu; - drv_pd = (stat_value >> 12) & 0x0000003Fu; - odt_pu = (drv_pu * clk_dqs_drv_impedance) / ro_dt; - odt_pd = (drv_pd * clk_dqs_drv_impedance) / ro_dt; - temp = ((1uL << 24) | - ((drv_pd & 0x0000003Fu)) | - ((odt_pd & 0x0000003Fu) << 6) | - ((drv_pu & 0x0000003Fu) << 12) | - ((odt_pu & 0x0000003Fu) << 18)); - temp |= readl(dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(temp, dmc.reg + REG_DMC_DDR_SCRATCH_2); - writel(0x0C010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x08000002u, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - writel(0x04010000u, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x80000002u, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(2500u); - writel(0u, dmc.reg + REG_DMC_DDR_CA_CTL); - writel(0u, dmc.reg + REG_DMC_DDR_ROOT_CTL); -#endif -} - -static inline void adi_dmc_lane_reset(bool reset, uint32_t dmc_no) -{ -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - u32 temp; - phys_addr_t base = (dmc_no == 0) ? REG_DMC0_BASE : REG_DMC1_BASE; - phys_addr_t ln0 = base + REG_DMC_DDR_LANE0_CTL0; - phys_addr_t ln1 = base + REG_DMC_DDR_LANE1_CTL0; - - if (reset) { - temp = readl(ln0); - temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; - writel(temp, ln0); - - temp = readl(ln1); - temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; - writel(temp, ln1); - } else { - temp = readl(ln0); - temp &= ~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDLL; - writel(temp, ln0); - - temp = readl(ln1); - temp &= ~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDLL; - writel(temp, ln1); - } - dmcdelay(9000u); -#endif -} - -void adi_dmc_reset_lanes(bool reset) -{ - if (!IS_ENABLED(CONFIG_ADI_USE_DDR2)) { - if (IS_ENABLED(CONFIG_SC59X) || IS_ENABLED(CONFIG_SC59X_64)) { - if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) - adi_dmc_lane_reset(reset, 0); - if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) - adi_dmc_lane_reset(reset, 1); - } - else { - u32 temp = reset ? 0x800 : 0x0; - - if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) - writel(temp, REG_DMC0_BASE + REG_DMC_PHY_CTL0); - if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) - writel(temp, REG_DMC1_BASE + REG_DMC_PHY_CTL0); - } - } -} - -static inline void dmc_controller_init(void) -{ -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - u32 phyphase, rd_cnt, t_EMR1, t_EMR3, t_CTL, data_cyc, temp; -#endif - - /* 1. Program the DMC controller registers: DMCx_CFG, DMCx_TR0, - * DMCx_TR1, DMCx_TR2, DMCx_MR(DDR2/LPDDR)/DMCx_MR0(DDR3), - * DMCx_EMR1(DDR2)/DMCx_MR1(DDR3), - * DMCx_EMR2(DDR2)/DMCx_EMR(LPDDR)/DMCx_MR2(DDR3) - */ - writel(dmc.dmc_cfg_value, dmc.reg + REG_DMC_CFG); - writel(dmc.dmc_tr0_value, dmc.reg + REG_DMC_TR0); - writel(dmc.dmc_tr1_value, dmc.reg + REG_DMC_TR1); - writel(dmc.dmc_tr2_value, dmc.reg + REG_DMC_TR2); - writel(dmc.dmc_mr0_value, dmc.reg + REG_DMC_MR); - writel(dmc.dmc_mr1_value, dmc.reg + REG_DMC_EMR1); - writel(dmc.dmc_mr2_value, dmc.reg + REG_DMC_EMR2); - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - writel(dmc.dmc_mr3_value, dmc.reg + REG_DMC_EMR3); - writel(dmc.dmc_dllctl_value, dmc.reg + REG_DMC_DLLCTL); - dmcdelay(2000u); - - temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); - temp |= BITM_DMC_DDR_CA_CTL_SW_REFRESH; - writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); - dmcdelay(5u); - - temp = readl(dmc.reg + REG_DMC_DDR_ROOT_CTL); - temp |= BITM_DMC_DDR_ROOT_CTL_SW_REFRESH | - (DMC_OFSTDCYCLE << BITP_DMC_DDR_ROOT_CTL_PIPE_OFSTDCYCLE); - writel(temp, dmc.reg + REG_DMC_DDR_ROOT_CTL); -#endif - - /* 2. Make sure that the REG_DMC_DT_CALIB_ADDR register is programmed - * to an unused DMC location corresponding to a burst of 16 bytes - * (by default it is the starting address of the DMC address range). - */ -#ifndef CONFIG_SC59X - writel(dmc.dmc_data_calib_add_value, dmc.reg + REG_DMC_DT_CALIB_ADDR); -#endif - /* 3. Program the DMCx_CTL register with INIT bit set to start - * the DMC initialization sequence - */ - writel(dmc.dmc_ctl_value, dmc.reg + REG_DMC_CTL); - /* 4. Wait for the DMC initialization to complete by polling - * DMCx_STAT.INITDONE bit. - */ - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - dmcdelay(722000u); - - /* Add necessary delay depending on the configuration */ - t_EMR1 = (dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL; - - dmcdelay(600u); - if (t_EMR1 != 0u) - while ((readl(dmc.reg + REG_DMC_EMR1) & BITM_DMC_MR1_WL) != 0) - ; - - t_EMR3 = (dmc.dmc_mr3_value & BITM_DMC_EMR3_MPR) >> - BITP_DMC_EMR3_MPR; - dmcdelay(2000u); - if (t_EMR3 != 0u) - while ((readl(dmc.reg + REG_DMC_EMR3) & BITM_DMC_EMR3_MPR) != 0) - ; - - t_CTL = (dmc.dmc_ctl_value & BITM_DMC_CTL_RL_DQS) >> BITP_DMC_CTL_RL_DQS; - dmcdelay(600u); - if (t_CTL != 0u) - while ((readl(dmc.reg + REG_DMC_CTL) & BITM_DMC_CTL_RL_DQS) != 0) - ; -#endif - - /* check if DMC initialization finished*/ - while ((readl(dmc.reg + REG_DMC_STAT) & BITM_DMC_STAT_INITDONE) == 0) - ; - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - /* toggle DCYCLE */ - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); - temp |= BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE; - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); - temp |= BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE; - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - - dmcdelay(10u); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); - temp &= (~BITM_DMC_DDR_LANE0_CTL1_COMP_DCYCLE); - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); - temp &= (~BITM_DMC_DDR_LANE1_CTL1_COMP_DCYCLE); - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - - /* toggle RSTDAT */ - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); - temp |= BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT; - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); - temp &= (~BITM_DMC_DDR_LANE0_CTL0_CB_RSTDAT); - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); - temp |= BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT; - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); - temp &= (~BITM_DMC_DDR_LANE1_CTL0_CB_RSTDAT); - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); - - dmcdelay(2500u); - - /* Program phyphase*/ - phyphase = (readl(dmc.reg + REG_DMC_STAT) & - BITM_DMC_STAT_PHYRDPHASE) >> BITP_DMC_STAT_PHYRDPHASE; - data_cyc = (phyphase << BITP_DMC_DLLCTL_DATACYC) & - BITM_DMC_DLLCTL_DATACYC; - rd_cnt = dmc.dmc_dllctl_value; - rd_cnt <<= BITP_DMC_DLLCTL_DLLCALRDCNT; - rd_cnt &= BITM_DMC_DLLCTL_DLLCALRDCNT; - writel(rd_cnt | data_cyc, dmc.reg + REG_DMC_DLLCTL); - writel((dmc.dmc_ctl_value & (~BITM_DMC_CTL_INIT) & - (~BITM_DMC_CTL_RL_DQS)), dmc.reg + REG_DMC_CTL); - -#if DELAYTRIM - /* DQS delay trim*/ - u32 stat_value, WL_code_LDQS, WL_code_UDQS; - - /* For LDQS */ - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1) | (0x000000D0); - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - dmcdelay(2500u); - writel(0x00400000, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); - stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT0) & - (0xFFFF0000)) >> 16; - WL_code_LDQS = (stat_value) & (0x0000001F); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); - temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - - /* If write leveling is enabled */ - if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); - temp |= (((WL_code_LDQS + LANE0_DQS_DELAY) << - BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & - BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - } else { - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL1); - temp |= (((DQS_DEFAULT_DELAY + LANE0_DQS_DELAY) << - BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & - BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL1); - } - dmcdelay(2500u); - - /* For UDQS */ - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1) | (0x000000D0); - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - dmcdelay(2500u); - writel(0x00800000, dmc.reg + REG_DMC_DDR_ROOT_CTL); - dmcdelay(2500u); - writel(0x0, dmc.reg + REG_DMC_DDR_ROOT_CTL); - stat_value = (readl(dmc.reg + REG_DMC_DDR_SCRATCH_STAT1) & - (0xFFFF0000)) >> 16; - WL_code_UDQS = (stat_value) & (0x0000001F); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); - temp &= ~(BITM_DMC_DDR_LANE0_CTL1_BYPCODE | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN); - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - - /* If write leveling is enabled */ - if ((dmc.dmc_mr1_value & BITM_DMC_MR1_WL) >> BITP_DMC_MR1_WL) { - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); - temp |= (((WL_code_UDQS + LANE1_DQS_DELAY) << - BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & - BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - } else { - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL1); - temp |= (((DQS_DEFAULT_DELAY + LANE1_DQS_DELAY) << - BITP_DMC_DDR_LANE0_CTL1_BYPCODE) & - BITM_DMC_DDR_LANE0_CTL1_BYPCODE) | - BITM_DMC_DDR_LANE0_CTL1_BYPDELCHAINEN; - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL1); - } - dmcdelay(2500u); -#endif - -#else - /* 5. Program the DMCx_CTL.DLLCTL register with 0x948 value - * (DATACYC=9, DLLCALRDCNT=72). - */ - writel(0x00000948, dmc.reg + REG_DMC_DLLCTL); -#endif - - /* 6. Workaround for anomaly#20000037 */ - if (dmc.anomaly_20000037_applicable) { - /* Perform dummy read to any DMC location */ - readl(0x80000000); - - writel(readl(dmc.reg + REG_DMC_PHY_CTL0) | 0x1000, - dmc.reg + REG_DMC_PHY_CTL0); - /* Clear DMCx_PHY_CTL0.RESETDAT bit */ - writel(readl(dmc.reg + REG_DMC_PHY_CTL0) & (~0x1000), - dmc.reg + REG_DMC_PHY_CTL0); - } -} - -static inline void dmc_init(void) -{ - /* PHY Calibration+Initialization */ - if (!dmc.phy_init_required) - goto out; - - switch (dmc.calib_mode) { - case CALIBRATION_LEGACY: - calibration_legacy(); - break; - case CALIBRATION_METHOD1: - calibration_method1(); - break; - case CALIBRATION_METHOD2: - calibration_method2(); - break; - } - -#if DQSTRIM - /* DQS duty trim */ - temp = readl(dmc.reg + REG_DMC_DDR_LANE0_CTL0); - temp |= ((DQSCODE) << BITP_DMC_DDR_LANE0_CTL0_BYPENB) & - (BITM_DMC_DDR_LANE1_CTL0_BYPENB | - BITM_DMC_DDR_LANE0_CTL0_BYPSELP | - BITM_DMC_DDR_LANE0_CTL0_BYPCODE); - writel(temp, dmc.reg + REG_DMC_DDR_LANE0_CTL0); - - temp = readl(dmc.reg + REG_DMC_DDR_LANE1_CTL0); - temp |= ((DQSCODE) << BITP_DMC_DDR_LANE1_CTL0_BYPENB) & - (BITM_DMC_DDR_LANE1_CTL1_BYPCODE | - BITM_DMC_DDR_LANE1_CTL0_BYPSELP | - BITM_DMC_DDR_LANE1_CTL0_BYPCODE); - writel(temp, dmc.reg + REG_DMC_DDR_LANE1_CTL0); -#endif - -#if CLKTRIM - /* Clock duty trim */ - temp = readl(dmc.reg + REG_DMC_DDR_CA_CTL); - temp |= (((CLKCODE << BITP_DMC_DDR_CA_CTL_BYPCODE1) & - BITM_DMC_DDR_CA_CTL_BYPCODE1) | - BITM_DMC_DDR_CA_CTL_BYPENB | - ((CLKDIR << BITP_DMC_DDR_CA_CTL_BYPSELP) & - BITM_DMC_DDR_CA_CTL_BYPSELP)); - writel(temp, dmc.reg + REG_DMC_DDR_CA_CTL); -#endif - -out: - /* Controller Initialization */ - dmc_controller_init(); -} - -static inline void __dmc_config(uint32_t dmc_no) -{ - if (dmc_no == 0) { - dmc.reg = REG_DMC0_BASE; - dmc.dmc_data_calib_add_value = DMC0_DATA_CALIB_ADD; - } else if (dmc_no == 1) { - dmc.reg = REG_DMC1_BASE; - dmc.dmc_data_calib_add_value = DMC1_DATA_CALIB_ADD; - } else { - return; - } - - if (IS_ENABLED(CONFIG_ADI_USE_DDR2)) - dmc.ddr_mode = DDR2_MODE; - else - dmc.ddr_mode = DDR3_MODE; - - dmc.phy_init_required = true; - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - dmc.anomaly_20000037_applicable = false; - dmc.dmc_dllctl_value = DMC_DLLCTL_VALUE; - dmc.calib_mode = CALIBRATION_METHOD2; -#else - dmc.anomaly_20000037_applicable = true; - dmc.calib_mode = CALIBRATION_LEGACY; -#endif - - dmc.dmc_ctl_value = DMC_CTL_VALUE; - dmc.dmc_cfg_value = DMC_CFG_VALUE; - dmc.dmc_tr0_value = DMC_TR0_VALUE; - dmc.dmc_tr1_value = DMC_TR1_VALUE; - dmc.dmc_tr2_value = DMC_TR2_VALUE; - dmc.dmc_mr0_value = DMC_MR0_VALUE; - dmc.dmc_mr1_value = DMC_MR1_VALUE; - dmc.dmc_mr2_value = DMC_MR2_VALUE; - -#if defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - dmc.dmc_mr3_value = DMC_MR3_VALUE; - dmc.dmc_zqctl0_value = DMC_ZQCTL0_VALUE; - dmc.dmc_zqctl1_value = DMC_ZQCTL1_VALUE; - dmc.dmc_zqctl2_value = DMC_ZQCTL2_VALUE; -#endif - - dmc.padctl2_value = DMC_PADCTL2_VALUE; - dmc.dmc_cphyctl_value = DMC_CPHYCTL_VALUE; - - /* Initialize DMC now */ - dmc_init(); -} - -void DMC_Config(void) -{ - if (IS_ENABLED(CONFIG_ADI_USE_DMC0)) - __dmc_config(0); - - if (IS_ENABLED(CONFIG_ADI_USE_DMC1)) - __dmc_config(1); -} diff --git a/arch/arm/mach-sc5xx/init/dmcinit.h b/arch/arm/mach-sc5xx/init/dmcinit.h deleted file mode 100644 index 46ff729282dbdf4b6d62844066bfa44d36b0ffc9..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/dmcinit.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef DMCINIT_H_ -#define DMCINIT_H_ - -#include - -#ifdef MEM_MT41K512M16HA - #include "mem/mt41k512m16ha.h" -#elif defined(MEM_MT41K128M16JT) - #include "mem/mt41k128m16jt.h" -#elif defined(MEM_MT47H128M16RT) - #include "mem/mt47h128m16rt.h" -#elif defined(MEM_IS43TR16512BL) - #include "mem/is43tr16512bl.h" -#else - #error "No DDR part name is defined for this board." -#endif - -void DMC_Config(void); -void adi_dmc_reset_lanes(bool reset); - -#endif diff --git a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h b/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h deleted file mode 100644 index a5838370555097b65517f18bcc0266a1a0e4cb1e..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/mem/is43tr16512bl.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef IS43TR16512BL_H -#define IS43TR16512BL_H - -/* DMC0 setup for the EV-21593-SOM and EV-SC594-SOM : - * - uses a single 8GB IS43TR16512BL-125KBL DDR3 chip configured for - * 800 MHz DCLK. - * DMC0 setup for the EV-SC594-SOMS : - * - uses a single 4GB IS43TR16256BL-093NBL DDR3 chip configured for - * 800 MHz DCLK. - */ -#define DMC_DLLCALRDCNT 240 -#define DMC_DATACYC 12 -#define DMC_TRCD 11 -#define DMC_TWTR 6 -#define DMC_TRP 11 -#define DMC_TRAS 28 -#define DMC_TRC 39 -#define DMC_TMRD 4 -#define DMC_TREF 6240 -#define DMC_TRRD 6 -#define DMC_TFAW 32 -#define DMC_TRTP 6 -#define DMC_TWR 12 -#define DMC_TXP 5 -#define DMC_TCKE 4 -#define DMC_CL0 0 -#define DMC_CL123 7 -#define DMC_WRRECOV 6 -#define DMC_MR1_DLLEN 0 -#define DMC_MR1_DIC0 0 -#define DMC_MR1_RTT0 0 -#define DMC_MR1_AL 0 -#define DMC_MR1_DIC1 0 -#define DMC_MR1_RTT1 1 -#define DMC_MR1_WL 0 -#define DMC_MR1_RTT2 0 -#define DMC_MR1_TDQS 0 -#define DMC_MR1_QOFF 0 -#define DMC_WL 3 -#define DMC_RDTOWR 5 -#define DMC_CTL_AL_EN 1 -#if defined(MEM_ISSI_4Gb_DDR3_800MHZ) - #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE4G) - #define DMC_TRFC 208ul -#elif defined(MEM_ISSI_8Gb_DDR3_800MHZ) - #define SDR_CHIP_SIZE (ENUM_DMC_CFG_SDRSIZE8G) - #define DMC_TRFC 280ul -#else - #error "Need to select MEM_ISSI_4Gb_DDR3_800MHZ or MEM_ISSI_8Gb_DDR3_800MHZ" -#endif - -#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h b/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h deleted file mode 100644 index 882777521b87542a672159dc04429dfc79115806..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/mem/mt41k128m16jt.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef MT41K128M16JT_H -#define MT41K128M16JT_H - -/* Default DDR3 part assumed: MT41K128M16JT-125, 2Gb part */ -/* For DCLK= 450 MHz */ -#define DMC_DLLCALRDCNT 72 -#define DMC_DATACYC 9 -#define DMC_TRCD 6 -#define DMC_TWTR 4 -#define DMC_TRP 6 -#define DMC_TRAS 17 -#define DMC_TRC 23 -#define DMC_TMRD 4 -#define DMC_TREF 3510 -#define DMC_TRFC 72 -#define DMC_TRRD 4 -#define DMC_TFAW 17 -#define DMC_TRTP 4 -#define DMC_TWR 7 -#define DMC_TXP 4 -#define DMC_TCKE 3 -#define DMC_CL0 0 -#define DMC_CL123 3 -#define DMC_WRRECOV (DMC_TWR - 1) -#define DMC_MR1_DLLEN 0 -#define DMC_MR1_DIC0 1 -#define DMC_MR1_RTT0 1 -#define DMC_MR1_AL 0 -#define DMC_MR1_DIC1 0 -#define DMC_MR1_RTT1 0 -#define DMC_MR1_WL 0 -#define DMC_MR1_RTT2 0 -#define DMC_MR1_TDQS 0 -#define DMC_MR1_QOFF 0 -#define DMC_WL 1 -#define DMC_RDTOWR 2 -#define DMC_CTL_AL_EN 0 -#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G - -#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h b/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h deleted file mode 100644 index 5735b87871c4668a19d25af15fd5aad94fdef005..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/mem/mt41k512m16ha.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef MT41K512M16HA_H -#define MT41K512M16HA_H - -/* Default DDR3 part assumed: MT41K512M16HA-107, 8Gb part */ -/* For DCLK= 450 MHz */ -#define DMC_DLLCALRDCNT 72 -#define DMC_DATACYC 9 -#define DMC_TRCD 7 -#define DMC_TWTR 4 -#define DMC_TRP 7 -#define DMC_TRAS 10 -#define DMC_TRC 16 -#define DMC_TMRD 4 -#define DMC_TREF 3510 -#define DMC_TRFC 158 -#define DMC_TRRD 6 -#define DMC_TFAW 16 -#define DMC_TRTP 4 -#define DMC_TWR 7 -#define DMC_TXP 3 -#define DMC_TCKE 3 -#define DMC_CL0 0 -#define DMC_CL123 3 -#define DMC_WRRECOV (DMC_TWR - 1) -#define DMC_MR1_DLLEN 0 -#define DMC_MR1_DIC0 1 -#define DMC_MR1_RTT0 1 -#define DMC_MR1_AL 0 -#define DMC_MR1_DIC1 0 -#define DMC_MR1_RTT1 0 -#define DMC_MR1_WL 0 -#define DMC_MR1_RTT2 0 -#define DMC_MR1_TDQS 0 -#define DMC_MR1_QOFF 0 -#define DMC_WL 1 -#define DMC_RDTOWR 2 -#define DMC_CTL_AL_EN 0 -#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE8G - -#endif diff --git a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h b/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h deleted file mode 100644 index 5ada7f2985b89ee5544fd65082ecb9a5e8a72558..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/init/mem/mt47h128m16rt.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#ifndef MT47H128M16RT_H -#define MT47H128M16RT_H - -/* Default DDR2 part: MT47H128M16RT-25E XIT:C, 2 Gb part */ -/* For DCLK= 400 MHz */ -#define DMC_DLLCALRDCNT 72 -#define DMC_DATACYC 9 -#define DMC_TRCD 5 -#define DMC_TWTR 3 -#define DMC_TRP 5 -#define DMC_TRAS 16 -#define DMC_TRC 22 -#define DMC_TMRD 2 -#define DMC_TREF 3120 -#define DMC_TRFC 78 -#define DMC_TRRD 4 -#define DMC_TFAW 18 -#define DMC_TRTP 3 -#define DMC_TWR 6 -#define DMC_TXP 2 -#define DMC_TCKE 3 -#define DMC_CL 5 -#define DMC_WRRECOV (DMC_TWR - 1) -#define DMC_MR1_DLLEN 0 -#define DMC_MR1_DIC0 1 -#define DMC_MR1_RTT0 1 -#define DMC_MR1_AL 4 -#define DMC_MR1_DIC1 0 -#define DMC_MR1_RTT1 0 -#define DMC_MR1_WL 0 -#define DMC_MR1_RTT2 0 -#define DMC_MR1_TDQS 0 -#define DMC_MR1_QOFF 0 -#define DMC_BL 4 -#define DMC_RDTOWR 2 -#define DMC_CTL_AL_EN 0 -#define SDR_CHIP_SIZE ENUM_DMC_CFG_SDRSIZE2G - -#endif diff --git a/arch/arm/mach-sc5xx/rcu.c b/arch/arm/mach-sc5xx/rcu.c deleted file mode 100644 index 49357501a93b045d22efba06c5ccd136729efeab..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/rcu.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Ian Roberts - */ - -#include -#include - -static const struct udevice_id adi_syscon_ids[] = { - { .compatible = "adi,reset-controller" }, - { } -}; - -U_BOOT_DRIVER(syscon_sc5xx_rcu) = { - .name = "sc5xx_rcu", - .id = UCLASS_SYSCON, - .of_match = adi_syscon_ids, -}; diff --git a/arch/arm/mach-sc5xx/sc57x.c b/arch/arm/mach-sc5xx/sc57x.c deleted file mode 100644 index b0587686d73f1cc54e34f4401a98be9134a1fb62..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/sc57x.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include - -#define REG_SPU0_SECUREC0 0x3108B980 -#define REG_PADS0_PCFG0 0x31004404 -#define REG_SPU0_SECUREP_START 0x3108BA00 -#define REG_SPU0_SECUREP_END 0x3108BD24 - -adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; - -void sc5xx_enable_rgmii(void) -{ - writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); -} - -void sc5xx_soc_init(void) -{ - sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); - sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); - sc5xx_enable_pmu(); -} diff --git a/arch/arm/mach-sc5xx/sc58x.c b/arch/arm/mach-sc5xx/sc58x.c deleted file mode 100644 index 0f892774309730b5ebf22c037cb8d7d0f49f53a6..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/sc58x.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include - -#define REG_SPU0_SECUREC0 0x3108C980 -#define REG_PADS0_PCFG0 0x31004404 -#define REG_SPU0_SECUREP_START 0x3108CA00 -#define REG_SPU0_SECUREP_END 0x3108CCF0 - -adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e1; - -void sc5xx_enable_rgmii(void) -{ - writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); -} - -void sc5xx_soc_init(void) -{ - sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); - sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); - sc5xx_enable_pmu(); -} diff --git a/arch/arm/mach-sc5xx/sc59x.c b/arch/arm/mach-sc5xx/sc59x.c deleted file mode 100644 index 174c6f5c4456aea62e191392ec60261571d65182..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/sc59x.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include - -#define REG_SPU0_SECUREC0 0x3108B980 -#define REG_PADS0_PCFG0 0x31004604 -#define REG_SPU0_SECUREP_START 0x3108BA00 -#define REG_SPU0_SECUREP_END 0x3108BD24 - -#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 -#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 -#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 - -adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e9; - -void sc5xx_enable_rgmii(void) -{ - writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); -} - -void sc59x_remap_ospi(void) -{ - clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, - BITM_SCB5_SPI2_OSPI_REMAP_REMAP, - ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); -} - -void sc5xx_soc_init(void) -{ - sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); - sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_END); - sc5xx_enable_pmu(); -} diff --git a/arch/arm/mach-sc5xx/sc59x_64.c b/arch/arm/mach-sc5xx/sc59x_64.c deleted file mode 100644 index 82537bf1965ef4755e34f6dab5a3a940f135a8c8..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/sc59x_64.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2024 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include - -#define REG_TSGENWR0_CNTCR 0x310AE000 -#define REG_PADS0_PCFG0 0x31004604 -#define REG_RCU0_BCODE 0x3108C028 - -#define REG_SPU0_SECUREP_START 0x3108BA00 -#define REG_SPU0_WP_START 0x3108B400 -#define REG_SPU0_SECUREC0 0x3108B980 - -#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 -#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 -#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 - -adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4; - -void sc5xx_enable_rgmii(void) -{ - writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); - - // Set dw for little endian operation as well - writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0); - writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0); -} - -void sc59x_remap_ospi(void) -{ - clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, - BITM_SCB5_SPI2_OSPI_REMAP_REMAP, - ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); -} - -/** - * SPU/SMPU configuration is the default for permissive access from non-secure - * EL1. If TFA and OPTEE are configured, they run *after* this code, as the - * current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will - * be expected to configure peripheral security correctly. If they are not - * configured, then this permissive setting will allow Linux (which always - * runs in NS EL1) to control all access to these peripherals. Without it, - * the peripherals would simply be unavailable in a non-security build, - * which is not OK. - */ -void sc5xx_soc_init(void) -{ - phys_addr_t smpus[] = { - 0x31007800, //SMPU0 - 0x31083800, //SMPU2 - 0x31084800, //SMPU3 - 0x31085800, //SMPU4 - 0x31086800, //SMPU5 - 0x31087800, //SMPU6 - 0x310A0800, //SMPU9 - 0x310A1800, //SMPU11 - 0x31012800, //SMPU12 - }; - size_t i; - - // Enable coresight timer - writel(1, REG_TSGENWR0_CNTCR); - - //Do not rerun preboot routine -- - // Without this, hardware resets triggered by RCU0_CTL:SYSRST - // lead to a deadlock somewhere in the boot ROM - writel(0x200, REG_RCU0_BCODE); - - /* Alter outstanding transactions property of A55*/ - writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */ - isb(); - - /* configure DDR prefetch behavior, per ADI */ - writel(0x1, 0x31076000); - - /* configure smart mode, per ADI */ - writel(0x1307, 0x31076004); - - // Disable SPU and SPU WP registers - sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213); - sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213); - - /* configure smpus permissively */ - for (i = 0; i < ARRAY_SIZE(smpus); ++i) - writel(0x500, smpus[i]); - - sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); -} diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c deleted file mode 100644 index 8f13127a6603d7bed4e9bc5240bcd4a9e85f0228..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/soc.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SC58X - #define RCU0_CTL 0x3108B000 - #define RCU0_STAT 0x3108B004 - #define RCU0_CRCTL 0x3108B008 - #define RCU0_CRSTAT 0x3108B00C - #define RCU0_SIDIS 0x3108B010 - #define RCU0_MSG_SET 0x3108B064 -#elif defined(CONFIG_SC57X) || defined(CONFIG_SC59X) || defined(CONFIG_SC59X_64) - #define RCU0_CTL 0x3108C000 - #define RCU0_STAT 0x3108C004 - #define RCU0_CRCTL 0x3108C008 - #define RCU0_CRSTAT 0x3108C00C - #define RCU0_SIDIS 0x3108C01C - #define RCU0_MSG_SET 0x3108C070 -#else - #error "No SC5xx SoC CONFIG_ enabled" -#endif - -#define BITP_RCU_STAT_BMODE 8 -#define BITM_RCU_STAT_BMODE 0x00000F00 - -#define REG_ARMPMU0_PMCR 0x31121E04 -#define REG_ARMPMU0_PMUSERENR 0x31121E08 -#define REG_ARMPMU0_PMLAR 0x31121FB0 - -DECLARE_GLOBAL_DATA_PTR; - -void reset_cpu(void) -{ - u32 val = readl(RCU0_CTL); - writel(val | 1, RCU0_CTL); -} - -void enable_caches(void) -{ - if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) - dcache_enable(); -} - -void sc5xx_enable_ns_sharc_access(uintptr_t securec0_base) -{ - writel(0, securec0_base); - writel(0, securec0_base + 0x4); - writel(0, securec0_base + 0x8); -} - -void sc5xx_disable_spu0(uintptr_t spu0_start, uintptr_t spu0_end) -{ - for (uintptr_t i = spu0_start; i <= spu0_end; i += 4) - writel(0, i); -} - -/** - * PMU is only available on armv7 platforms and all share the same location - */ -void sc5xx_enable_pmu(void) -{ - if (!IS_ENABLED(CONFIG_SC59X_64)) { - writel(readl(REG_ARMPMU0_PMUSERENR) | 0x01, REG_ARMPMU0_PMUSERENR); - writel(0xc5acce55, REG_ARMPMU0_PMLAR); - writel(readl(REG_ARMPMU0_PMCR) | (1 << 1), REG_ARMPMU0_PMCR); - } -} - -const char *sc5xx_get_boot_mode(u32 *bmode) -{ - static const char * const bmodes[] = { - "JTAG/BOOTROM", - "QSPI Master", - "QSPI Slave", - "UART", - "LP0 Slave", - "OSPI", -#ifdef CONFIG_SC59X_64 - "eMMC" -#endif - }; - u32 local_mode; - - local_mode = (readl(RCU0_STAT) & BITM_RCU_STAT_BMODE) >> BITP_RCU_STAT_BMODE; - -#if CONFIG_ADI_SPL_FORCE_BMODE != 0 - /* - * In case we want to force boot sequences such as: - * QSPI -> OSPI - * QSPI -> eMMC - * If this is not set, then we will always try to use the BMODE setting - * for both stages... i.e. - * QSPI -> QSPI - */ - - // (Don't allow skipping JTAG/UART BMODE settings) - if (local_mode != 0 && local_mode != 3) - local_mode = CONFIG_ADI_SPL_FORCE_BMODE; -#endif - - *bmode = local_mode; - - if (local_mode >= 0 && local_mode <= ARRAY_SIZE(bmodes)) - return bmodes[local_mode]; - return "unknown"; -} - -void print_cpu_id(void) -{ - if (!IS_ENABLED(CONFIG_ARM64)) { - u32 cpuid = 0; - - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid)); - - printf("Detected Revision: %d.%d\n", cpuid & 0xf00000 >> 20, cpuid & 0xf); - } -} - -int print_cpuinfo(void) -{ - u32 bmode; - - printf("CPU: ADSP %s (%s boot)\n", CONFIG_LDR_CPU, sc5xx_get_boot_mode(&bmode)); - print_cpu_id(); - - return 0; -} - -void fixup_dp83867_phy(struct phy_device *phydev) -{ - int phy_data = 0; - - phy_data = phy_read(phydev, MDIO_DEVAD_NONE, 0x32); - phy_write(phydev, MDIO_DEVAD_NONE, 0x32, (1 << 7) | phy_data); - int cfg3 = 0; - #define MII_DP83867_CFG3 (0x1e) - /* - * Pin INT/PWDN on DP83867 should be configured as an Interrupt Output - * instead of a Power-Down Input on ADI SC5XX boards in order to - * prevent the signal interference from other peripherals during they - * are running at the same time. - */ - cfg3 = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3); - cfg3 |= (1 << 7); - phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG3, cfg3); - - // Mystery second port fixup on ezkits with two PHYs - if (CONFIG_DW_PORTS & 2) - phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 3); - - if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) { - phydev->advertising &= PHY_BASIC_FEATURES; - phydev->speed = SPEED_100; - } - - if (phydev->drv->config) - phydev->drv->config(phydev); - - if (IS_ENABLED(CONFIG_ADI_BUG_EZKHW21)) - phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100); -} - -int dram_init(void) -{ - gd->ram_size = CFG_SYS_SDRAM_SIZE; - return 0; -} diff --git a/arch/arm/mach-sc5xx/spl.c b/arch/arm/mach-sc5xx/spl.c deleted file mode 100644 index 68e0310f5af53dcdf9f053b7d75dd4afe3ce148a..0000000000000000000000000000000000000000 --- a/arch/arm/mach-sc5xx/spl.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - */ - -#include -#include -#include -#include "init/clkinit.h" -#include "init/dmcinit.h" - -static bool adi_start_uboot_proper; - -static int adi_sf_default_bus = CONFIG_SF_DEFAULT_BUS; -static int adi_sf_default_cs = CONFIG_SF_DEFAULT_CS; -static int adi_sf_default_speed = CONFIG_SF_DEFAULT_SPEED; - -u32 bmode; - -int spl_start_uboot(void) -{ - return adi_start_uboot_proper; -} - -unsigned int spl_spi_get_default_speed(void) -{ - return adi_sf_default_speed; -} - -unsigned int spl_spi_get_default_bus(void) -{ - return adi_sf_default_bus; -} - -unsigned int spl_spi_get_default_cs(void) -{ - return adi_sf_default_cs; -} - -void board_boot_order(u32 *spl_boot_list) -{ - const char *bmodestring = sc5xx_get_boot_mode(&bmode); - - printf("ADI Boot Mode: 0x%x (%s)\n", bmode, bmodestring); - - /* - * By default everything goes back to the bootrom, where we'll read table - * parameters and ask for another image to be loaded - */ - spl_boot_list[0] = BOOT_DEVICE_BOOTROM; - - if (bmode == 0) { - printf("SPL execution has completed. Please load U-Boot Proper via JTAG"); - while (1) - ; - } -} - -int32_t __weak adi_rom_boot_hook(struct ADI_ROM_BOOT_CONFIG *config, int32_t cause) -{ - return 0; -} - -int board_return_to_bootrom(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev) -{ -#if CONFIG_ADI_SPL_FORCE_BMODE != 0 - // see above - if (bmode != 0 && bmode != 3) - bmode = CONFIG_ADI_SPL_FORCE_BMODE; -#endif - - if (bmode >= (ARRAY_SIZE(adi_rom_boot_args))) - bmode = 0; - - adi_rom_boot((void *)adi_rom_boot_args[bmode].addr, - adi_rom_boot_args[bmode].flags, - 0, &adi_rom_boot_hook, - adi_rom_boot_args[bmode].cmd); - return 0; -}; - -void board_init_f(ulong dummy) -{ - int ret; - - clks_init(); - DMC_Config(); - sc5xx_soc_init(); - - ret = spl_early_init(); - if (ret) - panic("spl_early_init() failed\n"); - - preloader_console_init(); -} - diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 3d5994c87886768b4ce993734eace9a6ccd2cb36..b439a19ec7eb0b2ec17d5c209c6b58900c102f9c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -467,10 +467,12 @@ void enable_caches(void) gd->arch.tlb_addr = tlb_addr; gd->arch.tlb_size = tlb_size; - carveout_start = get_timer(0); - /* Takes ~20-50ms on SDM845 */ - carve_out_reserved_memory(); - debug("carveout time: %lums\n", get_timer(carveout_start)); - + /* We do the carveouts only for QCS404, for now. */ + if (fdt_node_check_compatible(gd->fdt_blob, 0, "qcom,qcs404") == 0) { + carveout_start = get_timer(0); + /* Takes ~20-50ms on SDM845 */ + carve_out_reserved_memory(); + debug("carveout time: %lums\n", get_timer(carveout_start)); + } dcache_enable(); } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index feaf5ce459642b1b703f78caf02b34685867ee55..616e1afe5de68365d4c45cd5257107fc18276376 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -5,7 +5,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 160f6e73ca9e3f97cc2b242cb3cc0619fcd4a208..9e645a425317fd9f28271f8ff16ffed7c3fb964f 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -3,6 +3,7 @@ * Copyright (C) 2013-2017 Altera Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 9987d5bcee6fab4f4ce102c8e748dbcfbb032278..28f593b60e63575d138b9490e482c6494c504776 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index 7ec28d91ef326222e880ea8920575c09cbe96ab4..b92f0b3af806b97689bbb3bd38ca35d2be8dcade 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58b9321131a90d4da4a4d5bb069fa2802bce2636..8ab18f6b725296eeff1dcac3adec5eee97f1d8e9 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -3,6 +3,7 @@ * Copyright (C) 2016-2017 Intel Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 154ad2154ae7e55d0db382b7307de19f2050b066..8fa2760798b8de48e76cead37e9729a3f61721b6 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -3,6 +3,7 @@ * Copyright (C) 2013-2017 Altera Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index c4c071330fc34857396b91aa1bd4d29895be1047..0ed480de670d36a4b89715c3719d1ee48b9f8452 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 1e148947a3385ff1b9ed3ab5ae4e3ac65c2cfa8d..45300336d52a0e3aedf1f88783acb15b438ea17b 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 4dec47b8e960d25d75244193f38a54dc186ed612..69229dc651e4ffe2e7913c66b3da22ade38ca9de 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -4,8 +4,8 @@ * */ -#include #include +#include #include #include diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c index c946d4c38d96e823ef744345d71b6a5a039ded9f..18d692c63144983d09a3e2085a7cee753177a849 100644 --- a/arch/arm/mach-socfpga/fpga_manager.c +++ b/arch/arm/mach-socfpga/fpga_manager.c @@ -7,7 +7,7 @@ * platform code, the real meat is located in drivers/fpga/socfpga.c . */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 7c86350d5eac68682f0a9198ec09e35d5b905669..561d3408cd8fdb3827cad12c78084c5f3b657c13 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -4,7 +4,7 @@ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 49f3fb2e705755c710eaf07fb75eb8ed33a5e15d..6c9d32b9dd8a6ac89198274b40db1c1179914f0a 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -6,8 +6,6 @@ #ifndef _CLOCK_MANAGER_H_ #define _CLOCK_MANAGER_H_ -#include - phys_addr_t socfpga_get_clkmgr_addr(void); #ifndef __ASSEMBLY__ diff --git a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h index 01335dc931087d484fabb7a5d1f168d000f04520..d5a11122c723b22b6d1b93833e494909f758f3b5 100644 --- a/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h +++ b/arch/arm/mach-socfpga/include/mach/secure_reg_helper.h @@ -7,8 +7,6 @@ #ifndef _SECURE_REG_HELPER_H_ #define _SECURE_REG_HELPER_H_ -#include - #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC 1 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 2 #define SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC1 3 diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4c86f1e99170c098eb4b5259a2e6a9e861a4b702..101af2385529c38c14b1376f2d95bd5b8f210366 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 495ba2a0d4184a5d5e950eac9caeac5a08524e69..80ad0870341b20550a7bdd54d71be94b30d9f791 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 34c21317894d805b7fd18efda4717927ab769009..93c9e8b0fb408d60cce4a9ae3df465e47b4ff9aa 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b898b6f8f2262e9364390afac5acef3d9578dedc..e7500c16f720985f62e05e576630366d392ded5a 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -3,7 +3,7 @@ * Copyright (C) 2012-2017 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index ad1ef0db1869af08ac1323ed37632664de26aa97..2acdfad07b35be6d583869b2e0587558596e04c5 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index b8e40d9a78893641d08997e2e7edb9a8f2263611..91c6d7c55f134be8c7dd35aeee635b2fbf45f376 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -4,6 +4,7 @@ * */ +#include #include #include diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c index c8074f47e7604c8adf0edb230e4b783d7911bdf9..f378fce7f02df2032c044489e64795f9e260d081 100644 --- a/arch/arm/mach-socfpga/pinmux_arria10.c +++ b/arch/arm/mach-socfpga/pinmux_arria10.c @@ -4,9 +4,9 @@ */ #include -#include #include #include +#include #include static int do_pinctr_pin(const void *blob, int child, const char *node_name) diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index da335f4292cb1071e1303657ad7fd7e379f86c9b..27c030801134e597efcc4bcab85d218f0fd17bce 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9395122dae13854b12ce1e4a7d9f43b86e31feae..a65860ef021a8b14f8d32a70234b5875bcc554de 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -4,7 +4,7 @@ */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index dd0383c7c76dd8634f8be18f975f6276a9f60b39..f47fec10a0c6b24d8b73addf0269b2bccaedcf94 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c index f8811525da4d33e94c8dafefc9292cb53169b99b..36d6880141eac34aa038c864da9bfd283662af1c 100644 --- a/arch/arm/mach-socfpga/scan_manager.c +++ b/arch/arm/mach-socfpga/scan_manager.c @@ -3,7 +3,7 @@ * Copyright (C) 2013 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/secure_reg_helper.c b/arch/arm/mach-socfpga/secure_reg_helper.c index 802a966ce87a1e0f4a6d7c2b723fca04b380506e..0d4f45f33da546bab114648568f43b402bd04825 100644 --- a/arch/arm/mach-socfpga/secure_reg_helper.c +++ b/arch/arm/mach-socfpga/secure_reg_helper.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index 4347bf6e79274be5e6755a3190917601630864aa..e2db588506436f11ff0f453029cd2b32b387c814 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa170061803ea32ff8a7174bba1fea470..8ffc7a472b5b9460ee35de117bb96aba0a579fcd 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -4,11 +4,10 @@ * */ +#include #include #include -#include #include -#include int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len) { diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c20376f7f8ef3029293cda16f57f09e6f9a9c628..3981d2d4f140779f4ed2f276290d2520c2edc3dd 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -3,13 +3,14 @@ * Copyright (C) 2012-2021 Altera Corporation */ -#include +#include #include #include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 52617a39ccaf96b1a655906f41b0083d597e9b3a..ee5a9dc1e2f5059c52ea254c655a37046dd5a0af 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -8,7 +8,9 @@ #include #include #include +#include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index df79cfe0f7fafd4e84f27a23a6b66054fcf8afc3..287fbd1713c63e44dd9b3a89e0aa95947afe075a 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -3,11 +3,13 @@ * Copyright (C) 2012 Altera Corporation */ +#include #include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 5ff137e5c6fb05754d03ec3cf79c1194040585ed..d056871d29244154db5f4a49f4e5afdd5560fd12 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 53852cb744391886dba962e7df197af408018d22..c20e87cdbef3b69ab9384c85d5fa43c64d218049 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -9,7 +9,9 @@ #include #include #include +#include #include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 4fe67ea081127044c4d21cb849e342a48f50f4d7..ba6efc1d86418bc09581a8515a36207059043f51 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -4,6 +4,7 @@ * */ +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c index c377d1c32c79eb43bc8af59d9610f4a20bbd64bb..09caebb3c882a4cdd0bea9457a9564b6a16e84df 100644 --- a/arch/arm/mach-socfpga/system_manager_gen5.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -3,6 +3,7 @@ * Copyright (C) 2013-2017 Altera Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 4b42158be9d9731eaa02939f33a4fc3961ec8b68..958bb5107b5b96fd17e3bdc2bdd2c37878552d78 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index 99de5744c48f42491d92bb92daa6a8e01cef5a9c..d9e8c84bfcfee74baff9e7193a8338a334380edd 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Altera Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 809335863190925048f854c84186f12201e77d9f..84b13ce9d3a93529ec20971a806758e086a7305d 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c index e74c71cfbb44110e2daeb1bee563bc7a7d2bfb0e..e146f2c52901671d009631f237b7d9c98d8dd25a 100644 --- a/arch/arm/mach-socfpga/vab.c +++ b/arch/arm/mach-socfpga/vab.c @@ -4,9 +4,9 @@ * */ -#include #include #include +#include #include static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 92051d19b737ad761c2da7b28f5835af05ae9f34..6aa9bb26b4ec1f3c41b74b02a5a042a822110f31 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -6,6 +6,7 @@ #include #include +#include #include #include "log.h" diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index 43ce329dd10fe2237b7cbae15ba343fcae334ec0..ce86f04cad1f5a9a82815ca06df2f9b717338c58 100644 --- a/arch/arm/mach-socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c index e494d2eb3f9fd2fed335dd316efec4be83b58629..33ca14c9dc766599539943d1e59609be7250ad75 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -3,9 +3,8 @@ * Copyright (C) 2015 Marek Vasut */ +#include #include -#include -#include /* Board-specific header. */ #include diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index e0d0f8f81b7cf180c736fbbdc1bbdc3e9e7d3621..0c40ae987613ac30af29e3b491e0349b6cefdc32 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include #include diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index f13581033e6bf28a0cdd4c9fc7d5e163d0e3475c..6a0d6b5ead72991ef9119c666040fcb9c33c059d 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 8f3fbaf80c8c61703d0226880821cc5811a2a42b..cd3a0f6633556c61384cffc1672999e983f2e122 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -3,10 +3,8 @@ * Copyright (C) 2015 Marek Vasut */ -#include +#include #include -#include -#include #include /* Board-specific header. */ diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 737e6809f8d310594eff0e90df045afc99bcebae..0bd8d7b22c4df6297477d52683d48f11857103d2 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c index ebddf6a7dbcc5f5c48a018127ae0e29b8d7f12e3..158bf40cb97e8fb688ab1523413a3b312ab936a0 100644 --- a/arch/arm/mach-stm32mp/boot_params.c +++ b/arch/arm/mach-stm32mp/boot_params.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 9ba7a6c9a892958280c23c0bd0fa2d853b54ebd9..5b869017ec1abd5823e90d2dea4784ff1c125c8d 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 0cb3c7a9fa440c07cc9cda12d21e61bf043d78cb..c7fe232f86e0cdff6faff1e20f1cccb9c56f8c3e 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -3,6 +3,7 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 967fa4e06c0e8ddf0f14f84199f407e97a8f0dca..adee6e05b636bd611af656353a506d9dd18ccfbd 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -3,6 +3,7 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 07c5e0456f824bf5f3b8ef5c795da50ef319056f..35bed3199422812b54bd53b329722d5d086fa775 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -3,12 +3,12 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c index 4b1ed50e9fe5d87503d8afb973470f47439fbb9b..d18455bf36f1d90f7b3a6ec014ff735eff7f2869 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -3,6 +3,7 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 78b12fcbb6acafdca7ead328f8eb671a52297843..fb1208fc5d570bb3e4676c308bf67f56c57f626f 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 478c3efae73e65317c8430ea735f1f68c742bbe9..524778f00c67d409017d3767cce57601f35ef119 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c index e1e4dc04e01cd18c2a318f2bafdcb9e7d34fc5ba..d0b6c3cc5a5595ba301c4c97e0045c848c994ffd 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -5,11 +5,11 @@ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 7772546b2fefbee2e7e55bce77ca7e012c363a10..4f2379df45fbfb8a4c2b8a6f15f80f6c2b2b0fd7 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include /* PWR */ #define PWR_CR3 0x0c diff --git a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c index 79c44188cc56363cd5d4602e8dd1a5b08d3e464f..846637ab162e3126063a54a61557156f7b2a6b13 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c @@ -5,10 +5,10 @@ #define LOG_CATEGORY UCLASS_REGULATOR +#include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 7a8fd3178adff04303d4d23781a9365f10c0b0e7..6c79259b2c82147fb94ea2b575beb34add1658cb 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 4a811065fc31655eb644f1076c90501973c63ee2..845d973ad1b2473341a769cb9f6e25bd525542e6 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH -#include +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index f096fe538d88d3472ef2a00f1e8822f1c9c2eb9d..d75ec99d6a17adfdf3746177176815bc17c3d05b 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index 8bcbd9793404b8860554acb15c67742397c069ae..a2e351d74a7aa1dde520d0814ce6fa16539eb670 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c index 3666dddca15c3844d58358f0920a4cd9196129d9..9077f86a8b4cffd59f4d87294306041d24608b3d 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -1,3 +1,4 @@ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c index ceaafd6ec6fac3e6ea1a0d1424eac2f462c01349..0471e8a49e586e87f53e26be38bd5e6421ea5ff7 100644 --- a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -1,3 +1,4 @@ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c index 3faf8d5bd9743cb58944370ddd4f5b1921bacdb0..232b4fe2df7f226d315e2f16148d9145a67aced3 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c @@ -11,6 +11,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c index ce2ffa7a020e9558f5eaf365baa20fcc3c7a9e37..b6d6a6874682da9d8340a7e0c1ee1fdd41cc8b70 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c @@ -11,6 +11,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index e6446b9180da4d54b0fc045bee9b67427d95971c..c11cb8678f64bf746b2245632674072f38b6bb52 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index afe8e25c7f58c9d4f49ec807bc3b04798bc3be58..2136ca3a4cb0107221ac074819001ee99e1fea35 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -19,6 +19,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c index c243b574406de13941851e29bd399ca5fce87298..10008601134ab47390d0135e4ab5fda85b5a09f9 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c index bc47a4638533c7e0658460d411f677a07ba980c6..bd57e2f6aac2907d5f94e2d2a751bdad1b233327 100644 --- a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c @@ -1,3 +1,4 @@ +#include #include #include diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 1ea620e4ab594634cce575ee1efa19994b43d5da..532730fe7270aba943f92cce32adf4137cee9e98 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -6,7 +6,7 @@ /* Tegra AP (Application Processor) code */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 4fbe47a91e1e24bd795fba2132aeb66d689ca242..ea4eac392d96fe3d633f26146db9d4c34a0e0db4 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -7,6 +7,7 @@ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index c382e0428603f6c6bc1134cc606de2b0c59dd8f6..327d70bd4cc081abfbba0d4e1f7514c069fc62f6 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 479137e457cb7f77eb1c98c6040626f7bdb992a3..adea12c9b7f9a3bc1cbf2e14ce10360b455a263d 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 462364abf03846f08aa79a54756dda60c1978f94..d7063490e222092e04e634df94e3edafe225ecad 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -5,6 +5,7 @@ /* Tegra cache routines */ +#include #include #include #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL) diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index c12543d71ac0a2ea81ac54d20eefe2ddfe800ecb..8f5bb2f261a9357aabf9dc581f67c70ccba5027f 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -3,6 +3,7 @@ * Copyright (c) 2016-2018, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 157e6c4911a4c35aad72c05fad36e56b9fdc6c96..575da2bdb5a2dc3c5a26273bf19ae7842ae31bbf 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -5,6 +5,7 @@ /* Tegra SoC common clock control functions */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 8fa1207e97a8adf17f7cea161895b19fa8d22542..92ff6cb1bf86d6ef4774f4487b5baa68a8b24986 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -24,6 +24,7 @@ * (C) Copyright 2004 Texas Insturments */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index 5f2a5917102406ddccf887460786f10d76190cfe..59ca8aeabac7ba720c9050052a5915ef1455379d 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/crypto.c b/arch/arm/mach-tegra/crypto.c index 49e6a45243adc55c2a2ae8d33b7e3c5327de6562..893da35e0b9dfcdc5cba70a7e0f5f37ec0f2b87a 100644 --- a/arch/arm/mach-tegra/crypto.c +++ b/arch/arm/mach-tegra/crypto.c @@ -4,6 +4,7 @@ * (C) Copyright 2010 - 2011 NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index f4ae602d523965fd2f5d47ea70bf18df69df8654..c11494722bc7aee5a8d9a2ed5a7376511f9232e3 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 83fad35d4dcc4879db9643b2b0250df04c1442e9..2eea14b5a744a1067f42d5c39d82b3de0bbd71a6 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include "emc.h" #include diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index e9b5259ac7010126469c07e06eed3aac1f1e7b9e..83bd505538411cb7c9ddc5b8739c8dc00b7f3654 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 23381759b79716e8e68ba4fe76550398a0dcd1ea..36538e7f96adc75a51638c413b121ac79c4e0194 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -5,6 +5,7 @@ /* Tegra vpr routines */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c index 0445d5d48e5cbe877589f8fc29e901e1399e5924..66c1276f4b876cbe90ec0c8e6b7176d5d711bf67 100644 --- a/arch/arm/mach-tegra/ivc.c +++ b/arch/arm/mach-tegra/ivc.c @@ -3,11 +3,11 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include #include -#include #include #define TEGRA_IVC_ALIGN 64 diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 3f968d4aeae862053dc4e7f26335ebbe1bbb9aa5..c4f5106750b80cc14ce501c2e4a0697e7b051ff2 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -3,6 +3,7 @@ * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 2a2f8467216e82bd943035bde642cdef6837b2eb..631bc04e95061d20b5075df7ab657092dfabaf43 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -3,8 +3,8 @@ * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. */ +#include #include -#include #include #include diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 5df0eb28c96f4a4a20fcf408707b3924586466bb..ed897efc5f07510683104786212ec4a4b040a8d2 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -5,6 +5,7 @@ * * Allen Martin */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c index 11b40480246620d88c8a0dd7e89b93227d0295f1..5ad586ac17fb079974c682a3e0a5dcda0c6a27a0 100644 --- a/arch/arm/mach-tegra/sys_info.c +++ b/arch/arm/mach-tegra/sys_info.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5cc8ac44dde9c780f6c258c13e4406f8ba543f4..2ee755bc649c69788cf6ac4253eabb6b598181c1 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -6,6 +6,7 @@ /* Tegra114 Clock control functions */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 3fe2d2d73246584b2a3777093b4ae6de96536641..7d8f080c310caf02ee3b688b0dc7f4c319b33f0a 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 4ac0c10c597d1d2a257a7ea7a655561964aacc92..ed8b6d963816a45369d1df288944e0d0805ee957 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -6,7 +6,7 @@ /* Tegra124 Clock control functions */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 07892aedd3cbfad645c676730368228d3c199b5d..b1bfe8fb5e139937f5ed9347a20de53d15302700 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/pmc.c b/arch/arm/mach-tegra/tegra124/pmc.c index 2294911501e799353b5948f50835f3bba30d81bb..3921ffb52af49b5835ecf64a46069c4ffe636944 100644 --- a/arch/arm/mach-tegra/tegra124/pmc.c +++ b/arch/arm/mach-tegra/tegra124/pmc.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Google, Inc */ +#include #include #include diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index a50b681935aa33384d358237dbdf12cb7a9663e2..ab102a6226115a3256059e9a12acbc7d2961331b 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -4,6 +4,7 @@ * Author: Jan Kiszka */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 1153444267d33d2730bf672dea9b2f0370f4146c..69736aa392553194b3a6b71d9fb341442e6a373c 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt +#include #include #include -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index e155b98cf65545b78ea383fa4422290df755ce57..b2c44f3d237c60614786305510f399f1fcf3c439 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -4,6 +4,7 @@ * Copyright (c) 2022, Svyatoslav Ryhel */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 6af20e9c782bb7dfd0b7c42f4dbdc1214c1c13ce..109b73bfbe7f14e6266736eb316ad1c8d2ce18b0 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -7,6 +7,7 @@ /* Tegra20 Clock control functions */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 1ba3930b5e6ed814626e72d79a020c3cebd64adf..e5b60598f7f7a383c67bc9e3884dc37387191259 100644 --- a/arch/arm/mach-tegra/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 207e50aac9053b70e662fb48143a553bb0438199..4ba3fb23fd63b64ba61b51dd32ad58cb6f8ea559 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index e2ee8f124ac799c533c2b92fe01eb462c4ccbecf..fb5e699c940dac395551b6600ddb74b2c7cb762f 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -3,7 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index f2fe5d0fa9dc09d5c3111c6da6202312265fea58..05d0668cdbaacc69ec72f8d809f6c8a62e3724ff 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -4,6 +4,7 @@ * (C) Copyright 2010,2011 NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 18034c83a1c216618555c04267b957c68ea30d9d..5e3a9ebaceb3ed6ef1d8d6d9cb787e057de59298 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 65bbe1825356998ceef9ba8eab98a7297d4460f2..94ce762e01f5886f1737583980eb9c9d53035ffa 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 57ff0b2a19afec2e2fc41086c78779c39b8c2481..74817e0440b8080ac747bda8c330c1e14a2bd0fa 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -6,10 +6,10 @@ /* Tegra210 Clock control functions */ +#include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index e409c2842e241a1f9b35337883bd6a1c67319780..30d0395bb0e58553a6885d8db7084702ff57503c 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -5,9 +5,9 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt +#include #include #include -#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index 250009ea8d8ec59097296ae0407806be444835ed..cff1a3e98d2746800114eef60ceaed504a7cbe3e 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -4,9 +4,9 @@ * Copyright (c) 2022, Svyatoslav Ryhel */ +#include #include #include -#include #include #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 7d61127920be9b2c18739d3d04d5ced7ef8c695e..0af8cde8c64db419199df67a0ab77feea298a1eb 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -6,6 +6,7 @@ /* Tegra30 Clock control functions */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 51a9deab1fdab485567376b2a9458f2d2d25ad3a..60bbf13ea5259837f19b13ceb6ffbf981702e93e 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index a3515d903a69525672a242117143a22a12014f45..28fdebe50a331c173cd6b7f196cb9aedd501a479 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt +#include #include #include #include diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 1345b80747e88b076589adac826ec82f4737ab76..f2d90302f6d2932beac4c839be5485e1272f0dbb 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -3,9 +3,9 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include -#include #include struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type) diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index 7541b567d0fd0fb0cbd3cf4721ec61d180188e09..05a91346a897310123534471bf9d4f70068c901b 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -3,7 +3,7 @@ * Copyright (C) 2019 Stephan Gerhold */ -#include +#include #include #include #include diff --git a/arch/arm/mach-u8500/cpuinfo.c b/arch/arm/mach-u8500/cpuinfo.c index 6d4c6196c3dfb18f3953fcae32c5cc244c01258e..ab05b8a51b239d26915d43d376986299731ae2fd 100644 --- a/arch/arm/mach-u8500/cpuinfo.c +++ b/arch/arm/mach-u8500/cpuinfo.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Stephan Gerhold */ +#include #include #include diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680ff116bb2496c2c080de826c0ac6b0..e6f1286e71fdf071b5cbd16fcf3a87bc389545b7 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "init.h" #include "sg-regs.h" diff --git a/arch/arm/mach-versal-net/clk.c b/arch/arm/mach-versal-net/clk.c index 61b8fe71b1aefaf26885038a12f2b82b4a9ece61..d097de7afa632d8aca5eed259fac921a299875c2 100644 --- a/arch/arm/mach-versal-net/clk.c +++ b/arch/arm/mach-versal-net/clk.c @@ -6,6 +6,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f638f7d9859cb2a48ba832745db71927..a82741e70fc88c65fc0cf740651917b0c5662511 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -6,6 +6,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c index 19943dfdd4ca6300d24445efff5a74cf7fb5e52a..5e3f44c77822f529d77e8dab8077048c0c1ec648 100644 --- a/arch/arm/mach-versal/clk.c +++ b/arch/arm/mach-versal/clk.c @@ -4,6 +4,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd1ce10ab2f12aaf3f9063141c975e8..e4dc305d92884d27a5504603df48036045771a80 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -4,6 +4,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 921ca49c3596e83371a636d7be3f7797f109b621..2487b482ddb15a6ce5d12622aada083eef13c600 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -4,8 +4,7 @@ * Siva Durga Prasad Paladugu */ -#include -#include +#include #include #include #include diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..858ca9414c05353bf84e2aee355e50379c4eec59 --- /dev/null +++ b/arch/arm/mach-versatile/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = timer.o +obj-y += reset.o diff --git a/arch/arm/mach-versatile/reset.S b/arch/arm/mach-versatile/reset.S new file mode 100644 index 0000000000000000000000000000000000000000..c7f1225fb298e895936eb8dc48e4a3d8f79c5f40 --- /dev/null +++ b/arch/arm/mach-versatile/reset.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + */ + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c new file mode 100644 index 0000000000000000000000000000000000000000..b471412186d19abf136cb0826427e9b314c841b7 --- /dev/null +++ b/arch/arm/mach-versatile/timer.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + */ + +#include + +#define TIMER_ENABLE (1 << 7) +#define TIMER_MODE_MSK (1 << 6) +#define TIMER_MODE_FR (0 << 6) +#define TIMER_MODE_PD (1 << 6) + +#define TIMER_INT_EN (1 << 5) +#define TIMER_PRS_MSK (3 << 2) +#define TIMER_PRS_8S (1 << 3) +#define TIMER_SIZE_MSK (1 << 2) +#define TIMER_ONE_SHT (1 << 0) + +int timer_init (void) +{ + ulong tmr_ctrl_val; + + /* 1st disable the Timer */ + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); + tmr_ctrl_val &= ~TIMER_ENABLE; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + + /* + * The Timer Control Register has one Undefined/Shouldn't Use Bit + * So we should do read/modify/write Operation + */ + + /* + * Timer Mode : Free Running + * Interrupt : Disabled + * Prescale : 8 Stage, Clk/256 + * Tmr Siz : 16 Bit Counter + * Tmr in Wrapping Mode + */ + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); + tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); + tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); + + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + + return 0; +} diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index c1b018cf22e92c000e712d6c720b53ab3fa8e991..5e1ba8d43ed1920bd2740fb080e0cd803edc9b69 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -4,6 +4,7 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ #include +#include #include #include #include diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index c75e453d57301b6fe4d97f93bac4b0c3d1be01aa..3b6518c71c90dcd46e31655715f99ee23856dc09 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -3,11 +3,10 @@ * Copyright (C) 2012 Michal Simek * Copyright (C) 2012 Xilinx, Inc. All rights reserved. */ -#include +#include #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index b9a2eef5a6f023ecc05b68e6b5f1abd13d863595..28988ef95b5ac3dca13d63ff86863407361f7d53 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -4,7 +4,7 @@ * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. */ -#include +#include #include #include #include diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index ef877df0fe85125dfc9ab399ccc67d2dd0e413a8..5d9f4d23f34bfd7496234d3087521367d7489407 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 - 2017 Xilinx Inc. */ +#include #include #include #include diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 8ef12ed65ceb40fc5fc2d7bd3f00b140ec89d8a9..fea1c9b12ad16c9b6c1385a9657d7580d7078f31 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index 9a912dd5bd7cd30fccf42b33878f5b3444b0c35b..0d368443d824a8427ae8d1ab7c9de43ac6b559d0 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c index 9a05fbf9c11b48c5cc6394305ee7ef92630f8fd0..8a2b7fdcbe9fe56daad72563fec843ec0a40d857 100644 --- a/arch/arm/mach-zynqmp/aes.c +++ b/arch/arm/mach-zynqmp/aes.c @@ -7,8 +7,9 @@ * Christian Taedcke */ +#include #include -#include + #include #include #include diff --git a/arch/arm/mach-zynqmp/clk.c b/arch/arm/mach-zynqmp/clk.c index 9b573b1746aa0001fad220ac4a9bdf172d849b7a..3b05f8455bf5deb33fa7f1984a8c89a0e8cec603 100644 --- a/arch/arm/mach-zynqmp/clk.c +++ b/arch/arm/mach-zynqmp/clk.c @@ -4,6 +4,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 07668c94689152c891c47a0674959a36e2542cd3..6ae27894ecd95972e1d245efdbb1f62b6ccabbd6 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -4,10 +4,9 @@ * Michal Simek */ +#include #include #include -#include -#include #include #include #include diff --git a/arch/arm/mach-zynqmp/ecc_spl_init.c b/arch/arm/mach-zynqmp/ecc_spl_init.c index 1eef1078951402c42f091400ddba83ae3e71cd7d..f547d8e3a5bfe076b6d72154fb83a9482bd850cc 100644 --- a/arch/arm/mach-zynqmp/ecc_spl_init.c +++ b/arch/arm/mach-zynqmp/ecc_spl_init.c @@ -5,6 +5,7 @@ * Jorge Ramirez-Ortiz */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index b007307e1f368e66eed0da7bebde6fb8b4701bc6..dce92438926e471f8a7dadb3e0702675ddd10f6c 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -5,6 +5,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h index 01a13d4c7c060e5bd1e7eec6b5a4cad115514192..2a9cffbd0f800619bae02822e2cd40fbae03c578 100644 --- a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h +++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h @@ -9,8 +9,6 @@ #ifndef ZYNQMP_AES_H #define ZYNQMP_AES_H -#include - struct zynqmp_aes { u64 srcaddr; u64 ivaddr; diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 9b46a25a1cbe970f1b6e01e2ab2f688549c59003..aff9054212c57bc67bee78d6d8bccdc0ff27704e 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -4,16 +4,14 @@ * Michal Simek */ -#include +#include #include #include -#include #include #include #include #include #include -#include #define LOCK 0 #define SPLIT 1 diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index 5b4d66359bfb6c01281cd3e50ce0b882be81ee2a..b4d7f44bbeee37f8ae1e04c2d8e415083b3c5b78 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -4,6 +4,7 @@ * * Michal Simek */ +#include #include #include #include diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 6b67245f348c5b7198fc8b7bbdaa47d751b7a455..979ff3aef6c28c4f1bde36f8e11312c07201fdca 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -5,6 +5,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 93efc722ba8a025ea684246859ee9922242eba33..c2ef5770a3dfdf924397894962be13e2a4bfa392 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -7,8 +7,6 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H -#include - /* Architecture-specific global data */ struct arch_global_data { #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index cf6ae5adddfdcf97e0432e555bc1bca00fc98797..3719f11c03c6d1a64cb470f407e391902c9481d5 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -8,6 +8,7 @@ #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 521776705786aef848a3ee31e5f1f94cc2a0cb91..cb224bd254236202ed31f57f1decc33516cab56f 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -10,6 +10,7 @@ #include #include #include +#include #include void board_boot_order(u32 *spl_boot_list) diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index bb4112f22a3c99a2b5fbaf5fe064d90637a34831..93506dec894e0dfb11ad47eec77eb6e3e96c46f9 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -9,7 +9,6 @@ #define __ASM_GBL_DATA_H #include -#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 147a95ecea8bb0f82ba2789bbdc35e1bc0fe2b5b..34b7e0bed945ef4267a6a53a763619c3ebade4c2 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -9,7 +9,6 @@ #include #include -#include struct octeon_eeprom_mac_addr { u8 mac_addr_base[6]; diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 89846c9723c7fca7094e0a8bbd421c483c6aea08..40469d1be0906794406fb09c2bb4f029c943d95b 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 3fcd0b8465b454f4a3ed4602b232458dfe581360..15b2792e619b01c09ffc6aa12a7c89d30a033c97 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -80,7 +80,6 @@ config SOC_MT7621 bool "MT7621" select MIPS_CM select MIPS_L2_CACHE - select MMC_SUPPORTS_TUNING select SYS_CACHE_SHIFT_5 select SYS_MIPS_CACHE_INIT_RAM_LOAD select PINCTRL_MT7621 diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 792fa01ab9e2d88578db1b933dd7a7de73d96687..de7bfa947f1135660ee9ad65d826a17cc4c92407 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -4,7 +4,7 @@ * Scott McNutt */ -#include +#include #include #include #include diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 27093c4faa3d8525147529150f9e5a55ed9326b3..90cabb67571b813d852af596f90fac4386427d66 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -7,6 +7,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/arch/nios2/cpu/traps.c b/arch/nios2/cpu/traps.c index 59690214f14e722af9888f9021d7952b8f2396d8..087a05097d9e6ffdbf67ae01f77e728542f14333 100644 --- a/arch/nios2/cpu/traps.c +++ b/arch/nios2/cpu/traps.c @@ -4,8 +4,8 @@ * Scott McNutt */ +#include #include -#include #include void trap_handler (struct pt_regs *regs) diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index d9bbd54734e508cfce400ac26dca9398f9d4bcbc..b56e8a5078e04d505e5b4ef5cd1c37385bfcfb40 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -7,7 +7,6 @@ #define __ASM_NIOS2_GLOBALDATA_H_ #include -#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index ce939ff5e15aa958e77f96554643b9cc8033956c..657a17c7204fa3863b5a4b3b3d4f8921465c97bd 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -4,6 +4,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c index 8f543f2a2f2664f227b5ba9ed99e0ff87af423c1..5864d8f0f4733453f6791a16c8e0cca5d5874217 100644 --- a/arch/nios2/lib/cache.c +++ b/arch/nios2/lib/cache.c @@ -5,6 +5,7 @@ * Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e0be938ea9825576baeb93848b1287b4203aab0d..f6ffe295b8ed8fee526493a34606c823208e317e 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -9,6 +9,7 @@ * Derived from the MPC8260 and MPC85xx. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 9ab5ea313d3a98a36c9919abc3e83fc4250d5c6f..3e24752e2f6c162c822eae7e4a10d528ba11798f 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -6,6 +6,7 @@ * based on the contribution of Marian Balakowicz */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 1bd4f2b3449dc9c6690c9d12b4dcb32ef7b7c9fd..33b2151f878c4ccc9b0c8b79f273f1c73d998007 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -6,6 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c index d86c981811e99870336fc8c723616fc772ce1270..f9486678af33bf2c36901adf619dbe2c0c627f58 100644 --- a/arch/powerpc/cpu/mpc83xx/interrupts.c +++ b/arch/powerpc/cpu/mpc83xx/interrupts.c @@ -6,6 +6,7 @@ * Copyright 2004 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index ae60be9e8774dfb48fef4455bba55dbe6a48c89d..5e02f4094bb11733e885f74a2e7b9b84f87d99b2 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -3,6 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 6f378c4e221ff7f6d22786d1c5b6701a6a2c8267..65ef0497c2a13a247347ae0b1288e54dc4d3871e 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -6,6 +6,7 @@ * with some bits from older board-specific PCI initialization. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index efa30c6833893088d2c8af045b9940fb6227cb07..47ca74c5c35686101bf6ec262b5f0a3960a4d746 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -7,6 +7,7 @@ * Anton Vorontsov */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 256dbfe8a4bb0b60b4909b55b8c8ddd23b9db7a9..52360703a7da2eeade3f2488f0535b86edfef10c 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -6,6 +6,7 @@ * based on source code of Shlomi Gridish */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index d3ca24422a597412c499c847341bfa0d4d38927b..d4848b2ec4d5d0d2cde00e0b92b3268dad3fe7c5 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e847c03f378b4135b2bd72fca720eeb2e0863998..6da8fc4381d1f8604f33fa95ee252fc9500cdb7c 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -12,6 +12,7 @@ #ifndef CONFIG_MPC83XX_SDRAM +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 72464962613f361864f36fb3012e2afc7a20a0a1..b7a87fec2f5b44867c1d409754e2a859af3f6e58 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -8,6 +8,7 @@ #ifndef CONFIG_CLK_MPC83XX +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 7036e3fae0c85ecf5ab8bdfb52826ff4868cd9fd..b55bfaffcaed086ad8d547eac513fe4c649f6429 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -3,7 +3,7 @@ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 79ea1a9bb3c907dd350d3ca2e2b5c579f6f0abf7..94e6323d73653980566d2978a01a0b4bafaa5c44 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -11,6 +11,7 @@ * exceptions */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index df2f0efe3eda71346f71b079ded7fcab1360c3e8..013a171ed87b04d7afea841a91f06d34c2c6e499 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -3,8 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 25fdb4b042110d55cdc8c16caf2b146ad4cd6456..8e18e12f634121b1bf833b25e5c6019e63075c84 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -3,6 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 9ebb3d838fa4e945c6f464f4102e4d1a67ceffde..7921334827402a1d8cb52b753d842b1895375ae5 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index bbe4a0dd62b0d7ff1f9644514ae2c13c99b58a78..e53dd43f31fe998308ea19a1e33927987565c0e8 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index f91a4d441d3aef6cbbe2f692502baea208688c18..c7d473d4a1b43dea063f7d0f4ba5f2dba75e0ed0 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6356b02163805ed916784fad12c39145e8ef0eb3..e8a3e82765fc6e7f817c9a0e1ad52ba1913fad5f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 574510fa0883955019e64d90700cbb0e3fccf2c9..a67f37e3af96eb23b5f9f9c693bbce6e369f2786 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -3,9 +3,8 @@ * Copyright 2009-2012 Freescale Semiconductor, Inc */ -#include +#include #include -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c56e98d4b49ed7602c5549c4dd42df58ce3055a0..e26436bf5701932cd232edeabb1f17a5cc687845 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 945020f7ecbe1e87c1860e47b26b207f79383167..9b6577e547e573e82850b517bbb40dd58aef5c66 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -3,6 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 78316ea5ffe24cfc06280064cdf2b2db7cf30b71..7c2de02c4c56b9d9b2907c2be56da88196aeb195 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -3,7 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index 3c98768f22ea87dbfaf29e78fc7e95d993b467c4..bcbdfac02792ba44a77951f343998a6c067ccfc9 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -10,7 +10,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index af6731cbb3a495c2c05af2dfcbdcc8bfbb980e70..4b8844a4d960b04d8cf40361e4a429a980b85815 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index b638f24ed14cc5b4f912e245f226d7bd460f9d80..7c47e415f05dd51e12310374b82c227504f18a69 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -3,7 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index bafff2083b35bca78e8871843027419f752be126..cbcb57fe3a5454ff8e3691f1b94d2aadb2221751 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index ad979caf6a7de243df10ee0e59b73b7f10df76ae..a48f3c15128584df7095852da26dc3e0b9e8190c 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 924afa096d181089a3b00d0a59085ae49130e6e8..479ee085d3abdb3e0ecfc898f065ce0151151177 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index d38041ef5c2ba9e7951978d5c0a2cae6f31cb83b..56e5ef6468c1f9c788408f567cd8554490a9b264 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index ec0f14ae6a74d81d7bb6c4cf4a4ad7f9ea24fac3..47f13e3c1cd788ceef22f7ea8af7734f8a97265e 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index 6d306d99c32d9ca9bd36041271fe13fc8e88d65b..7a8f653727efdc60f6d5b22c894d92ad428719fb 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 49626fc1d1b6c15471d5bd7166a85c518608c341..8c5d82ae8ade2a9261f82bcfe643016dd4dce649 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index ae5227a1eed183ff714beebd9d41b0bf1c21ed12..540a6e6e191fbeaa7a5bd4242ce2083e071537d6 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -3,8 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 3943859a518831212e4441f4d0dce80fa30b5167..3eca3a69326fe896249728ac6056a7f59150e268 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 0675a59414be19292e4de4b6c1d97a38ee0a730f..8f645258a5fc49ae3176db25d68a426fffd2ec8b 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -3,8 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c index b1586f110e86842f809a29777239523c1bb96702..ec8234c1c1e5fa3e23376402f4eb80212c0e2b03 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -3,6 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 15ab4ac93852d10e999ec17cd2b8f478508fe7c4..db411162022b0a5fb4faabb79a0fceaed1107e8f 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -3,8 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c index 438fd446be36b43aa8157a8e0327eda9105280a4..463fa119c9b8b642050348ec283d6b82f1cf3eca 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c @@ -3,6 +3,7 @@ * Copyright 2009-2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 0a34e066e94028503af8c1e0b92a1bb6468ca24b..bd05eae2551defe2659f69d4a1331754c9c4038a 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -3,8 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c index 409f2ac938d1f1e50cf9bae791373ed0f693e5e6..2327b2c2a414339d2adf43f068dd954c3ef2de2b 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -3,6 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 782874d79d7ccf836a2647ff2c85c84f15efe68f..6b4cbddcdfe15a403307c720c5c914195673d176 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -3,6 +3,7 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index c3f7493efc7e23cc0cec1a696bf2b08772f00e93..3cf41ca76d5bc0c279e3ba9ff7cf3791624c981c 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -6,7 +6,7 @@ * based on source code of Shlomi Gridish */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a7e1b3c98a9d358d55b1ee0d1bafd89949233844..9af40310b46fccfa726238c865aba49ef5efc2b3 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -9,6 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 29318fad5f0b0cda591db8779af2bbaf34b0ce3b..ce2b9c21667780d512d14c60fd07a2d01a9d475f 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -3,6 +3,7 @@ * Copyright 2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index 7239d28f9368898d554e8432072f66faa753178d..bab076b2b1809f2edc815c7522fb5a3dd00c1ccb 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -3,8 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 0d958fe131b51d53056986475e4dc76edc213c17..16458e73be13b1d93dc3fc68ce34cbc3324b5525 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index bb92fc392cc2dcb9e3aa11698e4180e67212ddc2..59f4f9c6692c3c4041554eca8b3375ee0a9bdee1 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -3,8 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 2033ebbaa5e65f59bea7500759449bb15629a913..3a7fdef79c2e9de87267fffcb64f47dc2b3af904 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -3,11 +3,10 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include -#include static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 26a2d745a864a0f266309e4b1197bed160ad5372..390bb1153758977831e6df9ee8fa4350a4384f03 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -3,8 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 6702acaf772390f4394c202f2d180a2d83998251..5f34aab4531e6c219ceb6144130ce76729983397 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -5,10 +5,9 @@ * Shengzhou Liu */ -#include +#include #include #include -#include #include "fsl_corenet2_serdes.h" struct serdes_config { diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index c319bf5cff57ca3eb641fd508bdae60f028b0bf0..37ea7788ccfc865ca20bb515eca7d607bcab32f9 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -3,8 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ -#include -#include +#include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 36fe34f11ecc8cf959343029207824123ad06e85..61402e84ef62823726eb11bdd8be06d79ada5a83 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -3,6 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e0b36f869a9cc68051c8686ef308a30b137c871f..2a78f0fe502cb8eedfd4b755e626095bb8d71b47 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index db70f07500c570fab1243899ebc3483bf945d4e5..8f451b486248466bef6981af366e950b79c7b25d 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -19,7 +19,7 @@ * This file handles the architecture-dependent parts of hardware exceptions */ -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 82f28749eb17de4c3e3b67cb664db99ecdb9f236..73d28f2a4e28aeb98e988e737f30f848c1a31422 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index f1c1cbc1c3c60f4cbe08a47cbb4c4d02e69d6ff6..300429024878139daf7b3b39418025ffc764c98e 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -8,6 +8,7 @@ * cpu specific common code for 85xx/86xx processors. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 843dd191ccf780b627e0fd5b2208202c290c6384..29489b46e6cd084f0c6ed6130f6c4bfdfa38d145 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 29399bcd8b6866cdc67cd398944f57fc3af0fd39..8e1f6c964d3f3f2d8610ee738a39ca72a7dba691 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -5,14 +5,12 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include #include #include -#include -#include struct paace *ppaact; struct paace *sec; diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index f16bc1996639d79ee67a195c45209de6594f3f99..35409dc8824c1807f7607e57a2fbdac2a3ce6b1f 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -6,6 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 831a11736cc8f135780da00ad7e10042b8890a02..b906279226a52c83ba7dea772caa89cf587efb11 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -3,6 +3,7 @@ * Copyright 2012-2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0c7288c75740febe9dee1e132028d39e314496a5..c0b4a1217d338f7c671bd98639d3fb52aaba99f7 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -3,13 +3,13 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include #include #include #include -#include #include #include diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index 21dfce4c8c732dd9b9bc79e4cf53d9739c5fd691..b94faa5408e1013525dceb5d8f23fc8c35a0289c 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -39,8 +39,6 @@ #endif #if defined(__KERNEL__) && !defined(__ASSEMBLY__) -#include - extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index e69e7dbefe88b0803abc2d955e10248dda7a8b61..1459db74beea62fa36135195ec4224caf3cc020f 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -8,7 +8,7 @@ #ifndef _ASM_FSL_DMA_H_ #define _ASM_FSL_DMA_H_ -#include +#include #ifdef CONFIG_MPC83xx typedef struct fsl_dma { diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 4ce869b5c189980989b834c246d991d2183cde5e..0af3d8902ace15906a8d59869cebfd07ac9f5022 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -6,9 +6,7 @@ #ifndef _FSL_LIODN_H_ #define _FSL_LIODN_H_ -#include -#include -#include +#include #include struct srio_liodn_id_table { diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 021eec72382d4d16a1180c067b211d6a97ca1029..54ef4fb629542090cd41a7748d0dbb8413f39e98 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -6,8 +6,6 @@ #ifndef _FSL_PORTALS_H_ #define _FSL_PORTALS_H_ -#include - /* entries must be in order and contiguous */ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index fdf76115233344f9fee397c3153bdc7448599d86..ddde4f80c632ee70967323b22cd8a83c51388def 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -7,7 +7,6 @@ #define __FSL_SERDES_H #include -#include enum srds_prtcl { /* diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index a9efbbdd3d498c9b25a9850b0dbff996267f1720..f7860122a00b903765850205f1aaf4dad156173c 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -93,6 +93,4 @@ struct arch_global_data { #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") -#include - #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h index e11300cab20dc299820948c3744c923625ccb2d7..cf1300f6e297c23bb7e9388c09eba4404fb5b226 100644 --- a/arch/powerpc/include/asm/immap_8xx.h +++ b/arch/powerpc/include/asm/immap_8xx.h @@ -12,8 +12,6 @@ #ifndef __IMMAP_8XX__ #define __IMMAP_8XX__ -#include - /* System configuration registers. */ typedef struct sys_conf { diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c index 6491c210f4e25dd2be864416a81cffe74aaa2e3c..55dcad5df8e9888a2e2602953a6c066a9a7acc39 100644 --- a/arch/powerpc/lib/bdinfo.c +++ b/arch/powerpc/lib/bdinfo.c @@ -6,6 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index f55b5ff8320eb08218e26841c900c57bb264cceb..75c6bfd2bf8151306cbc3ad7a3560e84d7b358df 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -7,7 +7,7 @@ */ -#include +#include #include #include #include diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c index e480b26964948d95f4e9ed944a2e0a1979e0482e..c4c5c2d45138ab532151d5414840bcd8de397515 100644 --- a/arch/powerpc/lib/cache.c +++ b/arch/powerpc/lib/cache.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/powerpc/lib/extable.c b/arch/powerpc/lib/extable.c index fd45e8a790d984e609c2a3d18fb42848b2363989..7e9d4f22f39048ba15bd3049317bf39ac90302fd 100644 --- a/arch/powerpc/lib/extable.c +++ b/arch/powerpc/lib/extable.c @@ -5,6 +5,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include /* diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index 92b8a0bceacf4a89b3b4c0f38984aeb39e38c107..df312dfa28ef1c8231b717cdb71e9fa151cb04a0 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -7,7 +7,7 @@ * Gleb Natapov */ -#include +#include #include #include #include diff --git a/arch/powerpc/lib/kgdb.c b/arch/powerpc/lib/kgdb.c index 20fcb7eef0ece3fe883aeb67d7bddae96ad8b6df..8727d18884c427d4df25751cdf4e09aaa559e5bd 100644 --- a/arch/powerpc/lib/kgdb.c +++ b/arch/powerpc/lib/kgdb.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 3a24cbfff3bcfed25e601f34686de427fd9241ce..b638ea7be6117f8c7800dc19dccdb747824da6cb 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -2,6 +2,7 @@ /* * Copyright 2012 Stefan Roese */ +#include #include #include #include diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c index afd869e4ac30fb64e6483c3adf4c97da21a5f10b..2e731aa8701dd0da2af00372e06ee715d8d0958f 100644 --- a/arch/powerpc/lib/stack.c +++ b/arch/powerpc/lib/stack.c @@ -10,6 +10,7 @@ * Sysgo Real-Time Solutions, GmbH * Marius Groeger */ +#include #include #include #include diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c index 0a0e75e726b0e9cb244c68ec2bd10ba0a5491a0d..8d6babfb83d6edd71785651325fbd2d44836b511 100644 --- a/arch/powerpc/lib/time.c +++ b/arch/powerpc/lib/time.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7e20ef63bba016b2f7c3a7b14aff0c5ea1b4b1a4..fa3b016c52728862019c426f031262c40901ee51 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE Sifive core devices that uses L2 cache to store SPL. # board-specific options below -source "board/AndesTech/ae350/Kconfig" +source "board/andestech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/openpiton/riscv64/Kconfig" @@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" # platform-specific options below -source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/andes/Kconfig" source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig similarity index 91% rename from arch/riscv/cpu/andesv5/Kconfig rename to arch/riscv/cpu/andes/Kconfig index e3efb0de8f05f91e044a67df032012b1373506b5..120fec5e5409b6e31b251fa9d3a7c546ac2cfcfe 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andes/Kconfig @@ -1,4 +1,4 @@ -config RISCV_NDS +config RISCV_ANDES bool select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 @@ -8,7 +8,7 @@ config RISCV_NDS imply ANDES_PLMT_TIMER imply SPL_ANDES_PLMT_TIMER imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE + imply ANDES_L2_CACHE imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile similarity index 100% rename from arch/riscv/cpu/andesv5/Makefile rename to arch/riscv/cpu/andes/Makefile diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c similarity index 90% rename from arch/riscv/cpu/andesv5/cache.c rename to arch/riscv/cpu/andes/cache.c index 269bb27f75a642bb14f3f54f0c56d245f4ee1f09..7d3df8722dd0e1d9e63eced941a2bd48d7e2feee 100644 --- a/arch/riscv/cpu/andesv5/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -12,21 +12,21 @@ #include #include -#ifdef CONFIG_V5L2_CACHE +#ifdef CONFIG_ANDES_L2_CACHE void enable_caches(void) { struct udevice *dev; int ret; ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(v5l2_cache), + DM_DRIVER_GET(andes_l2_cache), &dev); if (ret) { - log_debug("Cannot enable v5l2 cache\n"); + log_debug("Cannot enable Andes L2 cache\n"); } else { ret = cache_enable(dev); if (ret) - log_debug("v5l2 cache enable failed\n"); + log_debug("Failed to enable Andes L2 cache\n"); } } @@ -78,7 +78,7 @@ void dcache_enable(void) asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); #endif -#ifdef CONFIG_V5L2_CACHE +#ifdef CONFIG_ANDES_L2_CACHE cache_ops(cache_enable); #endif } @@ -89,7 +89,7 @@ void dcache_disable(void) asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); #endif -#ifdef CONFIG_V5L2_CACHE +#ifdef CONFIG_ANDES_L2_CACHE cache_ops(cache_disable); #endif } diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c similarity index 100% rename from arch/riscv/cpu/andesv5/cpu.c rename to arch/riscv/cpu/andes/cpu.c diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c similarity index 100% rename from arch/riscv/cpu/andesv5/spl.c rename to arch/riscv/cpu/andes/spl.c diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index 62d184aeb5719e91b1a6e39f223b3fffa56575a3..45ad2a5f7bc64be91c3784a6570f5848c5c843f4 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -12,6 +12,13 @@ u8 get_pcb_revision_from_eeprom(void); u32 get_ddr_size_from_eeprom(void); +/** + * get_mmc_size_from_eeprom() - read eMMC size from EEPROM + * + * @return: size in GiB or 0 on error. + */ +u32 get_mmc_size_from_eeprom(void); + /** * get_product_id_from_eeprom - get product ID string * diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c index 161335abee18f17fd477ab4c0c4f2edf396b02b1..03014c56dce285422e6ec1b516fc791a2f1a83cf 100644 --- a/arch/riscv/lib/boot.c +++ b/arch/riscv/lib/boot.c @@ -4,8 +4,7 @@ * Rick Chen, Andes Technology Corporation */ -#include -#include +#include unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char *const argv[]) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 7350e2ced8552ad911c393725c3e568f09ce1dc6..f9a1428a486c6bf7dc01200d7611d7c40a15ac98 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -60,21 +60,20 @@ static void show_regs(struct pt_regs *regs) #endif } -#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER) -static void show_backtrace(struct pt_regs *regs) +static void __maybe_unused show_backtrace(struct pt_regs *regs) { uintptr_t *fp = (uintptr_t *)regs->s0; unsigned count = 0; ulong ra; - printf("backtrace:\n"); + printf("\nbacktrace:\n"); /* there are a few entry points where the s0 register is * set to gd, so to avoid changing those, just abort if * the value is the same */ while (fp != NULL && fp != (uintptr_t *)gd) { ra = fp[-1]; - printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT, + printf("%3d: FP: " REG_FMT " RA: " REG_FMT, count, (ulong)fp, ra); if (gd && gd->flags & GD_FLG_RELOC) @@ -87,12 +86,6 @@ static void show_backtrace(struct pt_regs *regs) count++; } } -#else -static void show_backtrace(struct pt_regs *regs) -{ - printf("No backtrace support enabled\n"); -} -#endif /** * instr_len() - get instruction length @@ -165,7 +158,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); - show_backtrace(regs); + if (CONFIG_IS_ENABLED(FRAMEPOINTER)) + show_backtrace(regs); show_code(epc); show_efi_loaded_images(epc); panic("\n"); diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index 309422f75e3f31dbaf555f14ced7670e508e7632..001b2b53c1c8a80b23eff9fe25dcb7e23d96fa10 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -10,7 +10,6 @@ #define __ASM_GBL_DATA_H #include -#include /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 8c1839935ca1acf4b5a29fbe6bbef53cb05f99fb..0f7dfdd3cf7909e187b02a62be090af70d21fb1e 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -4,6 +4,7 @@ * (C) Copyright 2007 Nobuhiro Iwamatsu */ +#include #include #include #include diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index b0ad685a91b12080a67b039efeba47759e088335..1b2f50dbe6e4339bc595374f9ad094564dc60442 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -4,6 +4,7 @@ * Nobuhiro Iwamatsu */ +#include #include #include #include diff --git a/arch/sh/cpu/sh4/interrupts.c b/arch/sh/cpu/sh4/interrupts.c index eace09aeabfa8d45dbd89fe391a2606943d8266f..278a3e32ac910b0dcd351f3a8f1cc3cdbc318e18 100644 --- a/arch/sh/cpu/sh4/interrupts.c +++ b/arch/sh/cpu/sh4/interrupts.c @@ -4,6 +4,7 @@ * Nobuhiro Iwamatsu */ +#include #include int interrupt_init(void) diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c index c59743374657092ca07b6da0f2bbda2e434cb112..bf403d3c520ec517dd49c1f4d0db03840cf9703e 100644 --- a/arch/sh/cpu/sh4/watchdog.c +++ b/arch/sh/cpu/sh4/watchdog.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index 933c302d68cead1a5b7d4d076fff3a96bfa68fa5..bd946ffd8fd7305d74cd956cc9e35499ffae613c 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -10,8 +10,6 @@ #ifndef __ASM_SH_GLOBALDATA_H_ #define __ASM_SH_GLOBALDATA_H_ -#include - /* Architecture-specific global data */ struct arch_global_data { }; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 53b1c147c2e30a39e37a2f95fa58ef3bf6ebbe21..b31fa6d70311c523075a58d5be1c7bba29858768 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Vladimir Zapolskiy */ -#include +#include #include #include diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index e298d766b52d0ae666671480916685d7a55caef8..05d586b1b6cecc2f2a68650f07a9dd224d877b4f 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -7,7 +7,7 @@ * (c) Copyright 2008 Renesas Solutions Corp. */ -#include +#include #include #include #include diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index 5feb19835561f94f41e0ea8db3afbfb9a52fa101..19c8e3ca3e7be63606f6388155658677c23a2053 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -10,6 +10,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/sh/lib/time_sh2.c b/arch/sh/lib/time_sh2.c index 0ee7dc756ba6701a461b1422ac55c1bb297a182d..5484c543c6c8284a67716e3dcff824dd1ff16c1b 100644 --- a/arch/sh/lib/time_sh2.c +++ b/arch/sh/lib/time_sh2.c @@ -7,6 +7,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index e731c6a7cb36009e6ff6deccfbe3435f02a6b2e5..c2e285ff0f62c38e5acb33b05345c233b47d7359 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -9,10 +9,10 @@ * Linux SuperH zImage loading and boot */ +#include #include #include #include -#include #include #include diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index 13fe695014be9f2085290e16db1dd96508c52952..da01e71335f1cbd2df719a1b8850a369777ca7ea 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -6,10 +6,10 @@ #define LOG_CATEGORY UCLASS_IRQ +#include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index 76230aea837d9051179ad730ad4a2103cc88c3bf..c610a7f44770fe2c606f0a0325bbff89087fbbe7 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY LOGC_ACPI +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index f480bb1d8c347f43997987cefe381fb9f6510f82..647c9df6a72b27e9006b0345c73b760ab55bb4f3 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c index 498b306cd6183cf96c37344ad17ca718b2ee52a6..9a5502617bf553b3d5878cad4aa72b75f5d63041 100644 --- a/arch/x86/cpu/apollolake/cpu_common.c +++ b/arch/x86/cpu/apollolake/cpu_common.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8798fa79d4c193f32bde7b9e6396c8e41fbb887a..8f48457ee2209e656510cc06b1ef355f52103617 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -5,6 +5,7 @@ * Portions taken from coreboot */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index f6fbddce922aa8a33fe5b4fcd2be2fb090b90659..fb75e1f709519bd8a46ae4e7e89def11665a0381 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -3,6 +3,7 @@ * Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 19065e17ae04d8bd49be3f142cbe7a3090c469b4..c6be707e4eaf537ca92ae3921bac2902cd10456f 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 5fca19f90d382b7ecbc545d944fdbf7ee35f8680..a9b13c0c7047684ba62cf57757c6d6b89fe239a0 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 9ee362239efefd1a8f38cbb17909a6150cf22ef7..2405dec8525b1af4e3d5aa93164844b4a833de62 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index 531ff1cd91f47058d5feefab3066a30a6617235a..4be6366f0438fcfc807dd9ce94109194e58e4c98 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -5,6 +5,7 @@ * From coreboot Apollo Lake support lpc.c */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index 32190312ff8cd879bddb704cac5ef69522cbf49f..a0f9b031dea31d74f129ec3c0e2249648f595bfd 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 32fd0344861e9040dbbaa69d21b5178b50d5d4ec..163119e2e9e9c706d088f9fb17576bb3047cf43b 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c index b1503c25140aa542be90cca57aa8c9c0f723a973..5ed7963579eaa43ab1a094e72d8cee9a85509b60 100644 --- a/arch/x86/cpu/apollolake/punit.c +++ b/arch/x86/cpu/apollolake/punit.c @@ -3,10 +3,10 @@ * Copyright 2019 Google LLC */ +#include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index b351d73e7d8b1ea6021c2afa09515e41766106c9..6078d5a200e8841a1cec26accc1a1f73a0f87e49 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/systemagent.c b/arch/x86/cpu/apollolake/systemagent.c index f966b9083fc2ea1da32a4695faecdd6907506713..b6bc2ba14f151e5b2329dcb3dea14e9ca8760ef8 100644 --- a/arch/x86/cpu/apollolake/systemagent.c +++ b/arch/x86/cpu/apollolake/systemagent.c @@ -4,6 +4,7 @@ * Take from coreboot project file of the same name */ +#include #include #include #include diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index 7e4c816dcef0d9fd31771242c4df669b3190f162..a9362436000cd1e90c12f6c27e7bce2ea88027e1 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -7,6 +7,7 @@ * Some code from coreboot lpss.c */ +#include #include #include #include diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 7821964f1fca96c385140b3dc48808c47c4609a9..ccc4851b1881dfbb94c88a1b5ef9b26dffebbebb 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 7756a1a4a8e857905817489148a9b17da982c209..c270426d820818f9576c32fea0db0e9ced27faab 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -5,6 +5,7 @@ * Based on code from coreboot */ +#include #include #include #include diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 3736127239e56be4e464b2bdf0914429bee14159..08dbd5538f7a9fac331d957d95ff3a4f8ebf3466 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 9eb456f90d1085ec3a821508aa8fa8665970a70e..fb3f946c45f90d9225799bd43c4ffb7088b06cbd 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -5,6 +5,7 @@ * Copyright (C) 2015, Kodak Alaris, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 839ff4d2bf219dfd3053f2026e27676f16b00eb3..f73738ce5c01bbe07ec0cc599beea8374d2843fe 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include @@ -10,7 +11,6 @@ #include #include #include -#include #include /* GPIO SUS */ diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c index 8cf4b628d41a4559dbb11b67a3311283969c5e65..3345049993d6f301465ccb9bc360909c7068db03 100644 --- a/arch/x86/cpu/braswell/braswell.c +++ b/arch/x86/cpu/braswell/braswell.c @@ -3,10 +3,10 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #include #include -#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c index 8b28d28d13663163ffa6cd15ea98a6f6775b0a95..d78c6b0feb6ab192dbfa1ceef4dc6953db884e53 100644 --- a/arch/x86/cpu/braswell/early_uart.c +++ b/arch/x86/cpu/braswell/early_uart.c @@ -3,6 +3,7 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #define PCI_DEV_CONFIG(segbus, dev, fn) ( \ diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index aaf3e67f81cc5c142ee9cf8c361fb0cf22bad3e8..243298fd5718b23717c561c40cf7ec18db645e4b 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -3,6 +3,7 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/adsp.c b/arch/x86/cpu/broadwell/adsp.c index 90b2449475e56d2dc457a06d3cfa351cb3059412..1fa18237809cdfe9d1f9283a8701949bd94ce15c 100644 --- a/arch/x86/cpu/broadwell/adsp.c +++ b/arch/x86/cpu/broadwell/adsp.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_SYSCON +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index dc6717eca40ea8c307a2a6bed9c93fd999716061..cbd4a3b67973c46afa78c4b5e8b237e9a932682f 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -5,6 +5,7 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c index a48be29599433945311eb6f22eb6ff4500070767..df5a9675ee4baf380c7cd53fdbc79cd8f9013afe 100644 --- a/arch/x86/cpu/broadwell/cpu_from_spl.c +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include int misc_init_r(void) { diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index c43fb7a608b4e411faa79f4724490f589e498659..2049dbfe24a57c43dba1802301febe9dbae91fc2 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -5,6 +5,7 @@ * Based on code from coreboot src/soc/intel/broadwell/cpu.c */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c index f8b2a60d09f1ce6231ebec8e1d0cecbde1cdabb9..cb5595c930e143dc9c6954a513df9b82b5ebd67f 100644 --- a/arch/x86/cpu/broadwell/iobp.c +++ b/arch/x86/cpu/broadwell/iobp.c @@ -5,6 +5,7 @@ * Modified from coreboot */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c index b945693f1cf9e1d2fc3450e071aec94981f65237..d2638a4e7a6b840dd60b6162542632663e6b6140 100644 --- a/arch/x86/cpu/broadwell/lpc.c +++ b/arch/x86/cpu/broadwell/lpc.c @@ -5,6 +5,7 @@ * From coreboot broadwell support */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c index 3399d822e5b65bbd4822f7a25d83c610f8cd4e4e..ae16ce2649922137070943e48cbc0d43912ffa39 100644 --- a/arch/x86/cpu/broadwell/me.c +++ b/arch/x86/cpu/broadwell/me.c @@ -5,6 +5,7 @@ * Based on code from coreboot src/soc/intel/broadwell/me_status.c */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c index d67ab03627d12ab1eaf58cfdaccbbcd13c2fc142..141babc51c3a57c376c8f160a28d3bcb46f34965 100644 --- a/arch/x86/cpu/broadwell/northbridge.c +++ b/arch/x86/cpu/broadwell/northbridge.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 The Chromium Authors */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 2c8b7380d962e36b9ca63c9d9f988672990ce21f..37fcddbb9b038c997feb949decad388854583660 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c index b6313c3466a403c04c7b0b6c081facd311805ae7..85bd37101ba21cc6c69dbf6344f4940ca1dedd71 100644 --- a/arch/x86/cpu/broadwell/pinctrl_broadwell.c +++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c index e1d60915f55a4826aecda60d642d796dc736cbda..62fd2e8d2c0e85e0f8376ce54ee425911266e1a6 100644 --- a/arch/x86/cpu/broadwell/power_state.c +++ b/arch/x86/cpu/broadwell/power_state.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Google, Inc. */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 653d31dd67c551b8bd304725a7f58514e960ac6a..df2df7972e98575e2b7b04f3b856284cfbb80472 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -6,7 +6,7 @@ * Copyright (c) 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c index 0f67ba9666f60d37f8047d43af78ec2a3c2b1fe0..be3c9e764ef38935031dc8b5920e6f78b67e8cb4 100644 --- a/arch/x86/cpu/broadwell/sata.c +++ b/arch/x86/cpu/broadwell/sata.c @@ -5,6 +5,7 @@ * From coreboot src/soc/intel/broadwell/sata.c */ +#include #include #include #include diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index cd534a17cf15943b48a24d1f989002dd4bdb8477..d30ebee021ead6563ae5e1786a841b9bbff20d6d 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d474c79e25efbb2a8f574ff6fbc6b5928c930e7a..82fe4c71cd27f17bb65c23b39c46a09b54e97819 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -5,6 +5,7 @@ * Graeme Russ, graeme.russ@gmail.com. */ +#include #include #include #include diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c index 566c65a96aedf688c1908f08761efd4e2d6f24cb..36661871e9234358aef62c99a39a3b92ac5002f1 100644 --- a/arch/x86/cpu/coreboot/coreboot_spl.c +++ b/arch/x86/cpu/coreboot/coreboot_spl.c @@ -3,6 +3,7 @@ * Copyright 2020 Google LLC */ +#include #include int dram_init(void) diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 013225f129a9c6d34211211e3a7a13f3b9a481e8..26352df421f7321de2ccb5283b53ebf6330ae48c 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -5,6 +5,7 @@ * Graeme Russ, */ +#include #include #include #include diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index ec4003c4e77e57d12527921d362167332b5ac14b..3ad611a530c429d77fa02268fd382b23f5752aa7 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -5,10 +5,10 @@ * Modified from the coreboot version */ +#include #include #include #include -#include #include static struct timestamp_table *ts_table __section(".data"); diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index c8433360f28e9c54dd9928b7b64521cf0c3121f9..ce55efc454bfa35b7939e300737b9ddb8bcb26fc 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -20,6 +20,7 @@ #define LOG_CATEGORY UCLASS_CPU +#include #include #include #include diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 6c53f0ea821fcc0f9eb34fb8b00f34d549c4ae57..59da41f383336787bf26a75d4d841297ef369514 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 218a68c4642dfc15cddc7faa18ba5f5a005aa227..f754489784a727537a0ab4333ae1d31d02a612a7 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -3,11 +3,11 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include #include -#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 642a87a37d8b2aeb65cca9adaf7506511f5ba78f..708bfbe7ee488d6f6e8a9915a9eb89bcdd8238e8 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include @@ -16,7 +17,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe400711402d375b7e74ecb4f5f11695944b8c9..56f3326146ca6c2158878771910644f162a23068 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index db2727d74851562d4f222d6a26327290d36169dd..8882532ebf3ad06ad387e2d99c606106abfb6583 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -18,6 +18,7 @@ * src/arch/x86/lib/cpu.c */ +#include #include #include #include @@ -31,7 +32,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index b3f4214acdb7729872b66a848d7961e47357871e..f3f3527237f2ecfe6bc828823f6f7d6d68721fbd 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -10,6 +10,7 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index 29676b4abfae66eed7897dfc7150c5e8db578286..d94ec208f65d58cb1dced468013f7787a3f15c86 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -8,6 +8,7 @@ * Modified from coreboot src/soc/intel/common/block/acpi.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index 46d9ede09cb0faee04025e2ec11b9167aeca122a..00308dbdef9bc62333e3094d86d2bb21f85020f9 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -10,6 +10,7 @@ * Copyright (C) 2012 Kyösti Mälkki */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index e7f4191304298eb7c37f9eef5c28e608763e728a..8f489e6c651c0203f7fa8743b38247837bb3949a 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -7,6 +7,7 @@ * Some code taken from coreboot cpulib.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 48b2ef253cbd23abb942a884c38548dfa2fca859..1c0dcedb5824473e362d75d2c847b44c0fcedf08 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c index e1d536be21224e6ef83d65ec4ee6154c60406800..5d3944dee2c84858d55a01b34343c464b8185f14 100644 --- a/arch/x86/cpu/intel_common/fast_spi.c +++ b/arch/x86/cpu/intel_common/fast_spi.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 75fa4e01d8ad481cae8de61d3a0df2ee321b1073..61ec5391b0942f9dd8c862b080f299237b84b8e4 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -6,6 +6,7 @@ * Modified from coreboot src/drivers/wifi/generic.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c index 78caff0dc123b066392d970d0dea9ddc4c869de4..1eed21d8cdf85c57b6010ddaeeb5ee57e05b08cf 100644 --- a/arch/x86/cpu/intel_common/intel_opregion.c +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -6,6 +6,7 @@ * Modified from coreboot src/soc/intel/gma/opregion.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 6d3184f969f92b6b30716ce2bfb8245c81371d00..ec73b3d89312adc5d1d4b08e28b1dc0d63841dc4 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -9,6 +9,7 @@ * Taken from coreboot itss.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c index f2bdf8c1e8780d388c2e64d4ec040fda95e03b2e..af68c0f079c42282f11a85acb7e6246a3c166a81 100644 --- a/arch/x86/cpu/intel_common/lpc.c +++ b/arch/x86/cpu/intel_common/lpc.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/lpss.c b/arch/x86/cpu/intel_common/lpss.c index 44cd3f0ca5f642449fab6a3901f4587fd4ab3696..26a2d2d1e36d9e0a270cf1153f14ca227a221a61 100644 --- a/arch/x86/cpu/intel_common/lpss.c +++ b/arch/x86/cpu/intel_common/lpss.c @@ -7,6 +7,7 @@ * Some code from coreboot lpss.c */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/me_status.c b/arch/x86/cpu/intel_common/me_status.c index a09bd5029ebb7660eef29de4629b7281b5a3b308..abc5f6fbc77bc307848f1b66225ea772fd1b9aba 100644 --- a/arch/x86/cpu/intel_common/me_status.c +++ b/arch/x86/cpu/intel_common/me_status.c @@ -5,6 +5,7 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ +#include #include #include diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 6cad2727075ce813df3fbe3d424fc7486ec47449..4d8e1d210838718b493bab85481bc10f4c8bd326 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -6,6 +6,7 @@ * Microcode update for Intel PIII and later CPUs */ +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index c834c05d130807bf8750efb73829e243a44f711f..ff959d1bd8d859ef62e553a79d81bec2e213a576 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -5,17 +5,17 @@ #define LOG_CATEGORY UCLASS_RAM -#include +#include #include #include #include #include #include -#include #include #include #include #include +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index 7aad8f8ca56a4167f4f1bd91be3b57e777ce1968..e4e53f73c08d94ff6245f708f34fb98d3dd5a05e 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_P2SB +#include #include #include #include diff --git a/arch/x86/cpu/intel_common/pch.c b/arch/x86/cpu/intel_common/pch.c index c4cc478b3064e0f8035f8f2792ec070c679a4d2c..af82b64a13c75032076efe3ea385da3e9350f12b 100644 --- a/arch/x86/cpu/intel_common/pch.c +++ b/arch/x86/cpu/intel_common/pch.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include diff --git a/arch/x86/cpu/intel_common/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c index a7524435ba0314e6142503400a954004ed3bca43..a3612817c45bb2558fc95f88b3eac7803b119691 100644 --- a/arch/x86/cpu/intel_common/report_platform.c +++ b/arch/x86/cpu/intel_common/report_platform.c @@ -5,12 +5,12 @@ * Copyright (C) 2012 Google Inc. */ +#include #include #include #include #include #include -#include static void report_cpu_info(void) { diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c index fa912bac57dd6a879747d0fe715f1bfa603bf25d..4f99de6ece2bc50c642d9f7afc291ee29d930f2f 100644 --- a/arch/x86/cpu/ioapic.c +++ b/arch/x86/cpu/ioapic.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index d4dd1816092be874800a5c525a0fa0fc0ef8a4a5..766b2451a2cc3e4b8762b22eed17cf6e48569e78 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 8ae4798f125ce8e4aea077111d39d9a6444e062a..417290f559e9e45d015dc7876704122c7c2e29ea 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2014 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index d71ab0a6385eb32242103ed964657fae0204201b..e71a10bfd441014b141c881bb7a9fcce4582c083 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -10,6 +10,7 @@ * Copyright (C) 2011 Google Inc. */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index ac868025f8edd17c479878682970a3badaa5a772..bee1671baf8b673b2a08b9210695142433fc6599 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -5,6 +5,7 @@ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c index 19b6ef283bc06db3a0e37c8f839b2be7e7477796..3c4ea6c267f8900ef3f30034efedc0bc99d363d9 100644 --- a/arch/x86/cpu/ivybridge/fsp_configs.c +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/ivybridge.c b/arch/x86/cpu/ivybridge/ivybridge.c index 81b54bb8dda5a35b3c35203dbd1233f05931eb19..eb3f362e4e99a25b84cb57ae7cab804ed6f9da1d 100644 --- a/arch/x86/cpu/ivybridge/ivybridge.c +++ b/arch/x86/cpu/ivybridge/ivybridge.c @@ -3,10 +3,10 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include -#include int arch_cpu_init(void) { diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 17a47edadbb8fbc7032fde9e28bf72e730f2f685..f931d2be1b521d2fd83f62b3f13023944c7032c8 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -5,6 +5,7 @@ * Copyright (C) 2008-2009 coresystems GmbH */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index b72de96a277eb0fe8c7bd0a899f5b264303aca87..3906a69796f3d475c3a4f4e54977b1506db169ba 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -6,6 +6,7 @@ * Copyright (C) 2011 The Chromium Authors */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 76e52f38ad8393ad0bfed9c6194e8e3842828c3e..994f8a4ff6a59f0e0622065922cfc9aff6457e23 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -6,6 +6,7 @@ * Copyright (C) 2011 The Chromium Authors */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 4e2484fa956de940f9b9f4658529bd99fb522319..f47ecdffae76ccd2966be111f5c8282d6f489324 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -4,6 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH */ +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index bddec6c66b6609326e7c0730411959ee93f35453..95a826da7130e751b1c78b72dba4c8ff83363c1f 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379f11c8aacc8288c9eddab95f830cd5..51dfe23f94d0711a073c83d436e689436dd1956d 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c index 55b1b1833eed9e297e5139608be5ee1eeead1cef..c0691454f1293aecc49f7d36f69548012efc5f67 100644 --- a/arch/x86/cpu/lapic.c +++ b/arch/x86/cpu/lapic.c @@ -6,6 +6,7 @@ * Copyright (C) 2014 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index aa1f47d7227eb7fb453fe2b6899b343dd5ea79cb..a133a5d8116159d2cc5cca51140c773adff59cfa 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -5,13 +5,13 @@ * Based on code from the coreboot file of the same name */ +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 50cba5fb88dc49231242d47d8e4cb4eebbbe6d8d..9c24ae984e907340dde770cd819128e91aff46aa 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -16,6 +16,7 @@ * since the MTRR registers are sometimes in flux. */ +#include #include #include #include diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index a7ad57f6de03f2452ac7b3650261344ff4b6a718..8a992ed82339f61bec2b872054078096a80fd9c3 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -8,6 +8,7 @@ * Daniel Engström, Omicron Ceti AB, */ +#include #include #include #include diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index 0708a380626f296caaf86fe0f6a587c1c0fdaa01..735b6560843aee7749583b24e958e66553a22c1d 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Miao Yan */ +#include #include #include #include diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index 62a301c0fd3ea7c3d5d12c4c7ae4e11495102e2f..d83abf00527132bb5838ddf9385d30c780aa0856 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index 17a04f86479ecd51907d3bd1463be9493ec1eb46..ebfe5956442a9320c399335e4968e384d5144171 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -6,6 +6,7 @@ * (C) Copyright 2019 Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 262584d01f0fff79ad379c010973272720c219e1..70414556086cc5574936766a983566430d16388f 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include static bool i440fx; diff --git a/arch/x86/cpu/qfw_cpu.c b/arch/x86/cpu/qfw_cpu.c index 468df5a36e61ae98823a1c2d7f65165867c8bc0b..ee00b8fe73279bfa381304fe98acda19dcc114fa 100644 --- a/arch/x86/cpu/qfw_cpu.c +++ b/arch/x86/cpu/qfw_cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 80e94600fc5af04d5180227dc5dc7c89d111c82d..0e18ceab68d4fe55af630cb282abb4c2f0e25fd2 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -3,13 +3,13 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include #include #include #include -#include static int quark_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry) diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4fa1dcb179e9a2dd38828613833376..ad98f3e07bae04874578ab56b62b37650e57407f 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index 3cca6bd4c227b67e47eb46e9c6f9c18831c734b3..df14779357d5c696593a1cea388aa9c920183c98 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -7,6 +7,7 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ +#include #include #include #include "mrc_util.h" diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index be9c36b96c4ff2c7d4a830df692b7fe48504d6dd..ce3c2b8ab426e8f811adaee99ce017d1a3acbd35 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -32,9 +32,9 @@ * DRAM unit configuration based on Valleyview MRC. */ +#include #include #include -#include #include "mrc_util.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 85408b3e33529acb7441cc0fe9724daf7e33e073..b0bc59b71ef5cc3ae87113c0937e7b5563ab8ca8 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -7,12 +7,12 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ +#include #include #include #include #include #include -#include #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c index 6261766cdf886ccaf0eedaa6ee93e64c2d551924..d4f8c082ffc2f4dee041e753fb61c4ff7bb89207 100644 --- a/arch/x86/cpu/quark/msg_port.c +++ b/arch/x86/cpu/quark/msg_port.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index fdf92b2c0c3a5b42216b299ab0ac925149161de7..62b83c228cfba3ac22f344bce947eb457343dd4a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #include static void quark_setup_mtrr(void) diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index a7e92b3f5c160674870c967bd181b1d609ece676..b4b3e1204bd5ac6affc8b2c1163b2af9b0bdbeb9 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -7,12 +7,11 @@ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei */ +#include #include #include #include #include -#include -#include #include "mrc_util.h" #include "hte.h" #include "smc.h" diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 3b5cbdb44f1a3469cf3c87358dd7185d95c53542..381edd0761587b21747b33ee874f92c0f9f02f88 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include void fsp_update_configs(struct fsp_config_data *config, diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 7c7eb413f993d0efbdea644b78c186382f0203dd..4a008622d19e33b5d4f9b2a251b4aefdb7e0bb6d 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625cd8fab5ebd3dfd165e08b475f0b7d..fbb33b246e5b5f395c6b7d5a8a32fc07a903f4b7 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c index 4c889dad6d2d4b47d7dd67e86034c995d7ad4d95..d28b280890d36060902db7090f6366c6b9538653 100644 --- a/arch/x86/cpu/slimbootloader/serial.c +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c index 142c9341cf86c041371ea7df2f925a1e49a8b451..ec5b87cfd63f862b7e5b9a619e4e9e44339d4929 100644 --- a/arch/x86/cpu/slimbootloader/slimbootloader.c +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index d4d0ef6f855269e2c3f24bc0bdc59f9e77d71d65..1d37cc9e2b0db384cfe951980fa8a8b71fd4886b 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -5,6 +5,7 @@ * Partially based on acpi.c for other x86 platforms */ +#include #include #include #include diff --git a/arch/x86/cpu/tangier/pinmux.c b/arch/x86/cpu/tangier/pinmux.c index 6afb8646a987aac6e4eebfab7d90b3ae553ade95..23bfa7c18d2c6c114c0f6102fe4886e19e257c26 100644 --- a/arch/x86/cpu/tangier/pinmux.c +++ b/arch/x86/cpu/tangier/pinmux.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Emlid Limited */ +#include #include #include #include diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b80b646bbcc4cfe6c49636e315b72e7..374b262b1348039dbf0acb47def815fefbc5081d 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/cpu/tangier/sysreset.c b/arch/x86/cpu/tangier/sysreset.c index f57423a611d2c0ae0d0bd6338e6372796f517c84..b03bc28f9353aa4cb5e372bac165545273b3323e 100644 --- a/arch/x86/cpu/tangier/sysreset.c +++ b/arch/x86/cpu/tangier/sysreset.c @@ -5,6 +5,7 @@ * Reset driver for tangier processor */ +#include #include #include #include diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 8a8f7d27a9d19d534daf11c79f3db8ff1cd271f1..1e2f6cc8b700fdb9dd1396535f1999615c46041a 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index c9b402c4dc73396f82f7a581d39631aded0cc6d3..e2c84cddec8e711d1b1b9f54051fedb0d38e737e 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -5,6 +5,7 @@ * Copyright (C) 2011 The Chromium Authors. */ +#include #include #include #include diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 80eab71031529e3db98855df8042957b48fdcfd8..5ea746ecce4ddb15b9fc643ba2327ca2a1c8f5a5 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c index b84ff798814edc0849b64c8b2bb3fda90b3adf9b..634f7660c03f9e9fa472a512f846afaa1871a506 100644 --- a/arch/x86/cpu/x86_64/interrupts.c +++ b/arch/x86/cpu/x86_64/interrupts.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/arch/x86/cpu/x86_64/misc.c b/arch/x86/cpu/x86_64/misc.c index 294511e6ebabadf6460b6f9096a14d6a8391c710..691b67ff68ab97ead8d95920894d50c86d3fd57b 100644 --- a/arch/x86/cpu/x86_64/misc.c +++ b/arch/x86/cpu/x86_64/misc.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/include/asm/arch-quark/mrc.h b/arch/x86/include/asm/arch-quark/mrc.h index 40c92a549cdfa39e325d5d7372d9f4b2dc1bd9bc..2353426cd6d2d0d15d35bab7542da4ccff5892b0 100644 --- a/arch/x86/include/asm/arch-quark/mrc.h +++ b/arch/x86/include/asm/arch-quark/mrc.h @@ -10,8 +10,6 @@ #ifndef _MRC_H_ #define _MRC_H_ -#include - #define MRC_VERSION 0x0111 /* architectural definitions */ diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h index 98a9360d5435ef35e0df821f9d6331c7e714ebdb..9527fdad3fd42ee0e5e7563a61dfa947333901f0 100644 --- a/arch/x86/include/asm/arch-quark/msg_port.h +++ b/arch/x86/include/asm/arch-quark/msg_port.h @@ -34,8 +34,6 @@ #ifndef __ASSEMBLY__ -#include - /** * msg_port_setup - set up the message port control register * diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index dec30e2b27f30581223c506712de65fe3d153aff..feca1983ba89a00f753db131c2e09bbec0e1789c 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -71,8 +71,6 @@ #ifndef __ASSEMBLY__ -#include - /* variable range MTRR usage */ enum { MTRR_VAR_ROM, diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 5864b2700cecc52d6bf5f9024f083fc9a31ca813..12fa395ffd28805c36934931396eb80adfa4b0d3 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -9,7 +9,6 @@ #define _COREBOOT_SYSINFO_H #include -#include /* Maximum number of memory range definitions */ #define SYSINFO_MAX_MEM_RANGES 32 diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 54aeffb9889dbf20253c6007703ab147248990b2..0dfb64babb962d5bdbc6631e171e6919b443d402 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -8,9 +8,6 @@ #ifndef _COREBOOT_TABLES_H #define _COREBOOT_TABLES_H -#include -#include - struct timestamp_entry { u32 entry_id; u64 entry_stamp; diff --git a/arch/x86/include/asm/early_cmos.h b/arch/x86/include/asm/early_cmos.h index 007aeb7c23eba46983a073cdad7ced7a8fc621c0..543a9e69f03af995eb9eaa61f422e5bbd4fdcc49 100644 --- a/arch/x86/include/asm/early_cmos.h +++ b/arch/x86/include/asm/early_cmos.h @@ -6,8 +6,6 @@ #ifndef __EARLY_CMOS_H #define __EARLY_CMOS_H -#include - /* CMOS actually resides in the RTC SRAM */ #define CMOS_IO_PORT 0x70 diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 06bd80ccc135374b7c6fe93b6816fe8fdb53db0b..1ef7f1f0349e6cc31622c7b0c926afd58c3ffe18 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -12,7 +12,6 @@ #include #include #include -#include enum pei_boot_mode_t { PEI_BOOT_NONE = 0, diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h index 5f6691939eb559489c71e885b7d44846155dd9db..aec49b9b815c6e1a1a683c516e9ceeecd1ae844c 100644 --- a/arch/x86/include/asm/handoff.h +++ b/arch/x86/include/asm/handoff.h @@ -9,8 +9,6 @@ #ifndef __x86_asm_handoff_h #define __x86_asm_handoff_h -#include - /** * struct arch_spl_handoff - architecture-specific handoff info * diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h index aa478594ec92a8e1788aa95c015b69ae52ef52a6..857036831492f9376117de4547aaa933ee5b57db 100644 --- a/arch/x86/include/asm/me_common.h +++ b/arch/x86/include/asm/me_common.h @@ -13,7 +13,6 @@ #define __ASM_ME_COMMON_H #include -#include #include #include diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 7c08f7a1d5c05b28b588b595559d58037f70a87c..f4c4d6c257c528e5d1e501e37cac00c9d49f492b 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -11,7 +11,6 @@ #include #include #include -#include struct udevice; diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index a73a2539ad35fa1962d00539440a91fe950e5b79..155fffabf080639faa75c4704a3cc88bae31f52c 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 880ef31df7d975284f26763a4779e17f057ca2ca..08e13fdea67f41fffe59ab2d769adfa7e26188fd 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_ACPI +#include #include #include #include diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 3a1e3318a15b934f97cd54794552733e4593d214..2c70acbe7b0b91ddc8bf1b2da72a593f2e5abc92 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -3,6 +3,7 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a42a7e6bbd65a90b813f6741d5aee7e4a4d963ac..a5683132b014564ea502e959fbc6a4ba71ecdc55 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_ACPI +#include #include #include #include diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c index b486f8fb37d634245aaf3e8cde7da45830a96392..ea2ec2a90833d516df0369deba0ea767ba7fb4e7 100644 --- a/arch/x86/lib/acpigen.c +++ b/arch/x86/lib/acpigen.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Google LLC */ +#include #include #include #include diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c index 7b2905dda56c4df16224946f11c19657c282d481..8df67db65c391d29a7a9a65ce6b3d04599434eca 100644 --- a/arch/x86/lib/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c @@ -11,6 +11,7 @@ * #defines from the assembly-language output. */ +#include #include #include diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 165e8ab944f016a268b309444305c9969c27cc77..124058442c55a096b97c37790c01eaabaf33fd8b 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include #include #include diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 03f7360032c6d496c05640bfdd315c9ac81f3630..f146bbd542277d3e968b10071d3369acef41230d 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -5,6 +5,7 @@ * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2009-2010 coresystems GmbH */ +#include #include #include #include diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index b2cf1527b1cd93b738f0e3c894410b2703d30879..d6b4da7e25022203b8339fa49a99f662fd6423e4 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -7,6 +7,7 @@ * Copyright (C) 2007-2009 coresystems GmbH */ +#include #include #include #include "bios_emul.h" diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 2c889bcd33c587af1b2c3834039d4790347b867e..050c420e86b69d211750cd3fdbe2ef6b09827d6e 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -7,6 +7,7 @@ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) */ +#include #include #include #include diff --git a/arch/x86/lib/cmd_boot.c b/arch/x86/lib/cmd_boot.c index 0444a5f89d3c3ae4aa92dc70ff97d69cebcd1fe0..4facbe5f32fb5d8918baaa0ead75d2c8a6f5bb96 100644 --- a/arch/x86/lib/cmd_boot.c +++ b/arch/x86/lib/cmd_boot.c @@ -14,6 +14,7 @@ * Marius Groeger */ +#include #include #include #include diff --git a/arch/x86/lib/coreboot/cb_support.c b/arch/x86/lib/coreboot/cb_support.c index b4d5fa4af32778ee81592552dbb53e67db3903f1..ebb45cdfb5b59df7b3d5b8d1d806d058d37633e5 100644 --- a/arch/x86/lib/coreboot/cb_support.c +++ b/arch/x86/lib/coreboot/cb_support.c @@ -5,9 +5,9 @@ * Copyright 2021 Google LLC */ +#include #include #include -#include unsigned int cb_install_e820_map(unsigned int max_entries, struct e820_entry *entries) diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c index ec997fa49cf28a08ad0f7a45257796c6179a42f8..f7fd9ea5bcbba53067a010bf8855f57cb0351576 100644 --- a/arch/x86/lib/coreboot/cb_sysinfo.c +++ b/arch/x86/lib/coreboot/cb_sysinfo.c @@ -6,12 +6,12 @@ * Copyright (C) 2009 coresystems GmbH */ +#include #include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 33fce5d0a5e51dbd36db431c0bdbfa35827cc0c8..05519d851a9d65b1c133252b3f45cb75b0dd5045 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/div64.c b/arch/x86/lib/div64.c index 57da889ef49b1d1870e38e96c1ba54f07be7c36b..2bea205f60f93b995b612393d906d2f5bbcf7537 100644 --- a/arch/x86/lib/div64.c +++ b/arch/x86/lib/div64.c @@ -6,7 +6,7 @@ * Copyright 2014 Google Inc. */ -#include +#include union overlay64 { u64 longw; diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 122b4f7ca01b61b15bfb4b1e20507652911fd59e..12fcff123805100deab3e14874c26e501ae7dea4 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/early_cmos.c b/arch/x86/lib/early_cmos.c index 5635d08718fa8baecac00da6dc0ad44625ff3566..f7b3bb2a8e190bd201e455daf587a02502c75dfa 100644 --- a/arch/x86/lib/early_cmos.c +++ b/arch/x86/lib/early_cmos.c @@ -10,6 +10,7 @@ * uclass write ops, that data is stored in little-endian mode. */ +#include #include #include diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index c47e6ca473881c0ea649601ed59f8f75f039dc78..8f2977a80709af50336b97878f018d33b2f1b3b9 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc17685df882bef73c733793e97005da44..cc889a688d8adf3529d040c17f68ed703526bc70 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 5f7701265a95340dca95ceb8bfa8188c1260af18..09d5da8c841a0113e7e899a73440971ab077a2cb 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_VIDEO +#include #include #include #include diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 19f9f65b2e410f5a9083a8fd0c744ece93bb708f..fd4d98ef627468e2f16fabefc9c88de4d822774a 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index ebf655a11439e371d0a28a8d96a55014a0662e08..df18f47675628cd2e2138f744aed733a7c4c0c32 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index f3a8134a3f2f5c3767954bc43f8143cb99a589dc..eee9ce54b1ce64ac59b438402c7b0de4cb289f53 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c index 6e311a12d20bced28d2a6bb947ec41f5ffe57fc1..d84c632f140742f8cc3ab4b6563d5ba3fb4adc46 100644 --- a/arch/x86/lib/fsp1/fsp_support.c +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_common.c b/arch/x86/lib/fsp2/fsp_common.c index 45a274c05123a4633608dc0a6e4a1233184baf62..d802a86967d5c83ba0220cf4834287d38727de64 100644 --- a/arch/x86/lib/fsp2/fsp_common.c +++ b/arch/x86/lib/fsp2/fsp_common.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 83c6d7bcc93f5b14ea5739898527412bd3426431..a1432239cfc1397717af8871c1b2a476d48f8f46 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index ecbadaae75cfb609f3dc8ddf50bd7648d04d201a..aadc08cf3c448ade3ce0816ed1cf9833219ecc3b 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index f4817830cc21ad793f51b6c0785830c31c9544d9..022e2cb64e5a52509613bc82aee67b7b97bb85e1 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -6,6 +6,7 @@ * Mostly taken from coreboot fsp2_0/memory_init.c */ +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index 16d30c25a57ac25a805f6fd00ba2eee605af61bb..a96d2b183f6e658dfcc338ddbf614134fee6976f 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_NORTHBRIDGE +#include #include #include #include diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c index 808f0eb9d29c506159048016d1904531c3e1e106..b2c76582453fac71378f7fa9c513727a67de11d2 100644 --- a/arch/x86/lib/fsp2/fsp_support.c +++ b/arch/x86/lib/fsp2/fsp_support.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c index 46e83aa395ab103ba24ab22dcb337cafc6202365..b35248e5fde7b3c7908d507b298f950bf178796b 100644 --- a/arch/x86/lib/hob.c +++ b/arch/x86/lib/hob.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include /** diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c index 8a590c6191faca7cebe69302a8e3bf409ea0002d..a8d1db188ece9eab5a54fb8d8038956172d70175 100644 --- a/arch/x86/lib/i8254.c +++ b/arch/x86/lib/i8254.c @@ -4,10 +4,10 @@ * Daniel Engström, Omicron Ceti AB, */ +#include #include #include #include -#include #define TIMER1_VALUE 18 /* 15.6us */ #define BEEP_FREQUENCY_HZ 440 diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c index 465ff70146f75b6a34f8a7c9bf0319f982246f68..a0e3c09257386c93bd6864c7ad51153a04063d8e 100644 --- a/arch/x86/lib/i8259.c +++ b/arch/x86/lib/i8259.c @@ -13,6 +13,7 @@ * Programmable Interrupt Controllers. */ +#include #include #include #include diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bd0efde00c1090d47c7cbc9ed7227f328ec06ff7..bf0c921577d192a2aaf089c0ce9dcc9cd8a8b5d3 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -4,11 +4,11 @@ * Graeme Russ, */ +#include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index f96b2bfd70eee26c6a2b048011aa8f3906ee6a97..ff52959ed285e241523bbdb960c5d2e1981d3b86 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -29,6 +29,7 @@ * Daniel Engström */ +#include #include #include #include diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 4f89db4e5389dfcad88060d19c547e62ae5f252f..67b931d3b28966ae6301a64fa0241f66181f630b 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include UCLASS_DRIVER(lpc) = { diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 5abd9288c2a3b3104139d998e55a0c4fc7b34d28..8e97d9ff36d93fe280c027135b8a9bcc5af1c056 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -5,6 +5,7 @@ * Adapted from coreboot src/arch/x86/boot/mpspec.c */ +#include #include #include #include diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 970704a8dd626eb69d95962608bbc9ce5901bf9c..6494b8d2634189a98ff2a92d55628ac338cef54e 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/arch/x86/lib/northbridge-uclass.c b/arch/x86/lib/northbridge-uclass.c index 1d1780535a2aee9e6fc558c36bf890ec7f87dcbf..383888724841ef95b1568a4d9c4691cc7ff686df 100644 --- a/arch/x86/lib/northbridge-uclass.c +++ b/arch/x86/lib/northbridge-uclass.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index 48cd1073c152ba77913894aa2eba41926df7ec20..382f768149f448ea9b63aebf11cae005c85f0cd5 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -8,6 +8,7 @@ * Software Foundation. */ +#include #include #include #include diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index d4f71c562f859d0fb265f56e0cdb5127809c2958..c93f245845de46f421aa37078edbeb45bd4884d0 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Google, Inc */ +#include #include #include #include diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 5178940901c28077ad69e32f8ae97cc00a1df279..caeaec9287fe621cefeafa9dc2f1eba92a2df12b 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -5,6 +5,7 @@ * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c */ +#include #include #include #include diff --git a/arch/x86/lib/pmu.c b/arch/x86/lib/pmu.c index 2127257cd431847b5ce81df7eee704e96df92ece..083aec8d8dd7010202df19345d5393ba7f28b7ff 100644 --- a/arch/x86/lib/pmu.c +++ b/arch/x86/lib/pmu.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c index 16cd6e49437c0b49e511da9b08ce863ca5efb0e9..03385396325d34ac13be95dcc9b2f8ea1e1c19dc 100644 --- a/arch/x86/lib/ramtest.c +++ b/arch/x86/lib/ramtest.c @@ -5,9 +5,9 @@ * From Coreboot src/lib/ramtest.c */ +#include #include #include -#include static void write_phys(unsigned long addr, u32 value) { diff --git a/arch/x86/lib/reloc_ia32_efi.c b/arch/x86/lib/reloc_ia32_efi.c index 17ab54dc2469e992fde0cbe70dcbbd04301cb75e..d56cd50bd937a1268949bf1b153b41bfdfb996b7 100644 --- a/arch/x86/lib/reloc_ia32_efi.c +++ b/arch/x86/lib/reloc_ia32_efi.c @@ -7,6 +7,7 @@ * All rights reserved. */ +#include #include #include diff --git a/arch/x86/lib/reloc_x86_64_efi.c b/arch/x86/lib/reloc_x86_64_efi.c index c7a21d9393d62713e25e9cf811d75ce1f5a1a275..2694de7110419322418c38b81dfdc11feb8c668e 100644 --- a/arch/x86/lib/reloc_x86_64_efi.c +++ b/arch/x86/lib/reloc_x86_64_efi.c @@ -9,6 +9,7 @@ * All rights reserved. */ +#include #include #include diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 9ce56062d24732da8f729572c38e3d903867c583..da819b9bdd2c1be9e291dee24de2b801886abecd 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -14,6 +14,7 @@ * Marius Groeger */ +#include #include #include #include diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c index 02fed601fb65fe827ba8c246b452e4c50978fc50..90ef239bcd3def2f10f55497bc8a95129b338893 100644 --- a/arch/x86/lib/scu.c +++ b/arch/x86/lib/scu.c @@ -9,6 +9,7 @@ * * This driver enables IPC channel to SCU. */ +#include #include #include #include diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 04d97327a4df8d0411ba385bf38917d8e44f497e..85e963b634b5070013c315aff6d4eb96af8cbb1e 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -12,6 +12,7 @@ * See https://simplefirmware.org/ for details */ +#include #include #include #include diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index f761fbc8bc3b9aaec7930477a75e3f0ff28fd631..c15f11f8cdf44209058ae35235589a1cb95093ac 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include @@ -28,7 +29,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 45a70e927634dd411cdae729d8707105b3e8b9fe..1095dc92c5aa13c514853c2543b666ab10810892 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_ACPI +#include #include #include #include diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 7c03dea07111b8d3ba071498244fa6a0e508f111..273e9c8e1ca157238fcb6d30fd8f1c0aa2012ae3 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 73a21bc8f03b650180d0fc42c03e30c0ea41118b..d7403876c13d4232fef942aee3fa089f3c47912a 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -14,6 +14,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index abcd8f7984fac81e601e650b10e2a826b3654894..98d9753b7e34be14e9de5d0e792d161b6c409683 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -8,7 +8,7 @@ * CPU specific code */ -#include +#include #include #include #include diff --git a/arch/xtensa/cpu/exceptions.c b/arch/xtensa/cpu/exceptions.c index 206767094e9f8895a142dda1bad2358f8588aa34..cf9af4326a2952d82e218b02665d9747aa520e18 100644 --- a/arch/xtensa/cpu/exceptions.c +++ b/arch/xtensa/cpu/exceptions.c @@ -10,12 +10,12 @@ * (Note that alloca is a special case and handled in start.S) */ +#include #include #include #include #include #include -#include typedef void (*handler_t)(struct pt_regs *); diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h index 40c129db4ace0e5066ad9f349bf909a296ee4637..1157978ab688ee2873019a7962f9cba12bf46723 100644 --- a/arch/xtensa/include/asm/global_data.h +++ b/arch/xtensa/include/asm/global_data.h @@ -6,8 +6,6 @@ #ifndef _XTENSA_GBL_DATA_H #define _XTENSA_GBL_DATA_H -#include - /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 1de06b7fb53daaf3bb978957f633b441f72075d8..9780d46e9b894268f79311872d79a058d9f72411 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -4,6 +4,7 @@ * (C) Copyright 2014 Cadence Design Systems Inc. */ +#include #include #include #include diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c index e6a7f6827fc2541fa6756f90191203e427ba1d94..4e0c0acc3bbe3d3b41d8215c1f0cef146ec08c42 100644 --- a/arch/xtensa/lib/cache.c +++ b/arch/xtensa/lib/cache.c @@ -4,6 +4,7 @@ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. */ +#include #include #include diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index c6739584bbf2b67967afd19e931f075d88633813..1c927d2a6a3cdcdd3eac807a60064f4544dd37ba 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -3,6 +3,7 @@ * (C) Copyright 2008 - 2013 Tensilica Inc. */ +#include #include #include #include diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index 192a2fa6327b448da9c6b3dfa070adc94eb674ed..36945bbdccf5d1cd88b6309f1d001fd80bfceced 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -9,7 +9,7 @@ * */ -#include +#include #include #include #include diff --git a/board/BuR/brppt1/mux.c b/board/BuR/brppt1/mux.c index 8932b9ab3b1ac5375a659bd3626b8ac70e1e3ab4..5d2c7a201ea0e7fa088f61c857a3ecb6d6b9724d 100644 --- a/board/BuR/brppt1/mux.c +++ b/board/BuR/brppt1/mux.c @@ -8,6 +8,7 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com */ +#include #include #include #include diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index 105fac8912d03d1be8937ef8f86749508d5ebe2d..ee006f0196c6d9e36b7510a9785dd88c514a9af2 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -6,6 +6,7 @@ * B&R Industrial Automation GmbH - http://www.br-automation.com/ * */ +#include #include #include #include diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index 2d3f593d0ab0052f4b439a1df0378e539665a5be..738a5d2ff94438bc738b616e6b7d757bb2057e0a 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -8,6 +8,7 @@ * B&R Industrial Automation GmbH - http://www.br-automation.com * */ +#include #include #include #include diff --git a/board/BuR/brsmarc1/mux.c b/board/BuR/brsmarc1/mux.c index b59d64f93ef3d36724e66d6066718d61cbad77ef..33c214d6b2a7e81af3eb605574a0a67efb5928fc 100644 --- a/board/BuR/brsmarc1/mux.c +++ b/board/BuR/brsmarc1/mux.c @@ -9,6 +9,7 @@ * */ +#include #include #include #include diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index b9b595cb156d823df1d1db38776b6df0844e3be4..a909104df4ac0c2a8f800a39f108b6053c0fe87a 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -8,6 +8,7 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com * */ +#include #include #include #include diff --git a/board/BuR/brxre1/mux.c b/board/BuR/brxre1/mux.c index e2e8ec57678f5280d2e15f76c319a83aeaf35232..6c5ad891ba915597a7c05b60f4b60c7f0b9d475d 100644 --- a/board/BuR/brxre1/mux.c +++ b/board/BuR/brxre1/mux.c @@ -8,6 +8,7 @@ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com */ +#include #include #include #include diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c index f5d09fef3d3499310276a892101122b98af452d0..32f32b65e9d82cc172243f9d0fb3860f7709ebff 100644 --- a/board/BuR/common/br_resetc.c +++ b/board/BuR/common/br_resetc.c @@ -5,6 +5,7 @@ * Copyright (C) 2019 Hannes Schmelzer * B&R Industrial Automation GmbH - http://www.br-automation.com/ * */ +#include #include #include #include diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 8aff821cfe8a11206b6e40b30d7e94eaf711bd4a..3c78020bf93c7c6fa19481f191314c66ed89cba9 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index cf5610861b50d502ada3770e0a7bd7c10b93e2fb..ea49c7a99c0bcdc60a1d45427fa08ddff0aa1884 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -7,7 +7,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include "asm/m5282.h" diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 1591b40deee6694f13c304db371c228dba0e5fcf..11d875647170d5096297d6fabeceda3d3cb28b7d 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marek Behún */ -#include +#include #include #include #include diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index e4ed7f258109762f570dce8df2b73e636d5e0604..00114e6d915651fa0f9f3d2beab2e1a76b8507bc 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 Marek Behún */ -#include +#include #include #include #include diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4ee1a394b0243c56d714b02816a4f486e00b17fa..3b7a71bdad2565b815e43cf3d05f6d606925d5b4 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -7,7 +7,7 @@ * Marvell/db-88f6820-gp by Stefan Roese */ -#include +#include #include #include #include diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index e8a7830fc05690aad234e5647b13020715c0f7ef..52880a16fad3c4add82420278b467dc135bf4c98 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 Simon Guinot */ +#include #include #include diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 083d91b696a1cf90075baee70f708d652d7c8964..917091340009ef4054e34bd382e66542daa3512e 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -8,7 +8,7 @@ * Written-by: Prafulla Wadaskar */ -#include +#include #include #include #include diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3a2fdb5c1546a3332338fe92afd7124866d47993..22bb008745e1f616fa9cbbd16684bcf95714d816 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -8,6 +8,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/Marvell/db-88f6720/db-88f6720.c b/board/Marvell/db-88f6720/db-88f6720.c index 920421366f11db546a92c16a078fc72f6b0f5d70..26c30647fbb04e3e4b1c8656e2b644c6be63000a 100644 --- a/board/Marvell/db-88f6720/db-88f6720.c +++ b/board/Marvell/db-88f6720/db-88f6720.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index 0f92cc385bc8bf13b8de2f74fbc430491c8bfe71..122c63d11f997164407e2c06a640ad2d71c83979 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 8f8b2720107ac979461eaf7b4f03567a4a2c3404..1edc1cb6515c6be692a413217ad316c97d18d6f7 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index 6bca1f91a0a48e4949e3c2da58e7ff7aebd05a8b..9e1fdecfca4d973dc86543026df2ed4457ef7483 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -3,6 +3,7 @@ * Copyright (C) 2014 Stefan Roese */ +#include #include #include #include diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c index a7a84798a53bc51f63b778924ec44c2367742d7f..0abdca1cd2106bcdcf5b89c3008d204f8bd051a4 100644 --- a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ +#include #include #include #include diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 3812750613181616d0e08ac86e199be68ea0b2e0..d15faa1cb7ff813b09713ba4ccb056d983bc7d5a 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -8,6 +8,7 @@ * Written-by: Siddarth Gore */ +#include #include #include #include diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 7c3cea22b936b5818744d109b15697cc80578c96..ea87ded222e60b280b1cb3a3cf744ee1f825057f 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -5,6 +5,7 @@ * Written-by: Siddarth Gore */ +#include #include #include #include diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c index c1b7cc3b613c4ad0a68ee2b2c88c6ce4fa979efa..0c4f8e03b8596e301cd64a6db4d2dc86c54ec92f 100644 --- a/board/Marvell/mvebu_alleycat-5/board.c +++ b/board/Marvell/mvebu_alleycat-5/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index df3fb6d21645ee460970f7ad7b798afccf8952bc..1685b12b847858a3d1310193207242a2a423b7ee 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index 6d7042117424154cd41c8e7f287fe10f5e513c86..a8899af6e5af04331650d42db54f15f7ffc4a313 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/Marvell/octeontx2/soc-utils.c b/board/Marvell/octeontx2/soc-utils.c index 64eb95f3b400d81002ab5585ef6fa5096f7fe50a..43a19a90717ca70278596a7b35b58212b61bba04 100644 --- a/board/Marvell/octeontx2/soc-utils.c +++ b/board/Marvell/octeontx2/soc-utils.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index dda56a582b3e0aac47a3a4d12b6f7d29934e1f1b..581e2e084d6f78071eb0b78f5709b09487c47795 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -10,6 +10,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 23e761d5febf28c1dfb2d77a12794fa0c6762956..26ee39ef77f9fbd10f0ef3333d2a83ce6e3ac1c3 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -6,6 +6,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index e6ec00a9c6cc6d47ab3b4eeae1ebda0d6f912738..d72e3ef24ee61f4d360af4d652cf7d193bbfe139 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -9,6 +9,7 @@ * Marvell Semiconductor */ +#include #include #include #include diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index b2d0ad8c3f22bc9b7d73aad36b7cebfb6eb58ce1..caea89c10e0729f54bf9f5b94aa7e1dd24124943 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -12,6 +12,7 @@ * Marvell Semiconductor */ +#include #include #include #include diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c index fa7553250d1c30d5f4a8bd6d4bb3b50987b2996c..cd2bbdad1cd62c8d10ffd59b75b2a583179a457e 100644 --- a/board/Seagate/nas220/nas220.c +++ b/board/Seagate/nas220/nas220.c @@ -8,6 +8,7 @@ * Marvell Semiconductor */ +#include #include #include #include diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index 4f39757818230c9dee8d82a52e3fcd9adf79edb9..5c3f46e23f46f9925caa84dfb8268be4a5064e8b 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -5,7 +5,7 @@ * Luka Perkov */ -#include +#include #include #include #include diff --git a/board/Synology/ds414/cmd_syno.c b/board/Synology/ds414/cmd_syno.c index 29ea35e5e9107db0ac7b58d9ecda40059cd946e0..a62658a2eb6b2e18f9c9185be06be44e404f729d 100644 --- a/board/Synology/ds414/cmd_syno.c +++ b/board/Synology/ds414/cmd_syno.c @@ -5,6 +5,7 @@ * Copyright (C) 2015 Phil Sutter */ +#include #include #include #include diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index 8db810ad3eba680ca5d8b8f8641123d1acce071d..abe6f9eb5e23d76ea356ff9b7e30e5e4beb5dbc2 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Phil Sutter */ +#include #include #include #include diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 070933fb54b27c4c8bdaee23ff4fe24d6a4302be..d87fe3606f6a5c628ae912f782cfb58a9366b411 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -4,6 +4,7 @@ * Copyright 2022 Linaro */ +#include #include #include #include diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 1f7c1f25adcf969d6a980a5795e89e9295b2a692..f4257bc993d6051628729b345f3e45267beab78f 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -4,7 +4,7 @@ * Copyright 2022 Linaro */ -#include +#include #include #include #include diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 50b35db5f6cf3737eb366a3495dd2c55fe70e7b3..56b7bdb57c944347e3d94cc5e14b9f6dadca250f 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -4,6 +4,7 @@ * Copyright 2019-2023 Kococonnector GmbH */ +#include #include #include #include diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c index 93cf0744002607c2b0afc863a3aad99fd496a840..e8959ede51d9cf0daf0e67493e088937cf35d266 100644 --- a/board/advantech/imx8qm_dmsse20_a1/spl.c +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -3,7 +3,7 @@ * Copyright 2017-2018 NXP * Copyright 2019-2023 Kococonnector GmbH */ -#include +#include #include #include #include diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 3def182f2967e24fb2b444632866877da9725d3d..7f766a688bb5eaa713ef164499dd2c5c96983972 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -4,6 +4,7 @@ * Copyright (C) 2019 Oliver Graute */ +#include #include #include #include diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index 5863e335a8bcd0dbd353a6d02dc837406233e07e..d32400101fc9311cda312e7a80f283bac9ab61e3 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -2,7 +2,7 @@ /* * Copyright 2017-2018 NXP */ -#include +#include #include #include #include diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 9bbd5fd291aa32a24b73f5634e0309ddaa82bc5e..8499fc541fa70e37fb69639107f7b2be95d24773 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -4,6 +4,7 @@ * Copyright (C) 2016 George McCollister */ +#include #include #include diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index 5e6d6c6234fb4db9c277fab0cd3b9e27b99cf574..e0a7f3fa89f0c91292782ec9492120cd481c8a0a 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -4,6 +4,7 @@ * Allied Telesis */ +#include #include #include #include diff --git a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c index f30821c17963f111011cc1c5856d3d74295691d6..52b8eba92fc1ab520a3b8a51de142bf21ada30eb 100644 --- a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c +++ b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c @@ -4,6 +4,7 @@ * Allied Telesis */ +#include #include #include #include diff --git a/board/alliedtelesis/common/gpio_hog.c b/board/alliedtelesis/common/gpio_hog.c index 7da70fb4f7d6d537d2b7c177f4d09b57cf76f6e4..4aecf7e2cef7a30d4db2cbe056d94240361f51b4 100644 --- a/board/alliedtelesis/common/gpio_hog.c +++ b/board/alliedtelesis/common/gpio_hog.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Allied Telesis Labs */ +#include #include #include #include diff --git a/board/alliedtelesis/x240/x240.c b/board/alliedtelesis/x240/x240.c index c1b7cc3b613c4ad0a68ee2b2c88c6ce4fa979efa..0c4f8e03b8596e301cd64a6db4d2dc86c54ec92f 100644 --- a/board/alliedtelesis/x240/x240.c +++ b/board/alliedtelesis/x240/x240.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 65e6d48db0a6adc694fdcfc17cfcb2492621209c..80ad62c2c665dc92d2a286f3cf735b9966934ea3 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -3,7 +3,7 @@ * Copyright (C) 2017 Allied Telesis Labs */ -#include +#include #include #include #include diff --git a/board/amarula/vyasa-rk3288/vyasa-rk3288.c b/board/amarula/vyasa-rk3288/vyasa-rk3288.c index b220256c67fa12bf72590a98d20340752ec4aeab..92e0698c534be4b8fe1cfa9e3731d6d22e00c45b 100644 --- a/board/amarula/vyasa-rk3288/vyasa-rk3288.c +++ b/board/amarula/vyasa-rk3288/vyasa-rk3288.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Amarula Solutions */ +#include #include #ifndef CONFIG_TPL_BUILD diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c index ccb2f7d1bb1913d6b579338332df7727b161cea0..c2776310a3dc7da037c43589d7736c605f2c1ae2 100644 --- a/board/amlogic/beelink-s922x/beelink-s922x.c +++ b/board/amlogic/beelink-s922x/beelink-s922x.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index b770a1f8c537275a439d4bd2ee104ad3557a0b6a..010fc0df7d18c9425e57df3cea286cf752f4fea0 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -4,6 +4,7 @@ * Author: Vyacheslav Bocharov */ +#include #include #include #include diff --git a/board/amlogic/jethub-j80/jethub-j80.c b/board/amlogic/jethub-j80/jethub-j80.c index 07a08dcd17001b567b27648204bc6987e367e570..0b781666e985d3b70f0838a2ccb9012f0e81d67b 100644 --- a/board/amlogic/jethub-j80/jethub-j80.c +++ b/board/amlogic/jethub-j80/jethub-j80.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c index 8f3f2045d74d3323d4ab9650a66c51010bb8e291..bbd23e20fcdd1cd7439a3492fd4434088b1d61ed 100644 --- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c +++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c @@ -3,7 +3,7 @@ * Copyright (C) 2023 Neil Armstrong */ -#include +#include #include #include diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c index ae953d0e4bab7a8b088740cb8918caa3a03c2ece..a4bcc62174a0e88429e1ba68691ab88355a866d3 100644 --- a/board/amlogic/odroid-n2/odroid-n2.c +++ b/board/amlogic/odroid-n2/odroid-n2.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c index 3bede46b324c89c070d7d40b0363e3cb971a2d2e..754242e4a9fa112426a8079ebcf541cd6645c239 100644 --- a/board/amlogic/p200/p200.c +++ b/board/amlogic/p200/p200.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Beniamino Galvani */ +#include #include #include #include diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c index d44ebae07ddea6e86c3ab604df05c394eaaae85d..769e2735d27ecc86a7a8ebf40dd70b0fa38cc4b4 100644 --- a/board/amlogic/p201/p201.c +++ b/board/amlogic/p201/p201.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Beniamino Galvani */ +#include #include #include #include diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index ae9834c0bf8dd1eb69a066068c274337efde1715..f6e60ae3af1799a21d4fd1793e217e83eaed9a0a 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c index 0c0afccb38c25b45a86dfd99b220efb2d75bc80b..47f1566a9d3d09b44bf232267301023afaf8f500 100644 --- a/board/amlogic/q200/q200.c +++ b/board/amlogic/q200/q200.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c index 96244c9ccb11b5be05d0c6c212fb564502c0d971..06a9044fd8087cc585a0ff356b63d933e65eb277 100644 --- a/board/amlogic/s400/s400.c +++ b/board/amlogic/s400/s400.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/sei510/sei510.c b/board/amlogic/sei510/sei510.c index 1a978d1290a547f5de573e74e83ed8c077508c45..bb188c21f75f334730ee67b9c2bd7324be4cecd6 100644 --- a/board/amlogic/sei510/sei510.c +++ b/board/amlogic/sei510/sei510.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/sei610/sei610.c b/board/amlogic/sei610/sei610.c index 8a096b15bfb271b31d710a8a6a102a1ca675c6b2..6490bac9eb5576669e548d7f5e88a378ea8a81c9 100644 --- a/board/amlogic/sei610/sei610.c +++ b/board/amlogic/sei610/sei610.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c index 96244c9ccb11b5be05d0c6c212fb564502c0d971..06a9044fd8087cc585a0ff356b63d933e65eb277 100644 --- a/board/amlogic/u200/u200.c +++ b/board/amlogic/u200/u200.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index bbc2d826e05056aeb536f9cf694e3a7a7575599d..a4850364f418e89c2735086c47de54ee72741c73 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c index b84366aaeb15d71ed196b7947e161b8ebc1851e5..4199198496b1817eecf547716f5431249216d441 100644 --- a/board/amlogic/w400/w400.c +++ b/board/amlogic/w400/w400.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/board/AndesTech/ae350/Kconfig b/board/andestech/ae350/Kconfig similarity index 91% rename from board/AndesTech/ae350/Kconfig rename to board/andestech/ae350/Kconfig index a85e7d6351702861cb84ba0ff5687017adb7b197..096564b3dc166a873fc49fb30eef48d09793c6d0 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/andestech/ae350/Kconfig @@ -1,13 +1,13 @@ if TARGET_ANDES_AE350 config SYS_CPU - default "andesv5" + default "andes" config SYS_BOARD default "ae350" config SYS_VENDOR - default "AndesTech" + default "andestech" config SYS_SOC default "ae350" @@ -33,7 +33,7 @@ config SYS_FDT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select RISCV_NDS + select RISCV_ANDES select SUPPORT_SPL select BINMAN if SPL imply SMP diff --git a/board/AndesTech/ae350/MAINTAINERS b/board/andestech/ae350/MAINTAINERS similarity index 95% rename from board/AndesTech/ae350/MAINTAINERS rename to board/andestech/ae350/MAINTAINERS index a6bc90baf883c0865682b0c837c56b3a4f09fb98..31e34e610dff6f9700125542375512f2d20c5498 100644 --- a/board/AndesTech/ae350/MAINTAINERS +++ b/board/andestech/ae350/MAINTAINERS @@ -1,7 +1,7 @@ AE350 BOARD M: Rick Chen S: Maintained -F: board/AndesTech/ae350/ +F: board/andestech/ae350/ F: include/configs/ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv32_falcon_defconfig diff --git a/board/AndesTech/ae350/Makefile b/board/andestech/ae350/Makefile similarity index 100% rename from board/AndesTech/ae350/Makefile rename to board/andestech/ae350/Makefile diff --git a/board/AndesTech/ae350/ae350.c b/board/andestech/ae350/ae350.c similarity index 99% rename from board/AndesTech/ae350/ae350.c rename to board/andestech/ae350/ae350.c index 62b93b4ecba12d07bf8a2f77683d0bac9285744e..5ae5baed6ba2e57a470448f40e75f0210aa14a37 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/andestech/ae350/ae350.c @@ -99,7 +99,7 @@ void *board_fdt_blob_setup(int *err) #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init() { - /* enable v5l2 cache */ + /* enable andes-l2 cache */ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) enable_caches(); } diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8cfac9fbb3427ac902c540ae7e5dbae93bba19fb..17f37badd746072786883ae3ccfb4d72f4132848 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -9,6 +9,7 @@ * Author: Fabio Estevam */ +#include #include #include #include diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c index 5b25545cdb8839845599c81bfaadc7622c0004e3..365fdca1b76f6919dc3de7817e1f478a6f2a2666 100644 --- a/board/armadeus/opos6uldev/board.c +++ b/board/armadeus/opos6uldev/board.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Armadeus Systems */ +#include #include #include #include diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 3ad77f51949f5df93226938b4a4ff0fbd52d3212..01c80aaf9d7717f65cc64b2d5d0b1171d352a4f7 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe304ba8a18b3225c997079cb1f057bf..ad02cf16da5e0d5a430c1582106e55b51224e26f 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -16,7 +16,7 @@ * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index f4101b649e305fcb0a2156f08cdce63d9c46baed..9db5135a8ffab1fb0397bb77c85d73847ce438b3 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -16,7 +16,7 @@ * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index e1b4f49d044b8cdddf4f90865bf1eecffa16a95c..53941b5f5f2887cffc52cb09ed55f8d3a38351a8 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -4,7 +4,7 @@ * Usama Arif */ -#include +#include #include #include #include diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 6c374e25e32c367cc78461dcb73a4d4e346ead9e..763131c217e53968ce68a410059297b767cfd460 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -15,7 +15,7 @@ * ARM Ltd. * Philippe Robin, */ -#include +#include #include #include #include diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 1045c905f732d1172eb7f78703dfff390dc0f25c..e553da86e0e04feb7a1324630ded77f81d7755da 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -5,6 +5,7 @@ * Author: Liviu Dudau */ +#include #include #include #include diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0119f54f0df8ceb4785d8517780977c7fc532820..ee65a596838a768698b7aefba5cd553d09cf3d31 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -4,7 +4,7 @@ * David Feng * Sharma Bhupesh */ -#include +#include #include #include #include diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 6e505c630d1270d77b9d174a9573e48e264b1c70..f85737432b3155d81821d26aa31d9448d27069c7 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -13,6 +13,7 @@ /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ +#include #include #include #include diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index 43fcbc65513dc4bf515e8907b4f34ca1b5e414cc..43563c412793f608faeda7a44cca1ef3c26c975d 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -5,10 +5,9 @@ * modified by Wolfgang Wegner for ASTRO 5373l */ -#include +#include #include #include -#include #include #include #include diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 48aec652c4a43cd74b85d36f97aa0b63d4f6f5d0..b8e02f459031ea7cdeab06941904a130cb6abfb2 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 5d7a18379fae89c298c09a4cbb86c8341b3bf79e..eab3a130819505a6d6a7eb4a6ad96218aa0806fd 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2b0b01798eae978b9ca498118469e54b4b7ee4a0..15f20b62f6720e2298644faf0c728b0df1eb6504 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 3bd94d0889da25fa437109f2c7ec09b945d3ee57..f53c1cf612d545385c3f25fa104f811221f848f2 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index afc0c0520e1f6648930d022a1f796c0e4a4fb1f5..a3e294c88fc8988d4c677c4939932ba1369efe29 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -4,7 +4,7 @@ * Josh Wu */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 214e917381e732b24cc5ab0fe3d0aff118a19d66..11725f778b7dbca3af1b6ac56abdf6c394c663d0 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -5,7 +5,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index e5688c6cf132dae2171cd05e3da5470cfc8062b9..ab666b6be34f18085aa2d51b6616a82bb34cc284 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Atmel Corporation */ -#include +#include #include #include #include diff --git a/board/atmel/common/board.c b/board/atmel/common/board.c index 55afd43d4f32fdc136e8eb85bedbbf9f81d40bdd..c93c0e52e30d52c1a3ecd6e17fdd073f31f032ef 100644 --- a/board/atmel/common/board.c +++ b/board/atmel/common/board.c @@ -4,6 +4,7 @@ * Wenyou Yang */ +#include #include #include #include diff --git a/board/atmel/common/mac-spi-nor.c b/board/atmel/common/mac-spi-nor.c index 628f795812955690ab6a523be80d9320122b2aa1..ced27b65e63b8feb68b2537692503311bada5ab1 100644 --- a/board/atmel/common/mac-spi-nor.c +++ b/board/atmel/common/mac-spi-nor.c @@ -5,6 +5,7 @@ * Author: Tudor Ambarus */ +#include #include #include #include diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c index 97edb7a549d42d79307e046a84b3d2911db17ce2..4606008c697f1fb16df501ea84116f9a91c4c30f 100644 --- a/board/atmel/common/mac_eeprom.c +++ b/board/atmel/common/mac_eeprom.c @@ -4,7 +4,9 @@ * Wenyou Yang */ +#include #include +#include #include #include #include diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 771888205814d8e9019338d1fe10b148b8134ce4..a5049f4aad411591c276fb87f336779f86370d23 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -4,6 +4,7 @@ * Wenyou Yang */ +#include #include #include #include diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index e75043ec00f9028bf81e32244d6d38fb3eb03618..f53d359404ef2763d1d51a1a7da8e987a3399268 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -5,6 +5,7 @@ * Author: Durai Manickam KR */ +#include #include #include #include diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 2e5073f02b3e0d17e73f8ba27f491c00e135cd5e..3fbfca4acc96d7d133790e426dce55f6ab541d4b 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -5,7 +5,7 @@ * Author: Sandeep Sheriker M */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 36995a927cf15b95ed27fd1a3544ebc9b0b7c1c1..329eac7223add7eb9d4f4e4b4acb91604384be08 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -4,6 +4,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index c775d593e58c91e65a70a919600601b11fe29c54..6e41017af17ce83d00d55012625641f2eb901fd8 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -5,7 +5,7 @@ * Author: Nicolas Ferre */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01acc4953a6648711d81f41a67074515..d0679317fb2d5c37a5ef8f6ee9edf9a148831ce5 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 986da01639f94afc0208d5a6a7461aaca1c72aab..fabe492715ab055997b7d2356541c927d337f810 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -4,7 +4,7 @@ * Eugen Hristev */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 438829df82d5d2bfb40bbc20d1ab389d4aa253eb..854715ea2269bd2a6ac8ddb5d67d249dde7d5cf0 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -4,7 +4,7 @@ * Wenyou Yang */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index c8a8eb49826b6797d541e9d6b028f8b1e21d326b..aa522075691c7b07ecde3f37b60076172a6229f3 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -4,6 +4,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 54cc3c4d9003fac61d9fef74d46f71de41721e71..ce73a801e50111570ff398cc98da5c8ba153c8d9 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index f2e1242fcb0fff4d44d55211982be28fedab7f93..660a6b9d58358320b010babddc2c12fa25458844 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 09ca16ca88ce571bc7d1192873c5b2a5b7502870..780aba15ab1d4d27b49f4fec6baa403306914b2c 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 1f8b85f0614e486ca555f95524009b3bce7a819a..2226906a3b3d7b9b9c7d765eaaf46838ba40c320 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -4,7 +4,7 @@ * Bo Shen */ -#include +#include #include #include #include diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96421e2a010e080a108c2910facd5c4..33cd0903d25366c22265e771c8d23e3ff32f9fa9 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index c07115a2119527e9335b3eb05689b3ad2eb05ac8..295fd079dcf7cee5cb4a128e5e67ce06fe040941 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -4,7 +4,7 @@ * Eugen Hristev */ -#include +#include #include #include #include diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index e35bda81468113bd63ad5f3177857cf0bfd35312..29bde60228f914d61270dd1f1dd78cef06edff76 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -4,6 +4,7 @@ * Avionic Design GmbH */ +#include #include #include #include diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 4d7477237d446517620175c4fd9e1e1bd2357449..988f057a281cab446f12824a89775ef51878a544 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -6,6 +6,7 @@ * Avionic Design GmbH */ +#include #include #include #include diff --git a/board/avionic-design/tec-ng/tec-ng-spl.c b/board/avionic-design/tec-ng/tec-ng-spl.c index 250494524952b398372d0faace4ceea25737b671..6e544641833e7184f980492ac0df97f87f5be862 100644 --- a/board/avionic-design/tec-ng/tec-ng-spl.c +++ b/board/avionic-design/tec-ng/tec-ng-spl.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c index 099053235ded49f922377dd3210b6b061672054d..99fe1edfb33097288ef4adf8ccd47497e8f21f23 100644 --- a/board/beacon/beacon-rzg2m/beacon-rzg2m.c +++ b/board/beacon/beacon-rzg2m/beacon-rzg2m.c @@ -3,6 +3,7 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include #include #include diff --git a/board/beacon/imx8mm/lpddr4_timing.c b/board/beacon/imx8mm/lpddr4_timing.c index c1498dd5eaf4753c14fcf39bfce994088d0d4ec5..8e48b9d81b770d6751900c726f5fd4facc6129df 100644 --- a/board/beacon/imx8mm/lpddr4_timing.c +++ b/board/beacon/imx8mm/lpddr4_timing.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12013aa5a4da42a07d1707593f4594a563fc6bce..1632238bf5dd5f3e5a21f03226cbfc17bbbc5e8e 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index f03841e5a01ddbf15ffbaa4c18e4b2753eaa01a2..b4d46f11f98d251665c69f77027aa8b57cf4528d 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -3,6 +3,7 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include #include #include #include diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c index dd74e7c0f7559f78fe0e589d689aefdb804042be..8963a51fbba098031e614e9bb4475d241f8a8065 100644 --- a/board/beacon/imx8mp/imx8mp_beacon.c +++ b/board/beacon/imx8mp/imx8mp_beacon.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */ +#include #include #include #include diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 30d577f7e0e334446806d530c616a94e8419db73..591e8ca9ab5b27d502b8aca3ac3c53a9048ded52 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/beagle/beagle/beagle.c b/board/beagle/beagle/beagle.c index ac2f89cf213aa664ae8b7d4e4d048e39fb4eae65..847d596646e3312328e0d012037eb92c4872f672 100644 --- a/board/beagle/beagle/beagle.c +++ b/board/beagle/beagle/beagle.c @@ -12,7 +12,7 @@ * Syed Mohammed Khasim * */ -#include +#include #include #include #include diff --git a/board/beagle/beagle/led.c b/board/beagle/beagle/led.c index efbd7c1e0e3641fb5fa3468930421480ffd9b5b0..e21c0169db7160843d49e3ce885c9e5a85ded99d 100644 --- a/board/beagle/beagle/led.c +++ b/board/beagle/beagle/led.c @@ -3,6 +3,7 @@ * Copyright (c) 2010 Texas Instruments, Inc. * Jason Kridner */ +#include #include #include #include diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index 3a766728a6f718359cc7319fcdedd647c9adb7dd..e7b131836b61bc5a077c4928ef2d63d5908bfc25 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -7,6 +7,7 @@ * Copyright (C) 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c index fd28a70f4d72b9e5f8b44775463a735e10c0d1a5..bf472902562227cdf32df17eac19071d5f3bb3ab 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020_video.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -7,6 +7,7 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 3275803226a38acdabda3defa259f95a92f9494f..9b42299b080f8c4a31bd0a985935273b385db559 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -7,7 +7,7 @@ * Author: Ryan Mallon */ -#include +#include #include #include #include diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index a1a00e7ffc49cd0a4f0e8aec30db5f4863b52546..65c2f35671358f2329fca7b7397c49389aaa94ed 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -5,7 +5,7 @@ * Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ -#include +#include #include #include #include diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 41d7567ad21e1fe56ebe74d6dae0e2c62c182038..ee9e6d632ed49e9893f094843ce406be00e95e59 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -8,7 +8,7 @@ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ -#include +#include #include #include #include diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c index eab3398c4aec84c470fa40ec6574678a54288936..53850ffb8f7e7230305736e85c24efa6eee22abf 100644 --- a/board/bosch/guardian/mux.c +++ b/board/bosch/guardian/mux.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ +#include #include #include #include diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index ab688745938a4786fb72c17bcc46e6373f578028..aebdfd4dfec0753bd9683e43895afc7293847158 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -11,7 +11,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c index a2a8947a3bd86ce023f7b1d2d82a3c9f4af123f2..f19d1866c7216b59371875faa6353e71a7714db4 100644 --- a/board/bosch/shc/mux.c +++ b/board/bosch/shc/mux.c @@ -9,6 +9,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 2b0cb2361c4061205805e9f4da3fff6054c7cfd7..382c01ddf4e017c68c0610eed50c5ca520d1d444 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -4,6 +4,7 @@ * Copyright (C) 2013, Boundary Devices */ +#include #include #include #include diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index a6ced92565f98c383a930603f10c65978c721847..bcecb4d783922468eeaa3160b53c5bbb39b73ed4 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -3,6 +3,7 @@ * (C) Copyright 2022 Broadcom Ltd. */ +#include #include int board_init(void) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 45cc62936cecb0cc894f9f38595486a8c6889665..1249e45af0362b5f2e9733c8164a93205390ebf2 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -4,6 +4,7 @@ * Copyright (C) 2023 Linus Walleij */ +#include #include #include #include diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62adffe9ba0b990fc07a5f88023a0f3a..7ae6742c4be8ff487d412a18e2ffcba61aa9a59b 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -4,8 +4,8 @@ * */ +#include #include -#include #include #include #include diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index bc05aecc446dd83f4c54de89f933c5763c4a17e5..aead6f099e818ae43cd7b8c9728a4d35cc6a0769 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c index c03e390762a9d65c6cc65001cfd54495455602ea..c82eabbfbea1ec43f466d5e87a9f6e9787171e6b 100644 --- a/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c +++ b/board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index 724841b57456029ec227eb4ea142606eb3cde5f6..5b4812e129e3179d62dca64efd09cf501ccf77e1 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c index c99896873991f10646f61e4edd531dd9738aa0d6..0ebf208be82a2317e0720ca0aabebd380abf207d 100644 --- a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c +++ b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c @@ -3,6 +3,7 @@ * Copyright 2021 Collabora Ltd. */ +#include #include #include diff --git a/board/bticino/mamoj/mamoj.c b/board/bticino/mamoj/mamoj.c index 71497b8ab1e8672f8cbe584f18ec8131b9a7001b..c9da42b43bf5d393930536d458502fb9e7ce97b1 100644 --- a/board/bticino/mamoj/mamoj.c +++ b/board/bticino/mamoj/mamoj.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Jagan Teki */ +#include #include #include #include diff --git a/board/bticino/mamoj/spl.c b/board/bticino/mamoj/spl.c index 59b7c24ccc9ac6525c85ae7a1591e3a88f902045..883b7f4133b9e2a03f60373ffe748c9d48b4d131 100644 --- a/board/bticino/mamoj/spl.c +++ b/board/bticino/mamoj/spl.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Jagan Teki */ +#include #include #include #include diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 1e501a09813dbc9516d97cd9a189c783d061013e..6a866b5470d6e1fd3746c6cb047c47cb24b35a8c 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -7,6 +7,7 @@ * Marvell Semiconductor */ +#include #include #include #include diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index 5110fed31194f5596eb1e02910201beeb47d526e..8e4081b4c6dd1edc7a3f432321119efdea2c8c91 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -4,7 +4,7 @@ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. */ -#include +#include #include #include #include diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index 8e39a157ea311fb5534536ea1627d5c0dedf503d..3d31776d48419fa35f3802af2fe007c2bce9f1f4 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -7,7 +7,7 @@ * Mateusz Kulikowski */ -#include +#include #include #include #include diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index ce7afb78ed50c65746ae1283b55ea0f129ed3a84..37340fe97003aa221d5bb54f839c6a083cf5b38d 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -3,9 +3,8 @@ * (C) Copyright 2014, Cavium Inc. **/ -#include +#include #include -#include #include #include #include diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index b1a805c136093d6e83c436b068c50fb4ece0a2f3..ab20825ed36fe5c44f1a83be40cfdaa40c5fed8e 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -3,7 +3,7 @@ * (C) Copyright 2014, Cavium Inc. **/ -#include +#include #include #include #include diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c index 15b200454da7aaadd33b8020b316ab0fdb5219e2..95ee7bbfe29a03a5c11830990b4fca0d32959df8 100644 --- a/board/cei/cei-tk1-som/cei-tk1-som.c +++ b/board/cei/cei-tk1-som/cei-tk1-som.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index dd7551170d2575550d19b3272db060fa8da04cc3..e6909b3b1c5330f4de947e7025d73e7db9c73a65 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c index 091c9a59a52b66bbe63b044cc34b20fcd52c187f..bc4e984d5056a282ed5f960e59228fc89ff026ea 100644 --- a/board/cloos/imx8mm_phg/imx8mm_phg.c +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c index b8892ed2fccd80bf483db833b62a8bf55817d67e..0c3a0135a8600432e8fbd532837cf36748fcee08 100644 --- a/board/cloos/imx8mm_phg/spl.c +++ b/board/cloos/imx8mm_phg/spl.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index 48eee67129fac8f063ce24dd07a5a2f32625a204..59e1218b411a18fd5169bc0cf032c9ac351960c5 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -10,6 +10,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/cloudengines/pogo_v4/pogo_v4.c b/board/cloudengines/pogo_v4/pogo_v4.c index c8ad563f721deca364553e81db386ffea61a38f1..61ce0d59c77e3d3a059fd96a3bfbf6c0a7ef4c25 100644 --- a/board/cloudengines/pogo_v4/pogo_v4.c +++ b/board/cloudengines/pogo_v4/pogo_v4.c @@ -11,6 +11,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 774aa82b57feda4e6cb081a158240873fae1f638..69a9df942311949cc6712be30ede9712aea7ba77 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 157b71da85e80b426b9979723418ea4e1183f41a..8416af163ad1c194732e3e0d7c6ed75e8e2e2f6b 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -4,17 +4,13 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include -#include -#include #include -#include #include -#include #define PHYS_FLASH_1 CFG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 7853c4d024a35fa17668518e02dcf9e108df6b05..af19a658b542133054a3114940b6c38bd0cdf02b 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -7,7 +7,7 @@ * Author: Uri Mashiach */ -#include +#include #include #include #include diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c index ae8e834662071e1c28e786f5d1d4709aca1d683a..40ba0f7a96056ee9f495457785e303b156920789 100644 --- a/board/compulab/cl-som-imx7/common.c +++ b/board/compulab/cl-som-imx7/common.c @@ -7,6 +7,7 @@ * Author: Uri Mashiach */ +#include #include #include #include "common.h" diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c index 25123ee145a647d0a99677cd60b7b10b4556d451..18f16a48738c39024f1acb2421c4247abcaafab5 100644 --- a/board/compulab/cl-som-imx7/mux.c +++ b/board/compulab/cl-som-imx7/mux.c @@ -7,7 +7,7 @@ * Author: Uri Mashiach */ -#include +#include #include #include diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c index 9b6bbb974da743756429ca410add6673675e69cc..98c3b831f1e1aca28d3968c8e790737dacef4c7d 100644 --- a/board/compulab/cl-som-imx7/spl.c +++ b/board/compulab/cl-som-imx7/spl.c @@ -7,6 +7,7 @@ * Author: Uri Mashiach */ +#include #include #include #include diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 4a6cc3e56308693ce4d2204b1cdc97a9327f1e4c..7bce09e432c045f4950dc27c97d807ce444f7ceb 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -7,7 +7,7 @@ * Author: Nikita Kiryanov */ -#include +#include #include #include #include diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c index a71861b1731b3efaf562e0d5b4dafe4fb95032b7..ed8c7a3bf5f870c13530f704d27e1f74995a0e99 100644 --- a/board/compulab/cm_fx6/common.c +++ b/board/compulab/cm_fx6/common.c @@ -7,6 +7,7 @@ * Author: Nikita Kiryanov */ +#include #include #include #include diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index b11bf2d28c68da5de9b29d1d1f77e10c20bd786b..079f196200e585756e3fc1800699e2bdca9b62d4 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -7,6 +7,7 @@ * Author: Nikita Kiryanov */ +#include #include #include #include diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index 181581926c37f5cbec3444b21c304f7186839c4b..5df378a62e3c293e6d565c67fd33c8d679d36aa1 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Compulab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/cm_t43/mux.c b/board/compulab/cm_t43/mux.c index f10910565d500a0c72e96cbf740a1ab825170634..778ea05e84cb699372bebaa3c7e9904cdfeb853e 100644 --- a/board/compulab/cm_t43/mux.c +++ b/board/compulab/cm_t43/mux.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Compulab, Ltd. */ +#include #include #include #include "board.h" diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index 212bfeb5c307b5ffe198e528ae7be7b9eb7289c5..a6223a477fef689f4dcecfae15f38f5190965102 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Compulab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c index 6ffebe6bdb413a6d863556907b9e682264e612ea..528c97df19a4cdf1c82adef340cf7394fdd5ad04 100644 --- a/board/compulab/common/common.c +++ b/board/compulab/common/common.c @@ -5,6 +5,7 @@ * Authors: Igor Grinberg */ +#include #include #include #include diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index efdaf342d5c31be4ac2cdeb728615885946f31dc..c4b257f851d664ae451c9fad5f6c5a8bf9f5d19b 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -6,13 +6,13 @@ * Igor Grinberg */ +#include +#include #include -#include #include #include #include #include -#include #include "eeprom.h" #define EEPROM_LAYOUT_VER_OFFSET 44 diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c index 411fc4943bacb579d538e859baf2fc6d8c3fafa3..f0d365272c1bed56bae660a608528f12f908c4ca 100644 --- a/board/compulab/common/omap3_smc911x.c +++ b/board/compulab/common/omap3_smc911x.c @@ -5,6 +5,7 @@ * Authors: Igor Grinberg */ +#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 99d3bf3af3bc88cc518a55864ea1e2337cd8ed55..b230478b611aa52be346014befcc04af96c4b7de 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c index efcc95c739fd60354e446bb30584a81e3cab5559..9019a1f2035cd8dfd42a92b99edcbe0485aa9f3c 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c index 67f59ed9407f98883156c2ae06656858a334e2f8..5141c04f12dc89bb24155934838072e8aa1e7d7b 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c index 273ee89c0bc692e9d7802c51e02ab7153b749ad4..2334722497db4df9a4104da5775e52cd129f9d7d 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c index 1243800b32414ba87bfad52866ad2d795e2f8618..e65445e0155906b7772f7def3e90dd0ea83e253d 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c index 1256848f9a982a40bf1fbc460eb3d3ec65a84c3a..90cc33a6e4605f4f1eb9284feee1882a3acd3b08 100644 --- a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* (C) Copyright 2019 CompuLab, Ltd. */ -#include +#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index ba15873414283b4c334bb9bec5ff03a052706696..af070ec315c4d1a342e99fa2bfda7b251aed8fcc 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -4,6 +4,7 @@ * Copyright 2020 Linaro */ +#include #include #include #include diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 6d9af2538b630a0939d557ab35368b803dfe2fb9..19c1acd8a5254da7bcd8348da2e7cec62cca574f 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -4,6 +4,7 @@ * Copyright 2020 Linaro */ +#include #include #include #include diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index af05c0c0f059a75edcf59269f255b53a264f76ef..21ff0cda7f70ac47ef85b1b99eeb9ea4dde89e3c 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c index 64282ae9dc7732165e5c0ea309782ba2d3ef9dc2..1b765b113743f48d9eb40032dbde0947877a2e18 100644 --- a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c +++ b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c @@ -4,7 +4,7 @@ * Copyright (C) 2021-2023 Conclusive Engineering Sp. z o. o. */ -#include +#include #include #include #include diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 99c33a1943e0d6992f6f6f8cee20bc819e4c02c4..d8e5b1d6963341426e5b9327874843f343f4a313 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -3,7 +3,7 @@ * Copyright 2018 congatec AG * Copyright (C) 2019 Oliver Graute */ -#include +#include #include #include #include diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c index 242e794981b7ebf320f31f876925144c2cbd53ce..b432ce27459f60e3773a690880a60a0c136d26a8 100644 --- a/board/congatec/cgtqmx8/spl.c +++ b/board/congatec/cgtqmx8/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c index 74a189ab4d7f4d2920744f57db6c79b1d6e57128..bb7a3d4a9aa03fe3a3bb27f41a8c6ae875f2b0c9 100644 --- a/board/congatec/common/mmc.c +++ b/board/congatec/common/mmc.c @@ -4,8 +4,7 @@ * Copyright 2018 NXP * */ - -#include +#include #include #include #include diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 4197e88fb6ff2a7f3a555f52bf07973b42b4741f..315b6dc5429573001c1eb48e9f7b7e20bef414c3 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index f2ca10767681d83ecc5e10868d8586421b2c7901..e58dce37477feed4b4ab8625e4aa0461a39244dd 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index c07e0eae4e9d21b40319062ca14b171dc6b6768b..fdfa3affc3b134378ab4b33f377ef7191dacfa4a 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -3,7 +3,7 @@ * (C) Copyright 2020 - Cortina Access Inc. * */ -#include +#include #include #include #include diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c index ec13d9a7ed7dee7283057bb3a06debd6d673e844..ef304124564950b77ad23116b4d2d2a4430a87db 100644 --- a/board/cssi/cmpcpro/cmpcpro.c +++ b/board/cssi/cmpcpro/cmpcpro.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 3bbde9808d20c3f03e6deda648b0c3f30b86f0c8..8ebfe4c601890307df5cbebd3a9da16a95d5c8ea 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -9,6 +9,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index b4d74a8fd8bd8113654afd1cf35728dca12df496..4ece82c73039211889a92ba663683c386884d024 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 339702e8392774e54d2ea7075138f967f485c0aa..bfb2bddc1d1f8cdd4523ce562819bf97371c0cb6 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index 17aafd719c9d444a23b63cc0f48e89a82320e72a..4a9c62fb86fc3fa5d41e5273e802438b35a39fb0 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index 138acd36ad2407570760a4676a174738119c1d08..f0f373aa2800ea8d5357baf240a57eb9e33ed847 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index c1935898533297c165569eafa64ecefa62da8e87..cc2d253e391ed6636807c49fcc5307d92992e9cd 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 0011c8285237590959611a3fd61ceae6497cde93..05053a87a5a926f255390dd8a31342b8958d5ebd 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 607e05ad9ae453c6a2f09055c3913048929be511..9738e2bd9c77a967ebaeb0ff85dd0b2aaa067050 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c index 907cc985d7a9e6b61c511b5bf705e87bf6bd9cb0..87506a77a17e5b274ae18c13c01dbc0eb36dc81f 100644 --- a/board/dfi/dfi-bt700/dfi-bt700.c +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 32c50b4f0f59c53e430dc648bc7cdd6e272c67e9..34094a020b0754ffef1340a34f3991b5fbdca6d6 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -4,6 +4,7 @@ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ +#include #include #include #include diff --git a/board/dhelectronics/common/dh_imx.c b/board/dhelectronics/common/dh_imx.c index 3d6487dd0d8c7d8757490c274c063268083bcb1f..7f451bad59c7f8b6cd0ee5b194b60e1acadbaccd 100644 --- a/board/dhelectronics/common/dh_imx.c +++ b/board/dhelectronics/common/dh_imx.c @@ -4,9 +4,9 @@ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner */ -#include #include #include +#include #include #include "dh_imx.h" diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index c8dd30dfeaf532e32cb9f0cadd2b12a44625b4b7..0676587c38a1058807c36328f3bea7ab1dc05629 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -5,7 +5,9 @@ * Copyright (C) 2017 Marek Vasut */ +#include #include +#include #include #include #include diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 3a5495ea18e3a66448166b66616bb07c881b24c1..e6d5657c62d00f52a00cae34b207bab851f61bed 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -5,6 +5,7 @@ * Copyright (C) 2017 Marek Vasut */ +#include #include #include #include diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c index f6db9f678042f100f2401ae077f5a426736a297b..44456da681ce56183cdeac0c65b729e82b5b387a 100644 --- a/board/dhelectronics/dh_imx8mp/common.c +++ b/board/dhelectronics/dh_imx8mp/common.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index c635735d89cb92d748014a39c974290ebd28d1b3..ff2c0e872151902372a7a3cc3238e318d4cd925e 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 714f846521e0b9308c9fbacc039df36f773c3409..7d228da8e5b73181adf28754e0cc2f0b6a14844a 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -3,6 +3,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 20c9d70737ec6d54d756560a2492bf8ac0395f99..22af423536d5a016ca5642d099ff2eaef9c57208 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 222e5facf434cb78e315069044f6f7e6f8532e87..2b03e4891d92f0d3d1565e9fc169c0c055014b80 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include diff --git a/board/ea/mx7ulp_com/mx7ulp_com.c b/board/ea/mx7ulp_com/mx7ulp_com.c index 8f78937e097300e727b6d0d2ccf4232d95e6395a..cd9591a9e3243156bf3c021f030660bb3aab25bf 100644 --- a/board/ea/mx7ulp_com/mx7ulp_com.c +++ b/board/ea/mx7ulp_com/mx7ulp_com.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 2ad256f8635791772b6c336445af8ce4af49935e..3a52e4ae675fd1c051b6c56a4a7517309da6bfb2 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -9,7 +9,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index f306a134031599c0121510f80d1754eb74b5ad7b..c97927e5cfe9ec4d3eb2ee79f2ed236b130c9db9 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -7,7 +7,7 @@ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/efi/efi-x86_payload/payload.c b/board/efi/efi-x86_payload/payload.c index d7d1e53e911cda86bac69ee817fbd02e39cca6d2..5d4492cdc77acc5c6c71a90a41c9ffda62f075b6 100644 --- a/board/efi/efi-x86_payload/payload.c +++ b/board/efi/efi-x86_payload/payload.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 64e341c3779c6b08fd2fc994970f11a897412ddc..9953df017e1906d461f2bbafb39197960406277e 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -52,7 +52,7 @@ * http://www.ethernut.de/ */ -#include +#include #include #include #include diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c index 42e1914a8759f38ce5f00a0e7c0a708931ebfb6e..81f1abf2fad9ffd7d782a82e609709b2b5b4a8af 100644 --- a/board/egnite/ethernut5/ethernut5_pwrman.c +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -31,8 +31,8 @@ * For additional information visit the project home page at * http://www.ethernut.de/ */ +#include #include -#include #include #include #include diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5aa47d5b4d158dd111dcd9d276dac25..10398e7f71264ee11ab3993be315d48ebc23cee7 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -4,6 +4,7 @@ * Authors: Andy Yan */ +#include #include #include #include diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c index 896350140d61c64cab5db1eb71092d94975d6c1e..a3c23bdfb64e0fb25b9379607efcaec841bbf133 100644 --- a/board/embest/mx6boards/mx6boards.c +++ b/board/embest/mx6boards/mx6boards.c @@ -12,6 +12,7 @@ * Copyright (C) 2013 Jon Nettleton . */ +#include #include #include #include diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 393fcaeb7422d9ca206061c7e5209728601fc695..7e7d84f6c00ffcf49181cf9b9ab18d6a5890e3e8 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Linaro Limited */ +#include #include #include #include diff --git a/board/emulation/common/qemu_mtdparts.c b/board/emulation/common/qemu_mtdparts.c index c1501276789c6e353013f347dba42cfb521e031f..60212e97acf6535a699b2f96e4a5a3a0a37f5ec8 100644 --- a/board/emulation/common/qemu_mtdparts.c +++ b/board/emulation/common/qemu_mtdparts.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Linaro Limited */ +#include #include #include diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 6095cb02b23f17502ab87a755942635fba78f133..ecfd19f1a7eddfd101608028c9670993d7936585 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -3,7 +3,7 @@ * Copyright (c) 2017 Tuomas Tynkkynen */ -#include +#include #include #include #include diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 58e5d5eb942708152fa7d124dad1648e29ce50c5..221361691c15b9cf987b0c8ae48873fb18b27427 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -4,7 +4,7 @@ * Copyright (C) 2021, Bin Meng */ -#include +#include #include #include #include diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index e5193e31e37e485041865ec7bf5fb9ffc58197ea..173245b40e3ca0167cd55545d3c71dfd6a1d2023 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index 8e0477c7a6e47b53e3f758572209a2726dca28e7..df9149e0d6d857fa7276ec39d1868df60d7f1d56 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 8bc80ee6baa84c26f23248f6cc28a11bb0a134d5..f1ccdc334363b45e6d0f7431bb98a311b7a4f584 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/board/engicam/imx6q/imx6q.c b/board/engicam/imx6q/imx6q.c index d799fe6526af9733a503575a6d84b7837869a6e3..e6c888fcfde114ee20c147259124a17780d9359e 100644 --- a/board/engicam/imx6q/imx6q.c +++ b/board/engicam/imx6q/imx6q.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include diff --git a/board/engicam/imx6ul/imx6ul.c b/board/engicam/imx6ul/imx6ul.c index 24d654445dbd8569a6b85b1d1fbd6b69b0c1ca46..412d6c302e88e5ab56f4cf3d6e1137c336adc21f 100644 --- a/board/engicam/imx6ul/imx6ul.c +++ b/board/engicam/imx6ul/imx6ul.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c index 236337546aeea42bf14006dbc32f9ba8ecc4a6b7..320388faae3e074ab956d1ddce13c0bd139c0ab3 100644 --- a/board/engicam/imx8mm/icore_mx8mm.c +++ b/board/engicam/imx8mm/icore_mx8mm.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include diff --git a/board/engicam/imx8mm/lpddr4_timing.c b/board/engicam/imx8mm/lpddr4_timing.c index fcd45c158f2271c86e116d50512844acbe5b68e4..821212740bcc70a1733b5d707116f3ce9502fe45 100644 --- a/board/engicam/imx8mm/lpddr4_timing.c +++ b/board/engicam/imx8mm/lpddr4_timing.c @@ -6,6 +6,7 @@ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga */ +#include #include #include diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index d51ae241e85cd5fd0646dba2f2a5a6ab607eab57..af9044a3c2b036d5a5e04ae869796f1899b109e6 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -5,6 +5,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index e2ed70caa43a60a49c5c16fcff40464cd7d3b3e7..5f820cc8dd70164d5c74202e42e527278f8794e4 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -8,6 +8,7 @@ * Jagan Teki */ +#include #include #include #include diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index cd31aa6041d1397fb5b465d174f0c2c52f5596d3..36b83aace392cead37fb16ac424e510af3f4d046 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -8,6 +8,7 @@ * Jagan Teki */ +#include #include #include #include diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index bb2bd446aa8c42ae628e4c9151cb1ab7cd4788ad..2b7779cc01dd3b6424f78bbdff2d6fab7e8049f1 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -5,7 +5,7 @@ * Copyright (C) 2020 Amarula Solutions(India) */ -#include +#include /* board early initialisation in board_f: need to use global variable */ static u32 opp_voltage_mv __section(".data"); diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index bc2af66d8e964143f1f2330f07903855598a1fc7..5223e9bae8d7733b0f3f454cef44126be602ce83 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -6,6 +6,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1d4f2d615997f59cad475ba8df5fa7..9e36210422411704db57f5d30f5b945ef129ebc1 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -9,7 +9,7 @@ * esd electronic system design gmbh */ -#include +#include #include #include #include diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 8e67ab4b13273c04d8c48827285c740a9212877d..95d8b00924d8a39138fabda7866f9a26d82df690 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include #include #include #include diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index 404bdc632bbc7b31c034b4a783a5bc29ac834aa4..af00250e118d427f91e8226c24b5fe5fb623ce11 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index a149e4fe822ecea57bad0318929f79150078f1b0..590519b32af2a812ba05c7eaed95d2944421845c 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index 6f66ed6851d4095823d418fc53c622eb19df5db4..e7e07fff86c337145dccc237cc80dda12c2fc361 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -4,9 +4,8 @@ */ -#include +#include #include -#include /* * CADMUS Board System Registers diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 56b01e3f51f046ed30803ff76b9afcd31006d674..dc2d62850d19713adbcbbfec0d53650ff3d6e072 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -3,6 +3,7 @@ * Copyright 2004 Freescale Semiconductor. */ +#include #include #include #include "cadmus.h" diff --git a/board/freescale/common/cds_via.c b/board/freescale/common/cds_via.c index 6fc3a21780f6c2eefeac6ed9b08a129a6344eba1..6184472b1658d34996d2f27d06d1b0c808884c5e 100644 --- a/board/freescale/common/cds_via.c +++ b/board/freescale/common/cds_via.c @@ -3,6 +3,7 @@ * Copyright 2006 Freescale Semiconductor. */ +#include #include /* Config the VIA chip */ diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index d4192e5ab5218efde0f33728da0bbcbfdf3c9add..6c096266b4840eb9a0450260fd8e84116ce705cc 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -3,10 +3,10 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include -#include int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c index 50252bb5007f667bd53115922b9c8d06e76f7f61..9a75c5a09dd17749a84cbca6e240c91198f71fe0 100644 --- a/board/freescale/common/emc2305.c +++ b/board/freescale/common/emc2305.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 650ecc7b44022a385bcbafe651db61cefe2899d0..358303108d8dc7531d55947377553efeee42a43b 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -3,6 +3,7 @@ * Copyright 2011-2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 27a33924c84d1686a0e6dfb70f04df53dee91ea1..87ed814d6a2a3018b2ceaa05531fda6a6c933fe7 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -4,7 +4,7 @@ * Copyright 2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index e03434dcdfed09729a41a86a9a593e22fca8b35b..bfe6357b0d603e16ecbae571e9c11f0fc52fc20c 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -4,7 +4,7 @@ * Copyright 2021-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c index 20705ecc8e4669e595847ab978f15cfbb7bd7249..119ed3c6171bff594423b72f3fd24ec0141930ab 100644 --- a/board/freescale/common/i2c_common.c +++ b/board/freescale/common/i2c_common.c @@ -5,7 +5,7 @@ * Copyright 2021 Microsoft Corporation */ -#include +#include #include #include "i2c_common.h" diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c index 89151ccaf06012b3a6b25a733e81d5b3bcb550c0..d40b34f10397eeba1f9b9342e109420e50b3cec0 100644 --- a/board/freescale/common/i2c_mux.c +++ b/board/freescale/common/i2c_mux.c @@ -5,9 +5,8 @@ * Copyright 2021 Microsoft Corporation */ -#include +#include #include -#include #include "i2c_common.h" #include "i2c_mux.h" diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index af30faa0c5feb102bf500cb1fa4abff9afb773fa..5f95571d24cc0e6879ba5852cedf2c94864ed644 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index bf76274c43ca4a5399aff6ececb3071a32235089..f754cf42fd38949464d978136962fae492a1566c 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor */ -#include +#include #include #include diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c index cf14b29a3ec1f3f88483da346dfcffa3b2ab953c..d6b4c65a3c0856e50f360e64b365e40023c1ae44 100644 --- a/board/freescale/common/mc34vr500.c +++ b/board/freescale/common/mc34vr500.c @@ -4,6 +4,7 @@ * Hou Zhiqiang */ +#include #include #include #include diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c index 00e4f3675fe4cac8bf4feebbd8b12025cf606686..8cd5079f962df8bcbf33056eb5e975913e1f4445 100644 --- a/board/freescale/common/mmc.c +++ b/board/freescale/common/mmc.c @@ -4,8 +4,8 @@ * Copyright 2018-2022 NXP */ +#include #include -#include #include #include #include diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 74c345807e64128a7efa12db09425f0edc2f06b0..7be1ccee6383f6c436858ad93018f5f1287ff7ad 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -29,6 +29,7 @@ * boot from the alternate bank. */ +#include #include #include diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c46e87f4cceed989bcfbd9afdfedcfc11eb680d2..a95d15c1ef39b908ec3ad8a5f35179a0c9807417 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor */ -#include +#include #include #include #include diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 83818d6d84794a78f92dba5493ada3360b9f4f3d..1a1e9343d23b843f3ca74170894a2cd2a935ae91 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index cebdedfa4a7a3070936a7ecf525379a72327822b..1a2d9cbfc0ce02674f29454f7078a102bd300489 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -6,9 +6,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 0d7a94fd232f81ac595bd464096971d716b7b8b6..a9288820b2ebaa7047cb5e5f8875d66cc9c21c35 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 6400ac052454a1c0ba2287ba2e6a0d0c80edb07b..da2c1de078b74cad9c9211f15c26c14a47a1a313 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -7,7 +7,7 @@ * This file provides support for the QIXIS of some Freescale reference boards. */ -#include +#include #include #include #include diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index 5ee730cefd044ba9ee187bde7657a83ff5bcc767..a1c7a94a90e347c58c3e3b032e53870d6b83b15b 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -3,6 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ +#include #include #include diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ec3c9e37222a550666fbf8ed2f1ac4a8c274d261..64139d4659f24a3d5f132c73f54fe9822f0a2d17 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -6,6 +6,7 @@ * Timur Tabi (timur@freescale.com) */ +#include #include #include #include diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 84cb43fad56a457c2747dbe5e747e992db8916a7..fc5d400cfe18d0e49a444c8fc15513a869a4c160 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -5,13 +5,12 @@ * Copyright 2020 Stephen Carlson */ -#include +#include #include #include #include #include #include -#include #include #ifdef CONFIG_FSL_LSCH2 #include diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index 4c4436af3b1dd7e796e48458488d2df4e60c182a..e0975fcda7050942a0b764363fa4cd2f5453d982 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index cd251d274ff68a4e70f0449b4e72f8ec479dace2..35437811d9df7c8e343dbf9057412f04d6d78fe6 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -3,6 +3,7 @@ * Copyright 2019, 2021 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index 6b6fb0a7dd2178a20d9869a1b478d5a8b5124ad8..e35d505aea97236554eb9437c6a5dc0fd18c49ab 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 231b9289eead9467bd77207dd81ac7530772280a..dd54fa9b6085bb288c2782395f032c9ee754d48d 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 12da1b2abfbb7d1a22a2910f7f1d7ebce470bf0a..9dd2cbc799c3181cf4b3ea899ab7cc52b8c247e5 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index ab920a4539cdf9a77607e1eba5640fa8a6233436..e577e4d9ccaa9a79e8fd09967dc7781259678094 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index e9559e3d843aaac7cbf08ce4b65f366fb3209cca..46bc7f8591cbf850d6ad85d5c4e5cf42b15c278d 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c index 5d8f2803be67f56db518fb5e8183355af3c3ddd5..ec68edaf6905b51c064b83f84782dffb2cf67ddc 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index a346305c8633fedc760ff9361dd34eac49da07c6..818cdd615eb9a3c28c1a5229e29596a1e4df9667 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index 72527f774ca93edc6cd62c9c9e3d265d7dd586e4..2b209c8886f2c15d853aa8ed7502d93aecb5bfa9 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index ad786833309104756b7f64ec252f302739582b53..17fd437116d35da1544163e13414ab19b76ebad6 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index adb9556a021c89b9c37d081c6b6909e32338ee00..833bee55462d1757e4dda413e99df10cf8e7ffc4 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index 05e3c0a2ff26ab99f1c8933771d308bccc8f7fec..462c43ceebc75b864d2001c10dd01e77846d58d4 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 0af6106726378ffd6e34251ccdf94c937037af9e..dd04d5925a009067bf7c5aad09838585a982eeef 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index d123b21b72251a402a0e36bcf0fbc073b4d721f7..c49b5be4762052ca7754471779e4032632e6161b 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index 341831a7d30d5f7c5063a2f07a035c3b67b4340e..c54dc9d05c5c493c3c604b6841d10deacc815f57 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -3,6 +3,7 @@ * Copyright 2022 NXP */ +#include #include #include #include diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index e5807134bb2357016c186fc49323372d15e94d96..6d5e110b27764665cbf80eb923a25086449862a3 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -3,6 +3,7 @@ * Copyright 2022 NXP */ +#include #include #include #include diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c index 42a0a67ae933fbeb2594916937b30dcec38172b4..785da604b964077437b93a46dca6bd9e19b9736e 100644 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ b/board/freescale/imxrt1020-evk/imxrt1020-evk.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c index 46a644908e9d0f46c9016fcb970a149362d5b34b..4cc3defc8828831c16a978a2bdf8a060686aea8f 100644 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c index e10b8830ec6ad5d820077ec58888bbfed412bd46..4b82ee5e9ce447add8f17afee620256f138b6d72 100644 --- a/board/freescale/imxrt1170-evk/imxrt1170-evk.c +++ b/board/freescale/imxrt1170-evk/imxrt1170-evk.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c index c431e5e611bb521c9862f9ad1bf8a10d960e7c3f..d2df9351eaccd49637118fb921f383b6cc928d16 100644 --- a/board/freescale/ls1012afrdm/eth.c +++ b/board/freescale/ls1012afrdm/eth.c @@ -4,6 +4,7 @@ * Copyright 2017 NXP */ +#include #include #include #include diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index dae2cf097bc0cddce057c087b6818d3e651dab30..271072bf7a1cb3c5750328be30799c0203f7dd7d 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -3,7 +3,7 @@ * Copyright 2017-2018, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c index d5e87c5393b8fc6a5c98219130189ad5df873efe..38267acedde1817adad2cb92ca02368200844189 100644 --- a/board/freescale/ls1012aqds/eth.c +++ b/board/freescale/ls1012aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 7d56eb0117d4a33b3e7ff872d321de6f2350bc0e..a5ea8d634edca221a0772a3e8da72736a088e3e9 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 71cb2988a56dbcff460a096795a8bf3c032690d6..5c661274987cd077cc2c3612e00cc178827cfad8 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 7f8001b4981f290dc6a43cb6f07ed332508665ee..18f92089caef1b4a3f8821b5b583cd7d79059abe 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 7abc41269330d4e8cc4287fd0e0ca16c6ead5727..d6f22bd6a2a3c0d406174eb0f77a8797bc8cce5a 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 5b0f23688f0bf6ddd711b897765480b24c750ac5..4e70acc5a0cc83b0c7c8617f5b69242622e4ce50 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c index c406f2436d1ae6db1837357311b79b92244fd086..3e976da6b305805fb8a09ee7312af32a6aa30e6c 100644 --- a/board/freescale/ls1028a/ddr.c +++ b/board/freescale/ls1028a/ddr.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index e01b5a8c2eb0dc5cb56c27af284e39ee1b33f37d..7f181ab3dfb793887379c53538c9c79c8233a855 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -3,7 +3,7 @@ * Copyright 2019-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 2a9717df616ca8eacc580d5c31e75182a4756ee0..23947bdb84c97ccb161209ba3d46d05db083ef88 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -3,6 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include #include #include #ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 5a8ca27b3278fef2f35d31c8422a8c4b3b8d11f5..cd1f83e3d0686b4f278ccb4f20bfb4bc5501d8cd 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fdf011efc5bdac8e94c5b6d92c4a76add1c3e669..b87da41e40831fc07a19deb2fb84774da4daa6fa 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -4,7 +4,7 @@ * Copyright 2019-2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index bda2f3ac3a69c8c06e9a159639f748c1b19f40d4..9db3aa58605972e2d930d26fd9acd65e5fb82453 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -5,7 +5,7 @@ * Freescale LS1043ARDB board-specific CPLD controlling supports. */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 187925e981a5f51892037ea4186223459ed2d6d1..4d2fce384121772ad2389534f19c5a71542bc68e 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index cacc49c0584d46925e82aa113aa640b7d357c5f9..cc95214c4e3f9f3dd086a98e5a6556325d109b98 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c index b08caee1d97dda19404aa7994f35b467c78cd3db..256397b52b6502c70c0356803d48c697e4583502 100644 --- a/board/freescale/ls1046afrwy/ddr.c +++ b/board/freescale/ls1046afrwy/ddr.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c index 8efc7f68424ce923835da3573a031fa93899b967..d1a2bfe188554ea873b71215c0c5043dd6519301 100644 --- a/board/freescale/ls1046afrwy/eth.c +++ b/board/freescale/ls1046afrwy/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2019 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0cce6192d2d46c981051906fe5fe25..899c22a367e6b2b018622fad35611bb13ba47cf5 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -3,7 +3,7 @@ * Copyright 2019, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index ac1b60497216e9bfd598250e15155f4c4f75b9dd..9a96de2717862e5b81101e22359279cd2f167f09 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -3,6 +3,7 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ +#include #include #include #ifdef CONFIG_FSL_DEEP_SLEEP diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index cd3500c2e9600644d7571c9400f229b557cff328..bbf8b8c2bee5516cfb09bf71b3361d0da8d3fa3e 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -4,7 +4,7 @@ * Copyright 2018-2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index a83b2170651987dd7e15e9c02baa8c6fea169ba3..2faac54a0e235f422d2c086859247506645c34d7 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -4,7 +4,7 @@ * Copyright 2019-2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 7f8ca2e857fdf0fa336404459f64070cfba09389..ee19d4ff8aab14b224212991a14389f4690648df 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -5,7 +5,7 @@ * Freescale LS1046ARDB board-specific CPLD controlling supports. */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index 68353022e7dd93a29a430ecfa1a7e22c4da0d8f1..befb556bd30bfacd5d5357a9434529dffcb87812 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index fee8e0e21d44991522e824bd3769c5c12a20f6c6..bbc22a3cdf4a247b21642d98df9293065b585d0d 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -2,7 +2,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 0492f0a8c0ae7ce919ed94e90790f8d3595ca7fa..26e69db55f74bfea916d965c69efe7e4342d5827 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index d2e239c4d61504b6432361d26f41cc581865118f..9e0941cc9d6e48abf8e0627c82f002a3078ce451 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -3,6 +3,7 @@ * Copyright 2017 NXP */ +#include #include #include #include diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 58951f2bb2aad91276e2dfd62d94309135dc81fb..98a91c48adb0370c5e1fd4d6faaf8c7a4da5c52d 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -2,7 +2,7 @@ /* * Copyright 2017-2022 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 2986ffb7a820925c6cb553af913675c78389efc6..2767d058cc963b9231b5a2e3596f070220b03d69 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -3,6 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 4c8d0706688f7dc43a2d3356ca0a598d5ef926e7..5c94c83121b5af3819c83b6ab6054436b0faf5f8 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index ec34b42e619ad2e712e5cec366a0b4e3fd6baa48..07fa847333243c66334588b85487940fc4787a80 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 6f824f57c478496e93e753e2336328edcd1934e9..5c30de83d8417050319d7ff823f828d503656ac4 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor * Copyright 2017, 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c index 637e43a22beeb8be7a3a15615e9b5b72b3c6cc58..7ab7a9e6ca830d09217111266fc483bd7afd2643 100644 --- a/board/freescale/lx2160a/ddr.c +++ b/board/freescale/lx2160a/ddr.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index 90e7c9100e1211240168877a8c1d08afe51eeac6..c5dfefe1f3425a6b1a22faf1b071d16271aa63be 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 3aa984dab8e73e294f30a4f308a42d46263ecc17..b3187a14214a4a163337b07964dbabc4b77a9f3c 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -3,7 +3,7 @@ * Copyright 2018-2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index b202b8094d923d1af5694a6c18144b2a106d8f79..6125c9e13aa35dd4e157600130321ae40cf2edb3 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index 65cde56fb2d7ae8b6d2ef851d5a369c2e2a156c8..44161a0b0a1c441753e3f95850f762d50cd2111b 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index 717dc087e02b5ca56e618afe94a0cddbf6229257..d67db24d588320f88a8183261359eb38e4fd21ce 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index 334518a4bc9d49245f9928ecdf7e256f04b6de0e..eeb9cfd31259e632b08c31924194f398c17cc712 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -7,11 +7,10 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include +#include #include #include #include -#include #include diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index d0b01f81745f3482c9e0806e701f78e45828a40f..c1cff52fb3db1bc8c35f9cc357e73237859edebf 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -7,7 +7,7 @@ * Hayden Fraser (Hayden.Fraser@freescale.com) */ -#include +#include #include #include #include diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index d1286badc61cba5b5a4cb906477df509f3ccd361..3c20a23385c5dcf6395e9179544419479bc35406 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -6,7 +6,7 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ -#include +#include #include #include #include diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index e1d94fc9a3e263488fa4c68e8dcd6d1d5d877997..00fa35ca5f71b8efcd941a94cc45066a2e171638 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -8,7 +8,7 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ -#include +#include #include #include #include diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index 81da6e2abd46a9d8ef48e59c7ddb58d2d5fbab27..53e0f202101ce0eeaeb290a7ca0af4113a4d2a27 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index 196d56dc17d35b5a312d2a0d71bd5d35dc15faa5..76ebc0ab8dcd8b34332d29f7758e7c18155f6153 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 26d5f3bf58ce15312ecafef4614826038f258d2d..b278dbfb4852443308b9bae08bb84039de9a9899 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index a250d61ef3685cdf0943a37e9336a0db3cd1d039..d921eef8b6759f9591b76d34f48f707903755f70 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -8,6 +8,7 @@ */ #include +#include #include #include diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index d6fdf41bab47ac09ef47cf5227e71c53980b230b..0e9eec316c2fc928db886c64114ee571656c8d2a 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index e7c08d22e6bbd4fb214659e231e64e2b2797becb..6d825a66e33f3a4650eaf8e6351e04dce0927a46 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -8,6 +8,7 @@ */ #include +#include #include #include diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 55299745a3cbb85ce22f7b1802e5490c1f9cf71c..97884a3979649f33239383a38c674e18ccf76800 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -5,7 +5,7 @@ * Joe D'Abbraccio */ -#include +#include #include #include #include diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index 14202cd5a7886c49218e383b0f44f2a5526a62ca..b6c1847b141b5a20fb726087cc63d2ce169f99d9 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -3,6 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ +#include #include #include diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 2334870fda0813b1862451c36b103e0f774fb0a3..7b6ef5b11c920ce94d2ff3c8556abe381e9bc214 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 7810010fd04297bf1f60607efd98e6a290197515..ec6e3a2d0ab58fc36c6628b1860541520c44118c 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -5,7 +5,7 @@ * (C) Copyright 2002 Scott McNutt */ -#include +#include #include #include #include diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 0b2afa8054d81105e79387f68fca1a51764d1758..994a32dd92ad04267c9dca1c3c8b813b2f13a989 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -6,9 +6,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c index fbc8fbdbf593576d0f398261ce4e8e48193dbf17..df4fb3912558da9de8efeaa15982199af8d7302a 100644 --- a/board/freescale/mx23evk/mx23evk.c +++ b/board/freescale/mx23evk/mx23evk.c @@ -11,6 +11,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c index a4c39a35221913419e9e01dce01b8c9823a0a88f..14e9b4a8634f3bfdef25c9ee7f542ee6fdec6d69 100644 --- a/board/freescale/mx23evk/spl_boot.c +++ b/board/freescale/mx23evk/spl_boot.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index b84b045bd1f54a9dd74b006c855feacdd5fb5332..cc0c85885446a5984b84f1eff2da6203a5c3214d 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index ada572912dad84d9c2aab6f0444fbf1268793b8b..88c3bf36089c7ee2830fdf0d2dad94c0dd7cfbe9 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -11,6 +11,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 694568423026509f83bbbf90e02476f8c56ac400..95edb35994435892d4ff99c91f19ddd0a20d9b82 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -3,7 +3,7 @@ * (C) Copyright 2009 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 2d8f5da9906f4a56f90065267f25b0d76dd41d9d..d418cd8f4c0dbb19a4d4130adc37baad7f66ce49 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -4,7 +4,7 @@ * Jason Liu */ -#include +#include #include #include #include diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 17095c34e92616e5c790afe6bc038085e6ab8df0..0dfd7dec9efb9b00301d11a1f03799c418152b80 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -7,6 +7,7 @@ * Author: Eric Nelson */ +#include #include #include #include diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c index bc9c4259f07b1c0b80790104d3d9b0e254504583..61d0ca3408f0bddcbe85f22a0f2558fc171f92ae 100644 --- a/board/freescale/mx6memcal/spl.c +++ b/board/freescale/mx6memcal/spl.c @@ -4,6 +4,7 @@ * Author: Eric Nelson */ +#include #include #include #include diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index e782543c0fae70667e67c89b207bab6248bb77b2..77e92006131a7e10d2db107767a3dec1020b62af 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -5,6 +5,7 @@ * Author: Fabio Estevam */ +#include #include #include #include diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index d37d8a4136f6942dd368b0553f506b05816b07c1..e9ac57118b0191cf3537bb71499c1e143c3d60e6 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 7114444fc3e6d54e1aaba16da94a9b425c9224e8..10a00095affb39f2d4b53809a23aef8e135b34a7 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 6176f738238941c0a9959bb1e1768a3c0b47366f..84cc51e9cac780e2519e6474fa63dea5bebd3ebd 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index e3353feec688a12165f26e1a965126ac5bf7cfbb..e7958df40243977237225cfe9b4debf21de03227 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 6b0665a1067fb4672fcb275bb613ab5384522ac0..534b16cec7ae87abb916992b551eacc7b2e5ac93 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 189eddefea3f4a3c3f415ba46d7584f130fc12f8..de45f8b1d24bee69c1992fbf5d59f4caa48bef05 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 3db167c0dad3f8aeff8f9428b0ca816b9bac5d5e..4fe23b51cd1bc165dfa51dd491745fbc50f1bab7 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index af68e57854e2cf25455d4380c511113491e13c02..01e32136532d1cebbf4a54aa167a7f58fbed5269 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 43a0936bc9afb1338b8306bce7e8f75ec92c871c..b423ec8e218a5f9eba40c02533c16c6807c4d66e 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index a7d80f2852119b16e063085c29fa83973795f668..13fc2fa2e38cde5b03c21a32f3c948278ffe63db 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ab0031440ae830b8cde67e2a5fa8d49577f4533a..d32274b24812e272e6984503cb4d0cc283b7dd4c 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index fc26cef2cc8ee32f29db84adb4a641c1d3065901..e450f626e0adc4d5106d2b2649dcbdfc9c95e144 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 8cd79c6fb5f67b1d7c2234319705b734700af535..8f0dec4c0ab7fd245aa9bee62d6181d9027d0983 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 44acebaa2bbd99a9d837ed0ad209420e9cb7de07..265cde81a3c2b49ac6ed33949a521e992d4ac0f3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -3,9 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 8622a5a610a52d51cc96133752430b924a424cc5..5f16779abaadc1c000d4211660e1d8a587868d04 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -3,12 +3,11 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include -#include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 49594070b836469ac7345ae4a456c4a55dd8dc2a..6085984eab43481325855fe41ff84318e3c3e771 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -3,7 +3,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 399ff7207229368ffcea774e05b81fd358e27e23..602b7f0156ba8fb19587b0732dd7281721e408d3 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index b07f481fbf9d25be2ecdda1437f098152dc30551..6c3f82849e3a54aa29308cf268ff8ecfda10969c 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 511bcf5506b4457f1635b7e6d96502c6e6fb795e..f9e0b5b25ab78b4e03c7a47a9c3da99939d4ff50 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -3,7 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index ae0b7adbe544474f8ae752af10b1105b3621e5a6..94773969e9d8989c5e6bc1e425cedeb37b0ba6c6 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -3,9 +3,8 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 915a8b994d5c2ba296f775bf5af6f3149aecaa01..a1908b8a57125c12806a38e5e9fcfd7f686ef472 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -11,6 +11,7 @@ * CPLD_BASE - The virtual address of the base of the CPLD register map */ +#include #include #include diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index b8b765a85ef533a128a27a6aa856548bde7b1df7..910058cefe16004a84708233f89cc9db0a0f8a06 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 65850866777605bd66e46cc3b6534e07dd3b294f..c0d05539c5c00a49df7cc22812894dadfdf9a4bd 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -12,7 +12,7 @@ * and serdes protocol selection. */ -#include +#include #include #include #include diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index d5b71f7843036885a5cc1b7258f4708f941068b5..575259b19c03c22f86e86b296f44e169616d85b6 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -3,7 +3,7 @@ * Copyright 2011,2012 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index cc933ccd5440ec0b91037a9fd1fc91fbf8b79898..17a6226cafc7e56d4cd83310c8e64b5f3e30fceb 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -7,7 +7,7 @@ * The following macros need to be defined: */ -#include +#include #include #include #include "cpld.h" diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index f8d504fb3c734dd1fff00514f2d3bacc4cebabee..1b4173989925eeca1308aee0674879b87eccd141 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 7185a0abd520a3b66defff486fb51c9a7889f3d3..ad78f72f98c82c740f134f4a151a9f1c728d4641 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -5,7 +5,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 81caa961897a09f52e9bbe9d88fa7ea325e62822..d636bef325f05cb34483eeee6274ca019225b394 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index de6cdda194e71133da22f0666ff4d8aea32b4a70..9faf259af74dbdc4c8d3d23befa46ac9617fa4d2 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 0a29e27b42cdacab0999b5cd90887dca636f530c..73f9d3ac72e7553eefa942d6f3bdb75cc20cd254 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -4,7 +4,7 @@ * Copyright 2020-2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 008bd6e72b7b73d129db8a3684104ea105a2d798..2519a9e4dbee7206139cd279ce16ee22d199cde5 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -3,9 +3,8 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index c2d526ae15ac4e667822d2b3867201eab2b375c0..9ac57bbd8300aa51d10568a8c79a8800ebe16f45 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -10,7 +10,7 @@ * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map */ -#include +#include #include #include diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index bab684860dad007a1ea7b6814b6311f63efd5b34..02ddb6614158c5d962c36b8d035389fdaea94b43 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index d5c084e319d4e6658db5f79b89b15252ee4e092d..5eca9386f6eb38c41e06713d84dd00341e2c300b 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index d34641c2397048a6b9122db2f41d99cceafca242..a0d6eb5b2707e026a1e1ca209ab72c7b1d4adf77 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index e02a1f95d4cbf4c07d60b700e7acefe2809f0fff..dd8283f3c60aac1f5273446a3c85f3cccccefd4c 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index ef4dfef4965c32656b413e9cdf8087d0d7411043..b3080492716780a59f47d2cd89de587985df2edb 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -4,7 +4,7 @@ * Copyright 2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 24bc83f756bd745a9b385ad35d99f1fb3216fe10..10be580b81363ae1e74352a7e6048357bd6ff1ba 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -3,9 +3,8 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index 9076fbba10af39adbc82e19bcfd638672a3110e1..56471b3988b9a31b82a1b7e8d31aba9008918310 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -3,6 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 9f299227e2956d5d307619ee4786b68984517314..569b193eab783634700acdf44280e9b3bd77a2e2 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -6,7 +6,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index 287f4650e05897c1d18c1fa72c9fdfb5b1fb73d1..3cdd4937684e54b8e830f4d192f5122b12988164 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 44ad4e68d9f6cd22f81557bfd81e4e18dea65fda..8866be54a66150217e7263a7881f809690e2eb21 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 5e71da0e163f77ee59f817fd4e99719e21dd0e2f..8be55e52e5f6555b657ea83a6d0adfe46efedcf5 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f99d51c8cd762430810b436a7589965578d93ab0..3d220afc16e6cd03ac7eed1c2d0df99a14ced84d 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -6,9 +6,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index d2226af627863ecae316e3a69f14d39602d3a81b..933fa0decc31540e9c7870e0dc8ed0a4fb89415c 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -5,9 +5,8 @@ * Freescale T2080RDB board-specific CPLD controlling supports. */ -#include +#include #include -#include #include "cpld.h" u8 cpld_read(unsigned int reg) diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index fe98f62668a7f38551ec9f57d11cca7cf5ab2ec4..1fbab36e1a2058e8a2524a8acce7b7a85a0090e9 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index 5223eccb2804767e180d5f0f717b4eacd2f92e6c..e4592eac1530692773b3268bbd4b3f8d5c8551ef 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -6,6 +6,7 @@ * Shengzhou Liu */ +#include #include #include #include diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index e1f570a89358bc8e1065d7a201cf13764523484f..53a13694506fd70cea96ac7a1f47aecda280243a 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -6,7 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index df3b9c6fe4050c2427432c6dae3b3b0da7a662c3..130cb8847c0f7632ff96736bc0d73329ae2ad631 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -2,7 +2,7 @@ /* Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index d93edf007ad9138bab8deded20ca1433442c6916..e33e5d082d8004681120e63b3900b17987cae19e 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -4,7 +4,7 @@ * Copyright 2021-2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index df5831541f380b6678124908b2dfeb8d6f8a126c..688a208c621f939c56d6ee99c67dc6c9bafef0a2 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -6,9 +6,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index cd14d5895f5039b00fa8a1b8e83a9d3394abedb4..8b1012086ec7a245045517277fc18c430bf859ec 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -14,7 +14,7 @@ * */ -#include +#include #include #include diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 5b60b50c672bc541950d870bd05a9e1623bbb627..57cbde154f0e4ecab14a5b021b409f7a15ea6a8e 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -3,6 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index e7646365d7d4000c6059677992f165a72ecafc79..2e52543847bffd445a326febf59e45ba50a419ae 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -5,7 +5,7 @@ * Chunhe Lan */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index c43ac0f30d74a7c3884e890126de1325ddb00e01..43eeb884e2ff71554d1b9a2f0cb111ca6f813851 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 9d2472dec250fa935c2d4907ac59b8ad622459ab..779457d29640da8656d9b3afa4084a64a6b81e6b 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -5,7 +5,7 @@ * Author: Chunhe Lan */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 5cacfd273803e3140994b3af06155076b7398a29..ab717769ed5caa5c8cdcf7d17f6b531f7ae6bca8 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -4,7 +4,7 @@ * Copyright 2023 NXP */ -#include +#include #include #include #include diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 1fb9d41d52b15beb39acca2146b40ab8dd6bd34d..f5af893c2d9d4315063211fac93d1bd2d58ec798 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -3,9 +3,8 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 80a798af9cb6971352253a84479e49cacaaaa852..98cb0140ad02637ca284a8dcfc67c2ab9a06f146 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -3,6 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index c8cbc5a15fa8c5c8094bfc714855a1bc57343a34..393c5a447d6fd085fe6af6981c56ff1fefc3391c 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/friendlyarm/nanopi2/hwrev.c b/board/friendlyarm/nanopi2/hwrev.c index cd9c2414a3209ad6e8ff4304833af83c35b2c103..585e08c944f9c9dcd012701b4582f1366abc3f7d 100644 --- a/board/friendlyarm/nanopi2/hwrev.c +++ b/board/friendlyarm/nanopi2/hwrev.c @@ -5,6 +5,7 @@ */ #include +#include #include #include diff --git a/board/friendlyarm/nanopi2/lcds.c b/board/friendlyarm/nanopi2/lcds.c index b37367300cf0c92e7c56840f7fdbdd947086737f..7303e53af9257efafe562309e9179d0f461ef7df 100644 --- a/board/friendlyarm/nanopi2/lcds.c +++ b/board/friendlyarm/nanopi2/lcds.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/board/friendlyarm/nanopi2/onewire.c b/board/friendlyarm/nanopi2/onewire.c index 31cc871330cacfdaae04cc9f778533c2acab5ff9..4f0b1e33c2df98f9c618a6a3d0936f1fd719aba8 100644 --- a/board/friendlyarm/nanopi2/onewire.c +++ b/board/friendlyarm/nanopi2/onewire.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c index 2b5b2844fbd289270834875287bf3cddbe1a525a..d9dfb256b32a36df78f616c6df4e7d207361d39a 100644 --- a/board/gardena/smart-gateway-at91sam/board.c +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c index fb3ec48f9c52ee35c3ab2f83118c519a21b03df4..2807c4e3114147388ca5eaa3408592891c849ff1 100644 --- a/board/gardena/smart-gateway-at91sam/spl.c +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c index c6b14bed41fb676d0fac4333fd021064dca7640e..0cfde91c94c62f153322c4696c436d891ac7454c 100644 --- a/board/gardena/smart-gateway-mt7688/board.c +++ b/board/gardena/smart-gateway-mt7688/board.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Stefan Roese */ +#include #include #include #include diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 891d1b5ddcaa8b8d377802b854ebca1f8cdc32e2..74328b2e1b31d7252ed0f58cebde83532d7a025f 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -5,6 +5,7 @@ * Author: Tim Harvey */ +#include #include #include #include diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index b37f19722491d3732a1e17f458e9b4b7edd0d0cd..e622a9ba9e4daa97d2403ea7bfce9fcf0dfade16 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 21a908c20dd52517b05feef58b1589d652f8eba9..683def7e9f71123080de996415465e0e6d211de5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 3de4727b2edf1b196efcd3612f4150a8835433fc..2f046c9c0b3ed12a39033f918221d50753bc5ff9 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -4,7 +4,7 @@ * Author: Tim Harvey */ -#include +#include #include #include #include diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index afaabf3487933f1b7975ea9bb1112717e6a39892..241be4ee630b0fb46a4dfb58ff4db154101ce5a8 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include #include #include #include diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 3f2c090a94fc30d71557844586c8a8ded356813d..78b431dc28441ce2c5c080c847e54ca9a938ad57 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -6,6 +6,7 @@ */ #include +#include #include #include diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index f10d310a46d4078d688f13ec28f67099c91f7f70..b0a315ba9531f1779d774008da0e017066918797 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include #include #include #include diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 4abb3e451285ec144428948c79421c05b9b33da9..0f620c2d91728f9fc76d4c77bc255f335b45ba25 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -4,7 +4,7 @@ * Copyright (C) 2016 Mario Six */ -#include +#include #include #include #include diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c index a12e115c72cbb89bdbba8c867bde1e46a382315b..61d30c2e637319a1569da4e540dd56e3347e9bf5 100644 --- a/board/gdsys/a38x/dt_helpers.c +++ b/board/gdsys/a38x/dt_helpers.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c index f303793b63b70eaec5fa437b1f1a2cb675b73800..d16233ed78ee6e1edc5c4bf683719a66492b4bcc 100644 --- a/board/gdsys/a38x/hre.c +++ b/board/gdsys/a38x/hre.c @@ -4,6 +4,7 @@ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc */ +#include #include #include #include diff --git a/board/gdsys/a38x/hydra.c b/board/gdsys/a38x/hydra.c index 970d508ff328ccdb529d7d7d3d2f6f75aadc7f7d..495a97691881976ddeb0923f986cea94352eed53 100644 --- a/board/gdsys/a38x/hydra.c +++ b/board/gdsys/a38x/hydra.c @@ -1,8 +1,8 @@ +#include #include #include /* ctrlc */ #include #include -#include #include "hydra.h" diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c index 690a29690b9ce45171218f0dcc361da1157216c0..60a5c37aeffb02ceda13a7c52a90744b5cc8f6bb 100644 --- a/board/gdsys/a38x/ihs_phys.c +++ b/board/gdsys/a38x/ihs_phys.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c index 15c36e22684fdd86b449f36b40fca72a265effd0..7020fae18941fa22ab340b21847fd61630967ab8 100644 --- a/board/gdsys/a38x/keyprogram.c +++ b/board/gdsys/a38x/keyprogram.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index fb6313f01975efc386134c93e08a00b1bdd0bbea..1412421a02181b407479bdd117612218b22c18dd 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -4,6 +4,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#include #include #include #include diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 7698e76b5248f71b60d538f42a119efab1d9b4e0..9ca69ebcbbe749db02f45f860b294e22ea65dfbf 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -8,6 +8,7 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS +#include #include #include #include diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c index a814566beaf0e5055b7b65135cab7b2ef9880b81..5f1215e9e8a65a34e7d9ca6363380a408ce9460e 100644 --- a/board/gdsys/common/ihs_mdio.c +++ b/board/gdsys/common/ihs_mdio.c @@ -4,6 +4,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#include #include #include diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index f01b48b5c8e94e74cbfe322e5e9d523123f457aa..7292d7ab5a41095214a3ebe8c745427f5ae6a58f 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -6,6 +6,7 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS +#include #include #include diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index bd9c5ca996980f88d055c3987f7235fe98da9168..dc548efbc7a43afda789cbcdecd6c3b890bc87bf 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -6,6 +6,7 @@ #ifdef CONFIG_GDSYS_LEGACY_DRIVERS +#include #include #include #include diff --git a/board/gdsys/common/osd_cmd.c b/board/gdsys/common/osd_cmd.c index 39e64f5f2eb343edf6aba3fab2fa88a137b419c3..6a9c0b4c24f0dad5ab8438a451b11d9ced346af0 100644 --- a/board/gdsys/common/osd_cmd.c +++ b/board/gdsys/common/osd_cmd.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ +#include #include #include #include diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index 05e4d84460ae1e163721b80c7b33020129fcab89..cc608c4ac434a95ffed6cbc85fff8a65e3598b00 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 42c45ecedceade1fa76c58f2e126b783a56aa50f..0f90f8ad327bebbb51526adff0d8b7c4c4a32c50 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -4,6 +4,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#include #include #include #include diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 2933de0f3048c7c10fadcea74606c97882d65dec..4fac146353da0cef5144b0febbf72a15b8599c7c 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -13,7 +13,7 @@ #ifndef CONFIG_MPC83XX_SDRAM -#include +#include #include #include #include diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index 031773bc5ef33598a91692a0cc9119f58d7b091e..a2cbd1512e9214c6380c68d36047597d628a05e4 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/board/ge/common/ge_rtc.c b/board/ge/common/ge_rtc.c index 5c62ecca8c89febc5ea506d9cdd6d9a3492a0e36..6437afc7bd0aaee59a60cc692b81eb557aa06330 100644 --- a/board/ge/common/ge_rtc.c +++ b/board/ge/common/ge_rtc.c @@ -3,6 +3,7 @@ * Copyright 2017 General Electric Company */ +#include #include #include #include diff --git a/board/ge/common/vpd_reader.h b/board/ge/common/vpd_reader.h index d32c18da351c8251a96ba82a713d445c9221a9ac..0c51dc57e90251d802989ca9495386492623deb0 100644 --- a/board/ge/common/vpd_reader.h +++ b/board/ge/common/vpd_reader.h @@ -3,7 +3,7 @@ * Copyright 2016 General Electric Company */ -#include +#include "common.h" struct vpd_cache; diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 9396d43f8adda711541e86b443e7c91f92386c06..cc462d53da6a1b2da991efe7c25d7cec43a4c9bf 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -8,6 +8,7 @@ * Jason Liu */ +#include #include #include #include diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index eb4dd758b3b58b0efa8078becf2c1365cca89044..4e2c6ebde73c330a483a0ef3fc452d57c6aff828 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -8,6 +8,7 @@ * Fabio Estevam */ +#include #include #include #include diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 7b2724c01d045e72db0de03a614c24fa5d708856..9d9168d608a1eec7b8dcd5bf10422d1228d23474 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SYSINFO +#include #include #include #include diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index 9544d6dd19a800cfb265a9fc3351962b99fceb2b..d0a740dd3f40492a776211c5c550178d1f377331 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index cfba9300dcbf37439274c4cf12a5e014437ad53d..83de5bfd75fa2500041c34a45dd777976dcc2289 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 53c3435c92fcbd0ccaa7cf2d6520254423a2e287..32dbcdc4d10a56d8aada6cb3fae53120a7db84a1 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 8313b37655fbfbbb79d99434896bb19e662080be..64b32ca96df34a89d983e018a5b0b42b2926a7b2 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -4,7 +4,7 @@ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ -#include +#include #include #include #include diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index 07bb5b7d79744334a1d47564d95963f84f4b3eba..cf1d7cee92525b30b9b1d57d9f002609fd0828d2 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -4,6 +4,7 @@ * Copyright (C) 2016 Grinn */ +#include #include #include #include diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c index 899c502dfbc89718005e5d2b0ad49e7f31183138..9c057278ace15f50176c950174f8701070b7916d 100644 --- a/board/highbank/ahci.c +++ b/board/highbank/ahci.c @@ -3,6 +3,7 @@ * Copyright 2012 Calxeda, Inc. */ +#include #include #include #include diff --git a/board/highbank/hb_sregs.c b/board/highbank/hb_sregs.c index 94052f7a3f9a91e8ce2b01b8ea97ddabad705b58..d9dd2c2bf67f13472442735023ec3a1934143ff4 100644 --- a/board/highbank/hb_sregs.c +++ b/board/highbank/hb_sregs.c @@ -10,6 +10,7 @@ * Copyright (C) 2019 Arm Ltd. */ +#include #include #include diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index f3df83ed6c9bb14b205f738a48d55d66029e269a..7f67d1e45308531d94d099d959e442d6177e7a7f 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Calxeda, Inc. */ +#include #include #include #include diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 95a831efcafda1b9fa470fc0279021cd1b3875bf..c9a2d60ee56c0212676326126b8a65d3e6df86e2 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Linaro * Peter Griffin */ +#include #include #include #include diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index 5029f4edb2af3fd7d15935cbb43f3cb36b0a5f0e..f41fabbad099739d382c07747b03537c8461119e 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam */ +#include #include #include #include diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75a71c97e92fb5627740ecff8d8f8d2..b89e7e869766d20a00a7b1e20e112d460032e87f 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -4,6 +4,7 @@ * Jorge Ramirez-Ortiz */ +#include #include #include #include diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 0966e257464a26cd273fe75893eb83f99b2ca393..68d3d300dc40627156b5a0dae6499c0a6d094efe 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,6 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ +#include #include #include #include diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c index b0f7d3243c5eb218af10f4b73afa15d1b09f0438..c246a7b9d455f77ec252eb55e679a496091db069 100644 --- a/board/imgtec/boston/checkboard.c +++ b/board/imgtec/boston/checkboard.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include #include #include diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 55356d1175de590de329b3688423a796fd74de19..cecf454011ccc9c0dc4ec3236dda73cdbd92cf7e 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -3,7 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ -#include +#include #include #include diff --git a/board/imgtec/boston/dt.c b/board/imgtec/boston/dt.c index 874a21cec61ed5ee7d63208efb72a8543b1b024b..bf772ff5dec4f7b10de1c50bf0a17cbd0dbb037c 100644 --- a/board/imgtec/boston/dt.c +++ b/board/imgtec/boston/dt.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include #include #include diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c index 4e268381d3c5222c534299ac7f6eade0b0bf4465..89f5e7ad792c905d61c7156e02e0b5070327190c 100644 --- a/board/imgtec/ci20/ci20.c +++ b/board/imgtec/ci20/ci20.c @@ -6,6 +6,7 @@ * Author: Paul Burton */ +#include #include #include #include diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c index edd5c203b16da51ac5aca1eef5b33a1099824ff1..aba11e25be31736f3ada5f34224ab73f71e0fca4 100644 --- a/board/imgtec/malta/superio.c +++ b/board/imgtec/malta/superio.c @@ -6,6 +6,7 @@ * Setup code for the FDC37M817 super I/O controller */ +#include #include #define SIO_CONF_PORT 0x3f0 diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index e50ee8efe55860a4ff40952f1ad21fe76c8be7ad..7122692721143faf10bf1608138d36b4298a2b3f 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -8,7 +8,7 @@ * */ -#include +#include #include #include diff --git a/board/intel/cherryhill/cherryhill.c b/board/intel/cherryhill/cherryhill.c index b4378afee1526127627f93e10472c71222545488..c037d5b14cd71c10ca58079b1463acb08f9794f7 100644 --- a/board/intel/cherryhill/cherryhill.c +++ b/board/intel/cherryhill/cherryhill.c @@ -3,6 +3,7 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #include diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c index e5cda068e17d051062f5ffcdbecc5d90190d9ed9..7f61ef8b366b20970b289d0ef11cdad292d4a68d 100644 --- a/board/intel/cougarcanyon2/cougarcanyon2.c +++ b/board/intel/cougarcanyon2/cougarcanyon2.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 036beb1146dcac2f68461ae64fe4a8797ebebe6b..55095deeadd7100856977e012f7f9b47a47c52a2 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c index 911ffda2fc7811c9ce798183d648fbadbff3ce37..11e7f74e47cca0c9733d698ad71eddcd77d03b76 100644 --- a/board/intel/edison/edison.c +++ b/board/intel/edison/edison.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 19e5d0952fb845cba7a5f40f38e4a93e0758a901..341b627a65f5919a6cd07f2f364a1e0371bada41 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Bin Meng */ +#include #include #include #include diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index cdc2e0b75d811e0d01db56cfe00f07dca2b0bc05..b02e3f0d4e5c43144255bb412915d879e92b49b1 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -3,6 +3,7 @@ * Copyright (C) 2015, Google, Inc */ +#include #include #include #include diff --git a/board/intel/slimbootloader/slimbootloader.c b/board/intel/slimbootloader/slimbootloader.c index f92c0b5112f001028cd314fa60468460848f5782..b20ddf0c682e608a73fe829e783cb1eab8d89022 100644 --- a/board/intel/slimbootloader/slimbootloader.c +++ b/board/intel/slimbootloader/slimbootloader.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include int board_early_init_r(void) diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index fbed8abcecfb4629e928e59438a26d423a81e64c..f3a0de3967bba17b15dadb729220f8b65157a55b 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -7,7 +7,7 @@ * Andrej Rosano */ -#include +#include #include #include #include diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 00b08987e9e8f6ac7072775c1454964ec18e40ca..0387160200190c35a6acad7f0097c0c6dde30204 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -6,6 +6,7 @@ * Luka Perkov */ +#include #include #include #include diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 7cd26ce3c34b7f14c3957b8288e5f02929e7755c..7dbb080089271c28dd498a747de6a4ec5686d569 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -5,7 +5,7 @@ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/ */ -#include +#include #include #include #include diff --git a/board/isee/igep003x/mux.c b/board/isee/igep003x/mux.c index 1a40c0077627560daa5a4fb97df2c0be4be0712c..550e3b3197dd993cc4e79ae63d81fb3383adbf77 100644 --- a/board/isee/igep003x/mux.c +++ b/board/isee/igep003x/mux.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c index 2584d2e5ddfde02f4a3139642f4aeff47a45a330..3fdf83e845c9cf4c5b414dd1be9faa5b90a1abb0 100644 --- a/board/isee/igep00x0/common.c +++ b/board/isee/igep00x0/common.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 8a3f290f678fe6fbc0529edc269e40723d01e801..0f0a9c592fcc3f76fc0630c33b89edefd862ccbd 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -3,7 +3,7 @@ * (C) Copyright 2010 * ISEE 2007 SL, */ -#include +#include #include #include #include diff --git a/board/k+p/kp_imx53/kp_id_rev.c b/board/k+p/kp_imx53/kp_id_rev.c index cbfe94e25a28059fbd3f8326cae9361c8dbddfd7..9f93cf008ce8542b84d7d933f1970694a28ed6b4 100644 --- a/board/k+p/kp_imx53/kp_id_rev.c +++ b/board/k+p/kp_imx53/kp_id_rev.c @@ -9,11 +9,11 @@ * Daniel Gericke */ +#include #include #include #include "kp_id_rev.h" #include -#include static int eeprom_has_been_read; static struct id_eeprom eeprom; diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe081d43987fab6b7db30bedf1510b3b..7c3a695cb258a9a30b66167e24a2751c59eb311c 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c index e0895194300a064fc6d04723a5730076f2449fa4..e6877e4c07039dc3bf04b780a5b8a5e3673a7f36 100644 --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Lukasz Majewski */ +#include #include #include #include diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c index 6a5e252751d4788132c7897b9079c67f824de15f..54902437940bb9e46a9c4fdbd2a5574e0a30a1d0 100644 --- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Lukasz Majewski */ +#include #include #include #include diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 9358c25dcb05151547268bf4655aacfea78de3ee..991022ac833a2195ca4438237471fa370faf8eda 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -7,7 +7,7 @@ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com */ -#include +#include #include #include #include diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index f01fe44303c902df294701cb7130809ee9fdc64a..67db0c50f47c1e80b49ae6d0fadf6e946747f67f 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -4,11 +4,10 @@ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com */ +#include #include #include #include -#include -#include #include "common.h" #define MAC_STR_SZ 20 diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index c8299483299d732c43e7e344aaae1e4e1fd36f78..b433f69675abad4fd1ab9f0e4347f0897f17576a 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -4,7 +4,7 @@ * Valentin Longchamp */ -#include +#include #include #include diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 40718aa58a7b568a1839f432d29af9eec41c53c5..acd13105dd55e729d9977b85ac9c2bf13462d9b0 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -13,7 +13,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 77e11e9bc1ed9824538e063a9901d2c3c0789100..41b24e39433d55bd14a32e6afce32b989cc6796b 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -7,7 +7,7 @@ */ #include -#include +#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8875fc2dd23686e17d89ef02801b51..556d39d4d4e3c0a3eda43948933c523779da5e4d 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -4,7 +4,7 @@ * Copyright 2020 Hitachi Power Grids. All rights reserved. */ -#include +#include #include #include #include diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c index 1a626c520680057e4a826e319fed0e27c1059d4f..6a4cb21786ac07bdf7e3dff3b3aaf651b3711903 100644 --- a/board/keymile/secu1/socfpga.c +++ b/board/keymile/secu1/socfpga.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2017-2020 Hitachi Power Grids */ +#include #include #include diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 4c8407bb676846dda2a1270d53a07b0df5a1d13a..9c5b687b3e8bb7e22bd99e48256e8805aae5eb05 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -4,7 +4,7 @@ * based on board/solidrun/clearfog/clearfog.c */ -#include +#include #include #include #include diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index a908aee9eccf7e8f15f454152549f95a07056de9..4548e7c1dff90d63ba120b0dedbe7e9ee21cfdf7 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include "pitx_misc.h" +#include #include #include #include diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index 475e52f62314c8dc4fe59ee0c6154503aaa8eae7..a247803a4b469bffcddb6dac3a50eac1247f83d0 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index 851aeef8f8c28dbd2da8d67c8cb89b4b4c60bd91..74b79c7a009f1c3a114169345eb9044910570100 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/kontron/sl28/cmds.c b/board/kontron/sl28/cmds.c index 7851361c48cc7ee68b4e93b62ea89cf9ae3744cc..08a22b5d01e0b7d9702b205b41cfc1b3020592bd 100644 --- a/board/kontron/sl28/cmds.c +++ b/board/kontron/sl28/cmds.c @@ -5,11 +5,10 @@ * Copyright (c) 2020 Kontron Europe GmbH */ +#include #include #include -#include #include -#include #define CPLD_I2C_ADDR 0x4a #define REG_UFM_CTRL 0x02 diff --git a/board/kontron/sl28/common.c b/board/kontron/sl28/common.c index d8d0172a21b7479d5088f53c4cd6f43a92631392..331de29baee637a805e8f9db83f3a55249966efa 100644 --- a/board/kontron/sl28/common.c +++ b/board/kontron/sl28/common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include diff --git a/board/kontron/sl28/ddr.c b/board/kontron/sl28/ddr.c index 9b881fdc265e64457523ec1cad94d84404d9fc38..315d9f99c71d3a93062edfc89bbdc76e8faebe14 100644 --- a/board/kontron/sl28/ddr.c +++ b/board/kontron/sl28/ddr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index adfec8ba2379cb65563569230079b8b58104efb4..4ab221c12bf6ef777ee13417d2978c9778284195 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 45a4fc65120e45cf06752dfe2035179ec6acc8b4..80acde74956db0816da33b6f8d85b5af24ce5c6d 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ -#include +#include #include #include #include diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48bc2c2a9b954bb6fba081783f59287e..a9cd6850e983e84c899e372f8b2e1f950d388aa5 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -5,7 +5,7 @@ * Copyright (c) 2020 Michael Walle */ -#include +#include #include #include #include diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 3220727f236601a4e5c76af1f0a0ec444f56c0fd..f009a8afd48c32507b3172402a4ae78a6b5affa7 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -5,6 +5,7 @@ * Copyright (C) 2014 Marek Vasut */ +#include #include #include #include diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index 008418b01846858af23e44183ebf6a810eb0ed8b..24c0fb22268f5077d91f2fcdda112be37ff2b281 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -5,7 +5,7 @@ * Copyright (C) 2014 Marek Vasut */ -#include +#include #include #include #include diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c index be5a737a31dd32ea295d2cfbecbd7aed964925d0..a96a877f5f21834d9784104d711d28c61ad84c0e 100644 --- a/board/kosagi/novena/video.c +++ b/board/kosagi/novena/video.c @@ -9,6 +9,7 @@ * Copyright (C) 2014 Marek Vasut */ +#include #include #include #include diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 066d315baa221aeecdb536eccdd05aca20659671..b3c176dd59a09075cd01c99935e287b257a60cac 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -9,7 +9,7 @@ * Gregory CLEMENT */ -#include +#include #include #include #include diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 1a153668a43ce1620c23c779d5bd92ba812b3bb7..43afe593c78b87eb36e76604176b2163886b3016 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -12,7 +12,7 @@ * Copyright (C) 2007 Sergey Kubushyn */ -#include +#include #include #include #include diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index 88d5d08814335a1b86809f99d187bf032daaeee8..86032d7fcdf7b0e876bc6c8b9ed71b0a22e22c52 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c index a0bbd03e8d19cc47cb4d07227ee376b6fc1d692a..e3a59dbec009b1175e18520e661f56cc97b19548 100644 --- a/board/liebherr/display5/display5.c +++ b/board/liebherr/display5/display5.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 819d3acbe56091fb79dd629ff9b2db2571baaab5..97928e92215c34dfeb1b2e7954fe065fbba87b0f 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c index fef915b2acaaeb2f6e36d620cf0e749e3148679a..1b49526fba4f2dbc230c5ad45982054ea98d454f 100644 --- a/board/liebherr/mccmon6/mccmon6.c +++ b/board/liebherr/mccmon6/mccmon6.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 88c157eca45ae0bf4f243e88cc71dc07378fbd32..6cf8f8390e8b74e39fc4e11fcc90e8337cc01177 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -12,6 +12,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 9ade3563b2554b50d0c5ee07a6dbced6920246b5..0a6fd7f1437e2e665e9b9521132f9b7d957f9204 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -13,6 +13,7 @@ * */ +#include #include #include #include diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index e6ca31016b7c3adfacd76659d55a43330b2d80a9..e69a73f2af6f1a536ee7ce15b012d3b86a63c371 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -10,6 +10,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 589136fd64aac1ce84efc149208878826980113c..0d53548dcb4badab5d9a000fb6b86a6dba08f16a 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -8,6 +8,7 @@ * and updates by Jagan Teki */ +#include #include #include #include diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index a9fe61918b6a23b7817d774b89a490ec445e9965..86992829caf45c63a1fb1c662879679e65b034f4 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -10,7 +10,7 @@ * Richard Woodruff * Syed Mohammed Khasim */ -#include +#include #include #include #include diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index e011520f2ec26327417864cae7d77756be096906..aad3dc864295a92269e424ddd8ad0ba6811088d6 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -3,6 +3,7 @@ * Copyright (C) 2014 Stefan Roese */ +#include #include #include #include diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index e7f492a13bc3176a30e92847778416a6a25ada6a..2cc73bc35dcae794ce15bda2f681afb90ec980ff 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -4,6 +4,7 @@ * Author: Sam Shih */ +#include #include #include #include diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c index c78eaa072439715498cde0b55baab3549fae412a..ec10f77c51e4847cfdb74a8c8778c79f899f37a5 100644 --- a/board/mediatek/mt7623/mt7623_rfb.c +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include #include diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c index 02719181624c5c396d1dbfc4a2bd8e8b2882c2c6..55f7696c51075cc8886a4ca9cc955d887fb31b4c 100644 --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -3,7 +3,7 @@ * Copyright (C) 2018 MediaTek Inc. */ -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mediatek/mt8183/mt8183_pumpkin.c b/board/mediatek/mt8183/mt8183_pumpkin.c index 1b8736966f616690e7d1da459d7e6b6798004cda..db613ebdc4f41398ca43f18d43b9fc4a35923255 100644 --- a/board/mediatek/mt8183/mt8183_pumpkin.c +++ b/board/mediatek/mt8183/mt8183_pumpkin.c @@ -4,6 +4,7 @@ * Author: Fabien Parent */ +#include #include #include diff --git a/board/mediatek/mt8512/mt8512.c b/board/mediatek/mt8512/mt8512.c index d2f557ffee5f9df5822a9880fe222af8864de97d..ac3adb8012221f5eb379c7cf05220d1feeca0971 100644 --- a/board/mediatek/mt8512/mt8512.c +++ b/board/mediatek/mt8512/mt8512.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 MediaTek Inc. */ +#include #include #include #include diff --git a/board/mediatek/mt8516/mt8516_pumpkin.c b/board/mediatek/mt8516/mt8516_pumpkin.c index 930bfec34836e9defc02611fce2ac2f31df1b34c..42f3863b92c32438f6e2c729af8c5c5c355d3b03 100644 --- a/board/mediatek/mt8516/mt8516_pumpkin.c +++ b/board/mediatek/mt8516/mt8516_pumpkin.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 BayLibre SAS */ +#include #include #include diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c index 745cfda2ddf07c5fa0e32fe2fa482005a0ba2cd3..e03da63b1d922e3d720eb65bc9b99021ad7f3ab8 100644 --- a/board/mediatek/mt8518/mt8518_ap1.c +++ b/board/mediatek/mt8518/mt8518_ap1.c @@ -3,7 +3,7 @@ * Copyright (C) 2019 MediaTek Inc. */ -#include +#include #include #include #include diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 79351f472731e46a4b07dc8af63f23241f385b2e..b8dffb0e48588565b188012be64466ce6d8fb141 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -6,6 +6,7 @@ * Copyright (C) 2014-2017 Olaf Mandel */ +#include #include #include #include diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index f47b45c1d5607e5af61cd1a7a8e06bd8c51dfd9a..18f5fd5c5ee9e7a6fa7aadbf772854410c308a3d 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -3,6 +3,7 @@ * Copyright 2021-2022 Marek Vasut */ +#include #include #include #include diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 7beac33cfbd379b9cee4008408c40a7c80943b73..0f5f82924e7732493aee3ef793332cc175716764 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -4,6 +4,7 @@ * Padmarao Begari */ +#include #include #include #include diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c index 848a1aee4000465199895e39c07af56286a59fee..3c2203d22025216efa369f967f28e26273bcedf0 100644 --- a/board/microchip/pic32mzda/pic32mzda.c +++ b/board/microchip/pic32mzda/pic32mzda.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c b/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c index ae1c586277f985bc92114d43d8e2f1304f1245f5..315169ba661d9d613678194b39694aba98306ee1 100644 --- a/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c +++ b/board/mikrotik/crs3xx-98dx3236/crs3xx-98dx3236.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ +#include #include #include #include diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c index ebc490e24b1c91d8432f9cf517e0f62cc078a98a..be5c5060a2a09c561a52826e24cc185e043045e0 100644 --- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -4,6 +4,7 @@ * Copyright (C) 2018, Boundary Devices */ +#include #include #include #include diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c index 48a783593b6eaeea4296cfaa6093c3c53e64a82e..5120c628b91a1a701761852a42416dd10dd37c81 100644 --- a/board/mntre/imx8mq_reform2/spl.c +++ b/board/mntre/imx8mq_reform2/spl.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include #include #include #include diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index b1ce014bd55d1bee6f26c0dd53445d57f4511309..6ccbf02db06e67aded8f2bf06fb906d81ebf68e8 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -7,6 +7,7 @@ * Copyright 2021 Collabora Ltd. */ +#include #include #include #include diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index b1b5561838dc55a8569177679d678865a10987db..ed7a1b7d3d00269e31c31290c1ed6900f9313d82 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -7,7 +7,7 @@ * Copyright 2021 Collabora Ltd. */ -#include +#include #include #include #include diff --git a/board/mscc/common/spi.c b/board/mscc/common/spi.c index cb43ad6811e7b32967387a8524aaa8371c74a076..45b9649336dbccc571fe9e5d2b25ddd9d9dea504 100644 --- a/board/mscc/common/spi.c +++ b/board/mscc/common/spi.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Microsemi Coprporation */ +#include #include #include #include diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index acaeb46802238f4623e8f51086e0b29e99a4e7d1..84b95be648d7ed9c93f51b67db98b464e157a819 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index f9ea26ebc5c63ee59f10440837cdb7b72200191b..48170b3aa12d71cec00d93cb59d513c30fb4ee82 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 4cec25b3976c6f665bd19391a55809eb0ea86835..d69db04de664fd31b8594eed609053e34c9dde60 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 951c24dd286b4fabb480d7970d10d37c9006a48e..99d5f5be657e519c69d7f0c7b8b5787bc2b04b8f 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index 9055b73ada273ba71d6f6c8b6b4a3073ac960f7e..49993168c237ddd26371ecc9e5292de50bd40df8 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -3,7 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include +#include #include #include #include diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c index 4414487eff241d019f7c50f2ded5795dace4e13f..3cf14e2bc660595f2c2cee5a9c6a8409559ef625 100644 --- a/board/myir/mys_6ulx/spl.c +++ b/board/myir/mys_6ulx/spl.c @@ -4,7 +4,7 @@ * Author: Parthiban Nallathambi */ -#include +#include #include #include #include diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c index 9cf3a2fe60a2fc26425a238eef2e693b366566cd..cfc3529c3488e4254b8cd4500ccd069708e950f2 100644 --- a/board/netgear/dgnd3700v2/dgnd3700v2.c +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/board/novtech/meerkat96/meerkat96.c b/board/novtech/meerkat96/meerkat96.c index ca3b0698f5a8e251b1ab904ef4f48edf685e9a8d..1edebe5db9be745517a2c6ea66a8662477856e20 100644 --- a/board/novtech/meerkat96/meerkat96.c +++ b/board/novtech/meerkat96/meerkat96.c @@ -12,6 +12,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 1f519219e7e641ff5465b10425acec63281e1001..53c931c3c2443647e8c3424e4e0c93086aff1a6a 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 3c4e5aaf2940103e6bfb9b06b0c528d5d6f999a8..e69bca95031f41664f1800a2d91a23df5f849741 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -4,6 +4,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/board/nvidia/beaver/beaver-spl.c b/board/nvidia/beaver/beaver-spl.c index c6956ff9f5827694813a8be77bbb77deb9107433..b5d0c14854dd46020545c54854eae89cd9d85eff 100644 --- a/board/nvidia/beaver/beaver-spl.c +++ b/board/nvidia/beaver/beaver-spl.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/board/nvidia/cardhu/cardhu-spl.c b/board/nvidia/cardhu/cardhu-spl.c index 80912a65a19486a966702e1133da4e4eb1105e23..de2fa300f1c89b99fff230ff49928a6d8ccdd722 100644 --- a/board/nvidia/cardhu/cardhu-spl.c +++ b/board/nvidia/cardhu/cardhu-spl.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ab0dc61ebe54e912d73cae16903c0a785885713a..6848e3400466fb8ca80258ab649ee763a8ccd535 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index c00c6343eaa0fc91fab9ce8d5c18face57d62c05..72511e401e3cea6e0c48cf6f079907cc2ba9ce80 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index da14e09c40cc4e0a7932d3fb9f00d9eddc29d5e8..52236792e24da3f14d7b7c33d332f97620c22c65 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index da6edb42c1eb2fb32e3e2dbf5998ad5f4fd6ef60..7f3cdd70fe7793ffac777cd88620bc002dbfa88e 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index e15f31dcfd7f911152170fd6f672ff1eb26e9dd3..06a36f8ed3871920702999ebc2958feff7ba2284 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/p2371-0000/p2371-0000.c b/board/nvidia/p2371-0000/p2371-0000.c index edf2b1adb7c60891641c828cf81617448e8ffb57..b819b049f4b4fca3ffdfd67c6eff43fe409e5d2b 100644 --- a/board/nvidia/p2371-0000/p2371-0000.c +++ b/board/nvidia/p2371-0000/p2371-0000.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 5f203d8ffaa8fbac73f4160360fe5acdd4c70464..816c7bec6ae4eafe09e63df68fdc99412a8b4989 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index 4056f986483b3e6b6fa406b0f4876988c360b48f..a4c4259eeaee9339cca130415166b0d9d844eb3a 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 12eaa7a1e53da27b2efaf866668bf2a24d4a2263..5ff89c45423e82a1aa1962719b49a57311ae96f7 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION */ +#include #include #include #include diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index 530c438a2e3081b8b2b5fd1a806523ef077ff610..fb1a224daa72e7b4d79caa48c747bbd4bd8a8f46 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index a646dcc96b52e371a4c25460ff08c1b46a6cf5ec..829751112f1c05a586e6c20951d537d86b88eb7b 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index b89e03703b210fa24b6a29e1a088a2817506e82e..395bdd99c78915411aa07feb6701cb8a145168c4 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c index fa10cda4870e7647c79e6c41d6e06ed4052bb3e0..d89bbe5ecce2f828e266242d7327c79fff9ca970 100644 --- a/board/nvidia/venice2/venice2.c +++ b/board/nvidia/venice2/venice2.c @@ -4,7 +4,7 @@ * NVIDIA Corporation */ -#include +#include #include #include #include "pinmux-config-venice2.h" diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index b2bb6678c23f48a7f224a4d5f1c8b88a5e61071a..bdd5fcd76ae8d77aedf469430d7f733e874a89f1 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -5,6 +5,7 @@ * Copyright (C) 2013 Marek Vasut */ +#include #include #include #include diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index eb85ce9643d8f753170930e07aa8af170f02903f..248176c23cdc60a926a754356f91f5af741996d9 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -5,6 +5,7 @@ * Copyright (C) 2013 Marek Vasut */ +#include #include #include #include diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c index 4c957e8899212a4feeca467c3423618336766419..f2282d15488866d172de5989daffc3e88ebaa6a4 100644 --- a/board/openpiton/riscv64/openpiton-riscv64.c +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -8,6 +8,7 @@ * Pragnesh Patel * Tianrui Wei */ +#include #include #include #include diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index 10469aecd0bbc196c4891b82ae62a82aaff07fab..edb200e9e55bd021fabf28ccfb435f5d1fe6c620 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -5,6 +5,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index c34fc503059bb2f78492b4f2416265eaadf39e48..3feb00fd1ecbbcd50c035fc0a75086c914c342af 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -5,8 +5,6 @@ ifdef CONFIG_SPL_BUILD # necessary to create built-in.o obj- := __dummy__.o -else -obj-$(CONFIG_ARCH_K3) += k3/ endif obj-y += phytec_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c index bfd60ffb777307ecad2aad626386733c6099bebd..ee34a5b95791d39f645010de6e30ee92120c7248 100644 --- a/board/phytec/common/imx8m_som_detection.c +++ b/board/phytec/common/imx8m_som_detection.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile deleted file mode 100644 index bcca1a9f846c238cb505728264306bf834debfd9..0000000000000000000000000000000000000000 --- a/board/phytec/common/k3/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -obj-y += board.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c deleted file mode 100644 index 9cb168c36cbaff9b10905c0b8d20080c80023d44..0000000000000000000000000000000000000000 --- a/board/phytec/common/k3/board.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -#include -#include -#include - -#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) -int mmc_get_env_dev(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - return 0; - case BOOT_DEVICE_MMC2: - return 1; - }; - - return CONFIG_SYS_MMC_ENV_DEV; -} -#endif - -enum env_location env_get_location(enum env_operation op, int prio) -{ - u32 boot_device = get_boot_device(); - - if (prio) - return ENVL_UNKNOWN; - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) - return ENVL_FAT; - if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) - return ENVL_MMC; - case BOOT_DEVICE_SPI: - if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) - return ENVL_SPI_FLASH; - default: - return ENVL_NOWHERE; - }; -} - -#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) -{ - u32 boot_device = get_boot_device(); - - switch (boot_device) { - case BOOT_DEVICE_MMC1: - env_set_ulong("mmcdev", 0); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_MMC2: - env_set_ulong("mmcdev", 1); - env_set("boot", "mmc"); - break; - case BOOT_DEVICE_SPI: - env_set("boot", "spi"); - break; - case BOOT_DEVICE_ETHERNET: - env_set("boot", "net"); - break; - }; - - return 0; -} -#endif diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index b14bb3dbb7fa78dce7a74d67f294ff0a9d8b88bb..78c173df20d44c415d9ba8a3460e63e489452e3a 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index b98c46dbcbd4190806a207c28e70e1d97552d392..b6d459fdfce65e8968582b8c593e12300a607e49 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -6,7 +6,7 @@ * Copyright (C) 2015-2016 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index 20f2aac332da8d421e97d15cbcf044b4fb12059c..0f7235979b0428e5485898a62be11cf2bec0e5d2 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index ecc5b75d8d4200d5280ddf3c590f41f0aeae73f3..b37c6fe218da48a6ca5b4da478a66f72ca5a9081 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -9,6 +9,7 @@ * Both NAND and eMMC cannot be set because they share the * same pins (SD4) */ +#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index 2022525651dc8e66de6f09ffcc831df9e50d1dae..5700effbd3f6640a1c70e2f9ddab47439de6d3bb 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -10,7 +10,7 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ -#include +#include #include #include #include diff --git a/board/phytec/phycore_am335x_r2/mux.c b/board/phytec/phycore_am335x_r2/mux.c index bb1c48da0fe53546bbb371c2407fffa6096ab1f2..7091c985ba12d909c998d823f2f824ec76468e15 100644 --- a/board/phytec/phycore_am335x_r2/mux.c +++ b/board/phytec/phycore_am335x_r2/mux.c @@ -6,6 +6,7 @@ * Copyright (C) 2019 DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda7b2268d05e7aafe9a77d648089b41..618b4c370d1e636c403cf32e6ef252661dc4e144 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -5,8 +5,11 @@ */ #include +#include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -54,3 +57,67 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif + +#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) +int mmc_get_env_dev(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return 0; + case BOOT_DEVICE_MMC2: + return 1; + }; + + return CONFIG_SYS_MMC_ENV_DEV; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 boot_device = get_boot_device(); + + if (prio) + return ENVL_UNKNOWN; + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + case BOOT_DEVICE_SPI: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + default: + return ENVL_NOWHERE; + }; +} + +#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + env_set_ulong("mmcdev", 0); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_MMC2: + env_set_ulong("mmcdev", 1); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_SPI: + env_set("boot", "spi"); + break; + case BOOT_DEVICE_ETHERNET: + env_set("boot", "net"); + break; + }; + + return 0; +} +#endif diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index 06cffbca3a690154318e1aae020c8987c66d8055..ef6472916903877bbe182dfaa48912aab1c79b1f 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index 8d858590a39b3fbab00c855692214de2831f91bf..690a51f7a72e917095cbb7b9ee0e7075a41408e3 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index 35683591433cfccf73484f353c072da479469615..dbdd6bb793739a0195272391869f782b53c44afa 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 352f803e4541704fe1cfdb07caed62452ea70dbd..df158024654e64ee8ffd20a53a1cc7c45798c062 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -4,6 +4,7 @@ * Author: Teresa Remmet */ +#include #include #include #include diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index a970634b4c331d973f3ae7fa70f3d048801245e9..3f49f39e3d5ddc80fa629e7d84c9cd4d023ea59c 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -4,11 +4,13 @@ * Author: Wadim Egorov */ +#include #include #include #include #include #include +#include #include #include #include diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 01e210fcdd156c6e071546fd5a67268598c560cb..0a4048d4982fea354e6e6d4f1883cddf5ad21800 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -5,6 +5,7 @@ * liuhao */ +#include #include #include #include diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index fbbf6789b50541893ea00f03b613a9e53dd2930d..0e837b0f50f4abd6701f8fd460fb6d250723fb35 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 0ea335e7486b22ba356678f2853b21128f45f558..960e491c7687adacfa0a5aa4699639e92afd0551 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index 112770ba493100f60effa0e5e3dac2867984e7e1..14b94c9e33ce3ad5ccaad9985601a176db57dbcc 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c index 6cbd1815cad5815c556cbec2456bc2997ee64945..eb904e116b1199415d22b980bad6a3325f1c960f 100644 --- a/board/polyhex/imx8mp_debix_model_a/spl.c +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index a3c421572afb7fa398182d2e5b5b994f04f4f6f4..d0249e71f09aa1a84a6109f24aa558e2d39fbfde 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -4,6 +4,7 @@ * Copyright 2021 Purism */ +#include #include #include #include diff --git a/board/purism/librem5/lpddr4_timing.c b/board/purism/librem5/lpddr4_timing.c index e9559e3d843aaac7cbf08ce4b65f366fb3209cca..46bc7f8591cbf850d6ad85d5c4e5cf42b15c278d 100644 --- a/board/purism/librem5/lpddr4_timing.c +++ b/board/purism/librem5/lpddr4_timing.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/purism/librem5/lpddr4_timing_b0.c b/board/purism/librem5/lpddr4_timing_b0.c index 5d8f2803be67f56db518fb5e8183355af3c3ddd5..ec68edaf6905b51c064b83f84782dffb2cf67ddc 100644 --- a/board/purism/librem5/lpddr4_timing_b0.c +++ b/board/purism/librem5/lpddr4_timing_b0.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index ed57554a2bc314a42c4be7c0e18e78d6c1d45199..9aadc553302e0bb06dfedb536af1d4716cc50241 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -4,7 +4,7 @@ * Copyright 2021 Purism */ -#include +#include #include #include #include diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index 6bb12602193ae746560267bf57b51958d7b911d2..60a2e19143dbbe0e02c4251d085ea38d50d23b2b 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index b88de9c4ec85e0d8346cf8886c68d37b4a0e8611..ac65054136caca92d39436abc11bea23c9a841e0 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/board/qca/ap152/ap152.c b/board/qca/ap152/ap152.c index 53587288c93933315a2e612a6e33f1238d431e0d..82458c3af421ce46b9cc2c6afdf98813aec5a39c 100644 --- a/board/qca/ap152/ap152.c +++ b/board/qca/ap152/ap152.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Rosy Song */ +#include #include #include #include diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index bd2e213b3bca4e0ffa402e9ddfdebfc1b01bb34c..fbbfc0e65e24ba4c0feedc04ec9129b563dbb0e5 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index d3333a59db01caa940224a99df6b43a3375cacf8..ac7de711c588f7cfb31fbc0f18fb1d85d3ce803c 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 8d1d549a217cd47f7b91180a28eaeb629b017f70..f9bc07649e0a7ddd7cc2eed263881f57b61f558f 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -6,6 +6,7 @@ * Simon Baatz */ +#include #include #include #include diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index d996eb0cf695ef13305a6f8ed7a576c14ac854d9..2851ebc985355945335685a6c40711c1ab3eeb84 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -3,6 +3,7 @@ * (C) Copyright 2012-2016 Stephen Warren */ +#include #include #include #include diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index c88257d96772d7cf2eb8d6d3e75086fdcb15d92c..27fccacf6f809b5e8a062993f19de89cd35d9745 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a07ba615e33d66edd5a8081694b4a12..c475c3f50ab3bbbe18be66ef7e8d44d8ad4e7271 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -10,6 +10,7 @@ #include #include #include +#include #define RZA1_WDT_BASE 0xfcfe0000 #define WTCSR 0x00 diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index a0805030ea4636efc7379fb5ee93c1b56394aff1..8c606463e45528f50781569d24a5f4b53d57fc80 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c b/board/rockchip/evb_rk3308/evb_rk3308.c index c895da934a998b4f8a4a8b32fbc7336bd4c41604..e0c96fd70a287fbdd2eebb28a3ca5657c2823ef5 100644 --- a/board/rockchip/evb_rk3308/evb_rk3308.c +++ b/board/rockchip/evb_rk3308/evb_rk3308.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd */ +#include #include #include diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 48b9d8f80c4b5097f242d28349317d1fcc0c6def..0d7a486bed74cbe09212978a1764d8d2bb2330a8 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -4,6 +4,7 @@ * Authors: Andy Yan */ +#include #include #include #include diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index c452b131208d0c0a5530011b13771818f75fbc2c..0ca91cdeb014c77cd17f598da55fb78727dfe42a 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index e966e9f201abbb3ae8cd5e2c15a11d00ddba442d..eff3a00c30a81662274a1df9ea1029e21441006a 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -3,7 +3,9 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include +#include #include #include #include diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c index a1f3f3cd7972d6b9c1a0607a862058c5a1bbcb13..c23097f04769ffb00721218dd9d6543725911144 100644 --- a/board/ronetix/imx7-cm/imx7-cm.c +++ b/board/ronetix/imx7-cm/imx7-cm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c index 136de3cf3ef22ad034606291054550089a5d907e..b94cfd6ffc6761adafab04aa12f836974aa84f91 100644 --- a/board/ronetix/imx7-cm/spl.c +++ b/board/ronetix/imx7-cm/spl.c @@ -5,6 +5,7 @@ * Author: Ilko Iliev */ +#include #include #include #include diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index fbee2c39771e628b3841350eee8faf21c1707a6d..9805a3a7da8cef09206e4f7012914f67d527f05b 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/ronetix/imx8mq-cm/lpddr4_timing.c b/board/ronetix/imx8mq-cm/lpddr4_timing.c index a7ad9375ce378a69181a0be51cc3a4ef17e3dbe7..685600ee62f545a2fb17285c0e7e0f517437d135 100644 --- a/board/ronetix/imx8mq-cm/lpddr4_timing.c +++ b/board/ronetix/imx8mq-cm/lpddr4_timing.c @@ -4,6 +4,7 @@ */ #include +#include #include #include diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index ee0ad20ced4ffc9b203de7348f0afe10225adc77..1c675bcab25a5b4860b916fa947b7a917afb6785 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -4,7 +4,7 @@ * */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index ee578749bce77f996c83156289474ee24f89ebd9..07febe69dc7c757c48a1630d6e90bf2e4e4da3fd 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -7,7 +7,7 @@ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 1de1bd6870163b020c6e93c709a40693a5525874..76f62ddde9125e7f5ff7ff4e783529d3aa390c43 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -7,7 +7,7 @@ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD */ -#include +#include #include #include #include diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f25307687f328ed8c3eb65cbb12437311..aa5c80ac64176734fb06532726795c7254cbcdda 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -10,7 +10,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687c9711b22d1999a8fe5c91b0d44f21..3ebf600e1d7c979810cdb372d6f5063724e1a31c 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -3,7 +3,7 @@ * Copyright (C) 2013 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/arndale/arndale_spl.c b/board/samsung/arndale/arndale_spl.c index c40ca7fa749cd97d7f756a38afe74bd81d49f4d0..6ad0273e0495f01e4bf13e76d6e1bffbdedc4863 100644 --- a/board/samsung/arndale/arndale_spl.c +++ b/board/samsung/arndale/arndale_spl.c @@ -3,6 +3,7 @@ * Copyright (c) 2012 The Chromium OS Authors. */ +#include #include #define SIGNATURE 0xdeadbeef diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa68902db3032fc9b5a70f6965c5640..5a71982775d05aed89962d7fd92ea19fb00e0986 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -4,7 +4,7 @@ * Rajeshwari Shinde */ -#include +#include #include #include #include diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 8328bf427cce2c02a78c21b0e1a76cd7b9cda074..9294d36ba358afa67e41213dd606d8912a93b558 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 56862bcb34daed5ac7507abbae6e37d36e5cb429..b3e87c9375139641046abaf904360f4d88e74f44 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c index c1b4342f4e229cd5bb3bc1923efb2c4a63f87f61..9487f9ec4e0cfb0bf17f1fe1b1c5c3e9811706c5 100644 --- a/board/samsung/common/gadget.c +++ b/board/samsung/common/gadget.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #define EXYNOS_G_DNL_THOR_VENDOR_NUM 0x04E8 diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index c134a9d70e249328cc774c1dbd0fdfa3d4fdb744..cc114aaaa6d388933278d15de66f4409d9b2b29d 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/common/sromc.c b/board/samsung/common/sromc.c index 689ac8f8c6f7f5bdc7e6c3fb970360863a587ee3..76e37dfe262af6b05cc72451c2bdcb58360ab854 100644 --- a/board/samsung/common/sromc.c +++ b/board/samsung/common/sromc.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_ETH +#include #include #include #include diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a27aeec75db14134f2dadfb7ee7830..c8f5a153bb47f8f8ba91b7ce19f0b356afadf58b 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -5,6 +5,7 @@ * Kyungmin Park */ +#include #include #include #include diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index 6c7a03624b0a93a9c0adb35a42a547442f75082c..c67c107b16c28a253854088e64bde32d23d9961f 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -4,7 +4,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 84d6d919f07f33fa4122910db31973a97358f29d..99e5613ced928e8e75b13b31d6e332840685e95f 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -4,7 +4,7 @@ * Przemyslaw Marczak */ -#include +#include #include #include #include diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index c474a7e54fa38477c7758575913e7e802e8a295f..ddf6a2b72fa5465ce270adff96673ab8bfea3da0 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 Samsung Electronics */ +#include #include #include #include diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c index 1c78cb6dda4f06d0ce8ccb1d6286c343a928f5ec..b0ef34dd6aa9fb33936fb929f7d49715fb2dafcd 100644 --- a/board/samsung/smdk5250/smdk5250_spl.c +++ b/board/samsung/smdk5250/smdk5250_spl.c @@ -3,6 +3,7 @@ * Copyright (c) 2012 The Chromium OS Authors. */ +#include #include #include #include diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c index ccf8b257ec26f6c9087ed6e13ffbb3e1ea42a891..84126f5608c70877670d44e977f73f69bc067598 100644 --- a/board/samsung/smdk5420/smdk5420_spl.c +++ b/board/samsung/smdk5420/smdk5420_spl.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 The Chromium OS Authors. */ +#include #include #include #include diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 86ec550aaca92ac52d4aad4db3a4d1ee9d09dcfa..04dc04a1a4a1cf7859d1bad0356a1e85cbca88f2 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -4,6 +4,7 @@ * Kyungmin Park */ +#include #include #include #include diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae1e6e4cd0dfd9bb4bc3e32bc2f72e0..4f46911b0b4d928f830b6afce9db94c9d282859d 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -5,7 +5,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cdf0a8d4c59f4421cd8b0074211ae15..47483a26a622dc215e62d939019f67f03fc789ce 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -3,7 +3,7 @@ * Copyright (C) 2011 Samsung Electronics */ -#include +#include #include #include #include diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 6efc6f3831dfc84ac8b58c34dc31e0a2d789df0e..6a3e5b29b9894c0f292ad3a44e6f845751106857 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -6,6 +6,7 @@ * Donghwa Lee */ +#include #include #include #include diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 612575a5094119b5fba3e5a17c18ad72ca08f1bd..81ccc124c809578a384276cb78b1f65f941a2978 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -5,6 +5,7 @@ * Piotr Wilczek */ +#include #include #include #include diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index ba56e86df4653d7cf3ba1feaf483aae6d0081489..265a2cde4b484813809ce26978f9bb13bbe73b1b 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -4,7 +4,7 @@ * Kyungmin Park */ -#include +#include #include #include #include diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 6bed724153ed0fecf9c1cbe09da360cb6dda2ac5..2d61dff89c2c03083927472164217b7a448a2915 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -5,6 +5,7 @@ * Kyungmin Park */ +#include #include #include #include diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c index e1d5b5b0497bd8b37ee6bb34f286104ed35b70af..09241c3a95459ead101775dd6777399a0bc31b82 100644 --- a/board/schneider/rzn1-snarc/rzn1.c +++ b/board/schneider/rzn1-snarc/rzn1.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/seeed/linkit-smart-7688/board.c b/board/seeed/linkit-smart-7688/board.c index 91fa08fd9ec2d75247eb22ed9db85511b8a432b5..bf7c69ea8389311541c8fc5d8c0d2de07b5bd368 100644 --- a/board/seeed/linkit-smart-7688/board.c +++ b/board/seeed/linkit-smart-7688/board.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Stefan Roese */ +#include #include #include #include diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c index 2312d8fac693af753cf14acc356ff54edeec2300..b29da2c1fc1eb29ccef04544219f085dc307081f 100644 --- a/board/seeed/npi_imx6ull/spl.c +++ b/board/seeed/npi_imx6ull/spl.c @@ -4,7 +4,7 @@ * Author: Navin Sankar Velliangiri */ -#include +#include #include #include #include diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 53dac8bfe1bee54bbabef6601da2504b9cbad350..b1d7e3b1c05a2faff527a8c16460a7f3f7b3ab76 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -5,6 +5,7 @@ * Copyright 2019 Siemens AG * */ +#include #include #include #include diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index 696b5ebd340b94fc18250a08ddb5b843850accfc..e160c611a962142d0c624feea70fd60bb4fc6203 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -5,6 +5,7 @@ * Copyright 2019 Siemens AG * */ +#include #include #include #include diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 7d73d1f2b361f3944b46e92362f598bdfab5e1a0..569b86db00ace7585fa90e93c707f3f3f11d0dcd 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -10,7 +10,7 @@ * Lead Tech Design */ -#include +#include #include #include #include diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index ed292c364a5fed46f63dcf6c7779805e3bf4772d..0b0686e2628b7dc7a01751d5a136d159740821a3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -8,7 +8,7 @@ * Jan Kiszka */ -#include +#include #include #include #include diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 946fbc3f2299a9e70795aade85adf001451c16ee..15044c7d0edf5e89796c93969cc86a21b0ffed45 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -15,7 +15,7 @@ * DENX Software Engineering GmbH */ -#include +#include #include #include #include diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index bda12a97708863ea8404f9ce89738f27a35863b8..ad44a7c0d28b01a14c771a7a79ebc07dc4ab8def 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/silinux/ek874/ek874.c b/board/silinux/ek874/ek874.c index a3fe6f96d091857b55f6e1c5994dc89fd576f29a..6dc804a0c06e160b5637ddd4137657ec99cd6a7e 100644 --- a/board/silinux/ek874/ek874.c +++ b/board/silinux/ek874/ek874.c @@ -6,8 +6,8 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ +#include #include -#include #include #define RST_BASE 0xE6160000 diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index 08077a1f9e131a21f44c5315e6000a441d68d894..06653b5a8765922d4efde12cd40d7e52868526f7 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -3,7 +3,7 @@ * Copyright (C) 2019-20 Sean Anderson */ -#include +#include #include #include #include diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c index 22be10d70a739d110a191ffaa0d0a8fe1b2d703b..abad5efdafb4100873e8a3a3e3d0451da109151e 100644 --- a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c +++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c @@ -3,6 +3,7 @@ * Board init file for Skyworth HC2910 2AGHD05 */ +#include #include #include #include diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e7745abc15d5509cc05cb06c223007..062e4a7b79faba9de300ae53daf96f73c36de0bd 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index bf4894eff671b84bbaf710a5a3969b48b6402b9a..3a94f7beccd339b7af28d8e972757890b873e4da 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -3,6 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ +#include #include #include diff --git a/board/socrates/law.c b/board/socrates/law.c index 446fdbcaba319184ca250f650d3b152287ac3bbb..e4427ecff1bc682a5761ad2d9b51e0a1f0804e42 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -9,7 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 517a4a0af6ab5bf505a1f7886c15fed2d764dd2e..b1e38c511e5f5f66d05330d1ede1e6fd38a7ef5c 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -4,7 +4,7 @@ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. */ -#include +#include #if defined(CFG_SYS_NAND_BASE) #include diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index d0415d26ce72701e51bcc6bc1b1356c59a6d44dd..61402a554b784420c6bb1010c2444c2e2e8df6ca 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -4,7 +4,7 @@ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. */ -#include +#include #include #include #include diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 6e6e276cc74118f2601c7d2d7996d3bc11282a93..1d63c81a9c81fde37e73cf813ac8c4cfb96e0f72 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -10,7 +10,7 @@ * (C) Copyright 2002 Scott McNutt */ -#include +#include #include #include #include diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index 0cc675781d160db476a11fad7b99aa8cc032ac82..631f6c3407553b3534a8ffd0cc4108f32979db87 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -9,9 +9,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include -#include struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index a0dbf97524bd20c7bf1a77fe199d41956e23c310..4483bd7f7a3829fb05b545c5c8cefd776c6f5069 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 2483fbcf263167ab0be7c4f2289777ebacd690d8..b3f9550742ec44a58ad60409fb1e58060f52e598 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Altera Corporation */ -#include +#include #include #include #include diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 2dbd071abd9f29cee97fb813a67d0190a620bd32..6977db0a9e28b4a879ca1580a14f6eeb58ca20a3 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ -#include +#include #include #include #include diff --git a/board/solidrun/common/tlv_data.c b/board/solidrun/common/tlv_data.c index b8086605c3aeeccdcdfb206be019189da1722d72..cf5824886c37d873c2ff39c35a3053120b076130 100644 --- a/board/solidrun/common/tlv_data.c +++ b/board/solidrun/common/tlv_data.c @@ -3,9 +3,9 @@ * Copyright 2020 SolidRun */ +#include #include #include -#include #include "tlv_data.h" #define SR_TLV_CODE_RAM_SIZE 0x81 diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 3406ba8616e05f4d2005932089239af3c16cde50..7f4811d88794c8ac312ec8f18b4e81bd9520cb18 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -15,7 +15,7 @@ * Ported to SolidRun microSOM by Rabeeh Khoury */ -#include +#include #include #include #include diff --git a/board/somlabs/visionsom-6ull/visionsom-6ull.c b/board/somlabs/visionsom-6ull/visionsom-6ull.c index 0ecb5c3b4930f8d43d8dcd72ab2c421cd5cda5d2..38d14f6bc268d18226a86d0d0fb788e8f0246bc2 100644 --- a/board/somlabs/visionsom-6ull/visionsom-6ull.c +++ b/board/somlabs/visionsom-6ull/visionsom-6ull.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c index 5603ef24da800fb2f4f89246112b982256e7ba3a..d9125a76bf7fe473b4323b0dca6a66d55ffe2e29 100644 --- a/board/sr1500/socfpga.c +++ b/board/sr1500/socfpga.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ +#include #include #include #include diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index 50da063051b802180d12b1cbbfef9c3bbd701519..c8c0bad5da16bd3cb9f5d4d126a1504d20183f13 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -30,6 +30,7 @@ */ #ifndef CONFIG_SPL_BUILD +#include #include #include #include diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index 1db8e45480e16874be49d32e3bfc1b856439a6fc..77edb86e78c1361e4f161f3ead263a5d7a490f58 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -3,6 +3,7 @@ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/board/st/common/stm32mp_dfu_virt.c b/board/st/common/stm32mp_dfu_virt.c index 4049d72bf9d5604e6dd93cb712c08669f6d47c09..f0f99605796a592bc531a3d5caa200ca036c877e 100644 --- a/board/st/common/stm32mp_dfu_virt.c +++ b/board/st/common/stm32mp_dfu_virt.c @@ -3,6 +3,7 @@ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 45c2bb5bceacbc77989a9ddbf65ea792934d96b6..969ad484864d80bd860468b31123ff25145f5413 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_BOARD +#include #include #include #include diff --git a/board/st/common/stusb160x.c b/board/st/common/stusb160x.c index e1ad8b00717a5ecfb9fe4cea771668e67f929ff8..f0385e5e3830bca4234cdd9d6b8b198b12381542 100644 --- a/board/st/common/stusb160x.c +++ b/board/st/common/stusb160x.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_I2C_GENERIC +#include #include #include diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index a912712c9dd902723ac5879c1c5a4318877152ee..82817571ae3d95e4d669620df94ec2adfd303534 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 4b8038341b9ed04e42e9a3a2ae5d3d813fe644c4..8dda6a97bd1c08dae98f595f08313bd43fb19f0e 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -4,6 +4,7 @@ * Kamil Lulko, */ +#include #include #include diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 22d751b44d3da5b0768149d99b8441ef14eb2aaf..55e464cc7cf1352ca81435c38cd3ed9834e81158 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -10,6 +10,7 @@ * Kamil Lulko, */ +#include #include #include #include diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index db59ebb838e76e836b842df334a1c98721eef839..25472f041fef099adec80a2c9a045e3bbc8efeb7 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 134d207d95d83ff2d65516d341f0420a4d2b41b1..9ed6c1e67680ac4acc61a106712c3689bf797183 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -4,6 +4,7 @@ * Author(s): Patrice CHOTARD, for STMicroelectronics. */ +#include #include #include #include diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 6d86e4fe7aab411dfb91c6dff689603382cd230a..0f9666008430588e60efd95ccca848985acf7d5f 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -4,7 +4,7 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ -#include +#include #include #include #include diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 35ef9ff9e288e9b79b02a3677da8efa599a09f6b..4ca5e847212ea7d1ed57f937375e06e11d4f990c 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 35ef9ff9e288e9b79b02a3677da8efa599a09f6b..4ca5e847212ea7d1ed57f937375e06e11d4f990c 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 75aa4d139fb4061bcc749334a8f27ac405db3d39..0d39ce849a62d8e58f7b973df78cfadb0aa5776d 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -4,6 +4,7 @@ * Author(s): Dillon Min */ +#include #include #include #include diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index d63dffd97e87f4a74b5e449e1f3fe9124fb11a50..8b4a529f759a28bd3a00302686c4e95d5d488349 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 97532a8156ffcc73f7536023dfb8576b6fb5222c..db15d78237ea20556e04246989214b4e896b7d5e 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY LOGC_BOARD +#include #include #include #include diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig index 2186a939646d0c380015ed6cb3fbf0602ede7b58..d7e8a7a7d78649a4876dcd496bed66bee317e1e0 100644 --- a/board/starfive/visionfive2/Kconfig +++ b/board/starfive/visionfive2/Kconfig @@ -50,4 +50,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC +config STARFIVE_NO_EMMC + bool "Report eMMC size as zero" + help + The serial number string in the EEPROM is meant to report the + size of onboard eMMC. Unfortunately some Milk-V Mars CM Lite + modules without eMMC show a non-zero size here. + + Set to 'Y' if you have a Mars CM Lite module. + endif diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index ca61b5be227def8c1aa003f1dcda4575e560e153..b555189556a6e2b6b27e192ee00b8731012b16d9 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -129,6 +129,30 @@ void spl_fdt_fixup_mars(void *fdt) } } +void spl_fdt_fixup_mars_cm(void *fdt) +{ + const char *compat; + const char *model; + + spl_fdt_fixup_mars(fdt); + + if (!get_mmc_size_from_eeprom()) { + int offset; + + model = "Milk-V Mars CM Lite"; + compat = "milkv,mars-cm-lite\0starfive,jh7110"; + + offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); + /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ + fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); + } else { + model = "Milk-V Mars CM"; + compat = "milkv,mars-cm\0starfive,jh7110"; + } + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); +} + void spl_fdt_fixup_version_a(void *fdt) { static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110"; @@ -236,7 +260,9 @@ void spl_perform_fixups(struct spl_image_info *spl_image) pr_err("Can't read EEPROM\n"); return; } - if (!strncmp(product_id, "MARS", 4)) { + if (!strncmp(product_id, "MARC", 4)) { + spl_fdt_fixup_mars_cm(spl_image->fdt_addr); + } else if (!strncmp(product_id, "MARS", 4)) { spl_fdt_fixup_mars(spl_image->fdt_addr); } else if (!strncmp(product_id, "VF7110", 6)) { version = get_pcb_revision_from_eeprom(); diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index a86bca533b2ff43c8be89306b6e4953cb2c99636..6be534896260d318219648b12e64b01fda0cb474 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; #define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 #define FDTFILE_MILK_V_MARS \ "starfive/jh7110-milkv-mars.dtb" +#define FDTFILE_MILK_V_MARS_CM \ + "starfive/jh7110-milkv-mars-cm.dtb" +#define FDTFILE_MILK_V_MARS_CM_LITE \ + "starfive/jh7110-milkv-mars-cm-lite.dtb" #define FDTFILE_VISIONFIVE2_1_2A \ "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ @@ -61,7 +65,12 @@ static void set_fdtfile(void) log_err("Can't read EEPROM\n"); return; } - if (!strncmp(product_id, "MARS", 4)) { + if (!strncmp(product_id, "MARC", 4)) { + if (get_mmc_size_from_eeprom()) + fdtfile = FDTFILE_MILK_V_MARS_CM; + else + fdtfile = FDTFILE_MILK_V_MARS_CM_LITE; + } else if (!strncmp(product_id, "MARS", 4)) { fdtfile = FDTFILE_MILK_V_MARS; } else if (!strncmp(product_id, "VF7110", 6)) { version = get_pcb_revision_from_eeprom(); diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 5095a0e9fdb0fa770779f517eed2c45da8b6741d..838f41e41bd4fd8c82e84f01865562cd52e38a7f 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -404,6 +404,24 @@ static void set_product_id(char *string) update_crc(); } +/** + * set_vendor() - set vendor name + * + * Takes a pointer to a string representing the vendor name, e.g. + * "StarFive Technology Co., Ltd.", stores it in the vendor field + * of the EEPROM local copy, and updates the CRC of the local copy. + */ +static void set_vendor(char *string) +{ + memset(pbuf.eeprom.atom1.data.vstr, 0, + sizeof(pbuf.eeprom.atom1.data.vstr)); + + strncpy(pbuf.eeprom.atom1.data.vstr, + string, sizeof(pbuf.eeprom.atom1.data.vstr) - 1); + + update_crc(); +} + const char *get_product_id_from_eeprom(void) { if (read_eeprom()) @@ -463,6 +481,9 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } else if (!strcmp(cmd, "product_id")) { set_product_id(argv[2]); return 0; + } else if (!strcmp(cmd, "vendor")) { + set_vendor(argv[2]); + return 0; } return CMD_RET_USAGE; @@ -548,6 +569,24 @@ u32 get_ddr_size_from_eeprom(void) return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL); } +u32 get_mmc_size_from_eeprom(void) +{ + u32 size; + + if (IS_ENABLED(CONFIG_STARFIVE_NO_EMMC)) + return 0; + + if (read_eeprom()) + return 0; + + size = dectoul(&pbuf.eeprom.atom1.data.pstr[19], NULL); + + if (pbuf.eeprom.atom1.data.pstr[21] == 'T') + size <<= 10; + + return size; +} + U_BOOT_LONGHELP(mac, "\n" " - display EEPROM content\n" @@ -568,7 +607,9 @@ U_BOOT_LONGHELP(mac, "mac bom_revision \n" " - stores a StarFive BOM revision into the local EEPROM copy\n" "mac product_id \n" - " - stores a StarFive product ID into the local EEPROM copy\n"); + " - stores a StarFive product ID into the local EEPROM copy\n" + "mac vendor \n" + " - set vendor string\n"); U_BOOT_CMD( mac, 3, 1, do_mac, diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d69f624c19bff24257b5382a4d61f4..060d562cbc9024eed242006555dad92abbffc403 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -2,12 +2,12 @@ /* * Copyright (C) 2019 Stephan Gerhold */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c index 910feeda31f5410b8b79d2f229d5077ebd2ae0ac..345191b31c29b521d3786e54f3822211c2ca6029 100644 --- a/board/storopack/smegw01/smegw01.c +++ b/board/storopack/smegw01/smegw01.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ed86f1df5dc4197ca914b03de9ebecfddc32db1f..1313b01dcea555a9818eeceaf2c8b95497f8cc85 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -10,6 +10,7 @@ * Some board init for the Allwinner A10-evb board. */ +#include #include #include #include diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c index 270af2506d21a777065ec48742883871445eb50e..eeee6319e7991748e283c44cc5bd15a691124d69 100644 --- a/board/sunxi/chip.c +++ b/board/sunxi/chip.c @@ -5,6 +5,7 @@ * Based on initial code from Maxime Ripard */ +#include #include #include #include diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 4b78919a5baac2772f3d8b6e092295e60a685b1f..547d1c0cb4dea3fe2a261b47f0e9c8769f302824 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -1,3 +1,4 @@ +#include #include #include diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index 8976e3b16d68b25bd30cba50eeb1cba8e4b22c92..517506ccc4f0f5f457a51d5fb452fbe2b36768aa 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -1,5 +1,6 @@ /* DRAM parameters for auto dram configuration on sun5i and sun7i */ +#include #include #include diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 710e821e3fc8977fdb46c87c740c8b7d07d8a8fd..2a885305ebe028f071b1c2f970cd523fb3cac325 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index d5aa1f0776fd51ab7273aa0322e69e5cbffa4518..086421d9265daac82389183887a2a16d1630ec62 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -7,7 +7,7 @@ * This file copies memory testdram() from sandburst/common/sb_common.c */ -#include +#include #include #include #include diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index 7818f2671d5ad77b876945ad4bdf5384756f88cd..475e3edfa62e574c3cffe10b54ea8e83bde2e781 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -5,7 +5,7 @@ * (C) Copyright 2017 Angelo Dureghello */ -#include +#include #include #include #include diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index 2e54ede62d6f9c84d4eaa2f1bfe86f2d83cff0a6..3f7d42f3eb8d498d613f15779a18871105222a47 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c index 6d89c4a3998dea322ec0600df699fccd7916ba76..ab9088145abaf11db1ded69b82328310557bc08f 100644 --- a/board/tcl/sl50/mux.c +++ b/board/tcl/sl50/mux.c @@ -5,6 +5,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c index 03170b148c52ee530c1dbf772026ca8f54d8325e..6b9c4f4373cc5f612b1eb6cdddb4ef7c069680c7 100644 --- a/board/technexion/pico-imx6/pico-imx6.c +++ b/board/technexion/pico-imx6/pico-imx6.c @@ -6,6 +6,7 @@ * Author: Fabio Estevam */ +#include #include #include #include diff --git a/board/technexion/pico-imx6/spl.c b/board/technexion/pico-imx6/spl.c index 50f5177426479e18f9b10070f1e910f29440421d..3b36bb8df131ff35dcb766b1591c5e3a1b742176 100644 --- a/board/technexion/pico-imx6/spl.c +++ b/board/technexion/pico-imx6/spl.c @@ -6,6 +6,7 @@ * Fabio Estevam */ +#include #include #include #include diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 10dcf8077e20e1cae2de06102d111d3ede75993d..682c88dee78d1c4a630735177e1604de214c38fb 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 67484e62dad693d1765bff9057b826f608438466..ff56fd88d68ed21fea9382488cd5698b7e47da6a 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index d0f739c624a1e17ed561d4281decac88a1a94adc..b12941ccf82d34b8959148909abcd396c677f3c1 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 8f219f76c6038ec75c3f5b85c539e5d4691abee3..0192eafbaa146e4fe897d849b5278ce1e64c6362 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -5,7 +5,7 @@ * Author: Richard Hu */ -#include +#include #include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c index cd8ba59f6454fdbf685ddeefd49f95658d917261..97b9ee27527a5e7fa0a99f094b44340aefdd38ee 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_1gb.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c index 3f66238a5044f91fcb0e51e30b6b02248913c81c..1572a50a05f8281ee9003948781f291f63d3d6e8 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_2gb.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c index 2f037abc97dd250735da3bedbeaa8cf1ff0fa330..3fc60a3eeb9809e93b91ba70c4b5ba356b46102b 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_3gb.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c index 336ac4c2f5489ff488de522eef97941695ad3a3d..93b342351628c86a5cc5481e4ae6a5d04ede5d9b 100644 --- a/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c +++ b/board/technexion/pico-imx8mq/lpddr4_timing_4gb.c @@ -7,6 +7,7 @@ */ #include +#include #include #include diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 1659db112fa150a24dc35e1bbba7ef852bfd0328..2be3206f78a3e27779621d9cd8ae8efdc58e081f 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index c9d68b402aeba2a7497d1310ae2e545f9947740e..1a9c7996cb2a8a9c7210d2d089a7f11d95353758 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/board/terasic/de1-soc/socfpga.c b/board/terasic/de1-soc/socfpga.c index 8d17f44fd373445f3722f110917cad2643e82b85..22fbee40aba9381cb41845417dc64948d208cbda 100644 --- a/board/terasic/de1-soc/socfpga.c +++ b/board/terasic/de1-soc/socfpga.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2012 Altera Corporation */ +#include #include void board_boot_order(u32 *spl_boot_list) diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c index bb83e7561f4e75a91e0c59d065a2513d9b6a2d08..16c3e456b3e590be95a153c988558b5c5e881d69 100644 --- a/board/thead/th1520_lpi4a/board.c +++ b/board/thead/th1520_lpi4a/board.c @@ -4,6 +4,7 @@ * */ +#include #include int board_init(void) diff --git a/board/theadorable/fpga.c b/board/theadorable/fpga.c index 56d3647227bb50bbc11315ddbe256a22356c116d..bc8379cccf6d85d7891719611932bd2d1e236fff 100644 --- a/board/theadorable/fpga.c +++ b/board/theadorable/fpga.c @@ -3,10 +3,10 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include -#include #include #include #include diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index cca5c3d33b5ee073c66329622de64b9fc14bce34..144f122bb20643d46096593e8d4f42e030915755 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2019 Stefan Roese */ +#include #include #include #include diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 34f4a919656e66b78ffeaa8f5ffb5496531796a0..34f987c2b72820384666730c72135b4a8eb9eeae 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index b0a3842423fb3e47945d78c513336b1e74a7693c..1284c160d8116367ddf00a7441a5aff8a3699bc7 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -10,8 +10,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include - /** * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 960de15398f8173bf8a5d55beb3536f97465c38d..0bad154f86ed23051d658a71c3263b41a832704d 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 40b7fcfc3876f9061242fc93043d381c5a8d69a0..a4679a2e29489ee850a71295d99de03d87240b85 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -7,7 +7,8 @@ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include +#include #include #include #include diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index b1025bdda1e1d7db487d3a935516bfeb57815568..37a169aaf758b376925215dcd5750ffdcc204e67 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -11,7 +11,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include #include #define DEV_ATTR_MAX_OFFSET 5 diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 2fcccbd1f043b77bb77b7b0272b03a4dc4e66822..463f1cc71784e713b427ce0ca585940c6dd49d07 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -5,6 +5,7 @@ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include "../common/board_detect.h" diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 48668884bdd5bb0eac5bcb97a280ad0c9f7235eb..b004a89bb324c57c4dca613ef2554a5c63129eca 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -7,7 +7,7 @@ * Based on board/ti/dra7xx/evm.c */ -#include +#include #include #include #include diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index ea21d48bbc01593c7cc88ecc512b83187910dfaa..38e23ccbb67ce6b9ea636bafaf6e16261e80089a 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -7,9 +7,10 @@ * Steve Kipisz */ +#include +#include #include #include -#include #include #include #include diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c index da805befabcbb6dd3c57ac17d7cd58238e43226e..2e6105cfbf1567c072e97a19e5f48f542efefab5 100644 --- a/board/ti/common/cape_detect.c +++ b/board/ti/common/cape_detect.c @@ -4,11 +4,10 @@ * Köry Maincent, Bootlin, */ -#include +#include #include #include #include -#include #include "cape_detect.h" diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 2b1db2541b0b7ddd28f7e5ede7a608c5de71cc2e..a8a216d034a45de85ce5b96d731ad34b290ab2e5 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -9,7 +9,7 @@ * Aneesh V * Steve Sakoman */ -#include +#include #include #include #include diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index c6735d37dda7a0080be133eaaaa2ee9a08dc9275..5dcda12105b9ebd77d3d7984886cee1ae67b744c 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -6,7 +6,7 @@ * Texas Instruments Incorporated, */ -#include +#include #include #include "board.h" #include diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 4385be4221b722ee6d64769e69492882f2394e91..39abb24e15604e5aa3b8403c96a3df864c8c4f23 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index d07b77d23e27f734fa381dd08486ad0ca5695d56..5229afad63b0e8149ee96445fb6c6df30736becd 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -5,7 +5,8 @@ * (C) Copyright 2015 * Texas Instruments Incorporated, */ -#include +#include +#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index 2b5d2d75664976a1587cf2129b1c60ada56b8e8e..12c4649c3c4c14641153c33f2fbe206c70ae9c78 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 1971bc94f7d3c2e2bfe5afffd13401278687c512..f759ee364666ebaf9eeda7d4ea108eae555b5d16 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index fe350fee795ec79cb13d7771932bde6d59658958..0ade75263f8d67e9b81eac9af55dd9408964b87a 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include "ddr3_cfg.h" diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 28305326e6a18bdce96679cfe79afc50e1ba8cfd..95fe3a9021e237c2e4eca5819ce97ee82dc3ab8d 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include "ddr3_cfg.h" #include diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c index ef39e07815214ff64e8e9ea7a31e70de73279c0b..3000d7245eb21202a9168f563168acaf197e6f19 100644 --- a/board/ti/ks2_evm/ddr3_k2g.c +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include "ddr3_cfg.h" #include #include diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 05c050cee44061b72bd10b56790690897b44428c..198c5da0e62204a471080da230e4a69d0eaf1199 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include "ddr3_cfg.h" #include #include diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c index aa6d45f0f8af310e8442755cc2a1642863e4a8a1..805bf81f6bdf400cfb50fc899b9d224c69dc3d48 100644 --- a/board/ti/ks2_evm/ddr3_k2l.c +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include "ddr3_cfg.h" #include diff --git a/board/ti/omap3evm/evm.c b/board/ti/omap3evm/evm.c index 4eb08add25649dc5c6e8575b31030034aff81305..a4d6a0138d9b6f73c904a1d149ddd70694ae4d36 100644 --- a/board/ti/omap3evm/evm.c +++ b/board/ti/omap3evm/evm.c @@ -10,7 +10,7 @@ * Richard Woodruff * Syed Mohammed Khasim */ -#include +#include #include #include #include diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index e47d3a952d5ce5233154aed2b720d719e06a55f5..2209318601903a5f253b6b52e4f32ea680c5fe1f 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -4,6 +4,7 @@ * Texas Instruments Incorporated, * Steve Sakoman */ +#include #include #include #include diff --git a/board/ti/sdp4430/cmd_bat.c b/board/ti/sdp4430/cmd_bat.c index 6bf44d926550ab6dc78bc96b8cb4bc72ebf7da70..6c1e6ca393c66b3183b76ddc1272897a2f58c342 100644 --- a/board/ti/sdp4430/cmd_bat.c +++ b/board/ti/sdp4430/cmd_bat.c @@ -3,6 +3,7 @@ * Copyright (C) 2010 Texas Instruments */ +#include #include #ifdef CONFIG_CMD_BAT diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 1a71390f543bd313f37188dc07893a5fbcaaa127..2c9ae794fd4b1880f65c2722492918b1b2d0cf2b 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -5,6 +5,7 @@ * Aneesh V * Steve Sakoman */ +#include #include #include #include diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index f0c0f03deeb8da6b5b0b3ffe1357595a374d9f73..efef855b3d06817a323b7a42daffaacd003d93c7 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -5,7 +5,7 @@ * Copyright (C) 2011-2015 Vladimir Zapolskiy */ -#include +#include #include #include #include diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c index 07a367c3ad158b0285576c6646519e058fcc0c13..12e8ae9c39cb9e20104c4f71f09dede8c4b9208c 100644 --- a/board/timll/devkit3250/devkit3250_spl.c +++ b/board/timll/devkit3250/devkit3250_spl.c @@ -5,6 +5,7 @@ * (C) Copyright 2015 Vladimir Zapolskiy */ +#include #include #include #include diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index ad404f7e9c4c7701c35c57dffa52f6a2c95429aa..06009d8ad54c37069bcbe21c7a3bace5ea04e0d7 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -15,7 +15,7 @@ * Syed Mohammed Khasim * */ -#include +#include #include #include #include diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 72d67d90d418306d605c05735a97dbcf25f01d4f..0f993e644d71b7cece48add5d26af96e06530af2 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -3,6 +3,7 @@ * Copyright 2019 Toradex */ +#include #include #include #include diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 4557ed1f1f2ff17f57e94bbbd3211d8469257f62..ee87d9f4145f30162a56e5b4f2bb5cb9e8e4b8d7 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -3,6 +3,7 @@ * Copyright (c) 2016-2018 Toradex, Inc. */ +#include #include #include #include diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c index 8971f7aa16a1458fcfb520ddfb7994e906f597b5..e9bd1028bed5013658aba7a871c81bf410876770 100644 --- a/board/toradex/apalis-tk1/as3722_init.c +++ b/board/toradex/apalis-tk1/as3722_init.c @@ -3,6 +3,7 @@ * Copyright (c) 2012-2016 Toradex, Inc. */ +#include #include #include #include diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 2dcc042ab266f6aedb90729fef684eae7071b56a..0da245374a0d9387b2995e046e76c9bd66b0baca 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -6,7 +6,7 @@ * copied from nitrogen6x */ -#include +#include #include #include #include diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index b404b01e032e5aae1d7dc262cd6a737d79ba482b..6991b1bc136ef49153a4fabaf5a650d81856f0c8 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -7,6 +7,7 @@ * Helpers for i.MX OTP fusing during module production */ +#include #ifndef CONFIG_SPL_BUILD #include #include diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c index 157aaec6fe08b016710d5943805bb91d2af3cbaf..c89052ff5daa669770f4c872f151214285fcd723 100644 --- a/board/toradex/apalis_imx6/pf0100.c +++ b/board/toradex/apalis_imx6/pf0100.c @@ -7,6 +7,7 @@ * Helpers for Freescale PMIC PF0100 */ +#include #include #include #include diff --git a/board/toradex/apalis_t30/apalis_t30-spl.c b/board/toradex/apalis_t30/apalis_t30-spl.c index 250494524952b398372d0faace4ceea25737b671..6e544641833e7184f980492ac0df97f87f5be862 100644 --- a/board/toradex/apalis_t30/apalis_t30-spl.c +++ b/board/toradex/apalis_t30/apalis_t30-spl.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 02e8f8eb1fed9c64e49d99017cb6debae2023c32..b10beb447965173e5e9a8f25db3c8df0adce6a84 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -4,6 +4,7 @@ * Marcel Ziswiler */ +#include #include #include #include diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 7bfe200d6e4cab95cbde6eebb3773925341cf444..9b9fb342c9d9dbd1f96e4bcb5f092b59dde771c7 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2018-2019 Toradex AG */ -#include +#include #include #include #include diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 2a71e7b92de425b4759f07b29d833049d38e008b..35657852595128f5f860615149fdf3393ee3f870 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -3,6 +3,7 @@ * Copyright 2019 Toradex */ +#include #include #include #include diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 34e82c2b0780639e189d65990f60746817557b08..ce19a9c797523ae37fb0944b3f1fdd5ed3010068 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -6,7 +6,7 @@ * copied from nitrogen6x */ -#include +#include #include #include #include diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index b404b01e032e5aae1d7dc262cd6a737d79ba482b..6991b1bc136ef49153a4fabaf5a650d81856f0c8 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -7,6 +7,7 @@ * Helpers for i.MX OTP fusing during module production */ +#include #ifndef CONFIG_SPL_BUILD #include #include diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c index 58b7bc3bb9ae25815b3a4f624707b73f17c0a885..8f08d8c7337c1b9e7ac7ae2afb66bec48db383dd 100644 --- a/board/toradex/colibri_imx6/pf0100.c +++ b/board/toradex/colibri_imx6/pf0100.c @@ -7,6 +7,7 @@ * Helpers for Freescale PMIC PF0100 */ +#include #include #include #include diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index e966ffbf7818af0b382a8f0e50de716e780aa713..c37c5e0af6d9db06ad4ec052dba312310f028b9e 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -3,6 +3,7 @@ * Copyright (C) 2016-2018 Toradex AG */ +#include #include #include #include diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 6425fa881ea6a90ee035276bc5c6a809b9236483..97e33d00f0d6fc836178424357323b20fccb07f9 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 Lucas Stach */ +#include #include #include #include diff --git a/board/toradex/colibri_t30/colibri_t30-spl.c b/board/toradex/colibri_t30/colibri_t30-spl.c index 250494524952b398372d0faace4ceea25737b671..6e544641833e7184f980492ac0df97f87f5be862 100644 --- a/board/toradex/colibri_t30/colibri_t30-spl.c +++ b/board/toradex/colibri_t30/colibri_t30-spl.c @@ -7,6 +7,7 @@ * Svyatoslav Ryhel */ +#include #include #include diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 342673ac506ca781f51ecc44c468afccdf486a74..0da247de98f91e0b338120e872a714c33ce0beb1 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -4,6 +4,7 @@ * Stefan Agner */ +#include #include #include #include diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 87f82396d63aa38d5cd321f9282528047ee42367..35920008805fd2a3f199b2a6cfac05317f7923bb 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 2225cefec16784d3cc54518352327b7c4d809099..dcf00d2b632571aa5138381e390e71e6fe71e1c8 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -3,7 +3,7 @@ * Copyright (c) 2016-2020 Toradex */ -#include +#include #include #include "tdx-cfg-block.h" #include "tdx-eeprom.h" diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a6b45cdab810ae494852139fd79442281b16b257..9f09788137d595368b0301e3d8ed627d12176764 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 1020078afea27678b86f5ad5f3e37488cf5d2eb4..afa3686083a44173fde5b8c0bafef1304fa99d63 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -3,6 +3,7 @@ * Copyright 2020 Toradex */ +#include #include #include #include diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 020ee67748076ff870a7450b9343ded6fdcc91fb..55c02653da6864398c2d3f25777ad0d014d298b1 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -3,7 +3,7 @@ * Copyright 2020-2021 Toradex */ -#include +#include #include #include #include diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 8628112a78258cdbb935761467522033fe6b7593..73729a42b458bab93522d8d98211aa71b88237df 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -3,6 +3,7 @@ * Copyright 2022 Toradex */ +#include #include #include #include diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e57ec3b689678162e0a5dfbf09e4e7197216c4e4..e16a771e3ec16c22928de5b3141c878e297a60b8 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -3,7 +3,7 @@ * Copyright 2022 Toradex */ -#include +#include #include #include #include diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index 3ae0dc4ecd73cceb8cd93c4f005547a0b8a6b33a..f2de039b6b4752266b8af89f392ac35d14137b64 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Marek Vasut */ +#include #include #include #include diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 92142c10ae5aa59fc98ac64931c2587bd17281e9..1c2228c77ad07422650e8fe17c9cedbf7d14d72c 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 877539e359e2321201cdb34c78c390f8fb7a04b0..52851dd5b55e9fcd216bc43bbae97544108be2a2 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c index 21c710188e091928cf3e169a8ae46482677d7d80..5d239913fc5b6fccf1189fd4268e927cc9252f0b 100644 --- a/board/tq/tqma6/tqma6_wru4.c +++ b/board/tq/tqma6/tqma6_wru4.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include diff --git a/board/traverse/common/ten64_controller.c b/board/traverse/common/ten64_controller.c index 63b72c4df7b94c9801a97ba073319c8574c7c186..d6ef8a8d0df99a18e7e3f0443ccfefd3b89a1a64 100644 --- a/board/traverse/common/ten64_controller.c +++ b/board/traverse/common/ten64_controller.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/board/traverse/ten64/eth_ten64.c b/board/traverse/ten64/eth_ten64.c index c5f7acecc146326a1696dbce890361bcc9993bc5..3f96e572b75a58087e43ba5df5ac321b2dfe9ab9 100644 --- a/board/traverse/ten64/eth_ten64.c +++ b/board/traverse/ten64/eth_ten64.c @@ -3,6 +3,7 @@ * Copyright 2017 NXP * Copyright 2019-2021 Traverse Technologies Australia */ +#include #include #include #include diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index d41bd2e9deeb4e330638e8c90546606ef9a96306..6ff5312d6d798b92f37ed511325fd8c319bde08f 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -4,7 +4,7 @@ * Copyright 2017-2018 NXP * Copyright 2019-2021 Traverse Technologies */ -#include +#include #include #include #include diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index b435b721e53c8e9ae2c72cbbcee616cc026d4eaa..d99d93b44ae57f9e2920490317f05a13b1327405 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index 6c477530055c4cbc06ac1936f2ec314f70a13f4d..647380e1db63f5fdbbcb2978e4bd9b60fa6c86e6 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -6,6 +6,7 @@ * Based on board/wandboard/spl.c */ +#include #include #include #include diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c index 6d17563d32c072c0f78e386f1594da133557d4c1..1dff69c82771f5d0e69cd257a8c6ca2f596c4207 100644 --- a/board/variscite/dart_6ul/spl.c +++ b/board/variscite/dart_6ul/spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2019 Parthiban Nallathambi */ -#include +#include #include #include #include diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 532d8d60a76266138cef80cc44b38b2ccbaf219c..994fd4f705820c3301dab67526ca472185282a6f 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -5,6 +5,7 @@ * Copyright 2023 DimOnOff Inc. */ +#include #include #include #include diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 2c91e9fac43d120c0010087f10c5f06a02838811..bc7dc5888f2dac783dfc0e3e78aeee01a324b408 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -7,7 +7,7 @@ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ -#include +#include #include #include #include diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c index 77b142f08f0ad92547fc4872efda75ba4e2b2ebe..7b99cf0e182faec94b571e43ac89c42965907dfb 100644 --- a/board/vscom/baltos/mux.c +++ b/board/vscom/baltos/mux.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 9ce2785a4f0495f70577e5e3a3259bc475a37c00..717e02a039b7ce05aac482a479fb244dc077d40b 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -5,7 +5,7 @@ * Richard Hu */ -#include +#include #include #include #include diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index a48ef33ffdec22cb8d464e316901920dc5237aa5..8be62c86695d4ef119de2f8c0e4999e39927aad9 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -6,6 +6,7 @@ * Author: Fabio Estevam */ +#include #include #include #include diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 4cd3ff0051b765e5cb8407739cafe1684c396c3f..ead52d5a490c20b87efa81b9b7971371a170e64e 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index 9a236880e3cc26e61c2156210abfcb0d739c0955..c8e791a4da8ab4285a6a534a6a78e8a17fa62820 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -6,7 +6,7 @@ * Written-by: Albert ARIBAUD */ -#include +#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c index d4ab2299895d593dd0c1050ad833b9d90147f4c7..64dd5d4072a6e56ba6ad1303e994be405c6a02f7 100644 --- a/board/work-microwave/work_92105/work_92105_display.c +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -10,6 +10,7 @@ * MAX518 I2C DACs and native LPC32xx GPO 15. */ +#include #include #include #include diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c index 3f91221ce8b13403b03671e99a6785959a4a1279..d9401145f27d2cb444971aa89c3ea9feefb2bf78 100644 --- a/board/work-microwave/work_92105/work_92105_spl.c +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -6,6 +6,7 @@ * Written-by: Albert ARIBAUD */ +#include #include #include #include diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 4c3b9c9e278006cafd14b98b536e35bc24ea810a..1d2946f4fde808eb24a11aaf1caa26261dd6dc53 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -7,6 +7,7 @@ * (C) 2020 EPAM Systems Inc */ +#include #include #include #include diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 30a81376ac4183dce46d7655d92760079737c840..b47d2d23f913dbff20250e762947573c9ca20873 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -6,6 +6,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/board/xilinx/common/cpu-info.c b/board/xilinx/common/cpu-info.c index 765bb24d9376647f0b7519378c11ec75b1ec7e6d..bfe7f5b7e385c62ac709c83178ca918e4e7c7a96 100644 --- a/board/xilinx/common/cpu-info.c +++ b/board/xilinx/common/cpu-info.c @@ -4,6 +4,7 @@ * Michal Simek */ +#include #include #include diff --git a/board/xilinx/common/fru.c b/board/xilinx/common/fru.c index 8cf307e33f200837c868c95f9743b76628adcdd6..12b21317496a834b3ed0d7758c1c0ba4c4743357 100644 --- a/board/xilinx/common/fru.c +++ b/board/xilinx/common/fru.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 - 2020 Xilinx, Inc. */ +#include #include #include #include diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index 610293bccf78d96c2f2e5826dae54f115ba41868..167252c240cd95f38c0d1723ea87f0af49895b98 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -4,13 +4,13 @@ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. */ +#include #include #include #include #include #include #include -#include #include #include diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 88e10fa7a7fae1a132fb944358a3273a597e74e0..da03024e162f3c3f9a3b89207c6b79464d85866a 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -6,6 +6,7 @@ * Michal Simek */ +#include #include #include #include diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c index 4d52084846b7a592b053e3e364997a0fbfc8929f..b18a71fe52c0bede1171fae0aec727fb373b160d 100644 --- a/board/xilinx/versal-net/cmds.c +++ b/board/xilinx/versal-net/cmds.c @@ -7,10 +7,10 @@ #include #include +#include #include #include #include -#include #include /** diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 77ba783501ebb77cc2443131ba3e00ab65bc0319..4f6d56119db10f909a16480bdba7837907f0e131 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/board/xilinx/versal/cmds.c b/board/xilinx/versal/cmds.c index c78793573e86c26dbc74d30301e494989881077f..2a74e49aedec27389f465b778ede60a79275fdd3 100644 --- a/board/xilinx/versal/cmds.c +++ b/board/xilinx/versal/cmds.c @@ -6,10 +6,10 @@ #include #include +#include #include #include #include -#include #include static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index b9a91110ff792ad3d0621f3597f402cca34c61cc..6c365910011d916200c39ce26c885fb7b733a269 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -4,7 +4,7 @@ * (C) Copyright 2013 - 2018 Xilinx, Inc. */ -#include +#include #include #include #include diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c index 79bec3a4cfbc8ddc73159bcdbaedcb20d1df353e..2f55078dd768cdad4365750cda7f4eea86693cf6 100644 --- a/board/xilinx/zynq/bootimg.c +++ b/board/xilinx/zynq/bootimg.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. */ +#include #include #include #include diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b46f3ee5beead7eec7d849172c2c96..d7c7b2f229555788812cc6db50a94dd6297e86d9 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. */ +#include #include #include #include diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index bf39c5472ea9649ed286c86a3ff777da1f677370..9524688f27d9c1d7e42c8f5fb7c0679fe20717ab 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -4,14 +4,13 @@ * Siva Durga Prasad Paladugu > */ +#include #include #include #include #include #include -#include #include -#include #include #include #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c4050af2a5a5271a85b3ab7de6d1a9aef1989fbd..f370fb7347a5470492dea377d63db2719599a2bd 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -4,7 +4,7 @@ * Michal Simek */ -#include +#include #include #include #include diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c index 0c62b0013c46360e5247589f212ea01a5e25d4ad..5c5a2e93863f2c687ab895de764fd08c4e19f78a 100644 --- a/board/xilinx/zynqmp_r5/board.c +++ b/board/xilinx/zynqmp_r5/board.c @@ -3,9 +3,9 @@ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) */ +#include #include #include -#include int board_init(void) { diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c index d018b5738242c6f131a446f5c4cde5c5cd2e25c9..b3ea6608914a1a4264086a241e63ac430c53f392 100644 --- a/board/zyxel/nsa310s/nsa310s.c +++ b/board/zyxel/nsa310s/nsa310s.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Gerald Kerma */ +#include #include #include #include diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c index 38340b33c8bf5bccb5ed60b5d42b97e17cdd8056..f5f63ee5d3b00469c9c11f8057e90e19329e8d6f 100644 --- a/board/zyxel/nsa325/nsa325.c +++ b/board/zyxel/nsa325/nsa325.c @@ -14,6 +14,7 @@ * Marvell Semiconductor */ +#include #include #include #include diff --git a/boot/android_ab.c b/boot/android_ab.c index 143f373aae96f9ea5bac04c660148a0fb413ce10..1e5aa81b75033564b68d51f18a02e80b56c9067c 100644 --- a/boot/android_ab.c +++ b/boot/android_ab.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2017 The Android Open Source Project */ +#include #include #include #include diff --git a/boot/boot_fit.c b/boot/boot_fit.c index 4dcaf95c6ae3059ec625a4369e5c629aa42ce746..9d3941265636196e5321f38521291b373ba475fa 100644 --- a/boot/boot_fit.c +++ b/boot/boot_fit.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 7c7bba088c999f96862b6bb76616e9d0c3e6b13a..46815ea2fdbfc4964a39932a7b9032916af8d333 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootflow.c b/boot/bootflow.c index 9aa3179c388153cbe2ca567238a69122caa6d90e..68bf99329ab0df7b579dad37cce9d34aeb80b642 100644 --- a/boot/bootflow.c +++ b/boot/bootflow.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 143ef8413326e079bebe0649433ed0178bc08dad..16f9cd8f8ca572c590e555ce7abb657af6530831 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootm.c b/boot/bootm.c index 6fa8edab021e9bf8f7b121b4d1b4ee2278e4f443..032f5a4a160540a1e265886c121660fd08b4d0cb 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -5,6 +5,7 @@ */ #ifndef USE_HOSTCC +#include #include #include #include diff --git a/boot/bootm_os.c b/boot/bootm_os.c index 15297ddb530b48e1e923b81e46ed69f7df03cb58..ccde72d22c17f29131a1d3a5a171657564a0252e 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index c0abadef97cae87d2df27dd30daa8c0d10ca2ba1..1d157d54dbdd301cc4b08cf5650cf7379114133c 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c index 645b8bed10202a9171dd5bbeb8d8037524c76924..f015f2e1c75faad5862ef875b54b0d869aa21feb 100644 --- a/boot/bootmeth_cros.c +++ b/boot/bootmeth_cros.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index c7035c0d0c4e2fed5a0eeae63fdf8ffd40e54905..aebc5207fc01b043b2379da8c574b79cc4e690b2 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index 23ae1e610ac77b6fb354e5d63af156868cc07de7..b7d429f2c3dae608c4f9fabba11394e7de579bfe 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c index 9b55686948f7cbabe029affdcc0ed72d276a8efe..ae0ad1d53e3fbc03a115bca8b7a12f97c96e60b5 100644 --- a/boot/bootmeth_extlinux.c +++ b/boot/bootmeth_extlinux.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index 03d2589c264f20f0f2274436af52691b028e0b6f..70f693aa239b13889199267a1d7ba10d8199d783 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_qfw.c b/boot/bootmeth_qfw.c index dfaa944594e3856a9a0996fe5e4abddf1d219b0f..8ebbc3ebcd580355ad53d09f76bf07c17189461d 100644 --- a/boot/bootmeth_qfw.c +++ b/boot/bootmeth_qfw.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_sandbox.c b/boot/bootmeth_sandbox.c index 0bc8f688e30be6990f6e24b3f44909911215291c..aabc57e635a88bc9e41a572330392af80acf4326 100644 --- a/boot/bootmeth_sandbox.c +++ b/boot/bootmeth_sandbox.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c index 0e05d28d4d9b81feb2c152a0230be8d557c43e13..06340e43d2d7abc072a5fcc1194fdbe1e71809fc 100644 --- a/boot/bootmeth_script.c +++ b/boot/bootmeth_script.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/boot/bootretry.c b/boot/bootretry.c index 587b2de7d6b08db07e1dea512a834cb5590c2d12..8d850df9d4875c41cadabdeb4df9c6fde3fed99a 100644 --- a/boot/bootretry.c +++ b/boot/bootretry.c @@ -4,13 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include #include -#include #include static uint64_t endtime; /* must be set, default is instant timeout */ diff --git a/boot/bootstd-uclass.c b/boot/bootstd-uclass.c index 5de8efce19a5482bc25b27db525baf7c270f266e..81555d341e32b11d09b7c8bc50af6f8c31abb48c 100644 --- a/boot/bootstd-uclass.c +++ b/boot/bootstd-uclass.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/boot/cedit.c b/boot/cedit.c index c29a2be14ce2e531cb6e9dc7d8cd8a1dcf953284..8c654dba6dc35c900bbad0479ae96ea253f9f1e0 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include diff --git a/boot/common_fit.c b/boot/common_fit.c index a2f9b8d83c3b66a39ae0e172445d162f5146578a..cde2dc45e9076e740d18dcbc42caf4f29ee5968c 100644 --- a/boot/common_fit.c +++ b/boot/common_fit.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/boot/expo.c b/boot/expo.c index ed01483f1d3ac640791ee5aac7fff2d5f35c92aa..cadb6a0ad6e3b2424930ecadbbc7001f49729608 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include diff --git a/boot/expo_build.c b/boot/expo_build.c index a4df798adebd474a48281fa10bf74716aec59a9c..04d88a2c30815695b1acfafe8d569d860fdfd0dd 100644 --- a/boot/expo_build.c +++ b/boot/expo_build.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 53415548459ad2d7eee87954b8e3f7c44f2fe6ee..837920bd3a33fe939426d614fa7cbecd4fb2c009 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -6,6 +6,7 @@ * Stephen Warren */ +#include #include #include #include diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 874ca4d6f5afe7fb2bc0da6102d7ac0f535eb763..2bd80a9dfb18e5d0fcb5605d9e1bce0ff53fdbb6 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -6,6 +6,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/boot/image-android-dt.c b/boot/image-android-dt.c index 3b25018c2e774e4db72fc2a88fff0af29044bfd8..fb014190d44519977bd0b3d5d873e27b5b76e1ff 100644 --- a/boot/image-android-dt.c +++ b/boot/image-android-dt.c @@ -6,6 +6,7 @@ #include #include +#include #include #include diff --git a/boot/image-android.c b/boot/image-android.c index ddd8ffd5e5408a7a517918753656a887cc233dd6..88e40bc7ec6c8a69c0b10885ea0bc5ebd31cf9a0 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 Sebastian Andrzej Siewior */ +#include #include #include #include diff --git a/boot/image-board.c b/boot/image-board.c index b7884b8c5dc73e0d5d5be50fcc6ebd24d62041fe..09b6e4e0bdca7244c586398df01ebd322c6bf79e 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -8,7 +8,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/boot/image-cipher.c b/boot/image-cipher.c index 9d389f26cea55b5ff212c815a8b35417c447311d..b9061489396c3d6d34890a64d600c6738bef1f14 100644 --- a/boot/image-cipher.c +++ b/boot/image-cipher.c @@ -7,6 +7,7 @@ #include "mkimage.h" #include #else +#include #include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 56dd7687f51ca3638e109d1e25d8cd924c5cf74b..f09716cba303ed3da3b3db3edfb861ad70bdbf95 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -8,6 +8,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/boot/image-fit-sig.c b/boot/image-fit-sig.c index fe328df4a8500e6b0088a81b9b7358085bf488df..12369896fe3f614b5dedbec793a54831562a5d1c 100644 --- a/boot/image-fit-sig.c +++ b/boot/image-fit-sig.c @@ -7,6 +7,7 @@ #include "mkimage.h" #include #else +#include #include #include #include diff --git a/boot/image-fit.c b/boot/image-fit.c index fb03cab831bd068f62bb0a89fbfd69532a7d11a8..89e377563ce6f3efd69dcbbab1b2e4efd8249bdb 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -19,6 +19,7 @@ #else #include #include +#include #include #include #include diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c index cc19017404c83c64ac8d4e2857883b0e1dfcbcbf..b504ab42a5448a05943da69d524d2d6aa242b964 100644 --- a/boot/image-pre-load.c +++ b/boot/image-pre-load.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Philippe Reynes */ +#include #include DECLARE_GLOBAL_DATA_PTR; #include diff --git a/boot/image-sig.c b/boot/image-sig.c index 6bc74866eaedca3f17e78136ebad2c7c74178928..0421a61b0406640b158f49ba06acec213a1ae60b 100644 --- a/boot/image-sig.c +++ b/boot/image-sig.c @@ -3,6 +3,7 @@ * Copyright (c) 2013, Google Inc. */ +#include #include #include #include diff --git a/boot/image.c b/boot/image.c index eb12e4be04ac40d4c9d6d0aa162b9f49a5da30cf..073931cd7a3febb29a5f550070f24b256c6e8aa2 100644 --- a/boot/image.c +++ b/boot/image.c @@ -7,6 +7,7 @@ */ #ifndef USE_HOSTCC +#include #include #include #include diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 4b22bb6f525a38d257d65d6e1a4dc1aa126b3652..5c1c962ff4c13a52beb1822da62bf0a6513e12ea 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -4,6 +4,7 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/boot/scene.c b/boot/scene.c index ac976aa26bbe28d1c1292585009a0a6b8bc72da0..d4dfb49ada157e8b0f499a0b15a72a4bbd4830e1 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 80bd7457cb1a1c3888b078e1e47cd9126e9e97ad..63994165efba41192d1138dd17b9fcb11cedb272 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include diff --git a/boot/scene_textline.c b/boot/scene_textline.c index bba8663b98da695255696da85b22fb25e6d10110..6ea072a1c2688bb62a3d4664fd11ad8b9c8df347 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -8,12 +8,10 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include -#include #include -#include -#include #include "scene_internal.h" int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, diff --git a/boot/vbe.c b/boot/vbe.c index 00673de7ee2ec30ace7233e0583750ab30e6742e..52b328300374fab943c584810f4bf13140edf1d8 100644 --- a/boot/vbe.c +++ b/boot/vbe.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/boot/vbe_request.c b/boot/vbe_request.c index a1350c1a706ea8f234e0015c4757b1a370d5b0b4..0293ac6c869ff4322d7cf2e52bec53b5c0a1ab3e 100644 --- a/boot/vbe_request.c +++ b/boot/vbe_request.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/boot/vbe_simple.c b/boot/vbe_simple.c index 189e86d2a223ba742f8b470123881cbe00cc8b58..12682abd3996c54eb7d01b2dc4e33c4b62833e10 100644 --- a/boot/vbe_simple.c +++ b/boot/vbe_simple.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/boot/vbe_simple_fw.c b/boot/vbe_simple_fw.c index 4d6da9490a76f364d1ab9b0250d8ab7456951fba..d59a704ddbade4708aceb025b66c57996357f459 100644 --- a/boot/vbe_simple_fw.c +++ b/boot/vbe_simple_fw.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/boot/vbe_simple_os.c b/boot/vbe_simple_os.c index b4126d8d2d0b32247ac1a6b9490581b277b26ab3..84626cdeaf24a9c9051a5a68dded112246b83d49 100644 --- a/boot/vbe_simple_os.c +++ b/boot/vbe_simple_os.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/cmd/2048.c b/cmd/2048.c index 42cd171b0e41708606c9d7bffd0585f7770ffbdc..fa60aa94aad81a0e35e154fb4958df76176db829 100644 --- a/cmd/2048.c +++ b/cmd/2048.c @@ -3,10 +3,10 @@ /* Console version of the game "2048" for GNU/Linux */ +#include #include #include #include -#include #include #define SIZE 4 diff --git a/cmd/Kconfig b/cmd/Kconfig index c06fec3527589d95f1abcf7c13749221afde1e08..b026439c773118372e8164d024f73d98957105ec 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -539,7 +539,6 @@ config CMD_IMI config CMD_IMLS bool "imls" - depends on MTD_NOR_FLASH || FLASH_CFI_DRIVER help List all images found in flash @@ -832,7 +831,7 @@ config SYS_EEPROM_SIZE config SYS_EEPROM_PAGE_WRITE_BITS int "Number of bits used to address bytes in a single page" - depends on CMD_EEPROM || ENV_IS_IN_EEPROM + depends on CMD_EEPROM default 8 help The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. @@ -1024,8 +1023,8 @@ config CMD_ARMFFA - Displaying the arm_ffa device info config CMD_ARMFLASH + #depends on FLASH_CFI_DRIVER bool "armflash" - depends on FLASH_CFI_DRIVER help ARM Ltd reference designs flash partition access @@ -1168,7 +1167,6 @@ config CMD_FPGA_LOAD_SECURE config CMD_FPGAD bool "fpgad - dump FPGA registers" - depends on GDSYS_LEGACY_DRIVERS help (legacy, needs conversion to driver model) Provides a way to dump FPGA registers by calling the board-specific @@ -1604,7 +1602,6 @@ config CMD_TEMPERATURE config CMD_TSI148 bool "tsi148 - Command to access tsi148 device" - depends on DM_PCI_COMPAT help This provides various sub-commands to initialise and configure the Turndra tsi148 device. See the command help for full details. @@ -1618,7 +1615,6 @@ config CMD_UFS config CMD_UNIVERSE bool "universe - Command to set up the Turndra Universe controller" - depends on DM_PCI_COMPAT help This allows setting up the VMEbus provided by this controller. See the command help for full details. diff --git a/cmd/ab_select.c b/cmd/ab_select.c index faeb83816e58293967c69c1ad0f4b543d3fd73d4..bfb67b8236b62b56a81869fcebe46dd13fdcb60c 100644 --- a/cmd/ab_select.c +++ b/cmd/ab_select.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 The Android Open Source Project */ +#include #include #include #include diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 88c77d999290d12fa46b36383a35519130a19001..2653b555b10a07d89192536f300524072213b8f4 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/cmd/acpi.c b/cmd/acpi.c index 094d9d4e85865ec30e4db6ba95e0b39abce4669d..928e5dc525e6400788e70c409e123bd8386dd572 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC * Written by Simon Glass */ +#include #include #include #include @@ -10,7 +11,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/cmd/adc.c b/cmd/adc.c index f87f9785a114a46dde98d6b860af5ef51fec52f8..4cb18b66d4aad3234b3a7b64a0e2546874e0b714 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 BayLibre, SAS * Author: Neil Armstrong */ +#include #include #include #include diff --git a/cmd/addrmap.c b/cmd/addrmap.c index f7e4d9206de5cc70b70b2f3f55c9d3130e1220a6..bd23549f3a5f56512b0ef5ce588d66eb152a2503 100644 --- a/cmd/addrmap.c +++ b/cmd/addrmap.c @@ -3,6 +3,7 @@ * Copyright (C) 2021, Bin Meng */ +#include #include #include diff --git a/cmd/adtimg.c b/cmd/adtimg.c index 53f33764fbe8e0088c436fd8fd3e0652bc034c5c..f4b5cbf35b97e64b252f31b8e74588179292d371 100644 --- a/cmd/adtimg.c +++ b/cmd/adtimg.c @@ -7,8 +7,8 @@ #include #include -#include #include +#include #define OPT_INDEX "--index" diff --git a/cmd/aes.c b/cmd/aes.c index 87ad1ab82b9987f8d7e7af19b184f16639829a03..1264675aa01f48b9c120e93175d59e887dd2ce4d 100644 --- a/cmd/aes.c +++ b/cmd/aes.c @@ -5,13 +5,13 @@ * Command for en/de-crypting block of memory with AES-[128/192/256]-CBC cipher. */ +#include #include #include #include #include #include #include -#include u32 aes_get_key_len(char *command) { diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c index 73d6c20ccaceef4f153322b5f43ed87ea237f8c8..589a23115b0481f8167fc93c71cc4b5fcb2c6f52 100644 --- a/cmd/arm/exception64.c +++ b/cmd/arm/exception64.c @@ -5,6 +5,7 @@ * Copyright (c) 2018, Heinrich Schuchardt */ +#include #include #include diff --git a/cmd/armffa.c b/cmd/armffa.c index 181e31bc49adee5abb95983e716c2fa417fb48eb..9585150b9627c975b224a39641a60e4e48b8d0f3 100644 --- a/cmd/armffa.c +++ b/cmd/armffa.c @@ -5,6 +5,7 @@ * Authors: * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/cmd/armflash.c b/cmd/armflash.c index e292cf85c45dc17eebcc353541f19e47213e7d71..fdaea5ad811d2cb8283cd75559e352d5debec9fa 100644 --- a/cmd/armflash.c +++ b/cmd/armflash.c @@ -5,10 +5,10 @@ * * Support for ARM Flash Partitions */ +#include #include #include #include -#include #include #define MAX_REGIONS 4 diff --git a/cmd/axi.c b/cmd/axi.c index 3dbea0499deea8639f85f96eee44172aa8b19ebd..5620891db28b1488e2480a590343e0756f73ee25 100644 --- a/cmd/axi.c +++ b/cmd/axi.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/cmd/bcb.c b/cmd/bcb.c index fe6d6cb2c3815b9c6980d10f3c1b10ef4a194033..f3b92564d10bb0040b208ccbc1dcd9991d46c35d 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -8,12 +8,12 @@ #include #include #include +#include #include #include #include #include #include -#include #include enum bcb_cmd { diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 437ac4e86309c0d9d0877f6d2f26d68549167f75..79106caeec2e2c0a117e7407f495f1a55617e672 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -6,6 +6,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/bind.c b/cmd/bind.c index 3a59eefd5c58bc059ba26d62e532d45097de0216..be0d4d2a7115806efb02e920a15a5ba58d9d57cf 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 JJ Hiblot */ +#include #include #include #include diff --git a/cmd/binop.c b/cmd/binop.c index 10d91b5dbf2ee9dc8f946becbb054c2a4b71f03a..592e9146901bceeffc623560622011e19b733ebc 100644 --- a/cmd/binop.c +++ b/cmd/binop.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include #include #include -#include #include enum { diff --git a/cmd/blk_common.c b/cmd/blk_common.c index 4c05a4e0610e0bf5c32c1105317bae274b3a7d96..02ac92837b6cf33e992d31c04acd0a9fdcd44a04 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -8,10 +8,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include -#include int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id, int *cur_devnump) diff --git a/cmd/blkcache.c b/cmd/blkcache.c index dbd03df14dcf9e61fd574a988f029cfc4cc98468..1456654df6f5a0e313f13c0e340b74aaead9b5c1 100644 --- a/cmd/blkcache.c +++ b/cmd/blkcache.c @@ -6,9 +6,9 @@ */ #include #include +#include #include #include -#include static int blkc_show(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/blkmap.c b/cmd/blkmap.c index 164f80f1387d5f86f061fed1f92fe6ffcbfdc9a7..ef74ebc0036ce8b3d2314eedf491ce03b1aca42f 100644 --- a/cmd/blkmap.c +++ b/cmd/blkmap.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/cmd/blob.c b/cmd/blob.c index a3c1dc49224d00f5616c7bc0f639ba19bb0b2743..7c77c410d5284e87d86e4227f4ac42a34241889d 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -4,9 +4,9 @@ * Command for encapsulating/decapsulating blob of memory. */ +#include #include #include -#include #include #include #if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ diff --git a/cmd/bloblist.c b/cmd/bloblist.c index 333ae558142c9efe9003e7ee89a91384fc4b727e..26548ecf847e72e0fc9418073b9323e512f3d17f 100644 --- a/cmd/bloblist.c +++ b/cmd/bloblist.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/bmp.c b/cmd/bmp.c index 3b61844862450743167fbe5d1e3769361bcfa873..8f43a40dafdd430e36e1e19764982848037e8094 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -8,6 +8,7 @@ * BMP handling routines */ +#include #include #include #include diff --git a/cmd/boot.c b/cmd/boot.c index 23496cafdf5cbd4cd0e218d823491edbdb215375..14839c1cedcc691e00a7359a456075caecee1458 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -7,9 +7,9 @@ /* * Misc boot support */ +#include #include #include -#include #ifdef CONFIG_CMD_GO diff --git a/cmd/bootcount.c b/cmd/bootcount.c index 5e3b66e676b83ef2a6b371f3a38a0e0ad8c802c3..30ce5dba30d9bd69efdf3ce182e19e0d7e5228c0 100644 --- a/cmd/bootcount.c +++ b/cmd/bootcount.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include diff --git a/cmd/bootdev.c b/cmd/bootdev.c index fa7285ba25e1c04663b76fd2e8cd85ee9c95e27b..471189cda4808c23f7b7a427addac83d9e613204 100644 --- a/cmd/bootdev.c +++ b/cmd/bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/bootflow.c b/cmd/bootflow.c index 1588f277a4a0af78ddfe85ac972422c05754f9e4..be5d7d8e743aaf485682ce0b35e06c021782cebc 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/booti.c b/cmd/booti.c index 62b19e83436659da68e34cc05ece5cf8d2e3dbbb..b9637b3ec3d8de93f51bdd09ce295383fbaa4617 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/bootm.c b/cmd/bootm.c index 545b0c3d8235790302c72d33d9f3d0949a9191cc..9737a2d28c034881dca61192bd1eeb0d30efc41f 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -7,6 +7,7 @@ /* * Boot support */ +#include #include #include #include diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 977a04b7d7697f56cf49a4b03f91f2449d956346..78184fccab25d34bc2de50302485afe197e5b4b4 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/cmd/bootmeth.c b/cmd/bootmeth.c index ebf8b7e2530fb6a8eca5b70e46404da435d9d614..f5b01343c48ca4d0a38924f1d786919a29adcb4c 100644 --- a/cmd/bootmeth.c +++ b/cmd/bootmeth.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/bootstage.c b/cmd/bootstage.c index 5246924f39a4c6152e8b979c215c6ca8667734e1..77a4bc66ff43fd6e43c95545210d634b9f109034 100644 --- a/cmd/bootstage.c +++ b/cmd/bootstage.c @@ -3,9 +3,9 @@ * Copyright (c) 2012, Google Inc. All rights reserved. */ +#include #include #include -#include static int do_bootstage_report(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/bootz.c b/cmd/bootz.c index 55837a7599b921cdc7577236c152af82ca38efe3..b6bb4aae72d4468e886ce1f544605dc82a50058d 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c index ae0a81179d0a2d4b77925c1c01556f11028fb8c2..16f2b612c4db67a049ffbe76dd0053406746e26b 100644 --- a/cmd/broadcom/chimp_boot.c +++ b/cmd/broadcom/chimp_boot.c @@ -3,6 +3,7 @@ * Copyright 2020 Broadcom */ +#include #include #include diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c index e274267196362759cc7638934bfa4fdd30a524bb..a90a73a6d749077628a11ee6c3bea5e625146d28 100644 --- a/cmd/broadcom/chimp_handshake.c +++ b/cmd/broadcom/chimp_handshake.c @@ -3,6 +3,7 @@ * Copyright 2020 Broadcom */ +#include #include #include diff --git a/cmd/broadcom/nitro_image_load.c b/cmd/broadcom/nitro_image_load.c index 289b184e9afdcbbb79f683ce9e4f6b50c761f003..93b5cb4cebe6547d606f80e2fcd051e0def6a155 100644 --- a/cmd/broadcom/nitro_image_load.c +++ b/cmd/broadcom/nitro_image_load.c @@ -3,8 +3,8 @@ * Copyright 2020 Broadcom */ +#include #include -#include #define FW_IMAGE_SIG 0xff123456 #define CFG_IMAGE_SIG 0xcf54321a diff --git a/cmd/btrfs.c b/cmd/btrfs.c index 69d1b1f830d5dda72ea174d7ae590d135b8fe320..2843835d08b80710f1de6820c3402c3e15be90f9 100644 --- a/cmd/btrfs.c +++ b/cmd/btrfs.c @@ -3,6 +3,7 @@ * 2017 by Marek Behún */ +#include #include #include #include diff --git a/cmd/button.c b/cmd/button.c index 3e6db3f5b8eb5cef87031b399eae51d7a55466a6..1b45d0a2a035c61bcecb6951ab166a2b191ed727 100644 --- a/cmd/button.c +++ b/cmd/button.c @@ -5,6 +5,7 @@ * Based on led.c */ +#include #include #include #include diff --git a/cmd/cache.c b/cmd/cache.c index 0254ff17f9b242f7e8e63058f90f3529b186e455..b68d45b98bf2dab35f2c2904a8c4d1df6074417a 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -7,6 +7,7 @@ /* * Cache support: switch on or off, get status */ +#include #include #include #include diff --git a/cmd/cat.c b/cmd/cat.c index 6828b7b364e5a2ad4269d347d034aed915d015da..18aa6ca7aa67f3d2c4fa4af2696dfd723e790cda 100644 --- a/cmd/cat.c +++ b/cmd/cat.c @@ -4,6 +4,7 @@ * Roger Knecht */ +#include #include #include #include diff --git a/cmd/cbfs.c b/cmd/cbfs.c index c1035461df1582cbee548424c06ba9478ca24807..3cfc9eb272706af72d5a9816da58dcba4d74f8fe 100644 --- a/cmd/cbfs.c +++ b/cmd/cbfs.c @@ -6,10 +6,10 @@ /* * CBFS commands */ +#include #include #include #include -#include static int do_cbfs_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/cedit.c b/cmd/cedit.c index fec67a8e334980b3aa7b8e6253cbab5f8a994faa..6352e6369d1e32543239dac8713cc39ddc3723af 100644 --- a/cmd/cedit.c +++ b/cmd/cedit.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/clk.c b/cmd/clk.c index 6fda6efb1cea1533a62649e63746b992df249cbd..7bbcbfeda332d65446cdab5fe79c59a4b27f24c3 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2013 Xilinx, Inc. */ +#include #include #include #if defined(CONFIG_DM) && defined(CONFIG_CLK) diff --git a/cmd/clone.c b/cmd/clone.c index 1f3cff1836d1aee31d14f228ed50b8ea64dea5f6..a906207757127329d49e0e553d51a990282ef7b0 100644 --- a/cmd/clone.c +++ b/cmd/clone.c @@ -4,11 +4,11 @@ * */ +#include #include #include #include #include -#include #include #define BUFSIZE (1 * 1024 * 1024) diff --git a/cmd/cls.c b/cmd/cls.c index 4bee8a18305c0c3f41012a7262c1ac1bc0567d53..80d0558d46791008fc49ac351d09492bf459cc5a 100644 --- a/cmd/cls.c +++ b/cmd/cls.c @@ -5,6 +5,7 @@ * * cls - clear screen command */ +#include #include #include #include diff --git a/cmd/config.c b/cmd/config.c index f0d2033c61f4a7c31c40b7924589f88872f6162d..cf30841a35947e141aa2741a0f6f778cdc82979e 100644 --- a/cmd/config.c +++ b/cmd/config.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Masahiro Yamada */ +#include #include #include #include diff --git a/cmd/conitrace.c b/cmd/conitrace.c index 6cc113328ebc85fac20790580e129503065b5694..9a1bc35184852e1a7c89e587d62ba722531432fa 100644 --- a/cmd/conitrace.c +++ b/cmd/conitrace.c @@ -5,6 +5,7 @@ * * Copyright (c) 2018, Heinrich Schuchardt */ +#include #include #include diff --git a/cmd/console.c b/cmd/console.c index 12fc92061a1905c2bf10b8935a19f58adbd58cd4..58c2cf1c8943e177bc47201c39073b03d17b00d9 100644 --- a/cmd/console.c +++ b/cmd/console.c @@ -7,6 +7,7 @@ /* * Boot support */ +#include #include #include #include diff --git a/cmd/cpu.c b/cmd/cpu.c index 9e323069b9e8652f0291201052ffb24625f69747..245a82fa3eb4e920b4abb7a1125fdea528c07e1c 100644 --- a/cmd/cpu.c +++ b/cmd/cpu.c @@ -5,6 +5,7 @@ * Copyright (c) 2017 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/cmd/cramfs.c b/cmd/cramfs.c index b57e281592614e25af6adbda1453b602959ae96b..57e2afa2472bed29a1b786418b829dcaae0cbdce 100644 --- a/cmd/cramfs.c +++ b/cmd/cramfs.c @@ -10,6 +10,7 @@ /* * CRAMFS support */ +#include #include #include #include diff --git a/cmd/cros_ec.c b/cmd/cros_ec.c index 7b60e415b6c9ee9a46c9a73d39985ffc78e3c1fb..90921cecf602f93637e02ba2eb75c0c0b3f9d573 100644 --- a/cmd/cros_ec.c +++ b/cmd/cros_ec.c @@ -6,6 +6,7 @@ * Copyright (c) 2016 National Instruments Corp */ +#include #include #include #include diff --git a/cmd/cyclic.c b/cmd/cyclic.c index 40e966de9aa537c5565f4df44c29fdfc69e4a772..ad7fc3b975e1daf7d19e88523ef860681bb0a41f 100644 --- a/cmd/cyclic.c +++ b/cmd/cyclic.c @@ -8,12 +8,11 @@ * Copyright (C) 2022 Stefan Roese */ +#include #include #include #include #include -#include -#include #include struct cyclic_demo_info { diff --git a/cmd/date.c b/cmd/date.c index 755adec1e71e9dfe6d31ce243392989b31a295b2..4f98b470ca2e6a3de267a0313f454ee5e317557d 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -7,6 +7,7 @@ /* * RTC, Date & Time support: get and set date & time */ +#include #include #include #include diff --git a/cmd/demo.c b/cmd/demo.c index 5c422ac165bd7cb3bd3beb5971cc046f931878aa..ebd5a241c362c63ce813337df33aa353ec04ef8e 100644 --- a/cmd/demo.c +++ b/cmd/demo.c @@ -6,6 +6,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/cmd/dfu.c b/cmd/dfu.c index 46f0190588e05b160c2eb3071ab8e229e512c77d..d7bfb535dc68f9628f5ea7a85f56d7fcd580d60e 100644 --- a/cmd/dfu.c +++ b/cmd/dfu.c @@ -10,6 +10,7 @@ * Lukasz Majewski */ +#include #include #include #include diff --git a/cmd/diag.c b/cmd/diag.c index c6da5aae3fcd9aeba2e62144ace249bf26d63f6a..f51536dbfaaf84bdfe4639dde9bc6ed77fe44469 100644 --- a/cmd/diag.c +++ b/cmd/diag.c @@ -7,6 +7,7 @@ /* * Diagnostics support */ +#include #include #include diff --git a/cmd/disk.c b/cmd/disk.c index 2efc3ca4b1a2fb1ea6e2b1947192c586aaf384e4..92eaa02f4a1312d2ea83cb39211939b00d27c435 100644 --- a/cmd/disk.c +++ b/cmd/disk.c @@ -3,6 +3,7 @@ * (C) Copyright 2000-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/dm.c b/cmd/dm.c index ec9cfd85376e3f62a836b677b3ac1818559da2de..fb605c2da1a89e6b43850bc8cc620adf0b5ffbeb 100644 --- a/cmd/dm.c +++ b/cmd/dm.c @@ -6,6 +6,7 @@ * Marek Vasut */ +#include #include #include #include diff --git a/cmd/echo.c b/cmd/echo.c index 973213a03a66b57af5172e470a095b0e94f58e51..fda844ee9d3524ebeac6d60769cbefa3c7649e52 100644 --- a/cmd/echo.c +++ b/cmd/echo.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include static int do_echo(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 26f3750a80adb02ec26fb3af6e82ee3bb357e99b..322765ad02a013b1c5dff318f1f4285207f9714a 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -19,12 +19,12 @@ * */ +#include #include #include #include #include #include -#include #include #ifndef I2C_RXTX_LEN diff --git a/cmd/efi.c b/cmd/efi.c index 6bed2d743ba6ebe2cefa00abfa2a08b0e3d287ba..6cd5361aca59e2ec120c3ef006545f50c195e55b 100644 --- a/cmd/efi.c +++ b/cmd/efi.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/efi_common.c b/cmd/efi_common.c index c46764e6eea74258aafebd031255a0f91a801795..1aa2351fcdfde8435f6614066e24798a5b7904dc 100644 --- a/cmd/efi_common.c +++ b/cmd/efi_common.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 4164cb4f9b80bedadb8460c50dfd2559a14fe56a..0ba92c60e0392215f37a0981a4aeea24c78e1e98 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c index b3325a540f9a16ec626573a60d150b6ba54312e1..caca27495e02833cd1cdeea5eaba244f6d52339a 100644 --- a/cmd/eficonfig_sbkey.c +++ b/cmd/eficonfig_sbkey.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/cmd/efidebug.c b/cmd/efidebug.c index e978e74aad9c0475dd90dee38092d39c8b0054b8..c2c525f2351744ce44f46ac47768505dc84b08c3 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/cmd/elf.c b/cmd/elf.c index a02361f9f512eca9d1113a0181fe6fab330cc86e..df4354d37428b89bb7dec8431e502ed6eda83a6c 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -4,6 +4,7 @@ * All rights reserved. */ +#include #include #include #include diff --git a/cmd/ethsw.c b/cmd/ethsw.c index 4bf49ac598fcf6e063c4f5eb4f647d815a40875a..f8b8a798bf6a6f555395fbfed31b41a80ccb5817 100644 --- a/cmd/ethsw.c +++ b/cmd/ethsw.c @@ -5,13 +5,13 @@ * Ethernet Switch commands */ +#include #include #include #include #include #include #include -#include static const char *ethsw_name; diff --git a/cmd/event.c b/cmd/event.c index 00c828757ca923ac7fa0c6957bed824be0832ba5..f6cdb55fc913df3d19e1c08ec86397ff2512fc3c 100644 --- a/cmd/event.c +++ b/cmd/event.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/cmd/exit.c b/cmd/exit.c index d125ec1e31f2d80d8a5b3e288db94e988bec16ff..7bf241ec732d96b19e678ee1d13a8b9073d37522 100644 --- a/cmd/exit.c +++ b/cmd/exit.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include -#include static int do_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/ext2.c b/cmd/ext2.c index 45c8b353b58643333499a136a544ce1a56b09dc1..a0ce0cf5796b9dd091c004ddbbcb4ee36bbfd590 100644 --- a/cmd/ext2.c +++ b/cmd/ext2.c @@ -19,6 +19,7 @@ /* * Ext2fs support */ +#include #include #include diff --git a/cmd/ext4.c b/cmd/ext4.c index 40d1fe30d5ea68b461828c08f91de3012c46b32b..4791b69fd96d0bf526fa5bab83b54ae88668930c 100644 --- a/cmd/ext4.c +++ b/cmd/ext4.c @@ -25,6 +25,7 @@ * file in uboot. Added ext4fs ls load and write support. */ +#include #include #include #include diff --git a/cmd/extension_board.c b/cmd/extension_board.c index f43bf680858f61df24c95fc23ecaa5e9fb198475..2b672d888c68b28ee408e3a8544e9536e4f399d8 100644 --- a/cmd/extension_board.c +++ b/cmd/extension_board.c @@ -4,6 +4,7 @@ * Köry Maincent, Bootlin, */ +#include #include #include #include diff --git a/cmd/fastboot.c b/cmd/fastboot.c index d4cfc0c7a282b8697f50c207fa8cb46171797ee1..c3c19231c9889aa1e8ab9b56db4e81f31b10af43 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -6,6 +6,7 @@ * (C) Copyright 2014 Linaro, Ltd. * Rob Herring */ +#include #include #include #include diff --git a/cmd/fat.c b/cmd/fat.c index ad0e5ed7d6006588c57c7ab93abf6b64a870a681..69ce1fa5300bb6a8a46600057e57eafb45220ee6 100644 --- a/cmd/fat.c +++ b/cmd/fat.c @@ -7,6 +7,7 @@ /* * Boot support */ +#include #include #include #include diff --git a/cmd/fdt.c b/cmd/fdt.c index d16b141ce32d2173b08e64a8084b7b2b0f5a5192..331564c13be9a46844ec6c91213fb0da850c74e5 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -7,6 +7,7 @@ * Matthew McClintock */ +#include #include #include #include diff --git a/cmd/flash.c b/cmd/flash.c index de0e04f09cfbb734969142d8e0c33feaa1cf9e86..f4f85ecc7a8e0613c63e55406098a60726b879ef 100644 --- a/cmd/flash.c +++ b/cmd/flash.c @@ -7,9 +7,9 @@ /* * FLASH support */ +#include #include #include -#include #include #if defined(CONFIG_CMD_MTDPARTS) diff --git a/cmd/font.c b/cmd/font.c index ebde094b0a5bb641ed8e6f58a08c46f7e510efc8..cb39c88063fbfd133a3476b5d1d72f538e4e93bd 100644 --- a/cmd/font.c +++ b/cmd/font.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/fpga.c b/cmd/fpga.c index 93f14098ccb627db190f4b80c80d33057cd38507..8c64e957db0fd5e5e3b5fa2be7e756c4714a5d6e 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -7,6 +7,7 @@ /* * FPGA support */ +#include #include #include #include diff --git a/cmd/fpgad.c b/cmd/fpgad.c index b4bfaa1216572e0e9534f6c0d74f56522027dadf..dfc6220b5e01173af3b2aa2a9183f342a4da5298 100644 --- a/cmd/fpgad.c +++ b/cmd/fpgad.c @@ -8,10 +8,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include -#include #include diff --git a/cmd/fs.c b/cmd/fs.c index 3d7e06d6f1e5a288bb9b6418d0c4722ba37f9a8f..46cb43dcdb5bfafe4ad273a37b437ae1450398b2 100644 --- a/cmd/fs.c +++ b/cmd/fs.c @@ -5,6 +5,7 @@ * Inspired by cmd_ext_common.c, cmd_fat.c. */ +#include #include #include diff --git a/cmd/fs_uuid.c b/cmd/fs_uuid.c index 5f7770d09ac650df99581b18a6838bc93af8a7c2..5dc94aa6408177f07d10d0baf8af2554f0586ec8 100644 --- a/cmd/fs_uuid.c +++ b/cmd/fs_uuid.c @@ -5,6 +5,7 @@ * Copyright (C) 2014, Bachmann electronic GmbH */ +#include #include #include diff --git a/cmd/fuse.c b/cmd/fuse.c index 598ef496a430071dd3d141249eee7146f18bca78..f884c894fb002fad53f90d894a25559093c3223f 100644 --- a/cmd/fuse.c +++ b/cmd/fuse.c @@ -8,11 +8,11 @@ * Martha Marx */ +#include #include #include #include #include -#include #include static int strtou32(const char *str, unsigned int base, u32 *result) diff --git a/cmd/gettime.c b/cmd/gettime.c index fc307efce8c288e5d550bd61e40d2658a4b8da3b..2e74e02b49980a4e26c6c39f0886c52e1f09c97e 100644 --- a/cmd/gettime.c +++ b/cmd/gettime.c @@ -11,8 +11,8 @@ /* * Get Timer overflows after 2^32 / CONFIG_SYS_HZ (32Khz) = 131072 sec */ +#include #include -#include static int do_gettime(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/gpio.c b/cmd/gpio.c index 7a43dc6ab18430ea934761ace9bc0a3614881213..dab6f7097aec1a0c9ea40a64d128dfa665010377 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -6,6 +6,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include #include diff --git a/cmd/gpt.c b/cmd/gpt.c index 36b112d59784060766b0ffe8d24f0ac93df11e23..7aaf1889a5ace1f0edac2af2a5c808b9b9ed9429 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -10,6 +10,7 @@ * author: Piotr Wilczek */ +#include #include #include #include diff --git a/cmd/hash.c b/cmd/hash.c index 60d482b7f87267418b998e68a02592de1aaa121d..5534a735fa7eef8c1e2b1f105c2a6e5f9bf47de7 100644 --- a/cmd/hash.c +++ b/cmd/hash.c @@ -9,6 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/help.c b/cmd/help.c index 56579e28d31d7dfd0aa25130f8eb7093ea631783..9f8393eefd81f6ccea9a99f6cbd2d0779db3d611 100644 --- a/cmd/help.c +++ b/cmd/help.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include static int do_help(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/history.c b/cmd/history.c index 8972986ca9d1152eadf5b790e8fe695303d644e6..b6bf4670b1cea37031a70df351b33756f916fd14 100644 --- a/cmd/history.c +++ b/cmd/history.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/cmd/host.c b/cmd/host.c index e03576b4d2def808687a02f7db48d359a66426ef..c33c2a9787eb36562c66d9267d1d9eea22ba5d93 100644 --- a/cmd/host.c +++ b/cmd/host.c @@ -3,6 +3,7 @@ * Copyright (c) 2012, Google Inc. */ +#include #include #include #include diff --git a/cmd/i2c.c b/cmd/i2c.c index 7dac0a9fb6cbe459096eb4d8de99bc45001f7847..80831561c6711f70be75c7740380073b008d4ecf 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -64,6 +64,7 @@ * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). */ +#include #include #include #include diff --git a/cmd/ide.c b/cmd/ide.c index 036489fda979b8656cc9cd9f2a21867513c21e3c..ddc87d3a0bb95d0f36789267d5ac0c709c963ce6 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -8,6 +8,7 @@ * IDE support */ +#include #include #include #include diff --git a/cmd/ini.c b/cmd/ini.c index 963990176916d6af88b95331830ef68391afe22a..35de2373e60213b442f98e170b57e2d26d14f03f 100644 --- a/cmd/ini.c +++ b/cmd/ini.c @@ -11,9 +11,9 @@ * http://code.google.com/p/inih/ */ +#include #include #include -#include #include #include diff --git a/cmd/io.c b/cmd/io.c index 617373d3cb71052283915baa8de7ae1913e2cc74..2de1111998fe6f5987480cceef503ca84c2188e2 100644 --- a/cmd/io.c +++ b/cmd/io.c @@ -7,9 +7,9 @@ * IO space access commands. */ +#include #include #include -#include #include /* Display values from last command */ diff --git a/cmd/iotrace.c b/cmd/iotrace.c index 0a041ed8652a661aefccefa2dbef83f767d21ad8..f28359e2875d68b761c443c38cf136511f2c99e7 100644 --- a/cmd/iotrace.c +++ b/cmd/iotrace.c @@ -3,9 +3,9 @@ * Copyright (c) 2014 Google, Inc */ +#include #include #include -#include static void do_print_stats(void) { diff --git a/cmd/irq.c b/cmd/irq.c index 655aba576a8b29f43808adc7af7e2d33490b7df4..1d3e28cb3ce02427dc144ba3a0ca940564813d86 100644 --- a/cmd/irq.c +++ b/cmd/irq.c @@ -3,6 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/cmd/itest.c b/cmd/itest.c index b79512a505d6726048bb50514fde14fd69e6998a..74414cbdc4c67e8dba32b533b1c563d5e182e542 100644 --- a/cmd/itest.c +++ b/cmd/itest.c @@ -11,11 +11,11 @@ * A few parts were lifted from bash 'test' command */ +#include #include #include #include #include -#include #include diff --git a/cmd/jffs2.c b/cmd/jffs2.c index 89d336f5958564960a0988fb6441d6ee964879c4..e00fcc2022665024c7399d97224da15861566bc8 100644 --- a/cmd/jffs2.c +++ b/cmd/jffs2.c @@ -70,6 +70,7 @@ /* * JFFS2/CRAMFS support */ +#include #include #include #if defined(CONFIG_CMD_FLASH) diff --git a/cmd/kaslrseed.c b/cmd/kaslrseed.c index e0d3c7fe7489143ab1971e15a4c492f5c1d025de..9acb8e16386392550c1cfd42d0bbaf76f591c72f 100644 --- a/cmd/kaslrseed.c +++ b/cmd/kaslrseed.c @@ -6,6 +6,7 @@ * Copyright (c) 2021, Chris Morgan */ +#include #include #include #include diff --git a/cmd/led.c b/cmd/led.c index 4256b3429c2f9520f8cc54f51627b6e0bfa7a5d7..48a02baf509deaa0c0cb8e554cb8cb4f7076e2ac 100644 --- a/cmd/led.c +++ b/cmd/led.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index 1a5271000bf354c3a5aab7e2f02e0cd85a287b75..5903a90fe53b14b518376c6cd084e92e1b88e8e2 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/cmd/legacy_led.c b/cmd/legacy_led.c index 50de7e89d8f4c0533497fd907ef674c788cd2d5a..5256255f052dabdd477af3cc67c53b9b54049896 100644 --- a/cmd/legacy_led.c +++ b/cmd/legacy_led.c @@ -9,9 +9,10 @@ * Ulf Samuelsson */ +#include +#include #include #include -#include struct led_tbl_s { char *string; /* String for use in the command */ diff --git a/cmd/license.c b/cmd/license.c index 161663ff29c64173d3bb62f52c7aecdabdef80ab..15411b5a92d56ed09fd3e878c1d8032b8305c114 100644 --- a/cmd/license.c +++ b/cmd/license.c @@ -4,6 +4,7 @@ * Author: Harald Welte */ +#include #include #include #include diff --git a/cmd/load.c b/cmd/load.c index ace1c52f90added1f7906cad4acf2369d7893457..540361b43f02e09fdb9ec4d5a89ca37029279800 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -7,6 +7,7 @@ /* * Serial up- and download support */ +#include #include #include #include diff --git a/cmd/log.c b/cmd/log.c index 519ec76f3b5100338991bee570616ec8f32dc00a..c9a23e4ae0d311b3800b65a3a1639f80c2802c49 100644 --- a/cmd/log.c +++ b/cmd/log.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/lsblk.c b/cmd/lsblk.c index 7c00bfdc7a09a0b28adca7a00bfe82587a174fba..d214dafc3bee0353e39b251131153b34cbafa2f0 100644 --- a/cmd/lsblk.c +++ b/cmd/lsblk.c @@ -4,6 +4,7 @@ * Niel Fourie, DENX Software Engineering, lusus@denx.de. */ +#include #include #include #include diff --git a/cmd/lzmadec.c b/cmd/lzmadec.c index c40b96941b477b035b4551e34345c80c8e0f28cb..81924da461802425ebefff0f7173c48008cfbe96 100644 --- a/cmd/lzmadec.c +++ b/cmd/lzmadec.c @@ -9,10 +9,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include -#include #include #include diff --git a/cmd/mbr.c b/cmd/mbr.c index 7e1f92a13bb5eaa481991d05c14bab360bf0bd32..ec99b662834ebd121d18e0c951fb8961db21639c 100644 --- a/cmd/mbr.c +++ b/cmd/mbr.c @@ -8,11 +8,11 @@ * based on the gpt command. */ +#include #include #include #include #include -#include /** * extract_val() - Extract a value from the key=value pair list diff --git a/cmd/mdio.c b/cmd/mdio.c index c0a87087d315014a1bfea595cb152f52ea46798c..3c74326161efc2b36da82bf765a93a7cc47e4dd6 100644 --- a/cmd/mdio.c +++ b/cmd/mdio.c @@ -8,6 +8,7 @@ * MDIO Commands */ +#include #include #include #include diff --git a/cmd/mem.c b/cmd/mem.c index 4989d27f2ab466150a82e381703ee596d59af477..768057e4d3f682c3561ac28b57fd261c24c31793 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -10,6 +10,7 @@ * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) */ +#include #include #include #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/cmd/meson/sm.c b/cmd/meson/sm.c index b69f8123ee2da405f8b606de46a4931d78021377..de9a242e17f543a5ac8a275d2321f964bb556cf2 100644 --- a/cmd/meson/sm.c +++ b/cmd/meson/sm.c @@ -9,11 +9,11 @@ */ #include +#include #include #include #include #include -#include static int do_sm_serial(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/mii.c b/cmd/mii.c index ce3724896926d28391ba594dcdcce22ad0f33df7..fab420ee29e20c539fc04d00bb102d384fc7bf55 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -8,6 +8,7 @@ * MII Utilities */ +#include #include #include #include diff --git a/cmd/misc.c b/cmd/misc.c index 792d9723c759272fd27b246dae756963244a537f..ec32b41ed1e96f01bcc27b1d3d2a6226d8966bed 100644 --- a/cmd/misc.c +++ b/cmd/misc.c @@ -8,6 +8,7 @@ * A command interface to access misc devices with MISC uclass driver APIs. */ +#include #include #include #include diff --git a/cmd/mmc.c b/cmd/mmc.c index 7244a90f4dcebb3f1d415505a936963d7625b15b..2d5430a53079628b8bb10ba49a1ff46bcb4bd837 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -4,6 +4,7 @@ * Kyle Harris, kharris@nexus-tech.net */ +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include static int curr_device = -1; diff --git a/cmd/mp.c b/cmd/mp.c index b9b5e01624666add6de930e6c2afbc1701edca40..1b4373f25873a275931b87058513241a0a7b7b2b 100644 --- a/cmd/mp.c +++ b/cmd/mp.c @@ -3,9 +3,9 @@ * Copyright 2008-2009 Freescale Semiconductor, Inc. */ +#include #include #include -#include static int cpu_status_all(void) { diff --git a/cmd/mtd.c b/cmd/mtd.c index 795aaa2b37da7b539fee07efacb20be867aa73f3..9189f45cabd5505f47800633f3decc508cef978d 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -9,6 +9,7 @@ */ #include +#include #include #if CONFIG_IS_ENABLED(CMD_MTD_OTP) #include diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index f57d84dbb3add64dcde02de0151eb48f8641d433..b31db73ebfc9759636f961e0edbf622acd95f6a0 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -70,6 +70,7 @@ * */ +#include #include #include #include diff --git a/cmd/mux.c b/cmd/mux.c index 2f6c08b8b079432d86ac603387e71f8c3a7d3102..388fb0878a84aeb0cbe753ce22b000b1f89c1d6b 100644 --- a/cmd/mux.c +++ b/cmd/mux.c @@ -6,6 +6,7 @@ * Author: Pratyush Yadav */ +#include #include #include #include diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index e3f21dd0d81521970c4ebbbfc1d80568b7722a15..744b1c20aa83f2f4743975dfdd132c40c5ab9c51 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/cmd/mvebu/comphy_rx_training.c b/cmd/mvebu/comphy_rx_training.c index 5653877cd4a2cbca0b70c605c392acb72c80ff61..4ee8f54ea9c7ab839bdbae52a578d067010b6b8a 100644 --- a/cmd/mvebu/comphy_rx_training.c +++ b/cmd/mvebu/comphy_rx_training.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0 */ +#include #include #include #include diff --git a/cmd/nand.c b/cmd/nand.c index 5a328e0acddfa244e4d5c1ae207235e1fc782ac9..fe834c4ac5c030e64c37736566904b3ec6f0e3a8 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -23,6 +23,7 @@ * only */ +#include #include #include #include diff --git a/cmd/net.c b/cmd/net.c index b206ff58e68176ce6db4f232e220af78a97e5c9e..d407d8320a3d84dcf445938eeaef41bced20cb9d 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -9,6 +9,7 @@ /* * Boot support */ +#include #include #include #include diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 98a687bcabbdd3fc4d29cc55169489aba4661902..e77338f81394b3f92fb23779bd7dfc30266e7f7f 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -23,7 +23,7 @@ * environment. After that, we use a hash table. */ -#include +#include #include #include #include diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index 64ae2ad2ce24b926c21f728bf4b31b2dbbe4370a..7a30b5cc8f87ca4fe614d8cd5227bb11ae9b74ec 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/cmd/nvme.c b/cmd/nvme.c index f2c9acba5c3272a17a93a27acef6cb77632ddf29..09d5f438fb1a112fd75da207fc139c5ee8d91197 100644 --- a/cmd/nvme.c +++ b/cmd/nvme.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 Bin Meng */ +#include #include #include #include diff --git a/cmd/onenand.c b/cmd/onenand.c index 6e808ce3fce4d1214cfdef8e2f999101e73ad817..fad781583a313503db6962deb4153f01be11db11 100644 --- a/cmd/onenand.c +++ b/cmd/onenand.c @@ -9,6 +9,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c index b155278ee2ad2972e141a079f533ac2f4a64aeb8..b3cafd924108fa417bc483b843bf42514c2be14a 100644 --- a/cmd/optee_rpmb.c +++ b/cmd/optee_rpmb.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/cmd/osd.c b/cmd/osd.c index 5671338d9e7bc27173c9852a7b387de1d4dbd881..210bc5d4c231ab6b2b54fc8258bf7e2c576b2b78 100644 --- a/cmd/osd.c +++ b/cmd/osd.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ +#include #include #include #include diff --git a/cmd/panic.c b/cmd/panic.c index 7c0affa5eb50e6ad73ff20b9dfa57d52ff86e861..f13b3f094fab53ccf1e42bd0f0c2065e597c7489 100644 --- a/cmd/panic.c +++ b/cmd/panic.c @@ -3,7 +3,7 @@ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include static int do_panic(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/part.c b/cmd/part.c index d140a1eddb92e1a4d9ff3ffa0442cb66d99cecd3..c75f85acd52d4dca58bebfab742cca99cc4f2641 100644 --- a/cmd/part.c +++ b/cmd/part.c @@ -15,6 +15,7 @@ * Pavel Bartusek */ +#include #include #include #include diff --git a/cmd/pcap.c b/cmd/pcap.c index 8d610966c13dedd0dd612631b9da894c55e590a8..a0149203fad542db7b57d3ba2880e2d4fffd1b2a 100644 --- a/cmd/pcap.c +++ b/cmd/pcap.c @@ -4,8 +4,8 @@ * Ramon Fried */ +#include #include -#include #include #include diff --git a/cmd/pci.c b/cmd/pci.c index 3c0aed50cae309630fbe941d4780f165632f0014..d89e71c16a04900a9adbc7ae092e080dd3d280f1 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -12,6 +12,7 @@ * PCI routines */ +#include #include #include #include diff --git a/cmd/pci_mps.c b/cmd/pci_mps.c index 19e71db8cbd2fe074b8ea1efa8ee61638587791d..98161da93a059ee9a8b8dddfc6ceb51853ed663d 100644 --- a/cmd/pci_mps.c +++ b/cmd/pci_mps.c @@ -6,6 +6,7 @@ * PCI Express Maximum Packet Size (MPS) configuration */ +#include #include #include #include diff --git a/cmd/pinmux.c b/cmd/pinmux.c index 01f3e4af6cec3a4cdad6ed96357729949a788645..105f01eaafffce364e673af7817d122d27f9547d 100644 --- a/cmd/pinmux.c +++ b/cmd/pinmux.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/cmd/pmc.c b/cmd/pmc.c index 1a3416fb2a96afb5d631d2af277bdce184690a63..9a3ba2bffc50041f61c0a21f11af0b5c4ac8cefe 100644 --- a/cmd/pmc.c +++ b/cmd/pmc.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/cmd/pmic.c b/cmd/pmic.c index 3ad1b8aa3756473dfb8779bb3060c38827760ea3..c9e9730adf909e30fd8420145b7d66a80cd6cbaf 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -3,6 +3,7 @@ * Copyright (C) 2014-2015 Samsung Electronics * Przemyslaw Marczak */ +#include #include #include #include diff --git a/cmd/printf.c b/cmd/printf.c index a1727ac15a2d8b24a753861487a8c87fbd589c49..0c6887e0d6e983327eaaf073d20a368ba17ffd72 100644 --- a/cmd/printf.c +++ b/cmd/printf.c @@ -84,12 +84,12 @@ * We try to be compatible. */ +#include #include #include #include #include #include -#include #define WANT_HEX_ESCAPES 0 #define PRINT_CONVERSION_ERROR 1 diff --git a/cmd/pvblock.c b/cmd/pvblock.c index 3a83ac9cd92c8a0f6a5efb5ebfc88b01e2fc8b53..1b604c37373c5de86b20b8f796aa289d429547f8 100644 --- a/cmd/pvblock.c +++ b/cmd/pvblock.c @@ -6,6 +6,7 @@ */ #include +#include #include /* Current I/O Device */ diff --git a/cmd/pxe.c b/cmd/pxe.c index ae02c28c07503763290b073702d6589e2f2fbeb1..21134eb7a304646ad305eaac48bd289b8be5a8d8 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -4,12 +4,12 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include #include #include -#include #include "pxe_utils.h" diff --git a/cmd/qfw.c b/cmd/qfw.c index 1b108118658e39c3cd039a53afb718a74df7ed81..1b8c775ebf5ab10cffac06998f1a043dd3ff2b84 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Miao Yan */ +#include #include #include #include diff --git a/cmd/read.c b/cmd/read.c index af54bd176547fa05724e18bfca8cfccd0a2f85e9..1218e7acfd0a3bd2b876b010a997a51506be1a3e 100644 --- a/cmd/read.c +++ b/cmd/read.c @@ -8,10 +8,10 @@ * Software Foundation. */ +#include #include #include #include -#include static int do_rw(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/reginfo.c b/cmd/reginfo.c index 53b8bc41bfe518d9b6c0a60618c7f5a713d9c714..c8a04b1754eb5ace63a18bad5d5d40f3ccbd4743 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -4,6 +4,7 @@ * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com */ +#include #include #include diff --git a/cmd/regulator.c b/cmd/regulator.c index da298090bb7605d0e6dbf9630edc6971044ff114..635a9add58567e3f082aa330a5d0de722527e6d5 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -3,6 +3,7 @@ * Copyright (C) 2014-2015 Samsung Electronics * Przemyslaw Marczak */ +#include #include #include #include diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c index 3c5b6a05b1afef2bac4aeade13550ecad5e23f16..ea8724a187da9b3fc90f90eca4a94ba7414b1d9f 100644 --- a/cmd/remoteproc.c +++ b/cmd/remoteproc.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 * Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index a231604e492084bf1c0f688e51279f5d6a65e27d..2d8ee7e5bbb07b5af312b14fa57bac9b1a4469e8 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -5,6 +5,7 @@ * Copyright (c) 2020, Heinrich Schuchardt */ +#include #include #include diff --git a/cmd/rkmtd.c b/cmd/rkmtd.c index a870c11911085e9c557016a06b4392f30fbc24a5..5b80427cb949aace1fa550b20b8a0cf0aeadeed0 100644 --- a/cmd/rkmtd.c +++ b/cmd/rkmtd.c @@ -8,6 +8,7 @@ * Copyright (C) 2023 Johan Jonker */ +#include #include #include #include diff --git a/cmd/rng.c b/cmd/rng.c index 2fb7202303acd04af16b8c8f288f0d695351094d..e5ab8681122606f5f403fd64de250627c64769f9 100644 --- a/cmd/rng.c +++ b/cmd/rng.c @@ -4,6 +4,7 @@ * * Copyright (c) 2019, Heinrich Schuchardt */ +#include #include #include #include diff --git a/cmd/rockusb.c b/cmd/rockusb.c index 48497aa876418e56768d4e61c05702eaabefc0c2..07088564a109b60acce67d6857a5223b6c9648a6 100644 --- a/cmd/rockusb.c +++ b/cmd/rockusb.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Eddie Cai */ +#include #include #include #include diff --git a/cmd/rtc.c b/cmd/rtc.c index a931fd9d54f0199bbfdb94689840d67a84d7ccf6..a344cfa76b1d52c1f77fa00b4c7f9c8cb2dd4f07 100644 --- a/cmd/rtc.c +++ b/cmd/rtc.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/cmd/sata.c b/cmd/sata.c index 8b923f9378b221cbc1002021ecdfd66bbfaa3824..9c9fe111d12f2b7fe071b02c7c666a5e8389247b 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -9,6 +9,7 @@ * Dave Liu */ +#include #include #include #include diff --git a/cmd/sb.c b/cmd/sb.c index 1aa5921f03e6695e04d89165567fd4077ac59fc3..0d55818e3c6741b3cef63a58ab8222d4a5068c49 100644 --- a/cmd/sb.c +++ b/cmd/sb.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/scp03.c b/cmd/scp03.c index 9c749d19af81745f7c129147ab25adc57eaa9d8b..2b8d5aecf3497be82f65e3ad3a09d3ac9ed6fd89 100644 --- a/cmd/scp03.c +++ b/cmd/scp03.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/cmd/scsi.c b/cmd/scsi.c index c286bdc072605796614c817fea43f4cf5fb6d968..c501d7f456d7eba9af7701e6e679db326419a179 100644 --- a/cmd/scsi.c +++ b/cmd/scsi.c @@ -7,6 +7,7 @@ /* * SCSI support. */ +#include #include #include #include diff --git a/cmd/seama.c b/cmd/seama.c index 3c8e819923400c93d3957e99d23ab9e1862fcb84..3aafb43c48a056842ce314f028e135edd32a61d0 100644 --- a/cmd/seama.c +++ b/cmd/seama.c @@ -4,6 +4,7 @@ * Support for the "SEAttle iMAge" SEAMA NAND image format */ +#include #include #include diff --git a/cmd/setexpr.c b/cmd/setexpr.c index e111b8ba98ad7c276621aca949ccd31ba5dc12ed..ab76824a32bbee54690ea4302785f6aa77e43eda 100644 --- a/cmd/setexpr.c +++ b/cmd/setexpr.c @@ -8,6 +8,7 @@ * This file provides a shell like 'expr' function to return. */ +#include #include #include #include @@ -15,8 +16,6 @@ #include #include #include -#include -#include #include #include "printf.h" diff --git a/cmd/sf.c b/cmd/sf.c index f43a2e08b318ca3a6ddc4f8af791d46a455d7611..e3866899f6c463df518736b3c5d10316c4df89d7 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -5,6 +5,7 @@ * Copyright (C) 2008 Atmel Corporation */ +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/cmd/sha1sum.c b/cmd/sha1sum.c index 52aa26c78d2f9b8b81d5390adc771700b1569e6d..bcc665a5a6c692a9176fcc5694eee6ba154f5ae8 100644 --- a/cmd/sha1sum.c +++ b/cmd/sha1sum.c @@ -7,6 +7,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/sleep.c b/cmd/sleep.c index 7616fed7556667448c532d130101483e4fea0066..c741b4aa029bdbf38da667467213c41c0bc87a72 100644 --- a/cmd/sleep.c +++ b/cmd/sleep.c @@ -4,10 +4,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include -#include -#include #include static int do_sleep(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/smccc.c b/cmd/smccc.c index 3a4d885e37e1fd74c4a265f17f9e25053d72f880..fb80431ad1d954bab5498c3cdcdc19bd8927a4a2 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -4,8 +4,8 @@ * Michalis Pappas */ #include +#include #include -#include #include #include #include diff --git a/cmd/sound.c b/cmd/sound.c index 08bf74112f1659401f4311a98c9d4e3e9e6daf61..0b7f9599716b29a6d1f9d68fedaafe2caae648d4 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -4,6 +4,7 @@ * Rajeshwari Shinde */ +#include #include #include #include diff --git a/cmd/source.c b/cmd/source.c index c9b5f8e400a615c055979270774cd9bde3183a79..0ba9736b1ab34fe746504893ca47c93c2a0fd8ec 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -14,6 +14,7 @@ /* #define DEBUG */ +#include #include #include #include diff --git a/cmd/spi.c b/cmd/spi.c index ea30c854c2188974b2086502d94dd44950bd90a9..f30018f33be81e0f7949f711aff02e9ce6beb3ec 100644 --- a/cmd/spi.c +++ b/cmd/spi.c @@ -8,6 +8,7 @@ * SPI Read/Write Utilities */ +#include #include #include #include diff --git a/cmd/spl.c b/cmd/spl.c index d1f47c7316b49f95c0bb2f4e20d8085500d94b68..8a2ded72be9ff7703426cc6df1bf66cf8933b465 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -4,6 +4,7 @@ * Corscience GmbH & Co. KG - Simon Schwarz */ +#include #include #include #include diff --git a/cmd/stackprot_test.c b/cmd/stackprot_test.c index e7ff4a0615894dedcd8ae29ef2d1381e1f974d3b..f3470288faccb1a7146ab5be3e8fe3a031c2c506 100644 --- a/cmd/stackprot_test.c +++ b/cmd/stackprot_test.c @@ -3,6 +3,7 @@ * Copyright 2021 Broadcom */ +#include #include static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/strings.c b/cmd/strings.c index 5bcb0f2b567cd4526116d6c3fdd31482eb18155b..bf348afce8141256c61e50a0f143e323c1f98a43 100644 --- a/cmd/strings.c +++ b/cmd/strings.c @@ -7,8 +7,8 @@ */ #include +#include #include -#include static char *start_addr, *last_addr; diff --git a/cmd/sysboot.c b/cmd/sysboot.c index 0ea08fd7b5356137f6df589525bd7c5c17cbe9b3..d14c570d96ab090de1158216040d79c77832fc03 100644 --- a/cmd/sysboot.c +++ b/cmd/sysboot.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include #include -#include /** * struct sysboot_info - useful information for sysboot helpers diff --git a/cmd/temperature.c b/cmd/temperature.c index 41e422fc937d9073a3bf0dad7c3893e116619093..420965de14362ae154817e9c726bce2438144f9c 100644 --- a/cmd/temperature.c +++ b/cmd/temperature.c @@ -5,6 +5,7 @@ * Written by Robert Marko */ +#include #include #include #include diff --git a/cmd/terminal.c b/cmd/terminal.c index 369a755e0f5f3a8bd0321ddb6648163259987bbe..9e32a4191e1e8cb0762039bbbdf3f09b44f308b5 100644 --- a/cmd/terminal.c +++ b/cmd/terminal.c @@ -7,6 +7,7 @@ /* * Boot support */ +#include #include #include #include diff --git a/cmd/test.c b/cmd/test.c index b4c3eabf9f604279285e941f82399c5c89a38215..fa7c48fb9f103bd197e582cc88fa43935fb44e29 100644 --- a/cmd/test.c +++ b/cmd/test.c @@ -4,10 +4,10 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include -#include #define OP_INVALID 0 #define OP_NOT 1 diff --git a/cmd/thordown.c b/cmd/thordown.c index 70061bf8d4cccb4013b1b83310806f2ae197f576..48e22b31d025cfb436044157e6ae973f319903d9 100644 --- a/cmd/thordown.c +++ b/cmd/thordown.c @@ -6,6 +6,7 @@ * All rights reserved. */ +#include #include #include #include diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index 70ce53d01e874ac3f825b923232b9e94d3381202..bbd406fc66eca5055c11285439002d126db47336 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c index 305023af1e7d02babd16ab538ce6fb6a7e6c6e3e..a0492a5fdee34b51072abf4a63949dc8a13e2ac2 100644 --- a/cmd/ti/pd.c +++ b/cmd/ti/pd.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/cmd/time.c b/cmd/time.c index eee6084e9685ab77fa5d616d73d4e67a7abe25eb..db8c1892df4a437050e39bff6c0f3cc6b29ba444 100644 --- a/cmd/time.c +++ b/cmd/time.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include static void report_time(ulong cycles) diff --git a/cmd/timer.c b/cmd/timer.c index 04fcd84ac6a65a116d113452e491c7a2f1989f74..551be5dd54eef463f09c9475dda88e373279a383 100644 --- a/cmd/timer.c +++ b/cmd/timer.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include -#include static int do_timer(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c index 0aec752177099b30947eb5594f69fa0bfde451f2..57cfd355df1bbece8f5a7eeae1a1fbb4cacc8054 100644 --- a/cmd/tlv_eeprom.c +++ b/cmd/tlv_eeprom.c @@ -9,6 +9,7 @@ * Copyright (C) 2014,2016 david_yang */ +#include #include #include #include diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index 1cd57f901b6d2b023252ad3b02f823145f421ce8..a7dc23d85d5d5e1d4ee350d445afb4aee86ab97d 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 The Chromium OS Authors. */ +#include #include #include #include diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index 6e019d1c7291b8ef894f749df5937aab742e77ca..1b1efcd204d2724073cfedc43e6617daee4d2dc9 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -3,10 +3,10 @@ * Copyright (c) 2013 The Chromium OS Authors. */ +#include #include #include #include -#include #include #include #include diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 99c540b26de946e714e071de6efc06135daa3e2f..7e479b9dfe36e511196b5a5ed855b9daf82942cc 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -4,6 +4,7 @@ * Author: Miquel Raynal */ +#include #include #include #include diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index 9c8b1c74384abeee612d09f1535f72a8abb6aa32..c7fa6e775f55cf1bacaff5925007c8d5601bb361 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -3,10 +3,10 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include -#include #include #include #include "tpm-user-utils.h" diff --git a/cmd/trace.c b/cmd/trace.c index 937e6a682add0f1182b7f5edc1d8c91b9bf0f62f..2e3ee1d3ba23cc2ac8d73a924bb925c5dbb06666 100644 --- a/cmd/trace.c +++ b/cmd/trace.c @@ -3,11 +3,11 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include #include #include -#include #include static int get_args(int argc, char *const argv[], char **buff, diff --git a/cmd/tsi148.c b/cmd/tsi148.c index 113b4e673304b6089a1e7f60eed899e9a4663045..0d849d9979e46ed10535cc58295cef375d946532 100644 --- a/cmd/tsi148.c +++ b/cmd/tsi148.c @@ -7,10 +7,10 @@ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com */ +#include #include #include #include -#include #include #include diff --git a/cmd/ubi.c b/cmd/ubi.c index 8c1b5df057247783e5033625abf8dafe4b9deee4..0a6a80bdd1093ea536d957e81e05b8811584691c 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -11,6 +11,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/cmd/ubifs.c b/cmd/ubifs.c index 8fd39032eccf88ebe4da48be19ef44037fe81cd2..2a035bc7ae6f334a1957d8351f31cf2e8447e0d8 100644 --- a/cmd/ubifs.c +++ b/cmd/ubifs.c @@ -11,11 +11,11 @@ #undef DEBUG +#include #include #include #include #include -#include static int ubifs_initialized; static int ubifs_mounted; diff --git a/cmd/ufs.c b/cmd/ufs.c index 6e21fbb1685ceea926427691baa43599753e60f9..536bd85b75d8670a1afdc8fa59a35d5d1c9be3c8 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -5,9 +5,9 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * */ +#include #include #include -#include static int do_ufs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/cmd/universe.c b/cmd/universe.c index d1a712829d014e7d1a338dc2fff112c1941a9b6f..fb3a32d4d5a722ff646d7081e5c8ef680fc9b4fc 100644 --- a/cmd/universe.c +++ b/cmd/universe.c @@ -3,9 +3,9 @@ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com */ +#include #include #include -#include #include #include diff --git a/cmd/unlz4.c b/cmd/unlz4.c index fc5200117adc0261b4723c59598c33e9bacf6a09..5f20838e899c65109b22bfdd8b72d86083e1aa3a 100644 --- a/cmd/unlz4.c +++ b/cmd/unlz4.c @@ -4,9 +4,9 @@ * FUJITSU COMPUTERTECHNOLOGIES LIMITED. All rights reserved. */ +#include #include #include -#include #include static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/unzip.c b/cmd/unzip.c index e7a3f9808b2c51fa1acf18ac1344298977665635..bc6cee060432fc6040ba51d51f55ca3879360de7 100644 --- a/cmd/unzip.c +++ b/cmd/unzip.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include #include #include -#include static int do_unzip(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/usb.c b/cmd/usb.c index 3a3764a5b8623dbfe42d1620ac11cb7fc8e91079..23253f22231c7e65e8bc4369a0d013f9ad0d900f 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -10,6 +10,7 @@ * project. */ +#include #include #include #include diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c index 39259a3b09253cb643f26f4f2f98c79745fbff62..cbdda733533ca53ccccffd457bbb8a6305d261fb 100644 --- a/cmd/usb_gadget_sdp.c +++ b/cmd/usb_gadget_sdp.c @@ -6,6 +6,7 @@ * Author: Stefan Agner */ +#include #include #include #include diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index 47e8b70cd103128d0a1f82dcc06e04ee89edeb55..751701fe73aff2c579e022bbbc2adbaad9859f11 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -6,6 +6,7 @@ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/cmd/vbe.c b/cmd/vbe.c index 423d9e5f8f09bdb17c90f5969a111d5a96bc0f56..0e84b0e97aa45568cd6ca05256348649a68ba38a 100644 --- a/cmd/vbe.c +++ b/cmd/vbe.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/version.c b/cmd/version.c index 53db1a0b6bd187fb1a52bc586f26914ea8fceed5..d99a44f19fb378f99e96a656f8410a3e85b64265 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/cmd/video.c b/cmd/video.c index 91bd6de14dc16afb8c864533e2b088a4edda258f..942f81c1633627bd1fddf40392c3d743d1824f82 100644 --- a/cmd/video.c +++ b/cmd/video.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/virtio.c b/cmd/virtio.c index a42a563ab7270729412916dc15231b153a00fcb0..019e317e75588ff4322e5af32cd9f1a7a2421623 100644 --- a/cmd/virtio.c +++ b/cmd/virtio.c @@ -4,6 +4,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/cmd/w1.c b/cmd/w1.c index e462e786a96e574e8cbaf9e4a661b6e02b9b7bd5..3209e65f377fb403394b72641e170004ebe36348 100644 --- a/cmd/w1.c +++ b/cmd/w1.c @@ -4,6 +4,7 @@ * Microchip Technology, Inc. * Eugen Hristev */ +#include #include #include #include diff --git a/cmd/wdt.c b/cmd/wdt.c index c7a06cca181f9daafe28dfba46f935e0dd2c43f7..b9fdf7ad155fae50dbb52817f1d096f5221035b3 100644 --- a/cmd/wdt.c +++ b/cmd/wdt.c @@ -5,6 +5,7 @@ * Copyright (c) 2019 Michael Walle */ +#include #include #include #include diff --git a/cmd/wol.c b/cmd/wol.c index 45d4ae3f719e9bf4c1bc1b0354ca4e9f2528108e..f0d634322721065962f630d089e14a31e6887ab1 100644 --- a/cmd/wol.c +++ b/cmd/wol.c @@ -7,9 +7,9 @@ /* * Wake-on-LAN support */ +#include #include #include -#include #if defined(CONFIG_CMD_WOL) void wol_set_timeout(ulong); diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c index 7ca2e13ae2f8b89b6987608a75c59775a4661993..84822a3e3211bde1d4482ebb31f5eb77ed0b60ae 100644 --- a/cmd/x86/cbsysinfo.c +++ b/cmd/x86/cbsysinfo.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c index 2620ab8ee0255ce6b97e92a42f4e0cb343aa424d..82e4415b16ebffe2a810eaac2f424b5a52cca700 100644 --- a/cmd/x86/fsp.c +++ b/cmd/x86/fsp.c @@ -3,6 +3,7 @@ * Copyright (C) 2014-2015, Bin Meng */ +#include #include #include #include diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c index 2dd30808bd109096f12146d58dc8b09659de2e57..04d092dbe7ef4c5a8758d54101db5cbb47573b25 100644 --- a/cmd/x86/hob.c +++ b/cmd/x86/hob.c @@ -3,6 +3,7 @@ * Copyright (C) 2014-2015, Bin Meng */ +#include #include #include #include diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index b2afb598c73e6f970121ae332737a957057c9d82..6ad7a123a4471ce653e90cafc84e4d3b12c9a529 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -3,9 +3,9 @@ * (C) Copyright 2014 Google, Inc */ +#include #include #include -#include #include #include #include diff --git a/cmd/ximg.c b/cmd/ximg.c index 1467484df8d0daa90775c640d9e46290379aa45a..0e7eead8d192e992f13b66767a096fe1ba5479ce 100644 --- a/cmd/ximg.c +++ b/cmd/ximg.c @@ -11,6 +11,7 @@ /* * Multi Image extract */ +#include #include #include #include diff --git a/cmd/xxd.c b/cmd/xxd.c index 8ae05f910cb07143b2ae4a801b1c927342272abc..446ac1915ef543a37fb4c99dfa8899dd66aa59f7 100644 --- a/cmd/xxd.c +++ b/cmd/xxd.c @@ -4,6 +4,7 @@ * Roger Knecht */ +#include #include #include #include diff --git a/cmd/yaffs2.c b/cmd/yaffs2.c index d0724d9bea8fe8e8257d5f79f50e818dd110e720..27fbd1be8f750a6285a5dc0ef485f71bf848e6a9 100644 --- a/cmd/yaffs2.c +++ b/cmd/yaffs2.c @@ -13,6 +13,7 @@ * ... */ +#include #include #include diff --git a/cmd/zfs.c b/cmd/zfs.c index 2f831532c2e8de6c73b653da1d7804174c6f32e7..6ef1b56ab10b582a1c158f665719c4aa1b493e1b 100644 --- a/cmd/zfs.c +++ b/cmd/zfs.c @@ -8,6 +8,7 @@ * made from existing GRUB Sources by Sun, GNU and others. */ +#include #include #include #include diff --git a/cmd/zip.c b/cmd/zip.c index 2d25542882291d3315b65204a1aa174ddd0a14e9..08afd62b973d88b505035e8fd8bcd02e9b1e593e 100644 --- a/cmd/zip.c +++ b/cmd/zip.c @@ -4,10 +4,10 @@ * Lei Wen , Marvell Inc. */ +#include #include #include #include -#include static int do_zip(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/common/autoboot.c b/common/autoboot.c index 898a57bc92bda200840ba480d28cd85eb13a48d8..6f0aeae6bf331afeb7ca0c365e3da078a653092b 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -4,14 +4,13 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/common/bloblist.c b/common/bloblist.c index 11d6422b695a7544dc48749c38cfbcf852cffa3e..ad06d7a1795deb9b1799abfd9348fcfa4706f776 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY LOGC_BLOBLIST +#include #include #include #include diff --git a/common/board_f.c b/common/board_f.c index 212ffb3090b202dff40273abe76a892a40cb49da..039d6d712d05251d8a1d9133b6d3cda92e04ac8d 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -9,7 +9,7 @@ * Marius Groeger */ -#include +#include #include #include #include diff --git a/common/board_info.c b/common/board_info.c index 33c260b404e896c5e1ba86f4259f092dc808dafb..f4c385add90c7b92299b6ffe2b1cf321f0f98cae 100644 --- a/common/board_info.c +++ b/common/board_info.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/common/board_r.c b/common/board_r.c index c823cd262f16e0d7b038bea3b1f120beb2a1d56e..da0b80f24ff07b6ae767704df2a64505edc457a8 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -9,7 +9,7 @@ * Marius Groeger */ -#include +#include #include #include #include diff --git a/common/bootstage.c b/common/bootstage.c index fb6befcbc4a87306eb65aecb4701997d760b3686..0e6d80718fd59b92051fd8b47d9a4a6d74ed1be0 100644 --- a/common/bootstage.c +++ b/common/bootstage.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY LOGC_BOOT +#include #include #include #include diff --git a/common/bouncebuf.c b/common/bouncebuf.c index b2f87e4d939b307b3a0909983f2a7f2a355f81ee..934b83f7ec3fd2147f2a49386b09e0e642a74aa8 100644 --- a/common/bouncebuf.c +++ b/common/bouncebuf.c @@ -5,6 +5,7 @@ * Copyright (C) 2012 Marek Vasut */ +#include #include #include #include diff --git a/common/cli.c b/common/cli.c index 4694a35cd0e0c926b38c7d5ec17eb46048aaf726..1c33daf1149a85792f0cd6ceaf35de65140c0112 100644 --- a/common/cli.c +++ b/common/cli.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "cli: %s: " fmt, __func__ +#include #include #include #include diff --git a/common/cli_getch.c b/common/cli_getch.c index a5ed6eb6fcfa7841b4f54d5125c4e60b804e325e..0ee790877748125007bc77ea14e363bb15d2cb98 100644 --- a/common/cli_getch.c +++ b/common/cli_getch.c @@ -6,10 +6,8 @@ * Copyright 2022 Google LLC */ +#include #include -#include -#include -#include /** * enum cli_esc_state_t - indicates what to do with an escape character diff --git a/common/cli_hush.c b/common/cli_hush.c index 96a98209b9d292b57d6339b89b523af7d8c064e9..9cda97f30e3c7fb241bf74b12b49f54f4565e0fc 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -75,6 +75,7 @@ #define __U_BOOT__ #ifdef __U_BOOT__ +#include /* readline */ #include #include /* malloc, free, realloc*/ #include /* isalpha, isdigit */ diff --git a/common/cli_readline.c b/common/cli_readline.c index 4cb82b40149a9888fb881d0fb8b5bae39cc3dec7..cf4339d0e509e95d3b78c9d88ebf013c0ba0defc 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -8,6 +8,7 @@ * JinHua Luo, GuangDong Linux Center, */ +#include #include #include #include @@ -15,7 +16,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/common/cli_simple.c b/common/cli_simple.c index 266c444334ebfb23e8ce180986a7af8a7594fa94..f89ba92d1b05c50bfa01a52498de5b7a5558e1c9 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -8,6 +8,7 @@ * JinHua Luo, GuangDong Linux Center, */ +#include #include #include #include diff --git a/common/command.c b/common/command.c index 3f691399cbee5aea2afc407d609ebc1a3175f31a..af8ffdba8f8ce1a5cfa9c50bac58a6840e73b8d3 100644 --- a/common/command.c +++ b/common/command.c @@ -8,7 +8,7 @@ * Command Processor Table */ -#include +#include #include #include #include @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/common/console.c b/common/console.c index 63f78004fdbc95f9453f42ca1cf063747e0c1ab8..aa3053bc441405d177adaaf456a8265054ed038e 100644 --- a/common/console.c +++ b/common/console.c @@ -4,6 +4,7 @@ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it */ +#include #include #include #include diff --git a/common/cros_ec.c b/common/cros_ec.c index 9ccc8fa16cdb616c49e673fab812b6fdc7711964..249d1f19411ef56305da9cd65777a51d24f1a623 100644 --- a/common/cros_ec.c +++ b/common/cros_ec.c @@ -8,6 +8,7 @@ * Software Foundation. */ +#include #include #include #include diff --git a/common/ddr_spd.c b/common/ddr_spd.c index 2f6eb99bf0cfbf4259b1c34b0e662ee024a48fb0..58dc9b3781b7ca93eb2e5d51908a440dfc01c817 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -3,8 +3,8 @@ * Copyright 2008-2014 Freescale Semiconductor, Inc. */ +#include #include -#include /* used for ddr1 and ddr2 spd */ static int diff --git a/common/dfu.c b/common/dfu.c index 1af8194139c336389d9a331e8873022d13ef1ab4..0d154e8d4c482a0f48dcf311cbef17eacfade4b8 100644 --- a/common/dfu.c +++ b/common/dfu.c @@ -10,6 +10,7 @@ * Lukasz Majewski */ +#include #include #include #include diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 9549c59f3585f44bbdb0f57dceae522b03881f7b..a0616217d4953599b953a6571935f257e66b6d17 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -12,6 +12,7 @@ #define DEBUG #endif +#include #include #include diff --git a/common/edid.c b/common/edid.c index 865ba9daa78a8681ea685d1eb73f0d1fc13ce82b..556c4e3434b609711ae7f5e6e83f2fcd54b57633 100644 --- a/common/edid.c +++ b/common/edid.c @@ -9,6 +9,7 @@ * Copyright (C) Nalin Dahyabhai */ +#include #include #include #include diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index 3bacb1ae7eb79a20d94714ffdc20348c46de0356..f56eebe679f78c94b1e0e36809ed858242c3d017 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -6,8 +6,7 @@ * Igor Grinberg */ -#include -#include +#include #include #include diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 1a425c1754d4ab881ecca97b722d247f10ca77c8..5a9be1da061fe72c378a5692081fc1950fc4dd52 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -6,8 +6,8 @@ * Igor Grinberg */ +#include #include -#include #include #include diff --git a/common/event.c b/common/event.c index dda569d447851f559a83f98fb7b1f3543156eab5..16c2ba6cc92112907cb97b97331bac2a8c8a9ac2 100644 --- a/common/event.c +++ b/common/event.c @@ -9,13 +9,13 @@ #define LOG_CATEGORY LOGC_EVENT +#include #include #include #include #include #include #include -#include #include #include diff --git a/common/exports.c b/common/exports.c index 48b084c3861377b5cdd9ed5232863e45f078f6eb..20d8b759bc25da2c583f360ce1fa8af973bda3c6 100644 --- a/common/exports.c +++ b/common/exports.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/common/flash.c b/common/flash.c index 24ddc8bee72423bd1a6e3c5d3062757fec22aa54..848f44e59dfdb349dec436e1f1176b5303633814 100644 --- a/common/flash.c +++ b/common/flash.c @@ -6,10 +6,10 @@ /* #define DEBUG */ +#include #include #include #include -#include #include diff --git a/common/hash.c b/common/hash.c index ac63803fed95b553a015f2fd65dd0c7c644e2cb4..3d6b84de4738223ebb83048dd394b422f7157b94 100644 --- a/common/hash.c +++ b/common/hash.c @@ -10,6 +10,7 @@ */ #ifndef USE_HOSTCC +#include #include #include #include diff --git a/common/hwconfig.c b/common/hwconfig.c index afaa6cb37ab4252a3ebf9bddf9f50d08b46802d6..cac0b6348f469aa1bb0fdd13ca1a38dfe5c596bd 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -10,6 +10,7 @@ #ifndef HWCONFIG_TEST #include +#include #include #include #include diff --git a/common/init/board_init.c b/common/init/board_init.c index a06ec1caa2ca55d5f83742a981cb49c7a24ee122..ed2365daa35e3acb49c21b9f85dc6be48a90b588 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -6,7 +6,7 @@ * Written by Simon Glass */ -#include +#include #include #include #include diff --git a/common/init/handoff.c b/common/init/handoff.c index a7cd065fb385cb05089d059038dd987e5e83fd23..d0be1bb17a2cfe5800fc9ae920287b3593fbcd2b 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -5,6 +5,7 @@ * Copyright 2018 Google, Inc */ +#include #include #include diff --git a/common/iomux.c b/common/iomux.c index 1224c15eb718b5e78f625f57274000114d85c7de..c428f7110a7a790d5d8c95a05a604c721fdba7a0 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -4,6 +4,7 @@ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. */ +#include #include #include #include diff --git a/common/iotrace.c b/common/iotrace.c index a0a5613bd9b345e1fd5f192865fd01b3f4b7c733..63d0cca3a00434b22616da06d80c6946211acb27 100644 --- a/common/iotrace.c +++ b/common/iotrace.c @@ -5,6 +5,7 @@ #define IOTRACE_IMPL +#include #include #include #include diff --git a/common/kallsyms.c b/common/kallsyms.c index 49b3897078ae9490295784b1cf625fc847e9722c..13344e634b9910d5a6267492496db16e2dae0bb2 100644 --- a/common/kallsyms.c +++ b/common/kallsyms.c @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ +#include /* We need the weak marking as this symbol is provided specially */ extern const char system_map[] __attribute__((weak)); diff --git a/common/kgdb.c b/common/kgdb.c index 01a09f1762869b95abfdc992ae5c38d3e91e823e..29b09fcfe56b3cf4d6a69b54dbdc9dd0af648be2 100644 --- a/common/kgdb.c +++ b/common/kgdb.c @@ -87,6 +87,7 @@ * ****************************************************************************/ +#include #include #include diff --git a/common/kgdb_stubs.c b/common/kgdb_stubs.c index 256d88697d7e5b2d879b94841624f5071e4b0b72..66aed7cea1c7e268afcbb7274e1c71fa5208c0e8 100644 --- a/common/kgdb_stubs.c +++ b/common/kgdb_stubs.c @@ -7,6 +7,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include #include diff --git a/common/log.c b/common/log.c index dfee250b158a77f6284de849953702ba8b5cf537..42d35f04b689b26d21723d5c7c9bb518366dd9a4 100644 --- a/common/log.c +++ b/common/log.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/common/log_console.c b/common/log_console.c index c27101b8fe2237e0e2ef09b58a238fd8792a8c67..bb091ce21a4a616e763406b4f4c8e1a61acd0932 100644 --- a/common/log_console.c +++ b/common/log_console.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/common/log_syslog.c b/common/log_syslog.c index d01bb749c22d88c676902b0d0c4437975e114524..53c4def5d1c0f140780061d4f386342801602f16 100644 --- a/common/log_syslog.c +++ b/common/log_syslog.c @@ -5,6 +5,7 @@ * Copyright (c) 2020, Heinrich Schuchardt */ +#include #include #include #include diff --git a/common/main.c b/common/main.c index b0b6e74f5d3d385df0be498240d9001dfa2c5136..82d3aafa53c916229a206e84d053b44d53963257 100644 --- a/common/main.c +++ b/common/main.c @@ -6,6 +6,7 @@ /* #define DEBUG */ +#include #include #include #include diff --git a/common/malloc_simple.c b/common/malloc_simple.c index 4e6d7952b3ca9711113a5c9f5d14c1bf97aa1e8c..0a004d40e1ec80ae9e7b5d61c4f8d831462083d8 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_ALLOC +#include #include #include #include diff --git a/common/memsize.c b/common/memsize.c index 86109579c95402f2e2230971973700c87c2d1d94..d646df8b04cb6f5d2e26c84e6d6b34d84ad14f66 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/common/menu.c b/common/menu.c index e48424995b649561b9d346299dea3c9e97f3342f..b55cf7b9996795d95283ef493ee708cd2c52965f 100644 --- a/common/menu.c +++ b/common/menu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 9b8744e5d8bfd96eb139d48cac6f91822a5d3b15..194c84e7e89d1c2515e6dec34ca55283ec9801fe 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -9,6 +9,7 @@ * channel. */ +#include #include #include #include diff --git a/common/s_record.c b/common/s_record.c index 486dd93abd41f9b33cb5de625b7bcf5d2dbe5f71..2b7651fcffca011c4f272baf8319dae75c22f99e 100644 --- a/common/s_record.c +++ b/common/s_record.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include static int hex1_bin (char c); diff --git a/common/scp03.c b/common/scp03.c index 54b1bd54b6044f8384c7be92f16d99e065fbef4a..09ef7b5ba3dcbe9620fb049ad43cdff66e5a6dfd 100644 --- a/common/scp03.c +++ b/common/scp03.c @@ -4,11 +4,10 @@ * */ +#include #include #include #include -#include -#include static int scp03_enable(bool provision) { diff --git a/common/spl/spl.c b/common/spl/spl.c index 9a879e9fb102085071bfe0b166e704becc355e1f..e06bc75d36b29921d55f5e6bc6e22dc4ee9e1b70 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -6,7 +6,7 @@ * Aneesh V */ -#include +#include #include #include #include @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index 0b1c981a105d207196a85d3ce3c1c1c3ce3e3a2f..3bdd013a35fe138e43cf4d2bf8bfd27f6ceb0c87 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -9,6 +9,7 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index bc551c5c074cffc9f7bafddbea9da3b1cc07ad13..04eac6f306bdda08113d04cd220473c61149094e 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c index e172a2d7b83c0811a2abe558380fc25a32208e2f..0eefd39a51985247727bbcd579fb24c557a6c03a 100644 --- a/common/spl/spl_bootrom.c +++ b/common/spl/spl_bootrom.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH */ +#include #include __weak int board_return_to_bootrom(struct spl_image_info *spl_image, diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c index e9f381c392cd785c5675e7563d4b250c44c5e088..8a779da8fa1e08220c98ee5a417237ba5dfbb69a 100644 --- a/common/spl/spl_dfu.c +++ b/common/spl/spl_dfu.c @@ -5,6 +5,7 @@ * * Ravi B */ +#include #include #include #include diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index 76f49a5a8a6acbddbfcd96f139fd521a03921a05..2be6f04b02c5e6b2573a5556483dfc8dc094d657 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include #include +#include #include #include #include diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index bd8aab253a9895aab6898734ca11068a79e4059b..a52f9e178e664813f0109305ab6e2bfa1ccf7631 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -8,10 +8,12 @@ * FAT Image Functions copied from spl_mmc.c */ +#include #include #include #include #include +#include #include #include #include diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 988125be008d56d68fd1ac7da5c1d36ca07db406..e5195d460c490960ab35428dda64e112b0048a0e 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index 2c31777fcd3af2bc5c738f492a465df280197933..b4ea9241d68595c7e852c7eb0fbb49c9e251ee44 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -4,6 +4,7 @@ */ #define LOG_CATEGORY LOGC_ARCH +#include #include #include #include diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index a77893455f256d5b485f692b9150f4cef1e18aaf..08687ca8f6c49b9e9a03d9da4d9eaa01c74c4d9c 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Stefan Roese */ +#include #include #include #include diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ccab0be4be23d4d5ab83bc72fc7e2828e0c3b4d7..3d032bb27ce3ff89dff674498eaa48098cf6d9cf 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -5,6 +5,7 @@ * * Aneesh V */ +#include #include #include #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 5631fa6d5635044b33e2a4748d4bbeb5ed4c42fd..3b0a15242389e43d303d1338f9491e4c30dac3a4 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -3,6 +3,7 @@ * Copyright (C) 2011 * Corscience GmbH & Co. KG - Simon Schwarz */ +#include #include #include #include diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index be7278bb93344d756135fdf6f38919bb557fa9ae..898f9df705a29996da45c7575695dc49be137284 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -6,6 +6,7 @@ * (C) Copyright 2012 * Ilya Yanok */ +#include #include #include #include diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index ed76b5e1293b574b9598c401317c9a56a317843e..70745114efedf438f422db688297d34388641fce 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -3,7 +3,7 @@ * Copyright (C) 2012 Stefan Roese */ -#include +#include #include #include #include diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c index 0e15a3c7545a3d7104de8ddb6a03abb72068fcf1..c8774d67ecf132ae7bf81c9d5cacea47995a5be4 100644 --- a/common/spl/spl_nvme.c +++ b/common/spl/spl_nvme.c @@ -5,6 +5,7 @@ * */ +#include #include #include diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c index f6f65286c21670c887b4aa27e69b1da7efe6d8dc..53a8c6de89eb0f90bf26e7d0152b667e10e78c03 100644 --- a/common/spl/spl_onenand.c +++ b/common/spl/spl_onenand.c @@ -7,6 +7,7 @@ * Copyright (C) 2011 * Corscience GmbH & Co. KG - Simon Schwarz */ +#include #include #include #include diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index 5a26d7c31a43b24baf27cb7701973851bb61d77b..ec62aab929b9ccd7c9041785f98226e0dbf9fbf1 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -5,6 +5,7 @@ * * Based on common/spl/spl_atf.c */ +#include #include #include #include diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 5a23841f6981589344499bfdbd98611904379f31..8aeda237be13cc46fb970d0ddc0993327956d543 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -9,6 +9,7 @@ * Michal Simek * Stefan Agner */ +#include #include #include #include diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 67fc620d9bea91d330b1dbbb1f9fc5269c387ced..32746ce9f3cf70de6ad201a146ff93d3c97ce704 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -8,7 +8,9 @@ * Derived work from spl_usb.c */ +#include #include +#include #include #include #include diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 9ca80bd534f8ba5bad46d6df5e5c1664af6b6a33..9143c27bbf1d9028fcee587de8272fe9cb4a06cb 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -4,6 +4,7 @@ * Author: Stefan Agner */ +#include #include #include #include diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 2047248f39b0a3f608f7b33329f186508ea62c1e..941fa911040ea31b6439a8564149e3e7c04131b2 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Sean Anderson */ +#include #include #include #include diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 8ab4803f7c4bf5f1a34535d3e5409fc52d6c8668..89de73c726cd294db3922bf1173b0ab677306e2b 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -8,7 +8,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include #include #include diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index a8d3f43b452849d2e75fad6ae69317b17624a0c8..d7ab9efd1108c08c42e65f85635c186c6041d489 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -4,6 +4,7 @@ * Ladislav Michl */ +#include #include #include #include diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c index 932da56ab6db7bd9daa4617041001377c583a44a..479e2dc1826ecab55946c92293be5ed41dfc246b 100644 --- a/common/spl/spl_usb.c +++ b/common/spl/spl_usb.c @@ -8,8 +8,10 @@ * Derived work from spl_mmc.c */ +#include #include #include +#include #include #include #include diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 1465c3e46b921652626f5aee8d37b063035e380d..959915ffa6100e2f52336e104e8dedd8c16537ad 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -4,7 +4,7 @@ * Author(s): Vikas Manocha, for STMicroelectronics. */ -#include +#include #include #include #include diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 4c7222af612dc92d59d85899c46d524923f3182f..1faaa2c938d4ba637a25af552e320a2e3e857f25 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -8,11 +8,13 @@ * * Matt Porter */ +#include #include #include #include #include #include +#include #include #define BUF_SIZE 1024 diff --git a/common/splash.c b/common/splash.c index c5591293634a171be87c2a4ce57741df22e471bb..6820db683bd6cabbd68d45a499390717801c60b0 100644 --- a/common/splash.c +++ b/common/splash.c @@ -20,12 +20,11 @@ * */ +#include #include #include #include #include -#include -#include static struct splash_location default_splash_locations[] = { { diff --git a/common/splash_source.c b/common/splash_source.c index 5b27116044954fb3b7de7184ceb3bca966aae4c1..2ce0768833d9d1f4058fa005728aa21b5b283c58 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -5,6 +5,7 @@ * Authors: Igor Grinberg */ +#include #include #include #include diff --git a/common/stackprot.c b/common/stackprot.c index 4e3297b7d0069860fcad53b1357c886d47934697..6495951a773c5bf71c7d06576034024049692911 100644 --- a/common/stackprot.c +++ b/common/stackprot.c @@ -3,6 +3,7 @@ * Copyright 2021 Broadcom */ +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/common/stdio.c b/common/stdio.c index a61220ce4b9c606419534cf2178109fbbc138f20..e3354f092dc9f0dc07247e8a87bfa54f426b4e26 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/common/update.c b/common/update.c index eb0b60a2ce4897053ee2dadfe0e9102587fb2c6d..ec302ca68fb0925a590eb1e94f3db67507cb500d 100644 --- a/common/update.c +++ b/common/update.c @@ -6,6 +6,7 @@ * Bartlomiej Sieka */ +#include #include #include #include diff --git a/common/usb.c b/common/usb.c index 84b10f5c7d8c2b5993827e2aa8c84482684b4a0d..99e6b857c74ce281431995f2fd41a4328ed9e6b4 100644 --- a/common/usb.c +++ b/common/usb.c @@ -25,6 +25,7 @@ * * For each transfer (except "Interrupt") we wait for completion. */ +#include #include #include #include diff --git a/common/usb_hub.c b/common/usb_hub.c index 807f490bb6094788321f2f9e9f472ecd8eb06501..2e054eb93537a2e62e9bcc1ec53ac193895d5ba2 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -21,6 +21,7 @@ * Probes device for being a hub and configurate it */ +#include #include #include #include @@ -28,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/common/usb_kbd.c b/common/usb_kbd.c index f3b4a3c94e6de4f84cc9ee7cf7d95d131e82d94b..820f591fc5bb5d408be2fdba8868e51cb8d85c8b 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -6,6 +6,7 @@ * Part of this source has been derived from the Linux USB * project. */ +#include #include #include #include @@ -14,7 +15,6 @@ #include #include #include -#include #include #include #ifdef CONFIG_SANDBOX diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 68a04ac0412b3d1ebe42d795f71fcdad637c5eab..89e18a2ddad66c48b6d5e24fda05d9bcf8c2a284 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -7,6 +7,7 @@ * Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver */ +#include #include #include #include diff --git a/common/usb_storage.c b/common/usb_storage.c index a79ed2e23a441d6df3759349b040ee20a9212a90..774d5bdf54b4be7d56bfe12b5aaf86cc2d5bf248 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -32,6 +32,7 @@ */ +#include #include #include #include diff --git a/common/xyzModem.c b/common/xyzModem.c index 9feb240de28143d3caa516febbd7a1c3289ebd84..fb319f71190735a9fd07dad187deaeb1dca70a71 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -21,13 +21,12 @@ * *========================================================================== */ +#include #include #include -#include #include #include #include -#include /* Assumption - run xyzModem protocol over the console port */ diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 66bb4f6371d1be71de89a031794bd5145d7e8669..70498ca7fb2a912a3f8196f47f38e494e4280f29 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -8,7 +8,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_DEFAULT_DEVICE_TREE="am3517-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/am3517-evm" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_AM3517_EVM=y CONFIG_EMIF4=y @@ -58,6 +58,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-bo CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index fcade9172b7127d72a39c700d9509711522aafb5..a03509bf46715d55c230fdb23219368afe888dbb 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_MMC=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_NET is not set diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index a0caa367f9dbb0e67855d9393cf5859429d6ecbb..eccc15a0ae51f5de55b28797fe63bf5e5ae2d6f9 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 55d44700d6ecb8c15e15cd454cefb60cf2800e0e..acfe3934104f90fe3250c21d2b52acb45342ad51 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y @@ -28,6 +28,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -35,7 +36,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -60,7 +61,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -88,8 +88,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 48ee8b9fd258ba4eb56a4229a5e40d4fd6adcd5c..95fdb418d82b85591ccd2bbe18591830da8be4b8 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -9,7 +9,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y @@ -29,6 +29,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -36,7 +37,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set @@ -61,7 +62,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -89,8 +89,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig index 2608bb67679bcd4819cb3c0a22b40298a3e9752c..3d45d939abb254eac6d9cca08f79b0f03b0ed7fc 100644 --- a/configs/coolpi-4b-rk3588s_defconfig +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-coolpi-4b" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig index c5bb7a429574beef3e64ae361083d4471d2802c4..5190d69c1c582f8c225a97b496ad0b1ddf1f9454 100644 --- a/configs/coolpi-cm5-evb-rk3588_defconfig +++ b/configs/coolpi-cm5-evb-rk3588_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-coolpi-cm5-evb" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 1095a761ab84f459aea0393f60259717d1916c4d..30d1a93fec39cb08a7edcf9291544b662ef9e234 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -18,7 +18,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x80000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 4d6efbebf3481f8a70c161fd8d7dd5a07fcac9bc..936de610713631386de1911588da05d241b0774e 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -14,7 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8001ff00 CONFIG_ENV_SIZE=0x2800 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SYS_LOAD_ADDR=0xc0700000 CONFIG_ENV_ADDR=0x60100000 CONFIG_LTO=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 1f22b65302d904c1cd5e94173951fefebba095db..62cbd02b69af02e822fa91649ed69b67b2744ab3 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0000f20 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/davinci/da850-evm" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0x8001ff00 diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 4d8b495ccfec5674d4351af0dad1ac38e9324386..aedb4570ef8a5549c9566283c8730d30fc5df476 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -4,7 +4,8 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-eaidk-610" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -25,19 +26,24 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -50,5 +56,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 59b88a851e40e167132599a3f7f36152da14a289..454ed9e0a6287b26dcebd045918843d490d33978 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1" CONFIG_ROCKCHIP_RV1108=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_TARGET_ELGIN_RV1108=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 04a94e13a68a7d62f63968a3829bac1fd4d6fb5d..f4c2ea12adaae1caf5a9a72d39eec8d6bd6681c0 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-evb" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 53ad6777ec50b4156f4747fe86b0accfb86e14ac..bfb85223437d58b178d26e5ad24ced6d4fb08e50 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d81c7f9604e162449babe4b27a83bc2d631ea0e2..756d6952de1f8aeb18e327e1f742593778212fd1 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-evb" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y @@ -15,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -27,10 +27,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_HS400_SUPPORT=y @@ -39,6 +38,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -47,8 +48,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -71,5 +70,4 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index e71d6705568f7ab5f398bee555a388de19d68b43..2076f55122befba0ab0eb92ae0d13dca4a04d5bf 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-evb1-v10" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 @@ -14,7 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig index a8c32c4fcf4a59df0f9d1e12161274b1155f2471..1d5585677a4618ff9c074e8c3baeeec94c5048b6 100644 --- a/configs/evb-rk3588_defconfig +++ b/configs/evb-rk3588_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-evb1-v10" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_EVB_RK3588=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 25453fba0dc1f5cc772659efa739e9ea4f9665bd..6204cb4b9634059e67cc9632a7b8dfcc4daf8c0c 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -5,7 +5,7 @@ CONFIG_TEXT_BASE=0x60000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 -CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb" CONFIG_ROCKCHIP_RV1108=y CONFIG_DEBUG_UART_BASE=0x10210000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 618f6baf91a50b46eea2811636373dbd143ea974..dce8093376d61c9a7e1d8a663a9651038159a374 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,64 +2,66 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-ficus" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 545c047c6df86f266161770ce3e919df92d0215f..edacef29edfcc4b021050d72ac0fcfda1b77cd91 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-firefly" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y @@ -16,7 +16,7 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -29,24 +29,28 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +67,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index 033702fd149fe32fb8ea319aaa4baafd3864b928..66a33afbbaf06be4adb4c012f6635f0c6e8cb747 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index 87a171701e42a860ebc3e1c2c6f6adc273be3064..42bc2c9a7656cebf8265acccb8bf03985c2cb325 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index f29505ea150b428272bf0a580db88b53fbff8202..b69cf4cd057a0c331fc7eeb9a86b43278f5c3597 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-jaguar" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_SPL_SERIAL=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 310250ed4a528b543b7e4ff54baf57c349a22f16..60d4770cb0e47d722dfa3af75f97217d454c6135 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -3,43 +3,63 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge-captain" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -48,6 +68,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +84,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 3fe5542d1256595ef84facccb2f97629c19122c3..1321ca1ea59e75bc6ecaaf932c332e87bf55822c 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -3,20 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " @@ -24,21 +31,28 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_PHY_REALTEK=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -47,6 +61,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -62,5 +77,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 4b41454d710da4f366c81c2aa719f98e1445d36a..3898142c5c7cde7fe0fb3d50113439ee01ef4756 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -3,43 +3,63 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-khadas-edge-v" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -48,6 +68,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +84,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index e5088341389ab2560f3923b23d973968f1d34c0b..ea96e1ef758fd9c5008322a53f22e49505a803c3 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -4,7 +4,8 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-leez-p710" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,8 +14,9 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -24,17 +26,23 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -56,5 +64,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index ea67b6a728645991b1475b7d0513530e4ba37013..88593bfa705167823f7434d8354cac17640cf24d 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index cdfacb66e6783f35c650df9bda9c460f411f8f7b..c63f4c076d55367f448dc3539526f9a33d168f92 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,9 +2,10 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopc-t4" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y @@ -15,7 +16,7 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,20 +29,26 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -66,5 +73,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig index 738dda026b01ef9cacb278769ee774bb38a1b72d..926267f93ad588a5ddbfe4e5f080bb9e6ce70fa0 100644 --- a/configs/nanopc-t6-rk3588_defconfig +++ b/configs/nanopc-t6-rk3588_defconfig @@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-nanopc-t6" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 51596f57ae35dc064562d213330b05fae568867e..08c21ee6e5d2f7d73056f5dcbd5d6b561169b02a 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -2,18 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,25 +25,37 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -61,5 +77,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 2af84fb6ff1705f27105818ebcc29fe8dd574ef8..ad01431cc3ae4d00358a045b5f321ef91d67c848 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -2,18 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,25 +25,36 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -61,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 1b76f98e0df7cac7732827f92afa33da87c50a69..34f892d5d3c1054c00e20e9e8cdaf298326f78ed 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -2,18 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-m4b" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,25 +25,36 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -61,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index c176c5a121111e11ef5c9c9a0ca9fb0ed1f03dc1..f38235489ff7a606b6e43bf79c2fec4fdca60334 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -2,9 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-neo4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -25,19 +27,25 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -61,5 +69,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index beef682a582e2964dd54a867fe1a91b9469a9959..f311a0a80ba7449f003aaae0591dac74af189be5 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 8960c1afaba566382356eadc71eaf5836967bba5..533dc1029f73fffc5ee3f12196f2fcf4e46b8a27 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 96e67e248d3254c90ec55a826fd774ff158eaecc..2591a9cc8ab25b3aefbd3690cdbe91a97ec0a95b 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index ea01d323541b993fb21468d1c521a6542f6871fc..ada04b46cb169226847f8640f11022ddd6dfb5d0 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -2,9 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-r4s" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -25,19 +27,25 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y @@ -64,5 +72,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 00743b7f926c402fd641c0cd982ec0ff728c29da..4a6c320faf5ca6c340fee841ec4e18d8e7171f23 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 91e3a19dea6dc5e7a375a1cad736a559ec07aabc..7ab12e619acfb6f23329a3b7771d1bc95a5e7f1c 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 56198556affcf272039f99bf4d54654837f02dc7..ac281e65392c8397a40818e07e8c92a6b1c6c74b 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_RK3588_NEU6=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 40baec319c9e5779245a97bda344cf84026592da..c01e5fb0d044e93d8d51cddef4c4b978045d4bde 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_RK3588_NEU6=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index e749f9af9d2386b312b3e1f189f053f513feb598..b5263caff6dcd5f1c52f1d5820c18c8b59e20da1 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 -CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-odroid-m1" CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index f9b8ac5c07945a32c2bd03dae563777b222f36bb..23b2e503385d5ab2484248f830e44e262c4e7ea3 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -9,7 +9,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-35xx-devkit" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set @@ -59,6 +59,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl- CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 256ca9921d1f4f4b734d88f3c0da540020b443dc..a5f242ff40cf43b7c672b7187033b54db59ba7cf 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -9,7 +9,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-35xx-devkit" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set @@ -61,6 +61,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl- CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 00c4d847d27065da94c2bf69035a4d87ec8d72a5..d081d4e0fb4618f6a970eb6fef9731acdeb56c13 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -9,7 +9,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-37xx-devkit" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set @@ -58,6 +58,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl- CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 04ba40111e31416d0ca5f38634c82686ab284313..68e89d245eeed964579f575ce3f4ff621749f0ae 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -9,7 +9,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit" +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-37xx-devkit" CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set @@ -61,6 +61,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl- CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig index ba8005363ad0edde32616e33c225b3cc82816998..138a633f320e2b39d31b6403a808386493db53f4 100644 --- a/configs/orangepi-5-plus-rk3588_defconfig +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-plus" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig index d61f85aaa8c60308ff0f15247dbdeb8cf81b92c6..33529d4cac312eca073b94142093811ac4ea7ef3 100644 --- a/configs/orangepi-5-rk3588s_defconfig +++ b/configs/orangepi-5-rk3588s_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-orangepi-5" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 5fbbd5fc655897e2c9f5e88349fc177b1541d042..14cdbd813c81f0d5e2ec0229613d6ad9ff914c5c 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus-lts" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index c5afe5ea6e5c180d76d6b00201fbbf4ef8e84178..7fe58e7a14674759fa3cbba8c494f4462bce8a4e 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-orangepi-r1-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index c6a92b2decf327ad46f74f6c8a5b0b50fa089e0d..5dfbdeaf17f5f2f1bc6e6a74930f3bef09f9c864 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -2,9 +2,11 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-orangepi" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -25,19 +27,26 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -56,5 +65,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index e9a287cb441f7d6251d4231214e66c1f96962fe7..9f42edd723249f329ab69b3aa74eec647cfc2eaf 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -147,7 +147,7 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 1064fb0e793682e3f4bf4394cb8cdec87655c145..9b52f8ad0644c6a149a32be4d8d2de8729917b96 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" -CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y @@ -160,7 +159,7 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 61d784fa17f6efb6873efe05f4a2d46c98a2ffdd..15a7e7089e73ff3e153de2a0f0cd16818d364c2a 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -171,7 +171,7 @@ CONFIG_USB_STORAGE=y CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_SPL_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 017054a8e12b6371cc3301502ddef0fb613cb4ed..2f6b158a6772973e3c6ab63b1b2b152f3824414b 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -62,7 +62,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index b3da43a5bf1eaf1e9e1ee9f416ab04f7f6b078a7..b42a410da69c630701237c675892139740fb180e 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -53,7 +53,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Phytec" +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff CONFIG_CI_UDC=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 23ac24a0bffe5376c0abbb353ffbcc825303d36a..5d3e32f9108e2ae536c7e935617e6f3b66076bec 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -2,11 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-pinebook-pro" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -35,16 +36,16 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y @@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -72,11 +75,10 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -99,5 +101,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 8c6323f6c516adc88f10322ccfb46d5fa1dd670a..0eade88068f4df269b8b7da662df52da4217aa13 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -3,10 +3,10 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-pinephone-pro" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -33,17 +33,15 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y @@ -55,20 +53,20 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y @@ -88,5 +86,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig index ad237edf8d9378e95252cef306ae3a005fa694c9..e46acf3a3b58cc009a01189ff66d9647640d47b4 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 14a7bc8b1e00750a92a13f05b903a23d10213858..34a0b575991e4e75776f1c60b3560cd3e3d1e93e 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -2,26 +2,17 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-puma-haikou" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0 CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_PUMA_RK3399=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -31,9 +22,8 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 -CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_PAD_TO=0x38000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y @@ -52,7 +42,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y @@ -61,7 +50,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig index 535e34fb99035103be357fe093aa399ae333387a..1ea8e0f40cc46cb467db339cf64fe7b20733060a 100644 --- a/configs/quartz64-a-rk3566_defconfig +++ b/configs/quartz64-a-rk3566_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-quartz64-a" CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig index e197defd3af3926aad794c732309e47deb7df998..f61b2c181a1f615810d3ef693003758380eea427 100644 --- a/configs/quartz64-b-rk3566_defconfig +++ b/configs/quartz64-b-rk3566_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-quartz64-b" CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig index 33cbda88285f0ddea527a272dafe2f0347ed6fd3..06c5cff3ca55847189d1cab8b252cfeb1d075cdf 100644 --- a/configs/quartzpro64-rk3588_defconfig +++ b/configs/quartzpro64-rk3588_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-quartzpro64" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_QUARTZPRO64_RK3588=y diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index d23ab57ada57c73cc0a0e3e4efc7627c4333da18..48c8fcf5a66b038433670506c2ad406523281915 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-cm3-io" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index dbb77b85f5d91aaae0dce5302b3aab6aace2a903..496fee0e0a44894d2ff42c18372b0ae8f78cb787 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index ef58bd6575322e762dc1ea7020958bfc92fba159..862ea4301f25bbfb0d675cea7d37fb71102e92d7 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-roc-cc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 1dbd39e6b5e7812a249e38a47f14f91b3904a818..91b9422e26fbd5669c40a0ac7ec69d1f9739148a 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-roc-cc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 1ff4e15c8c1008d39581382988d0ab582f1a0407..a57899bfdfa08151858dc3dec5c6fedcadf73a09 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -4,10 +4,11 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-roc-pc-mezzanine" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -38,18 +39,22 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -57,6 +62,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set @@ -84,5 +90,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index a41f71d9e1670bf7b54ca7ba1c3b1657f2ea1bd2..b45f0e0a89948072992f7b7f31fc77e784d1e693 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -8,7 +8,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-roc-pc" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -20,7 +20,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -38,30 +37,33 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -87,5 +89,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index b06b57fe0bf35e78f823754b381753e9c3c8f536..66ac2f6d7aac03953c22b166314391ba2879a250 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3a" CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index bebea4fd06913c6f012974498e62032555deafcd..80dc44986e7130103fa8bd5afe713a96fb2799fa 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -3,23 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" -CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-4c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -27,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -35,29 +38,38 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -78,7 +90,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 712502517eb265e35d5f40d28f04d638ff842f67..f52d4bf9913bb47424a11eb09a292a2a5857183b 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -3,25 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" -CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-4se" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y @@ -36,17 +40,28 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -57,9 +72,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -80,7 +97,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 315b8b853fc334ede7e691870e033e8fb3da2ca5..e71c4588b9428f73b45bb631b121b48d3ef30a82 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -5,8 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" -CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-pi-4a" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -18,8 +17,8 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -42,10 +41,11 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -57,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -69,6 +73,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index e1adec6001743c5f16329e5e454308c8aa17702a..14373933a34f43268b2a36346f4301011dceb69e 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -3,23 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" -CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock-pi-4c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -35,16 +41,28 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -55,9 +73,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -78,7 +98,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 23029255bca291f4119e4edbe135e00ceaa8f5f0..5cc54af3ca56338ccfffb9ed49f353db7fd17940 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock-pi-e" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_DEBUG_UART_BASE=0xFF130000 diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 6889cdcbf7d88169c9835f751153ff2102ace548..ec995a54a0ee6869e371a851b2bdea1fc2d16894 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -2,10 +2,9 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399pro-rock-pi-n10" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y @@ -18,7 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -31,22 +30,25 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 37a124eae181ec1f6f16cf898b8d288143c2d5df..c15ba3d8a4514623a8fdfd1fd17988859d1cacc0 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-pi-s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index 01df911d9dc84eadaf5a9da1c827fbf412f6ddde..c09e6655f0218b09f9b1561eee272dd27faef905 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5a" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_ROCK5A_RK3588=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 9e14b14af7c6c81488ea76808e491b02a234a15e..fc118cea7bae776062f99fff25396cc772112345 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5b" CONFIG_ROCKCHIP_RK3588=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index b0be1d1d76334e241637c684a78b3a205b3e6eab..9d77dfb7098ace6bf9992472af858e87fde37f8c 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-rock64" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3328=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 13575c5800547eb73c21faf6ab38ff544b6ce54c..8fff3ed17c24373108c6e3f2a506cefd67f19712 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rock960" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y @@ -12,11 +12,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,15 +27,18 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -52,8 +54,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -73,9 +73,11 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index d66b4a9d8900a69c6d7033ad87f6b71308145f01..fc0804a0b80d42e391cde3b4399071a687800862 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -2,10 +2,12 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-rockpro64" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -17,11 +19,8 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -35,15 +34,15 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -59,7 +58,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -67,11 +69,10 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 @@ -99,5 +100,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index bed143d64d6d0c22a8d3a9a1b00ac150cd53a8ef..98f8904c9180f8791c82448831d15ffe59277fcb 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index e4e4843e8cd58d59ede57395afa9c0e251b792a4..1b8676e1d10533f180cc4fe68c6f99c76d69f99b 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 215396599e417d3770c2e622f46f448d94f2f32e..abc10a79adaed4d84b2037d0d8bcc312f9fa0fb4 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index d1ec55e558aa0d23e20563bed7ebf1944731db24..3c8f8fc1bb75f6e193eaefca947db3b7a43c636b 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 8e9c35b3ceff1b63efc4fe6e11b30f7d675cfaa9..9853c448809ad90ae3771d69eb1aabfb12639dca 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 89d6372c1de010b51ab55e6e01624f56bac8bbd7..060a8809506a1c7fd52c1ca7be732fd0c3a097bb 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig index 9d565c162ef239eb7c3c687c5b072ec0f8f14395..82910daf7cc6b00dee7bc326f0f1680d0abefa22 100644 --- a/configs/soquartz-blade-rk3566_defconfig +++ b/configs/soquartz-blade-rk3566_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-blade" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_QUARTZ64_RK3566=y diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig index fe2c771db71baa3214cfe4f7d1c5448e5ecb94ce..5744f1baa81a0cb4d907a082c0f9c744db4b7490 100644 --- a/configs/soquartz-cm4-rk3566_defconfig +++ b/configs/soquartz-cm4-rk3566_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-cm4" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_QUARTZ64_RK3566=y diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig index db9eee2175149b8bf202212d90874389c4f2f6e2..920df9b622d7d4274f9e27fc74a4a7b70142f429 100644 --- a/configs/soquartz-model-a-rk3566_defconfig +++ b/configs/soquartz-model-a-rk3566_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-soquartz-model-a" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_QUARTZ64_RK3566=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 3bbd1dbd67c79fa52ecdbf0604bc222b46013d2e..174ac24dc746a12117624fea3c5e94ea47e12fe4 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -62,6 +62,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_PROMPT="StarFive # " CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_SIZE=512 diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig index 76bfa50c306cdca58d4003e0ab79e0826530e1ac..5a190357e454ab4da328ed963619cacf15cd3608 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig index 038b14769e501eebf94bf6d1c46d462f9246f0f2..e6e1bda7ec1ae0d5b9b99c04c8a0a55849c2fe18 100644 --- a/configs/turing-rk1-rk3588_defconfig +++ b/configs/turing-rk1-rk3588_defconfig @@ -3,17 +3,12 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SF_DEFAULT_MODE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-turing-rk1" CONFIG_ROCKCHIP_RK3588=y -CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_TURINGRK1_RK3588=y CONFIG_DEBUG_UART_BASE=0xFEBC0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_PCI=y CONFIG_DEBUG_UART=y @@ -29,8 +24,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -64,11 +57,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_SF_DEFAULT_BUS=5 -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_XMC=y -CONFIG_SPI_FLASH_XTX=y +# CONFIG_SPI_FLASH is not set CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y @@ -84,7 +73,6 @@ CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y -CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/disk/disk-uclass.c b/disk/disk-uclass.c index ee3cc4407d76bee65bb5b5ef48209ed8ce5c3f89..efe4bf1f9490ba8e972569a7ac8aa61b25c21de5 100644 --- a/disk/disk-uclass.c +++ b/disk/disk-uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_PARTITION +#include #include #include #include diff --git a/disk/part.c b/disk/part.c index bc932526f906af54e348c1ef31a80b33ca5db105..2bee6695828a4a1f5dcf0f6a83d332a16ad2323b 100644 --- a/disk/part.c +++ b/disk/part.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 9b0f2fe749854355470b4034831b66367c5b08de..65e30fea558d5ccbcddc3b167cb62b92f0ade3e1 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -4,12 +4,12 @@ * Hans-Joerg Frieden, Hyperion Entertainment * Hans-JoergF@hyperion-entertainment.com */ +#include #include #include #include #include "part_amiga.h" #include -#include #undef AMIGA_DEBUG diff --git a/disk/part_dos.c b/disk/part_dos.c index e6b5295e0ec4d70ae494d0cca0b159f1642d6f1f..567ead7511de747674f89850b3fc18c0c526d0d4 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -13,11 +13,11 @@ * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 */ +#include #include #include #include #include -#include #include #include #include "part_dos.h" diff --git a/disk/part_efi.c b/disk/part_efi.c index b1a03bd165e07f497df93d66da6acf4415efbd9a..4ce9243ef25cdb3fa66275e49597af092867c0bb 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -12,6 +12,7 @@ #define LOG_CATEGORY LOGC_FS +#include #include #include #include diff --git a/disk/part_iso.c b/disk/part_iso.c index 6e05b2feffbab4073c309d56cc24dc14199b0846..6ac6d95be92171929069098e6e5997772d7b7577 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -4,6 +4,7 @@ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. */ +#include #include #include #include diff --git a/disk/part_mac.c b/disk/part_mac.c index 81a65823be9939d72b4441d3e3c462b95e236c21..db5e203be59257a4bb9d011cbd2fe93efaf45a09 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -12,6 +12,7 @@ * http://developer.apple.com/techpubs/mac/Devices/Devices-126.html#MARKER-14-92 */ +#include #include #include #include diff --git a/doc/board/AndesTech/adp-ag101p.rst b/doc/board/andestech/adp-ag101p.rst similarity index 100% rename from doc/board/AndesTech/adp-ag101p.rst rename to doc/board/andestech/adp-ag101p.rst diff --git a/doc/board/AndesTech/ae350.rst b/doc/board/andestech/ae350.rst similarity index 100% rename from doc/board/AndesTech/ae350.rst rename to doc/board/andestech/ae350.rst diff --git a/doc/board/AndesTech/index.rst b/doc/board/andestech/index.rst similarity index 100% rename from doc/board/AndesTech/index.rst rename to doc/board/andestech/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index 428faa810bec4ee78e4349eeebfcabaf94e0b30d..2340eeb07778b10bb1af01d7a3292e846c9c08d4 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -8,7 +8,7 @@ Board-specific doc actions/index advantech/index - AndesTech/index + andestech/index allwinner/index amlogic/index anbernic/index diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst index 2762bf74c11860f1705353c6f9366639adb00756..d369b986ccd5f1af0c98eb8e2139db6be392dde3 100644 --- a/doc/board/starfive/index.rst +++ b/doc/board/starfive/index.rst @@ -6,5 +6,6 @@ StarFive .. toctree:: :maxdepth: 1 - milk-v_mars.rst + milk-v_mars + milk-v_mars_cm visionfive2 diff --git a/doc/board/starfive/milk-v_mars_cm.rst b/doc/board/starfive/milk-v_mars_cm.rst new file mode 100644 index 0000000000000000000000000000000000000000..b31de6043bbafa17261f5b6ecb2dd32a51caaa5b --- /dev/null +++ b/doc/board/starfive/milk-v_mars_cm.rst @@ -0,0 +1,193 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Mars CM +============== + +U-Boot for the Milk-V Mars CM uses the same U-Boot binaries as the VisionFive 2 +board. In U-Boot SPL the actual board is detected and the device-tree patched +accordingly. + +The Milk-V Mars CM Lite comes without eMMC and needs a different pin muxing +than the Milk-V Mars CM. The availability and size of the eMMC shows up in the +serial number displayed by the *mac* command, e.g. +MARC-V10-2340-D002E016-00000304. The number after the E is the MMC size. U-Boot +takes a value of E000 as an indicator for the Lite version. Unfortunately the +vendor has not set this value correctly on some Lite boards. + +Please, use CONFIG_STARFIVE_NO_EMMC=y if EEPROM data indicates eMMC is present +on the Milk-V Mars CM Lite. Otherwise you will not be able to read from the +SD-card. + +The serial number can be corrected using the *mac* command: + +.. code-block:: + + mac read_eeprom + mac product_id MARC-V10-2340-D002E000-00000304 + mac write_eeprom + +.. note:: + + The *mac initialize* command overwrites the vendor string and the MAC + addresses. This is why it is avoided here. + +By default the EEPROM is write protected. The write protection may be overcome +by connecting the "GND" and "EN" test pads on top of the module. + +Building +~~~~~~~~ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE= + +The M-mode software OpenSBI provides the supervisor binary interface (SBI) and +is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot. +Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use +a current release. + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=generic FW_TEXT_START=0x40000000 + +(*FW_TEXT_START* is not needed anymore after OpenSBI patch d4d2582eef7a +"firmware: remove FW_TEXT_START" which should appear in OpenSBI 1.5.) + +Now build the U-Boot SPL and U-Boot proper. + +.. code-block:: console + + cd + make starfive_visionfive2_defconfig + make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin + +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well +as the FIT image (u-boot.itb) with OpenSBI and U-Boot. + +Device-tree selection +~~~~~~~~~~~~~~~~~~~~~ + +Depending on the board version U-Boot sets variable $fdtfile to either +starfive/jh7110-milkv-mars-cm.dtb (with eMMC storage) or +starfive/jh7110-milkv-mars-cm-lite.dtb (without eMMC storage). + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + + env set fdtfile my_device-tree.dtb + env save + +or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to +provide a default value. + +The variable *$fdtfile* is used in the boot process to automatically load +a device-tree provided by the operating system. For details of the boot +process refer to the :doc:`U-Boot Standard Boot <../../../develop/bootstd>` +description. + +Boot source selection +~~~~~~~~~~~~~~~~~~~~~ + +The low speed connector nRPIBOOT line is used to switch the boot source. + +* If nRPIBOOT is connected to ground, the board boots from UART. +* If nRPIBOOT is not connected, the board boots from SPI flash. + +Compute module boards typically have a switch or jumper for this line. + +Flashing a new U-Boot version +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is +in file u-boot.itb. + +Assuming your new U-Boot version is on partition 1 of an SD-card you could +install it to the SPI flash with: + +:: + + sf probe + load mmc 0:1 $kernel_addr_r u-boot-spl.bin.normal.out + sf update $kernel_addr_r 0 $filesize + load mmc 0:1 $kernel_addr_r u-boot.itb + sf update $kernel_addr_r 0x100000 $filesize + +For loading the files from a TFTP server refer to the dhcp and tftpboot +commands. + +After updating U-Boot you may want to reboot and reset the environment to the +default. + +:: + + env default -f -a + env save + +Booting from UART +~~~~~~~~~~~~~~~~~ + +For booting via UART U-Boot must be built with CONFIG_SPL_YMODEM_SUPPORT=y. + +With nRPIBOOT connected to ground for UART boot, power the board and upload +u-boot-spl.bin.normal.out via XMODEM. Then upload u-boot.itb via YMODEM. + +The XMODEM implementation in the boot ROM is not fully specification compliant. +It sends too many NAKs in a row. Tio is a terminal emulation that tolerates +these faults. + +:: + + $ tio -b 115200 --databits 8 --flow none --stopbits 1 /dev/ttyUSB0 + [08:14:54.700] tio v2.7 + [08:14:54.700] Press ctrl-t q to quit + [08:14:54.701] Connected + + (C)StarFive + CCC + (C)StarFive + CCCCCCCC + +Press *ctrl-t x* to initiate XMODEM-1K transfer. + +:: + + [08:15:14.778] Send file with XMODEM + [08:15:22.459] Sending file 'u-boot-spl.bin.normal.out' + [08:15:22.459] Press any key to abort transfer + ........................................................................ + .......................................................................| + [08:15:22.459] Done + + U-Boot SPL 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200) + DDR version: dc2e84f0. + Trying to boot from UART + CC + +Press *ctrl-t y* to initiate YMODEM transfer. + +:: + + [08:15:50.331] Send file with YMODEM + [08:15:53.540] Sending file 'u-boot.itb' + [08:15:53.540] Press any key to abort transfer + ........................................................................ + … + ...............| + [08:15:53.540] Done + Loaded 1040599 bytes + + + U-Boot 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200) + +Booting from SPI flash +~~~~~~~~~~~~~~~~~~~~~~ + +With nRPIBOOT disconnected from ground for SPI boot, power up the board. You +should see the U-Boot prompt on the serial console. diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index fa3cd6aec82ee2ee375db99f10ae19081c7c897c..f6248cdcb1e1d7419da478296aea79155ac4a87d 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -110,8 +110,9 @@ Include files You should follow this ordering in U-Boot. In all cases, they should be listed in alphabetical order. First comes headers which are located directly in our -top-level include diretory. Second are headers within subdirectories, Finally -directory-local includes should be listed. See this example: +top-level include diretory. This excludes the common.h header file which is to +be removed. Second are headers within subdirectories, Finally directory-local +includes should be listed. See this example: .. code-block:: C @@ -128,6 +129,9 @@ For files that need to be compiled for the host (e.g. tools), you need to use ``#ifndef USE_HOSTCC`` to avoid including U-Boot specific include files. See common/image.c for an example. +If you encounter code which still uses a patch to remove that and +replace it with any required include files directly is much appreciated. + If your file uses driver model, include in the C file. Do not include dm.h in a header file. Try to use forward declarations (e.g. ``struct udevice``) instead. diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 64757b4df18bd352a127f98664617555e11783ad..383f4480c6ececb8837d7daccd44c25be54585eb 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -71,7 +71,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.07-rc2 was released on Mon 06 May 2024. -.. * U-Boot v2024.07-rc3 was released on Mon 20 May 2024. +* U-Boot v2024.07-rc3 was released on Mon 20 May 2024. .. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024. diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst index 44b544fa78b46e8a7e7e40dd8c2740c6f34c7d07..bb1145da268bbf5a0d1084b9f62ea7d88f6dcbc5 100644 --- a/doc/develop/tests_writing.rst +++ b/doc/develop/tests_writing.rst @@ -281,6 +281,7 @@ new one of those, you should add a new suite. Create a new file in test/ or a subdirectory and define a macro to register the suite. For example:: + #include #include #include #include diff --git a/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt deleted file mode 100644 index 4a56f78f555bc47c1d4ece8681e303b1521b7553..0000000000000000000000000000000000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt +++ /dev/null @@ -1,42 +0,0 @@ -Rockchip Dynamic Memory Controller Driver -Required properties: -- compatible: "rockchip,rk3399-dmc", "syscon" -- rockchip,cru: this driver should access cru regs, so need get cru here -- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here -- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here -- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here -- rockchip,cic: this driver should access cic regs, so need get cic here -- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address -- clock: must include clock specifiers corresponding to entries in the clock-names property. - Must contain - dmc_clk: for ddr working frequency -- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver: - Must contain - Genarate by vendor tool and adjust for U-Boot dtsi. - -Example: - dmc: dmc { - bootph-all; - compatible = "rockchip,rk3399-dmc"; - devfreq-events = <&dfi>; - interrupts = ; - clocks = <&cru SCLK_DDRCLK>; - clock-names = "dmc_clk"; - reg = <0x0 0xffa80000 0x0 0x0800 - 0x0 0xffa80800 0x0 0x1800 - 0x0 0xffa82000 0x0 0x2000 - 0x0 0xffa84000 0x0 0x1000 - 0x0 0xffa88000 0x0 0x0800 - 0x0 0xffa88800 0x0 0x1800 - 0x0 0xffa8a000 0x0 0x2000 - 0x0 0xffa8c000 0x0 0x1000>; - }; - - &dmc { - rockchip,sdram-params = < - 0x2 - 0xa - 0x3 - ... - >; - }; diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 5b4df36804b5d01cbcc044bd48f61332346f65c7..426f41e1a028a447c121923e5fba70206cd22bd5 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -5,7 +5,7 @@ charset-normalizer==3.3.2 docutils==0.20.1 idna==3.7 imagesize==1.4.1 -Jinja2==3.1.3 +Jinja2==3.1.4 MarkupSafe==2.1.3 packaging==23.2 Pygments==2.17.2 diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c index 16600be821c9fc4fdd1488504ae29a7cd004c1ca..1b35bf22014f9f038c04bd46924e0101c347385f 100644 --- a/drivers/adc/adc-uclass.c +++ b/drivers/adc/adc-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_ADC +#include #include #include #include diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c index ecc564cd219a6c0fadf7fd1daa8382d7d7bfdf7b..2bda733af90d7334732450e9925e39bec47a63aa 100644 --- a/drivers/adc/exynos-adc.c +++ b/drivers/adc/exynos-adc.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Samsung Electronics * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c index f593fb6447b3f28b9a2af9d81bff172000002505..41d04e0426cd943fd51753c11b4210e4d3768f56 100644 --- a/drivers/adc/imx93-adc.c +++ b/drivers/adc/imx93-adc.c @@ -6,6 +6,7 @@ * Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c */ +#include #include #include #include diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index 60e348968fb54e5e3172738ae1292182621a948a..c15c7fea47fedc114a4f5919921d6e57446affd5 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -7,6 +7,7 @@ * Amlogic Meson Successive Approximation Register (SAR) A/D Converter */ +#include #include #include #include diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index f6832ab30731463546917204863b791c54136a92..10ded1b088f380265c5b8100f7ed6ff90b60f738 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -5,6 +5,7 @@ * Rockchip SARADC driver for U-Boot */ +#include #include #include #include diff --git a/drivers/adc/sandbox.c b/drivers/adc/sandbox.c index 24d4af63bd9be535d50d38a4afc7427b9f451c16..43cad34ffebf8d67d6e56f71a9bb8040e274ab0e 100644 --- a/drivers/adc/sandbox.c +++ b/drivers/adc/sandbox.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Samsung Electronics * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c index af340b8b273b0c13fea29b8817dc896576111a7a..6c176961f17ae6007f67f26e6762d8dec92afee4 100644 --- a/drivers/adc/stm32-adc-core.c +++ b/drivers/adc/stm32-adc-core.c @@ -6,6 +6,7 @@ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c. */ +#include #include #include #include diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index d50f00f1233e07cfdf8f9e2b26137b3bb7b4b408..1fba707c6f7dac054a0ae843d1990e97d8acbc0d 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -6,6 +6,7 @@ * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c. */ +#include #include #include #include diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index f2102aaa6353da03719bc8c4fb7c9d921d2095d1..5356b9d83d34be1d7b0d35664b7a369e8e120cca 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -3,6 +3,7 @@ * Copyright (C) 2017, Bin Meng */ +#include #include #include #include diff --git a/drivers/ata/ahci-uclass.c b/drivers/ata/ahci-uclass.c index 7affb3f1ec7954cf36a86b45c26b378d6d8d5c79..d398b50b9a1e781629e7e75affedcbee5cd2d523 100644 --- a/drivers/ata/ahci-uclass.c +++ b/drivers/ata/ahci-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_AHCI +#include #include #include diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index ac869296d525125343e1bd245ee701f4af3f836a..04ddc3394648e38229d97a3dd05f2aafe01019a6 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -8,10 +8,10 @@ * * This driver provides a SCSI interface to SATA. */ +#include #include #include #include -#include #include #include diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c index f6e2d6bee45be35845a87256ab58356e0948bc7c..f05150d61ddf4ff5d4c70c53995aeb0caa072cb1 100644 --- a/drivers/ata/ahci_mvebu.c +++ b/drivers/ata/ahci_mvebu.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 6cf5cee055e7c20668a8310ebaeac9ac0183b2a4..9064774e6614d7915b6ab4906ac29b823bad664f 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index b480cde4465b7b7d661e2c4a8b9f33d4c48c218b..15fd3e365b2bf969070114ec3854d7b4415a834c 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -8,6 +8,7 @@ * Author: Mugunthan V N */ +#include #include #include #include diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index a29d641343edf280165923a500174a6b38424df1..b4d4e39c9b3bf00d1cc03fe7f8b0e0ce91d7d7e8 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -4,6 +4,7 @@ * Terry Lv */ +#include #include #include #include diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index 4990148388b62a2a97a30df0f910ac18186ca2ac..969bc191f8e8dd992a9c126e38bdf8ba073ed2ff 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -5,6 +5,7 @@ * Author: Dave Liu */ +#include #include #include #include diff --git a/drivers/ata/libata.c b/drivers/ata/libata.c index ef659cb1728a0a985227335a53ccbe23836dedd9..47e2c5c1cc402750e0854fd80dd2077a4804a62b 100644 --- a/drivers/ata/libata.c +++ b/drivers/ata/libata.c @@ -5,9 +5,9 @@ * port from the libata of linux kernel */ +#include #include #include -#include u64 ata_id_n_sectors(u16 *id) { diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 53aabee0a5e6a992691645c86e8d827317806c46..2c5227df306bcad86286a20d3062221d397325ae 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -8,6 +8,7 @@ * Author: Frank Wunderlich */ +#include #include #include #include diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index 84437d3d346b4f261f000f3f578a382c6e477699..784d9bbeacb47985d9727f47e4d84726715f9487 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -9,6 +9,7 @@ * Dave Liu */ +#include #include #include #include diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c index a5ca6f6fd5bb7a55d3d2956973daab9322fbfbae..f638493ce04ff8e56e80f506cbc6e9b08c55715f 100644 --- a/drivers/ata/sata_bootdev.c +++ b/drivers/ata/sata_bootdev.c @@ -5,6 +5,7 @@ * Copyright 2023 Tony Dinh */ +#include #include #include #include diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index a81b3165992a922ffbe749982c7e2a459f863486..7769d4f99efdffc364567a48996a7ee3257e68ff 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 - 2016 Xilinx, Inc. * Michal Simek */ +#include #include #include #include diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index ac78760a33ebabc65e1d97c2e1653c70d3cbd1f6..94d7369351a32ae398c2d62ac06bc03f9f28498d 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -31,6 +31,7 @@ * No port multiplier support */ +#include #include #include #include @@ -45,7 +46,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 5b80f6249d767e3e22bb1aec94f399ca57a0c253..43a91a79120a399f06ee87e698b497c1cb664c14 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c @@ -5,6 +5,7 @@ * Author: Tang Yuantian */ +#include #include #include #include diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c index bea0b040738c3d87181af02409e5c9d808035f5c..e6f3ef0720055236bac144b8e7227581c21a50b2 100644 --- a/drivers/axi/axi-emul-uclass.c +++ b/drivers/axi/axi-emul-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_AXI_EMUL +#include #include #include #include diff --git a/drivers/axi/axi-uclass.c b/drivers/axi/axi-uclass.c index fa2475cbaf4e34bec018eebc59631fb97b51a87d..41551ae85c9cdad48442cf2bdae7d167d854a899 100644 --- a/drivers/axi/axi-uclass.c +++ b/drivers/axi/axi-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_AXI +#include #include #include diff --git a/drivers/axi/axi_sandbox.c b/drivers/axi/axi_sandbox.c index 6f698a405f92734eab575f8d0894d824bcc42910..b91c91f6b3b6368d2645d59cc400c35748470c37 100644 --- a/drivers/axi/axi_sandbox.c +++ b/drivers/axi/axi_sandbox.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/axi/ihs_axi.c b/drivers/axi/ihs_axi.c index a37dd1e1786769c5962641b864fd9d6cc27a43b1..a7e9761fbfc2bcee2b31c2c3fe725696ec221033 100644 --- a/drivers/axi/ihs_axi.c +++ b/drivers/axi/ihs_axi.c @@ -7,6 +7,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/axi/sandbox_store.c b/drivers/axi/sandbox_store.c index b9413c758f7b62714a8ea0e0dbb249e13770302d..ef349a50b7981736912b38b9966e0138bd6b584b 100644 --- a/drivers/axi/sandbox_store.c +++ b/drivers/axi/sandbox_store.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index d544ffb5ffb6483c16fb33681350477f81b85cf1..7ebead6bfad6155a82eb9afb067f2555b5e7db30 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -45,6 +45,7 @@ * Jason ported this file to u-boot to run the ATI video card * BIOS in u-boot. ****************************************************************************/ +#include #include #include #include diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 690fb5a4d7b304f85e7410ad0428e70352dd3ddb..02c4286a854c11adf16040c7c90e06dda0efe857 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -48,6 +48,7 @@ ****************************************************************************/ #define __io +#include #include #include "biosemui.h" diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7f883daf8f0665e90f05297e1c415a1e6f5eec7e..9596a1fdd3e0081790fe7cabce1024f364f39c91 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -42,6 +42,7 @@ ****************************************************************************/ #define __io +#include #include #include "biosemui.h" diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index ba4328474ce2d8f30e8a53fd051561323a441969..82befbae66f7b54b4fa23e86bf8f57635d61501e 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -46,6 +46,7 @@ ****************************************************************************/ #include +#include #include "biosemui.h" BE_sysEnv _BE_env = {{0}}; diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index b426dc3bc45e128aff39ab8a3606c8b114858424..95f3cc09aad58918403d42bdc0a9d670ae38c13b 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -38,6 +38,7 @@ ****************************************************************************/ #include +#include #include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index 7e188d58a52c5f819604bf23f44f340cda3fa01a..e2028eaf08339c712940dfad8cc36de6cad1e069 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -36,6 +36,7 @@ * instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ +#include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 57422ec3d473aae195de9d44700db1456179a017..8c1a146165c98b103c011ef2d877858e140b1511 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -72,6 +72,7 @@ * ****************************************************************************/ +#include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 32fecb3479131e7e67027c51b432dedb58683974..6cd1ac3982527a4cb8355a8214cd503a4d92129f 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -41,6 +41,7 @@ * ****************************************************************************/ +#include #include #include #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index b3cccb17f202203eb802b831fadb97b211acad5e..5f6c795fb7ffc8f45334eac7dca5cca2a916ae10 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -97,6 +97,7 @@ * ****************************************************************************/ +#include #define PRIM_OPS_NO_REDEFINE_ASM #include "x86emu/x86emui.h" diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 483ecd52efe3dc34f4d7e23d87b98881bc39c0f9..f96652415cd371b05fbd589bab1447083a5fc74c 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -39,6 +39,7 @@ * ****************************************************************************/ +#include #include #include "x86emu/x86emui.h" diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 512c952f4d7af7becdda51a7dd4b86e1cc46abc5..77066da352a37b1dd831eedb4c0fe32a5ef6dc54 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_BLK +#include #include #include #include diff --git a/drivers/block/blk_legacy.c b/drivers/block/blk_legacy.c index f36932183d1f89ee253829f93c91ce0844b5ddea..5bf1d04715243d1e87674d5b8479933fdee1c5b3 100644 --- a/drivers/block/blk_legacy.c +++ b/drivers/block/blk_legacy.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c index 0e69160249c7f12e7c8484f3c4dec620836c2df4..26bcbea4353307bf81c61b8a25bd45b8192846b8 100644 --- a/drivers/block/blkcache.c +++ b/drivers/block/blkcache.c @@ -4,6 +4,7 @@ * Author: Eric Nelson * */ +#include #include #include #include diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 34eed1380dca8aa9640174fd53bd314e8a5ac4b8..21201409ed4b22c85c9f788875399a6d10830552 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -4,6 +4,7 @@ * Author: Tobias Waldekranz */ +#include #include #include #include diff --git a/drivers/block/efi-media-uclass.c b/drivers/block/efi-media-uclass.c index dc5e4f59b7f3c98acca4b88018e367105b4eb8cd..e012f6f2f4c4464c22a91633e26cd8da64efe1db 100644 --- a/drivers/block/efi-media-uclass.c +++ b/drivers/block/efi-media-uclass.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include UCLASS_DRIVER(efi_media) = { diff --git a/drivers/block/efi_blk.c b/drivers/block/efi_blk.c index 9766cd6f832776ac2c1525d786cef7d1ee9e9619..917a19f6025460be78a5a8c017039f9157674057 100644 --- a/drivers/block/efi_blk.c +++ b/drivers/block/efi_blk.c @@ -8,6 +8,7 @@ * Copyright 2021 Google LLC */ +#include #include #include #include diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index cf42bd1e07acd3b9d723993b2c018b48c46fd849..b3647e3ce3359537514d9338709e9bb0e61cc1fd 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_HOST +#include #include #include #include diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c index b3ff3cd1fab921b2ed54cfb0ebcd5095ed41dda9..52313435a0cb84b3b2b3b699506d519db35995be 100644 --- a/drivers/block/host_dev.c +++ b/drivers/block/host_dev.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_HOST +#include #include #include #include diff --git a/drivers/block/ide.c b/drivers/block/ide.c index b16623d7a3ab4f0b6b879e23a2f2a36b56bb4f46..c698f9cbd558ddb82f8f51d8e9cb84b492a3d90e 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_IDE +#include #include #include #include diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index ec34f1ad8c2e9471723dd6485563b514c3bf546b..be4e02cb601a67d871070dbf2e42daacd5c16761 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Henrik Nordstrom */ +#include #include #include #include diff --git a/drivers/block/sb_efi_media.c b/drivers/block/sb_efi_media.c index 3255db0649611c45f516975e43e76fee202e9d78..52af155a600109c572ef4936dccc59e65337d7d1 100644 --- a/drivers/block/sb_efi_media.c +++ b/drivers/block/sb_efi_media.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include static const struct udevice_id sandbox_efi_media_ids[] = { diff --git a/drivers/bootcount/bootcount-uclass.c b/drivers/bootcount/bootcount-uclass.c index 0178c1818e59edbe63412beb2dc3287cec8a65c2..5a369c82f1c5e22d48aa7e498e0d5af38bf12a47 100644 --- a/drivers/bootcount/bootcount-uclass.c +++ b/drivers/bootcount/bootcount-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_BOOTCOUNT +#include #include #include #include diff --git a/drivers/bootcount/bootcount_at91.c b/drivers/bootcount/bootcount_at91.c index 1a06db1fb7406792d6519695a2b404326070246f..c4ab5ceafabdf03828ecd53310a13cfd7a5376a7 100644 --- a/drivers/bootcount/bootcount_at91.c +++ b/drivers/bootcount/bootcount_at91.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c index 960cd71b9d562cccc35a8c82ada5455a1246862c..b75c9002b2c0a7ffb532570a9af13aa637ffcf22 100644 --- a/drivers/bootcount/bootcount_env.c +++ b/drivers/bootcount/bootcount_env.c @@ -4,6 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ +#include #include void bootcount_store(ulong a) diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a113f4f4aadf48f19636093a6c7338..8cc30cf40eff4a6c2310007c6175b662d40ac39c 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -4,6 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ +#include #include #include #include diff --git a/drivers/bootcount/bootcount_syscon.c b/drivers/bootcount/bootcount_syscon.c index 5dbc13cd5452e9a9a113a737f857b00223c33e2f..f80d87071d98b0dbf6d612691395954ad13335b3 100644 --- a/drivers/bootcount/bootcount_syscon.c +++ b/drivers/bootcount/bootcount_syscon.c @@ -3,6 +3,7 @@ * Copyright (c) Vaisala Oyj. All rights reserved. */ +#include #include #include #include diff --git a/drivers/bootcount/i2c-eeprom.c b/drivers/bootcount/i2c-eeprom.c index 12c430465c981ae1e8764a16cfdb36c28275faa8..709be094b118084e7a340b215516bf23be3e3225 100644 --- a/drivers/bootcount/i2c-eeprom.c +++ b/drivers/bootcount/i2c-eeprom.c @@ -4,6 +4,7 @@ * (C) Copyright 2019 GE */ +#include #include #include #include diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c index 8c529f5592b43e19a41ed48234cf92f2b797cb68..df046f1b0ab08a719102921b6bb4c66a956facc3 100644 --- a/drivers/bootcount/pmic_pfuze100.c +++ b/drivers/bootcount/pmic_pfuze100.c @@ -8,6 +8,7 @@ * This works only, if the PMIC is not connected to a battery. */ +#include #include #include #include diff --git a/drivers/bootcount/rtc.c b/drivers/bootcount/rtc.c index b131946aa9d1e00777924d9045e973827b7e82d6..483caaa80df400d11c4796d7ac45d55c96801bb1 100644 --- a/drivers/bootcount/rtc.c +++ b/drivers/bootcount/rtc.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/bootcount/spi-flash.c b/drivers/bootcount/spi-flash.c index 155d0323ee78477d2f52ff9785b1ff90d05c523d..03050e66613470cedd1d2623c3c75d5e662037c0 100644 --- a/drivers/bootcount/spi-flash.c +++ b/drivers/bootcount/spi-flash.c @@ -4,6 +4,7 @@ * (C) Copyright 2019 GE */ +#include #include #include #include diff --git a/drivers/bus/ti-pwmss.c b/drivers/bus/ti-pwmss.c index d1f6f3bab00f9beef5f79746e8d2ac33aedab6de..265b4cf83b5996c95de41745d2d82721ae6a7b27 100644 --- a/drivers/bus/ti-pwmss.c +++ b/drivers/bus/ti-pwmss.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include static const struct udevice_id ti_pwmss_ids[] = { diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 5f9f0a0d0b7b675b5679ca1bbd74e2bb984b774b..778c0654f6a3bae3f324a1f8c20115ae32ce9748 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/button/button-adc.c b/drivers/button/button-adc.c index da7ddf2a857778df902a90b9d94ba3addd372c1c..9c24c960e6ffc8da6fdf9897150dcb9b69ac87f9 100644 --- a/drivers/button/button-adc.c +++ b/drivers/button/button-adc.c @@ -5,6 +5,7 @@ * Author: Marek Szyprowski */ +#include #include #include #include diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index 43b82d98aeb7f9c26aa113b38b2351dab1a55766..7b5b3affe2ddab2aea0601053ec4e7aab19d8c1b 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Philippe Reynes */ +#include #include #include #include diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c index cda243389df3b4f728a14c3295a75fd67d6a9624..032191d61abc58a21ca0dfaac0a16262071d124f 100644 --- a/drivers/button/button-uclass.c +++ b/drivers/button/button-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_BUTTON +#include #include #include #include diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 26c2d80a1c568dece31fa9d8e6ac5520469a92c9..4f35865744458cb0b243e204d2ad71de71be643e 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -22,11 +22,11 @@ config L2X0_CACHE ARMv7(32-bit) devices. The driver configures the cache settings found in the device tree. -config V5L2_CACHE - bool "Andes V5L2 cache driver" +config ANDES_L2_CACHE + bool "Andes L2 cache driver" select CACHE help - Support Andes V5L2 cache controller in AE350 platform. + Support Andes L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the device tree and enable L2 cache. diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 78e673d09e5b52f698da1efbe335aebbf1b279b5..e1b71e0ed514e693341b547fbbc387904ae279fc 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -3,6 +3,6 @@ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o -obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o +obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-andes-l2.c similarity index 84% rename from drivers/cache/cache-v5l2.c rename to drivers/cache/cache-andes-l2.c index f0b8ecc88079e23b0ad2de4fa84f20aae0e93830..45d29f2fbd96f33065e96908d18017a5e4dddbf2 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-andes-l2.c @@ -4,6 +4,7 @@ * Rick Chen, Andes Technology Corporation */ +#include #include #include #include @@ -72,7 +73,7 @@ static u32 status_bit_offset = 0x4; DECLARE_GLOBAL_DATA_PTR; -struct v5l2_plat { +struct andes_l2_plat { struct l2cache *regs; u32 iprefetch; u32 dprefetch; @@ -80,9 +81,9 @@ struct v5l2_plat { u32 dram_ctl[2]; }; -static int v5l2_enable(struct udevice *dev) +static int andes_l2_enable(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); volatile struct l2cache *regs = plat->regs; if (regs) @@ -91,9 +92,9 @@ static int v5l2_enable(struct udevice *dev) return 0; } -static int v5l2_disable(struct udevice *dev) +static int andes_l2_disable(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); volatile struct l2cache *regs = plat->regs; u8 hart = gd->arch.boot_hart; void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); @@ -113,9 +114,9 @@ static int v5l2_disable(struct udevice *dev) return 0; } -static int v5l2_of_to_plat(struct udevice *dev) +static int andes_l2_of_to_plat(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); struct l2cache *regs; regs = dev_read_addr_ptr(dev); @@ -137,9 +138,9 @@ static int v5l2_of_to_plat(struct udevice *dev) return 0; } -static int v5l2_probe(struct udevice *dev) +static int andes_l2_probe(struct udevice *dev) { - struct v5l2_plat *plat = dev_get_plat(dev); + struct andes_l2_plat *plat = dev_get_plat(dev); struct l2cache *regs = plat->regs; u32 cfg_val, ctl_val; @@ -182,23 +183,23 @@ static int v5l2_probe(struct udevice *dev) return 0; } -static const struct udevice_id v5l2_cache_ids[] = { +static const struct udevice_id andes_l2_cache_ids[] = { { .compatible = "cache" }, {} }; -static const struct cache_ops v5l2_cache_ops = { - .enable = v5l2_enable, - .disable = v5l2_disable, +static const struct cache_ops andes_l2_cache_ops = { + .enable = andes_l2_enable, + .disable = andes_l2_disable, }; -U_BOOT_DRIVER(v5l2_cache) = { - .name = "v5l2_cache", +U_BOOT_DRIVER(andes_l2_cache) = { + .name = "andes_l2_cache", .id = UCLASS_CACHE, - .of_match = v5l2_cache_ids, - .of_to_plat = v5l2_of_to_plat, - .probe = v5l2_probe, - .plat_auto = sizeof(struct v5l2_plat), - .ops = &v5l2_cache_ops, + .of_match = andes_l2_cache_ids, + .of_to_plat = andes_l2_of_to_plat, + .probe = andes_l2_probe, + .plat_auto = sizeof(struct andes_l2_plat), + .ops = &andes_l2_cache_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index c7bdd9d064a59c7a9857b657864fe6ca963ea918..560f4c94f1ef89186cba3e093f540ccd36562d4e 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2019 Intel Corporation */ +#include #include #include diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c index cc00b80f60b86562dc4ccd6320c69d387f4c6130..521df40466f99004bb25c88e88ae43fbfa48d344 100644 --- a/drivers/cache/cache-sifive-ccache.c +++ b/drivers/cache/cache-sifive-ccache.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 SiFive */ +#include #include #include #include diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c index 300e7bc86e1a1421f0d2a259f12582067afa96a3..0c13dbdb75c41d15c5504ed83a5e6512e00ecde0 100644 --- a/drivers/cache/cache-uclass.c +++ b/drivers/cache/cache-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CACHE +#include #include #include diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 2e20b83ab8039540550f1ab45f101cad8140a4e5..955dfc8a0f844be525c8171455d4780734c445de 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include #include diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 9acbc47fe8edf780e04246197beeeb6179c9b0f9..bda6873be331d3c1f975fa7a8801d65dd4123812 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -246,7 +246,6 @@ config CLK_ZYNQMP This clock driver adds support for clock realted settings for ZynqMP platform. -source "drivers/clk/adi/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 847b9b29110005658a66c3961ad2522a9fc66d23..638ad04baeb05f40cb8688acc83f59640fa144cb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o -obj-y += adi/ obj-y += analogbits/ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig deleted file mode 100644 index 5745bedf88cda4bd7eb4e4b19cd0f9831f9b6ed6..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -config COMMON_CLK_ADI_SHARED - bool "Enable shared ADI clock framework code" - help - Required for shared code between SoC clock drivers. Automatically - selected by an appropriate SoC-specific clock driver version. - -config COMMON_CLK_ADI_SC598 - bool "Clock driver for ADI SC598 SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select SPL_DM if SPL - select SPL_CLK if SPL - select SPL_CLK_CCF if SPL - select SPL_OF_CONTROL if SPL - select COMMON_CLK_ADI_SHARED - depends on SC59X_64 - help - This driver supports the system clocks on Analog Devices SC598-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC594 - bool "Clock driver for ADI SC594 SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select SPL_DM if SPL - select SPL_CLK if SPL - select SPL_CLK_CCF if SPL - select SPL_OF_CONTROL if SPL - select COMMON_CLK_ADI_SHARED - depends on SC59X - help - This driver supports the system clocks on Analog Devices SC594-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC58X - bool "Clock driver for ADI SC58X SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select COMMON_CLK_ADI_SHARED - depends on SC58X - help - This driver supports the system clocks on Analog Devices SC58x-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. - -config COMMON_CLK_ADI_SC57X - bool "Clock driver for ADI SC57X SoCs" - select DM - select CLK - select CLK_CCF - select OF_CONTROL - select CMD_CLK - select COMMON_CLK_ADI_SHARED - depends on SC57X - help - This driver supports the system clocks on Analog Devices SC57x-series - SoCs. It includes CGU and CDU clocks and supports gating unused clocks. - Modifying PLL configuration is not supported; that must be done prior - to booting the kernel. Clock dividers after the PLLs may be configured. diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile deleted file mode 100644 index f3f1fd92e5fda3a4eb6322913d6e2bb35b0b74a4..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# (C) Copyright 2022 - Analog Devices, Inc. -# -# Written and/or maintained by Timesys Corporation -# -# Contact: Nathan Barrett-Morrison -# Contact: Greg Malysa -# - -obj-$(CONFIG_COMMON_CLK_ADI_SHARED) += clk-shared.o clk-adi-pll.o - -obj-$(CONFIG_COMMON_CLK_ADI_SC594) += clk-adi-sc594.o -obj-$(CONFIG_COMMON_CLK_ADI_SC598) += clk-adi-sc598.o -obj-$(CONFIG_COMMON_CLK_ADI_SC58X) += clk-adi-sc58x.o -obj-$(CONFIG_COMMON_CLK_ADI_SC57X) += clk-adi-sc57x.o diff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c deleted file mode 100644 index 372baa9c11b5d3802ea2ca4670da554ffd19d85b..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-adi-pll.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -#define ADI_CLK_PLL_GENERIC "adi_clk_pll_generic" - -struct clk_sc5xx_cgu_pll { - struct clk clk; - void __iomem *base; - u32 mask; - u32 max; - u32 m_offset; - u8 shift; - bool half_m; -}; - -#define to_clk_sc5xx_cgu_pll(_clk) container_of(_clk, struct clk_sc5xx_cgu_pll, clk) - -static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk) -{ - struct clk_sc5xx_cgu_pll *pll = to_clk_sc5xx_cgu_pll(dev_get_clk_ptr(clk->dev)); - unsigned long parent_rate = clk_get_parent_rate(clk); - - u32 reg = readl(pll->base); - u32 m = ((reg & pll->mask) >> pll->shift) + pll->m_offset; - - if (m == 0) - m = pll->max; - - if (pll->half_m) - return parent_rate * m * 2; - return parent_rate * m; -} - -static const struct clk_ops clk_sc5xx_cgu_pll_ops = { - .get_rate = sc5xx_cgu_pll_get_rate, -}; - -struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, - void __iomem *base, u8 shift, u8 width, u32 m_offset, - bool half_m) -{ - struct clk_sc5xx_cgu_pll *pll; - struct clk *clk; - int ret; - char *drv_name = ADI_CLK_PLL_GENERIC; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - - pll->base = base; - pll->shift = shift; - pll->mask = GENMASK(width - 1, 0) << shift; - pll->max = pll->mask + 1; - pll->m_offset = m_offset; - pll->half_m = half_m; - - clk = &pll->clk; - - ret = clk_register(clk, drv_name, name, parent_name); - if (ret) { - pr_err("Failed to register %s in %s: %d\n", name, __func__, ret); - kfree(pll); - return ERR_PTR(ret); - } - - return clk; -} - -U_BOOT_DRIVER(clk_adi_pll_generic) = { - .name = ADI_CLK_PLL_GENERIC, - .id = UCLASS_CLK, - .ops = &clk_sc5xx_cgu_pll_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc57x.c b/drivers/clk/adi/clk-adi-sc57x.c deleted file mode 100644 index b17563f0444fe1962afbe4567172b0aa6e127baf..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-adi-sc57x.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "oclk_0_half"}; -static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; -static const char * const gige_sels[] = {"sclk1_0", "sclk1_1", "cclk0_1", "oclk_0"}; -static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", - "dclk_1"}; - -static int sc57x_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC57X_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC57X_CLK_DUMMY] = &dummy; - clks[ADSP_SC57X_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC57X_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC57X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC57X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC57X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output == PLL output - clks[ADSP_SC57X_CLK_CGU0_PLLCLK] = sc5xx_cgu_pll("cgu0_pllclk", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC57X_CLK_CGU1_PLLCLK] = sc5xx_cgu_pll("cgu1_pllclk", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Dividers from pll output - clks[ADSP_SC57X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC57X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC57X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC57X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - - clks[ADSP_SC57X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC57X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC57X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", - "sysclk_1", cgu1 + CGU_DIV, 5, - 3, 0); - clks[ADSP_SC57X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", - "sysclk_1", cgu1 + CGU_DIV, 13, - 3, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC57X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC57X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC57X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC57X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC57X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC57X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC57X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC57X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC57X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC57X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", - "oclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC57X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, - "cclk1_1_half", - "cclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC57X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC57X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC57X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC57X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC57X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC57X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC57X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC57X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); - - // CDU output enable gates - clks[ADSP_SC57X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - CLK_IS_CRITICAL); - clks[ADSP_SC57X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC57X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC57X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC57X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc57x_clk_ids[] = { - { .compatible = "adi,sc57x-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc57x_clk) = { - .name = "clk_adi_sc57x", - .id = UCLASS_CLK, - .of_match = adi_sc57x_clk_ids, - .ops = &adi_clk_ops, - .probe = sc57x_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc58x.c b/drivers/clk/adi/clk-adi-sc58x.c deleted file mode 100644 index 05a0feddec7aaf62d3039fc49fcf9502ec1acf96..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-adi-sc58x.c +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const sharc0_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "sysclk_0", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "sysclk_0", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dummy"}; -static const char * const spdif_sels[] = {"oclk_0", "oclk_1", "dclk_1", "dclk_0"}; -static const char * const reserved_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk1_1", "cclk0_1", "oclk_0"}; -static const char * const lp_sels[] = {"sclk0_0", "sclk0_1", "cclk1_1", "dclk_1"}; -static const char * const sdio_sels[] = {"oclk_0_half", "cclk1_1_half", "cclk1_1", - "dclk_1"}; - -static int sc58x_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC58X_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC58X_CLK_DUMMY] = &dummy; - clks[ADSP_SC58X_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC58X_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC58X_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC58X_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC58X_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC58X_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC58X_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Final PLL output - clks[ADSP_SC58X_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 1); - clks[ADSP_SC58X_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 1); - - // Dividers from pll output - clks[ADSP_SC58X_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC58X_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC58X_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC58X_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - - clks[ADSP_SC58X_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC58X_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC58X_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC58X_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC58X_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC58X_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC58X_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC58X_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_s1seldiv", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC58X_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC58X_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC58X_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC58X_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_s1seldiv", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC58X_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC58X_CLK_OCLK0_HALF] = clk_register_fixed_factor(NULL, "oclk_0_half", - "oclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC58X_CLK_CCLK1_1_HALF] = clk_register_fixed_factor(NULL, - "cclk1_1_half", - "cclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC58X_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC58X_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC58X_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC58X_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC58X_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC58X_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC58X_CLK_RESERVED_SEL] = cdu_mux("reserved_sel", cdu + CDU_CFG6, - reserved_sels); - clks[ADSP_SC58X_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC58X_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC58X_CLK_SDIO_SEL] = cdu_mux("sdio_sel", cdu + CDU_CFG9, sdio_sels); - - // CDU output enable gates - clks[ADSP_SC58X_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - CLK_IS_CRITICAL); - clks[ADSP_SC58X_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC58X_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC58X_CLK_RESERVED] = cdu_gate("reserved", "reserved_sel", - cdu + CDU_CFG6, 0); - clks[ADSP_SC58X_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC58X_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC58X_CLK_SDIO] = cdu_gate("sdio", "sdio_sel", cdu + CDU_CFG9, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc58x_clk_ids[] = { - { .compatible = "adi,sc58x-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc58x_clk) = { - .name = "clk_adi_sc58x", - .id = UCLASS_CLK, - .of_match = adi_sc58x_clk_ids, - .ops = &adi_clk_ops, - .probe = sc58x_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc594.c b/drivers/clk/adi/clk-adi-sc594.c deleted file mode 100644 index c80bbf9728d2faa85313d5f01de56679bd9be957..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-adi-sc594.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; -static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; -static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const arm_sels[] = {"cclk1_0", "dummy", "dummy", "dummy"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"oclk_0", "oclk_1", "dummy", "dummy"}; -static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; -static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "cclk0_1", "dummy"}; -static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; -static const char * const lpddr_sels[] = {"oclk_0", "dclk_0", "sysclkin_1", "dummy"}; -static const char * const ospi_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", "dummy"}; -static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; - -static int sc594_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC594_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC594_CLK_DUMMY] = &dummy; - clks[ADSP_SC594_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC594_CLK_SYS_CLKIN1] = &clkin1; - clks[ADSP_SC594_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // CGU configuration and internal clocks - clks[ADSP_SC594_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC594_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC594_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - clks[ADSP_SC594_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, false); - - // Final PLL output - clks[ADSP_SC594_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 1); - clks[ADSP_SC594_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 1); - - // Dividers from pll output - clks[ADSP_SC594_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC594_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC594_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC594_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC594_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC594_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC594_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", - "cgu0_pllclk", - cgu0 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC594_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", - cgu0_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 17, 1, 0); - - clks[ADSP_SC594_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC594_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC594_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC594_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC594_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC594_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC594_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC594_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", - cgu1_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 17, 1, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC594_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC594_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC594_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC594_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC594_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC594_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC594_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC594_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC594_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv", - cgu1 + CGU_SCBF_DIS, 0); - - // CDU output muxes - clks[ADSP_SC594_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC594_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC594_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC594_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC594_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC594_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC594_CLK_RESERVED_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); - clks[ADSP_SC594_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC594_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC594_CLK_LPDDR_SEL] = cdu_mux("lpddr_sel", cdu + CDU_CFG9, lpddr_sels); - clks[ADSP_SC594_CLK_OSPI_SEL] = cdu_mux("ospi_sel", cdu + CDU_CFG10, - ospi_sels); - clks[ADSP_SC594_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, - trace_sels); - - // CDU output enable gates - clks[ADSP_SC594_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", - cdu + CDU_CFG0, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", - cdu + CDU_CFG1, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", - cdu + CDU_CFG3, CLK_IS_CRITICAL); - clks[ADSP_SC594_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC594_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC594_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); - clks[ADSP_SC594_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC594_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC594_CLK_LPDDR] = cdu_gate("lpddr", "lpddr_sel", cdu + CDU_CFG9, 0); - clks[ADSP_SC594_CLK_OSPI] = cdu_gate("ospi", "ospi_sel", cdu + CDU_CFG10, 0); - clks[ADSP_SC594_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc594_clk_ids[] = { - { .compatible = "adi,sc594-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc594_clk) = { - .name = "clk_adi_sc594", - .id = UCLASS_CLK, - .of_match = adi_sc594_clk_ids, - .ops = &adi_clk_ops, - .probe = sc594_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-adi-sc598.c b/drivers/clk/adi/clk-adi-sc598.c deleted file mode 100644 index d4a16ac9603bd42a9a8b628a37c4c7e70d18310f..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-adi-sc598.c +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk.h" - -static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"}; -static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"}; -static const char * const cgu1_s0sels[] = {"cgu1_s0seldiv", "cgu1_s0selexdiv"}; -static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"}; -static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"}; -static const char * const arm_sels[] = {"dummy", "dummy", "cclk2_0", "cclk2_1"}; -static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"}; -static const char * const can_sels[] = {"dummy", "oclk_1", "dummy", "dummy"}; -static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"}; -static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"}; -static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "dummy", "dummy"}; -static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"}; -static const char * const lp_ddr_sels[] = {"oclk_0", "dclk_0", "sysclk_1", "dummy"}; -static const char * const ospi_refclk_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", - "dummy"}; -static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"}; -static const char * const emmc_sels[] = {"oclk_0", "sclk0_1", "dclk_0_half", - "dclk_1_half"}; -static const char * const emmc_timer_sels[] = {"dummy", "sclk1_1_half", "dummy", - "dummy"}; -static const char * const ddr_sels[] = {"cdu_ddr", "3pll_ddiv"}; - -static int sc598_clock_probe(struct udevice *dev) -{ - void __iomem *cgu0; - void __iomem *cgu1; - void __iomem *cdu; - void __iomem *pll3; - int ret; - struct resource res; - - struct clk *clks[ADSP_SC598_CLK_END]; - struct clk dummy, clkin0, clkin1; - - ret = dev_read_resource_byname(dev, "cgu0", &res); - if (ret) - return ret; - cgu0 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cgu1", &res); - if (ret) - return ret; - cgu1 = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "cdu", &res); - if (ret) - return ret; - cdu = devm_ioremap(dev, res.start, resource_size(&res)); - - ret = dev_read_resource_byname(dev, "pll3", &res); - if (ret) - return ret; - pll3 = devm_ioremap(dev, res.start, resource_size(&res)); - - // We only access this one register for pll3 - pll3 = pll3 + PLL3_OFFSET; - - // Input clock configuration - clk_get_by_name(dev, "dummy", &dummy); - clk_get_by_name(dev, "sys_clkin0", &clkin0); - clk_get_by_name(dev, "sys_clkin1", &clkin1); - - clks[ADSP_SC598_CLK_DUMMY] = &dummy; - clks[ADSP_SC598_CLK_SYS_CLKIN0] = &clkin0; - clks[ADSP_SC598_CLK_SYS_CLKIN1] = &clkin1; - - clks[ADSP_SC598_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels, - 2, CLK_SET_RATE_PARENT, - cdu + CDU_CLKINSEL, 0, 1, 0); - - // 3rd pll reuses cgu1 clk in selection, feeds directly into 3pll df - // changing the cgu1 in sel mux will affect 3pll so reuse the same clocks - - // CGU configuration and internal clocks - clks[ADSP_SC598_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df", - "sys_clkin0", - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC598_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 0, 1, 0); - clks[ADSP_SC598_CLK_3PLL_PLL_IN] = clk_register_divider(NULL, "3pll_df", - "cgu1_in_sel", - CLK_SET_RATE_PARENT, - pll3, 3, 1, 0); - - // VCO output inside PLL - clks[ADSP_SC598_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df", - cgu0 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, true); - clks[ADSP_SC598_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df", - cgu1 + CGU_CTL, CGU_MSEL_SHIFT, - CGU_MSEL_WIDTH, 0, true); - clks[ADSP_SC598_CLK_3PLL_VCO_OUT] = sc5xx_cgu_pll("3pll_vco", "3pll_df", - pll3, PLL3_MSEL_SHIFT, - PLL3_MSEL_WIDTH, 1, true); - - // Final PLL output - clks[ADSP_SC598_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_3PLL_PLLCLK] = clk_register_fixed_factor(NULL, "3pll_pllclk", - "3pll_vco", - CLK_SET_RATE_PARENT, - 1, 2); - - // Dividers from pll output - clks[ADSP_SC598_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC598_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk", - cgu0 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC598_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC598_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk", - cgu0 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC598_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0", - cgu0 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC598_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0", - cgu0 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC598_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv", - "cgu0_pllclk", - cgu0 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC598_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel", - cgu0_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu0 + CGU_CTL, 17, 1, 0); - clks[ADSP_SC598_CLK_CGU0_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_0", - "cgu0_vco", - CLK_SET_RATE_PARENT, - 1, 3); - - clks[ADSP_SC598_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 0, 5, 0); - clks[ADSP_SC598_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk", - cgu1 + CGU_DIV, 8, 5, 0); - clks[ADSP_SC598_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 16, 5, 0); - clks[ADSP_SC598_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk", - cgu1 + CGU_DIV, 22, 7, 0); - clks[ADSP_SC598_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1", - cgu1 + CGU_DIV, 5, 3, 0); - clks[ADSP_SC598_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1", - cgu1 + CGU_DIV, 13, 3, 0); - clks[ADSP_SC598_CLK_CGU1_S0SELEXDIV] = cgu_divider("cgu1_s0selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 0, 8, 0); - clks[ADSP_SC598_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv", - "cgu1_pllclk", - cgu1 + CGU_DIVEX, 16, 8, 0); - clks[ADSP_SC598_CLK_CGU1_S0SEL] = clk_register_mux(NULL, "cgu1_sclk0sel", - cgu1_s0sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 16, 1, 0); - clks[ADSP_SC598_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel", - cgu1_s1sels, 2, - CLK_SET_RATE_PARENT, - cgu1 + CGU_CTL, 17, 1, 0); - clks[ADSP_SC598_CLK_CGU1_CCLK2] = clk_register_fixed_factor(NULL, "cclk2_1", - "cgu1_vco", - CLK_SET_RATE_PARENT, - 1, 3); - - clks[ADSP_SC598_CLK_3PLL_DDIV] = clk_register_divider(NULL, "3pll_ddiv", - "3pll_pllclk", - CLK_SET_RATE_PARENT, pll3, - 12, 5, 0); - - // Gates to enable CGU outputs - clks[ADSP_SC598_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv", - cgu0 + CGU_CCBF_DIS, 0); - clks[ADSP_SC598_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv", - cgu0 + CGU_SCBF_DIS, 3); - clks[ADSP_SC598_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv", - cgu0 + CGU_SCBF_DIS, 2); - clks[ADSP_SC598_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel", - cgu0 + CGU_SCBF_DIS, 1); - clks[ADSP_SC598_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv", - cgu0 + CGU_SCBF_DIS, 0); - - clks[ADSP_SC598_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv", - cgu1 + CGU_CCBF_DIS, 0); - clks[ADSP_SC598_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv", - cgu1 + CGU_SCBF_DIS, 3); - clks[ADSP_SC598_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv", - cgu1 + CGU_SCBF_DIS, 2); - clks[ADSP_SC598_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel", - cgu1 + CGU_SCBF_DIS, 1); - clks[ADSP_SC598_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_sclk0sel", - cgu1 + CGU_SCBF_DIS, 0); - - // Extra half rate clocks generated in the CDU - clks[ADSP_SC598_CLK_DCLK0_HALF] = clk_register_fixed_factor(NULL, "dclk_0_half", - "dclk_0", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_DCLK1_HALF] = clk_register_fixed_factor(NULL, "dclk_1_half", - "dclk_1", - CLK_SET_RATE_PARENT, - 1, 2); - clks[ADSP_SC598_CLK_CGU1_SCLK1_HALF] = clk_register_fixed_factor(NULL, - "sclk1_1_half", - "sclk1_1", - CLK_SET_RATE_PARENT, - 1, 2); - - // CDU output muxes - clks[ADSP_SC598_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0, - sharc0_sels); - clks[ADSP_SC598_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1, - sharc1_sels); - clks[ADSP_SC598_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels); - clks[ADSP_SC598_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3, - cdu_ddr_sels); - clks[ADSP_SC598_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels); - clks[ADSP_SC598_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels); - clks[ADSP_SC598_CLK_SPI_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels); - clks[ADSP_SC598_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels); - clks[ADSP_SC598_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels); - clks[ADSP_SC598_CLK_LP_DDR_SEL] = cdu_mux("lp_ddr_sel", cdu + CDU_CFG9, - lp_ddr_sels); - clks[ADSP_SC598_CLK_OSPI_REFCLK_SEL] = cdu_mux("ospi_refclk_sel", cdu + CDU_CFG10, - ospi_refclk_sels); - clks[ADSP_SC598_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12, - trace_sels); - clks[ADSP_SC598_CLK_EMMC_SEL] = cdu_mux("emmc_sel", cdu + CDU_CFG13, emmc_sels); - clks[ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL] = cdu_mux("emmc_timer_qmc_sel", - cdu + CDU_CFG14, - emmc_timer_sels); - - // CDU output enable gates - clks[ADSP_SC598_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel", cdu + CDU_CFG0, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel", cdu + CDU_CFG1, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2, - CLK_IS_CRITICAL); - clks[ADSP_SC598_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel", cdu + CDU_CFG3, - 0); - clks[ADSP_SC598_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0); - clks[ADSP_SC598_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0); - clks[ADSP_SC598_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0); - clks[ADSP_SC598_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0); - clks[ADSP_SC598_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0); - clks[ADSP_SC598_CLK_LP_DDR] = cdu_gate("lp_ddr", "lp_ddr_sel", cdu + CDU_CFG9, 0); - clks[ADSP_SC598_CLK_OSPI_REFCLK] = cdu_gate("ospi_refclk", "ospi_refclk_sel", - cdu + CDU_CFG10, 0); - clks[ADSP_SC598_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0); - clks[ADSP_SC598_CLK_EMMC] = cdu_gate("emmc", "emmc_sel", cdu + CDU_CFG13, 0); - clks[ADSP_SC598_CLK_EMMC_TIMER_QMC] = cdu_gate("emmc_timer_qmc", - "emmc_timer_qmc_sel", - cdu + CDU_CFG14, 0); - - // Dedicated DDR output mux - clks[ADSP_SC598_CLK_DDR] = clk_register_mux(NULL, "ddr", ddr_sels, 2, - CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - pll3, 11, 1, 0); - - ret = cdu_check_clocks(clks, ARRAY_SIZE(clks)); - if (ret) - pr_err("CDU error detected\n"); - - return ret; -} - -static const struct udevice_id adi_sc598_clk_ids[] = { - { .compatible = "adi,sc598-clocks" }, - { }, -}; - -U_BOOT_DRIVER(adi_sc598_clk) = { - .name = "clk_adi_sc598", - .id = UCLASS_CLK, - .of_match = adi_sc598_clk_ids, - .ops = &adi_clk_ops, - .probe = sc598_clock_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c deleted file mode 100644 index dcadcafa9d236882af8c7b397eeeeb44461a23cb..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk-shared.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - */ - -#include "clk.h" - -static ulong adi_get_rate(struct clk *clk) -{ - struct clk *c; - int ret; - - ret = clk_get_by_id(clk->id, &c); - if (ret) - return ret; - - return clk_get_rate(c); -} - -static ulong adi_set_rate(struct clk *clk, ulong rate) -{ - //Not yet implemented - return 0; -} - -static int adi_enable(struct clk *clk) -{ - //Not yet implemented - return 0; -} - -static int adi_disable(struct clk *clk) -{ - //Not yet implemented - return 0; -} - -const struct clk_ops adi_clk_ops = { - .set_rate = adi_set_rate, - .get_rate = adi_get_rate, - .enable = adi_enable, - .disable = adi_disable, -}; - diff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h deleted file mode 100644 index f230205c31126ab85b64d2980c64f3b41c6befb6..0000000000000000000000000000000000000000 --- a/drivers/clk/adi/clk.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Author: Greg Malysa - * - * Ported from Linux: Nathan Barrett-Morrison - */ - -#ifndef CLK_ADI_CLK_H -#define CLK_ADI_CLK_H - -#include -#include -#include - -#define CGU_CTL 0x00 -#define CGU_PLLCTL 0x04 -#define CGU_STAT 0x08 -#define CGU_DIV 0x0C -#define CGU_CLKOUTSEL 0x10 -#define CGU_OSCWDCTL 0x14 -#define CGU_TSCTL 0x18 -#define CGU_TSVALUE0 0x1C -#define CGU_TSVALUE1 0x20 -#define CGU_TSCOUNT0 0x24 -#define CGU_TSCOUNT1 0x28 -#define CGU_CCBF_DIS 0x2C -#define CGU_CCBF_STAT 0x30 -#define CGU_SCBF_DIS 0x38 -#define CGU_SCBF_STAT 0x3C -#define CGU_DIVEX 0x40 -#define CGU_REVID 0x48 - -#define CDU_CFG0 0x00 -#define CDU_CFG1 0x04 -#define CDU_CFG2 0x08 -#define CDU_CFG3 0x0C -#define CDU_CFG4 0x10 -#define CDU_CFG5 0x14 -#define CDU_CFG6 0x18 -#define CDU_CFG7 0x1C -#define CDU_CFG8 0x20 -#define CDU_CFG9 0x24 -#define CDU_CFG10 0x28 -#define CDU_CFG11 0x2C -#define CDU_CFG12 0x30 -#define CDU_CFG13 0x34 -#define CDU_CFG14 0x38 - -#define PLL3_OFFSET 0x2c - -#define CDU_CLKINSEL 0x44 - -#define CGU_MSEL_SHIFT 8 -#define CGU_MSEL_WIDTH 7 - -#define PLL3_MSEL_SHIFT 4 -#define PLL3_MSEL_WIDTH 7 - -#define CDU_MUX_SIZE 4 -#define CDU_MUX_SHIFT 1 -#define CDU_MUX_WIDTH 2 -#define CDU_EN_BIT 0 - -extern const struct clk_ops adi_clk_ops; - -struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name, - void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m); - -/** - * All CDU clock muxes are the same size - */ -static inline struct clk *cdu_mux(const char *name, void __iomem *reg, - const char * const *parents) -{ - return clk_register_mux(NULL, name, parents, CDU_MUX_SIZE, - CLK_SET_RATE_PARENT, reg, CDU_MUX_SHIFT, CDU_MUX_WIDTH, 0); -} - -static inline struct clk *cgu_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width, u8 extra_flags) -{ - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, - reg, shift, width, CLK_DIVIDER_MAX_AT_ZERO | extra_flags); -} - -static inline struct clk *cdu_gate(const char *name, const char *parent, - void __iomem *reg, u32 flags) -{ - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT | flags, - reg, CDU_EN_BIT, 0, NULL); -} - -static inline struct clk *cgu_gate(const char *name, const char *parent, - void __iomem *reg, u8 bit) -{ - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, bit, - CLK_GATE_SET_TO_DISABLE, NULL); -} - -static inline int cdu_check_clocks(struct clk *clks[], size_t count) -{ - size_t i; - - for (i = 0; i < count; ++i) { - if (clks[i]) { - if (IS_ERR(clks[i])) { - pr_err("Clock %zu failed to register: %ld\n", i, PTR_ERR(clks[i])); - return PTR_ERR(clks[i]); - } - clks[i]->id = i; - } else { - pr_err("ADI Clock framework: Null pointer detected on clock %zu\n", i); - } - } - - return 0; -} - -#endif diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index bdc7be0fb5d3f4c5a70cec763143f7546135b6f6..cca6d6741221f706d8825eb14be7d69a2bc4de7c 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include #include diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 72b923465df58c56b66cdac57aeafecbdc09d1eb..92f2abdaf93587142dcdf0d24dad0b16045cb866 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index 1840f73beeec6a8efe79ae78cfcdda66841a8d47..578597a16e81acdbb64913ea84587ac2add0bb75 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index b75f52d203b23b600b53ddbdf0fe5d2ef38c01a6..9bbe2cd0ca70751cd2682e7d844b17406536fd84 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -3,6 +3,7 @@ * Copyright (C) 2020-2022 Intel Corporation */ +#include #include #include #include diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 3e256101a947a772fc273a4567d6e7e89f5d3092..3fa19e05c47ef91c183e2034f620100138283030 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -3,6 +3,7 @@ * Copyright (C) 2020-2022 Intel Corporation */ +#include #include #include #include diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a330dcda4dcbeeb602f7210e262f88e64ab99623..dc446ce9fb7dc6dfba0cc48b3bfd14c76411fabd 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Google, Inc */ +#include #include #include #include diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 535010b7941484804573279f90226c2641dba034..a15909329bbdbb96b87b1389cd342fcdf04dd65a 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -3,6 +3,7 @@ * Copyright (C) ASPEED Technology Inc. */ +#include #include #include #include diff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c index c410cd2b5052377ec4e10aca85b1cdd39bf4cf41..87738b7b5bffba9b3a9201d2a6476d1d3a046514 100644 --- a/drivers/clk/at91/clk-generic.c +++ b/drivers/clk/at91/clk-generic.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-generated.c from Linux. */ +#include #include #include #include diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 09daae97676de7a682c88eb32f5292d586353ed8..025c7a7aa26da8c3a4984843a04bfe3d1626a84d 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index d28775d64d33ff8c939391bfab2701bbcec2e148..aec0bca7b3cb0fd7768f5f4e0fc4ea992535ca92 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c index 08d7e7dddc9e5f769bc1200fd41214bc6daec130..52cbc520cef4bb3e21a1a6721be946e322b65fc1 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-peripheral.c from Linux. */ +#include #include #include #include diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index d0b14656c4d67355ae28b2425c32de8a75321616..868de4b1774b3b97b24cb486cacc9c1e9dbe0bb1 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -8,6 +8,7 @@ * * Based on drivers/clk/at91/clk-programmable.c from Linux. */ +#include #include #include #include diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index a30035eb8ce9626740e8e8708a0152081135771a..383f79cfbaf52abfe31f5a57ad08ea1cfae603a7 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 3545b0b24bd721d9e5e7b0cc3bf08b4757beeab9..82f79e74a1902ccc0f6f7e3e563c259a042da39d 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/clk-system.c from Linux. */ #include +#include #include #include #include diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index 84784ae41ce8a0094aee2e8dd321463d1e2df865..7c8bcfb51dba4e595adb06c08aba028ce451f94d 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/clk-utmi.c from Linux. */ #include +#include #include #include #include diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 1d738f160b6e0881ac6ca6730e54f016e9899b27..ee67093c60737bb88cf1046b65513f954acf0ca8 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -6,7 +6,7 @@ * * Author: Claudiu Beznea */ -#include +#include #include #include #include diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index aa4bc8fa47ad5d160a7702e11f423602134fa9dc..87d2069d89ce98de506588836ec09688ddf50dff 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -4,6 +4,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index b7d64bdbb3d4b3e9a07bc0c43928252050251f99..d858c860f696f9a49b1f052e6154b0c21ba07fb0 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -7,6 +7,7 @@ * Based on sam9x60.c on Linux. */ +#include #include #include #include diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 63b2c6474679282bd136017cbc8ca4075323eabc..3e62fb1f58d34ba07f6c0a0b2d963efbf40f023c 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -9,6 +9,7 @@ * Based on drivers/clk/at91/sama7g5.c from Linux. */ +#include #include #include #include diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6d6f12578db7027ab6890335c181804fa0852096..43136ab2e349dd06224ca9a28e206687142c0344 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -7,6 +7,7 @@ * Author: Claudiu Beznea */ +#include #include #include #include diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c index e5f74e714d54712e8b413c85bef5099993f0f57f..b8700f517fc99c617f431b616afada8aaa199ea4 100644 --- a/drivers/clk/clk-cdce9xx.c +++ b/drivers/clk/clk-cdce9xx.c @@ -8,6 +8,7 @@ * Based on Linux kernel clk-cdce925.c. */ +#include #include #include #include diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 199ca6eaa370a87bfce567ee72a40024c562b48f..d2e5a1ae401dcd038d484397294395eb0f0d2209 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index aa210e3d15fdf11dcd0e59378a9cfa6c1ad5fc58..2ad682b8fe2c419f9af2e41d11a257f49ed100e0 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 068798cf9b059dc0e03dfe3412a84eb69925319e..2a446788e191dc4b62db4d4b64ef8fb567b4217c 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index bf1c6a93b468c023bfc6e514d77effd879055dab..cfd90b717e73f3dd0a630617e16ee65d5ae40e45 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 53655059279e51d91b4fb81e43ca444c078cb956..85074f1b86e8720b6d6778fda4a67ca441d46266 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -9,6 +9,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 39e01c3fbc61c85e49a8a8ba1ccd253544d84a79..f410518461e914348af8a2d28656032d38d04e41 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -23,6 +23,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 4c832f1a53073ff18434b1f669154d87136e4575..ed6e60bc4841892c8b42f81edf3cda4994a903ac 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c index 4a3f50c638b18e9e208f3cf28a5a63b0027db9c6..a10a843f11f9bb169109295af30fd878ee32f50e 100644 --- a/drivers/clk/clk-xlnx-clock-wizard.c +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -7,6 +7,7 @@ * Author: Zhengxun Li */ +#include #include #include #include diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index b8c2e8d531b91f986995d15669620feff936e617..6ede1b4d4dcc4ac16e3d547d825d5bf8088239ff 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c index 0b41872b71923f28ac98569bfb8ea2291cafd926..8c22ed2f43d4a6f46cd04ff12040a4aa5eaa3744 100644 --- a/drivers/clk/clk_bcm6345.c +++ b/drivers/clk/clk_bcm6345.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Maxime Bizon */ +#include #include #include #include diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 030ff7cc58ec64d5b7ba5e83fdf0e03ab57aab33..4bcf9117551232a20df1ff99900e5c891002d71f 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include #include #include #include diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c index 1d740cf49f6277233f8403f85ab78daeae904c28..6c1139e5c519fbba93dde1aa4194fcd40efd7a59 100644 --- a/drivers/clk/clk_fixed_factor.c +++ b/drivers/clk/clk_fixed_factor.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index d1da05cc18a5b1eaeaf962cbc0c9c1e16388bdac..b5e78c70559ed6e067c26157a4e866cb87f829d1 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index d1a6cde8f0f8e8ad52873caa9b52d30435d472f5..7432ae8f0642b1722e9efd42ae3d9351c643904d 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -4,6 +4,7 @@ */ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c index 885aa834516589e0d2ed47df84b4124e42a72071..a77d0e7419c91d59a229cab477a43e43e7ad36e6 100644 --- a/drivers/clk/clk_pic32.c +++ b/drivers/clk/clk_pic32.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c index 8dd77f18d90170f30d1c6a6ff49ce2fdf561c51a..73d943f9e092313576e3a45018358c5564a8519e 100644 --- a/drivers/clk/clk_sandbox.c +++ b/drivers/clk/clk_sandbox.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index f96a15c30b3aaca856c78323bf068e90d1bd17d3..38184e27aa4fe9158f35adf24f2d349f925dcb4c 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -6,6 +6,7 @@ * Common Clock Framework [CCF] driver for Sandbox */ +#include #include #include #include diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 87350212775cb44eb1c78c852515b1a1d0264c38..c224dc1d2cb9573f7fff1da9338a50663e31f55b 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index e42d2032d45e011b751c19b395b6f99d5c54e78e..34a49363a51a89cc8d618058691bc6fd35850ca1 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c index 9ccaf13d24202434b136108c9df1e8a80d8cb748..bbe722560329c05950dbd15287075d40e8ff6879 100644 --- a/drivers/clk/clk_versaclock.c +++ b/drivers/clk/clk_versaclock.c @@ -5,6 +5,7 @@ * Derived from code Copyright (C) 2017 Marek Vasut */ +#include #include #include #include diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 35ee56d0693d6b1dc8c67d277887e1403b372c57..42ab032bf7e79548584031719fdd48c8c5c23641 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -4,6 +4,7 @@ * Siva Durga Prasad Paladugu > */ +#include #include #include #include diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 2e0e7bbe68ffaa5fa4b67d7ea52bb0912d168d8c..3b1e0208d47e483d643a8cbb669d73503b877136 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -5,6 +5,7 @@ * */ #define DEBUG +#include #include #include #include diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index b62b4646f4e557c74b022994735658458f03d42d..e3cefe2e0c72f48b0bc991e9d4c91ab490ae8fed 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -7,6 +7,7 @@ * Copyright (C) 2013 Xilinx, Inc. All rights reserved. */ +#include #include #include #include diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 5999926614840bbad766773f1b3cc8576a5439ef..e23f7da3f9299910ab1a930db6a43963ad842efd 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 3aa751bf4e42b8634dad43d359769602c79bad43..9caa932e12fb4657acfd9997bd3d84adc37f0afc 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -5,6 +5,7 @@ * Thomas Abraham */ +#include #include #include #include diff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c index 9c61a84ea61f4183d6843ddb03d28a7a35de7d37..33fb6ed0c7a412afc9b971b8ffcc95daf6f6d574 100644 --- a/drivers/clk/ics8n3qv01.c +++ b/drivers/clk/ics8n3qv01.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 45f1bcaea2886126c4dd2117ac4e30b7aa8b15c6..494156751dae6b21fdedc5e5b3cca76e615fa2fe 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 2cf20be2ccae356e116677076fd9276b47d2d79e..6d71c0c03ffe8fef35a356ae976cfcf607f3b2cd 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -4,6 +4,7 @@ * * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index 8f42a5cb1b72d62c951d8c7f5e4bb7052e6e553b..9228f279e27d75bc4fff40b34bd0e03f9854af04 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c index d7f2640fbb7c25b0b1ecd50bbf6a5ed23191b0e6..bc8574137137f1cae311649b36563164695fc37a 100644 --- a/drivers/clk/imx/clk-gate-93.c +++ b/drivers/clk/imx/clk-gate-93.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 65fa6b5b139f31c8c2f098cc306c25892f4c81d0..da2723023778eff9ce1eac9ed8ec7f7fcdb436b5 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -14,6 +14,7 @@ * */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba9923d8f6fab4322bb89a9d2fd678a1a22a8bfd..67825af89b8120b2e59b1b6e277efd677215b715 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index 96cf5fece75f849cfa03bb04f0f06e850e708f76..d39b87b2e245fce46ac417f800f0f730878dd0bb 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 70e2e53bdea5a10ec974c90dca552d565b7dcd5a..1a00dd1d287b2aa183927a25531ce02481b07d5a 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ed9e16d7c180467c591f8dc8a4f82edb3a3c723a..457acb8a401ee5b6fa60cde9593f9d82ae03e3ee 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 1f498b6ba4ea4930a5ce960672e354a50a9c3ef9..7dfc829df2c44158d8c0d1ab8337ef7ef7a71a43 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index ed4acd79ef741d63035907ef7820747a696d27f8..cf197df96dbba262170cdbffde5dfc46d1c75038 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 62fed7e3e32cef0933f2a8e05edfc08af390bab7..01e33de9d63f26eb9b0c3bae0b48e443b3b473e1 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 18bdc08971bfea55635d9d43e7219ce240ae7b7f..d900d4cd528642f1508050bb7d0deb27a3a82987 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index ede36c412bffd3861a0c50a639e9261eda3b0fc9..f0cb797d97500d9032a01340aa00c1c813a7db03 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -3,6 +3,7 @@ * Copyright 2021 NXP. */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index c80b02975aad0f8a83f794c4b17a149b6552c7be..dc91ac5adbf15b0494e2bc9e904f906a71c739aa 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 754f3948427582fd095f32ed5f1c08259980cdc8..d40635d17a4aadf4ef2cc5ba0e95467a42f8e1b4 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c index 20b9dc315001dc0a614ea1497bd9bcff8157b0da..077dd1bf02d3cbae359f142442fe38fa29694ee4 100644 --- a/drivers/clk/imx/clk-imxrt1170.c +++ b/drivers/clk/imx/clk-imxrt1170.c @@ -4,6 +4,7 @@ * Author(s): Jesse Taube */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 378cdff072feb8f4c991eab717e2ed6f5c01f61b..b8be3167c4cd9f6374df121fcf76541428bb60ed 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -14,6 +14,7 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 3911e033905698d71196eb93dd662113c906e50c..1cb685ee9abd4744f18c0a0712c0b49446bef267 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index c6692f2f9f5adc1a126339ee2ce822b9449ea285..fad306aeed232156016a1a1536956b96991dd49d 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c index a677a7caac7c84e5576a8b228e8ce4493a2e92b3..46ccbb1d834d28458bfd37cab709ed240bb24635 100644 --- a/drivers/clk/intel/clk_intel.c +++ b/drivers/clk/intel/clk_intel.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2beb63030f22a4e620ddc2816c5cb57f2f275132..259ea335959cf5de9ea5af3af74f52b1caed745b 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -6,6 +6,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 5072c9983c111fab2146421065d4ac4dc9bd3b0d..0c7411ee814db8b2bcc22cc62f18509325dde845 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -6,6 +6,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0c796a1788aaed56db1bb8d22d4fcfeae5879860..31b6fa02251ac945541d07435cf69a11f5f16efa 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -6,6 +6,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9612a62e56a70c9049644bcd7e58e33eb0372967..17e653a1f00ad2d3a7cc193373aa7988bab7249d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -8,6 +8,7 @@ * Author: Weiyi Lu */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c index ab27067344288fd5127a17b392db9e096cd0a9b0..193e069cb05357becc63508c61875b73b88db5db 100644 --- a/drivers/clk/mediatek/clk-mt8512.c +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -6,6 +6,7 @@ * Author: Chen Zhong */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 623f88499f1b0be2bd2b832d70cd10565eadfe18..29f70620e09dded79aecd8711d6fe3df7d381c7b 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -6,6 +6,7 @@ * Author: Fabien Parent */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c index ba8cc584d46f73dc06899c5c22a7bcff230c11f1..23865148372693e3878ddf6c89168b27d4e03afe 100644 --- a/drivers/clk/mediatek/clk-mt8518.c +++ b/drivers/clk/mediatek/clk-mt8518.c @@ -6,6 +6,7 @@ * Author: Chen Zhong */ +#include #include #include #include diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d2c45be30decb552ce3bb435c6468919c3832b8b..4303300d3a8d3729148757dfc3a96c37a95ad974 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -6,6 +6,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index a1b8d79149102183402f470a60511d5300d0232c..5220a337a8bbf7600a70fcae711990c58ae353cd 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -4,6 +4,7 @@ * Author: Igor Prusov */ +#include #include #include #include diff --git a/drivers/clk/meson/axg-ao.c b/drivers/clk/meson/axg-ao.c index 6ccf52127b027a4087d5a4f1076928888c62f468..311ffc1cca9a3b6927095128fe69b5bd9ae9d8bb 100644 --- a/drivers/clk/meson/axg-ao.c +++ b/drivers/clk/meson/axg-ao.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index c421a622a587d2eddef70d28b65e560722cf7f62..d6da59d269b0e09862ddf5dae45192d8ea4330f6 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c index 61d489c6e1c8df55245efd1e795259bd50594667..1a855a68966e5d07db4d52428a0bcf004d9d3f84 100644 --- a/drivers/clk/meson/g12a-ao.c +++ b/drivers/clk/meson/g12a-ao.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 5d7faaa3eabf98ca550ee371104c32b85c4396a5..e4fed8ddfb273bc8d10252ad21e07f5a4e14bfe6 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 72ad4fd0e85fd9e422082a7e241eb28d82e61312..e379540deee77bff47e29310cff6a56394c64e02 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -5,6 +5,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 0a82777ff74dbc7640e4263d2e8898e61ac9fda0..08f8bfcecbed28e1e15102e3c1bd5911d4fda0c3 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ +#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c index 5e8fb9952895421bcb6156e88889dc0346d86e78..5739fd66e8dfb7caf9dca36e2950d92829a4764a 100644 --- a/drivers/clk/microchip/mpfs_clk_cfg.c +++ b/drivers/clk/microchip/mpfs_clk_cfg.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ +#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c index d0e7b1ff844f00c4fd97f9188a376d1837ef1d99..f37c0d86047c6a7f882e3c675c06d14d448ccfae 100644 --- a/drivers/clk/microchip/mpfs_clk_msspll.c +++ b/drivers/clk/microchip/mpfs_clk_msspll.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2022 Microchip Technology Inc. */ +#include #include #include #include diff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c index 41c6df4fb9795faee0ae2461c0599763b7e259b1..ddeccb9145759fc31bb8cca3ae11e379197d581d 100644 --- a/drivers/clk/microchip/mpfs_clk_periph.c +++ b/drivers/clk/microchip/mpfs_clk_periph.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari */ +#include #include #include #include diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index a29ad0d7a68d7e8afaf2e46f92cf038a8ad6eadb..cc734450ef002033c53356aae70762470015604c 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c index 2e263fb2cd2862a68ba29edfbfd7acc3e69e2b22..4d3ac847d1d56c2480ead9e225161440caeffc2c 100644 --- a/drivers/clk/mtmips/clk-mt7628.c +++ b/drivers/clk/mtmips/clk-mt7628.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 30330393f760fe34b3c78f23b617309b18903477..f5c9bd735c1381c3855b3abc77834e0cb9c4f4f8 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -8,6 +8,7 @@ * Gregory CLEMENT */ +#include #include #include #include diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index c1bab84c070e35f3ce739cfce2e1468157ebe71b..846a73cd6b3610978c7dfe447c236ee12b9c1d61 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -8,6 +8,7 @@ * Gregory CLEMENT */ +#include #include #include #include diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index 513112c1146ca055d99c85eddd7de527b674c60f..678fdd5a45406377e97e1406001ab242f03be6cc 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ +#include #include #include "clk_owl.h" #include diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 41fe4d896a7c8f79ec00659f597270c6689a8c43..d3b63b9c1ac5b440b32bab0bc9f7b1c9720c1c30 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -7,6 +7,7 @@ * Based on Little Kernel driver, simplified */ +#include #include #include #include diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index c77d69128b00ad5e2d926e61f50878c7164f2e3f..479f9771a46445e92aee194325193d403eb4f1a3 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -7,6 +7,7 @@ * Based on Little Kernel driver, simplified */ +#include #include #include #include diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index 0e6d93b3d7c28c86f8e291758156a741a4a036ae..72f235eab212be6acb827306f6458fb2159f8759 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 3a9cf2a231f2ca19d767a305edb832fa544a01f8..05e5ab7d094b8534c9c7c73171101301f8c242cb 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -12,6 +12,7 @@ * Based on Little Kernel driver, simplified */ +#include #include #include #include diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 70a1f648e585920ff781362e65bd28e17aca62f3..8a897a52bc00bf283b20c4d6dddcd2836e6a8da1 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -5,6 +5,7 @@ * (C) Copyright 2022 Sumit Garg */ +#include #include #include #include diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index f41f8c9e8dee5b5d4fe0d6cd0ba6a83274400835..782df7da8444fac96b1be98d2876cfc3c769d0bf 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -8,6 +8,7 @@ * Based on Little Kernel driver, simplified */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 44c6f14618d2fb74d2093b5d8bf9bbfc8c66842d..66f8bb1669557bfd03ae993dc28a5a73d58eceec 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd */ + #include #include #include #include diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index d7825c66493e267bdf5977f4628e7b4fdb1eb9e0..2875c152b20d72638e9a1b7005e1366d4681b643 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 274428f2b4bd5e0b52818b4dca898acb45b68055..6238b14c29e1a6436f5d5be4aa768c93f622eca5 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c index f7dea7859f7444de8f4531044b4ea521d56c1826..f83335df6db6b42ad86b3fb112233f741dd02765 100644 --- a/drivers/clk/rockchip/clk_rk3066.c +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index a07285593b554b8855048e25e4b9a52ad55a9dde..182754e7052decf8e45cf1770c78cbed894abac5 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index f569a100f22b3ebe450db0088ea768881253af7a..f98b46a0f73bf67df1b61fd559efa6eed560bedd 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -4,6 +4,7 @@ * (C) Copyright 2016 Heiko Stuebner */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 9b71fd863bad48832d0f0915e30d627102710fc0..9371c4f63a4806a97d91ab53400be724829b351c 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 432a79291c8a4250b20735e71c7b5f9b7338d72c..0b7eefad15f100a00c23a85e28c465a0b6481981 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index e73bb6790af262c81a2ae11d94d700ec307d8861..861648321d408431cd05c4f8d76108735f6b0fe5 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 4b94d6364d137bbed43b85e4313aebaf9df8e697..314b903eaa03ea8b05044bbd4408da99946106f7 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include @@ -705,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case PCLK_HDMIPHY: rate = rk3328_hdmiphy_get_clk(priv->cru); break; + case SCLK_USB3OTG_REF: + rate = OSC_HZ; + break; default: return -ENOENT; } @@ -779,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case PCLK_DDR: case ACLK_GMAC: case PCLK_GMAC: + case SCLK_USB3OTG_REF: case SCLK_USB3OTG_SUSPEND: case USB480M: return 0; diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index d8943980521576acf00ff205c0327cdd812e90e5..1c5dfaa3800b256a45c91d8e332937e6c4b43dcd 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -5,6 +5,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index cc414c38432cc9a29c6d1de64c80f572a14f1e0b..67b2c05ec9ed30fe0a80af13e9dbf286b2c89fd5 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -4,6 +4,7 @@ * (C) 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include @@ -925,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) return rk3399_saradc_get_clk(cru); } +static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru) +{ + if (readl(&cru->clksel_con[18]) & BIT(10)) + return 100 * MHz; + else + return OSC_HZ; +} + +static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz) +{ + if (hz == 100 * MHz) + rk_setreg(&cru->clksel_con[18], BIT(10)); + else if (hz == OSC_HZ) + rk_clrreg(&cru->clksel_con[18], BIT(10)); + else + return -EINVAL; + + return rk3399_pciephy_get_clk(cru); +} + static ulong rk3399_clk_get_rate(struct clk *clk) { struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); @@ -955,7 +976,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: - return 24000000; + case SCLK_USB3OTG0_REF: + case SCLK_USB3OTG1_REF: + return OSC_HZ; case PCLK_HDMI_CTRL: break; case DCLK_VOP0: @@ -966,10 +989,14 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3399_saradc_get_clk(priv->cru); break; + case SCLK_PCIEPHY_REF: + rate = rk3399_pciephy_get_clk(priv->cru); + break; case ACLK_VIO: case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: break; case PCLK_ALIVE: case PCLK_WDT: @@ -1048,7 +1075,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0; - case SCLK_DDRCLK: + case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS: @@ -1056,10 +1083,14 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3399_saradc_set_clk(priv->cru, rate); break; + case SCLK_PCIEPHY_REF: + ret = rk3399_pciephy_set_clk(priv->cru, rate); + break; case ACLK_VIO: case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: return 0; default: log_debug("Unknown clock %lu\n", clk->id); @@ -1105,12 +1136,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, return -EINVAL; } +static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk, + struct clk *parent) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + const char *clock_output_name; + int ret; + + if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) { + rk_setreg(&priv->cru->clksel_con[18], BIT(10)); + return 0; + } + + ret = dev_read_string_index(parent->dev, "clock-output-names", + parent->id, &clock_output_name); + if (ret < 0) + return -ENODATA; + + if (!strcmp(clock_output_name, "xin24m")) { + rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + return 0; + } + + return -EINVAL; +} + static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) { switch (clk->id) { case SCLK_RMII_SRC: return rk3399_gmac_set_parent(clk, parent); + case SCLK_PCIEPHY_REF: + return rk3399_pciephy_set_parent(clk, parent); } debug("%s: unsupported clk %ld\n", __func__, clk->id); @@ -1201,7 +1259,8 @@ static int rk3399_clk_enable(struct clk *clk) rk_clrreg(&priv->cru->clkgate_con[13], BIT(7)); break; case SCLK_PCIEPHY_REF: - rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + if (readl(&priv->cru->clksel_con[18]) & BIT(10)) + rk_clrreg(&priv->cru->clkgate_con[12], BIT(6)); break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); @@ -1295,7 +1354,8 @@ static int rk3399_clk_disable(struct clk *clk) rk_setreg(&priv->cru->clkgate_con[13], BIT(7)); break; case SCLK_PCIEPHY_REF: - rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); + if (readl(&priv->cru->clksel_con[18]) & BIT(10)) + rk_setreg(&priv->cru->clkgate_con[12], BIT(6)); break; default: debug("%s: unsupported clk %ld\n", __func__, clk->id); diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 35563509d61767b6d36bf8eaf4717141cf128973..24eeca8bf265ab0cfe7eede20db3d1adefaaa643 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -4,6 +4,7 @@ * Author: Elaine Zhang */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index ceae08a19aa586ad4d0d977d705e4327d22d0268..4c611a390499201dd1fc93e5d589ae5094c957a5 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -4,6 +4,7 @@ * Author: Elaine Zhang */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 75202a66aa68c1a4f820bab29b317ea484f95632..fc442f7eebe24a5924b4e8b9530fdec054cddb12 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -4,6 +4,7 @@ * Author: Andy Yan */ +#include #include #include #include diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index aeeea95691479e8a6a450fb25b27f1b86d9494cb..cfdfcbdb0f4c21ee76ccebeab7e87355ed028b3d 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -5,6 +5,7 @@ * Author: Finley Xiao */ +#include #include #include #include diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 5ea86062800693594c2dc00e9547588ee8766aaf..c8fb60029070576588d60a58f621ce1cb59a893f 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -22,6 +22,7 @@ * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 */ +#include #include #include #include diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 581035842fc31a27c3d10410873b979df1f7cf86..1568a1f4cd912e681c0c0af7ad4d599ab49fb2aa 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -6,6 +6,7 @@ * Xingyu Wu */ +#include #include #include #include diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75d7ba2c3fe02f14e2db6bda08db9e46982..a38694809a0068fbf55191ed872f5bb7bd81e995 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -6,6 +6,7 @@ * Xingyu Wu */ +#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index cad07cc952e77cec74f7749b11e25e77e0ef77fd..37e996e78f96ca08c290ed7b40c651ac6536ae4b 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index fceb3c44b94e4e4f5249ff1bc99c7ae4adba4316..d68c75ed2013c6246a372dcfa99be0db5b3e87d2 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index a554eda504deefea5f84535e1b5a642eb66cb617..d440c28eb485f48ed2dba8bb38408067ccc74820 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 204ac170531dca93b16f3dd5db97268b9fbf6660..6f000c8e44487f917a584b36f98bd0b2faa3e940 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_CLK +#include #include #include #include diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 362dba10252182581fc05dc873f010e658dc9829..5174ae53a1a226f21d0d83dc0bb8558087edc532 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_CLK #include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 19fe248044b42c058bf520a3c3c9839fe22ae152..f27306fe33b358c10b0e16b400709fc20b7f1c14 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index f771369c9423c12846225d2d96a10712b4a21f6c..16ac589bb2bf4f0c690b4b8aad370f2f8b9cfce2 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index fdee4347e99174320aa2a71d661aabccba0f3e14..45d5ba75bf51bff14fd4badcbbb333205956ba60 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 04f76a7c2a38f8818421ce91300e3619738f1762..6ca800050ed0c6cc2ac123a5d99a46869c873971 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index f1b01d25ddd41895487b4716b9c1b470a846d2dc..fd26cd4f5d66f3dfe1134b51a54267e7ed3784ab 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 6751af8a8031170c6ebf24462f558089bba2ea3c..c5834f44103f1471d8d91cf45b10925a7a7f7580 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index d8621a3e64cc2595debea8b7d28b9f9fa86ce0b2..760d98cd620c5565df11c635befc351262b64272 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_d1.c b/drivers/clk/sunxi/clk_d1.c index b990a1185948e320a1dd05d8e7a02cff80b33fee..9dae761de83c417c1fb0ab48ca83b4eb2313b383 100644 --- a/drivers/clk/sunxi/clk_d1.c +++ b/drivers/clk/sunxi/clk_d1.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Samuel Holland */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c index e22956992014d29a32c05a9d67cf46d459a711ba..7b4c3ce517650e21f88a194daefcf93d79c40dc1 100644 --- a/drivers/clk/sunxi/clk_f1c100s.c +++ b/drivers/clk/sunxi/clk_f1c100s.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 George Hilliard . */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index ce55caeb1573c367dc044392a4c3303b1dd006f5..32bc95fccca48baf3b6cecff6ae65e02b4f78c47 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 1b7bd9dea2f81e7c364d2537a7de592f5ff507f5..071fd581003d4a1fea0ea3fc1a1ce58d6b5bf460 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index b1e999e18c1422957e71f4f1495bb86457021600..113dcff2851555dc849429f2ed85e810a92fb42c 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Jernej Skrabec */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 721debdae2386675d189d35590635bb5019d890c..0fef6f3566d524e172da5fb19e02c1527739af01 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 2ef4f45dacf554628706032b6f89662c022bf796..1782cffc404aab20f574fcc894eaf23a88e04aaa 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 85410e282e8538c6609776780cd0821bf00a3102..6524c13540e0c4f76666974ae146140918d0ac20 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8dc378da51aa26e891fb674ab1f63de9f48..c5214b9b3e2ebaf5902e5203522e91a019781a91 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c index ec52326c3b365eac9845e2fb98531ae0da2f486a..5a98a3f3f0e6c5e769b4375a88e7219cf62b3c92 100644 --- a/drivers/clk/tegra/tegra186-clk.c +++ b/drivers/clk/tegra/tegra186-clk.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c index 1b0b9818cdd4d410bb0abf4ad8c3c5401b875147..3cf279d6a3a9763c8fd15573bda7026e84df3ba3 100644 --- a/drivers/clk/ti/clk-am3-dpll-x2.c +++ b/drivers/clk/ti/clk-am3-dpll-x2.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c index 21ec01f8dd9aa06d9938f06439fbff54b7265c19..398a011a5cea9c82c2d38c823a2bc498c870e6c9 100644 --- a/drivers/clk/ti/clk-am3-dpll.c +++ b/drivers/clk/ti/clk-am3-dpll.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/dpll.c */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index c5c97dc35c4de48d58fabd1e8d302bf9be529c44..8926e57ebc848a8a080eb2be1a6337a8bbdf59bc 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c index 40a742d7fdc48ecf1c6b51913cc83cfa3d46e950..15941f17811a51bf7edeaa412ca68fc2bb908fab 100644 --- a/drivers/clk/ti/clk-divider.c +++ b/drivers/clk/ti/clk-divider.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/divider.c */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c index 873ceb8a2ab7df9358eeecd721c1bd70a2b6db1c..eb15f6243f2046ece233ea49a5c854e7c6848f71 100644 --- a/drivers/clk/ti/clk-gate.c +++ b/drivers/clk/ti/clk-gate.c @@ -7,6 +7,7 @@ * Loosely based on Linux kernel drivers/clk/ti/gate.c */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index b3a1b4cedb78f34af4ab9bf2b45639042a5d65ea..8323e6e6919c00d238475b475c35dee4f7bff629 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -6,6 +6,7 @@ * Tero Kristo */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 41e5022ea0cd1cdc6f6bfdd1e59894e76dcf8114..7aa162c2f70290a6dce1f2d76f99745215f57590 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -6,6 +6,7 @@ * Tero Kristo */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c index db5393414318f11c193a5f498c60a2415ec6fabc..215241b16135ba0610d405c3a0d944808c2197d7 100644 --- a/drivers/clk/ti/clk-mux.c +++ b/drivers/clk/ti/clk-mux.c @@ -7,6 +7,7 @@ * Based on Linux kernel drivers/clk/ti/mux.c */ +#include #include #include #include diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index e374bd3bcc20d140ca0e25d0ec63f3faeda06901..9e5760d33544ebcf958634ee45a58ddda011b7c1 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -8,6 +8,7 @@ * Loosely based on Linux kernel sci-clk.c... */ +#include #include #include #include diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 28cd151288190c9d2abcebfe977c12c6df72d416..6e5cc90f0f8ca5780e38faba7bd95c96e015dcbf 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/clk/ti/omap4-cm.c b/drivers/clk/ti/omap4-cm.c index a30ce9d09d273fece962b1f767e6dc615278fed9..3cdc9b28887d96b298f17aab8788270460106e95 100644 --- a/drivers/clk/ti/omap4-cm.c +++ b/drivers/clk/ti/omap4-cm.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 33369c93916b06a68f81db056988bd4954adae4c..c31e59641d9344bd5f6e870bfd0c2c3ed081e657 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 9f7842289218cce3a0638c523e566012bae60379..0ebd288ab4209788dd0f93271e3dbcc18915dfef 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -8,6 +8,7 @@ #define LOG_CATEOGRY LOGC_ACPI +#include #include #include #include diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index 437080ed778099bfd4eb71a2ff58ad8206b2192d..a86b9325dd8d68047c52c54446ef2be2ef8290d7 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY LOGC_DM +#include #include #include #include diff --git a/drivers/core/device.c b/drivers/core/device.c index 18e2bd02dd56acb98f65901bfb2a8b3183b87a05..bf7f261cbce02f36be0a7b39027beb478c5cc633 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -8,8 +8,8 @@ * Pavel Herrmann */ +#include #include -#include #include #include #include diff --git a/drivers/core/devres.c b/drivers/core/devres.c index 8df08b91021c3758a9d37216f426a21e9592c9a9..78914bdf7f210c15e7eb75453e0be95e92812505 100644 --- a/drivers/core/devres.c +++ b/drivers/core/devres.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY LOGC_DEVRES +#include #include #include #include diff --git a/drivers/core/dump.c b/drivers/core/dump.c index 5ec30d5b3c1a49ef92754a907f60800d0040c4e6..841124830ee78928bd9793cacf0f1a9d4530e6ef 100644 --- a/drivers/core/dump.c +++ b/drivers/core/dump.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 6be8ea0c0a9c9af0373b9b10d667ec7c8b346bda..5f27d25114851192a7fcc90ce3be9da0a500f6b3 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -8,6 +8,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 2839a9b737180295c7436711a4441203d9fbcffe..8034a8f48d99bca46e4df87a15215aa371b6297d 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_DM +#include #include #include #include diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 41f2e09b9c276f617274d66dca4ae3d7b74a2bc1..c8db743f529841667dd38b1e1da558675f7411c7 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -19,6 +19,7 @@ * Linux version. */ +#include #include #include #include diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c index d7913ab3d2fd582102c54663b8f4be541acadaff..b3b3d7ccdd56adb0b9bc6a2ce0ef36d15e500f5e 100644 --- a/drivers/core/of_addr.c +++ b/drivers/core/of_addr.c @@ -6,6 +6,7 @@ * Copyright (c) 2017 Google, Inc */ +#include #include #include #include diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index a3ebe9e9c2455895b67bc5f8db995d2f15dd4738..59ce9174ad076bff7795c108c06620b026e6688f 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 9a5eaaa4d1342a416990395a9289cd5c4a4f29e3..21a233f90f0b45c00e7cc996e52534d68a4aae03 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY LOGC_DT +#include #include #include #include diff --git a/drivers/core/read.c b/drivers/core/read.c index 55c19f335ae12b8d9f83d1cb2a10e2ffc13cf935..1a4a95cddea34a9f65b08e5e916a6b11516e944f 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/core/read_extra.c b/drivers/core/read_extra.c index 5a0153a46610e5789435fff0ab4f04461968abe8..5138348827831f370cd23c45aaa388ec6fc9c760 100644 --- a/drivers/core/read_extra.c +++ b/drivers/core/read_extra.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 7ff7834bdf08cef904b0cc7449b540ba2da888bb..dd32328098c42d61d5be496bba40cf1c6282e5a4 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY LOGC_DM +#include #include #include #include diff --git a/drivers/core/root.c b/drivers/core/root.c index 4bfd08f4813075b422770b7f8531b069f3418978..d4ae652bcfb1d5b625d845974b0234bb015063da 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_ROOT +#include #include #include #include diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index f402bb5d6748f3c9b492da78a0538d4e22c334fb..6022e7514e0e99ebda831a5724a2eb877a7ff9f5 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SIMPLE_BUS +#include #include #include #include diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c index f38372ec60bcad4d8c630001d164630f2f99dc32..1bb0d86e289dc1bea90ffcb93c051afc7fa1ddc8 100644 --- a/drivers/core/simple-pm-bus.c +++ b/drivers/core/simple-pm-bus.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index f0e69d7216b3f0f0eeaf1726d1b37b1577335473..a47b8bd3c0175b3688f315f59426825083ceaf55 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SYSCON +#include #include #include #include diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 762536eebc6ee2f89f1e3ff36b1032d107481d53..e46d5717aa62206d18734573ffe31cc8ede399bf 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_DM +#include #include #include #include diff --git a/drivers/core/util.c b/drivers/core/util.c index 108a3bc4dac14c41ae22466fe195595ab2b8babb..81497df85ffd191c54026ead92cb907f24a4bfc9 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/drivers/cpu/at91_cpu.c b/drivers/cpu/at91_cpu.c index b45cc6ca1a9af8c59ca5a0adeebf8470e841eb02..34a3f61c7e95709afb42a4dd2a35e05ed075714f 100644 --- a/drivers/cpu/at91_cpu.c +++ b/drivers/cpu/at91_cpu.c @@ -5,6 +5,7 @@ * Author: Claudiu Beznea */ +#include #include #include #include diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index db624ee47fb0e642990c771e816d5c9c6db7de6a..3dd04fa88581191068b4bc56b82fa23a2c760997 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 16f8f2e52194a33869ad733a33cb0b9297f8d3ee..9772578968bacc1f4f9d80974e29e09813298554 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_CPU +#include #include #include #include diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1bdc51bfafe93b303c12ae8aabb8503eb267..2e871fe313c107d83a0c85e103e406cfe2ed57fe 100644 --- a/drivers/cpu/cpu_sandbox.c +++ b/drivers/cpu/cpu_sandbox.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a565547a15e032038fb49060666867ffbe44..98ff95f5ff5c84f2fe82fa7411a8bd6be124bd3e 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c index 4e24ada40022e919a2d792cb49dec8556f588894..a229f6913b07ee18318b9e6d5cb8bddcf1db5048 100644 --- a/drivers/cpu/microblaze_cpu.c +++ b/drivers/cpu/microblaze_cpu.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2022, Ovidiu Panait */ +#include #include #include #include diff --git a/drivers/cpu/mpc83xx_cpu.c b/drivers/cpu/mpc83xx_cpu.c index 9a7b5fd7c423480ca6b812adb6a6830682d42f9f..e451c11116ab8037f4fe0df497396f678da6d317 100644 --- a/drivers/cpu/mpc83xx_cpu.c +++ b/drivers/cpu/mpc83xx_cpu.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 4f2958a23cee0abfea3f1ca1f43beb954fcfe728..d39a943cb8478baa3ebd91d6ef07c40545eb6de7 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -23,7 +24,7 @@ static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size) const char *cpu; cpu = dev_read_string(dev, "compatible"); - if (size < (strlen(cpu) + 1)) + if (!cpu || size < (strlen(cpu) + 1)) return -ENOSPC; strcpy(buf, cpu); diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index 0e43e82fc5fa3fb465d169766cdc3de1b42372d1..261d3efe84e5827a81d0cdbd20108706b32d892f 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -3,12 +3,10 @@ * Advanced Crypto Engine - SHA Firmware * Copyright (c) 2012 Samsung Electronics */ - -#include +#include #include "ace_sha.h" #include #include -#include #ifdef CONFIG_SHA_HW_ACCEL #include diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index efc791a4def4eb56e7a8dbfe9f6ea88849477c40..ad9e81a586c74fdd4ec0c0c39307207c94f0be1e 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -8,8 +8,6 @@ #ifndef __ACE_SHA_H #define __ACE_SHA_H -#include - struct exynos_ace_sfr { unsigned int fc_intstat; /* base + 0 */ unsigned int fc_intenset; diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index e3f81ebd5c742dca063cb3929ce54c84b8c97cb3..47a007f633a68b8fd1fbadc4f336b4b017fb5d1d 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -3,6 +3,7 @@ * Copyright 2021 ASPEED Technology Inc. */ #include +#include #include #include #include diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index 17cc30a7b54dfe1a70b71b376d33ce4796c0e64f..6b6c8fa658892e212ef1aa240ebe996e18b0bdb4 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -3,6 +3,7 @@ * Copyright 2021 ASPEED Technology Inc. */ #include +#include #include #include #include diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c index 6b19c171fcdae4bf607ef81b4c2d8728c79cfaec..31706960157c904360650c7642dfc9ee36283e55 100644 --- a/drivers/crypto/fsl/dcp_rng.c +++ b/drivers/crypto/fsl/dcp_rng.c @@ -7,6 +7,7 @@ * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux */ +#include #include #include #include diff --git a/drivers/crypto/fsl/error.c b/drivers/crypto/fsl/error.c index 7b232d94c2a3167b1272f8b7ec8c4de614fdb788..c76574919c74f60784edd2036b5c217f11fbc8b3 100644 --- a/drivers/crypto/fsl/error.c +++ b/drivers/crypto/fsl/error.c @@ -7,9 +7,9 @@ * Derived from error.c file in linux drivers/crypto/caam */ +#include #include #include -#include #include "desc.h" #include "jr.h" diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 0ecd6befd2591dc48afc901ef1c100896cc27884..9b6e4bca062c4a67de25fccbc558c5c9b113bd1d 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 79b32e2627c4579816a036efaea2adaff2c939f8..f22f24b60775e6aca58adb4f15ddcdfecb2073b3 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -4,6 +4,7 @@ * Copyright 2021 NXP */ +#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c index 7c22f8e012b839b0778a619506294974f03baba4..29af79f577dc8d770fcf950b45f7b73d745a6720 100644 --- a/drivers/crypto/fsl/fsl_mfgprot.c +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -4,6 +4,7 @@ * Copyright 2017 NXP */ +#include #include #include #include diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c index 125a72ae6d32cfb92b672e99bf2b7f38f50ff99a..335b7fe25acbcf65fe6994c54ca6bdd82c51d190 100644 --- a/drivers/crypto/fsl/fsl_rsa.c +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 55191736931812cecd968995ef74f73b84edb16d..d32c1fe5c31aa6137ce40c4676c9cd4798abaa14 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -8,7 +8,7 @@ * */ -#include +#include #include #include #include "desc_constr.h" diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 27e2480894657aacb05ddcefb5c354d49d67c7a0..8ae5c434bdbe70c35de20ace828a03125a59a28e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -6,7 +6,7 @@ * Based on CAAM driver in drivers/crypto/caam in Linux */ -#include +#include #include #include #include diff --git a/drivers/crypto/fsl/rng.c b/drivers/crypto/fsl/rng.c index 786a710f5fb6f1f76cf86d20e8dd2c9e40a518de..0636494805218a28d3769a1050285108adc77bdc 100644 --- a/drivers/crypto/fsl/rng.c +++ b/drivers/crypto/fsl/rng.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index e9c39ddcfd9e4415e3b7e08ece2888b772d2342b..9de30a6112fa2af8d24eaad30b7e7781d9f7bb92 100644 --- a/drivers/crypto/fsl/sec.c +++ b/drivers/crypto/fsl/sec.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include +#include #include #include #if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4 diff --git a/drivers/crypto/hash/hash-uclass.c b/drivers/crypto/hash/hash-uclass.c index 5d9f1e0d59bd6c21b41069ac7aa655943ae5b06b..446eb9e56a4f9246db856d96bb4f6082723c540b 100644 --- a/drivers/crypto/hash/hash-uclass.c +++ b/drivers/crypto/hash/hash-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_HASH +#include #include #include #include diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c index ffd4ab149ffb5acedeaf5db090868078433468b1..d8065d68ea486fbe70b414fae56af11ae0793e0a 100644 --- a/drivers/crypto/hash/hash_sw.c +++ b/drivers/crypto/hash/hash_sw.c @@ -4,6 +4,7 @@ * Author: ChiaWei Wang */ #include +#include #include #include #include diff --git a/drivers/crypto/nuvoton/npcm_aes.c b/drivers/crypto/nuvoton/npcm_aes.c index 8d3a30ea918d6a9ec3d40e3ea869c17a9f8f3e9d..6493ea108ec7fafd92b14adf613cf29907411c64 100644 --- a/drivers/crypto/nuvoton/npcm_aes.c +++ b/drivers/crypto/nuvoton/npcm_aes.c @@ -3,13 +3,13 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include #include #include #include -#include #define ONE_SECOND 0xC00000 diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c index 6da162069aa73bbf432a15369e92eeb371939de2..2a5e6726880b77150a31fc3abcc6e205e642d693 100644 --- a/drivers/crypto/nuvoton/npcm_sha.c +++ b/drivers/crypto/nuvoton/npcm_sha.c @@ -3,6 +3,7 @@ * Copyright (c) 2024 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c index 4f59adc09c9c94c46e3fc300fd5dddc72429b7e7..7bed444c3fbf2440c47b97e477ae2f86af4af40a 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c index 107500dd6e079b1bc2dd66ff021eb9604f5278dc..057cc74b10bb4dcdecb70152b59bee247be319d4 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_MOD_EXP +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 7f2cccb6af2020fd80434ef65361aca25aa82049..65ecdd022c4371adfbe13a8bceb8fe83a80b5840 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index bd2af94bb0dd014a4830ceb6b688374777bb2d46..8ef5fa4c481c3d4ffb79365808dc52bde890398a 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Intel Corporation */ +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 46c53e7c7a348c3855bf2da1a8b1a4624724cce4..34d2a2789ccff76c6f9ebb2a980b2fc2f689f2e9 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -2,6 +2,7 @@ /* * Copyright Altera Corporation (C) 2014-2015 */ +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index db09986f64b46bee631900ffcfbd1bbe65b6689c..d9039443b91cfd71bca7c67c6ffb8457eb87f97d 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac3e973a99d0b60a0cfd47eea50da06..4d36fb453323650f6bed2ea32f9432e10aec9506 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 9e57c2ecfa4f63c26584320c83842e5c213deede..4716abfc9a8b051aa562e8bc9a1f54f089d32e6d 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 7636e71a0a6b69e302d5819ce5e78ec5f682f4aa..e402f2929ab7d50f97a3bf004154f42f824daccf 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3,8 +3,8 @@ * Copyright Altera Corporation (C) 2012-2015 */ +#include #include -#include #include #include #include diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index 618ba00da645d6d008d5f72f5d6e7682b7d94032..c72a683ffef2b0f1fb7a94c9b20aaebf95ab5eae 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -6,8 +6,6 @@ #ifndef _SEQUENCER_H_ #define _SEQUENCER_H_ -#include - #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \ / seq->rwcfg->mem_if_write_dqs_width) #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \ diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 9f9aea804d97a2753c04a7e319f18c0793974225..9dada5e11756fb45b5c383bb7efaf1a1cd382a72 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -5,7 +5,7 @@ * Derived from mpc85xx_ddr_gen3.c, removed all workarounds */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 9a25192c079803dcbf9fc684ce339f57537baf74..8f8c2c864c3f84a2a9e27159052b8d896e2f55aa 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -10,13 +10,12 @@ * Author: James Yang [at freescale.com] */ -#include +#include #include #include #include #include #include -#include #include #include #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index cc87a95214d8a52388b35a5deee58d8e9b5649fb..e5481eaa0ddd78d376d1f8d5e39b6a929d71b862 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -3,6 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index 5674685a191e0f567a975a836f9670b1274af312..3b78118a9d823517c35388403ac3099b6071a5d6 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -3,9 +3,9 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ +#include #include #include -#include #include #include diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index c30ecdaafafd66d740f010ac86771a391ea10a65..1f8db90c45bde2b6956a150d9ba2182cdf679728 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -8,7 +8,7 @@ * JEDEC standard No.21-C 4_01_02_11R18.pdf */ -#include +#include #include #include diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index 75e3bfe08be7bd122a589b707f54208431eccf1b..ea79162262873e661463397f93715b4e1188c3df 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -10,10 +10,10 @@ * */ +#include #include #include #include -#include #include diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 31c58d9a8e31dcb7980f74c90c6e7dcb4331dc3b..f8d1468a26f16e9b1940e751144c2efa93eebd16 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -4,7 +4,7 @@ * Copyright 2021 NXP */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c index 7812b1b01cafa649c7d87e5c99bb20bbe2f200df..28f2219b2a432d203ee9e3d1c1742c1e24876063 100644 --- a/drivers/ddr/fsl/fsl_mmdc.c +++ b/drivers/ddr/fsl/fsl_mmdc.c @@ -7,7 +7,7 @@ * Generic driver for Freescale MMDC(Multi Mode DDR Controller). */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 94a5e447d56ac4b5c013d48ab8b8695cebb7801f..eb2f06e8300abf9f476830749a6bfdb8f58e1513 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -11,11 +11,11 @@ * York Sun [at freescale.com] */ +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index aaf9800b3723276afff5fc36ab5cde97d7742688..5e4ad56f0714eb4d87e7e943a3dfb31b5b3b2611 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -4,6 +4,7 @@ * Copyright 2017-2021 NXP Semiconductor */ +#include #include #include #include diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 31091bb44952618cdadfd89df04dc2d1c98725ee..cd332718b640469af9e2494edb02daa97902136a 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -10,7 +10,7 @@ * Author: James Yang [at freescale.com] */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index a8520754006a73ebe94515264f71a2a8f33ccaa2..16186bdbae72fa0b493efb344072a4264548062e 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -3,7 +3,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 00b4b376dd45da8a2799aae9155b1252d9fb7cf9..b830e7cbd1418a3c64f50475d77eccc4629a6367 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -3,9 +3,9 @@ * Copyright 2008-2011 Freescale Semiconductor, Inc. */ -#include +#include #include -#include +#include #include #include diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index b0a61fa2b4162d7644a88aa84ca7ba38e8db9c29..1c4a1cae4df4b6482ce4a4517bdf74047418d44f 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -3,10 +3,9 @@ * Copyright 2008-2020 Freescale Semiconductor, Inc. */ -#include +#include #include #include -#include #include #include #include diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 852a5d0eca41e4ec21610ea2606cf7d3c39dba98..7cff823458475da9b7faccee9c46a60ee0d7fd31 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -4,19 +4,16 @@ * Copyright 2017-2018 NXP Semiconductor */ -#include +#include #include #include #include #include -#include #include #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ defined(CONFIG_ARM) #include -#else -#include #endif /* diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 0a73170e41835adeaa34bbf94db5eeb493eb124b..60051392e713bcad80a550cd5127f1154eedf2ee 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -4,10 +4,9 @@ * Copyright 2021 NXP */ -#include +#include #ifdef CONFIG_PPC #include -#include #endif #include #include diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index e9209ce8b61d7ed3507bc102cc8f57ebba077067..52a4aa632304559fce99682842e48b91020e980e 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -3,6 +3,7 @@ * Copyright 2018-2019 NXP */ +#include #include #include #include diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c index 172e260a55d926483587e772800f11dea8ac83a9..c362a2da338baebc32b895c87cc89e838bfdfdb5 100644 --- a/drivers/ddr/imx/imx8ulp/ddr_init.c +++ b/drivers/ddr/imx/imx8ulp/ddr_init.c @@ -2,6 +2,7 @@ /* * Copyright 2021 NXP */ +#include #include #include #include diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 5b0ad773875da9f6a57faa8c618b232056d1e702..7a333880e6b66af01fea18d24c35b859dcc081a3 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -3,6 +3,7 @@ * Copyright 2022 NXP */ +#include #include #include #include @@ -10,7 +11,6 @@ #include #include #include -#include static unsigned int g_cdd_rr_max[4]; static unsigned int g_cdd_rw_max[4]; diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c index ccc10df1845282e5b1e1ac25eaa106dd09f7bbc2..cd905f952c64b5a9147234c69c4eb655b524df58 100644 --- a/drivers/ddr/imx/phy/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index cf5bdad7abe7be4187be57816b2da9b6b349f0a8..45e1a70dbd44d23151fd5e13c3ea91c1851921de 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index c1fc800f191b45292943fa8b93fbb4d8c6ff89d5..b9b2403012d91d6bbf1ea58e1b5dc8c2b261505d 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c index 985835ec92352671789f5586550b1c6ffae0ea16..2a4596680b19b6d26da7d6964e51ed43ff7c55d0 100644 --- a/drivers/ddr/marvell/axp/ddr3_dfs.c +++ b/drivers/ddr/marvell/axp/ddr3_dfs.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_dqs.c b/drivers/ddr/marvell/axp/ddr3_dqs.c index bda0d7ec4735ba1ee5754e4b51954a6b9a3aed0e..0db94212b90f5b343c62bb20bc8c06b8df9ffcf0 100644 --- a/drivers/ddr/marvell/axp/ddr3_dqs.c +++ b/drivers/ddr/marvell/axp/ddr3_dqs.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_hw_training.c b/drivers/ddr/marvell/axp/ddr3_hw_training.c index bb3e1be1f4c6fd7f1b296c1fef9d58bd1ea62e80..35d98faf58f3d2a62511ecf83add479d3c10f243 100644 --- a/drivers/ddr/marvell/axp/ddr3_hw_training.c +++ b/drivers/ddr/marvell/axp/ddr3_hw_training.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_init.c b/drivers/ddr/marvell/axp/ddr3_init.c index 23c6d119f61e85ef1ee73d809d15ba6914e2a138..a9dcb74cecb74adcad1b100db15dc06751e077da 100644 --- a/drivers/ddr/marvell/axp/ddr3_init.c +++ b/drivers/ddr/marvell/axp/ddr3_init.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_pbs.c b/drivers/ddr/marvell/axp/ddr3_pbs.c index 2322900185d3e48ae229e5dd167b4ee65122b557..069a42fbf5ed35a615ffac1beb3a8a5f38770b5a 100644 --- a/drivers/ddr/marvell/axp/ddr3_pbs.c +++ b/drivers/ddr/marvell/axp/ddr3_pbs.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_read_leveling.c b/drivers/ddr/marvell/axp/ddr3_read_leveling.c index db7003f72caf2b6013f1bf7d1a3f9ba579829a2e..30a5c354885744747556b9368b5e781beaeaffaa 100644 --- a/drivers/ddr/marvell/axp/ddr3_read_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_read_leveling.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c index f8fee2623d046814f8168a5abbb10c50fac4ea88..0b150b20f3a1e312aab79055e6bea27738e05245 100644 --- a/drivers/ddr/marvell/axp/ddr3_sdram.c +++ b/drivers/ddr/marvell/axp/ddr3_sdram.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_spd.c b/drivers/ddr/marvell/axp/ddr3_spd.c index c169a8ea16b4b2024d8aa259f85ba2fcd0303765..4763403c127886bcbae83a66811b638360418d2c 100644 --- a/drivers/ddr/marvell/axp/ddr3_spd.c +++ b/drivers/ddr/marvell/axp/ddr3_spd.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c b/drivers/ddr/marvell/axp/ddr3_write_leveling.c index ea7bac56d0ed154eafa7967db686d1c58025ebf1..d4add4477745b8a0b27be252b32aa35bc4fb71ca 100644 --- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c +++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c index 6ecacfeb93369092d8b076e2167472a6dab5201e..76aea96682c73067539eadafc574c5d9b2f2532a 100644 --- a/drivers/ddr/marvell/axp/xor.c +++ b/drivers/ddr/marvell/axp/xor.c @@ -3,6 +3,7 @@ * Copyright (C) Marvell International Ltd. and its affiliates */ +#include #include #include #include diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c index bfba5d245c68588a3ecc5ea10dfbb8a67de3adf9..149b6071cfde42ec5a840bc853929d5543d4b055 100644 --- a/drivers/ddr/microchip/ddr2.c +++ b/drivers/ddr/microchip/ddr2.c @@ -3,6 +3,7 @@ * (c) 2015 Paul Thacker * */ +#include #include #include #include diff --git a/drivers/demo/demo-pdata.c b/drivers/demo/demo-pdata.c index 73711991626bf9335cdf2a71adc742d635a7d799..818f77503a31032e1853a056ab27044f6dee4549 100644 --- a/drivers/demo/demo-pdata.c +++ b/drivers/demo/demo-pdata.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include diff --git a/drivers/demo/demo-shape.c b/drivers/demo/demo-shape.c index 3ccd5bced95e9b821ff779b29a689dd47b4bc954..b6b29bcb31b3397ec56b042c4385504b9278a345 100644 --- a/drivers/demo/demo-shape.c +++ b/drivers/demo/demo-shape.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index 944d58972224fd95f242c57d9a42b7b509f3ac06..28b271f7791cb24279e0a7aa33abf3f0975f4519 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -6,6 +6,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/drivers/demo/demo-uclass.c b/drivers/demo/demo-uclass.c index d7b1305dc65df180f8db8b434cde578374ad6f2a..09f9a47d4de6c9435c58ad79d6b74b2149d5c946 100644 --- a/drivers/demo/demo-uclass.c +++ b/drivers/demo/demo-uclass.c @@ -6,6 +6,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 540d48fab77dadd9ac8b2380492b140ca75b1088..2adf26e2fe24051734a8b50e6cdb77c043d52c26 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -6,6 +6,7 @@ * author: Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/dfu/dfu_alt.c b/drivers/dfu/dfu_alt.c index e9132936a90b9daced72b246c0f805f675e6fdf2..ece3d2236f3dcdd8b122581cb573d5ef36907baf 100644 --- a/drivers/dfu/dfu_alt.c +++ b/drivers/dfu/dfu_alt.c @@ -4,6 +4,7 @@ * Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index cfa6334e43973dc8726e12be20ed75c8b707bf94..12c54e90ef71ff4348a60a92e815925baafc0201 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -6,6 +6,7 @@ * author: Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index c36ac09189f3e7d0e3eedcdfdcc5b7c1161d4814..485586989c8a60007c1dff7963b685f7edc21457 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -7,6 +7,7 @@ * Based on dfu_nand.c */ +#include #include #include #include diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index 940cfefc986c8874d7168f68bee701d4c5f44df8..08e8cf5cdb37e1335cef4e41b5e72f9fab714467 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -9,6 +9,7 @@ * author: Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c index 043acbf022fccb60909375d22cf8d36c211be316..c4f4bd2e482f0cf2734c9ec3d3df1699b3df24d8 100644 --- a/drivers/dfu/dfu_ram.c +++ b/drivers/dfu/dfu_ram.c @@ -8,6 +8,7 @@ * author: Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 7c1c0f9e2dc7db296fb5a614503ff9d05651c061..2dae159370644c7b8f04468e0f6e460844029c9e 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -3,6 +3,7 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include diff --git a/drivers/dfu/dfu_virt.c b/drivers/dfu/dfu_virt.c index 2c31445af12ad7649bfde1b7ced0b8c232d8b860..29f7a08f6728f09f56246136ca02cc496a89af0a 100644 --- a/drivers/dfu/dfu_virt.c +++ b/drivers/dfu/dfu_virt.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 331815c469f9249e77b3d22495997a2264527705..da988f6bb6676e8a3fa04db08f2eea92a93c2cf3 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c index fd3a353d5484e038f0abcac6d7b72d7eae0907da..33c7b9814156aed3da4fcbd9627b44d65861d8d6 100644 --- a/drivers/dma/bcm6348-iudma.c +++ b/drivers/dma/bcm6348-iudma.c @@ -15,6 +15,7 @@ * Copyright (C) 2010 Broadcom Corporation */ +#include #include #include #include diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 2c76ba3fe328d577b1fabee2ac41383a0e98a213..0c1d88e10c65616318d57e59aaa2b4ad5184b4d1 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_DMA +#include #include #include #include diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 0cd9bcb511099c82e7c6e54ee4ea9b3ba9367bc2..700df2236bd1a4463f1615a4afc0d78f2f4c728d 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -9,6 +9,7 @@ */ #include +#include #include #include diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index c84db454bfd4d70e79f7f35cc2a98d35c62b0eed..9a5ba79f3fe523d404dbe3d7b72021c58548785a 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -5,10 +5,10 @@ * (C) Copyright 2012-2014 * Texas Instruments Incorporated, */ +#include #include #include #include -#include struct qm_config qm_memmap = { .stat_cfg = KS2_QM_QUEUE_STATUS_BASE, diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c index f15b67546a9f9e3daa48399af3de72529893fba7..0efdfd028cfda0a4dbc6c0e232e0905d7aa9b2b7 100644 --- a/drivers/dma/lpc32xx_dma.c +++ b/drivers/dma/lpc32xx_dma.c @@ -7,9 +7,9 @@ * Copyright (c) 2015 Tyco Fire Protection Products. */ +#include #include #include -#include #include #include #include diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c index 0290b93340f4d6e10a2f2c5fb0b754972c3f067b..a19e5e37fb9d68886782faae027819b771f0267f 100644 --- a/drivers/dma/sandbox-dma-test.c +++ b/drivers/dma/sandbox-dma-test.c @@ -7,6 +7,7 @@ * Author: Grygorii Strashko */ +#include #include #include #include diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index d64059f39ab8b32c5f88d6770b2ba214f7632688..31ffff07f5b3a140ca92efb266e0526df34fc42d 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index da341a2477839ccd53ee8e6d5b0378fccf88738f..8f6d396653e027cd01fd431f4d26f0e24e3c1596 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -5,6 +5,7 @@ */ #define pr_fmt(fmt) "udma: " fmt +#include #include #include #include diff --git a/drivers/dma/xilinx_dpdma.c b/drivers/dma/xilinx_dpdma.c index 1d615ec28387db4432bfff5b786b51fd4d6cc616..d4ee21dfc07f83580926dbe80b04b4bdd2fd6460 100644 --- a/drivers/dma/xilinx_dpdma.c +++ b/drivers/dma/xilinx_dpdma.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Xilinx Inc. */ +#include #include #include #include diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c index 2d2166bde6822258d6db42a042c155a0e34c3237..a33b5ef919cc2dd1291ce6ed06709c5073bc92f3 100644 --- a/drivers/extcon/extcon-max14526.c +++ b/drivers/extcon/extcon-max14526.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c index 1a59287388206234dd54ca30b7ac67bb7f40ac27..9dd22b5762694d48d9961b206c234e7960a46835 100644 --- a/drivers/extcon/extcon-uclass.c +++ b/drivers/extcon/extcon-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_EXTCON +#include #include #include diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index e4484d65aca5994cbaeb1a9276e09fbe732fb46f..01443c5d39e237b5114c2ea02a8afb29465bbab7 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 The Android Open Source Project */ +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include /** diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 12ffb463deb98229b3486cfd54b4785fcc041224..3576b06772998e9e66a6986eb9dc49b2681a0579 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -11,11 +11,11 @@ */ #include +#include #include #include #include #include -#include /** * fastboot_buf_addr - base address of the fastboot download buffer diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 93cbd598e024fe9a7c4fcbef302534d35da1ad57..f65519c57b4735d39770073bc17261d7048966c9 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 The Android Open Source Project */ +#include #include #include #include @@ -11,7 +12,6 @@ #include #include #include -#include #include static void getvar_version(char *var_parameter, char *response); diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index f11eb66761b1ed46d2e8401e71b0e4342b656ec6..060918e49109424e45dc7d38b8cb4bb99cb1fc0b 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c index afc64fd5280717ae4041ed70268ccc01cfbb0496..bbe26ddcc9bedf9f48399914f2951808da41c14d 100644 --- a/drivers/fastboot/fb_nand.c +++ b/drivers/fastboot/fb_nand.c @@ -5,6 +5,7 @@ */ #include +#include #include #include diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index e0767fc7551786aa380da1c849459eef938ffe9e..f1e91d151ea3ae91e03d676f3ada94f32f9df3c4 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -5,6 +5,7 @@ * Authors: * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index 94e6105cb38ebcadff3d248870a5a0bce5cb9384..ee0bf9a55b4850c34f110e86daad976c9a0f520c 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -6,6 +6,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 1521d9b66ac3e97cc25975c10b305105760e8d3e..4bf9f6041fecbe46bbdddfefc6ff7828d6afbaef 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -5,6 +5,7 @@ * Authors: * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index 44b32a829ddfe9a94084c05b0135a1ffe8a343e8..11142429c09b06a4235dcd1b92ea9dd5fccca996 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -5,6 +5,7 @@ * Authors: * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/firmware/firmware-sandbox.c b/drivers/firmware/firmware-sandbox.c index 226b5cfc191e306b3d1fe5071423581dd6f1759e..d970d75f781d6beabfd77d048e4c29e20e9e1361 100644 --- a/drivers/firmware/firmware-sandbox.c +++ b/drivers/firmware/firmware-sandbox.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Xilinx, Inc. */ +#include #include static const struct udevice_id generic_sandbox_firmware_ids[] = { diff --git a/drivers/firmware/firmware-uclass.c b/drivers/firmware/firmware-uclass.c index 84caf25548bee119916c4b347a0b9167141fe6b4..e83a147a000b6d919cd10d530e4b4b1ac209efe7 100644 --- a/drivers/firmware/firmware-uclass.c +++ b/drivers/firmware/firmware-uclass.c @@ -2,6 +2,7 @@ #define LOG_CATEGORY UCLASS_FIRMWARE +#include #include /* Firmware access is platform-dependent. No generic code in uclass */ diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f99507d86c6146e7165ad17a727cdb029640bc69..dfad798a2e7d93b3d93038f7b2cde1bdcce08a67 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -5,6 +5,7 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index c32c3f5c6a54fc8cea0a55ba5bc08675d4347ce4..03544d76ed4ad3980b3ce1b6a47ac1d72120d316 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -6,6 +6,7 @@ * Copyright (C) 2015 ARM Limited */ +#include #include #include #include diff --git a/drivers/firmware/scmi/base.c b/drivers/firmware/scmi/base.c index f4e3974ff5b4305d0654d413d6fee71a741490f9..1d41a8a98fc61b113f255e233589fea28d4f2b85 100644 --- a/drivers/firmware/scmi/base.c +++ b/drivers/firmware/scmi/base.c @@ -6,6 +6,7 @@ * author: AKASHI Takahiro */ +#include #include #include #include diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index 6d4497f4b92ad21f7b303896fc75e2cdc27885c8..7ad3e8da9f08866f4e722fee6f7e292bff9d91c5 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c index 631625d715bfaaf71578da69a0dd4f853d056b48..48dbb88a3fb504ff9ca18eab58e36230b3ed6516 100644 --- a/drivers/firmware/scmi/optee_agent.c +++ b/drivers/firmware/scmi/optee_agent.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index 19be280ec44845369d1f46509978ec9b5b59c60b..cc9011c7312f0e53878aebb9d127d9d449464243 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 96c2922b067e2886b3fa963bcd7e396f4569a569..603e2bb40aff1a8aa63005e8df37dcd903244b49 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 8c907c3b0328095c4b35ba089ed608fcda48b567..0f1003e167e6ba207c0eb93540b0508e6f3083d6 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index ac35d07ebaffd2e6a9c839cced7f9b52dffb1796..972c6addde21b7338cb4183b9fcaf257fe85d77d 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c index 67d2f45002490ab64a6bc997eda93a8f4681d99b..509ed618a997ff7ecdc0d2ef953f68c3b944607f 100644 --- a/drivers/firmware/scmi/smt.c +++ b/drivers/firmware/scmi/smt.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SCMI_AGENT +#include #include #include #include diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 8ce0f46e70c8dd4ea4e3756c04f291a75854ef5f..6c581b9df9c0e3d8b234fc978ad87896b1cb0b45 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -7,6 +7,7 @@ * Lokesh Vutla */ +#include #include #include #include diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index cb7877a8afe761dc5c2179d5961a8ba3df357063..4c00cdf0b57db544275cf652af937b3b2c04ec30 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -9,7 +9,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include #include #include /* ACEX device family */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index ae06f0123a0353b662c5733513f41f67c9b9581c..6a4f0cb9bc06ec4ed41e6ca6be404c8b05fa8e8a 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,6 +12,7 @@ /* * Altera FPGA support */ +#include #include #include #include diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 7e78d6e2d6ce6659b598b69cf101429e206ee8e8..6e8a313db35bcbde943140dc4c3850031c52000f 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -7,9 +7,8 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include -#include #include #include /* ACEX device family */ #include diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 38ba6c21ea2beeb733704196dfb56e6df9107b35..81e6d8ffc0bdcbdb704abec9a0ad0892aca40e86 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -5,6 +5,7 @@ */ /* Generic FPGA support */ +#include /* core U-Boot definitions */ #include #include #include /* xilinx specific definitions */ diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index 45caef4f5c108e86ae35bcca3692692aae622403..903d143a361c4b35848a5db5af2f6f41707ff9df 100644 --- a/drivers/fpga/intel_sdm_mb.c +++ b/drivers/fpga/intel_sdm_mb.c @@ -3,16 +3,14 @@ * Copyright (C) 2018 Intel Corporation */ +#include #include #include -#include #include #include #include #include -#include #include -#include #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000 diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c index b9cecdd8720a6f201338096be7561a2eed125d5c..adc60919f3b01b5d88b4fcba1231a8a1ca28f0c4 100644 --- a/drivers/fpga/ivm_core.c +++ b/drivers/fpga/ivm_core.c @@ -29,6 +29,7 @@ * the ispVMLCOUNT function */ +#include #include #include #include diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index 036580cad70f8cc549b02c53af39f430c0325d0b..e292d991cd18644ec4f97db77ba48d2b36ac3bde 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -10,6 +10,7 @@ * Copyright 2009 Lattice Semiconductor Corp. */ +#include #include #include #include diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index bb98c0e2bcf7e6854bd946c277b0579569357b18..d73414d5ac54140c677b01172e61536e29d5a6ce 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -4,7 +4,7 @@ * All rights reserved. */ -#include +#include #include #include #include diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index e9822b2bb0ecab9cae52c2b2c480794d677afdee..96b195063e0802ec82eaaf7d6036e1828b0a1507 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index 9473f0573289969162f37e483c47bec908a8fdfa..d73474f29ee13f209066c6c0efaf701702bc2bc2 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -4,7 +4,7 @@ * All rights reserved. */ -#include +#include #include #include #include diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 9cd6cb7f0fbd83f9c66c4ab78e9421df1b8326b0..6eef87b78e16d41cf8635a8930f6642e33c5ae48 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -6,7 +6,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include #include /* Spartan-II device family */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index b4d87d47d9332388bb2c1709b3c5553b9aefdfa7..e892fa571f196f42e3467017617090d60b0f3ff9 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -11,9 +11,8 @@ #define LOG_CATEGORY UCLASS_FPGA -#include /* core U-Boot definitions */ +#include /* core U-Boot definitions */ #include -#include #include /* Spartan-II device family */ /* Note: The assumption is that we cannot possibly run fast enough to diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 73fecd9dca5516fc52b1ba6385c877e0f7b36889..b450a81072ed3c0a71f80b65dfd5d4cf3e522b6c 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -4,6 +4,7 @@ * Eran Liberty, Extricom , eran.liberty@gmail.com */ +#include /* core U-Boot definitions */ #include #include diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c index 372f16d92d1a650fa6c26b60267f85e6a2a7be60..abae3b5b7511a5b4a94c81cf89b76f69bad163de 100644 --- a/drivers/fpga/stratixv.c +++ b/drivers/fpga/stratixv.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index 1957e8dcacaced8c0e185288c946d494393813d2..be58db54275cc7b382faf0fee696b2f668a5d433 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -4,6 +4,7 @@ * Siva Durga Prasad Paladugu > */ +#include #include #include #include diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8e2c12bb58b1271efea0e3d3a31084eafc49cfdb..3ded27f9b3ffa4b88bed1710f3c1b0c385df6f21 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -14,7 +14,7 @@ #define LOG_CATEGORY UCLASS_FPGA -#include +#include #include #include #include diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c46513226d9b36dee94b2265753fc773b0cd69ea..8170c3368ef6f89646e8617d869f1ca1f38b8cea 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -11,13 +11,13 @@ * Xilinx FPGA support */ +#include #include #include #include #include #include #include -#include /* Local Static Functions */ static int xilinx_validate(xilinx_desc *desc, char *fn); diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2b62bbbe3cf5d24608cddb58adea24cca123f059..2656f5fc5ecf3ad2d408028f00b203930f700fa6 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 57467b4d975aac8ecccdc828b6307243c6ca3af3..a2e3b305fa4173ec331f8d2101046fa7ed9960ea 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -6,11 +6,10 @@ * Joe Hershberger */ -#include +#include #include #include #include -#include #include #include #include diff --git a/drivers/fuzz/fuzzing_engine-uclass.c b/drivers/fuzz/fuzzing_engine-uclass.c index 08ce3ed2ec1566a6b5d44c57ce464bd4f29addc1..b16f1c4cfb71024890bf7f689273a47104107b2e 100644 --- a/drivers/fuzz/fuzzing_engine-uclass.c +++ b/drivers/fuzz/fuzzing_engine-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_FUZZING_ENGINE +#include #include #include diff --git a/drivers/fuzz/sandbox_fuzzing_engine.c b/drivers/fuzz/sandbox_fuzzing_engine.c index 677402470edc438648cc9492e444576136359554..ebb938e5ba8610bf9ad72ae1ce7506dad51cec9a 100644 --- a/drivers/fuzz/sandbox_fuzzing_engine.c +++ b/drivers/fuzz/sandbox_fuzzing_engine.c @@ -4,6 +4,7 @@ * Written by Andrew Scull */ +#include #include #include #include diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index bab7a7e80d1d3e121a9531f610a8465d8a6a4624..0a8edaaa418fdf24c0aa984ada7a560980751637 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_FWU_MDATA +#include #include #include #include diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c index 331428ccdb9a25e83f559b14623ecc223428af10..7a7cfe86114bf29ea85d2e16678d7f52ca16ba49 100644 --- a/drivers/gpio/74x164_gpio.c +++ b/drivers/gpio/74x164_gpio.c @@ -8,6 +8,7 @@ * */ +#include #include #include #include diff --git a/drivers/gpio/altera_pio.c b/drivers/gpio/altera_pio.c index 7ba1595e4ae3290e5ca4fb310dec582dd1ff1dc6..edc5a8093b0c46e0ad8fab58c905dc410baf6c2f 100644 --- a/drivers/gpio/altera_pio.c +++ b/drivers/gpio/altera_pio.c @@ -4,6 +4,7 @@ * Copyright (C) 2011 Missing Link Electronics * Joachim Foerster */ +#include #include #include #include diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index 50a6981590753fa7b25172de892bc2c1f7aa6f3f..f80f4afd24ff420def5fa528e94c5faa4612f441 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index 65d064b46dfb617fbfc25e1340a5d78fde049957..be1dd752bf769b06d6c688fc7d236b2ed9e01cdd 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -5,6 +5,7 @@ * Copyright (C) 2015 Atmel Corporation * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index 6e632c8fc7308da348adeedccd347e880410253d..af6631697f58bf13ca6068ac3255d2d5e7351634 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -5,6 +5,7 @@ * X-Powers AXP Power Management ICs gpio driver */ +#include #include #include #include diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c index ccf84fdae11f292e494dc4562b74b51d5dcc1dbd..704a6fa7121028fb088d0553da9beccb141162f9 100644 --- a/drivers/gpio/bcm2835_gpio.c +++ b/drivers/gpio/bcm2835_gpio.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/gpio/bcm6345_gpio.c b/drivers/gpio/bcm6345_gpio.c index e76c84e806ad5f7f91df6fbb0aabe6c146213a6e..e031f71a784d987697af9d8559f3d955b9cb3f46 100644 --- a/drivers/gpio/bcm6345_gpio.c +++ b/drivers/gpio/bcm6345_gpio.c @@ -7,6 +7,7 @@ * Copyright (C) 2008-2011 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/gpio/cortina_gpio.c b/drivers/gpio/cortina_gpio.c index e0ea14cce6960fafce0670d17a4dbd41d7953584..72ef523be96054a6638d37f84fd4f65c1d8b84b3 100644 --- a/drivers/gpio/cortina_gpio.c +++ b/drivers/gpio/cortina_gpio.c @@ -5,6 +5,7 @@ * GPIO Driver for Cortina Access CAxxxx Line of SoCs */ +#include #include #include #include diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 1ccb9e69f1580ec0485e5824dc29f43c65717190..b310f2dbf65183dc0c7463c32d349c759e4c9596 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -6,6 +6,7 @@ * Laurence Withers */ +#include #include #include #include diff --git a/drivers/gpio/ftgpio010.c b/drivers/gpio/ftgpio010.c index 4cb550a540c624dbe9ea22c24127098d6cd03ea3..6c091d4fd874bf5e93bda63e9f59894df95518e7 100644 --- a/drivers/gpio/ftgpio010.c +++ b/drivers/gpio/ftgpio010.c @@ -3,6 +3,7 @@ * Faraday Technology's FTGPIO010 controller. */ +#include #include #include #include diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c5608f4a9dfcc04183f829b0703d0f30ac839772..1c3d18796b3a07baf5a4d6206fbbcaf22e307ac3 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -6,6 +6,7 @@ * * Implementation extracted from the Linux kernel and adapted for u-boot. */ +#include #include #include diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index c8d2dff5f7bfd85e1c7b91b597f521e955d8ec16..ca7aa14eeb2310f9e601933419ba929acef8771c 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -37,6 +37,7 @@ #include #include +#include #include #include #include diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index d1a399388095cbade4b6a128c51cc41890cb7547..707785012322eb8b3aa21fe7bc2a6b59a6bd8e6a 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Marek Vasut */ +#include #include #include #include diff --git a/drivers/gpio/gpio-rza1.c b/drivers/gpio/gpio-rza1.c index 8c3fe61b25f61ea0f37995c1fd1baeae9f78ff16..f14be871e8d0462b3dab20ed9c7eed78b394132e 100644 --- a/drivers/gpio/gpio-rza1.c +++ b/drivers/gpio/gpio-rza1.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Marek Vasut */ +#include #include #include #include diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 92ce68dd4a135e8a63dec23f9ececada23fbbfb6..4234cd912c9f0277d5af80fec249a3028c8ecc03 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index 033fb4b60ee6e9dc4b0bf85c330c50056abc4f1c..61c705b5ac56d896f070c6caff51e55431e72d32 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/gpio/gpio_slg7xl45106.c b/drivers/gpio/gpio_slg7xl45106.c index a7c9ff53af7dc78583f5adc7f0feca68cdcc04c5..4ad06c18b4bdcf4391d999bf72dbf4a11e71e2dd 100644 --- a/drivers/gpio/gpio_slg7xl45106.c +++ b/drivers/gpio/gpio_slg7xl45106.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/gpio/hi6220_gpio.c b/drivers/gpio/hi6220_gpio.c index 7ceb5f424c9d8e760f85cc3753d3f24f27278962..e287c31b93fc11ae6e487abe377bcacd0f79f185 100644 --- a/drivers/gpio/hi6220_gpio.c +++ b/drivers/gpio/hi6220_gpio.c @@ -4,6 +4,7 @@ * Peter Griffin */ +#include #include #include #include diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c index 734b31d3dc17621fc7a5a6c6f815413c09183be1..66f8441840b54bb2d5f4b76cdf717bf80d17c60e 100644 --- a/drivers/gpio/hsdk-creg-gpio.c +++ b/drivers/gpio/hsdk-creg-gpio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index fc1d418315c560f2e794fb383d3764d98d482b39..3227a8d5b574eb074987870c6487b231fba0d980 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -5,6 +5,7 @@ * RGPIO2P driver for the Freescale i.MX7ULP. */ +#include #include #include #include diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c index 53ed0a3eed06e32608c1b9b8283c46f38fce93bb..20af35de2cf5b19735dba748a55d05d9d476cec9 100644 --- a/drivers/gpio/intel_broadwell_gpio.c +++ b/drivers/gpio/intel_broadwell_gpio.c @@ -3,6 +3,7 @@ * Copyright (c) 2012 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c index 0ab6e8a90bcba8c23758ad68fca169bbb0cc17fb..4a3ec6d6350230ae36a8a870cedb0a088d81a889 100644 --- a/drivers/gpio/intel_gpio.c +++ b/drivers/gpio/intel_gpio.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 096bc3b05bb7aa9064a9a6346b43a96a9bd90839..2ed0d0bea9a59738698f33ac47f5cdb0ffa3f6e5 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -28,6 +28,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/gpio/iproc_gpio.c b/drivers/gpio/iproc_gpio.c index 8688f12e43c72bdffc477b5681ca0f4c38de62d9..7187d3257b9057b108b2316b75d4ab7261446a79 100644 --- a/drivers/gpio/iproc_gpio.c +++ b/drivers/gpio/iproc_gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Broadcom */ +#include #include #include #include diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c index e183f5594b51fde1ac256181583394ca05fbb283..a15769793f175a77bc12e254c13008f1bf08ad22 100644 --- a/drivers/gpio/kw_gpio.c +++ b/drivers/gpio/kw_gpio.c @@ -12,6 +12,7 @@ * Dieter Kiermaier dk-arm-linux@gmx.de */ +#include #include #include #include diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c index 2b537e007ba9a7ab4adb5a45cf097e960970855b..de66c765d11e4afcf7d2355c810205e6f16d5df6 100644 --- a/drivers/gpio/lpc32xx_gpio.c +++ b/drivers/gpio/lpc32xx_gpio.c @@ -6,6 +6,7 @@ * Written-by: Albert ARIBAUD */ +#include #include #include #include diff --git a/drivers/gpio/max7320_gpio.c b/drivers/gpio/max7320_gpio.c index f733cc924e566f5ab4c62ccd120e3114bceebefc..647aed907b4cc7275ccb9ff1fb57121ccc1f8a85 100644 --- a/drivers/gpio/max7320_gpio.c +++ b/drivers/gpio/max7320_gpio.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c index 42e7fe9d474c729880a6c05a57ad322a936abfdd..df99fde5660205da7d562c4150df02faaeb3528c 100644 --- a/drivers/gpio/mcp230xx_gpio.c +++ b/drivers/gpio/mcp230xx_gpio.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/gpio/mpc83xx_spisel_boot.c b/drivers/gpio/mpc83xx_spisel_boot.c index 2be8c73ae3d7d7507e951b36369344836e8b5f33..fd26a36a0f9402b1d9e4e723dc0b423cb6bfbb13 100644 --- a/drivers/gpio/mpc83xx_spisel_boot.c +++ b/drivers/gpio/mpc83xx_spisel_boot.c @@ -5,6 +5,7 @@ * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx. */ +#include #include #include #include diff --git a/drivers/gpio/mpc8xx_gpio.c b/drivers/gpio/mpc8xx_gpio.c index e2b12f8b56c744707b19f0377e43e35511845523..2f6534653313558f07231c0e41eceed0aaf0f01a 100644 --- a/drivers/gpio/mpc8xx_gpio.c +++ b/drivers/gpio/mpc8xx_gpio.c @@ -10,6 +10,7 @@ * Copyright 2010 eXMeritus, A Boeing Company */ +#include #include #include #include diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index e9bd38f162c10c76460bc63f93c03a711cb4d38e..f7ffd8926aded4d054536e91988b6046f04d9671 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -9,6 +9,7 @@ * Copyright 2020-2021 NXP */ +#include #include #include #include diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c index 5a40304f1f932da68ce3dfb511a5d92d57913263..c97e44005ee1b6f61ef355da527dd38a5203d9f0 100644 --- a/drivers/gpio/mscc_sgpio.c +++ b/drivers/gpio/mscc_sgpio.c @@ -7,6 +7,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 2fb266f12854d17ae570da1f048e8ae8d2e57fc7..f5d9ab54e8170704f867cf3e6ae26a0c8bee2838 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -5,6 +5,7 @@ * (C) Copyright 2015 Mateusz Kulikowski */ +#include #include #include #include diff --git a/drivers/gpio/mt7621_gpio.c b/drivers/gpio/mt7621_gpio.c index 63a202310a5efad3f53b2cbdd8a90d83c4dd593b..43bb4df4da72384319d6afe3dee9e058ed22d0bc 100644 --- a/drivers/gpio/mt7621_gpio.c +++ b/drivers/gpio/mt7621_gpio.c @@ -7,6 +7,7 @@ * Copyright (C) 2013 John Crispin */ +#include #include #include #include diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c index 0d82380dde4a4775df4a67460d94f82380b011af..f706a6dfa4fed81cf7924074b420367f868f1cdb 100644 --- a/drivers/gpio/mvebu_gpio.c +++ b/drivers/gpio/mvebu_gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index cac6b32b279649472111548cd5517676127f004b..1dec4e35e0a706d2410dbdc4c36439c13c8f0c9b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -6,6 +6,7 @@ * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, */ +#include #include #include #include diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 80910c9ec4c237ba0ded0728822ca91bb21cf5ec..1356f89ac2f080e3c5a8adc94bcac4d5e3ad1d52 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/drivers/gpio/nmk_gpio.c b/drivers/gpio/nmk_gpio.c index c2716e71763293529c65062cf34092c99ad7a502..e1bb41b196cc34ca9636dbd755149eca905cecf0 100644 --- a/drivers/gpio/nmk_gpio.c +++ b/drivers/gpio/nmk_gpio.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ +#include #include #include #include diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c index da3b3ffbc92fdeccf62573fdd3517e411278616e..98e5dc79c1ccd9fdc67859e4278471f7bdf6fd4e 100644 --- a/drivers/gpio/npcm_gpio.c +++ b/drivers/gpio/npcm_gpio.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 741b2ff7f177919efd1ce34ea13c2993aa2890d2..e2565d709535a8e425b314dc5995f08486193db4 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -4,6 +4,7 @@ * DeokJin, Lee */ +#include #include #include #include diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 1aceafcdf58171479f2f28503898122abdfcf75f..50c4f75ddf5db592bebe735c0bb73e75b444e28e 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -17,6 +17,7 @@ * Copyright (C) 2003-2005 Nokia Corporation * Written by Juha Yrjölä */ +#include #include #include #include diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index fc4dcf9f98615ce32e344814912b99fcb71e91ba..b5ed35256ee761cb70615ffd45995fa76ee33caf 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -8,11 +8,10 @@ * pca9539, etc) */ -#include +#include #include #include #include -#include /* Default to an address that hopefully won't corrupt other i2c devices */ #ifndef CFG_SYS_I2C_PCA953X_ADDR diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 80ebaadb3e43f2509ded552696d7afdc7973c9fa..b0c66d18317eefd16911197896671d92158743ac 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -18,6 +18,7 @@ * 2. Support Polarity Inversion */ +#include #include #include #include diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c index 10ae86ec5d457431770ae78442119cc4ef5ea539..f38e215c4d6e86e109a8cfb5449c645a84cac7cd 100644 --- a/drivers/gpio/pcf8575_gpio.c +++ b/drivers/gpio/pcf8575_gpio.c @@ -17,6 +17,7 @@ * */ +#include #include #include #include diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c index d8edfefb2d752634bd470525e224796a4c31bf2a..975a2af3ccb883972441e8ea247ada2d328663c3 100644 --- a/drivers/gpio/pic32_gpio.c +++ b/drivers/gpio/pic32_gpio.c @@ -4,6 +4,7 @@ * Purna Chandra Mandal */ +#include #include #include #include diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 80fee841ee3ffe11ff66638383756cdd633474f3..0dd3434e9e046f3ded034334a375a55c8779e5d7 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -5,6 +5,7 @@ * (C) Copyright 2015 Mateusz Kulikowski */ +#include #include #include #include diff --git a/drivers/gpio/qe_gpio.c b/drivers/gpio/qe_gpio.c index ac6e68299e079beaf221a0136a24788d616a9c6b..16e8d1eae6edea5966764ba188a65e6ef69e7a4c 100644 --- a/drivers/gpio/qe_gpio.c +++ b/drivers/gpio/qe_gpio.c @@ -4,6 +4,7 @@ * Christophe Leroy */ +#include #include #include #include diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 24ba12dd820e68199499e53b05b13889e130d6c3..2e901ac5c7343571b30ebdb2ef7d31640794afb3 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -6,6 +6,7 @@ * Peter, Software Engineering, . */ +#include #include #include #include diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 83e65aa4aec4490af99956ef3ede5beb2c6bf220..06ed585f3d64c750dc3106b5aa33da1090e904ce 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -4,6 +4,7 @@ * Minkyu Kang */ +#include #include #include #include diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index f5be278144387e54ad7badce83ece64588a9ae18..305f9a6ff62f0e53ad9f4412d10255bebb648dce 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/gpio/sandbox_test.c b/drivers/gpio/sandbox_test.c index 4699a976252c2464b3c796e9edf96325dc4355ce..c76e19974196ffb5e2cc9ec23ebf46eed40c0b48 100644 --- a/drivers/gpio/sandbox_test.c +++ b/drivers/gpio/sandbox_test.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include #include diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 9f6051c1c4d36253500143b4348a487394b1d132..2495d6c1c154fd8bb908ac4d695196a0df0e2143 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -9,6 +9,7 @@ * for more details. */ +#include #include #include #include diff --git a/drivers/gpio/sifive-gpio.c b/drivers/gpio/sifive-gpio.c index 90f59120ecd08c9e7c0762fa0431be79f3d8b93f..151f484e8fd1c15cec00868daa26f183b4291d96 100644 --- a/drivers/gpio/sifive-gpio.c +++ b/drivers/gpio/sifive-gpio.c @@ -5,6 +5,7 @@ * Copyright (C) 2019 SiFive, Inc. */ +#include #include #include #include diff --git a/drivers/gpio/sl28cpld-gpio.c b/drivers/gpio/sl28cpld-gpio.c index e85f9260ec39725dfe219fbf9e25c7310eb6bf58..700fc3df298cfbb821f9e70dec76a99674b94b14 100644 --- a/drivers/gpio/sl28cpld-gpio.c +++ b/drivers/gpio/sl28cpld-gpio.c @@ -5,6 +5,7 @@ * Copyright (c) 2021 Michael Walle */ +#include #include #include #include diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index b8eb55465d3c2d83a988c699658035b4a4ce92b2..7a2ca91c76926b070c424aacb1455fa5bf41afee 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 5e86474d3dbb37c4eab7684d38e2355ccfdce00e..e4463a223f7b235e323d67eda270586f0c7c62f5 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -9,6 +9,7 @@ * Tom Cubie */ +#include #include #include #include diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 1d45b50074613b31039db96cf6895678b400e06a..b07496e6e49c3ce9fc83d7fda2089c460e4bf032 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -20,7 +20,7 @@ * MA 02111-1307 USA */ -#include +#include #include #include #include diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c index 01b8245c8d5b4fb73cef907347cda664b4a13422..94a20d143e10b868e760b50af4cc483568423b55 100644 --- a/drivers/gpio/tegra186_gpio.c +++ b/drivers/gpio/tegra186_gpio.c @@ -4,6 +4,7 @@ * (based on tegra_gpio.c) */ +#include #include #include #include diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 0c40d36c41e205073c02b95bf7abd0d511092517..55105f2802c30f334fec9debcf0099d3e252b240 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -10,6 +10,7 @@ * Tom Warren (twarren@nvidia.com) */ +#include #include #include #include diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c index 5b4bba96da70ba5a72320f4067ab30668f7967ef..339392dcd35a6e179e8f3d45916e0880a3b268a2 100644 --- a/drivers/gpio/vybrid_gpio.c +++ b/drivers/gpio/vybrid_gpio.c @@ -4,6 +4,7 @@ * Bhuvanchandra DV, Toradex, Inc. */ +#include #include #include #include diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/xilinx_gpio.c index c0a92378b035aa0b5da35f3fbc699acda4b78df2..fa8d630b4658628691621a997e83e434af4addf8 100644 --- a/drivers/gpio/xilinx_gpio.c +++ b/drivers/gpio/xilinx_gpio.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 - 2018 Xilinx, Michal Simek */ +#include #include #include #include diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 7db58c70663e9db8981c7ae7db7527bc8cb97084..71a56127c0aa9ead92782e0a2ac566b98b8632f8 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -8,6 +8,7 @@ * Copyright (C) 2009 - 2014 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c index 8aaffaf37b3dd1078153aab3defc607c74c60244..e9565ff5430e04720748bc2d5ef63d4ef98636a4 100644 --- a/drivers/gpio/zynqmp_gpio_modepin.c +++ b/drivers/gpio/zynqmp_gpio_modepin.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/hwspinlock/hwspinlock-uclass.c b/drivers/hwspinlock/hwspinlock-uclass.c index ea93efc97df7535cdc363d57eba8ac3c87cfe1d1..e9a4d7f9fbbd66297f7b146f06d793ce5a97590c 100644 --- a/drivers/hwspinlock/hwspinlock-uclass.c +++ b/drivers/hwspinlock/hwspinlock-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_HWSPINLOCK +#include #include #include #include diff --git a/drivers/hwspinlock/sandbox_hwspinlock.c b/drivers/hwspinlock/sandbox_hwspinlock.c index fcda55517e1e74678145c9c234f7a09d5c04c531..be920f5f99dfba4850bf3480cb9dc4433f8b04af 100644 --- a/drivers/hwspinlock/sandbox_hwspinlock.c +++ b/drivers/hwspinlock/sandbox_hwspinlock.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c index 5273b9bfed89ffb01bbb53c91bf747eef059048b..346b138e98f002629c702e1a001dc29b59c1be71 100644 --- a/drivers/hwspinlock/stm32_hwspinlock.c +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_HWSPINLOCK +#include #include #include #include diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c index 82cb5db5cc8bc0f34f82aa16947b724784dda8bb..142f41178c10988f41ddf5069a20e093bc1560a5 100644 --- a/drivers/i2c/acpi_i2c.c +++ b/drivers/i2c/acpi_i2c.c @@ -3,6 +3,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/drivers/i2c/ast2600_i2c.c b/drivers/i2c/ast2600_i2c.c index 9d1d70670b9546c76f401343fc3b8a3e92f02ea6..e566b01feacfb3b12f977f1b20a700382ea4a4ea 100644 --- a/drivers/i2c/ast2600_i2c.c +++ b/drivers/i2c/ast2600_i2c.c @@ -2,6 +2,7 @@ /* * Copyright ASPEED Technology Inc. */ +#include #include #include #include diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index 02ee406bbd7d4e5c80f66e52869b9ebb0a59ce86..1c1d5566dad41365044e51f30736665afd8dad72 100644 --- a/drivers/i2c/ast_i2c.c +++ b/drivers/i2c/ast_i2c.c @@ -5,6 +5,7 @@ * Copyright 2017 Google, Inc. */ +#include #include #include #include diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c index cfae36c74d19e051433167f65be3ed6d8c706195..b7a25885e66634cc7a8a062e5cbe761dc058fdda 100644 --- a/drivers/i2c/at91_i2c.c +++ b/drivers/i2c/at91_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/i2c/cros_ec_ldo.c b/drivers/i2c/cros_ec_ldo.c index dfe823c142c5df305d4dbf31a704b64bfb68a017..c593540ac1380d8d82e40470057a6ef01791f471 100644 --- a/drivers/i2c/cros_ec_ldo.c +++ b/drivers/i2c/cros_ec_ldo.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c index 2d610e0a2aa92bbdc5ed69ecaf10de02c38c22ba..75828b6e7c273c53fadf564494fb0346004df859 100644 --- a/drivers/i2c/cros_ec_tunnel.c +++ b/drivers/i2c/cros_ec_tunnel.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 391327472087afd7ea2530e4bb24c1cdaec076fb..25ef937dc0b3ba918916b59fb9d5a05cccc278b4 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -11,7 +11,7 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ -#include +#include #include #include #include diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e8c1623d41fdd9ecd73c6e433808d432bf02f807..29cf63375c7f173e71c8265f69ddd041c8fbc4f2 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -4,6 +4,7 @@ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. */ +#include #include #include #include diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 11c986722650c2297b9381fe0a7a274381edf5c8..28495a3f4285b7b4098f6e8112ed053885d98faa 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -5,6 +5,7 @@ * Copyright 2019 Google Inc */ +#include #include #include #include diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 9a364fdae375236f5136ea73aa333e2472dbe561..a7349e06cfd363597c52c53130253bb1129e313a 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -6,6 +6,7 @@ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch */ +#include #include #include #include diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index bac14fb2f422d6a60c315844275abe3949d6ab9b..d9d8ee81d2ed298aa6e5089abe747135612cfb21 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -6,7 +6,7 @@ * Changes for multibus/multiadapter I2C support. */ -#include +#include #include #include /* Functional interface */ #include diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c index 3f7cf8533ec763e44e12f10786f93342c0f229ce..935b2ac637727da082f4277203ed0af3ab9347a0 100644 --- a/drivers/i2c/i2c-cdns.c +++ b/drivers/i2c/i2c-cdns.c @@ -7,6 +7,7 @@ * with added driver-model support and code cleanup. */ +#include #include #include #include diff --git a/drivers/i2c/i2c-cortina.c b/drivers/i2c/i2c-cortina.c index 96f957164c191c9b5a008ddca52899738ce27044..960ae8c700f979ff3838576190991b3763bc3ec0 100644 --- a/drivers/i2c/i2c-cortina.c +++ b/drivers/i2c/i2c-cortina.c @@ -4,12 +4,12 @@ * Arthur Li, Cortina Access, arthur.li@cortina-access.com. */ +#include #include #include #include #include #include -#include #include "i2c-cortina.h" static void set_speed(struct i2c_regs *regs, int i2c_spd) diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index 0954d53847e62045cfb3939a64735f43b8221d17..d421ddfcbe2946dde139793a221f5b322d9b4253 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_I2C_EMUL +#include #include #include #include diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index e0a575fb4a48d1fa5877b56c79c0873e1a039b0f..5fc3cfe42ef7f8181d86eb8cde6f910384dcd46e 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -5,6 +5,7 @@ * This file is based on: drivers/i2c/soft-i2c.c, * with added driver-model support and code cleanup. */ +#include #include #include #include diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c index 788747879a2594ee35f2e868a096f11f9e1997e4..d453e243d6f2b24e94433c304ff6c7a684a1dde3 100644 --- a/drivers/i2c/i2c-microchip.c +++ b/drivers/i2c/i2c-microchip.c @@ -6,6 +6,7 @@ * Padmarao Begari * Conor Dooley */ +#include #include #include #include diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 380a9f8f3addc6a4d86ccab35d46b52dc7247f65..98f95859f3bc11975758fc74d755e4ca3a50ebd9 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_I2C +#include #include #include #include diff --git a/drivers/i2c/i2c-versatile.c b/drivers/i2c/i2c-versatile.c index a8f0a170f7992005a6ae3f7a1fc04cb7def73846..0a1a85dfc288fc3dbd53567f0e42f57cddf4ea83 100644 --- a/drivers/i2c/i2c-versatile.c +++ b/drivers/i2c/i2c-versatile.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 7c43a5546d3d2bc5ea2e4b021c9508a45fe7ccd2..fe0cd75d94a16fb9febb18bdb103fdf1035dca2b 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -7,7 +7,7 @@ * * Multibus/multiadapter I2C core functions (wrappers) */ -#include +#include #include #include #include diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index dc88cd19167e658db52c11b054365918afa659df..d715714638fff1c1b1567afb5fb33cfe82cd6242 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -4,6 +4,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#include #include #include #include diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 6c0d8eb5f4f532503f7b1595c5fc3189ed1e091f..ad9293c92e1ad2adf920f910369e643cfdd425d4 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -3,6 +3,7 @@ * Copyright 2016 Freescale Semiconductors, Inc. */ +#include #include #include #include diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index d8ceea10cda748c81e2593beb6f320fdf4a3b7ff..4fc6f1a11a7585d2b949f171a76e0ca19b0b1c3c 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -7,11 +7,11 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include #include -#include #include /* PCI Configuration Space (D31:F3): SMBus */ diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c index 6570f64fe7748ef887755ecdfe3a141ad7f68398..39af49c4ec54295212ead5a8caab8eb475ea1d9b 100644 --- a/drivers/i2c/iproc_i2c.c +++ b/drivers/i2c/iproc_i2c.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index a4e42e64a9b8fd1f056f4585c0a16b9490b28f20..496f4feec5666a5acabc1207472ca2cfa98ac1d1 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -6,7 +6,7 @@ * Written-by: Albert ARIBAUD - 3ADEV */ -#include +#include #include #include #include diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c index 19f1b6b08196622fe516df521bffa88bb13f8b3b..434e3461b1dd0b74dd57762b95722a319507b16a 100644 --- a/drivers/i2c/meson_i2c.c +++ b/drivers/i2c/meson_i2c.c @@ -2,6 +2,7 @@ /* * (C) Copyright 2017 - Beniamino Galvani */ +#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c index a83d7cb0829d3b336074c35785f63431f00bf2a4..ad730e0e79ffd9cb4b4266a17938102ef6d0d44b 100644 --- a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c +++ b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c @@ -4,12 +4,12 @@ * Written by Simon Glass */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c index f212bd1f983647e0df261b280ad8dd80cae752b8..4ca206115f855e9a8751dfffecd391afdca944e6 100644 --- a/drivers/i2c/muxes/i2c-mux-gpio.c +++ b/drivers/i2c/muxes/i2c-mux-gpio.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c index d1999d21feb77d14a6641d4285492f6a063b5ef8..a5d1bb0576dbc9747e494348cdae14ed1a497ad2 100644 --- a/drivers/i2c/muxes/i2c-mux-uclass.c +++ b/drivers/i2c/muxes/i2c-mux-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_I2C_MUX +#include #include #include #include diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index b4e3e16a9764fdf94aa50c68795c932ba7b4a4b1..0034dfbf6daf801828cc6b3e0eabbf16eccd1a99 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -5,6 +5,7 @@ * Written by Michal Simek */ +#include #include #include #include diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 949cc45d308d46411e6d6b032f85d8873aa889bd..5bc9cd7b295a41d2b4b9b215eef418e4bfe1bf1f 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -16,6 +16,7 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ +#include #include #include #include diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 44e8e191b0392b9a91e19f2e32c3df2039789064..c38330f758a9fc6c52365db2d670e2a356333daa 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -7,7 +7,7 @@ * Copyright (c) 2010 Albert Aribaud. */ -#include +#include #include #include #include diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 0acdaf7e7431f5a701843e7e17e2af279a0b385e..d501133a0c8fc67124b58fc33325f392d38ba817 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -14,7 +14,7 @@ * */ -#include +#include #include #include #include diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 8562dd82bd630f7872f5f3f22f34f1f65e567ded..07cda0fa67935c9153eaa9d44ddd8a692c7e28f9 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -1,8 +1,8 @@ +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index cf714d22ee4634a4b19c905cec9443f2da6c8a38..fff85118d0de1f68cd025217fee44c3190d3b649 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -12,6 +12,7 @@ * Andreas Larsson */ +#include #include #include #include diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ebe472e20cdb32a1cf291766364ba460a2215c04..6fc9d1eba9d1be50621a963f285bbf9035ca2f3f 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -38,6 +38,7 @@ * */ +#include #include #include #include diff --git a/drivers/i2c/qup_i2c.c b/drivers/i2c/qup_i2c.c index 26707d63980e0f309a8348e5cf06325226757cff..5ae3cccd4acd7669632b0f05d620e75cbd5c6fe5 100644 --- a/drivers/i2c/qup_i2c.c +++ b/drivers/i2c/qup_i2c.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index f0f9b2afacfbb7f9a48a497c92126bfb7773601c..ff9a2d80dda1c1b606cf9b7de325ae27e6a76031 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -11,6 +11,7 @@ * Kuninori Morimoto */ +#include #include #include #include diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index 2aa0f5fbfae4d49cd648d21aebcfca6571fa680f..f0e50914c68d4330f404a39fa31c8f7ee1d48d0a 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -9,6 +9,7 @@ * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu */ +#include #include #include #include diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index fa167268ae718f4370e7a726895be7df1397dd48..9927af94a80b1dfbb66c41e276d52118ba6b996f 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -6,6 +6,7 @@ * Peter, Software Engineering, . */ +#include #include #include #include diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 72d2ab0f73d87835bd026e8d87911253f12f00a5..505e20bc61c8c4cea9700b5fc5ad49f8610e60f4 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -4,10 +4,10 @@ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch */ +#include #include #include #include -#include #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include #include diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 74bb5e93397363328cf2cce491ac2cacb54ec449..c99e6de933279f1925be81042037ea957c7b66d6 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -5,6 +5,7 @@ * Copyright (c) 2014 Google, Inc */ +#include #include #include #include diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index ab816101dea0e8f7ab87f4a16a6d6b3d503c730a..3335d9482a29f82fc522a68bca9896594a623975 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -7,6 +7,7 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ +#include #include #include #include diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 1f2afc65e8b314084547b58535a2740f97731e43..ed8ba47de4500ca1fd34cde7426ed80fc8582a17 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -15,7 +15,7 @@ * Please see doc/driver-model/i2c-howto.rst for instructions. */ -#include +#include #if defined(CONFIG_AT91FAMILY) #include #include diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 3f51b1dd1db42b2700acc731cd8425b312969371..f42e08a6418038dec61b9591032a231709eb1399 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_I2C +#include #include #include #include diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index c927c0edf2504f42f12fc11c0830fd7ce64bd011..b8e07a533ca92d953f29953f6cb5dda260076184 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 2197f1805663d9435f66456976d46e676ab8d9c2..f36f2c7afacfa4aa59c2894dbc3d6b9c018c4c24 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c index d30eb5231229826328dc04d965cd9531092c2586..588f6bdcc4b40f1a6162a314b2e63abb24d378bf 100644 --- a/drivers/i2c/tegra186_bpmp_i2c.c +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 3c324bd26635ba1307826e94e66065c10dfb47d1..57d77d56ea5515cd902280294c0a586359d35cdd 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -5,6 +5,7 @@ * NVIDIA Corporation */ +#include #include #include #include diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c index 056024e350fbed1f742856b4d3b48045928c491b..72199a62b2d77c844a25b79a8f2cc70926831b12 100644 --- a/drivers/i2c/xilinx_xiic.c +++ b/drivers/i2c/xilinx_xiic.c @@ -9,6 +9,7 @@ * Copyright (c) 2009-2010 Intel Corporation */ +#include #include #include #include diff --git a/drivers/input/apple_spi_kbd.c b/drivers/input/apple_spi_kbd.c index 5b30cec2dcb9874001c98e97ffe666d4d6026bc2..7cf12f453a30d1c161bd47b3320203413a7085cf 100644 --- a/drivers/input/apple_spi_kbd.c +++ b/drivers/input/apple_spi_kbd.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/input/button_kbd.c b/drivers/input/button_kbd.c index 0a917ac8b9957be36c09b76330b1c000728540e4..c73d3b18be9c6a1e1afb8a41178e50d0f76e07a4 100644 --- a/drivers/input/button_kbd.c +++ b/drivers/input/button_kbd.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c index 0917ee20fedc76cc22990de667d3ff6b76c6bedc..c4853463739b19814c24b9ac53759312c2b9cee2 100644 --- a/drivers/input/cros_ec_keyb.c +++ b/drivers/input/cros_ec_keyb.c @@ -5,6 +5,7 @@ * Copyright (c) 2012 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 9bf21053cf064e586020a8c11e0be63f384ee371..e6070ca015296b29d618e31fb123669786f2d5e8 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_KEYBOARD +#include #include #include #include diff --git a/drivers/input/input.c b/drivers/input/input.c index 3f146fb07e6d59abb45452099a15a1bc03c5f7d4..8a6506e7c6f9f237386861ae5ec5ec60f379b292 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -6,13 +6,13 @@ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de */ +#include #include #include #include #include #include #include -#include #include #ifdef CONFIG_DM_KEYBOARD #include diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c index 2e631660c880d58d5aa771db9065b3444b62ae83..e2fb2e1707875af4bd2fff23391426689fe7b953 100644 --- a/drivers/input/key_matrix.c +++ b/drivers/input/key_matrix.c @@ -6,6 +6,7 @@ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de */ +#include #include #include #include diff --git a/drivers/input/keyboard-uclass.c b/drivers/input/keyboard-uclass.c index df9ee8f7d659b304540a29f563af52038965d62f..aefc8e825e207749cf10eb9d8fb636c730a3b01d 100644 --- a/drivers/input/keyboard-uclass.c +++ b/drivers/input/keyboard-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_KEYBOARD +#include #include #include #include diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index fc13975d4f0f496ca1f242c345851bfb4b1d602a..d4741a76663eab3ddcbea91402b59a981204a129 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -4,6 +4,7 @@ * NVIDIA Corporation */ +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index 9327dea1e3bba51fcb81685e6c639e8558ce48bb..6ecd84303bc2bf56df73a45c41ea0515c9357d7b 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/iommu/iommu-uclass.c b/drivers/iommu/iommu-uclass.c index bb31cd519d25d163bea32c1f4e0df58f6acb6129..dff3239cccb151c59041e14dcc1cc0b9b52d2f9e 100644 --- a/drivers/iommu/iommu-uclass.c +++ b/drivers/iommu/iommu-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_IOMMU +#include #include #include #include diff --git a/drivers/iommu/sandbox_iommu.c b/drivers/iommu/sandbox_iommu.c index e37976f86f02b35d88de203984ccb0a720b22926..6ceb7fd5ec374a55b12982182ede7d0b9a39a70f 100644 --- a/drivers/iommu/sandbox_iommu.c +++ b/drivers/iommu/sandbox_iommu.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index f37bf6a1550c5ef52877aa302fdab4c3fa30ed8a..a4be56fc258443802fbf0ef4158890615ec20355 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_LED +#include #include #include #include diff --git a/drivers/led/led_bcm6328.c b/drivers/led/led_bcm6328.c index dcc5741195cd3f7993e8f5e359a360b044227479..f59a92fb1fda3bbd538fd86294f50baab1f53fb6 100644 --- a/drivers/led/led_bcm6328.c +++ b/drivers/led/led_bcm6328.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/drivers/led/led_bcm6358.c b/drivers/led/led_bcm6358.c index b1373ab7426721c34f981e4e7a4ccb47d13d1aed..25aa3994d0e4a252edabe6706e977fd1ca266fb0 100644 --- a/drivers/led/led_bcm6358.c +++ b/drivers/led/led_bcm6358.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/drivers/led/led_bcm6753.c b/drivers/led/led_bcm6753.c index 170caf7bdca76818ae851ddcfc1c3082e6f2a961..2466d9301166379bfd0382b20665fa0a5f26eca8 100644 --- a/drivers/led/led_bcm6753.c +++ b/drivers/led/led_bcm6753.c @@ -6,6 +6,7 @@ * drivers/led/led_bcm6858.c */ +#include #include #include #include diff --git a/drivers/led/led_bcm6858.c b/drivers/led/led_bcm6858.c index a6efdcf640535729671ed7937932acefe7acd57d..397dc0d8693ddd8fae84843b3b3a25507d8251fd 100644 --- a/drivers/led/led_bcm6858.c +++ b/drivers/led/led_bcm6858.c @@ -7,6 +7,7 @@ * drivers/led/led_bcm6358.c */ +#include #include #include #include diff --git a/drivers/led/led_cortina.c b/drivers/led/led_cortina.c index 2d3ad323d33be7837057c85ba0eb676174d11311..bcbe78d632ac5fb8a4b4b7bfd5fa471e5d3cf929 100644 --- a/drivers/led/led_cortina.c +++ b/drivers/led/led_cortina.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c index ce22fb49f2a96f1d0022135288f57517a676c6d7..71421de628c993860dfde9efa5e0c7519d5618f2 100644 --- a/drivers/led/led_gpio.c +++ b/drivers/led/led_gpio.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index 15dd836509b8b9b1f94b60195c9ce64b658b107d..ae6de3087ab7754a22949decdb2488be670e1096 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -4,6 +4,7 @@ * Author: Ivan Vozvakhov */ +#include #include #include #include diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c index 2ee49734f40654b528b68ba1ccee213e645431fd..30c8e2f03fa8f688b16b8e38a0ffa49776aea23b 100644 --- a/drivers/mailbox/apple-mbox.c +++ b/drivers/mailbox/apple-mbox.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 5eafe46fd4d073d2ce155856a65b2894b66a72de..05f6b1795d64269cda206d2a1836fcc9f264f320 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -6,6 +6,7 @@ * Lokesh Vutla */ +#include #include #include #include diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index 4bf4987ce0a1db957f165dd5726fccdeafb42f8a..85ba8c5fd99d53b471e450ac7189fe6c5909ad1a 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MAILBOX +#include #include #include #include diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c index a2cfde2f62d6ee23f32a2c20844f1abce4bdf98d..ffd4674d1ef7f12089ab0a5191b33fea8348a75c 100644 --- a/drivers/mailbox/sandbox-mbox-test.c +++ b/drivers/mailbox/sandbox-mbox-test.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c index 87e06e492fe7a2c6d73d2790fae3fed8f9573cf0..87d38de0cb612afaf971e47434298f4bb2448e28 100644 --- a/drivers/mailbox/sandbox-mbox.c +++ b/drivers/mailbox/sandbox-mbox.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index dda108735fce5877d85c3b9aa644fbca563cbcf5..046e1a8aca6e6af41ac4d78fb5f30451b2139ad3 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MAILBOX +#include #include #include #include diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index bfd4d7cdf2e4d8047484fd83aa285677ac497916..08c51c40f1411a51653ee74c8872db05aad4987a 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index 4df69734ed952c707992671577a375c6ddd3f75b..eb86847bbe2354e0bfda3d4551e64066ec9c3f38 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -5,6 +5,7 @@ * Copyright (C) 2018-2019 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index 713dead5c572feb35805fefe97ca943c1fde6874..1ce9607785862b2ecb5d6e940b83ba05d41e6bc1 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_NOP +#include #include #include #include diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 29131f536a66df204c937b556d19b33c3f802ec4..41325eb0f9414903eec725c051350786b5412fa7 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 8af48e199a74ad53a9ba98d1f6494e78e71e3ea3..8877b8f4385b9bb220dfcb0e9f603253dc7d453c 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c index 21e64fa3e6fef88bdc2b0a6a0a16b83761bb35ec..878df12771c8d72907e1ee86d2de5cb068fd2039 100644 --- a/drivers/misc/altera_sysid.c +++ b/drivers/misc/altera_sysid.c @@ -4,6 +4,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 3b9046da880c106859978d36a5a10a1e6ce2259b..707daa90bdba76551bc28848ecfbda881b0c901c 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -10,6 +10,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c index 8220addd579bbc147c5ea138fe9324a8a3637e72..ba3a599c4a51714ce58b04dd9af2347f1b1d6640 100644 --- a/drivers/misc/cbmem_console.c +++ b/drivers/misc/cbmem_console.c @@ -3,8 +3,8 @@ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. */ +#include #include -#include #include void cbmemc_putc(struct stdio_dev *dev, char data) diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index fabe4964a334ba8cbf04a155a7c9baf615a8b41e..9c1e6a5e3e70686feacce2d7bafe6f6468ffd7e0 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -15,6 +15,7 @@ #define LOG_CATEGORY UCLASS_CROS_EC +#include #include #include #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/misc/cros_ec_i2c.c b/drivers/misc/cros_ec_i2c.c index 5516aa8b3ffd47ab48abff395baa22f4032b2af7..a1b78a3045dd56e799fd56954fbf71915b0e06fe 100644 --- a/drivers/misc/cros_ec_i2c.c +++ b/drivers/misc/cros_ec_i2c.c @@ -12,6 +12,7 @@ * KBC. */ +#include #include #include #include diff --git a/drivers/misc/cros_ec_lpc.c b/drivers/misc/cros_ec_lpc.c index e2a3226362a9707c559c28362c9805cc11fe143c..1a8a81349c3a520489ff17ce3695cd2b2165ee4c 100644 --- a/drivers/misc/cros_ec_lpc.c +++ b/drivers/misc/cros_ec_lpc.c @@ -12,11 +12,11 @@ * KBC. */ +#include #include #include #include #include -#include #include #ifdef DEBUG_TRACE diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 1cad51d474de333523872717f315fad9adf801b9..1201535f4af4b834cedcfc0e5a1c4983bf5e8015 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_CROS_EC +#include #include #include #include @@ -16,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index e86791c03a73c8c84e891c75781bd50ad22a2b7d..591ff30df89b8e52098ca16bb2265c753fdc7b0b 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -12,12 +12,12 @@ * KBC. */ +#include #include #include #include #include #include -#include int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes) { diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index 302015e27938c1241308934cd50f7a5b4f75a9d5..9340596f2c6392f9d69f2c37ac445e798d0f1777 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -8,6 +8,7 @@ * and 4 programmable non-volatile GPIO pins. */ +#include #include #include #include diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c index 1963c8664a54e8f28fd72448dba9bddd63831e8f..a518f750611a46c47cd608660464a3c9a138ab04 100644 --- a/drivers/misc/esm_pmic.c +++ b/drivers/misc/esm_pmic.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 66803f4b9975f4792c70adf16625cdf0e5bf1799..1ffc199ba1e4939b737feb83f3208d00b6339bfc 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_FS_FIRMWARE_LOADER +#include #include #include #include diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c index 2c3d2348076258d0a9ca70d7fbebe312011d4ef0..179053a298af955ca2ae5d9c63b75af18cf36f91 100644 --- a/drivers/misc/fsl_devdis.c +++ b/drivers/misc/fsl_devdis.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. * Author: Zhuoyu Zhang */ -#include +#include #include #include #include diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 93f41da0f974fbd6ff8bbef34b150b180ef6f76a..f165b8c36ba445cf01d53b41206c3b5247e3cbf3 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -4,7 +4,7 @@ * Author: Dipen Dudhat */ -#include +#include #include #include diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 65468a68dbdfdeab0fe2d57b5554872dcd19e73f..85cc3c26b2eff3ce699c56f0de834fd841e1f3f5 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -8,6 +8,7 @@ * Martha Marx */ +#include #include #include #include diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index e7c0df78b6b65af2e2d49ad2341a0243dbbc465c..6b831281e96ff188d095f587045f3caf5738788f 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index 7518089e1e3e7ed603559b94bd7ae7518154cfb9..3597ee22242cc6b9a435f9ab9d5f4877607a4de5 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -3,7 +3,7 @@ * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include diff --git a/drivers/misc/gdsys_ioep.c b/drivers/misc/gdsys_ioep.c index d4916a277b84bcd505af8614308a9925abe18e10..145cfa23c6c5fea0401e1656d680dc3a51729371 100644 --- a/drivers/misc/gdsys_ioep.c +++ b/drivers/misc/gdsys_ioep.c @@ -11,6 +11,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/drivers/misc/gdsys_rxaui_ctrl.c b/drivers/misc/gdsys_rxaui_ctrl.c index d4cd63ca9f89fc8a35bc43d7e91b95f2e312deb3..8f5cbe420f8756b8609bd252deb5e1e2effebbe5 100644 --- a/drivers/misc/gdsys_rxaui_ctrl.c +++ b/drivers/misc/gdsys_rxaui_ctrl.c @@ -7,6 +7,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c index 0adbb8df3c2ca8c0c553996902926abe57bd0f54..27e7dc483276e71abfa72d4eb600905b717e14fc 100644 --- a/drivers/misc/gdsys_soc.c +++ b/drivers/misc/gdsys_soc.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index e63689967a7ac0ee0f1bdc7e607bfb728ec11a67..30679f80cf15539e0cdb7c383ad44602569cd09b 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 10f0173d80500d026514f022fed150c0f2ed57a5..9111bd724cbbfb097460e4bae87343254d60143a 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -5,6 +5,8 @@ #define LOG_CATEGORY UCLASS_I2C_EEPROM +#include +#include #include #include #include diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 3ad2e047ee3ee84ef5cb8a6c6eea1431923649fe..6f32087ede56d7eb98de2affdd64f52625a52342 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -5,6 +5,7 @@ * Copyright (c) 2014 Google, Inc */ +#include #include #include #include diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c index fe196b6081987401acb34937e61b00cae9b667ee..a0fece985d85bc3105d6448458fea5c095be8585 100644 --- a/drivers/misc/ihs_fpga.c +++ b/drivers/misc/ihs_fpga.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de */ +#include #include #include #include diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 90d251a440589ca07e545ae1303121a74f888188..b81f73f283f4c5fb7f3325aaa4b7ed5a9a0df65d 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index bbd7e24200bde6a7809dc38c462860719d5a842e..798800aa75837f4100e7a737e9cc4cc582277a36 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a8d4293c91d4b58e55d63da078d274..6e2c678e614f6ba3fa35f471c41673d9ecd4e2c4 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 3745504637b3b472151577a70e0a201f3d7b9098..e0ec22c7abf9fa8afa58d81c5f3a6ea439c909cb 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index 0cf81f33ba5e704b45840be8c9e4cb2917946327..053cdcf0fe07c4d14f20447ff553ea0c1ed58e87 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -3,6 +3,7 @@ * Copyright 2020-2022 NXP */ +#include #include #include #include diff --git a/drivers/misc/imx_ele/fuse.c b/drivers/misc/imx_ele/fuse.c index d12539c8aac06142f72eff41cb97d801c397c30d..4e4dcb42cdd95fc609b0e9cb711a256b5a97228f 100644 --- a/drivers/misc/imx_ele/fuse.c +++ b/drivers/misc/imx_ele/fuse.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 79eb7c200dc24aa42ca3855079ebe232d8ad70e7..7b79ed2df466010c1c08fd3ed3638b03e1320dd3 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_IRQ +#include #include #include #include diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c index 5d176f63b5cfa7d465d7ced56d4b007a8a640854..8b5573fcaddda24ea0d7c93b8a370f7d875c5bad 100644 --- a/drivers/misc/irq_sandbox.c +++ b/drivers/misc/irq_sandbox.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/drivers/misc/irq_sandbox_test.c b/drivers/misc/irq_sandbox_test.c index 3669b863bec180a29319bede798a8eb474af43a1..95c45c24edb82adb294fe48c62ac12b0d5286187 100644 --- a/drivers/misc/irq_sandbox_test.c +++ b/drivers/misc/irq_sandbox_test.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include #include #include diff --git a/drivers/misc/jz4780_efuse.c b/drivers/misc/jz4780_efuse.c index 5c92de26ec5fc6c49c2fcb58e9f472294396eeb7..1fba3271db6120833dbc71dcb326c5ada860240b 100644 --- a/drivers/misc/jz4780_efuse.c +++ b/drivers/misc/jz4780_efuse.c @@ -6,6 +6,7 @@ * Author: Alex Smith */ +#include #include #include #include diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 87471cc3b16adb39f485ca29121be24a4f7edc4b..0d29eff1ac08af8500eb479027fb9b21808f2fdb 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c index fa3d656562206c909096e8e87148976a6fe93210..f6ac18bdc757745ee19b7d63747b755bdb4f8a3a 100644 --- a/drivers/misc/k3_esm.c +++ b/drivers/misc/k3_esm.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c index 8cb6e999bed1d0d968e76c107be380a62926beb4..5351c7ed34fd0ac8686d36ad36460bb56848b168 100644 --- a/drivers/misc/ls2_sfp.c +++ b/drivers/misc/ls2_sfp.c @@ -12,6 +12,7 @@ */ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/drivers/misc/microchip_flexcom.c b/drivers/misc/microchip_flexcom.c index c5ddecac755171e5e9b25d4a69855b5a0fade377..e0a6f2d38801e05ef39e5d590f3647d8137dc871 100644 --- a/drivers/misc/microchip_flexcom.c +++ b/drivers/misc/microchip_flexcom.c @@ -4,6 +4,7 @@ * Author: Eugen Hristev */ +#include #include #include #include diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 1389e146b61281b976d87c99eb4e530056de7811..cfe9d562fa0d2fc5a9ca6f85926fcbfc499506ad 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c index 2473419df2a39e23f82ade8e0b59674a8110ecc7..31cde2dbac07eb0c55a400ca12e303712edc3dec 100644 --- a/drivers/misc/misc_sandbox.c +++ b/drivers/misc/misc_sandbox.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include diff --git a/drivers/misc/mpc83xx_serdes.c b/drivers/misc/mpc83xx_serdes.c index cf9aa9b35b337ca390c68cee6c54cad705a84074..93c87e998c4f3923213d60e3096bee1ef6cd7a40 100644 --- a/drivers/misc/mpc83xx_serdes.c +++ b/drivers/misc/mpc83xx_serdes.c @@ -9,6 +9,7 @@ * Copyright (C) 2008 MontaVista Software, Inc. */ +#include #include #include #include diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index d1674caa138cf0e56bfe188ee54c351be1d251e0..8ee18f29d9be04a50b54c10b9f5a5eff69696008 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -11,6 +11,7 @@ * Copyright (C) 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c index 6432c62dac34b9b9289164fd8ebc081ac1ffe05c..facc720c8ef20395bbef0940e1f43d40fd70a8f4 100644 --- a/drivers/misc/mxs_ocotp.c +++ b/drivers/misc/mxs_ocotp.c @@ -11,6 +11,7 @@ * etc.) which would make common driver an ifdef nightmare :-( */ +#include #include #include #include diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c index 58bab888c3c862456948c177c5cbdc2fdb316972..79f57f57d89caad34260ce07a15685baee902d72 100644 --- a/drivers/misc/npcm_host_intf.c +++ b/drivers/misc/npcm_host_intf.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c index adb6135291dcf0fe56011b9ac169b623be2fc795..08029724c04097e3659077f9645c36641c4ce60b 100644 --- a/drivers/misc/npcm_otp.c +++ b/drivers/misc/npcm_otp.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/misc/nuvoton_nct6102d.c b/drivers/misc/nuvoton_nct6102d.c index a3ca037d25f7d97da49dca8538bcff64195cb999..daf5019d0170f3234ae110777596b108ae00dd5f 100644 --- a/drivers/misc/nuvoton_nct6102d.c +++ b/drivers/misc/nuvoton_nct6102d.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/misc/nvmem.c b/drivers/misc/nvmem.c index d0cb0a35b816246133410e60da2c66469b696eb0..5a2bd1f9f72c8c2bf67b61eac55a33e207fc16ea 100644 --- a/drivers/misc/nvmem.c +++ b/drivers/misc/nvmem.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Sean Anderson */ +#include #include #include #include diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index 016c807337821d4d62a3e4549a4f25b3fba71a8a..f24857a1515e27201ab9a642498864a43d84e701 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_P2SB +#include #include #include #include diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c index 3dac6bd82e30d3416e287587d750eb740c76645e..51f87161d5b796c496aae44249760832f4142b85 100644 --- a/drivers/misc/p2sb_emul.c +++ b/drivers/misc/p2sb_emul.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/drivers/misc/p2sb_sandbox.c b/drivers/misc/p2sb_sandbox.c index 9f3cd14958b845ad640ef73bde960e87b468c126..d80bca22a6b2fce145b34a5512d65e964b0ff74b 100644 --- a/drivers/misc/p2sb_sandbox.c +++ b/drivers/misc/p2sb_sandbox.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_P2SB +#include #include #include #include diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c index 040d0d5cf48cc0016de01b25cbfeeeb3ac347069..cdc4390f8155dcefcf1788006281b9e4904e1f34 100644 --- a/drivers/misc/pca9551_led.c +++ b/drivers/misc/pca9551_led.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Stefan Roese */ +#include #include #include #include diff --git a/drivers/misc/pwrseq-uclass.c b/drivers/misc/pwrseq-uclass.c index bddc3c3368572eed3f48608765f5d0276125c9f2..a0f24e1bf3a967bc544871e54a8d0d8b6cb3ddd4 100644 --- a/drivers/misc/pwrseq-uclass.c +++ b/drivers/misc/pwrseq-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_PWRSEQ +#include #include #include diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 0e002ac25f48180d103ecbd982062a0dd3e54dd7..db98619fdf53c9b74dc3d0c3c739c4fdd974d30d 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_QFW +#include #include #include #include diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c index c7430147718a88c32a54424fe720b228e9aeeeda..2f96b79ea407dd56ba1bc2ddcd4857f9168273ab 100644 --- a/drivers/misc/rockchip-efuse.c +++ b/drivers/misc/rockchip-efuse.c @@ -6,6 +6,7 @@ * Written by Philipp Tomsich */ +#include #include #include #include diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 2123c31038fce15dd10090773883d2cd2fc59629..4f757083a1b6d9e8152a470381022c2b2f31d4f3 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/misc/sandbox_adder.c b/drivers/misc/sandbox_adder.c index de1c635758209d70f6dd693a9fb27e24e168f32f..3ea33e46e9f23d21da6319ba671e48ea52605a30 100644 --- a/drivers/misc/sandbox_adder.c +++ b/drivers/misc/sandbox_adder.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include diff --git a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c index 7fbcd3799e524f4e32e1496e6b8e774fe977c2d4..a624a358802c7bfe1ffd7d85eb05e3afcc45ef9e 100644 --- a/drivers/misc/sifive-otp.c +++ b/drivers/misc/sifive-otp.c @@ -17,6 +17,7 @@ * Right now first 1KiB is used to store only serial number. */ +#include #include #include #include diff --git a/drivers/misc/sl28cpld.c b/drivers/misc/sl28cpld.c index 1c61b005af3a71569027e8bd113f1e636e7c5548..01ef1c6178fcca9c4d419528ad1486a1084f8cfe 100644 --- a/drivers/misc/sl28cpld.c +++ b/drivers/misc/sl28cpld.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Michael Walle */ +#include #include #include diff --git a/drivers/misc/smsc_lpc47m.c b/drivers/misc/smsc_lpc47m.c index 1b15907b09331d1c40994409cfb512c8afad75b9..bda064f1365b39b01ca2bdcf3f39b08c36f2220c 100644 --- a/drivers/misc/smsc_lpc47m.c +++ b/drivers/misc/smsc_lpc47m.c @@ -3,6 +3,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include diff --git a/drivers/misc/smsc_sio1007.c b/drivers/misc/smsc_sio1007.c index 6d99aa61d91d630852749bc1808737f40d1deaea..3b7b1c8bcf2ac05f186f753cb33e937f3fa30b45 100644 --- a/drivers/misc/smsc_sio1007.c +++ b/drivers/misc/smsc_sio1007.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/drivers/misc/spltest_sandbox.c b/drivers/misc/spltest_sandbox.c index 3011a22927135b6a7a2c49979d7c2f15301b8ec2..6b9701a06aee68aec7b981fdba3971831f421941 100644 --- a/drivers/misc/spltest_sandbox.c +++ b/drivers/misc/spltest_sandbox.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c index 3b1baa4f840b1ba7fad71472f0ff7ada373fa418..a6e9c03a02ecda7e36fd3d195d3504e34f49b8ae 100644 --- a/drivers/misc/status_led.c +++ b/drivers/misc/status_led.c @@ -4,8 +4,8 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include -#include /* * The purpose of this code is to signal the operational status of a diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 0dd827e1dd0ea9aff6ebded2a223b0e86c0c778e..c1e5428a6b815eb2d5fb9a217ca8034aa466d7d3 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_NOP +#include #include #include #include diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 34be6c28c1923984f946d95d9f12ac6cf30ff997..9fd6c367dc61bc4d58e5742f8cebb09648484131 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index d4a5620c62c11b4f2069b18a68886803ac2f6c14..ee5c12bd0a426cb2e68deb3f89c93b33c309a060 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/misc/syscon_sandbox.c b/drivers/misc/syscon_sandbox.c index 6adb4154c25bf3af360b0bb3ac1acd39b394b2bb..d5cef188d74238dc8aec6475f7302a685af75653 100644 --- a/drivers/misc/syscon_sandbox.c +++ b/drivers/misc/syscon_sandbox.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c index a1585b818677849665e7a768b6dd04d79817d4a0..fecac9c4d902cf07cc120f6b87ca8acafd7629b3 100644 --- a/drivers/misc/tegra186_bpmp.c +++ b/drivers/misc/tegra186_bpmp.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/misc/tegra_car.c b/drivers/misc/tegra_car.c index 497ec18564cca87a324954ada3d399158fdf899a..0ddbb3c619b22e0a3cd963f0c624cf8daa6d2145 100644 --- a/drivers/misc/tegra_car.c +++ b/drivers/misc/tegra_car.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/misc/test_drv.c b/drivers/misc/test_drv.c index 9b1e357a1397d1b760b733c5eaaab90e545d1289..927618256f0ac88d73cf6e1955a8412a7101a2d0 100644 --- a/drivers/misc/test_drv.c +++ b/drivers/misc/test_drv.c @@ -3,6 +3,7 @@ * Copyright (c) 2014 Google, Inc */ +#include #include #include #include diff --git a/drivers/misc/turris_omnia_mcu.c b/drivers/misc/turris_omnia_mcu.c index be77acbd16529d34fdbfa869bfaed849dcc5ca95..6b2f17c0002d89893f1cb5e483d2535d1b8415c4 100644 --- a/drivers/misc/turris_omnia_mcu.c +++ b/drivers/misc/turris_omnia_mcu.c @@ -4,6 +4,7 @@ * Copyright (C) 2024 Marek Behún */ +#include #include #include #include diff --git a/drivers/misc/usb251xb.c b/drivers/misc/usb251xb.c index daba2c2d6835d26993db40fab40746d9f8cce249..92e92ba5e6240ddd4f58e1874e97b9b4209c74aa 100644 --- a/drivers/misc/usb251xb.c +++ b/drivers/misc/usb251xb.c @@ -10,6 +10,7 @@ * https://patchwork.kernel.org/patch/9257715/ */ +#include #include #include #include diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c index e7655ceff74cad28ee947c89da119c7d82210347..99aad1412ae733c24dbdf796fc37108c0313563b 100644 --- a/drivers/misc/vexpress_config.c +++ b/drivers/misc/vexpress_config.c @@ -4,6 +4,7 @@ * Author: Liviu Dudau * */ +#include #include #include #include diff --git a/drivers/misc/winbond_w83627.c b/drivers/misc/winbond_w83627.c index 87b9043e65c449aa641fe01cf131359eaff64a15..3838b3f74f40738bec07dd601b1512964413215f 100644 --- a/drivers/misc/winbond_w83627.c +++ b/drivers/misc/winbond_w83627.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index d0944793c92d3fd7d3be063ab754d6fb3ec3b232..549634891a36d9a3a56bf916efb283cdf91284d1 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -147,16 +147,9 @@ config SPL_MMC_IO_VOLTAGE support. For eMMC this not mandatory, but not enabling this option may prevent the driver of using the faster modes. -config MMC_SUPPORTS_TUNING - bool - -config SPL_MMC_SUPPORTS_TUNING - bool - config MMC_UHS_SUPPORT bool "enable UHS support" depends on MMC_IO_VOLTAGE - select MMC_SUPPORTS_TUNING help The Ultra High Speed (UHS) bus is available on some SDHC and SDXC cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus @@ -165,7 +158,6 @@ config MMC_UHS_SUPPORT config SPL_MMC_UHS_SUPPORT bool "enable UHS support in SPL" depends on SPL_MMC_IO_VOLTAGE - select SPL_MMC_SUPPORTS_TUNING help The Ultra High Speed (UHS) bus is available on some SDHC and SDXC cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus @@ -201,7 +193,6 @@ config SPL_MMC_HS400_SUPPORT config MMC_HS200_SUPPORT bool "enable HS200 support" - select MMC_SUPPORTS_TUNING help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -209,7 +200,6 @@ config MMC_HS200_SUPPORT config SPL_MMC_HS200_SUPPORT bool "enable HS200 support in SPL" depends on SPL_MMC - select SPL_MMC_SUPPORTS_TUNING help The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO. @@ -357,7 +347,6 @@ config MMC_OCTEONTX bool "Marvell Octeon Multimedia Card Interface support" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) depends on DM_MMC - select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2 help This selects the Octeon Multimedia card Interface. If you have an OcteonTX/TX2 or MIPS Octeon board with a diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 48fac7a11b483aa61736b4db4f52cba63b31b54d..fadab7d40bb795232f86586fe4352aa539bdc754 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -396,7 +397,7 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) writeb(val, host->ioaddr + reg); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING #define ITAPDLY_LENGTH 32 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) @@ -499,7 +500,7 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) } #endif const struct sdhci_ops am654_sdhci_ops = { -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .platform_execute_tuning = am654_sdhci_execute_tuning, #endif .deferred_probe = am654_sdhci_deferred_probe, @@ -559,7 +560,7 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) } const struct sdhci_ops j721e_4bit_sdhci_ops = { -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .platform_execute_tuning = am654_sdhci_execute_tuning, #endif .deferred_probe = am654_sdhci_deferred_probe, diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index f00b0ff0dc95354aaaaf7bbe4ab66fe4ecdbaf34..cecc7ad783d093899807345bf9d64df20b109185 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -11,6 +11,7 @@ /* #define DEBUG */ +#include "common.h" #include #include #include diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c index 87a6f66ebb370b5e3b9caaf9d9be8a37328f885e..c9626c6beb8f697180cd4758aa33a2afd6141954 100644 --- a/drivers/mmc/aspeed_sdhci.c +++ b/drivers/mmc/aspeed_sdhci.c @@ -4,6 +4,7 @@ * Eddie James */ +#include #include #include #include diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 0b265196f025ea147af717ab151e09b760c2a750..d92bad97b71e9c2964ca969a1b54704e3c8bfca4 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -4,6 +4,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 598a51d914a97ccaa7e48b0ac476c6c746ecf2f1..5e48394fd0fb4aa277c61606faaa97415defae28 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -36,6 +36,7 @@ * Inspired by sdhci-pci.c, by Pierre Ossman */ +#include #include #include #include diff --git a/drivers/mmc/bcm2835_sdhost.c b/drivers/mmc/bcm2835_sdhost.c index 720127468d373499d04d4f27aeee4d573a8d8533..5c23c03d10d750beacba23f0ed8a9939c65bb269 100644 --- a/drivers/mmc/bcm2835_sdhost.c +++ b/drivers/mmc/bcm2835_sdhost.c @@ -30,6 +30,7 @@ * sdhci.c and sdhci-pci.c by Pierre Ossman */ #include +#include #include #include #include diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c index 7bddbebb1622b03f1b2b30ea8a53f416088ce6b7..49846adcf5476e19408986d24b2d0ebf53fc3738 100644 --- a/drivers/mmc/bcmstb_sdhci.c +++ b/drivers/mmc/bcmstb_sdhci.c @@ -6,6 +6,7 @@ * Author: Thomas Fitzsimmons */ +#include #include #include #include diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 54a2ba4795e3bb3b96187ea6df85905c75927364..a17ed8c11cbef70ca80c34babee54abc465fa58d 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -4,6 +4,7 @@ * Arthur Li */ +#include #include #include #include diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index 5107fcd836259285da36f93dbecff24d9b7ba888..3a3d23aec00a9e384db7a3ecc55666592adf54e8 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index e6107c770fe3069be59112f41e41cdd0b0066cd3..e1036641452ab4f3f072dc7bb8212c8968cf3a0d 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index a51f762988daa47b4bd1b0074316a973439131ed..2f849c43b129bc42af40fd56d3115f4e7958615f 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c index f47cf8485216e60bb5d9ff2b2becca0749116c94..3d587a464d5057c9d609c437ef77fb951ee98e66 100644 --- a/drivers/mmc/f_sdh30.c +++ b/drivers/mmc/f_sdh30.c @@ -5,6 +5,7 @@ * Copyright 2021 Socionext, Inc. */ +#include #include #include #include diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0c66980b6218bc8d02df32989fb5abbaa9b0b205..595d88bd56253f256a8bb1022f7feac6584e8ce7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -1101,7 +1102,7 @@ static int fsl_esdhc_reinit(struct udevice *dev) return esdhc_init_common(priv, &plat->mmc); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) { struct fsl_esdhc_plat *plat = dev_get_plat(dev); @@ -1174,7 +1175,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = fsl_esdhc_execute_tuning, #endif .reinit = fsl_esdhc_reinit, diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index a9b8d7dd67f33d43e09e008f4d55ff5293a51ac0..b74c014002058f84d10823f87ae1049c96ecc06e 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -634,7 +635,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) priv->clock = clock; } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static int esdhc_change_pinstate(struct udevice *dev) { struct fsl_esdhc_priv *priv = dev_get_priv(dev); @@ -912,7 +913,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) int ret __maybe_unused; u32 clock; -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING /* * call esdhc_set_timing() before update the clock rate, * This is because current we support DDR and SDR mode, @@ -950,7 +951,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING /* * For HS400/HS400ES mode, make sure set the strobe dll in the * target clock rate. So call esdhc_set_strobe_dll() after the @@ -1617,7 +1618,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = fsl_esdhc_execute_tuning, #endif #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 1a11258be4defa6d1ea98131166062b4fcb4bceb..6d7c0cff22a5fd6794ceafc1ea6fd775e788cf7e 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 11e44264e47daa2448a8981998cf8390794f6a17..cabb747fbbdb5f0e37403babf158742621483322 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -9,6 +9,7 @@ * Author: Rick Chen (rick@andestech.com) */ +#include #include #include #include diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 6a531fa096152264740aed9524cabb47fc782809..3ee99558f6f9f50c56162c8e28084fb85ded1736 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -8,7 +8,7 @@ * Copyright (C) 2004-2006 Atmel Corporation */ -#include +#include #include #include #include diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index c68a9157bfccf16e642cb237dc57e58ab59173dc..dc0210402bd21fad9c8a17ca2eb67d959b01be74 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -4,6 +4,7 @@ * peter.griffin */ +#include #include #include #include diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c index 7ab74ff117a697fe1d89b0acb7c7c66f54d6eafe..11d86ad658f98e84ad4eaf3242c196002dce95b1 100644 --- a/drivers/mmc/iproc_sdhci.c +++ b/drivers/mmc/iproc_sdhci.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c index fc10bb256a4df53107d54fe89f060e8f37dd72f1..61e48ee0f62d4fc022ef6701797cf1e387f85aed 100644 --- a/drivers/mmc/jz_mmc.c +++ b/drivers/mmc/jz_mmc.c @@ -6,6 +6,7 @@ * Author: Paul Burton */ +#include #include #include #include diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c index 83f141226325d78561e0cb726c2510fa19ffddbb..2bbe673b91299d0d6d61b975cd43c44eb9e97f2f 100644 --- a/drivers/mmc/kona_sdhci.c +++ b/drivers/mmc/kona_sdhci.c @@ -3,6 +3,7 @@ * Copyright 2013 Broadcom Corporation. */ +#include #include #include #include diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 5852b24c6d2a5a9d1b1e8a62f8c0ec325b339182..0825c0a2a8382b16ea82396e02ce4c5646867359 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Carlo Caione */ +#include #include #include #include diff --git a/drivers/mmc/mmc-pwrseq.c b/drivers/mmc/mmc-pwrseq.c index a1c9624a2225528e860bb1fb268dee2362493018..2539f61323d13d6320f054dd34467432b3129df7 100644 --- a/drivers/mmc/mmc-pwrseq.c +++ b/drivers/mmc/mmc-pwrseq.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index da6a39b7d99074e697be579b8cfe76f29d8781ae..24170c59ecc1b3aeb3e92d022ad051f6f2dbaf18 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_MMC +#include #include #include #include @@ -111,7 +112,7 @@ int mmc_getcd(struct mmc *mmc) return dm_mmc_get_cd(mmc->dev); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static int dm_mmc_execute_tuning(struct udevice *dev, uint opcode) { struct dm_mmc_ops *ops = mmc_get_ops(dev); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b18dc331f785a08d9080eef3325c52aeab6e0f4e..7b068c71ff37871c309729faa573629b73635898 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "mmc_private.h" @@ -330,7 +329,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len) MMC_QUIRK_RETRY_SET_BLOCKLEN, 4); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static const u8 tuning_blk_pattern_4bit[] = { 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, @@ -1622,7 +1621,7 @@ static inline int bus_width(uint cap) } #if !CONFIG_IS_ENABLED(DM_MMC) -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static int mmc_execute_tuning(struct mmc *mmc, uint opcode) { return -ENOTSUPP; @@ -1703,7 +1702,7 @@ void mmc_dump_capabilities(const char *text, uint caps) struct mode_width_tuning { enum bus_mode mode; uint widths; -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING uint tuning; #endif }; @@ -1744,7 +1743,7 @@ static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) #if !CONFIG_IS_ENABLED(MMC_TINY) static const struct mode_width_tuning sd_modes_by_pref[] = { #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING { .mode = UHS_SDR104, .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, @@ -1847,7 +1846,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING /* execute tuning if needed */ if (mwt->tuning && !mmc_host_is_spi(mmc)) { err = mmc_execute_tuning(mmc, @@ -2225,7 +2224,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) mmc_select_mode(mmc, mwt->mode); mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING /* execute tuning if needed */ if (mwt->tuning) { diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c index 367c957b5181617a2939721e8d967c981cc8a618..0a74b1fb776ac01aff8f93bec27d266470b29d1b 100644 --- a/drivers/mmc/mmc_boot.c +++ b/drivers/mmc/mmc_boot.c @@ -4,6 +4,7 @@ * Written by Amar */ +#include #include #include #include "mmc_private.h" diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c index 5a1688b75d09f08e38590ca4937d71d966db652b..55ecead2ddf9a32fad67e27d7199c986eec1f043 100644 --- a/drivers/mmc/mmc_bootdev.c +++ b/drivers/mmc/mmc_bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index a87d2276c1b851365b878fd8a49dacf47f6cff4d..a101ee43fde506d27a34c655b5025f4614e60376 100644 --- a/drivers/mmc/mmc_legacy.c +++ b/drivers/mmc/mmc_legacy.c @@ -5,6 +5,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 675e642efd085f6c79fa58e9d4e20a7f60f405da..bcea800e5f616b1983bddd9cdcb383f5e65250b4 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -6,6 +6,7 @@ * * Licensed under the GPL-2 or later. */ +#include #include #include #include diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index c023d15e52a8df45a36207efd4ebca1d8e6bd6a4..a6f93380dd091f652e5fcdc003aceb01bd08d082 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 4ce0de6c47d869f7b4f409b6e27b39903111784e..5e9d66526a838a79d6cd56122628ffb1c2cf5008 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -7,6 +7,7 @@ * Based on Linux driver */ +#include #include #include #include diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 3a9258255a784fc00f0f20741b54b475832e4f69..296aaee73318c4ef19cd42b88aaeb491aba64479 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -1010,7 +1011,7 @@ static int msdc_ops_get_wp(struct udevice *dev) #endif } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static u32 test_delay_bit(u32 delay, u32 bit) { bit %= PAD_DELAY_MAX; @@ -1759,7 +1760,7 @@ static const struct dm_mmc_ops msdc_ops = { .set_ios = msdc_ops_set_ios, .get_cd = msdc_ops_get_cd, .get_wp = msdc_ops_get_wp, -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = msdc_execute_tuning, #endif .wait_dat0 = msdc_ops_wait_dat0, diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 2da5334c21f13c1ad93b4154c6dd4c637868cbf0..dbdd671c88bcc307029c616bac3f3f22fddca16d 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -3,6 +3,7 @@ * Marvell SD Host Controller Interface */ +#include #include #include #include diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd1485183b5989ce6200f7cc11ac066f5..fea55c61ed7daac57c2da489dec7d173907ac360 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -7,6 +7,7 @@ * Written-by: Maen Suleiman, Gerald Kerma */ +#include #include #include #include diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 1acea6f820b45a7b1e72f0d70fab702e54043aa0..0057273a2a767ef177dd884b4254479186fd5869 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 95390a5be7e59f17bb1641251784902f41e7e932..35a8e21058edaf607e6dd54fa43bd2a1d4789c88 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -20,6 +20,7 @@ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net */ +#include #include #include #include diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c index 2e1ce54c7d50b4d73d5a5efcb0ae0f3ccf515f69..2723e4887cf701d9961e627b45957b2b6743f478 100644 --- a/drivers/mmc/nexell_dw_mmc.c +++ b/drivers/mmc/nexell_dw_mmc.c @@ -6,6 +6,7 @@ * (C) Copyright 2019 Stefan Bosch */ +#include #include #include #include diff --git a/drivers/mmc/npcm_sdhci.c b/drivers/mmc/npcm_sdhci.c index dff4732ea06f14d4719922db4b1e6990bad1638d..d63521d6855ffb49995f7d22e58d864f83c13ee3 100644 --- a/drivers/mmc/npcm_sdhci.c +++ b/drivers/mmc/npcm_sdhci.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index 3b5e122173254cf5f373cb3eb53d47893cb0cac1..7f9c4f4d36d4aa727baf7fc986e682801eb59f7f 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -794,7 +794,7 @@ octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd, u8 desired_ctype = 0; if (IS_MMC(mmc)) { -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) { if (cmd->resp_type == MMC_RSP_R1) cr.rtype_xor = 1; @@ -1631,7 +1631,7 @@ static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data); } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp) { struct mmc_cmd cmd; @@ -2421,12 +2421,12 @@ static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode) return 0; } -#else /* CONFIG_MMC_SUPPORTS_TUNING */ +#else /* MMC_SUPPORTS_TUNING */ static void octeontx_mmc_set_emm_timing(struct mmc *mmc, union mio_emm_timing emm_timing) { } -#endif /* CONFIG_MMC_SUPPORTS_TUNING */ +#endif /* MMC_SUPPORTS_TUNING */ /** * Calculate the clock period with rounding up @@ -2573,7 +2573,7 @@ static int octeontx_mmc_set_ios(struct udevice *dev) err = octeontx_mmc_configure_delay(mmc); -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) { debug("%s: Tuning HS400 mode\n", __func__); err = octeontx_tune_hs400(mmc); @@ -3776,7 +3776,7 @@ static const struct dm_mmc_ops octeontx_hsmmc_ops = { .set_ios = octeontx_mmc_set_ios, .get_cd = octeontx_mmc_get_cd, .get_wp = octeontx_mmc_get_wp, -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = octeontx_mmc_execute_tuning, #endif }; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 2b7f9fc9a205f277a07bfd5a45d0b0b761daa160..99f21b2c546ae4d827c5d49247537056e5a39cb9 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include @@ -576,7 +577,7 @@ static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) return val; } -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING static void omap_hsmmc_disable_tuning(struct mmc *mmc) { struct hsmmc *mmc_base; @@ -1517,7 +1518,7 @@ static const struct dm_mmc_ops omap_hsmmc_ops = { .get_cd = omap_hsmmc_getcd, .get_wp = omap_hsmmc_getwp, #endif -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = omap_hsmmc_execute_tuning, #endif .wait_dat0 = omap_hsmmc_wait_dat0, diff --git a/drivers/mmc/owl_mmc.c b/drivers/mmc/owl_mmc.c index bd4906f58e7460dae300c4f299820a95dc8951e0..e84171a661a71b925c9204ee6f7b65b893138636 100644 --- a/drivers/mmc/owl_mmc.c +++ b/drivers/mmc/owl_mmc.c @@ -11,6 +11,7 @@ * channel, and those special bits used in this driver is picked from vendor * source exclusively for MMC/SD. */ +#include #include #include #include diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index d446c55f72b269b4096b6b7cfedef556ff4a020b..4d163ccba04192550405475af25bc4b5c095a30e 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Bin Meng */ +#include #include #include #include diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c index fed1f8416088ba8b1519d222b23c26a8717b2e1b..a330bbf8cbe2df2da27f3131a893938f4bceaad2 100644 --- a/drivers/mmc/piton_mmc.c +++ b/drivers/mmc/piton_mmc.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 1a10b7057a47ce65adeab0aa7f98539c6bc9273c..ad4529d6afa8a027dfb1abe8497a49aee48a4174 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 35667b86b50b2c8829b280783b5970a9c204ddf9..c889c7bc9855fab4cf35811a7ceea2b351a9863d 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -5,6 +5,7 @@ * Rockchip SD Host Controller Interface */ +#include #include #include #include diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 0658ce22cf132c2dcca506631374797f66b30dd4..b68d98573c9a5c0441b406548035494d3b15a138 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 80dbb38c9b36ee927497fafdb23354e9f755b524..3b74feae68c76bb20a18ed5657356f9759ba212c 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c index a24520f2e78c91e3e13ef6d5c4413836a7c17aba..0ba7940a4dbfc41308182ad2023e1c9b82f748a7 100644 --- a/drivers/mmc/sandbox_mmc.c +++ b/drivers/mmc/sandbox_mmc.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c index fdb189d71a640dad7b45112f633a7926c7795df8..283ba956deb9514130a7f60f8ac40a6ce8b2e86d 100644 --- a/drivers/mmc/sdhci-adma.c +++ b/drivers/mmc/sdhci-adma.c @@ -3,6 +3,7 @@ * SDHCI ADMA2 helper functions. */ +#include #include #include #include diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 07ec35a04635a3cef6a97b3cef9b9ab8a7f5103e..c0a9f60b1496fe6a9af6502c087920cc839d444c 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include @@ -273,7 +274,7 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ops = &sdhci_cdns_ops; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; sdhci_cdns_mmc_ops = sdhci_ops; -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning; #endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 560b7e889c779d677d6f598f8b1f87019c0de79e..af654ea8d13c26d62abc05d860802998de4f8ba3 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -7,6 +7,7 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ +#include #include #include #include @@ -14,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -351,7 +351,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, return -ECOMM; } -#if defined(CONFIG_DM_MMC) && CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING) static int sdhci_execute_tuning(struct udevice *dev, uint opcode) { int err; @@ -848,7 +848,7 @@ const struct dm_mmc_ops sdhci_ops = { .set_ios = sdhci_set_ios, .get_cd = sdhci_get_cd, .deferred_probe = sdhci_deferred_probe, -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING .execute_tuning = sdhci_execute_tuning, #endif .wait_dat0 = sdhci_wait_dat0, diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 06a30d5efb811c9cf326bd29e9bf1e813fc0d001..76dc1c68b821d30c3c7764763148ace565ff94d2 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 9bdbe5070b1dde414de521591e51360af8bd526f..0134399e3934c5865b4473d038363f45d4ba4b18 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -7,6 +7,7 @@ * Author: Eugeniy Paltsev */ +#include #include #include #include diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index f738019b835750270a05ae3b5c2e85624d7d9043..387cb8b6b50a1cbac0b0bfe29d8c601a75af032c 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -3,6 +3,7 @@ * (C) Copyright 2013 Altera Corporation */ +#include #include #include #include diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 91018b7e21af2beef4443a6a1d382f33016eb21e..23a1dd43c9b277df31d777b21f8302445cd036ae 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 9483fb57daf8a91a15c802c8f30702bfaed475b3..39ae79ba129308a5e24620c154ec5a4569599462 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_MMC +#include #include #include #include diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 0b56d1405bee54044f671e10bd3e313584cbff9a..714706d2411b851d663eb665e967ed0f59e0c6a3 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -13,6 +13,7 @@ * proper DM_MMC implementation at the end. */ +#include #include #include #include diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c index ae65c310b685024dcaa01e65ecf63c0b671c0194..11564273324386b65d161e3b3866a85ad09bd7fd 100644 --- a/drivers/mmc/tangier_sdhci.c +++ b/drivers/mmc/tangier_sdhci.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 5ed7f01d3f361daa297280a6e468e49aa019ef1b..c01fb3d01657f639819d741c316481b30c0488e4 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0b396122b464b84a84a7b6e4377e62814d805164..719c4830bc30bad9fc4fa1f762cfeb1f44404474 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 5b3650d52eead9124f3a5169288a09a252e97ddd..8cde4308aaede48ce195faaaf5c2914702e76831 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index 0e4902fab77cad5501a9b74b8e48683e7b3b2f01..27dbe0404e045adfb87a45508ff44fa7f1796df1 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -14,6 +14,7 @@ * Stefan Roese */ +#include #include #include #include diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 898be5a0913a89d700e540c6220f680a13673778..935540d17194c755b3bd0ef78cb0e0b78c7174c6 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index c26615821c80926fbee5d01f688199c1e16cd85c..d31391f36a47161e848c0215c2e96407669903c8 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Thomas Chou */ +#include #include #include #include diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index a7826e81c177394f74c15bb2c8e393d92603f6bc..8ade7949a68e0010b37af641c20d85c4f95b7b38 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -16,7 +16,7 @@ /* The DEBUG define must be before common to enable debugging */ /* #define DEBUG */ -#include +#include #include #include #include @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index b14d4773931baf5d268374d1eb28c29883e00075..bf4473ba9e8308e796f3b8f7f4d4cd3281c9ac10 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -5,6 +5,7 @@ * Written by: Piotr Ziecik */ +#include #include #include #include diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c index 599beda30d5550517018061e3e4a2f90f1e20c18..8161087b50c0e04942d386c6d1bc5dda784c9821 100644 --- a/drivers/mtd/hbmc-am654.c +++ b/drivers/mtd/hbmc-am654.c @@ -3,6 +3,7 @@ // Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ // Author: Vignesh Raghavendra +#include #include #include #include diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index a832f348f22df9b9021dce49a928874b1f9f0d79..859c7fd4ec246a97600f0599bf7a51cce45bc05a 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -11,6 +11,7 @@ /* The DEBUG define must be before common to enable debugging */ /*#define DEBUG*/ +#include #include #include #include diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c index 720bd824c4d7406f444cb3f0f413ca8b0923f0b2..0743fe7af9fd306c50fc2860f3f710e354535947 100644 --- a/drivers/mtd/mtd-uclass.c +++ b/drivers/mtd/mtd-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_MTD +#include #include #include #include diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 69cb3b51f9229e3721411b90b5da2dbe19d7bc96..14ce726b10d8d2b41ab958cb6274ae139978cc49 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -3,6 +3,7 @@ * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ +#include #include #include #include diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index be1d19b4ffa5982efc2da1631eddb493b7fe5efe..4886392a1cfaa59f430e2ca51f32275b9021cb27 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -19,6 +19,7 @@ #include #endif +#include #include #include #include diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c index 4ff0999f62a125499838f4ed6781f59770fd6f10..972aec6e26665537e5ea542c620764f2cc5eac43 100644 --- a/drivers/mtd/nand/bbt.c +++ b/drivers/mtd/nand/bbt.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "nand-bbt: " fmt +#include #include #include #include diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 472ad0bdefb1c9b6d14d2206db4015cb647f4016..f6d9c584f786eb998d501fdb2e83483f89e8c017 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "nand: " fmt +#include #include #ifndef __UBOOT__ #include diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 64d8ce0965ad16147a1fa21c2bc29f7b2a0ed69f..6831af98b73b46e8971ee26938945db8bcd8f4b8 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -9,7 +9,7 @@ * Stefan Roese, DENX Software Engineering, sr@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 4f013efafb3657629e4caee8995b28067c69a44f..ffcd963b3dacaa303cf0924fc42a3c5bbd3fd79a 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -5,6 +5,7 @@ * Copyright (C) 2014 - 2015 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 4dbf7b47135c69257cbeb2ce549bf8312548f296..6d94e7af38e9af1ca002ea142e03c812134aa64d 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -10,7 +10,7 @@ * (C) Copyright 2012 ATMEL, Hong Xu */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c index 3f59fbbbb8f147bd01c636cf1a386d1a3b0b4017..4e6d99fd3ca461c1b4fc17bddff1018742e447c3 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c index d54de0b3ecceb6e7424aaf99c8d525d6605f2fc3..6164989b93782afacaf0f68510a52ea3938ed63f 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c index a101222a28fa494be8523cd6cd4182eaabd8a45e..feae66ef25a6eab2442a2d642596fb588ff97f97 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c index 385642d0c091fb2855c95d61997ab123af59b561..dbd85af7079d510eb41da832be27f4114f4b1cca 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c index 407898ddae6e2b0f5700da98e2cf7afecf719e53..ef3649688c66f9977f1ac3f22bc28a64ef3f526d 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6838_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c index 564c678c9ef2427aefda6ddb0b341505200af230..027fdd37da3b6b4827d73f23554e5261166fd912 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index b7bf7cc0893d2e99bcbf1a15952044022f5c761a..efbf9a3120a43f75a13c4bb8e51fc3809f7d9fa8 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c index b3b3df5c042e4ec95d9e5f881b335ee1d0731722..a6acf556bcc75d24c8dd92f73d3a7d8fbb038b76 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_compat.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c index 430d6c9385381a2037545e6f9e2f2368358cb3f4..69711d98ce1b24df075faa826fad13132a7650c8 100644 --- a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Broadcom Corporation */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/cortina_nand.c b/drivers/mtd/nand/raw/cortina_nand.c index 06918a46e93ffed0eacc0313ff3decd3b451c1aa..b7be6602f7cc386570c52935b14bcfa69e430599 100644 --- a/drivers/mtd/nand/raw/cortina_nand.c +++ b/drivers/mtd/nand/raw/cortina_nand.c @@ -3,6 +3,7 @@ * Copyright (c) 2020, Cortina Access Inc.. */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index d4daf06b8de596da614c6cc5120e8da3f1b78a79..71bbb8231bfbbb960a28e5b5bb31dbfb0624c988 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -28,7 +28,7 @@ - */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index b2401116689a690e4658c9e3f06f8089f0bc0ae1..c827f80281c163bc39f69186cd71b237a3ec6629 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -5,6 +5,7 @@ * Copyright (C) 2009-2010, Intel Corporation and its suppliers. */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index b1e2c9d81617bc96a4b3b6dfb42b71a0e514d3ef..165a23312cb59cf6955804972eb2c8db4376635a 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -4,7 +4,7 @@ * Copyright (C) 2014-2015 Masahiro Yamada */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 157330cb287ae839226bef690f3d50567eff08ae..7853c3f74e2ab672664e69b1edeae92c9fbdd8e4 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -7,7 +7,7 @@ * Scott Wood */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index 17b8ef7ff4b995b93caffeaa614f258eb469cde9..26aaab08e893a6fa634f7e75b90f2b1aced66d41 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -9,7 +9,7 @@ * Author: Scott Wood */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 857d50ef9b09585d640808528b7c63584daaeb3c..1d7c1fddd3f64b7f3614b32e9aa0ca4b9cbf82a3 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -6,7 +6,7 @@ * Authors: Dipen Dudhat */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index c2ebee948707c684d5ede5f770b16f19e4747abe..69d26f1f79abb89700a740c4201e116664e8fa64 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -6,7 +6,7 @@ * Author: Dipen Dudhat */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/kirkwood_nand.c b/drivers/mtd/nand/raw/kirkwood_nand.c index cd182be268dca1ac65f50677adece44d0698afdb..621d2d232c88907a452540c8d7142c1a6897ed04 100644 --- a/drivers/mtd/nand/raw/kirkwood_nand.c +++ b/drivers/mtd/nand/raw/kirkwood_nand.c @@ -5,6 +5,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c index e9398eb4093e09565c8bd16930901e3743f63fd4..dfe73d64e46a1e324a28e5c033613fffd7e3a8f5 100644 --- a/drivers/mtd/nand/raw/kmeter1_nand.c +++ b/drivers/mtd/nand/raw/kmeter1_nand.c @@ -4,7 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index c89661badbf506a56e99ef6b83df7caffd350630..f8ae216d56c659a9c36db566c57bd6033b9bff11 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -19,7 +19,7 @@ * should not rely on the ECC validity. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 4d643bc64bc2ac089819b870626cf98c124e1d93..b21a0b9d293fe3cbf94df4fd4c0cdc34cc7dffab 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -10,7 +10,7 @@ * Author: Kevin Wells */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 0750b38f70810d4c2a81b5675442b881e51f31de..dbdc5b0bca1c56788243c6eba7e843ec40f882ab 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -5,7 +5,7 @@ * Copyright 2009 Ilya Yanok, */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index c5872848954edc78da662df177196e6895fd8c43..a855c9987f803e452b1c3469c2eeeb8e703c5a02 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -10,7 +10,7 @@ * Stefan Roese, DENX Software Engineering, sr at denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c index 0e54b5f69389549fbd951f81d6cbe667dd95270c..6abdc24bd30c097c9588ef3300812164b699d9e0 100644 --- a/drivers/mtd/nand/raw/mxic_nand.c +++ b/drivers/mtd/nand/raw/mxic_nand.c @@ -6,6 +6,7 @@ * Zhengxun Li */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 11b0247b2842b7b9c91f3826de8f58dedd7f3d36..fd65772af806691ab35047d94a487469831ba183 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -13,6 +13,7 @@ * Copyright 2017-2019 NXP */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index c8e064347adad0956b7b66ab396c210583bca501..f7d3f02f85a040cd0ceed0412276c295b8f2782d 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -4,6 +4,7 @@ * Copyright 2019 NXP * Author: Tim Harvey */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 36054492e18614c6bad97b3e384b11aa30485a1a..b591170346d04722c22c77a6131f9e5be77ef47b 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -5,7 +5,7 @@ * Ladislav Michl */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 18b95caffeffdccef76410bfcc78da23efc00ab6..688d17ba3c2fc837a06957e7f2dd4fe84e81b54e 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -28,6 +28,7 @@ */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_bbt.c b/drivers/mtd/nand/raw/nand_bbt.c index 1fb8535ab054f8802d5bdc5d9f10ca3faa83ae0f..cd451870a6f90732590c73caf4e6e1c77d980f09 100644 --- a/drivers/mtd/nand/raw/nand_bbt.c +++ b/drivers/mtd/nand/raw/nand_bbt.c @@ -57,6 +57,7 @@ * */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_bch.c b/drivers/mtd/nand/raw/nand_bch.c index f317cc26c9033744a449cebb0dc307dd8bcadf07..bb48ebbb96c76aa415ae05d324e0bded0373842a 100644 --- a/drivers/mtd/nand/raw/nand_bch.c +++ b/drivers/mtd/nand/raw/nand_bch.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_ecc.c b/drivers/mtd/nand/raw/nand_ecc.c index 0530ccb07226d1ed9d812a06ea5d1f34d3b53117..2bc329be1a3b010334aa651a588419e7ec75f67a 100644 --- a/drivers/mtd/nand/raw/nand_ecc.c +++ b/drivers/mtd/nand/raw/nand_ecc.c @@ -22,6 +22,7 @@ * this file might be covered by the GNU General Public License. */ +#include #include #include diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 4f46378ffe10634738257ebe36e2ff049d052d7d..be60d6d9d9952f7a8b728ebb331b587a832a5da6 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -6,6 +6,7 @@ * published by the Free Software Foundation. * */ +#include #include #include diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c index 87af675c13916f2157d9f7f593214a05ebd32cf6..7ac9bf4d1206dc2fdd1e8d7d6ac134bc93aa2352 100644 --- a/drivers/mtd/nand/raw/nand_spl_load.c +++ b/drivers/mtd/nand/raw/nand_spl_load.c @@ -4,7 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. */ -#include +#include #include /* diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index c0956ab0e491ef15b16dd7ae490f9edb8711c7be..80d6e0e1e4efa27f451a003af6b8bb32771021ac 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -4,7 +4,7 @@ * Stefan Roese, DENX Software Engineering, sr@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_timings.c b/drivers/mtd/nand/raw/nand_timings.c index c1bac1d01cc431666a1a4b94de3f415e895e255b..e6aa79039131ce1e0c4c172dcaae0a8f9f87b929 100644 --- a/drivers/mtd/nand/raw/nand_timings.c +++ b/drivers/mtd/nand/raw/nand_timings.c @@ -8,6 +8,7 @@ * published by the Free Software Foundation. * */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_util.c b/drivers/mtd/nand/raw/nand_util.c index fda4239fa792dfc677367fcac632a2b239a282a4..72cc24f40376eb95349c3984f0c32bb12ebb5a97 100644 --- a/drivers/mtd/nand/raw/nand_util.c +++ b/drivers/mtd/nand/raw/nand_util.c @@ -18,6 +18,7 @@ * Copyright 2010 Freescale Semiconductor */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 61751b9ae2db043106178eccc29cca10cc5d80d5..015ec9bc2de0179c954e8097aec87a61cc3d76bd 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -12,6 +12,7 @@ * sets in uboot */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 92a92ad63a022223b7c262d03f1e78a297520ada..2f8fa7d73d21c97b0b81f72ce6b5352ce9ef3b11 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -4,7 +4,7 @@ * Rohit Choraria */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 17c5601bead0e0c635ac730755420051bc069d97..1d9a6d107b17925a89ef706b81210a4993153baf 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -6,6 +6,7 @@ * Copyright © 2006 Marvell International Ltd. */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index f730e15d04107fd1c9571c9a992f0f8a1e3ec637..088cc7fead24147ff30d50e25bf792e490af56a9 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -5,6 +5,7 @@ * Author: Yifeng Zhao */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 083ea4c5a74b782ba655e1b9eac87823be9cce4e..d284b8cbb123eb5939933e67c1908d5eec72f039 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_MTD +#include #include #include #include diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 34197bb09a19551655160112f3215e0c9da691ac..0b5b74dc242d1b69fd39c6f820955679b4fef60d 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -25,6 +25,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index 040138e255925cbb27fee15ced5a3f35b303be07..c9b8c78ed7523a53b6d0bb253af66a4c1a8dcc9b 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index 8285f87359e79ea061660ce8e7dec37f4b64aef5..6086ecdfa3dbfba65219cf2c5e42534d7d7dc0b5 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -6,6 +6,7 @@ * (C) Copyright 2006 DENX Software Engineering */ +#include #include #include #include diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 1026595036892b09e785cd1cdd1059a42ddd039d..d2363a0662e274073679c1fcbac4a532acdb8b71 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -21,7 +21,7 @@ * - HW ECC: Only 24 and 32-bit error correction implemented. */ -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 5f90171a6fe3476e86e062507f45f55c034b4938..bacaf13c570dcab868d93432e70194318d966920 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -6,6 +6,7 @@ * This driver is based on plat_nand.c and mxc_nand.c drivers */ +#include #include #include #include diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index ef50237f10e6006da57b1fb94b4217c92fa1be5b..62c28aa422d25049593774baf9694597f2e0ac1b 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -21,6 +21,7 @@ #include #include #else +#include #include #include #include diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c index 95dfa58def17a3fd7393b69992e9488aa1ab238e..9a316d1de397e6e60e9a89f4ef77e4f18eaabaa6 100644 --- a/drivers/mtd/nvmxip/nvmxip-uclass.c +++ b/drivers/mtd/nvmxip/nvmxip-uclass.c @@ -6,6 +6,7 @@ * Abdellatif El Khlifi */ +#include #include #include #if CONFIG_IS_ENABLED(SANDBOX64) diff --git a/drivers/mtd/nvmxip/nvmxip.c b/drivers/mtd/nvmxip/nvmxip.c index 229938db3806b0e0ad6ac0baf442b962c62936bb..0bd98d64275fa1a88f6e8841f0336826d12e84c3 100644 --- a/drivers/mtd/nvmxip/nvmxip.c +++ b/drivers/mtd/nvmxip/nvmxip.c @@ -6,6 +6,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c index 460887c7da343388569d6f1138e32e4e556d9333..4d7471118a4c1394b6b510e6a05345c3ea143e9b 100644 --- a/drivers/mtd/nvmxip/nvmxip_qspi.c +++ b/drivers/mtd/nvmxip/nvmxip_qspi.c @@ -6,6 +6,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index edecb841338f5781ca79d8aa8a2d661935140bc2..762b01c1b0f0953ea774974ef66a103f42673382 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -19,6 +19,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index 6af1cb2ec19ad8ace1a40693c2c0cb1d469a24ed..cc1e449f4a72af4c6919a32dddb9e9e30b17feab 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -14,6 +14,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index a9d54a243ade6bf00ed0a1329d056cefecbb7b12..2699958a5de245ded105e1aa69a59c1911cbfa70 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -7,10 +7,9 @@ * Kyungmin Park */ -#include +#include #include #include -#include #include #include diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index db0ac6c1fb8f2454641c7920400856e2425fc0b2..ecacabefadcfa7ac0498079c7893dc230ac719a4 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -13,7 +13,7 @@ * OneNAND initialization at U-Boot */ -#include +#include #include #include #include diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index ccfdad4913e8916686297bc49d30fb46c3db3503..c415e5149a019e99f4d69d7c9bfff0d229642a90 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -9,6 +9,7 @@ * Emulate the pseudo BufferRAM */ +#include #include #include #include diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 8dcffde9aa396403f64aae56d81c8878f5baf56c..979b64d4a2f69de81592aba28a8f33993fbeacba 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -7,6 +7,7 @@ * Copyright (C) 2017 Marek Vasut */ +#include #include #include #include diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 73eea922c33a75cb45b426f3099d4ecec58ed7d3..cdbdbd6ea5810845aded4fc63e6784ac829f3d75 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -3,7 +3,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c index 2d5a16bf6a29a6ddd4240d47450224cda542c3d9..4fe547171a5f06705b3cedc4476720a76a36ba4c 100644 --- a/drivers/mtd/spi/sandbox.c +++ b/drivers/mtd/spi/sandbox.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY UCLASS_SPI_FLASH +#include #include #include #include diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index a4d15bd64aa2e18bc020a7b15b7a93f514ecc977..2da0cf0dcf9f4274118d8c4ed3eac1751126b902 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SPI_FLASH +#include #include #include #include diff --git a/drivers/mtd/spi/sf_bootdev.c b/drivers/mtd/spi/sf_bootdev.c index 017a74a3016fc6bd664ccfdd24270e2797a14787..d6b47b11ce451e430463a5a18d4469562b9f70de 100644 --- a/drivers/mtd/spi/sf_bootdev.c +++ b/drivers/mtd/spi/sf_bootdev.c @@ -5,6 +5,7 @@ * Copyright 2022 Google LLC */ +#include #include #include #include diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index 6db24189c8eaa67338af162370b4af1d78834b1f..6a0d953a72904c91381ec517bdfabcad266c6ce0 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -6,6 +6,7 @@ * Haikun Wang (haikun.wang@freescale.com) */ +#include #include #include #include diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c index 7342f26d88e0b50eb281cc14fff72369c41da5aa..071b25ac67f2d4e14f8ea3cf846716cbe926df85 100644 --- a/drivers/mtd/spi/sf_mtd.c +++ b/drivers/mtd/spi/sf_mtd.c @@ -3,6 +3,7 @@ * Copyright (C) 2012-2014 Daniel Schwierzeck, daniel.schwierzeck@gmail.com */ +#include #include #include #include diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7100b64bf22aae56f74fb2588af8fa0440ab0d9e..de6516f1065be9fb106e71894f22f5ff34b0f2f0 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -7,6 +7,7 @@ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. */ +#include #include #include #include diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 982dd251150dc5373dc96f0e2fd267f416fc1f08..f86003ca8c06439e6871f1661be790f1fb4c0852 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -9,6 +9,7 @@ * Synced from Linux v4.19 */ +#include #include #include #include diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 684206ea07ddb6caf79f97b4cdfd287e68c4c1a0..4e83b8c94c96ed6a9392ca88338d967448607402 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 5755c5eed297a9f756b939f5d0d2727b21b34693..0719fe845ca96f6812bc57f6c913b5a097da304b 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -9,6 +9,7 @@ * Synced from Linux v4.19 */ +#include #include #include #include diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index ec83be6b51fd46603bcfebc91fe9e124eff5527a..4523344ba6b02ac29fe215ad70a897a013d90e9a 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -4,7 +4,7 @@ * Kamil Lulko, */ -#include +#include #include #include #include diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c index 90a7c4c6f9e08552d68a54afbe6d423a4a345de0..b58d8e8d5656c41dea1ea17fbde382a1db2f2384 100644 --- a/drivers/mtd/ubispl/ubispl.c +++ b/drivers/mtd/ubispl/ubispl.c @@ -7,6 +7,7 @@ * Copyright (c) International Business Machines Corp., 2006 */ +#include #include #include #include diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index e1125458a629f5bccea8335b5a9b2236922a8e27..00e0282dcc0e194dc03739bd090979734e5206b6 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 Pengutronix, Philipp Zabel * Copyright (C) 2019 Texas Instrument, Jean-jacques Hiblot */ +#include #include #include #include diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c index 8a3e7a84f41bfd77d0d49b0a4bc3c5465d25454f..8833888ded37408a694fa8eb275e66409ddb7309 100644 --- a/drivers/mux/mux-uclass.c +++ b/drivers/mux/mux-uclass.c @@ -13,6 +13,7 @@ #define LOG_CATEGORY UCLASS_MUX +#include #include #include #include diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b4ff033afa9f0959c3ab921a0de8d3ab2e3e7b7f..b2d7b499766f4fb6fbf4d2836da523d012de581a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -193,24 +193,6 @@ config CALXEDA_XGMAC This driver supports the XGMAC in Calxeda Highbank and Midway machines. -config DWC_ETH_XGMAC - bool "Synopsys DWC Ethernet XGMAC device support" - select PHYLIB - help - This driver supports the Synopsys Designware Ethernet XGMAC (10G - Ethernet MAC) IP block. The IP supports many options for bus type, - clocking/reset structure, and feature list. - -config DWC_ETH_XGMAC_SOCFPGA - bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" - select REGMAP - select SYSCON - depends on DWC_ETH_XGMAC - default y if TARGET_SOCFPGA_AGILEX5 - help - The Synopsys Designware Ethernet XGMAC IP block with specific - configuration used in Intel SoC FPGA chip. - config DRIVER_DM9000 bool "Davicom DM9000 controller driver" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dce71685c3d09d2d4e08c690fa9132151f34a5e0..dc3404519d6e1edf5b3e67276b1b06b54380cc59 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -22,8 +22,6 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o -obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o -obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c index 059a65d46610b3f121d4b33e8f0d7250c4490247..da1f3f4580805f70905760919e2c314668e3c3e9 100644 --- a/drivers/net/ag7xxx.c +++ b/drivers/net/ag7xxx.c @@ -6,6 +6,7 @@ * Copyright (C) 2019 Rosy Song */ +#include #include #include #include diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index c57aafd0026309724dccf9cb8d40a6881ce48d48..e2340936fa62dd6f819a422aba290405e916b94d 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -8,6 +8,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include #include #include #include diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index f2e4392aa9ace8029f0f4c7752bd28e579e771e3..a99715a7282947996fabdcee936fd538759ceb0c 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -7,6 +7,7 @@ * This file is inspired from the Linux kernel driver drivers/net/phy/mdio-aspeed.c */ +#include #include #include #include diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c index ba244b4a26e25e3590c2899ee60504522b658cc5..cbe1e85222fa29d1d9dcf36b38c28a7fe51bc44f 100644 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -11,6 +11,7 @@ #endif #include +#include #include #include #include diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index c10719c6b510b1bf27403c7e9fec27655ce60f0f..1524f5c99890e02fd48974317e57092715ba84a5 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -3,6 +3,7 @@ * Copyright 2014 Broadcom Corporation. */ +#include #include #include #include diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index f87db4ab46e4d67b2ad0f1f13b788bc629e6a0b4..15a94f6ce9a105064761c08c77b7f3ae264d38d3 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Maxime Bizon */ +#include #include #include #include diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index 0601fcc42f58e177a8085964b6122e14c81a84f7..9679a45b0758fae6f4398033bb1dfe7b83d4c17e 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Maxime Bizon */ +#include #include #include #include diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c index 25fbcd7b116131879a21b3ee28bda5af3c63c375..1c9a9962408a32dd9289bb7f7036a4522a475f14 100644 --- a/drivers/net/bnxt/bnxt.c +++ b/drivers/net/bnxt/bnxt.c @@ -3,6 +3,7 @@ * Copyright 2019-2021 Broadcom. */ +#include #include #include diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index ebb399457fb58041f402742478db54cfe87b6c40..eb1e2a756cd3c5ce273b153682090e723a7352b3 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -3,6 +3,7 @@ * Copyright 2010-2011 Calxeda, Inc. */ +#include #include #include #include diff --git a/drivers/net/cortina_ni.c b/drivers/net/cortina_ni.c index 790268828002f60f022db417d2297702d0d1f52a..ef6ecd88b0ce4fec7723c2fe8a21ad98714b762d 100644 --- a/drivers/net/cortina_ni.c +++ b/drivers/net/cortina_ni.c @@ -7,6 +7,7 @@ * Ethernet MAC Driver for all supported CAxxxx SoCs */ +#include #include #include #include diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index ce028f451f137e4c2360c0246eeecba4f482638a..4e7af95b41c44fe5290e37f67e291ae5063874a1 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 07b0f49ef58104acc4279e11345e336698bfb2ac..682045cea2cfb058beeae01ea527e3e6d49b3518 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -8,6 +8,7 @@ * Designware ethernet IP driver for U-Boot */ +#include #include #include #include diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 9e17f0b9c2809113e09b8e6e43fce99394c57a16..bec8d67dad0fd238368f709d237f637fda33cea9 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -49,6 +49,7 @@ * TODO: external MII is not functional, only internal at the moment. */ +#include #include #include #include diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 67ac86f82bcd1dd1aae2d966e6ce98f25d1f03e5..32a5d52165ac7d11c7d97c1e73de6202e2750ecf 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -29,6 +29,7 @@ #define LOG_CATEGORY UCLASS_ETH +#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index d6bed278ca799443f6cf11251a247faf3d184758..9c4e390441333fe3c8b50f541b402dc776d6df49 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -3,6 +3,7 @@ * Copyright 2022 NXP */ +#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 77d626393d5afc3139ecded374cd1e9ece2a7680..8178138fc659111d58aaca7b3dcddf475245961d 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -5,6 +5,7 @@ * Qcom DWMAC specific glue layer */ +#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index c4557e57988dc56755e549e9a91d865a19f08811..fa9e513faea3011741926509af2160015181a746 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -8,6 +8,7 @@ * part in order to simplify future porting of fixes and support for other SoCs. */ +#include #include #include #include diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 09e714ce76a0e6f747ad9b1d0c8dcc65cdcd80af..5be8ac0f1a514b7600b55c80ad1821c89e181bc7 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -4,6 +4,7 @@ * Author: Yanhong Wang */ +#include #include #include #include diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c deleted file mode 100644 index d3e5f9255f5ad0bb4f59c926d44dfc5fcf0ecef2..0000000000000000000000000000000000000000 --- a/drivers/net/dwc_eth_xgmac.c +++ /dev/null @@ -1,1165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023, Intel Corporation. - * - * Portions based on U-Boot's dwc_eth_qos.c. - */ - -/* - * This driver supports the Synopsys Designware Ethernet XGMAC (10G Ethernet - * MAC) IP block. The IP supports multiple options for bus type, clocking/ - * reset structure, and feature list. - * - * The driver is written such that generic core logic is kept separate from - * configuration-specific logic. Code that interacts with configuration- - * specific resources is split out into separate functions to avoid polluting - * common code. If/when this driver is enhanced to support multiple - * configurations, the core code should be adapted to call all configuration- - * specific functions through function pointers, with the definition of those - * function pointers being supplied by struct udevice_id xgmac_ids[]'s .data - * field. - * - * This configuration uses an AXI master/DMA bus, an AHB slave/register bus, - * contains the DMA, MTL, and MAC sub-blocks, and supports a single RGMII PHY. - * This configuration also has SW control over all clock and reset signals to - * the HW block. - */ - -#define LOG_CATEGORY UCLASS_ETH - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dwc_eth_xgmac.h" - -static void *xgmac_alloc_descs(struct xgmac_priv *xgmac, unsigned int num) -{ - return memalign(ARCH_DMA_MINALIGN, num * xgmac->desc_size); -} - -static void xgmac_free_descs(void *descs) -{ - free(descs); -} - -static struct xgmac_desc *xgmac_get_desc(struct xgmac_priv *xgmac, - unsigned int num, bool rx) -{ - return (rx ? xgmac->rx_descs : xgmac->tx_descs) + - (num * xgmac->desc_size); -} - -void xgmac_inval_desc_generic(void *desc) -{ - unsigned long start; - unsigned long end; - - if (!desc) { - pr_err("%s invalid input buffer\n", __func__); - return; - } - - start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN(start + sizeof(struct xgmac_desc), - ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -} - -void xgmac_flush_desc_generic(void *desc) -{ - unsigned long start; - unsigned long end; - - if (!desc) { - pr_err("%s invalid input buffer\n", __func__); - return; - } - - start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN(start + sizeof(struct xgmac_desc), - ARCH_DMA_MINALIGN); - - flush_dcache_range(start, end); -} - -void xgmac_inval_buffer_generic(void *buf, size_t size) -{ - unsigned long start; - unsigned long end; - - if (!buf) { - pr_err("%s invalid input buffer\n", __func__); - return; - } - - start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)buf + size, - ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -} - -void xgmac_flush_buffer_generic(void *buf, size_t size) -{ - unsigned long start; - unsigned long end; - - if (!buf) { - pr_err("%s invalid input buffer\n", __func__); - return; - } - - start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN((unsigned long)buf + size, - ARCH_DMA_MINALIGN); - - flush_dcache_range(start, end); -} - -static int xgmac_mdio_wait_idle(struct xgmac_priv *xgmac) -{ - return wait_for_bit_le32(&xgmac->mac_regs->mdio_data, - XGMAC_MAC_MDIO_ADDRESS_SBUSY, false, - XGMAC_TIMEOUT_100MS, true); -} - -static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, - int mdio_reg) -{ - struct xgmac_priv *xgmac = bus->priv; - u32 val; - u32 hw_addr; - int ret; - - debug("%s(dev=%p, addr=0x%x, reg=%d):\n", __func__, xgmac->dev, mdio_addr, - mdio_reg); - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); - return ret; - } - - /* Set clause 22 format */ - val = BIT(mdio_addr); - writel(val, &xgmac->mac_regs->mdio_clause_22_port); - - hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); - - val = xgmac->config->config_mac_mdio << - XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT; - - val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | - XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | - XGMAC_MAC_MDIO_ADDRESS_SBUSY; - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); - return ret; - } - - writel(hw_addr, &xgmac->mac_regs->mdio_address); - writel(val, &xgmac->mac_regs->mdio_data); - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO read didn't complete: %d\n", ret); - return ret; - } - - val = readl(&xgmac->mac_regs->mdio_data); - val &= XGMAC_MAC_MDIO_DATA_GD_MASK; - - debug("%s: val=0x%x\n", __func__, val); - - return val; -} - -static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, - int mdio_reg, u16 mdio_val) -{ - struct xgmac_priv *xgmac = bus->priv; - u32 val; - u32 hw_addr; - int ret; - - debug("%s(dev=%p, addr=0x%x, reg=%d, val=0x%x):\n", __func__, xgmac->dev, - mdio_addr, mdio_reg, mdio_val); - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); - return ret; - } - - /* Set clause 22 format */ - val = BIT(mdio_addr); - writel(val, &xgmac->mac_regs->mdio_clause_22_port); - - hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); - - hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) << - XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; - - val = (xgmac->config->config_mac_mdio << - XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT); - - val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | - mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | - XGMAC_MAC_MDIO_ADDRESS_SBUSY; - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO not idle at entry: %d\n", ret); - return ret; - } - - writel(hw_addr, &xgmac->mac_regs->mdio_address); - writel(val, &xgmac->mac_regs->mdio_data); - - ret = xgmac_mdio_wait_idle(xgmac); - if (ret) { - pr_err("MDIO write didn't complete: %d\n", ret); - return ret; - } - - return 0; -} - -static int xgmac_set_full_duplex(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - - debug("%s(dev=%p):\n", __func__, dev); - - clrbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); - - return 0; -} - -static int xgmac_set_half_duplex(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - - debug("%s(dev=%p):\n", __func__, dev); - - setbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); - - /* WAR: Flush TX queue when switching to half-duplex */ - setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, - XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ); - - return 0; -} - -static int xgmac_set_gmii_speed(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 val; - - debug("%s(dev=%p):\n", __func__, dev); - - val = XGMAC_MAC_CONF_SS_1G_GMII << XGMAC_MAC_CONF_SS_SHIFT; - writel(val, &xgmac->mac_regs->tx_configuration); - - return 0; -} - -static int xgmac_set_mii_speed_100(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 val; - - debug("%s(dev=%p):\n", __func__, dev); - - val = XGMAC_MAC_CONF_SS_100M_MII << XGMAC_MAC_CONF_SS_SHIFT; - writel(val, &xgmac->mac_regs->tx_configuration); - - return 0; -} - -static int xgmac_set_mii_speed_10(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 val; - - debug("%s(dev=%p):\n", __func__, dev); - - val = XGMAC_MAC_CONF_SS_2_10M_MII << XGMAC_MAC_CONF_SS_SHIFT; - writel(val, &xgmac->mac_regs->tx_configuration); - - return 0; -} - -static int xgmac_adjust_link(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret; - bool en_calibration; - - debug("%s(dev=%p):\n", __func__, dev); - - if (xgmac->phy->duplex) - ret = xgmac_set_full_duplex(dev); - else - ret = xgmac_set_half_duplex(dev); - if (ret < 0) { - pr_err("xgmac_set_*_duplex() failed: %d\n", ret); - return ret; - } - - switch (xgmac->phy->speed) { - case SPEED_1000: - en_calibration = true; - ret = xgmac_set_gmii_speed(dev); - break; - case SPEED_100: - en_calibration = true; - ret = xgmac_set_mii_speed_100(dev); - break; - case SPEED_10: - en_calibration = false; - ret = xgmac_set_mii_speed_10(dev); - break; - default: - pr_err("invalid speed %d\n", xgmac->phy->speed); - return -EINVAL; - } - if (ret < 0) { - pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret); - return ret; - } - - if (en_calibration) { - ret = xgmac->config->ops->xgmac_calibrate_pads(dev); - if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", - ret); - return ret; - } - } else { - ret = xgmac->config->ops->xgmac_disable_calibration(dev); - if (ret < 0) { - pr_err("xgmac_disable_calibration() failed: %d\n", - ret); - return ret; - } - } - - return 0; -} - -static int xgmac_write_hwaddr(struct udevice *dev) -{ - struct eth_pdata *plat = dev_get_plat(dev); - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 val; - - /* - * This function may be called before start() or after stop(). At that - * time, on at least some configurations of the XGMAC HW, all clocks to - * the XGMAC HW block will be stopped, and a reset signal applied. If - * any register access is attempted in this state, bus timeouts or CPU - * hangs may occur. This check prevents that. - * - * A simple solution to this problem would be to not implement - * write_hwaddr(), since start() always writes the MAC address into HW - * anyway. However, it is desirable to implement write_hwaddr() to - * support the case of SW that runs subsequent to U-Boot which expects - * the MAC address to already be programmed into the XGMAC registers, - * which must happen irrespective of whether the U-Boot user (or - * scripts) actually made use of the XGMAC device, and hence - * irrespective of whether start() was ever called. - * - */ - if (!xgmac->config->reg_access_always_ok && !xgmac->reg_access_ok) - return 0; - - /* Update the MAC address */ - val = (plat->enetaddr[5] << 8) | - (plat->enetaddr[4]); - writel(val, &xgmac->mac_regs->address0_high); - val = (plat->enetaddr[3] << 24) | - (plat->enetaddr[2] << 16) | - (plat->enetaddr[1] << 8) | - (plat->enetaddr[0]); - writel(val, &xgmac->mac_regs->address0_low); - return 0; -} - -static int xgmac_read_rom_hwaddr(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret; - - ret = xgmac->config->ops->xgmac_get_enetaddr(dev); - if (ret < 0) - return ret; - - return !is_valid_ethaddr(pdata->enetaddr); -} - -static int xgmac_get_phy_addr(struct xgmac_priv *priv, struct udevice *dev) -{ - struct ofnode_phandle_args phandle_args; - int reg; - - if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, - &phandle_args)) { - debug("Failed to find phy-handle"); - return -ENODEV; - } - - priv->phy_of_node = phandle_args.node; - - reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); - - return reg; -} - -static int xgmac_start(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret, i; - u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; - ulong last_rx_desc; - ulong desc_pad; - - struct xgmac_desc *tx_desc = NULL; - struct xgmac_desc *rx_desc = NULL; - int addr = -1; - - debug("%s(dev=%p):\n", __func__, dev); - - xgmac->tx_desc_idx = 0; - xgmac->rx_desc_idx = 0; - - ret = xgmac->config->ops->xgmac_start_resets(dev); - if (ret < 0) { - pr_err("xgmac_start_resets() failed: %d\n", ret); - goto err; - } - - xgmac->reg_access_ok = true; - - ret = wait_for_bit_le32(&xgmac->dma_regs->mode, - XGMAC_DMA_MODE_SWR, false, - xgmac->config->swr_wait, false); - if (ret) { - pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret); - goto err_stop_resets; - } - - ret = xgmac->config->ops->xgmac_calibrate_pads(dev); - if (ret < 0) { - pr_err("xgmac_calibrate_pads() failed: %d\n", ret); - goto err_stop_resets; - } - - /* - * if PHY was already connected and configured, - * don't need to reconnect/reconfigure again - */ - if (!xgmac->phy) { - addr = xgmac_get_phy_addr(xgmac, dev); - xgmac->phy = phy_connect(xgmac->mii, addr, dev, - xgmac->config->interface(dev)); - if (!xgmac->phy) { - pr_err("phy_connect() failed\n"); - goto err_stop_resets; - } - - if (xgmac->max_speed) { - ret = phy_set_supported(xgmac->phy, xgmac->max_speed); - if (ret) { - pr_err("phy_set_supported() failed: %d\n", ret); - goto err_shutdown_phy; - } - } - - xgmac->phy->node = xgmac->phy_of_node; - ret = phy_config(xgmac->phy); - if (ret < 0) { - pr_err("phy_config() failed: %d\n", ret); - goto err_shutdown_phy; - } - } - - ret = phy_startup(xgmac->phy); - if (ret < 0) { - pr_err("phy_startup() failed: %d\n", ret); - goto err_shutdown_phy; - } - - if (!xgmac->phy->link) { - pr_err("No link\n"); - goto err_shutdown_phy; - } - - ret = xgmac_adjust_link(dev); - if (ret < 0) { - pr_err("xgmac_adjust_link() failed: %d\n", ret); - goto err_shutdown_phy; - } - - /* Configure MTL */ - - /* Enable Store and Forward mode for TX */ - /* Program Tx operating mode */ - setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, - XGMAC_MTL_TXQ0_OPERATION_MODE_TSF | - (XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << - XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); - - /* Transmit Queue weight */ - writel(0x10, &xgmac->mtl_regs->txq0_quantum_weight); - - /* Enable Store and Forward mode for RX, since no jumbo frame */ - setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, - XGMAC_MTL_RXQ0_OPERATION_MODE_RSF); - - /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ - val = readl(&xgmac->mac_regs->hw_feature1); - tx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & - XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; - rx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & - XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; - - /* - * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. - * r/tqs is encoded as (n / 256) - 1. - */ - tqs = (128 << tx_fifo_sz) / 256 - 1; - rqs = (128 << rx_fifo_sz) / 256 - 1; - - clrsetbits_le32(&xgmac->mtl_regs->txq0_operation_mode, - XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK << - XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, - tqs << XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); - clrsetbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, - XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK << - XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, - rqs << XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); - - setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, - XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC); - - /* Configure MAC */ - clrsetbits_le32(&xgmac->mac_regs->rxq_ctrl0, - XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK << - XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, - xgmac->config->config_mac << - XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); - - /* Multicast and Broadcast Queue Enable */ - setbits_le32(&xgmac->mac_regs->rxq_ctrl1, - XGMAC_MAC_RXQ_CTRL1_MCBCQEN); - - /* enable promise mode and receive all mode */ - setbits_le32(&xgmac->mac_regs->mac_packet_filter, - XGMAC_MAC_PACKET_FILTER_RA | - XGMAC_MAC_PACKET_FILTER_PR); - - /* Set TX flow control parameters */ - /* Set Pause Time */ - setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, - XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK << - XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); - - /* Assign priority for RX flow control */ - clrbits_le32(&xgmac->mac_regs->rxq_ctrl2, - XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK << - XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT); - - /* Enable flow control */ - setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, - XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE); - setbits_le32(&xgmac->mac_regs->rx_flow_ctrl, - XGMAC_MAC_RX_FLOW_CTRL_RFE); - - clrbits_le32(&xgmac->mac_regs->tx_configuration, - XGMAC_MAC_CONF_JD); - - clrbits_le32(&xgmac->mac_regs->rx_configuration, - XGMAC_MAC_CONF_JE | - XGMAC_MAC_CONF_GPSLCE | - XGMAC_MAC_CONF_WD); - - setbits_le32(&xgmac->mac_regs->rx_configuration, - XGMAC_MAC_CONF_ACS | - XGMAC_MAC_CONF_CST); - - ret = xgmac_write_hwaddr(dev); - if (ret < 0) { - pr_err("xgmac_write_hwaddr() failed: %d\n", ret); - goto err; - } - - /* Configure DMA */ - clrsetbits_le32(&xgmac->dma_regs->sysbus_mode, - XGMAC_DMA_SYSBUS_MODE_AAL, - XGMAC_DMA_SYSBUS_MODE_EAME | - XGMAC_DMA_SYSBUS_MODE_UNDEF); - - /* Enable OSP mode */ - setbits_le32(&xgmac->dma_regs->ch0_tx_control, - XGMAC_DMA_CH0_TX_CONTROL_OSP); - - /* RX buffer size. Must be a multiple of bus width */ - clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, - XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK << - XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, - XGMAC_MAX_PACKET_SIZE << - XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); - - desc_pad = (xgmac->desc_size - sizeof(struct xgmac_desc)) / - xgmac->config->axi_bus_width; - - setbits_le32(&xgmac->dma_regs->ch0_control, - XGMAC_DMA_CH0_CONTROL_PBLX8 | - (desc_pad << XGMAC_DMA_CH0_CONTROL_DSL_SHIFT)); - - /* - * Burst length must be < 1/2 FIFO size. - * FIFO size in tqs is encoded as (n / 256) - 1. - * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. - * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. - */ - pbl = tqs + 1; - if (pbl > 32) - pbl = 32; - - clrsetbits_le32(&xgmac->dma_regs->ch0_tx_control, - XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK << - XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, - pbl << XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); - - clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, - XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK << - XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, - 8 << XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); - - /* DMA performance configuration */ - val = (XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK << - XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | - (XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK << - XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) | - XGMAC_DMA_SYSBUS_MODE_EAME | - XGMAC_DMA_SYSBUS_MODE_BLEN16 | - XGMAC_DMA_SYSBUS_MODE_BLEN8 | - XGMAC_DMA_SYSBUS_MODE_BLEN4 | - XGMAC_DMA_SYSBUS_MODE_BLEN32; - - writel(val, &xgmac->dma_regs->sysbus_mode); - - /* Set up descriptors */ - - memset(xgmac->tx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_TX); - memset(xgmac->rx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_RX); - - for (i = 0; i < XGMAC_DESCRIPTORS_TX; i++) { - tx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, false); - - xgmac->config->ops->xgmac_flush_desc(tx_desc); - } - - for (i = 0; i < XGMAC_DESCRIPTORS_RX; i++) { - rx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, true); - - rx_desc->des0 = (uintptr_t)(xgmac->rx_dma_buf + - (i * XGMAC_MAX_PACKET_SIZE)); - rx_desc->des3 = XGMAC_DESC3_OWN; - /* Flush the cache to the memory */ - mb(); - xgmac->config->ops->xgmac_flush_desc(rx_desc); - xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf + - (i * XGMAC_MAX_PACKET_SIZE), - XGMAC_MAX_PACKET_SIZE); - } - - writel(0, &xgmac->dma_regs->ch0_txdesc_list_haddress); - writel((ulong)xgmac_get_desc(xgmac, 0, false), - &xgmac->dma_regs->ch0_txdesc_list_address); - writel(XGMAC_DESCRIPTORS_TX - 1, - &xgmac->dma_regs->ch0_txdesc_ring_length); - writel(0, &xgmac->dma_regs->ch0_rxdesc_list_haddress); - writel((ulong)xgmac_get_desc(xgmac, 0, true), - &xgmac->dma_regs->ch0_rxdesc_list_address); - writel(XGMAC_DESCRIPTORS_RX - 1, - &xgmac->dma_regs->ch0_rxdesc_ring_length); - - /* Enable everything */ - setbits_le32(&xgmac->dma_regs->ch0_tx_control, - XGMAC_DMA_CH0_TX_CONTROL_ST); - setbits_le32(&xgmac->dma_regs->ch0_rx_control, - XGMAC_DMA_CH0_RX_CONTROL_SR); - setbits_le32(&xgmac->mac_regs->tx_configuration, - XGMAC_MAC_CONF_TE); - setbits_le32(&xgmac->mac_regs->rx_configuration, - XGMAC_MAC_CONF_RE); - - /* TX tail pointer not written until we need to TX a packet */ - /* - * Point RX tail pointer at last descriptor. Ideally, we'd point at the - * first descriptor, implying all descriptors were available. However, - * that's not distinguishable from none of the descriptors being - * available. - */ - last_rx_desc = (ulong)xgmac_get_desc(xgmac, XGMAC_DESCRIPTORS_RX - 1, true); - writel(last_rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); - - xgmac->started = true; - - debug("%s: OK\n", __func__); - return 0; - -err_shutdown_phy: - phy_shutdown(xgmac->phy); -err_stop_resets: - xgmac->config->ops->xgmac_stop_resets(dev); -err: - pr_err("FAILED: %d\n", ret); - return ret; -} - -static void xgmac_stop(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - unsigned long start_time; - u32 val; - u32 trcsts; - u32 txqsts; - u32 prxq; - u32 rxqsts; - - debug("%s(dev=%p):\n", __func__, dev); - - if (!xgmac->started) - return; - xgmac->started = false; - xgmac->reg_access_ok = false; - - /* Disable TX DMA */ - clrbits_le32(&xgmac->dma_regs->ch0_tx_control, - XGMAC_DMA_CH0_TX_CONTROL_ST); - - /* Wait for TX all packets to drain out of MTL */ - start_time = get_timer(0); - - while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { - val = readl(&xgmac->mtl_regs->txq0_debug); - - trcsts = (val >> XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & - XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK; - - txqsts = val & XGMAC_MTL_TXQ0_DEBUG_TXQSTS; - - if (trcsts != XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE && !txqsts) - break; - } - - /* Turn off MAC TX and RX */ - clrbits_le32(&xgmac->mac_regs->tx_configuration, - XGMAC_MAC_CONF_RE); - clrbits_le32(&xgmac->mac_regs->rx_configuration, - XGMAC_MAC_CONF_RE); - - /* Wait for all RX packets to drain out of MTL */ - start_time = get_timer(0); - - while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { - val = readl(&xgmac->mtl_regs->rxq0_debug); - - prxq = (val >> XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & - XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK; - - rxqsts = (val >> XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & - XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK; - - if (!prxq && !rxqsts) - break; - } - - /* Turn off RX DMA */ - clrbits_le32(&xgmac->dma_regs->ch0_rx_control, - XGMAC_DMA_CH0_RX_CONTROL_SR); - - if (xgmac->phy) - phy_shutdown(xgmac->phy); - - xgmac->config->ops->xgmac_stop_resets(dev); - - debug("%s: OK\n", __func__); -} - -static int xgmac_send(struct udevice *dev, void *packet, int length) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - struct xgmac_desc *tx_desc; - unsigned long start_time; - - debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, - length); - - memcpy(xgmac->tx_dma_buf, packet, length); - xgmac->config->ops->xgmac_flush_buffer(xgmac->tx_dma_buf, length); - - tx_desc = xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false); - xgmac->tx_desc_idx++; - xgmac->tx_desc_idx %= XGMAC_DESCRIPTORS_TX; - - tx_desc->des0 = (ulong)xgmac->tx_dma_buf; - tx_desc->des1 = 0; - tx_desc->des2 = length; - /* - * Make sure that if HW sees the _OWN write below, it will see all the - * writes to the rest of the descriptor too. - */ - mb(); - tx_desc->des3 = XGMAC_DESC3_OWN | XGMAC_DESC3_FD | XGMAC_DESC3_LD | length; - xgmac->config->ops->xgmac_flush_desc(tx_desc); - - writel((ulong)xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false), - &xgmac->dma_regs->ch0_txdesc_tail_pointer); - - start_time = get_timer(0); - - while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { - xgmac->config->ops->xgmac_inval_desc(tx_desc); - if (!(readl(&tx_desc->des3) & XGMAC_DESC3_OWN)) - return 0; - } - debug("%s: TX timeout\n", __func__); - - return -ETIMEDOUT; -} - -static int xgmac_recv(struct udevice *dev, int flags, uchar **packetp) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - struct xgmac_desc *rx_desc; - int length; - - debug("%s(dev=%p, flags=0x%x):\n", __func__, dev, flags); - - rx_desc = xgmac_get_desc(xgmac, xgmac->rx_desc_idx, true); - xgmac->config->ops->xgmac_inval_desc(rx_desc); - if (rx_desc->des3 & XGMAC_DESC3_OWN) { - debug("%s: RX packet not available\n", __func__); - return -EAGAIN; - } - - *packetp = xgmac->rx_dma_buf + - (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); - length = rx_desc->des3 & XGMAC_RDES3_PKT_LENGTH_MASK; - debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); - - xgmac->config->ops->xgmac_inval_buffer(*packetp, length); - - return length; -} - -static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 idx, idx_mask = xgmac->desc_per_cacheline - 1; - uchar *packet_expected; - struct xgmac_desc *rx_desc; - - debug("%s(packet=%p, length=%d)\n", __func__, packet, length); - - packet_expected = xgmac->rx_dma_buf + - (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); - if (packet != packet_expected) { - debug("%s: Unexpected packet (expected %p)\n", __func__, - packet_expected); - return -EINVAL; - } - - xgmac->config->ops->xgmac_inval_buffer(packet, length); - - if ((xgmac->rx_desc_idx & idx_mask) == idx_mask) { - for (idx = xgmac->rx_desc_idx - idx_mask; - idx <= xgmac->rx_desc_idx; - idx++) { - rx_desc = xgmac_get_desc(xgmac, idx, true); - rx_desc->des0 = 0; - /* Flush the cache to the memory */ - mb(); - xgmac->config->ops->xgmac_flush_desc(rx_desc); - xgmac->config->ops->xgmac_inval_buffer(packet, length); - rx_desc->des0 = (u32)(ulong)(xgmac->rx_dma_buf + - (idx * XGMAC_MAX_PACKET_SIZE)); - rx_desc->des1 = 0; - rx_desc->des2 = 0; - /* - * Make sure that if HW sees the _OWN write below, - * it will see all the writes to the rest of the - * descriptor too. - */ - mb(); - rx_desc->des3 = XGMAC_DESC3_OWN; - xgmac->config->ops->xgmac_flush_desc(rx_desc); - } - writel((ulong)rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); - } - - xgmac->rx_desc_idx++; - xgmac->rx_desc_idx %= XGMAC_DESCRIPTORS_RX; - - return 0; -} - -static int xgmac_probe_resources_core(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - unsigned int desc_step; - int ret; - - debug("%s(dev=%p):\n", __func__, dev); - - /* Maximum distance between neighboring descriptors, in Bytes. */ - desc_step = sizeof(struct xgmac_desc); - - if (desc_step < ARCH_DMA_MINALIGN) { - /* - * The hardware implementation cannot place one descriptor - * per cacheline, it is necessary to place multiple descriptors - * per cacheline in memory and do cache management carefully. - */ - xgmac->desc_size = BIT(fls(desc_step) - 1); - } else { - xgmac->desc_size = ALIGN(sizeof(struct xgmac_desc), - (unsigned int)ARCH_DMA_MINALIGN); - } - xgmac->desc_per_cacheline = ARCH_DMA_MINALIGN / xgmac->desc_size; - - xgmac->tx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_TX); - if (!xgmac->tx_descs) { - debug("%s: xgmac_alloc_descs(tx) failed\n", __func__); - ret = -ENOMEM; - goto err; - } - - xgmac->rx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_RX); - if (!xgmac->rx_descs) { - debug("%s: xgmac_alloc_descs(rx) failed\n", __func__); - ret = -ENOMEM; - goto err_free_tx_descs; - } - - xgmac->tx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_MAX_PACKET_SIZE); - if (!xgmac->tx_dma_buf) { - debug("%s: memalign(tx_dma_buf) failed\n", __func__); - ret = -ENOMEM; - goto err_free_descs; - } - debug("%s: tx_dma_buf=%p\n", __func__, xgmac->tx_dma_buf); - - xgmac->rx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_RX_BUFFER_SIZE); - if (!xgmac->rx_dma_buf) { - debug("%s: memalign(rx_dma_buf) failed\n", __func__); - ret = -ENOMEM; - goto err_free_tx_dma_buf; - } - debug("%s: rx_dma_buf=%p\n", __func__, xgmac->rx_dma_buf); - - xgmac->rx_pkt = malloc(XGMAC_MAX_PACKET_SIZE); - if (!xgmac->rx_pkt) { - debug("%s: malloc(rx_pkt) failed\n", __func__); - ret = -ENOMEM; - goto err_free_rx_dma_buf; - } - debug("%s: rx_pkt=%p\n", __func__, xgmac->rx_pkt); - - xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf, - XGMAC_MAX_PACKET_SIZE * XGMAC_DESCRIPTORS_RX); - - debug("%s: OK\n", __func__); - return 0; - -err_free_rx_dma_buf: - free(xgmac->rx_dma_buf); -err_free_tx_dma_buf: - free(xgmac->tx_dma_buf); -err_free_descs: - xgmac_free_descs(xgmac->rx_descs); -err_free_tx_descs: - xgmac_free_descs(xgmac->tx_descs); -err: - - debug("%s: returns %d\n", __func__, ret); - return ret; -} - -static int xgmac_remove_resources_core(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - - debug("%s(dev=%p):\n", __func__, dev); - - free(xgmac->rx_pkt); - free(xgmac->rx_dma_buf); - free(xgmac->tx_dma_buf); - xgmac_free_descs(xgmac->rx_descs); - xgmac_free_descs(xgmac->tx_descs); - - debug("%s: OK\n", __func__); - return 0; -} - -/* board-specific Ethernet Interface initializations. */ -__weak int board_interface_eth_init(struct udevice *dev, - phy_interface_t interface_type) -{ - return 0; -} - -static int xgmac_probe(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret; - - debug("%s(dev=%p):\n", __func__, dev); - - xgmac->dev = dev; - xgmac->config = (void *)dev_get_driver_data(dev); - - xgmac->regs = dev_read_addr(dev); - if (xgmac->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed\n"); - return -ENODEV; - } - xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE); - xgmac->mtl_regs = (void *)(xgmac->regs + XGMAC_MTL_REGS_BASE); - xgmac->dma_regs = (void *)(xgmac->regs + XGMAC_DMA_REGS_BASE); - - xgmac->max_speed = dev_read_u32_default(dev, "max-speed", 0); - - ret = xgmac_probe_resources_core(dev); - if (ret < 0) { - pr_err("xgmac_probe_resources_core() failed: %d\n", ret); - return ret; - } - - ret = xgmac->config->ops->xgmac_probe_resources(dev); - if (ret < 0) { - pr_err("xgmac_probe_resources() failed: %d\n", ret); - goto err_remove_resources_core; - } - - ret = xgmac->config->ops->xgmac_start_clks(dev); - if (ret < 0) { - pr_err("xgmac_start_clks() failed: %d\n", ret); - return ret; - } - - if (IS_ENABLED(CONFIG_DM_ETH_PHY)) - xgmac->mii = eth_phy_get_mdio_bus(dev); - - if (!xgmac->mii) { - xgmac->mii = mdio_alloc(); - if (!xgmac->mii) { - pr_err("mdio_alloc() failed\n"); - ret = -ENOMEM; - goto err_stop_clks; - } - xgmac->mii->read = xgmac_mdio_read; - xgmac->mii->write = xgmac_mdio_write; - xgmac->mii->priv = xgmac; - strcpy(xgmac->mii->name, dev->name); - - ret = mdio_register(xgmac->mii); - if (ret < 0) { - pr_err("mdio_register() failed: %d\n", ret); - goto err_free_mdio; - } - } - - if (IS_ENABLED(CONFIG_DM_ETH_PHY)) - eth_phy_set_mdio_bus(dev, xgmac->mii); - - debug("%s: OK\n", __func__); - return 0; - -err_free_mdio: - mdio_free(xgmac->mii); -err_stop_clks: - xgmac->config->ops->xgmac_stop_clks(dev); -err_remove_resources_core: - xgmac_remove_resources_core(dev); - - debug("%s: returns %d\n", __func__, ret); - return ret; -} - -static int xgmac_remove(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - - debug("%s(dev=%p):\n", __func__, dev); - - mdio_unregister(xgmac->mii); - mdio_free(xgmac->mii); - xgmac->config->ops->xgmac_stop_clks(dev); - xgmac->config->ops->xgmac_remove_resources(dev); - - xgmac_remove_resources_core(dev); - - debug("%s: OK\n", __func__); - return 0; -} - -int xgmac_null_ops(struct udevice *dev) -{ - return 0; -} - -static const struct eth_ops xgmac_ops = { - .start = xgmac_start, - .stop = xgmac_stop, - .send = xgmac_send, - .recv = xgmac_recv, - .free_pkt = xgmac_free_pkt, - .write_hwaddr = xgmac_write_hwaddr, - .read_rom_hwaddr = xgmac_read_rom_hwaddr, -}; - -static const struct udevice_id xgmac_ids[] = { - { - .compatible = "intel,socfpga-dwxgmac", - .data = (ulong)&xgmac_socfpga_config - }, - { } -}; - -U_BOOT_DRIVER(eth_xgmac) = { - .name = "eth_xgmac", - .id = UCLASS_ETH, - .of_match = of_match_ptr(xgmac_ids), - .probe = xgmac_probe, - .remove = xgmac_remove, - .ops = &xgmac_ops, - .priv_auto = sizeof(struct xgmac_priv), - .plat_auto = sizeof(struct eth_pdata), -}; diff --git a/drivers/net/dwc_eth_xgmac.h b/drivers/net/dwc_eth_xgmac.h deleted file mode 100644 index 259f815f3f27477bf99cf8341276fb5cb07d7627..0000000000000000000000000000000000000000 --- a/drivers/net/dwc_eth_xgmac.h +++ /dev/null @@ -1,298 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2023 Intel Coporation. - */ - -#include -#include - -/* Core registers */ - -#define XGMAC_MAC_REGS_BASE 0x000 - -struct xgmac_mac_regs { - u32 tx_configuration; /* 0x000 */ - u32 rx_configuration; /* 0x004 */ - u32 mac_packet_filter; /* 0x008 */ - u32 unused_00c[(0x070 - 0x00c) / 4]; /* 0x00c */ - u32 q0_tx_flow_ctrl; /* 0x070 */ - u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ - u32 rx_flow_ctrl; /* 0x090 */ - u32 unused_094[(0x0a0 - 0x094) / 4]; /* 0x094 */ - u32 rxq_ctrl0; /* 0x0a0 */ - u32 rxq_ctrl1; /* 0x0a4 */ - u32 rxq_ctrl2; /* 0x0a8 */ - u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ - u32 us_tic_counter; /* 0x0dc */ - u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ - u32 hw_feature0; /* 0x11c */ - u32 hw_feature1; /* 0x120 */ - u32 hw_feature2; /* 0x124 */ - u32 hw_feature3; /* 0x128 */ - u32 hw_feature4; /* 0x12c */ - u32 unused_130[(0x140 - 0x130) / 4]; /* 0x130 */ - u32 mac_extended_conf; /* 0x140 */ - u32 unused_144[(0x200 - 0x144) / 4]; /* 0x144 */ - u32 mdio_address; /* 0x200 */ - u32 mdio_data; /* 0x204 */ - u32 mdio_cont_write_addr; /* 0x208 */ - u32 mdio_cont_write_data; /* 0x20c */ - u32 mdio_cont_scan_port_enable; /* 0x210 */ - u32 mdio_intr_status; /* 0x214 */ - u32 mdio_intr_enable; /* 0x218 */ - u32 mdio_port_cnct_dsnct_status; /* 0x21c */ - u32 mdio_clause_22_port; /* 0x220 */ - u32 unused_224[(0x300 - 0x224) / 4]; /* 0x224 */ - u32 address0_high; /* 0x300 */ - u32 address0_low; /* 0x304 */ -}; - -#define XGMAC_TIMEOUT_100MS 100000 -#define XGMAC_MAC_CONF_SS_SHIFT 29 -#define XGMAC_MAC_CONF_SS_10G_XGMII 0 -#define XGMAC_MAC_CONF_SS_2_5G_GMII 2 -#define XGMAC_MAC_CONF_SS_1G_GMII 3 -#define XGMAC_MAC_CONF_SS_100M_MII 4 -#define XGMAC_MAC_CONF_SS_5G_XGMII 5 -#define XGMAC_MAC_CONF_SS_2_5G_XGMII 6 -#define XGMAC_MAC_CONF_SS_2_10M_MII 7 - -#define XGMAC_MAC_CONF_JD BIT(16) -#define XGMAC_MAC_CONF_JE BIT(8) -#define XGMAC_MAC_CONF_WD BIT(7) -#define XGMAC_MAC_CONF_GPSLCE BIT(6) -#define XGMAC_MAC_CONF_CST BIT(2) -#define XGMAC_MAC_CONF_ACS BIT(1) -#define XGMAC_MAC_CONF_TE BIT(0) -#define XGMAC_MAC_CONF_RE BIT(0) - -#define XGMAC_MAC_EXT_CONF_HD BIT(24) - -#define XGMAC_MAC_PACKET_FILTER_RA BIT(31) -#define XGMAC_MAC_PACKET_FILTER_PR BIT(0) - -#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 -#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK GENMASK(15, 0) -#define XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) - -#define XGMAC_MAC_RX_FLOW_CTRL_RFE BIT(0) -#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 -#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK GENMASK(1, 0) -#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 -#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 -#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 - -#define XGMAC_MAC_RXQ_CTRL1_MCBCQEN BIT(15) - -#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 -#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK GENMASK(7, 0) - -#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 -#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK GENMASK(4, 0) -#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 -#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK GENMASK(4, 0) - -#define XGMAC_MDIO_SINGLE_CMD_SHIFT 16 -#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ 3 << XGMAC_MDIO_SINGLE_CMD_SHIFT -#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE BIT(16) -#define XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT 16 -#define XGMAC_MAC_MDIO_ADDRESS_PA_MASK GENMASK(15, 0) -#define XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT 21 -#define XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT 19 -#define XGMAC_MAC_MDIO_ADDRESS_CR_100_150 0 -#define XGMAC_MAC_MDIO_ADDRESS_CR_150_250 1 -#define XGMAC_MAC_MDIO_ADDRESS_CR_250_300 2 -#define XGMAC_MAC_MDIO_ADDRESS_CR_300_350 3 -#define XGMAC_MAC_MDIO_ADDRESS_CR_350_400 4 -#define XGMAC_MAC_MDIO_ADDRESS_CR_400_500 5 -#define XGMAC_MAC_MDIO_ADDRESS_SADDR BIT(18) -#define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) -#define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) -#define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) - -/* MTL Registers */ - -#define XGMAC_MTL_REGS_BASE 0x1000 - -struct xgmac_mtl_regs { - u32 mtl_operation_mode; /* 0x1000 */ - u32 unused_1004[(0x1030 - 0x1004) / 4]; /* 0x1004 */ - u32 mtl_rxq_dma_map0; /* 0x1030 */ - u32 mtl_rxq_dma_map1; /* 0x1034 */ - u32 mtl_rxq_dma_map2; /* 0x1038 */ - u32 mtl_rxq_dma_map3; /* 0x103c */ - u32 mtl_tc_prty_map0; /* 0x1040 */ - u32 mtl_tc_prty_map1; /* 0x1044 */ - u32 unused_1048[(0x1100 - 0x1048) / 4]; /* 0x1048 */ - u32 txq0_operation_mode; /* 0x1100 */ - u32 unused_1104; /* 0x1104 */ - u32 txq0_debug; /* 0x1108 */ - u32 unused_100c[(0x1118 - 0x110c) / 4]; /* 0x110c */ - u32 txq0_quantum_weight; /* 0x1118 */ - u32 unused_111c[(0x1140 - 0x111c) / 4]; /* 0x111c */ - u32 rxq0_operation_mode; /* 0x1140 */ - u32 unused_1144; /* 0x1144 */ - u32 rxq0_debug; /* 0x1148 */ -}; - -#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 -#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK GENMASK(8, 0) -#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 -#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 -#define XGMAC_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) -#define XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) - -#define XGMAC_MTL_TXQ0_DEBUG_TXQSTS BIT(4) -#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 -#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK GENMASK(2, 0) -#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE 0x1 - -#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 16 -#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK GENMASK(9, 0) -#define XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) -#define XGMAC_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) - -#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 -#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK GENMASK(14, 0) -#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 -#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK GENMASK(1, 0) - -/* DMA Registers */ - -#define XGMAC_DMA_REGS_BASE 0x3000 - -struct xgmac_dma_regs { - u32 mode; /* 0x3000 */ - u32 sysbus_mode; /* 0x3004 */ - u32 unused_3008[(0x3100 - 0x3008) / 4]; /* 0x3008 */ - u32 ch0_control; /* 0x3100 */ - u32 ch0_tx_control; /* 0x3104 */ - u32 ch0_rx_control; /* 0x3108 */ - u32 slot_func_control_status; /* 0x310c */ - u32 ch0_txdesc_list_haddress; /* 0x3110 */ - u32 ch0_txdesc_list_address; /* 0x3114 */ - u32 ch0_rxdesc_list_haddress; /* 0x3118 */ - u32 ch0_rxdesc_list_address; /* 0x311c */ - u32 unused_3120; /* 0x3120 */ - u32 ch0_txdesc_tail_pointer; /* 0x3124 */ - u32 unused_3128; /* 0x3128 */ - u32 ch0_rxdesc_tail_pointer; /* 0x312c */ - u32 ch0_txdesc_ring_length; /* 0x3130 */ - u32 ch0_rxdesc_ring_length; /* 0x3134 */ - u32 unused_3138[(0x3160 - 0x3138) / 4]; /* 0x3138 */ - u32 ch0_status; /* 0x3160 */ -}; - -#define XGMAC_DMA_MODE_SWR BIT(0) -#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 -#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK GENMASK(4, 0) -#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 -#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK GENMASK(4, 0) -#define XGMAC_DMA_SYSBUS_MODE_AAL BIT(12) -#define XGMAC_DMA_SYSBUS_MODE_EAME BIT(11) -#define XGMAC_DMA_SYSBUS_MODE_BLEN32 BIT(4) -#define XGMAC_DMA_SYSBUS_MODE_BLEN16 BIT(3) -#define XGMAC_DMA_SYSBUS_MODE_BLEN8 BIT(2) -#define XGMAC_DMA_SYSBUS_MODE_BLEN4 BIT(1) -#define XGMAC_DMA_SYSBUS_MODE_UNDEF BIT(0) - -#define XGMAC_DMA_CH0_CONTROL_DSL_SHIFT 18 -#define XGMAC_DMA_CH0_CONTROL_PBLX8 BIT(16) - -#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 -#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK GENMASK(5, 0) -#define XGMAC_DMA_CH0_TX_CONTROL_OSP BIT(4) -#define XGMAC_DMA_CH0_TX_CONTROL_ST BIT(0) - -#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 -#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK GENMASK(5, 0) -#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 4 -#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK GENMASK(10, 0) -#define XGMAC_DMA_CH0_RX_CONTROL_SR BIT(0) - -/* Descriptors */ -#define XGMAC_DESCRIPTORS_TX 8 -#define XGMAC_DESCRIPTORS_RX 8 -#define XGMAC_BUFFER_ALIGN ARCH_DMA_MINALIGN -#define XGMAC_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) -#define XGMAC_RX_BUFFER_SIZE (XGMAC_DESCRIPTORS_RX * XGMAC_MAX_PACKET_SIZE) - -#define XGMAC_RDES3_PKT_LENGTH_MASK GENMASK(13, 0) - -struct xgmac_desc { - u32 des0; - u32 des1; - u32 des2; - u32 des3; -}; - -#define XGMAC_DESC3_OWN BIT(31) -#define XGMAC_DESC3_FD BIT(29) -#define XGMAC_DESC3_LD BIT(28) - -#define XGMAC_AXI_WIDTH_32 4 -#define XGMAC_AXI_WIDTH_64 8 -#define XGMAC_AXI_WIDTH_128 16 - -struct xgmac_config { - bool reg_access_always_ok; - int swr_wait; - int config_mac; - int config_mac_mdio; - unsigned int axi_bus_width; - phy_interface_t (*interface)(const struct udevice *dev); - struct xgmac_ops *ops; -}; - -struct xgmac_ops { - void (*xgmac_inval_desc)(void *desc); - void (*xgmac_flush_desc)(void *desc); - void (*xgmac_inval_buffer)(void *buf, size_t size); - void (*xgmac_flush_buffer)(void *buf, size_t size); - int (*xgmac_probe_resources)(struct udevice *dev); - int (*xgmac_remove_resources)(struct udevice *dev); - int (*xgmac_stop_resets)(struct udevice *dev); - int (*xgmac_start_resets)(struct udevice *dev); - int (*xgmac_stop_clks)(struct udevice *dev); - int (*xgmac_start_clks)(struct udevice *dev); - int (*xgmac_calibrate_pads)(struct udevice *dev); - int (*xgmac_disable_calibration)(struct udevice *dev); - int (*xgmac_get_enetaddr)(struct udevice *dev); -}; - -struct xgmac_priv { - struct udevice *dev; - const struct xgmac_config *config; - fdt_addr_t regs; - struct xgmac_mac_regs *mac_regs; - struct xgmac_mtl_regs *mtl_regs; - struct xgmac_dma_regs *dma_regs; - struct reset_ctl reset_ctl; - struct reset_ctl_bulk reset_bulk; - struct clk clk_common; - struct mii_dev *mii; - struct phy_device *phy; - ofnode phy_of_node; - void *syscon_phy; - u32 syscon_phy_regshift; - u32 max_speed; - void *tx_descs; - void *rx_descs; - int tx_desc_idx, rx_desc_idx; - unsigned int desc_size; - unsigned int desc_per_cacheline; - void *tx_dma_buf; - void *rx_dma_buf; - void *rx_pkt; - bool started; - bool reg_access_ok; - bool clk_ck_enabled; -}; - -void xgmac_inval_desc_generic(void *desc); -void xgmac_flush_desc_generic(void *desc); -void xgmac_inval_buffer_generic(void *buf, size_t size); -void xgmac_flush_buffer_generic(void *buf, size_t size); -int xgmac_null_ops(struct udevice *dev); - -extern struct xgmac_config xgmac_socfpga_config; diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c deleted file mode 100644 index 270c1b0ca6ccd86749073c2e42ca8578b7aaccf9..0000000000000000000000000000000000000000 --- a/drivers/net/dwc_eth_xgmac_socfpga.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023, Intel Corporation - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dwc_eth_xgmac.h" - -#define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2 - -static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret; - - u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << - xgmac->syscon_phy_regshift; - - if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { - u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() - - SYSMGR_SOC64_EMAC0) >> 2; - - u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index; - - ret = socfpga_secure_reg_update32(id, - modemask, - modereg << - xgmac->syscon_phy_regshift); - if (ret) { - dev_err(dev, "Failed to set PHY register via SMC call\n"); - return ret; - } - - } else { - clrsetbits_le32(xgmac->phy, modemask, modereg); - } - - return 0; -} - -static int xgmac_probe_resources_socfpga(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - struct regmap *reg_map; - struct ofnode_phandle_args args; - void *range; - phy_interface_t interface; - int ret; - u32 modereg; - - interface = xgmac->config->interface(dev); - - switch (interface) { - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_GMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - break; - case PHY_INTERFACE_MODE_RMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - break; - case PHY_INTERFACE_MODE_RGMII: - modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - break; - default: - dev_err(dev, "Unsupported PHY mode\n"); - return -EINVAL; - } - - /* Get PHY syscon */ - ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, - SOCFPGA_XGMAC_SYSCON_ARG_COUNT, - 0, &args); - - if (ret) { - dev_err(dev, "Failed to get syscon: %d\n", ret); - return ret; - } - - if (args.args_count != SOCFPGA_XGMAC_SYSCON_ARG_COUNT) { - dev_err(dev, "Invalid number of syscon args\n"); - return -EINVAL; - } - - reg_map = syscon_node_to_regmap(args.node); - if (IS_ERR(reg_map)) { - ret = PTR_ERR(reg_map); - dev_err(dev, "Failed to get reg_map: %d\n", ret); - return ret; - } - - range = regmap_get_range(reg_map, 0); - if (!range) { - dev_err(dev, "Failed to get reg_map: %d\n", ret); - return -ENOMEM; - } - - xgmac->syscon_phy = range + args.args[0]; - xgmac->syscon_phy_regshift = args.args[1]; - - /* Get Reset Bulk */ - ret = reset_get_bulk(dev, &xgmac->reset_bulk); - if (ret) { - dev_err(dev, "Failed to get reset: %d\n", ret); - return ret; - } - - ret = reset_assert_bulk(&xgmac->reset_bulk); - if (ret) { - dev_err(dev, "XGMAC failed to assert reset: %d\n", ret); - return ret; - } - - ret = dwxgmac_socfpga_do_setphy(dev, modereg); - if (ret) - return ret; - - ret = reset_deassert_bulk(&xgmac->reset_bulk); - if (ret) { - dev_err(dev, "XGMAC failed to de-assert reset: %d\n", ret); - return ret; - } - - ret = clk_get_by_name(dev, "stmmaceth", &xgmac->clk_common); - if (ret) { - pr_err("clk_get_by_name(stmmaceth) failed: %d", ret); - goto err_probe; - } - return 0; - -err_probe: - debug("%s: returns %d\n", __func__, ret); - return ret; -} - -static int xgmac_get_enetaddr_socfpga(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - struct xgmac_priv *xgmac = dev_get_priv(dev); - u32 hi_addr, lo_addr; - - debug("%s(dev=%p):\n", __func__, dev); - - /* Read the MAC Address from the hardawre */ - hi_addr = readl(&xgmac->mac_regs->address0_high); - lo_addr = readl(&xgmac->mac_regs->address0_low); - - pdata->enetaddr[0] = lo_addr & 0xff; - pdata->enetaddr[1] = (lo_addr >> 8) & 0xff; - pdata->enetaddr[2] = (lo_addr >> 16) & 0xff; - pdata->enetaddr[3] = (lo_addr >> 24) & 0xff; - pdata->enetaddr[4] = hi_addr & 0xff; - pdata->enetaddr[5] = (hi_addr >> 8) & 0xff; - - return !is_valid_ethaddr(pdata->enetaddr); -} - -static int xgmac_start_resets_socfpga(struct udevice *dev) -{ - struct xgmac_priv *xgmac = dev_get_priv(dev); - int ret; - - debug("%s(dev=%p):\n", __func__, dev); - - ret = reset_assert_bulk(&xgmac->reset_bulk); - if (ret < 0) { - pr_err("xgmac reset assert failed: %d", ret); - return ret; - } - - udelay(2); - - ret = reset_deassert_bulk(&xgmac->reset_bulk); - if (ret < 0) { - pr_err("xgmac reset de-assert failed: %d", ret); - return ret; - } - - return 0; -} - -static struct xgmac_ops xgmac_socfpga_ops = { - .xgmac_inval_desc = xgmac_inval_desc_generic, - .xgmac_flush_desc = xgmac_flush_desc_generic, - .xgmac_inval_buffer = xgmac_inval_buffer_generic, - .xgmac_flush_buffer = xgmac_flush_buffer_generic, - .xgmac_probe_resources = xgmac_probe_resources_socfpga, - .xgmac_remove_resources = xgmac_null_ops, - .xgmac_stop_resets = xgmac_null_ops, - .xgmac_start_resets = xgmac_start_resets_socfpga, - .xgmac_stop_clks = xgmac_null_ops, - .xgmac_start_clks = xgmac_null_ops, - .xgmac_calibrate_pads = xgmac_null_ops, - .xgmac_disable_calibration = xgmac_null_ops, - .xgmac_get_enetaddr = xgmac_get_enetaddr_socfpga, -}; - -struct xgmac_config __maybe_unused xgmac_socfpga_config = { - .reg_access_always_ok = false, - .swr_wait = 50, - .config_mac = XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, - .config_mac_mdio = XGMAC_MAC_MDIO_ADDRESS_CR_350_400, - .axi_bus_width = XGMAC_AXI_WIDTH_64, - .interface = dev_read_phy_mode, - .ops = &xgmac_socfpga_ops -}; diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c index fde4aabbacec42a364ac5639ada225ab28f85987..871171e1be5e68c40bee29aed6860409ecc1724a 100644 --- a/drivers/net/dwmac_meson8b.c +++ b/drivers/net/dwmac_meson8b.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 BayLibre, SAS */ +#include #include #include #include diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 969d247b4f3ae2e8b3e683f281208db44aee259f..744b58bdd1a60d54f84997eac7d32f129774be73 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,6 +5,7 @@ * Actions DWMAC specific glue layer */ +#include #include #include #include diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index bba3fc4d34b0e0555b590abeccf56801e2eebe48..82fdff51dacc54358627696f49edbaf60fa4ceab 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -5,6 +5,7 @@ * Altera SoCFPGA EMAC extras */ +#include #include #include #include diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 663d900eb099a093f70e909f51ce3c0937b78f4b..4e7ba6667703e49545d71ff65c7efd176e9b6e59 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -29,6 +29,7 @@ tested on both gig copper and gig fiber boards * Copyright 2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 1e830b99f1d4564e99b98b87ad18962e2848b17d..69adf282c7394b2ee50b152c0f973619dca1282b 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -1,9 +1,9 @@ +#include #include #include #include #include "e1000.h" #include -#include #include /*----------------------------------------------------------------------- diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index d18a8d577ca422c9b6edeb28da21eb953dc7fae8..38d96ab72b6e1a76b0cad86f7abcd6ca85c36349 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c index 1dae26878e61d9a241cbbc9283a52ebff1377e69..9d1e8d38ffa693741ce9ffecc484f2dc36173fc1 100644 --- a/drivers/net/eth-phy-uclass.c +++ b/drivers/net/eth-phy-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_ETH_PHY +#include #include #include #include diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index dc7e6f1929fdde67c672f174511ab4533d402bd3..13fad8119bb5d133867360b6143d472cafbfe228 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -9,6 +9,7 @@ * Copyright (C) 2016 Cadence Design Systems Inc. */ +#include #include #include #include diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92bc2cdd4a784a4381ec5c16e8b0474b8fe9..90af18f80a88caf4512f1c5f2817bd2460d2ef4d 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -7,6 +7,7 @@ * (C) Copyright 2007 Pengutronix, Juergen Beisert */ +#include #include #include #include diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 46a0d38b101c79922bfdb974422523c1a0ca1ad8..1c5543e3c8786a61a4491e2bc0bd8ab83c7d08f7 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang */ -#include +#include #include #include #include diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index 371d9f07a46dab300cbcdc66c772000cddd4c1b9..c51a65cb94fbbd80a204ab345cd811cf636ee805 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -3,6 +3,7 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 19f3f0fef0737353accc0fb6281a2d7b5b6722ce..9fd26de0d72102c55f8e52da3a441aa5fefa9ba1 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP * Dave Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index 41b75761fddc401f9eddf802feeab904859eb417..3db5c907a2abeb26989288de75fcc6e25497f3bc 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 56c5c6846a4720582c5a4b4e636c2934415cc7a7..3b0ee98ddd352ad8f5fb465278a0c965f70b5df8 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -2,7 +2,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 37b54626af0c4f9fe2fe5d06cbb1d463f0404527..eeb67a39a77f1aa8af8920d57b632984c80d84ab 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -7,6 +7,7 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff +#include #include #include #include diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 26425d94ae5573e48be8865447a775f09f1dcade..e0b62b9449092350931b774ec6fac148f0374f9c 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -5,6 +5,7 @@ * Roy Zang * Some part is taken from tsec.c */ +#include #include #include #include diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 362bc9f30a1c9ed260ae460d3d1efbb3f0ca5687..9013b276bc954fb03ce3d3260b8ca5f30fa5e37a 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 6e63e338e5d5bceaad29b6320eda514871793bf6..7ad993221f78310c0831ea45bb25b3aa92ff0b81 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index 4fc1f723a3d9328477361ca9d9fee663fc1027e1..f931491b1120fa3b197e1a1aa6da43602407fb78 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index f6ae947ef99bb27d45714e72db825d7d0b83aa3c..ef9f4bcce4dd728c245434c6e90d70dff0017218 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 18d71e7b60e85ba1344db363e7b4aac625f82d7a..70ab4610cdf63195cf4da60cc5268c502632d70a 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -4,7 +4,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index dafa6d638e3a581b74f13950b3b237ab31ef7dc1..5c260bed7fd5d61673c96aa5bdc12246c5032e0a 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -2,7 +2,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index 390ca0aee707dfb031bb09b20d6ee46152828511..6174934d2b8195d31b6c761f84a1bd329a3dcdf1 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -5,7 +5,7 @@ * Shengzhou Liu */ -#include +#include #include #include #include diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index df76073eecde0285031e416dd276974055241ba4..f0a02bfe457fefafd096f62f8ed6997ee6b20ea5 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang */ -#include +#include #include #include #include diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c index f7b51ce0bbac8ce30b0481f38950e025cc4e5ee5..9cc9f3fde3ad46f1caeda4ac0eaedbed4a0d02a5 100644 --- a/drivers/net/fm/tgec.c +++ b/drivers/net/fm/tgec.c @@ -7,6 +7,7 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff +#include #include #include #include diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index f6c8f80c835e0c1e5514c334c7f0db7b71cb6691..22225c2f82f9bdf052d77baa7e28d29eed6e3d97 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -4,6 +4,7 @@ * Andy Fleming * Some part is taken from tsec.c */ +#include #include #include #include diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index c2869ce4010c0ec32db8a04c0a2a97ae2adebb5d..f5c5057bec100293f0ad0eecf6a204e2c3e53361 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2017-2018, 2020-2021 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index 482fb0463d5db30b25cb6c099f3d7b1a1234f0e6..4d32516b005541c5dcd00d5e505660173b1fc5b0 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index a6b0bafc8c60dea8f343ebcf08e93e27db0da083..1fd5089cc4be37351756bf367b006180c55c19e2 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -4,6 +4,7 @@ * Copyright 2017-2021 NXP */ +#include #include #include #include diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 2d5fcbb6dbd3a610c6cbb49dd8b87cb14cbe52b2..50ad76dfeb55b6bca7d4a6f40fc811afb9bcd009 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -4,6 +4,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c index e3c37d9045f119548772b59183a234f28f4f521b..fce73937502df8c49f1507b7bfa36ff19d24629d 100644 --- a/drivers/net/fsl_ls_mdio.c +++ b/drivers/net/fsl_ls_mdio.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index a0f1c59e058ce74ab6fb14be8aaa5e63d3bbe845..5fd11db05f5e99772740effd02bd350678db08f6 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -5,6 +5,7 @@ * Mingkai Hu */ +#include #include #include #include diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 8781e50a48dc81ccc14939b0ea8500bd9f261eb1..9b536fd5ab890dbbbbda76fbe6fde7fc7c57bb83 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -11,6 +11,7 @@ * Copyright (C) 2018, IBM Corporation. */ +#include #include #include #include diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 199a0723b8437d1d0b41f7719352b5af14a4e652..fae3adc3de347dcb2f3425ee6bfe0c08f80c68cc 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index d63e2dbfaebfabc9c5e052a5f76800509138902d..51f835adabc38784f1217f18d232956977e8a1aa 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -5,6 +5,7 @@ * Rockchip GMAC ethernet IP driver for U-Boot */ +#include #include #include #include diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c index 6b88f6fbf59669d5db10894e22d14f21c7ce2f37..1862235d0cd24cd276af4c5ca9ce44fb3e66e5dd 100644 --- a/drivers/net/higmacv300.c +++ b/drivers/net/higmacv300.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index cc2e826257a919686b24c1cdf50609dd89a4fc94..518548e3bbcd2a10673e59ab432a07144e6b4821 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index b72198ca53077be81b6beb53e7ee321e70c91493..87fbada06ba2ca7bb80e09608b5d7b1ebb36fb0e 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -4,6 +4,7 @@ * Copyright 2017, 2023 NXP */ +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index a803b8fa7972dd55adfd0d9653d7e5f3e6d049eb..adecb8135764f97087d7f79c419a86784c16e16f 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Freescale Semiconductor */ +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 2727fb01179c689a0abcc7da13d5f5ec44cd07ff..32bcb51725ac7b6207f323c631487baaaf284c66 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -2,7 +2,7 @@ /* * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 05017552b3fb3bced537d20a0ba7da7b9487c2dd..845a36bce875ef410707dcb8adaeab5fc889f544 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include +#include #include #include #include diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 25ae684063bb38f2a3b33df9cb6c9410148fdcfb..c2641a92d7ec916b4aa76710d5cfb213efeebefb 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -2,7 +2,7 @@ /* * Copyright 2018, 2020 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/macb.c b/drivers/net/macb.c index cbf5f6055189088ad09be3e0e2767bcb2c96b574..bca014c3cbb1671c4a2cab439bb6e853ed10afc3 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2005-2006 Atmel Corporation */ +#include #include #include #include diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 04b711e4f650498624019f9293bbea6bdb35d703..ec1fae9688bdf04f6ddd6f2eea965a40a01314a3 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -10,7 +10,7 @@ * (C) 2019 Angelo Dureghello */ -#include +#include #include #include #include diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 9bf887035d7f1b6ea378e892127796a8960d3a89..eae20654513e9a24b8feeb4f08a02cc249159a5b 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -4,6 +4,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ +#include #include #include #include diff --git a/drivers/net/mdio-ipq4019.c b/drivers/net/mdio-ipq4019.c index c824c3da3ddbf6c8369ee1f8b9e7f8a35c5e9893..50134b4d9b6a17869bd055bf1e8d1cb3f3cf6318 100644 --- a/drivers/net/mdio-ipq4019.c +++ b/drivers/net/mdio-ipq4019.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index c44fa6acdd70e664381ce8e00a34f5c2c9fd3ee7..78337731e1fd7a71e02ec772561e9806abfd96b0 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 925888e0765a214fedded4673b2cde8f6b4ed72c..7157428a685ebd84a74eecba07b786d89bff2b2e 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c index 2f3d0911fdf733b8218c2cd1d085ee1b42fc125a..5e4f00c4f4d943505273b884e139158bc0c639ba 100644 --- a/drivers/net/mscc_eswitch/luton_switch.c +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 30bb4b5bad8b593967f24779412623c22b67cd95..7ea1f551a11a4b8209ae8ac48fde0e9ba173efd6 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c index 8eab41df99ae5c520c81e9283f0843f2b7dfbbf2..be06e4833733db072e4d77b4efe3865aa22f7bf7 100644 --- a/drivers/net/mscc_eswitch/serval_switch.c +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c index 61547d7933e4f76a5c8337f845f52a709a53aaec..2d2329c204ae50ebfe74c974527090c177286bfe 100644 --- a/drivers/net/mscc_eswitch/servalt_switch.c +++ b/drivers/net/mscc_eswitch/servalt_switch.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index fc8a6bb331bb277df9d35a707e995939c3cf4d1c..b95de474fb027993edb5b74e3c30837723537645 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -13,6 +13,7 @@ * copyrights here, so I can't add them here. */ +#include #include #include #include diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 94f17a97fe0f54ebd6ede1db280fe322daf41987..75e7bcf83b768ac0d4f14927b4cfd83157296ae0 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -6,6 +6,7 @@ * Author: Mark Lee */ +#include #include #include #include diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 557b6b2c8f6ad47544aaaa252332f5bbd954bb94..8fbbc1caccad0c534f1f48dc311b6da8f46f247f 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -23,6 +23,7 @@ * on the mv88e6176 via an SGMII interface. */ +#include #include #include #include diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 17b62bbc20522d5beabfc3b16adb689fbb7db3cb..3587ca2124e33279c74be88a4ae18f15998db559 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -11,6 +11,7 @@ * Copyright (C) 2002 rabeeh@galileo.co.il */ +#include #include #include #include diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c index 3315e06f591f357ab64f9d3034d420ef82948714..5ebcfe14b7fb6d4634a3b711ee9f623b70f03b84 100644 --- a/drivers/net/mvmdio.c +++ b/drivers/net/mvmdio.c @@ -4,6 +4,7 @@ * Author: Ken Ma */ +#include #include #include #include diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index f014d39b1751b3b38e5056efba57ded76d50d69d..24933473fa059e9279f8189bfb212c43bf7e7e75 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -12,6 +12,7 @@ * Thomas Petazzoni */ +#include #include #include #include diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index d19a79d16007b4dc4a9801ea10970860b4e6e48d..1cd543076504690e4d788a2cb43ab6f6ed91f3ec 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 1943de8ba730466e70beb8cb404643bc2884d49a..151bc55e076b7fd4dc5deae00429f27b2500e5dd 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include #include #include -#include #ifndef CFG_NETCONSOLE_BUFFER_SIZE #define CFG_NETCONSOLE_BUFFER_SIZE 512 diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c index f0ec6c556cc22cb10f725ecdca3f85ecfc7dc222..2028f4ae286e077003c188d0c10e42c909d8f448 100644 --- a/drivers/net/npcm750_eth.c +++ b/drivers/net/npcm750_eth.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index adeca3d040dd124d50c6e8ea1c160c15d0e421dd..ecf8c28fe41b82d33df88bb04dc8ae730a589e99 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -5,6 +5,7 @@ * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver */ +#include #include #include #include diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 180a96af16b6b6144e9aeda19b31cba32c1c63d7..a1f3c2bd290cc63be4af01d74564551831e234aa 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -6,6 +6,7 @@ * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. */ +#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c index 99c2a8d4e92b7cd82decf7135d739b0cf6a38da0..2fe0db0fe7171db962b1edda0e6d26764e2ace35 100644 --- a/drivers/net/pfe_eth/pfe_cmd.c +++ b/drivers/net/pfe_eth/pfe_cmd.c @@ -9,6 +9,7 @@ * @brief PFE utility commands */ +#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index e24a6f93d9103814aae34ed99d6621b061f921c6..ab532c5a420eb91ef2204c8154f1a3b10c42df9e 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index ce2f76eabc8c378c65ba5794793f394aeb926e76..ff48726dbf559ef083aee5f8f9ba66e412b70753 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -3,7 +3,7 @@ * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ -#include +#include #include #include #include diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index ce448810ff6db27b74f5de5adc89d233c349d56f..0970449d0f9f982cf55cae660fe129196862b481 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -6,6 +6,7 @@ * Copyright 2022 Variscite Ltd. * Copyright 2022 Josua Mayer */ +#include #include #include #include diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 4517a6b13ba63d6e053c474546324d8591eecca7..a958e88d44fde5f9c2595e5d9f4048937d14bb03 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -6,6 +6,7 @@ * Copyright 2018, 2021 NXP */ #include +#include #include #include #include diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 61525f68c359eb43bbe31054a29033d98278c926..abb7bdf537cfa1e7405be003adba47715aab4240 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -6,6 +6,7 @@ * author Andy Fleming * Copyright (c) 2019 Michael Walle */ +#include #include #include #include diff --git a/drivers/net/phy/b53.c b/drivers/net/phy/b53.c index e95363067fe37ad1018078247edf26873598acb1..26e8e2fe64fb71bbbd315f80cb751049069f221e 100644 --- a/drivers/net/phy/b53.c +++ b/drivers/net/phy/b53.c @@ -22,6 +22,7 @@ * cover other switches would be trivial. */ +#include #include #include #include diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 0a49015eb89a89d70f746267ac4f4cab4f842fe2..ecccb7c3b54ad1443c4465622a5ed627341655a4 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include #include diff --git a/drivers/net/phy/ca_phy.c b/drivers/net/phy/ca_phy.c index 5b2c67d2fdadd5156faf0be06e9a0a8f667a96fa..edef21867b04deae221fd5a0fd14d434ad0836be 100644 --- a/drivers/net/phy/ca_phy.c +++ b/drivers/net/phy/ca_phy.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index d043e859bad74f5e2f49956aa4c38298750fbe35..1cf8b28f5827fba1c0fa8aa3a42fcbd64d0a16e1 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 72d668129851edc905964ddbb6e6b681886150a7..31ffa1ac7a98df6b60dc049a147316e6e1cc564a 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include #define MIIM_DM9161_SCR 0x10 diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 772cde1c520cd20f656cccb7b2370615176798f1..b6726031ebb8f13a43ee16c658cbcae1089cb5f6 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -3,6 +3,7 @@ * TI PHY drivers * */ +#include #include #include #include diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index b6fb5adae1f42c2320f618ad005efdd09bc8fc24..f9d4782580e9318049f1f69840431e320a650e26 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 2f8454ca27da24538e6d1de4c74e82678562635a..4dfdee60dccb23f454353453122c6b34dd1e4cd8 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 11d3616497697b7003bba4b2e3006d6d1b6d6d15..2f0823b83651a86ace38707695c45a0f9d4576c7 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/phy/generic_10g.c b/drivers/net/phy/generic_10g.c index 38dc9a8856310002f47f555a571b924e457dd8c1..34ac51ea070c8d3308e58782261c6905731336fd 100644 --- a/drivers/net/phy/generic_10g.c +++ b/drivers/net/phy/generic_10g.c @@ -7,6 +7,7 @@ * * Based loosely off of Linux's PHY Lib */ +#include #include #include diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c index fe50eec011ad0c78a45046c240ffbb0d055f3824..9d1b97d349ff4e76229e21f6269252eb31fafe40 100644 --- a/drivers/net/phy/intel_xway.c +++ b/drivers/net/phy/intel_xway.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c index a817c58b128ff21925bd2475b70ab159702d2bf7..20940033a38b89d571ab7466970dff6991f3cebd 100644 --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include /* LXT971 Status 2 registers */ diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b0a0b7fcb38b142dfdee14c1865c94379b45d9f0..0a90f710dfe49701d7b4a12605c5b34ec3d09f4c 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include #include #include diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 8c95bcbb9ad96979e9a7a2ac03a502f1fb864efa..9e64672f5cac30d84f66e51ae97980c2a3f58d89 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -22,6 +22,7 @@ * If both the fiber and copper ports are connected, the first to gain * link takes priority and the other port is completely locked out. */ +#include #include #include #include diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index d43b476b3c88418590d2bb1fe3c2ece71de4e629..b49c9b5f495360c1d19964d1e8a60adaa4622e82 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ #include +#include #include #include #include diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c index a9a64466ac2df4960108156caa94a60a64480e71..b0f3abcb037cc6200969d965b1b84f6460fc54d0 100644 --- a/drivers/net/phy/micrel_ksz8xxx.c +++ b/drivers/net/phy/micrel_ksz8xxx.c @@ -6,6 +6,7 @@ * author Andy Fleming * (C) 2012 NetModule AG, David Andrey, added KSZ9031 */ +#include #include #include #include diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 556d75e31ede027e38d753dd8bc20744079b393b..ffc3c987eaae0dbccacd20c139fa3288a9d0cb74 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -8,6 +8,7 @@ * (C) Copyright 2017 Adaptrum, Inc. * Written by Alexandru Gagniuc for Adaptrum, Inc. */ +#include #include #include #include diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 083d9d3996dc600c635e61cfa7c877a1d50d090c..cf71f7d4e7e5a3526c1e97e11ded132575dd7b9f 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -12,6 +12,7 @@ * channel. */ +#include #include #include #include diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index a96430cec43dcdd80e51c65f7c3f9e8d572c5552..a2c763c8791e99584496f6773793a9a7c9eabbb7 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ecc10f788afbd53b4b61fcb30b72e00ceee31fa3..85778106eddcdc04d06c15a27ba5e04a7cbec199 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -29,6 +29,7 @@ * changes may be required. */ +#include #include #include #include diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c index 6284298ebc1a328e9d1c6c97aaa4851c35cdef3e..56060762d85c16025656f89237bfbc8056cc3fea 100644 --- a/drivers/net/phy/mv88e6352.c +++ b/drivers/net/phy/mv88e6352.c @@ -4,6 +4,7 @@ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com */ +#include #include #include #include diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index f7e514ef203a460f7de95ff154ac2445f358e890..6b9e99ea11566f000d1f33f587bbc00284b02c9c 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include /* NatSemi DP83630 */ diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c index a1de438ffff1c31b871b119bdddf2978b5b05a9b..2bca116a9d81808755ff1bf7c3071a9e0a04b3c1 100644 --- a/drivers/net/phy/ncsi.c +++ b/drivers/net/phy/ncsi.c @@ -5,6 +5,7 @@ * Copyright (C) 2019, IBM Corporation. */ +#include #include #include #include diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index a1e4c3d053b669c39d78affe8f04d85af3d6e3c6..f24fc5b2de616104220cca358f8da150351dd7f3 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -5,6 +5,7 @@ * Copyright 2021 NXP * Author: Radu Pirea */ +#include #include #include #include diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index a61471f4277739737f0a5a9a8798c7bf1a43febb..471b0e322b58c70759635cbed2d0f909805ed3c0 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index fbf85d90f546c915b850fed0a914c3ef3c35c1d6..270176cfe6296f36e9c19e39ff1cd18ee9fdc54b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -7,6 +7,7 @@ * * Based loosely off of Linux's PHY Lib */ +#include #include #include #include diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 30f35cced9d60d03d65cd8eede5c0cf11a112313..7e1036b2271fb218f425feb1b36a818941c26fd9 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -6,6 +6,7 @@ * author Andy Fleming * Copyright 2016 Karsten Merker */ +#include #include #include #include diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 0d823f5f2b18556520745bb6d214b277bb39c9d8..056b607e0b8c93433cdf0f2f960647a950a5235e 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -9,6 +9,7 @@ * Some code copied from linux kernel * Copyright (c) 2006 Herbert Valerio Riedel */ +#include #include /* This code does not check the partner abilities. */ diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index b39311976d608643fa19cdfb65c132af8395ed5a..15f2c12ed83cde6d55ca6199e96b71b79c42db88 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -5,6 +5,7 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ +#include #include #include diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 4867d1931b44d1a8450448cb8a5a55bcff2088f7..c5cf0d7dfbd14fc660721bae2f4351a3925af35f 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -6,6 +6,7 @@ * Original Author: Andy Fleming * Add vsc8662 phy support - Priyanka Jain */ +#include #include /* Cicada Auxiliary Control/Status Register */ diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e44b7b75bd585c13364dd2f6f6495dc941b855e7..e2969bc48424fbf0fa3e90ae42514429f34db6e4 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index a59e17d11e5b11e2464f3410447c40d0689c7a9a..c07c780193f483aeaf96d9a80d2c95ed8b26c6e4 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c index eea3c48aeffc6b8cb7071403d6eeb8cdb3eff0e8..1333a3aa7e44838162e15bd733bf74f7b4acb4da 100644 --- a/drivers/net/pic32_eth.c +++ b/drivers/net/pic32_eth.c @@ -3,6 +3,7 @@ * (c) 2015 Purna Chandra Mandal * */ +#include #include #include #include diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c index 8610f9a1aa5df6b526a444a079d57d0f4d4a8bf1..d4049cfea525ec45f8838551f6e21b2790f491fc 100644 --- a/drivers/net/pic32_mdio.c +++ b/drivers/net/pic32_mdio.c @@ -5,6 +5,7 @@ * Copyright 2015 Microchip Inc. * Purna Chandra Mandal */ +#include #include #include #include diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c index ac3aedd8b49eb17a09a2bca38e2d684a291f953a..6d1509d90cf0fc3fb6db091f1c3364de5d2f9715 100644 --- a/drivers/net/qe/dm_qe_uec.c +++ b/drivers/net/qe/dm_qe_uec.c @@ -7,6 +7,7 @@ * Copyright (C) 2020 Heiko Schocher */ +#include #include #include #include diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c index 8c0168be859e03f138b8010a64844e1f7ed71112..a0bcc8d3e55bfcf360a822f52c5bd67961f22da6 100644 --- a/drivers/net/qe/dm_qe_uec_phy.c +++ b/drivers/net/qe/dm_qe_uec_phy.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Heiko Schocher */ +#include #include #include #include diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c index badf4e5db3e5f7928caf04f0d19e7e2b87b516f4..00848a1a37d7b252b363bb20baa451a2bd0c5a77 100644 --- a/drivers/net/qe/uccf.c +++ b/drivers/net/qe/uccf.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/drivers/net/qe/uccf.h b/drivers/net/qe/uccf.h index e60bbe241cd97ee9fa90b5ae301bbcdf04e4b0ca..99f8458edf67613f8d94ec84aaf84fe37fddb9f7 100644 --- a/drivers/net/qe/uccf.h +++ b/drivers/net/qe/uccf.h @@ -9,8 +9,8 @@ #ifndef __UCCF_H__ #define __UCCF_H__ -#include -#include +#include "common.h" +#include "linux/immap_qe.h" #include /* Fast or Giga ethernet */ diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index f1401d2f6ed2ea809479eca92836435f9ae88b9f..4764bca7082473bea5bcc466446cb86efd051e2a 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -8,6 +8,7 @@ * Based on the SuperH Ethernet driver. */ +#include #include #include #include diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6a21d27b74e7bb8b8e8feab850cfb3..5a69ca1a0f9e3c587179ce941a841631f1a879de 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 2e0afad089f8e03aa17469cd36b7285f1b691819..d8f24ec81a2f743058953445765a56950c379c30 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -68,6 +68,7 @@ * */ +#include #include #include #include diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index e80aebc0bcf204f27a69872e58d74df3b800f5ea..93e83661cec4ed5629f1d00948f11ccc1789049f 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -39,6 +39,7 @@ * 26 August 2006 Mihai Georgian * Modified to use le32_to_cpu and cpu_to_le32 properly */ +#include #include #include #include diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index 15670d6d24a10dc140b1c408cd8142120e06f138..fb1ba5a8c83a79939673006fdb0334f9e3f76331 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -4,6 +4,7 @@ * Copyright (c) 2018 Joe Hershberger */ +#include #include #include #include diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 1d716716778cbf372e89fad71ec7b62ad5ebbbf2..99eb7a3bbff6ec09be9689e731e7ae4d27a90c92 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index fe3627db6e3ead717af19800cc425a455a986c87..13022addb6a3e18720981fc9d9772f294a6ddd48 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -6,6 +6,7 @@ * Joe Hershberger */ +#include #include #include #include diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index f1ce994cfd53b2f1affc9f248f8c3344fc9a20e8..7b1f59dc498961f6ff018f30041288ca1e0621aa 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/sja1105.c b/drivers/net/sja1105.c index 0ba84a4496f5628199c21c0f43153582ed3ab703..48f044c647210fb644763f76d0a356f126c474d7 100644 --- a/drivers/net/sja1105.c +++ b/drivers/net/sja1105.c @@ -8,6 +8,7 @@ * Ported from Linux (drivers/net/dsa/sja1105/). */ +#include #include #include #include diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index f39ba40944f39d1ddfd28f0c6fce7902c8e5054a..616b7ce174f43f48bef61af242e9a4b35487f808 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -5,6 +5,7 @@ * (c) 2007 Pengutronix, Sascha Hauer */ +#include #include #include #include diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index f4b97798d2d624795da60d9d3910aef1f3fdf98d..8bff4fe9a9eafaa8aac917192494dcdb74c02169 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 3dee849c97e94b3c305c1af93a2f4dba8a6fd4fe..f546ad1fe8dd7197e2a70a486d8157cb4457c74d 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -5,6 +5,7 @@ * (C) Copyright 2012, Stefan Roese */ +#include #include #include #include diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index c70b42f6bcc249ff9124c2952a38311f32ad19f9..65ade1afd05ce527e4819108cab98cceb4c9f09c 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c index 3e66d7c7bdfbd0d58fa2f7b38c2a1c121ced1c68..d5428274d1907f5c00845a11986748e4d9bc52c3 100644 --- a/drivers/net/ti/cpsw-common.c +++ b/drivers/net/ti/cpsw-common.c @@ -5,6 +5,7 @@ * Copyright (C) 2016, Texas Instruments, Incorporated */ +#include #include #include #include diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index d7746f454baf6519c697d18254ac8ce7a98b8deb..9a5e9642df113ce9a82b61c9dd65568e53b95ac4 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -5,6 +5,7 @@ * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c index 9e0083ca7896e800eb91ba53f9853a6671817b29..f1b1eba75d00537cadce9c2d849858754e6ae37b 100644 --- a/drivers/net/ti/cpsw_mdio.c +++ b/drivers/net/ti/cpsw_mdio.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 03a1a7a115998fbcfa7c6579106970b0835f2f51..034877a769071d7ef3b3719727f20eda4a91362b 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -21,7 +21,7 @@ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors */ -#include +#include #include #include #include diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index c6e5bf21cf05a1799b3339cb3ee4ad6636d3f141..43dbf3f10670d2760d837581c421727890bc05e8 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -5,6 +5,7 @@ * (C) Copyright 2012-2014 * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 6481ee24a6010099cbabb5a213641c63706176a2..8833e3098d52ea53e38d6b9f02b23fbc77d4f2b0 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index bd1869dfc8300da13932e6cf11e23f7e93a49a78..09883f06be28986b523a5a00754c99cbbca7769e 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index a1a39f61488ebf0c34da7b0504d8c2e31b4e8770..ef151ee51b40a1acd4df81b6afce78af5dbbafde 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 555651937f863c00c5426c6cd86ac9fedb0d1e00..410fb25ddef420fa2970f1a8327b0775277da328 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index c25ac2e66009be99760b7e79c8aad3239ee5f571..16ba915fbaafa6c3ac738b85873a5af9971dd5b0 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -6,6 +6,7 @@ * Michal SIMEK */ +#include #include #include #include diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index b41ee95892e87a96813721535825a522e5edc674..7c57d32614fa68ce1bc3f31461dee994d3a47b77 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/drivers/nvme/nvme-uclass.c b/drivers/nvme/nvme-uclass.c index 44c88ad27f3e20d70162b52a31356e1452e7dfd3..f3af6a27b63bdb70db7f77e2ababe942255760e0 100644 --- a/drivers/nvme/nvme-uclass.c +++ b/drivers/nvme/nvme-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_NVME +#include #include #include #include diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 7c58ceb78f515ccaa56abe9616f09159e422e0d0..59a139baa0ba6c7323b29cc11311000d8fb4a84f 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 Bin Meng */ +#include #include #include #include diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c index 7e7538553e3f49b12c88c0100c5bac32cdd43705..819b748dc02ed1c8c588cf2783ab53ec51122dea 100644 --- a/drivers/nvme/nvme_apple.c +++ b/drivers/nvme/nvme_apple.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c index c24f8cf1eb1faf94f89bfcfc53d6eec9ba3a66c1..5bb43d299fca865577ac1daf2fb6be1327e11f27 100644 --- a/drivers/nvme/nvme_pci.c +++ b/drivers/nvme/nvme_pci.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 Bin Meng */ +#include #include #include #include diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c index 158102363e999ad0b01d7c8c7d8764e54e6aa44f..72cbac82bccaf686351313d3e5747ae4cacc9d2e 100644 --- a/drivers/nvme/nvme_show.c +++ b/drivers/nvme/nvme_show.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 Bin Meng */ +#include #include #include #include diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 9af2475800426438ee9717825fc64ed81fae9b84..af028f9cecad7ab6310ed585da209df03af0095d 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PCH +#include #include #include diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c index 4ef82a77e270493d686cab5be1e9d0eda1f857ca..5fb35a19effee90916af91c2ceef37240b144be3 100644 --- a/drivers/pch/pch7.c +++ b/drivers/pch/pch7.c @@ -3,6 +3,7 @@ * Copyright (C) 2014 Google, Inc */ +#include #include #include #include diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c index 24b0465efde48744343a4a81660cde26eb398c00..3137eb2c28f5bb4e846aacaf636058c3fb2e7791 100644 --- a/drivers/pch/pch9.c +++ b/drivers/pch/pch9.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_PCH +#include #include #include #include diff --git a/drivers/pch/sandbox_pch.c b/drivers/pch/sandbox_pch.c index aa82dca560f1cc1a4825196ab07911293e9e8159..37c368954b45311f51493247feec6417d602b2ac 100644 --- a/drivers/pch/sandbox_pch.c +++ b/drivers/pch/sandbox_pch.c @@ -3,6 +3,7 @@ * Copyright 2018 Google LLC */ +#include #include #include diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index f5db4bdb7605783f9fc10181c752e884743256cf..af0e55cd2f2cd99e654d1484a66fdb761f3128d9 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -25,6 +25,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c index 166ee9fcd431a61e32a3273633ed631f1a1f9ba2..a0b8afb87a012fd52bdad5ade62ff5dd7c4534c6 100644 --- a/drivers/pci/pci-emul-uclass.c +++ b/drivers/pci/pci-emul-uclass.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 12c31e74087f1db843934d5cef18f29c2ed9a74d..b81eb35368967b6ebf55f69f4c802af4f31ac94a 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ -#include +#include #include #include #include diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 76878246f1e02b20d28a9fcbd6fc8d274d6fb0fc..1252ef74c581b7f5731aae9ac76fe559c387992c 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -15,6 +15,7 @@ * Author: Phil Edworthy */ +#include #include #include #include diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 6571e653049deab2f46bf3d5cfe7ebf67b3f18c4..1a48256de036edc25412cfbbc67465a56a2842d0 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PCI +#include #include #include #include diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 90f81886445740f606df7a6e3f0eead9398f86cb..01230360bad21e8a705d509c15a987807028489b 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -8,7 +8,7 @@ * Copyright (c) 2021 Maciej W. Rozycki */ -#include +#include #include #include #include diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c index cfa818ed82183d00a36b1193e5a23b6ecd9a3bf9..2f4aff01049a2dcb48d00c5f9e97e7459e6cc524 100644 --- a/drivers/pci/pci_auto_common.c +++ b/drivers/pci/pci_auto_common.c @@ -11,6 +11,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index a57cf11cc537775a393c8565a7caf753900d4fd3..a18251297fd0db3c37a837d467f010ca994b8851 100644 --- a/drivers/pci/pci_common.c +++ b/drivers/pci/pci_common.c @@ -9,6 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index 8233925e525e76f50c40e58e51062554892f57f7..9dddca8efe07a14873cad62049fa5aa620b3eba1 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -4,6 +4,7 @@ * * Copyright (C) 2014 Google, Inc */ +#include #include #include #include diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c index 43275b3d6a228354101ab69f86e44dd7e8fa94e8..a1775445005a2f4cf078ab4962f3a33778b9c7e9 100644 --- a/drivers/pci/pci_ftpci100.c +++ b/drivers/pci/pci_ftpci100.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later +#include #include #include #include diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index c07feba79768e971155f3dba9a722e7f081ec975..249cfe66466b75a2e7dfee5df7dbc2ce500183c3 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -4,6 +4,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. * */ +#include #include #include #include diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 77815513b768415ef0472be58debcb506833b2d2..83559550e6fbe8e8a176c49dbacb6b4a12c340a2 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -10,6 +10,7 @@ * Pali Rohár */ +#include #include #include #include diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 78e5de937cdf8e1df4bcfa7607a58b9e0e6e2d7e..438583aa01795187e3e3eca147729b8b8bedf977 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -24,6 +24,7 @@ #define LOG_CATEGORY UCLASS_PCI +#include #include #include #include @@ -35,7 +36,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c index fed0850458d90f9e0c9c7520bc154d7a71a6289b..ca44d002371e2b3f7c2aea2a07ad39560020b931 100644 --- a/drivers/pci/pci_sandbox.c +++ b/drivers/pci/pci_sandbox.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index 3cd01e9b94a285559ddb52beb8b88c86c8ccc359..c1be56ce7a082580bb37a5f196de9f7d95c2a367 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -5,7 +5,7 @@ * (C) 2007,2008 Nobuhiro Iwamatsu */ -#include +#include #include #include #include diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index bb8832c6ab96cda4daa58c2819bc15004c66d63a..d6374a58e330a4d38778acbb1f8961489a889f01 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "tegra-pcie: " fmt +#include #include #include #include diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c index ab76166451c77c34a0553d272c66f263fa13e28e..8d036930e73b9e936285cf265f0ab834eb27e705 100644 --- a/drivers/pci/pci_x86.c +++ b/drivers/pci/pci_x86.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c index 6a8e715d4b6e16da07c4623c1fc8a758d4e52795..21bafba3b0eeffb720cc6ac0b930ea8ce3fe34fb 100644 --- a/drivers/pci/pcie_apple.c +++ b/drivers/pci/pcie_apple.c @@ -16,6 +16,7 @@ * Author: Marc Zyngier */ +#include #include #include #include diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c index f978c64365c38419cc13d3d5235b53d676c4a1c9..cd45f0bee9b7996b9305eb80fb282904a87821e4 100644 --- a/drivers/pci/pcie_brcmstb.c +++ b/drivers/pci/pcie_brcmstb.c @@ -12,6 +12,7 @@ * Copyright (C) 2020 Nicolas Saenz Julienne */ +#include #include #include #include diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 0673e516c6fee6c01e5a5d23592e0ef55d49d823..74fb6df412c7c200b03b78947c393f4c3ecff4c1 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -8,6 +8,7 @@ * Copyright (C) 2018 Texas Instruments, Inc */ +#include #include #include #include diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index bb78e7874b14d1f8f186cd4e6d37623db42c6ea0..f953797908b871c3ab50ea48df26a500dd5a348e 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -9,6 +9,7 @@ * Copyright (c) 2021 Rockchip, Inc. */ +#include #include #include #include diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 43b919175c9255de3cb7415ce66ee0c9c6686569..c41f3f1530443db1fd46937a542fbccebe806bb8 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -10,11 +10,10 @@ * - drivers/pci/pcie_xilinx.c */ -#include +#include #include #include #include -#include #include #include #include diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 1bad51fb3eb5bb6fde33bf6a61f77234f85a73e1..bc4635f67136ae188334bca9f83f7e838fc4d99e 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -5,6 +5,7 @@ * Copyright (c) 2021 Rockchip, Inc. */ +#include #include #include #include diff --git a/drivers/pci/pcie_dw_sifive.c b/drivers/pci/pcie_dw_sifive.c index 6285edf4b03707e1ed0324d0d76b561642ec197e..fac3f182372413edb42417e01c5a23aa38f0bc75 100644 --- a/drivers/pci/pcie_dw_sifive.c +++ b/drivers/pci/pcie_dw_sifive.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c index 78a5d035865191c1d5b8967dcb11fb1a07b03ec9..4195a02de390e77cfd51c06779504531ff4a16b5 100644 --- a/drivers/pci/pcie_dw_ti.c +++ b/drivers/pci/pcie_dw_ti.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Texas Instruments, Inc */ +#include #include #include #include diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c index 3cb2bbbccb4439e18d0f2b69329e9747483ee083..f5bc6e3d92d646b6123921dabd902298731729dd 100644 --- a/drivers/pci/pcie_ecam_generic.c +++ b/drivers/pci/pcie_ecam_generic.c @@ -7,6 +7,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include #include #include #include diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c index fc855dfca4eb23022b4805883eb6d9f812aa6a6f..e3e22891088e2bf87d710f0a7ee77b1538ba6819 100644 --- a/drivers/pci/pcie_ecam_synquacer.c +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -8,6 +8,7 @@ * Copyright (C) 2021 Linaro Ltd. */ +#include #include #include #include diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 18af23c9504e9a4b353ebe0db4685b52a9bcc8a9..ec917ee7d5b87d4c2401e08f0cf5b6e53e26e593 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -6,7 +6,7 @@ * Author: Hou Zhiqiang */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c index 9187e7af74617a8efc313f3d2c7c6da6efc9fe29..f4e227895d174534d0c7fb70375c5ef5f729d622 100644 --- a/drivers/pci/pcie_fsl_fixup.c +++ b/drivers/pci/pcie_fsl_fixup.c @@ -6,6 +6,7 @@ * Author: Hou Zhiqiang */ +#include #ifdef CONFIG_OF_BOARD_SETUP #include #include diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 11c4ccbfc5553a826f72c40d4ad1c5a7e8aae07c..78f2c7d6bcdf9e0aa0d9931348088202465aeb14 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -17,6 +17,7 @@ * those too in order to have a single modern PCIe iMX driver. */ +#include #include #include #include diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c index 959fd3690869131615f41d8522c542449f3e8054..60195cfe1b6e4e8d684197c22496a0d63c40df97 100644 --- a/drivers/pci/pcie_intel_fpga.c +++ b/drivers/pci/pcie_intel_fpga.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 360ef1b011f21e8627e2502ac7c77aa3cd35cc17..d6d3a9e202505d00d09152c8223e6fa93b6e6779 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1be33095b9cee07e563f841ecafa8c1b5ef0bfe5..3c7c4ca18e8b5324bb5bf3e0a1f28fb86774fc09 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -5,6 +5,7 @@ * Layerscape PCIe driver */ +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 3520488b345356a13b058c268750ebae6d35142a..83f7eebd6277002600fe1271f20e6f139ab00143 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -4,7 +4,7 @@ * Layerscape PCIe EP driver */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index ec4a7e7b65743937fde7e15ede17ff57becf91c6..c5198353957bbba9f5d29254632df94b5c952a3e 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -5,6 +5,7 @@ * Layerscape PCIe driver */ +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_fixup_common.c b/drivers/pci/pcie_layerscape_fixup_common.c index f37e37f6b153e8a21061ab7ed3d663934d700ace..095874a92763298cf4ef752316572b3e17ac4a17 100644 --- a/drivers/pci/pcie_layerscape_fixup_common.c +++ b/drivers/pci/pcie_layerscape_fixup_common.c @@ -7,10 +7,10 @@ * */ +#include #include #include #include -#include #include #include #include "pcie_layerscape_fixup_common.h" diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 57dc91f2faef6af50755bc0bc4c6f0ad185aee39..021c975869fd5c8be73d1b06bd5b3710c84638aa 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -6,7 +6,7 @@ * Author: Hou Zhiqiang */ -#include +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c index 60c4338bcdb5434ef7a3fb27b56d08a48067b5a7..b2a45bf105c84c2e2fa801f3efdba6177a53302d 100644 --- a/drivers/pci/pcie_layerscape_gen4_fixup.c +++ b/drivers/pci/pcie_layerscape_gen4_fixup.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c index e7913d43a8be398f870ec949601ccc2eb493d672..6a5bf88da2340edb15c777592e7f4a2baefaafda 100644 --- a/drivers/pci/pcie_layerscape_rc.c +++ b/drivers/pci/pcie_layerscape_rc.c @@ -4,6 +4,7 @@ * Layerscape PCIe driver */ +#include #include #include #include diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index 04d8cc29afd5c9f559b8590f1a23e0c3c6e5c07b..f0f34b5d119702920f5153e3905845c21478127e 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -7,6 +7,7 @@ * Honghui Zhang */ +#include #include #include #include diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c index 94de89bcad7b49bd529cfce5cb8c26ac397a25e1..3bd1f5cd6d912e2f5155fa2d5bb662af08404a48 100644 --- a/drivers/pci/pcie_phytium.c +++ b/drivers/pci/pcie_phytium.c @@ -7,6 +7,7 @@ * Copyright (C) 2019 */ +#include #include #include #include diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c index 622a5cee1099208bd3cf484bda2cb49b5acffc12..cd74bb471163be6667c7b9d3bdb8578d660d6c24 100644 --- a/drivers/pci/pcie_plda_common.c +++ b/drivers/pci/pcie_plda_common.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 19f9e58a640dca9c3f0c1cf4e605fd122bdd6a41..624841e9d8b81c0311002d20c8c7ea6764cf49e7 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -11,6 +11,7 @@ * Bits taken from Linux Rockchip PCIe host controller. */ +#include #include #include #include diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 569fbfd35c81def0560deef85b2e689585aa305b..903a544d37f6266b6ea498c3e6c345123d89c44e 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/pci/pcie_uniphier.c b/drivers/pci/pcie_uniphier.c index d1170b576bcd8cf74710e3c22054050ac07d3ffd..f2edea9899a4004e9c188a288fa772d64f220a39 100644 --- a/drivers/pci/pcie_uniphier.c +++ b/drivers/pci/pcie_uniphier.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index a674ab04beee834d40b4329f29faa3e24905af7e..3db460b5f93627304a3eeec82b2cd14b1568ea24 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Imagination Technologies */ +#include #include #include #include diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 902d1a51eaa3e819883e0c63f001cfb5a1399a56..6ee4cfbdb4a849632473d81cb8726d12d1eac168 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_PCI_EP +#include #include #include #include diff --git a/drivers/pci_endpoint/pcie-cadence-ep.c b/drivers/pci_endpoint/pcie-cadence-ep.c index e02ea14e4e4a80a90cc65c46cde9acb193da413d..d58c64982b275cc909d1beb4381620ba4dfe9066 100644 --- a/drivers/pci_endpoint/pcie-cadence-ep.c +++ b/drivers/pci_endpoint/pcie-cadence-ep.c @@ -4,6 +4,7 @@ * Written by Ramon Fried */ +#include #include #include #include diff --git a/drivers/pci_endpoint/sandbox-pci_ep.c b/drivers/pci_endpoint/sandbox-pci_ep.c index aa623fa357d561048b1c6311b19800207000e79e..de148cddb91e8c3527c71daa5cb5cefafa58e945 100644 --- a/drivers/pci_endpoint/sandbox-pci_ep.c +++ b/drivers/pci_endpoint/sandbox-pci_ep.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 Ramon Fried */ +#include #include #include #include diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index b9306c9a8279e0d1b7fae7766cd00384f877aa74..6624e9134f43baebf0bd612267498bd95a174a25 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -10,6 +10,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c index d715541bd4cb0e4db81bef95d14346a5bd06bffd..a2fa446cb1c9c26042ff20cd25bc9ac880609e01 100644 --- a/drivers/phy/bcm6318-usbh-phy.c +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -7,6 +7,7 @@ * Copyright 2013 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c index ffb37b634a31a494e55c4128b31a5170356b157b..857fb575ef19ee0df57d9dfaf0398581983e8f3e 100644 --- a/drivers/phy/bcm6348-usbh-phy.c +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -7,6 +7,7 @@ * Copyright 2013 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c index a8d24609bfc0d9970595ba79de3c0458432f448d..bfdcfb0d245ebe2406ddffc4ce4cebe300805021 100644 --- a/drivers/phy/bcm6358-usbh-phy.c +++ b/drivers/phy/bcm6358-usbh-phy.c @@ -7,6 +7,7 @@ * Copyright 2013 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c index 5bee130425d5dfc84cf5bfeddae162e295a712b5..1a2870d51499818729d88204bfecfbd908a78cae 100644 --- a/drivers/phy/bcm6368-usbh-phy.c +++ b/drivers/phy/bcm6368-usbh-phy.c @@ -7,6 +7,7 @@ * Copyright 2013 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index f5e23f36c56e225f0f303864ecacded5aab3b39c..4bb8a0ca7f348531c4c5dd7009ba76c1610f7065 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -11,6 +11,7 @@ * Jean-Jacques Hiblot * */ +#include #include #include #include diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index d4e8ece4935a28b7a730e2a719273e9becc73d96..ef924e7af508b48b9a1e098b700008829c25eb52 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -10,6 +10,7 @@ * */ +#include #include #include #include diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c index cfc15203d632e86d13d0d491a357da547e5c1f5a..3bb9c0814c14030e5baf5163c767b99319378aad 100644 --- a/drivers/phy/keystone-usb-phy.c +++ b/drivers/phy/keystone-usb-phy.c @@ -4,6 +4,7 @@ * Written by Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index bca325d1996067e5916b9ce222db549e2540868f..c490dc69c69573a779db2c791aa80ec013c9fd83 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ +#include #include #include #include diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index a666a4e794eec43a39b189a4a446909df174da49..7272dfb9fe80c0825111bcc5775dff18ada78996 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index b8cdedf6edf087f9e848e00844e369dee80d281e..bb15fbaf347eaee3459be7c76dc0e72536ba4d01 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ +#include #include #include #include @@ -11,7 +12,6 @@ #include #include #include -#include #include #include "comphy_core.h" diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index a8aa37fc46f354278c5b52e1f85073f7cdd5d039..10981d25ec9540ca4cfec898da1971e5ff4e5156 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Marvell International Ltd. */ +#include #include #include diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c index 3f89de19970bfb39c6fc69b6b770640204729fb1..faa1d9d6d378097a20ad9e5c3268c06fa3000a5d 100644 --- a/drivers/phy/meson-axg-mipi-dphy.c +++ b/drivers/phy/meson-axg-mipi-dphy.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/phy/meson-axg-mipi-pcie-analog.c b/drivers/phy/meson-axg-mipi-pcie-analog.c index 731917cef434ca6df6ecba0a34ae8c2292e9c241..236ea1ce5ca7f172535c1b01d95b3df3c78946e7 100644 --- a/drivers/phy/meson-axg-mipi-pcie-analog.c +++ b/drivers/phy/meson-axg-mipi-pcie-analog.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index 8cded12438b9cb050658b927583544349fe91e32..3958d2404b85d8a35cff66281714cc317b1c3983 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/phy/meson-g12a-usb3-pcie.c b/drivers/phy/meson-g12a-usb3-pcie.c index 4d183867c3a0876273f4fefe7ea2874e23988b5c..1eaff410efa4710f3f61bff2a0d2a0f47092d193 100644 --- a/drivers/phy/meson-g12a-usb3-pcie.c +++ b/drivers/phy/meson-g12a-usb3-pcie.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c index 4c88ccf39276204232d46a6e97bed547d73a78ac..725b056a71a78c39985093865287e3c656111e60 100644 --- a/drivers/phy/meson-gxbb-usb2.c +++ b/drivers/phy/meson-gxbb-usb2.c @@ -8,6 +8,7 @@ * Author: Beniamino Galvani */ +#include #include #include #include diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c index 92c285103c4a22157642bd3e2cddff37ceabcab3..d633effa4042612e29e7b827e5b0fdc6acba1c5e 100644 --- a/drivers/phy/meson-gxl-usb2.c +++ b/drivers/phy/meson-gxl-usb2.c @@ -7,6 +7,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/phy/mt76x8-usb-phy.c b/drivers/phy/mt76x8-usb-phy.c index 99f8a221f5a1d53066d703f7a21d54b5caf8bbd7..4069208b67905f514f15feebbbc4760db62d0bd1 100644 --- a/drivers/phy/mt76x8-usb-phy.c +++ b/drivers/phy/mt76x8-usb-phy.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c index 286171cba76a26bc3092f5b2c490b4a3ad6ab77c..c53e3216d0fd6182c48191a48834a6900af6f7ee 100644 --- a/drivers/phy/nop-phy.c +++ b/drivers/phy/nop-phy.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index 2be0178882a417e7ce1587849179952e41323fd8..d3d38062ecf789c8b68ba37603962395eb7b7135 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -6,6 +6,7 @@ * Written by Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/drivers/phy/phy-ab8500-usb.c b/drivers/phy/phy-ab8500-usb.c index 5de7b6f86ccaf67800a3ab4f17ae563f613ee14a..3d3d48c9733a4bfcc2482d135c53922ccc18be7d 100644 --- a/drivers/phy/phy-ab8500-usb.c +++ b/drivers/phy/phy-ab8500-usb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ +#include #include #include #include diff --git a/drivers/phy/phy-apple-atc.c b/drivers/phy/phy-apple-atc.c index 78eedf676b09324610009e3fb992ebd5defae318..15c5b8a1c2d0f092cf1b082e641066af950807ff 100644 --- a/drivers/phy/phy-apple-atc.c +++ b/drivers/phy/phy-apple-atc.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/phy/phy-bcm-sr-pcie.c b/drivers/phy/phy-bcm-sr-pcie.c index 97859a0cb87e9f144ad75405fc9342260ad80a34..cf33bab370729b57bd2de604f6d85e99452cd2ed 100644 --- a/drivers/phy/phy-bcm-sr-pcie.c +++ b/drivers/phy/phy-bcm-sr-pcie.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Broadcom */ +#include #include #include #include diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c index 8fb985a1e6828d02c54f546f6084dcc9b8605c66..bb61816add27da42668b399c7b03011040faabea 100644 --- a/drivers/phy/phy-core-mipi-dphy.c +++ b/drivers/phy/phy-core-mipi-dphy.c @@ -4,8 +4,8 @@ * Copyright (C) 2018 Cadence Design Systems Inc. */ +#include #include -#include #include #include diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c index cf26aaaa3d82717655ef6ad86fb77a8b46d594db..d025188eae983d42d8f91cc2a44df4e653d649ee 100644 --- a/drivers/phy/phy-da8xx-usb.c +++ b/drivers/phy/phy-da8xx-usb.c @@ -6,9 +6,9 @@ * DT support added by: Adam Ford */ +#include #include #include -#include #include #include #include diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index 75763046adc1cbdc0a8f386acb69f1104ac21d07..e5e96e77a681b4f347262ff650201094a3f95925 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 6f9ac1528e888fdbaccd6209047a3ea8e7ddc8c4..ea9edf212c6f0e4700ccfaeaca53232b38ed4465 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -5,6 +5,7 @@ * Ryder Lee */ +#include #include #include #include diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c index 2cca0f4a0546b1c4ad3a57d6a5e14b511d6081be..09fb14e26f043ae6e9c4baf5885a9c9a1ecb3820 100644 --- a/drivers/phy/phy-npcm-usb.c +++ b/drivers/phy/phy-npcm-usb.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f9428c7ad122a6d3c1908c46870c0788c6ce0d43..e528c4ec57934216f8067841ee20e6a370260d02 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index 7c292cae0e2fa00516ac5c1c23e45ba9cbce9baf..03c747b373b1aab317f760d4bd07c3083006dd57 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 8d643b762f90cd01570e31ed925f7c7cd9204861..000e495dbd4e1b54c893d16e97958364421d2460 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_PHY +#include #include #include #include diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c index c3d9972397aac2a29eee369a11ab8830166c82e1..70a746d2c92dcca45bc5948978c6059b006eceda 100644 --- a/drivers/phy/phy-ti-am654.c +++ b/drivers/phy/phy-ti-am654.c @@ -6,6 +6,7 @@ * Author: Kishon Vijay Abraham I */ +#include #include #include #include diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index acdcda15b5b85b94bb13e52ccedcfb04f4699704..0dcfe258bc44f004ba271e3c03b06091b2b9479e 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PHY +#include #include #include #include diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index 7049e740d56969ae7f28cdb793c857e19dad8dba..d1288bb17f3c15c051c3ac7e6211b1b35b6cf2cb 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -9,6 +9,7 @@ * Author: Laurent Pinchart */ +#include #include #include #include diff --git a/drivers/phy/qcom/msm8916-usbh-phy.c b/drivers/phy/qcom/msm8916-usbh-phy.c index 4b435aa2a6eb3378156ac30149703c5714428e40..f52046f7cb02c616b18a3c4d67caa26da4d4979e 100644 --- a/drivers/phy/qcom/msm8916-usbh-phy.c +++ b/drivers/phy/qcom/msm8916-usbh-phy.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Ramon Fried */ +#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-ipq4019-usb.c b/drivers/phy/qcom/phy-qcom-ipq4019-usb.c index 3b647324e021d6d9ebef6935fa89624dd167b00c..5808489249f5fff42d5b8f1708d39a7f5add84b3 100644 --- a/drivers/phy/qcom/phy-qcom-ipq4019-usb.c +++ b/drivers/phy/qcom/phy-qcom-ipq4019-usb.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c index c344809a6086556493450c39928d3e45901c77c3..05a9a2cf1d7cee3e9dbe1bfd984771525c50c1b5 100644 --- a/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c +++ b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c @@ -5,6 +5,7 @@ * Based on Linux driver */ +#include #include #include #include diff --git a/drivers/phy/qcom/phy-qcom-usb-ss.c b/drivers/phy/qcom/phy-qcom-usb-ss.c index 270d09d883c45867720d2c0b9cf07799373efd56..1b03a3c43dc8d78cf10fedf32103cc9aa2b9c9ef 100644 --- a/drivers/phy/qcom/phy-qcom-usb-ss.c +++ b/drivers/phy/qcom/phy-qcom-usb-ss.c @@ -5,6 +5,7 @@ * Based on Linux driver */ +#include #include #include #include diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c index 40284ef2fd34dc263409092627b549f661a4614d..bd1fdd3a667d379a7ca9f9d905cb61635a91babb 100644 --- a/drivers/phy/renesas/r8a779f0-ether-serdes.c +++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 3ad339bccc1d59e7e7c481592b8886ad462df51c..9ca66bf8db92be3345228225272e204792e3f56a 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 660037034ec0368f991ab01e8015fb812eb696f6..44ca4bc7919e31b543f11f45733a6df092c37696 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -7,6 +7,7 @@ * Copyright (C) 2016 ROCKCHIP, Inc. */ +#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 2737bd81dd968227eb071b6929bf0ea9805ad531..a4392daf4c922624a0fb4270888c95fe78c91197 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index c7459dbc5fc6437fcdff729483e95e7ad3b301cb..47c69dd6c4537fbed4c411b60d257ee386d35baf 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -8,6 +8,7 @@ * Kever Yang */ +#include #include #include #include diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 5bcc76613d14bd5ea2f4a558c962e3ea8b2ade99..18e76402799b729ba3df1ed92372dd76f2468b7d 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include @@ -20,7 +21,7 @@ #include #include #include - +#include #include #define BIT_WRITEABLE_SHIFT 16 @@ -73,6 +74,8 @@ struct udphy_grf_cfg { struct rockchip_udphy; struct rockchip_udphy_cfg { + unsigned int num_phys; + unsigned int phy_ids[2]; /* resets to be requested */ const char * const *rst_list; int num_rsts; @@ -582,10 +585,21 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) return 0; } +static int rockchip_u3phy_of_xlate(struct phy *phy, + struct ofnode_phandle_args *args) +{ + if (args->args_count == 0) + return -EINVAL; + + if (args->args[0] != PHY_TYPE_USB3) + return -EINVAL; + + return 0; +} + static int rockchip_u3phy_init(struct phy *phy) { - struct udevice *parent = phy->dev->parent; - struct rockchip_udphy *udphy = dev_get_priv(parent); + struct rockchip_udphy *udphy = dev_get_priv(phy->dev); /* DP only or high-speed, disable U3 port */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { @@ -598,8 +612,7 @@ static int rockchip_u3phy_init(struct phy *phy) static int rockchip_u3phy_exit(struct phy *phy) { - struct udevice *parent = phy->dev->parent; - struct rockchip_udphy *udphy = dev_get_priv(parent); + struct rockchip_udphy *udphy = dev_get_priv(phy->dev); /* DP only or high-speed */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) @@ -609,47 +622,32 @@ static int rockchip_u3phy_exit(struct phy *phy) } static const struct phy_ops rockchip_u3phy_ops = { + .of_xlate = rockchip_u3phy_of_xlate, .init = rockchip_u3phy_init, .exit = rockchip_u3phy_exit, }; -int rockchip_u3phy_uboot_init(void) -{ - struct udevice *udev; - struct rockchip_udphy *udphy; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_PHY, - DM_DRIVER_GET(rockchip_udphy_u3_port), - &udev); - if (ret) { - pr_err("%s: get u3-port failed: %d\n", __func__, ret); - return ret; - } - - /* DP only or high-speed, disable U3 port */ - udphy = dev_get_priv(udev->parent); - if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { - udphy_u3_port_disable(udphy, true); - return 0; - } - - return udphy_power_on(udphy, UDPHY_MODE_USB); -} - static int rockchip_udphy_probe(struct udevice *dev) { - const struct device_node *np = ofnode_to_np(dev_ofnode(dev)); struct rockchip_udphy *udphy = dev_get_priv(dev); const struct rockchip_udphy_cfg *phy_cfgs; + unsigned int reg; int id, ret; udphy->dev = dev; - id = of_alias_get_id(np, "usbdp"); - if (id < 0) - id = 0; - udphy->id = id; + ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, ®); + if (ret) { + dev_err(dev, "failed to read reg[0] property\n"); + return ret; + } + if (reg == 0 && dev_read_addr_cells(dev) == 2) { + ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®); + if (ret) { + dev_err(dev, "failed to read reg[1] property\n"); + return ret; + } + } phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev); if (!phy_cfgs) { @@ -658,6 +656,20 @@ static int rockchip_udphy_probe(struct udevice *dev) } udphy->cfgs = phy_cfgs; + /* find the phy-id from the io address */ + udphy->id = -ENODEV; + for (id = 0; id < udphy->cfgs->num_phys; id++) { + if (reg == udphy->cfgs->phy_ids[id]) { + udphy->id = id; + break; + } + } + + if (udphy->id < 0) { + dev_err(dev, "no matching device found\n"); + return -ENODEV; + } + ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap); if (ret) return ret; @@ -670,40 +682,6 @@ static int rockchip_udphy_probe(struct udevice *dev) return 0; } -static int rockchip_udphy_bind(struct udevice *parent) -{ - struct udevice *child; - ofnode subnode; - const char *node_name; - int ret; - - dev_for_each_subnode(subnode, parent) { - if (!ofnode_valid(subnode)) { - printf("%s: no subnode for %s", __func__, parent->name); - return -ENXIO; - } - - node_name = ofnode_get_name(subnode); - debug("%s: subnode %s\n", __func__, node_name); - - /* if there is no match, continue */ - if (strcasecmp(node_name, "usb3-port")) - continue; - - /* node name is usb3-port */ - ret = device_bind_driver_to_node(parent, - "rockchip_udphy_u3_port", - node_name, subnode, &child); - if (ret) { - printf("%s: '%s' cannot bind its driver\n", - __func__, node_name); - return ret; - } - } - - return 0; -} - static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) { /* configure phy reference clock */ @@ -837,6 +815,11 @@ static const char * const rk3588_udphy_rst_l[] = { }; static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { + .num_phys = 2, + .phy_ids = { + 0xfed80000, + 0xfed90000, + }, .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), .rst_list = rk3588_udphy_rst_l, .grfcfg = { @@ -863,17 +846,11 @@ static const struct udevice_id rockchip_udphy_dt_match[] = { { /* sentinel */ } }; -U_BOOT_DRIVER(rockchip_udphy_u3_port) = { - .name = "rockchip_udphy_u3_port", - .id = UCLASS_PHY, - .ops = &rockchip_u3phy_ops, -}; - U_BOOT_DRIVER(rockchip_udphy) = { .name = "rockchip_udphy", .id = UCLASS_PHY, .of_match = rockchip_udphy_dt_match, .probe = rockchip_udphy_probe, - .bind = rockchip_udphy_bind, + .ops = &rockchip_u3phy_ops, .priv_auto = sizeof(struct rockchip_udphy), }; diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c index b159147a765bbea8b39dc22a2d50c50fb1597bb2..7e123da25fb4f4d9fb0455751ec29af333ed95ea 100644 --- a/drivers/phy/sandbox-phy.c +++ b/drivers/phy/sandbox-phy.c @@ -4,6 +4,7 @@ * Written by Jean-Jacques Hiblot */ +#include #include #include diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c index 91208dfe12000e219123e1dee94df25484b92014..d352c4ca3a9c443e53a4dd6a304a4dc4f949b680 100644 --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -4,6 +4,7 @@ * Copyright 2019-2021 Socionext, Inc. */ +#include #include #include #include diff --git a/drivers/phy/socionext/phy-uniphier-usb3.c b/drivers/phy/socionext/phy-uniphier-usb3.c index 1d65c1f7da52b627c7142100a47a84cbd7cdbaf3..1d65b0b08f760778f7513aaa3588d001c48e3a75 100644 --- a/drivers/phy/socionext/phy-uniphier-usb3.c +++ b/drivers/phy/socionext/phy-uniphier-usb3.c @@ -4,6 +4,7 @@ * Copyright 2019-2023 Socionext, Inc. */ +#include #include #include diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c index 2447e89f50dff1db57c530fadf491204c0474646..9e5ac9bfde67315533e29e71c3e6f3bd35bc8dac 100644 --- a/drivers/phy/sti_usb_phy.c +++ b/drivers/phy/sti_usb_phy.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index 62f6cc2bfbfd03fa9e4a33d9b172e0b48ebc7481..29a35ae5ffb96333ea68b388b9da650c68936ff2 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -4,6 +4,7 @@ * Written by Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index c69a342e2b495d052055bd710abdf6323ac927fe..daf62f5deda039ae6eb12b637bb15c6d81dfaf52 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -4,6 +4,7 @@ * Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c index 9e7c347caf895757db081a589ff01d4f308a45e0..93920a6389bfb04b329d04fbbcae95e604f75811 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c @@ -3,6 +3,7 @@ * Copyright 2017 Google, Inc */ +#include #include #include #include diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c index bc12590e583604c96f643084072ddfac79824291..8a4f9705ca934764b00bb81e19338f7d1b2a57ae 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c @@ -3,6 +3,7 @@ * Copyright (C) ASPEED Technology Inc. */ +#include #include #include #include diff --git a/drivers/pinctrl/ath79/pinctrl_ar933x.c b/drivers/pinctrl/ath79/pinctrl_ar933x.c index 61e37a2e5598836a818e18f274dbe148e606fbcf..eb673a9f69cb9febdf9483241e9251134002976e 100644 --- a/drivers/pinctrl/ath79/pinctrl_ar933x.c +++ b/drivers/pinctrl/ath79/pinctrl_ar933x.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/drivers/pinctrl/ath79/pinctrl_qca953x.c b/drivers/pinctrl/ath79/pinctrl_qca953x.c index e4f695fc4d44c7b851bc84febf81a6653edb48c2..0d534268e9661a73cc1cfd757e9386386cb66e5b 100644 --- a/drivers/pinctrl/ath79/pinctrl_qca953x.c +++ b/drivers/pinctrl/ath79/pinctrl_qca953x.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index cf9350c151e0521aa8f9246a3d26041918d172fc..e949cb70900ab2ccd0b6a23822c4ab10fa1457af 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -10,6 +10,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c index 7d0c09a130c6f687a02fc84070af54750f8b04b2..58f28a137096798307c11e789bcb1c30fb5c09b0 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm6838.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm6838.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index b393127c642c063116f753808b51219f4e091596..8a045cdf7aa8948e9567b61a34f326286a9a416b 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c index 8fdf60715a53cd8fe18c65744af3a49023056aa1..77d510d8f6003c89dc78296bbfc2cf326307670e 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos7420.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c @@ -5,6 +5,7 @@ * Thomas Abraham */ +#include #include #include #include diff --git a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c index 61b98443daf3d5d13f1004bcb8ec41707ef94c91..1b696fdfd288bf5030679c892b935e3e4e5a81cf 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos78x0.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos78x0.c @@ -9,6 +9,7 @@ * Thomas Abraham */ +#include #include #include #include diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index 6cfe83a593a278c9299219f33b7221ddce8bb70f..1607000dedc1011077515c9091c98b1dbb7ddc86 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -16,6 +16,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c index e554d2854353aea4570178f30a7b70539d55537a..181a6ff27026c74d24634f25de4c7a61ca2fc554 100644 --- a/drivers/pinctrl/intel/pinctrl_apl.c +++ b/drivers/pinctrl/intel/pinctrl_apl.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_GPIO +#include #include #include #include diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 37fc28bb779048c2b404f638ae514dbd3d96938d..0baef57c1c2f9ac32679e03941955f41c47b994d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -4,6 +4,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c index 7e9ac6390b1edac1116fbeb8fdc9d98733b7628c..30cf3bc0be4ebfc021371576efbb98d6bb19038f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-a1.c +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c @@ -6,6 +6,7 @@ * Author: Igor Prusov */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c index 52c726cf038e26b15f1558634ed3da0fc1c40863..cfe94cf9e17ddb42c87a254fc3a9c56d43f39cec 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index 94e09cd3f8a2c64d99e0ab8abd7b3fca0ab5936a..820a6c9bb1aa2b5ca98e9f5c984d9aa4cce9808a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -7,6 +7,7 @@ * Author: Xingyu Chen */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 24f47f825582b1094a203af34875b8c9ca1fd3d4..90a4f8056cdb77e7a7614acf0accd1e9acf76a96 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -8,6 +8,7 @@ * Author: Yixun Lan */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c index 396b3a0e842e303da7de0a3868f41be553ab798c..99502d89c6c09e68be0b9af5cd570fd530901913 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 03ae1f9f8a5d7413f664cc5896319fd0f386062f..93a895c9fa7f3725f588cf8540f2dff499f8c728 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -6,6 +6,7 @@ * Copyright (C) 2016 Endless Mobile, Inc. */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 16517f95ddbfa2438ce8791eb30a3d309e1e1e41..a44145e2d4e80293f3ed52f68627e471fa564a3c 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -6,6 +6,7 @@ * Copyright (C) 2016 Endless Mobile, Inc. */ +#include #include #include #include diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index babf1bccc9697596522dc93d8906ff0454cfebf5..ee362d8464fc0a569e8b51ca1b08f88856dd3442 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 - Beniamino Galvani */ +#include #include #include #include diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c index 2af5587ec47a3e635c1d1218176f138af0b898f9..307ed1db8750ccc613b4fa36248570460136d6d5 100644 --- a/drivers/pinctrl/mscc/mscc-common.c +++ b/drivers/pinctrl/mscc/mscc-common.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-jr2.c b/drivers/pinctrl/mscc/pinctrl-jr2.c index 4ef4040cd702b99c3cf47b656dccec48bf10eb86..cb340581cc0f8758562c69161524caba9e21b35b 100644 --- a/drivers/pinctrl/mscc/pinctrl-jr2.c +++ b/drivers/pinctrl/mscc/pinctrl-jr2.c @@ -6,6 +6,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c index 7707350aace629ec5446ca8d3c78dc029ee06734..325c9a9705b252ec9d5d6e2af8e29861c2c65ace 100644 --- a/drivers/pinctrl/mscc/pinctrl-luton.c +++ b/drivers/pinctrl/mscc/pinctrl-luton.c @@ -7,6 +7,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c index 826388c2f7462b8783a562cf575d785b6a3f1a52..57e2ef0d7c16da5928057b9de55571818a8d8632 100644 --- a/drivers/pinctrl/mscc/pinctrl-ocelot.c +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-serval.c b/drivers/pinctrl/mscc/pinctrl-serval.c index 2081cd6750c86feea9115c04e15ec6b667b78fe4..a6b9796df81fc742e40c96bc0005a4d9bac38875 100644 --- a/drivers/pinctrl/mscc/pinctrl-serval.c +++ b/drivers/pinctrl/mscc/pinctrl-serval.c @@ -6,6 +6,7 @@ * Copyright (c) 2019 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/pinctrl/mscc/pinctrl-servalt.c b/drivers/pinctrl/mscc/pinctrl-servalt.c index efa4e26d9f721625a4a44c8cad1d0257cd855872..8e8678580db1dddf9421d6e6d4ca42ab726fb27b 100644 --- a/drivers/pinctrl/mscc/pinctrl-servalt.c +++ b/drivers/pinctrl/mscc/pinctrl-servalt.c @@ -6,6 +6,7 @@ * Copyright (c) 2019 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c index dc7acec4a77f6a767f339b4672e49ecb44de0ef1..79c63c7caec6caa6d5a0c4bd77e19147c5581a78 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mt7628.c +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c index bab34e97b615abc5aeced4010537c67782e3ba92..869b781068513ee192a474e0acf7fae4ea3117ed 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 64036296e24d74abcc3280ff0f216b1aa5d651cd..e834dddfd137d4e352db79509ccda940240cca09 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -16,6 +16,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 78184d2860a85dca0123dbe0e42bbae353e57eb9..252151f3e5d9acbc9075894cc37bb34cddd9e3f5 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later // (C) 2022 Pali Rohár +#include #include #include #include diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 0d5fa4ceb9ca38ebfa2a129722aeb3628e680d74..fd49a97b5b0a0945e7b7073204a70652e7d334e6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -4,6 +4,7 @@ * https://spdx.org/licenses */ +#include #include #include #include diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index d5be7baf50ddc06b5817870d593699af238fd19e..20497a746d26aa2c258c18cb4dce9f2022df5f9b 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -5,6 +5,7 @@ * Bongyu, KOO */ +#include #include #include #include diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index e7d0994f29e740cf90c6d42d2154b926ab1a8f74..863eb1455d239167292f67ea6bf8521d82de187d 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -7,6 +7,7 @@ * (C) Copyright 2019 Stefan Bosch */ +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index ff466c4910414db3ad8790cd59596a9836b29e28..1596dcc4747e6b645d803e17acd5d4f6abc5cdc7 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Peng Fan */ +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c index 6b690fdce8fd986a129c97b5ffa3dfef9914d7a8..b32b748cfc63cb95a6b7d12bb3fe29e3ecf7d7e3 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx5.c +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -4,6 +4,7 @@ * Copyright (C) 2016 Peng Fan */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 322eec87ff5d4ccaa7340d74e8ade2a5d45514c3..6994dbb61a3ddf74126f28e708b1175305604089 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -4,6 +4,7 @@ * Copyright (C) 2016 Peng Fan */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c index a8275e26456bb60d60df6e684d863ccfb7b33d49..77ddb8e0b9d515ce80a19ce38d5d39509bf88113 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Peng Fan */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c index 7ea2dbe7d36b6eb10d31c83f355a6ef1b09a87e2..6da9ff7c5bcea1a1de1da10fe3f92c527693218d 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 4e9a9ea6808621a54d3f79ec16f4b5917deba76d..46af44ecb1f22e71836968349d0a9bebd3d73b9d 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c index 73d3c009d5b6afce5760a4bb72de568c2de98864..4e8fa08bc6e3cfdc76e02fd252c2c93cddacc525 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c @@ -4,6 +4,7 @@ * */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c index 23f07f8d1e0535f636cac170f74e4379748b2913..53b70da869ecea1f777b60109d2418b9c63d4a1c 100644 --- a/drivers/pinctrl/nxp/pinctrl-imxrt.c +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index 85ab5fdf6404c97364370f7d8b74dbe1e44be2eb..eb90e28d4b21547b34beaeeb6bd7e93e914c1d5d 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c index 42d5c96468c7959626fb3f7d1279069653df2a36..4959834c0fcd37dcadec9fb5899c6c87f9c8b082 100644 --- a/drivers/pinctrl/nxp/pinctrl-scu.c +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -3,6 +3,7 @@ * Copyright 2018-2019 NXP */ +#include #include #include #include diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c index adf3073f1be087eb7992d93349bf2c5f4a2e7e74..14e2e9d3ee61c2a1a082b222523868330d14876e 100644 --- a/drivers/pinctrl/nxp/pinctrl-vf610.c +++ b/drivers/pinctrl/nxp/pinctrl-vf610.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include diff --git a/drivers/pinctrl/pinctrl-apple.c b/drivers/pinctrl/pinctrl-apple.c index f373afde58e41ce2917f421efd33a8bc67df7f43..62476358c349d5ce894f4ce240b9a4852bc19d41 100644 --- a/drivers/pinctrl/pinctrl-apple.c +++ b/drivers/pinctrl/pinctrl-apple.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index c697a4c3456ae4b8c1084930c7570a30c01024b4..84b398619c47cd569479b8c6e29ff14a6c31aac3 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -6,6 +6,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 5038cb535e38adb990532786ffd32f758da979f5..b7aab12f11c1b3fec523152df4a9d2f9e3b6e82d 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -6,6 +6,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 2464acf0b854f4001c5b8c9187dfd23a568b3afd..8909b57810af05c51f4cb46732e418a529d70442 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index dad036610c9e489eba6d49975f34fbb45f1bc9ec..ee35dfe142035b3e3a0a9c382fb6d0400ae9882e 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c index 61db9274cc3e854d76b29e46d189f6acc357b32a..dc0be7ce3bd6d1a39b48cbdbff307a9fde8d7190 100644 --- a/drivers/pinctrl/pinctrl-qe-io.c +++ b/drivers/pinctrl/pinctrl-qe-io.c @@ -6,6 +6,7 @@ * based on source code of Shlomi Gridish */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c index a5d056643a0fcfba178c217ceb434c38ad2a6478..776597745099745988347caa32720dca36b57798 100644 --- a/drivers/pinctrl/pinctrl-sandbox.c +++ b/drivers/pinctrl/pinctrl-sandbox.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index a3802d22d4f92cd644f6647de494c26c4207b1d1..d1db377c13799655a2a789bad24040f8c804095d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -4,6 +4,7 @@ * Copyright (C) 2021 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c index 4996b69d9afb07e471ec41fc56736bddcfc60fcc..1ff7ea00555104e67b0a69630d28f6ea0b68507b 100644 --- a/drivers/pinctrl/pinctrl-sti.c +++ b/drivers/pinctrl/pinctrl-sti.c @@ -6,6 +6,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 61f335c4eb14f054b3a4126ffd20e35a14d4f621..509e2a80e9a590c64ae807beb1c1b15d1860b63c 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_PINCTRL +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index d9c76898a9692d40b7cd4eecf7cb2edf9e93a209..b277ad5c48f9910d2f7f6907075c0f719b950c5d 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_PINCTRL +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 6fa203a3b8616e5add7998e27616de0d4c5115c3..eb17a4290b7d6716972b5fe6df1781ed62729145 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -8,6 +8,7 @@ * Copyright (C) 2021 Xilinx, Inc. All rights reserved. */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c index 9f38b56e9c0ed4d615b1ef5c04c3cb996b2517c3..54d97ac0ae37f5ab084be81e62f6de97be5d641a 100644 --- a/drivers/pinctrl/pinctrl_pic32.c +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -4,6 +4,7 @@ * Copyright (c) 2015 Microchip Technology Inc. * Written by Purna Chandra Mandal */ +#include #include #include #include diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index eada1001240cdc65a7c45b8aa7c6b18ff71edfc4..7120b8edba002d467a30e12640bdca519f7229bd 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_PINCTRL +#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 0c7437822ff20abef05a4526bfe0a8f6a3f596f3..b14a8921af4f39b39f066603b9ff24afffdf88c5 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -6,6 +6,7 @@ * */ +#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 132ece868bf2dbc0cd8805c59d90891db48bc67f..9697cb5beb7a0a30d9a10f3e556bc06c5fc5349a 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -6,6 +6,7 @@ * */ +#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 3215c677b263239d50d7c82f43d3c93ce5172d2f..26ab487857fef7c1702dfe96e4ba39eddfd7ea30 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -7,6 +7,7 @@ * Author: Robert Marko */ +#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 3c3336e76358cc61032d430814e31e33f5ef52c7..e68971b37ff094ad36cde82d57905d66d1d8d8a6 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index fb6defaeddf0237105e194ca9b4825b4a90528e4..4b7c670c90b7ab24f22602cd4fdee6e69aea8ee2 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -5,6 +5,7 @@ * (C) Copyright 2022 Sumit Garg */ +#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index f1a23f510999da4329074c15ab7ee5bbdf0fa44f..c1e5cc01fded493681f003326f746ddd61b21842 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -7,6 +7,7 @@ * */ +#include #include #include "pinctrl-qcom.h" diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index cc7885bae40802eccfc2cad377727da9ee899139..2c35491b24d86152a9992f08078278b15f2de8a7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index b14386ccd937d2fcced72b6c9be6f7809194d3c1..afcd34396e277e4e770dd2fd2c91926e6a514558 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3066.c b/drivers/pinctrl/rockchip/pinctrl-rk3066.c index 60e088a9a6f0d9133cd0822a9f4816cea18a524d..598b63223e364c57e27b25764a6df75c9b5b47df 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3066.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3066.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index d00fc3da8b234667a86d0afea10e47b700cb1e00..355c45eb7f8ccab930eb1186bebc8fba0d491fda 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 83db51f66ae43c713a3f80a5442d1f8467a918e9..9a982cbfad9ced0207080f7868b2e553364ecc78 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index b804597c048415f3875222b201442fc025b35658..351406da2d451af5a0c25320d16daa402fdb2c2d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 3870c1b7a341f998cc0b3cfcaa3a0acbdd0daa39..a976b7aeeb27f7bfe255b6c038f0b4adc4959ba2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index 2cd91b10a3bdbb55cf1e1a56a1b3a240a2899047..f9ac6347eaf15fbf839d9940794a14f43bd5c08c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 47c2e923a1bb5292bdbe934a91fdb78404c37327..65a750076773b361abc833f29a98ca564265271c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 9ae06ed19e9cda76f6d466fce2e01f48520a668a..ba867a891748741f788705b0bc94b1bf58b6f7d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index b7a5092c032ba3bac0889921d9421bf0d3cd7277..ae785573baf578cdd81b1c36df37fd4598f7a38c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index 5deedc648a41950461b6a468e4852fa0a5384207..1d439198260541bfd7542239ab339a042a27c21a 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -3,6 +3,7 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3588.c b/drivers/pinctrl/rockchip/pinctrl-rk3588.c index 98ababc7c90700c4b27359fc3625519f20437306..548cf09bcca4d49015c2683c5c2f8f73aeb06e20 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3588.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3588.c @@ -3,6 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 3e74e2f14895dd47c8c80f3cd459867bf897c477..8ef089994f467f74821601a68c024aa805f01f91 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 3eff5f59598c0d9ea9393a1b5e1a82efa8449eb6..5b70b503d2b12381194c1aa254c45c9b29eb3b19 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -3,6 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c index efa2408b204b421ad1c5a36b039d8c07c5b7237e..eefb8b17768b7d695deea74fa0139d2e6083982d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1126.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -3,6 +3,7 @@ * (C) Copyright 2020 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c index 95b1a752de2e337006dcc7cce3bf9ccd9f79291e..9b09cc21cfaa8e0633a89d36041260bf2a5a7049 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive.c @@ -7,6 +7,7 @@ * Author: Jianlong Huang */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra114.c b/drivers/pinctrl/tegra/funcmux-tegra114.c index 23e9e23836798a72df1b1744640e72c37b6bd55f..23a27c86888117b0140a837cb40a2f06f6455d9b 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra114.c +++ b/drivers/pinctrl/tegra/funcmux-tegra114.c @@ -5,6 +5,7 @@ /* Tegra114 high-level function multiplexing */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra124.c b/drivers/pinctrl/tegra/funcmux-tegra124.c index b041cead34462352f6ca692d81902248fb199226..e7ad85fde2d01f251eccf12b2d32558d070a7236 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra124.c +++ b/drivers/pinctrl/tegra/funcmux-tegra124.c @@ -6,6 +6,7 @@ /* Tegra124 high-level function multiplexing */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra20.c b/drivers/pinctrl/tegra/funcmux-tegra20.c index b8c9132378536be96178b9a54ec1d6a36e3ae27a..90fe0cba8ea44cd752cd4719470ff62e79e0465f 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra20.c +++ b/drivers/pinctrl/tegra/funcmux-tegra20.c @@ -4,6 +4,7 @@ */ /* Tegra20 high-level function multiplexing */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra210.c b/drivers/pinctrl/tegra/funcmux-tegra210.c index d52b6150e590f1c08ca0017f5eb4cd0c06151a78..30d994a17ffada40d817097aea86f25d812ccfac 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra210.c +++ b/drivers/pinctrl/tegra/funcmux-tegra210.c @@ -6,6 +6,7 @@ /* Tegra210 high-level function multiplexing */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/funcmux-tegra30.c b/drivers/pinctrl/tegra/funcmux-tegra30.c index e31b859beb8aca0e8980d038723e06556f9d5357..c3ee787f33b158674d764e1c8daa467f21da3905 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra30.c +++ b/drivers/pinctrl/tegra/funcmux-tegra30.c @@ -5,6 +5,7 @@ /* Tegra30 high-level function multiplexing */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-common.c b/drivers/pinctrl/tegra/pinmux-common.c index 5266c8db4876822832a9bfc6049dd608ed9d813a..16b03bfe7b068a4d044fd0cf305d5e2a80118699 100644 --- a/drivers/pinctrl/tegra/pinmux-common.c +++ b/drivers/pinctrl/tegra/pinmux-common.c @@ -4,6 +4,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra114.c b/drivers/pinctrl/tegra/pinmux-tegra114.c index 15c6b653aed88a88984e861eb598c29c6a41dc1a..11796602c548fbaa57ebe9f6a7163bc80d24f755 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra114.c +++ b/drivers/pinctrl/tegra/pinmux-tegra114.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra124.c b/drivers/pinctrl/tegra/pinmux-tegra124.c index 6d5b720aa0e63578073f976616c4b0864ade4d1a..261ce64b205ed90652bf425ada9ffabfec9bd6fc 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra124.c +++ b/drivers/pinctrl/tegra/pinmux-tegra124.c @@ -3,6 +3,7 @@ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra20.c b/drivers/pinctrl/tegra/pinmux-tegra20.c index c1f86476b9ef168d096244cfdc9c785d0998f050..0af39e74c53b927738979ee7281a4959f99cee0b 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra20.c +++ b/drivers/pinctrl/tegra/pinmux-tegra20.c @@ -5,6 +5,7 @@ /* Tegra20 pin multiplexing functions */ +#include #include #include diff --git a/drivers/pinctrl/tegra/pinmux-tegra30.c b/drivers/pinctrl/tegra/pinmux-tegra30.c index 59ce9cea4a97c61fd1043509b8dc4724d3a7512d..d11b2aa572dfac4cab02d941616168a3a2ee8c2d 100644 --- a/drivers/pinctrl/tegra/pinmux-tegra30.c +++ b/drivers/pinctrl/tegra/pinmux-tegra30.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index eafb65496a3d77c94f72a8a459a81c90e8a1f4d6..bdca3f2f715665a4e679f08e97888f1e243bdb73 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 778a9899483c8cbb905469af9fe84a62ec032866..a1a3cd73859a39354fbb2f4ec93a9d4f6a1611b7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 3ef10151dabfbc226d8f00678ec562c48adfe41a..7a92a46c17f5888b8d701e8683559c20484974e5 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 9302e309e20fdcc41218010da240452ab32af8a9..d33e4d7dd259d9a50a6a2a3615306862d07e6662 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index f7c5bf3bcaed7e4995b43eb8c6b16332901b4aaa..0e3eb131ecf799ac30914a30e25e5c61ee434baf 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 2704a50749e5182b7ccd7a15ee2d49f24598265a..7ba2266092f0b99f85ce8025f9e62faa80bfd0b2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 655ec6e6057332412aa7075a1e4543220094afe9..9ce2e2c270ef954d6aa81ff7c4e31df820a24823 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 226272c2b82f2d13b6e0adce61cc31477e313a31..e8c2018097c2691cc6ad900d36a6a289e75f5ae0 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 8df13ca209c7e83b1641220befe18b25d49e9ee4..8a8f1269bb51d65a7051d9541d216271534ff270 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -5,6 +5,7 @@ * Author: Dai Okamura */ +#include #include #include diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index c045ae99ac53366f49038a462cd7ab6d32cfe548..04c06fb280e269786bf98532e28e099bb8ab6cd7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada */ +#include #include #include diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c b/drivers/power/acpi_pmc/acpi-pmc-uclass.c index c289cede15b80176a844c78f16f80b17ec235ef8..34446a34e60d21778deae3938d8294f6aba8b20c 100644 --- a/drivers/power/acpi_pmc/acpi-pmc-uclass.c +++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC +#include #include #include #include diff --git a/drivers/power/acpi_pmc/pmc_emul.c b/drivers/power/acpi_pmc/pmc_emul.c index 8eff3d9fa7ac69b163a569c36a459a9bb2b6dc85..8015031da85926d6dc8d2bde3aeabdcdd41447b7 100644 --- a/drivers/power/acpi_pmc/pmc_emul.c +++ b/drivers/power/acpi_pmc/pmc_emul.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/power/acpi_pmc/sandbox.c b/drivers/power/acpi_pmc/sandbox.c index ed1bb1980931dac5bf6d3ae4bc221ad3fea552d0..8cf03f737c080069104f7c97cab2af60938cd75e 100644 --- a/drivers/power/acpi_pmc/sandbox.c +++ b/drivers/power/acpi_pmc/sandbox.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC +#include #include #include #include diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index 5a62382ab86e960ae026b0a4337db9102b5077d1..a93987c15382bdaf83c552b0f0602fc0238de99c 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -3,8 +3,8 @@ * (C) Copyright 2012 * Henrik Nordstrom */ +#include #include -#include #include #include diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 6ae416982ebe2ba17998ad9305dc61cdea43e0f0..3447b9f0113a12a5980de0ce61ed1d1f72d692da 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -4,11 +4,11 @@ * Henrik Nordstrom */ +#include #include #include #include #include -#include #ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_08 # define AXP209_VRC_SLOPE AXP209_VRC_LDO3_800uV_uS diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c index c22ca03f46948c9dba4e233ada1199d3860e9d8c..d251c314b9876ba8511bac5346e461ce543e7c34 100644 --- a/drivers/power/axp221.c +++ b/drivers/power/axp221.c @@ -9,6 +9,7 @@ * (C) Copyright 2013 Oliver Schinagl */ +#include #include #include #include diff --git a/drivers/power/axp305.c b/drivers/power/axp305.c index 0312ad9af763f643166fce940e93a6c4590c288b..049ef07f7467f878ecb7c5e021e46dc5d6f844eb 100644 --- a/drivers/power/axp305.c +++ b/drivers/power/axp305.c @@ -9,6 +9,7 @@ * (C) Copyright 2013 Oliver Schinagl */ +#include #include #include #include diff --git a/drivers/power/axp313.c b/drivers/power/axp313.c index 09ecb5b1ec2880d0417a1799b606af14cfe02532..bbc9e911115f1ab906650a0db239964e5a1367f5 100644 --- a/drivers/power/axp313.c +++ b/drivers/power/axp313.c @@ -10,6 +10,7 @@ * (C) Copyright 2013 Oliver Schinagl */ +#include #include #include #include diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c index 9e38e1a74508469a30eddf1191d90528981a5d0d..d327a584ded0373a11660c57847ab2d984907db3 100644 --- a/drivers/power/axp809.c +++ b/drivers/power/axp809.c @@ -10,6 +10,7 @@ * (C) Copyright 2013 Oliver Schinagl */ +#include #include #include #include diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index 83ae6ecc138d7da2df7ed739cdb475f47adcc1de..08286ea3b55077e710dd6527c89d80714990a46a 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -10,6 +10,7 @@ * (C) Copyright 2013 Oliver Schinagl */ +#include #include #include #include diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index bf9940621ee7f39392e45058165840cd4f6e7b5c..402c5b1fd18883bea376209faee2e2c78b1b6888 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c index 36b5a933748073e5aa774298a2fd07757e5a779c..80144dd977250b1d236e61e28b0a600b2e628dda 100644 --- a/drivers/power/domain/bcm6328-power-domain.c +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index 713a51d7807d1816b6c7d8687f45af9706ce76af..c8ca2665752fb9aa47765de2a57e32b2baca2d64 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -3,6 +3,7 @@ * Copyright 2017 NXP */ +#include #include #include #include diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index e8dcc057fee0071b43dc3792ec65d0ce87ec2b76..b45e468756bf4de8b0d5294ef034a372acb7d96b 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -4,6 +4,7 @@ */ #define DEBUG +#include #include #include #include diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 8b6870c8646335194cdc8edae34b944fde078f56..df5d7d695621af3fa1b70d21a39e5f6a96283e34 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -3,6 +3,7 @@ * Copyright 2017 NXP */ +#include #include #include #include diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c index 455ad53ef525e18ae45068fa5d8c2be8a1b79335..6188a04c45ed5a907268f1d1f00fbb0d34cedd54 100644 --- a/drivers/power/domain/imx8mp-hsiomix.c +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Marek Vasut */ +#include #include #include #include diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 20e9f32b3819b3ce067eb07009d8845778544df1..676fded8080ac57d3547fcf2b08c09a8d0e55f3b 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index 1c56e8508c3231549a3e829dd0dcfeb0f3cd1d6f..612660ce89f9a90d02cf2434d55bd8563019d626 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index 2d1ba1855a5bfb12158a7ae65168dc73f7b3300e..3b84147d48142f9909c00e900737712a78d83e8a 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 938bd8cbc9ffd1ba2109d702f886b6a99288d063..f6286c70c1d796173c3fda61c0e71a91526787f0 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_POWER_DOMAIN +#include #include #include #include diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c index 08c15ef342b3dd3ce01807ee59b7e97337f7dde5..1bf52f1d861c1b12b505563d2eff7e25f6dc00d4 100644 --- a/drivers/power/domain/sandbox-power-domain-test.c +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c index 9dd490b14a3f6e502baccd94d32704e4b6bd56ed..04a071044f3b5f6d01ab5c35eb1dc726a5a6eee1 100644 --- a/drivers/power/domain/sandbox-power-domain.c +++ b/drivers/power/domain/sandbox-power-domain.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c index 334c460c805f6fdc16948041b664267fd823020f..46da541b75a887ee82d882dfe276c45777c5d8dd 100644 --- a/drivers/power/domain/tegra186-power-domain.c +++ b/drivers/power/domain/tegra186-power-domain.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index b059dd37376d13a97d8239e5fa59068ca764a453..8996c40ddc03101be1d40ac250b024c97a7f1983 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c index 0a9f498b97b15173ce2b890c17ed89c3dc57734d..8d6abe13dbc6d3ccf0e500efb24674214a0ab99b 100644 --- a/drivers/power/domain/ti-sci-power-domain.c +++ b/drivers/power/domain/ti-sci-power-domain.c @@ -8,6 +8,7 @@ * Loosely based on Linux kernel ti_sci_pm_domains.c... */ +#include #include #include #include diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index ac93934eb42089cbe326667c8bfa79b101f66b78..5ee9e020fb3b658f5aeb2c7a2f4d1fe9b7a82353 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -3,6 +3,7 @@ * Copyright (c) 2021, Xilinx. Inc. */ +#include #include #include #include diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c index 21c2fabce1b888fa3cb127b22eebb955ddef46c5..6d62f6cae40d59588688e7b5ef4d88c5e1c5be2e 100644 --- a/drivers/power/exynos-tmu.c +++ b/drivers/power/exynos-tmu.c @@ -17,12 +17,11 @@ * MA 02111-1307 USA */ +#include #include #include #include -#include #include -#include #include #include diff --git a/drivers/power/mt6323.c b/drivers/power/mt6323.c index dd6cbcf18206573c0783d6e4397be3fb47b3e243..354817a037808d6dd3692b755793fb9e9fce6e52 100644 --- a/drivers/power/mt6323.c +++ b/drivers/power/mt6323.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Frank Wunderlich */ +#include #include #include #include diff --git a/drivers/power/pmic/ab8500.c b/drivers/power/pmic/ab8500.c index 9ba096711e14da01b62214da18644cb189b4e652..1f64f217c345fc9d1c24f21939f12c4bf5c4f759 100644 --- a/drivers/power/pmic/ab8500.c +++ b/drivers/power/pmic/ab8500.c @@ -7,6 +7,7 @@ * Copyright (C) ST-Ericsson SA 2010 */ +#include #include #include #include diff --git a/drivers/power/pmic/act8846.c b/drivers/power/pmic/act8846.c index 3058ef0f893d810c94f7a21538dfb88b9481db68..8f0f5a6d96e5ca63449d95ca174a8ff40df264a2 100644 --- a/drivers/power/pmic/act8846.c +++ b/drivers/power/pmic/act8846.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/power/pmic/as3722.c b/drivers/power/pmic/as3722.c index 9b0f4fb97363e1916419448ffd6dbe30a2dae593..c7dd9705d18960edf4bc4d54a0c0300cde7dc5a7 100644 --- a/drivers/power/pmic/as3722.c +++ b/drivers/power/pmic/as3722.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "as3722: " fmt +#include #include #include #include diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c index 52d8bd00b1fd8fa348c9f7e66db8cfb317cb22c0..987fbdf9bc08ab5e5b33155a121e3f5972fbb56b 100644 --- a/drivers/power/pmic/as3722_gpio.c +++ b/drivers/power/pmic/as3722_gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2014 NVIDIA Corporation */ +#include #include #include #include diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index a5df2570fc3e6a2dcaa4f1277c1a4fd341d66f63..ee6ae78e5c4c91e371de48d3ce8f423aae8274f8 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include #include #include #include diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c index 7bd3df391421c4d93743f696f8607981ec640c4f..ca95b82e6d0115db987adc771a571268b3f9bb06 100644 --- a/drivers/power/pmic/da9063.c +++ b/drivers/power/pmic/da9063.c @@ -4,6 +4,7 @@ * Martin Fuzzey */ +#include #include #include #include diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c index 95bf600cbc3fe4908bfdcfedd1ede2a69c3a4972..d556b9a5878a0dc7b977321cd2d75a9e5e5eb90b 100644 --- a/drivers/power/pmic/fan53555.c +++ b/drivers/power/pmic/fan53555.c @@ -3,6 +3,7 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c index 6e81b9c34279d9b2a70c3bd287973b97000bbbf5..f0a03742f87bc7cb1c34645686475905dd35351e 100644 --- a/drivers/power/pmic/i2c_pmic_emul.c +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -4,6 +4,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/pmic/lp873x.c b/drivers/power/pmic/lp873x.c index 2c8fa4ea312f2ac14aa39aa081f37e7118150377..fda5bc1516429ee8ec20ff4b9bbf40da893dbbb4 100644 --- a/drivers/power/pmic/lp873x.c +++ b/drivers/power/pmic/lp873x.c @@ -4,6 +4,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c index c2ff75bbcdcd9f2ecc8263c661d4f02904754381..904e02c4d818802150169151dcc9edf843be93bf 100644 --- a/drivers/power/pmic/lp87565.c +++ b/drivers/power/pmic/lp87565.c @@ -4,6 +4,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/pmic/max77686.c b/drivers/power/pmic/max77686.c index bfe57b386d3d2c5db525b0fa2cc5519f5ad4f4ef..7e6f7d1966f171a6fefa6578cab6433aa9cdd861 100644 --- a/drivers/power/pmic/max77686.c +++ b/drivers/power/pmic/max77686.c @@ -4,6 +4,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/pmic/max8997.c b/drivers/power/pmic/max8997.c index 4afa6c84ef82f986d95edc00255bbd029513f769..504a63bf743159c3feb3ba9c2853d7b8fe1557a3 100644 --- a/drivers/power/pmic/max8997.c +++ b/drivers/power/pmic/max8997.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/power/pmic/max8998.c b/drivers/power/pmic/max8998.c index 05669023753e8d17f5bd9e050bd93843d59d3f90..d155474447f5dec4c7249b0df4cf33de8764783b 100644 --- a/drivers/power/pmic/max8998.c +++ b/drivers/power/pmic/max8998.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 43badb5767a589c74e70529da159406905b6f66d..40d732224b6c2ee426dd5ae4cf200ab775ca0189 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c index 9d44f0ae655e843682d1286c9a795f402519fbcf..6180adf77e2d02d75e6fe66ff89bf9c9a03d7888 100644 --- a/drivers/power/pmic/mp5416.c +++ b/drivers/power/pmic/mp5416.c @@ -2,6 +2,7 @@ /* * Copyright 2020 Gateworks Corporation */ +#include #include #include #include diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index f676bf641694702ef0af739b0e688d964f4f1934..e340a32279fbf35445fd60ee38b78836307d434f 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -4,6 +4,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 07af6273d8aece5f94dccd7358539118deca004d..0bbe98cd8a29b5783b0fe057a1c7b2d26a5032cb 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/power/pmic/pfuze100.c b/drivers/power/pmic/pfuze100.c index 9e09805d251f1f1537215cb3388bd0958ad9fdb9..15420acb4725807be4c7f22e837118ab517869d5 100644 --- a/drivers/power/pmic/pfuze100.c +++ b/drivers/power/pmic/pfuze100.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c index bb459816d14381c8568588737c5f1fc442fb2abe..0e2f5e1f41111eff5342d46810fbb9d30c617003 100644 --- a/drivers/power/pmic/pmic-uclass.c +++ b/drivers/power/pmic/pmic-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PMIC +#include #include #include #include diff --git a/drivers/power/pmic/pmic_hi6553.c b/drivers/power/pmic/pmic_hi6553.c index 05305013882d70886db4d3869c634f49104bd76a..80b9078cf8f0732e0f798040c33aa1976d3623f0 100644 --- a/drivers/power/pmic/pmic_hi6553.c +++ b/drivers/power/pmic/pmic_hi6553.c @@ -4,6 +4,7 @@ * Peter Griffin */ #include +#include #include #include #include diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c index 145a631b6b24086ad885bdabe49d18a1b09c1c47..af94f37b0f108f79c9c10d1f850a0a137f4913a7 100644 --- a/drivers/power/pmic/pmic_ltc3676.c +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -4,6 +4,7 @@ * Tim Harvey */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_mc34vr500.c b/drivers/power/pmic/pmic_mc34vr500.c index 0dfdfbdf3dca1aa397489be4e75e49d3d90ac065..9dd1c46ea220bf3d258b597713b2d7b782b0097d 100644 --- a/drivers/power/pmic/pmic_mc34vr500.c +++ b/drivers/power/pmic/pmic_mc34vr500.c @@ -4,6 +4,7 @@ * Hou Zhiqiang */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_pca9450.c b/drivers/power/pmic/pmic_pca9450.c index 12500ba9990117d6ff08865455983d32f1ca2675..8c4d0a92306bde820c57454d1537ac5d130e6231 100644 --- a/drivers/power/pmic/pmic_pca9450.c +++ b/drivers/power/pmic/pmic_pca9450.c @@ -3,6 +3,7 @@ * Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index a266709d8d078990801458d65108e371585ec731..5115b55e49dc9c3d7af3eb8d3137a45cdee4b850 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -4,6 +4,7 @@ * Tim Harvey */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c index 602c4744aa6c2e57837c687f74d13cabcc24a159..a6d97252bc9e644de9f467864a6de9e82aed3bd4 100644 --- a/drivers/power/pmic/pmic_pfuze3000.c +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -4,6 +4,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c index 92d0a95859b0fed240363b04053e04efbb4a1f40..f2ac6494811ddbe8031285fe437faf930a80d0db 100644 --- a/drivers/power/pmic/pmic_qcom.c +++ b/drivers/power/pmic/pmic_qcom.c @@ -4,6 +4,7 @@ * * (C) Copyright 2015 Mateusz Kulikowski */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c index 4f0e406d560626d28950859c32757306c0d07126..6426d1488a5c2bee1f8ca1cf3f6d009fa314baba 100644 --- a/drivers/power/pmic/pmic_tps62362.c +++ b/drivers/power/pmic/pmic_tps62362.c @@ -4,6 +4,7 @@ * Author: Felipe Balbi */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c index bd44e0d9ae05150d1123998d3c9be43d47db8af1..ccbf2235933da9862f96f7e8d4d192743dd42533 100644 --- a/drivers/power/pmic/pmic_tps65217.c +++ b/drivers/power/pmic/pmic_tps65217.c @@ -4,6 +4,7 @@ * Texas Instruments, */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index 49d07e95cd7ce04c839aa460e88cb6d537581aca..6717490180413e03bbfb82689fbf44ca8734cfcb 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -4,6 +4,7 @@ * Texas Instruments, */ +#include #include #include #include diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c index df9bb66a7f9ca2d5605010f01d24edf1a3a079a1..e3de73082150244ef58e92a633db596b486c25e8 100644 --- a/drivers/power/pmic/pmic_tps65910.c +++ b/drivers/power/pmic/pmic_tps65910.c @@ -4,6 +4,7 @@ * Texas Instruments, */ +#include #include #include diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c index de8d805566aacdddfb19a04f17f7d6548968c0c6..ecf836eb0e659002ad64f5f0696ed6f69758eda7 100644 --- a/drivers/power/pmic/pmic_tps65910_dm.c +++ b/drivers/power/pmic/pmic_tps65910_dm.c @@ -3,6 +3,7 @@ * Copyright (C) EETS GmbH, 2017, Felix Brack */ +#include #include #include #include diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 12ff26a08558e7e2dc5bfb9bbc387ccd1dd8339b..3a8261d1749f053afec82825a255349e64490c6c 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c index 0124d84a7295bf7a3da8058c41e411c81a9dc07d..9d103dd840578bcf549be799a5024f3b3f33c684 100644 --- a/drivers/power/pmic/rn5t567.c +++ b/drivers/power/pmic/rn5t567.c @@ -4,6 +4,7 @@ * Stefan Agner */ +#include #include #include #include diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c index 17780017035bc2f8c6b672976eb4d25e484307b7..5ff4f20521135c31bd34582df52c2d3141e0e14b 100644 --- a/drivers/power/pmic/s2mps11.c +++ b/drivers/power/pmic/s2mps11.c @@ -4,6 +4,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c index 799d00125409efa350f476b07a978a6a6a8ab8a4..eea072ae824f4be635279cb1130a9f1a4a09e21e 100644 --- a/drivers/power/pmic/s5m8767.c +++ b/drivers/power/pmic/s5m8767.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/power/pmic/sandbox.c b/drivers/power/pmic/sandbox.c index ddc11d6df86f810b821bd81430f4609e9e996e05..14b82455f5fbc80b96bf9458adba700dc77c7b35 100644 --- a/drivers/power/pmic/sandbox.c +++ b/drivers/power/pmic/sandbox.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PMIC +#include #include #include #include diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index c99a0c27b3360ad5f13655f99380f56c660cf0f4..8701d4f971c9ba04c4101b54205d6255e37801e2 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/power/pmic/tps65090.c b/drivers/power/pmic/tps65090.c index ad2ab34719e5b08bdd2e6c9ab6f7850bc84fb83c..2a04d5948a5e4d407c399f068743ba383d3b1edc 100644 --- a/drivers/power/pmic/tps65090.c +++ b/drivers/power/pmic/tps65090.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/power/pmic/tps65219.c b/drivers/power/pmic/tps65219.c index 0716af027a3ad5fcd871a7aa65b1199ea644b27d..9462afee77fd6e9a3099ab19964634e74aa31fc8 100644 --- a/drivers/power/pmic/tps65219.c +++ b/drivers/power/pmic/tps65219.c @@ -4,6 +4,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index c3490db2a089850db40cf205fe52cb32a26a6bab..943d845086c3b6101d6a7d48b76acf53e6e1b92e 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -4,6 +4,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 1caf9f0934689c042d5bc0ec2f72e45a13f19b48..4f7ba099cd917baf8c2bb4a4846f6e15c7eb3c6c 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -9,6 +9,7 @@ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c index a5c7ea34c4ae436b92a6b0a904f08979cbbc6fc9..ad7aaf35a9a0279965a2196e88970d35e5372853 100644 --- a/drivers/power/power_dialog.c +++ b/drivers/power/power_dialog.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #include #include diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index a10a14a79616ca1c65a7aa168434a96e6a1d1d42..9dc930fb305aecb0302408447349f34b52f854cd 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -4,7 +4,7 @@ * Lukasz Majewski */ -#include +#include #include #include #include diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index a871fc4198722c0b60cc02a07934f03108b7e908..b67ac2f027b59c8ccf13862585cf6ea737d00bdf 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -10,6 +10,7 @@ * (C) Copyright 2019 NXP */ +#include #include #include #include diff --git a/drivers/power/power_spi.c b/drivers/power/power_spi.c index 54427316ce42f2163767e12b475ac5a3602a837f..1eaf9773ef8b35aa93a472575e46254462a7ba63 100644 --- a/drivers/power/power_spi.c +++ b/drivers/power/power_spi.c @@ -9,6 +9,7 @@ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/power/regulator/act8846.c b/drivers/power/regulator/act8846.c index d3e72da0d35a8b0a0b4272136d3b54c45f56bcdb..bdce97365dd00c448b3bac915be8e234451d4418 100644 --- a/drivers/power/regulator/act8846.c +++ b/drivers/power/regulator/act8846.c @@ -8,6 +8,7 @@ * zyw */ +#include #include #include #include diff --git a/drivers/power/regulator/anatop_regulator.c b/drivers/power/regulator/anatop_regulator.c index 824a753db16122c16dcc1ac1fa3fc940a06fa543..096a1565d5a7f5b150445edfa0f3be5cd1aea008 100644 --- a/drivers/power/regulator/anatop_regulator.c +++ b/drivers/power/regulator/anatop_regulator.c @@ -4,6 +4,7 @@ * Copyright (C) 2021 Linaro */ +#include #include #include #include diff --git a/drivers/power/regulator/as3722_regulator.c b/drivers/power/regulator/as3722_regulator.c index 8d60965fe9ac2dab11ee0c885704379f4e013c59..ec0776b440bb8a80ffc4f375c156a68f9797d65b 100644 --- a/drivers/power/regulator/as3722_regulator.c +++ b/drivers/power/regulator/as3722_regulator.c @@ -6,6 +6,7 @@ * Placeholder regulator driver for as3722. */ +#include #include #include #include diff --git a/drivers/power/regulator/bd71837.c b/drivers/power/regulator/bd71837.c index 59aec1a7313e16b2301315564aa6fc2f2fd95b26..913ed88d45f79079a6e41fb45f31abcceaa23d61 100644 --- a/drivers/power/regulator/bd71837.c +++ b/drivers/power/regulator/bd71837.c @@ -5,6 +5,7 @@ * ROHM BD71837 regulator driver */ +#include #include #include #include diff --git a/drivers/power/regulator/da9063.c b/drivers/power/regulator/da9063.c index 5d566b06a522824ec0c3060606e49b2607641915..8df1abcf7885cb38fdf0054586902773acb54128 100644 --- a/drivers/power/regulator/da9063.c +++ b/drivers/power/regulator/da9063.c @@ -4,6 +4,7 @@ * Martin Fuzzey */ +#include #include #include #include diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c index 5cba58f91cacdd8556060f62153bfefbc190fca3..fa8d88f2e0dc5e45a990b45ecc07f8dcda268ebc 100644 --- a/drivers/power/regulator/fan53555.c +++ b/drivers/power/regulator/fan53555.c @@ -3,6 +3,7 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 98c89bf2aff687a69e5b22419e7b9b4b5e852a4d..590c288d6575f7e7282e89a416db784426cbcf15 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -5,6 +5,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c index 38b22535c3dd4998a2670d9a1b1d24dc1e47519d..74137b7b876fd7b6201891d85739247633893ac6 100644 --- a/drivers/power/regulator/gpio-regulator.c +++ b/drivers/power/regulator/gpio-regulator.c @@ -4,6 +4,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/regulator/lp873x_regulator.c b/drivers/power/regulator/lp873x_regulator.c index c59d77118adad8436b86ca34b3581a8a9073eba3..c326f8efa471cc04d85fe0c47efde2b6eed79d7f 100644 --- a/drivers/power/regulator/lp873x_regulator.c +++ b/drivers/power/regulator/lp873x_regulator.c @@ -6,6 +6,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c index d622d9568156787db12ec9ad6d46cbad18121deb..6bbc831d2c8ab46f78c34cad4b81640c6da73b2c 100644 --- a/drivers/power/regulator/lp87565_regulator.c +++ b/drivers/power/regulator/lp87565_regulator.c @@ -6,6 +6,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/regulator/max77686.c b/drivers/power/regulator/max77686.c index 4e0ba12a0ef880d0477fc2d587a518f43c157537..3a20803993403b2e4601f32db78b7d19dd5ba7b0 100644 --- a/drivers/power/regulator/max77686.c +++ b/drivers/power/regulator/max77686.c @@ -6,6 +6,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/regulator/npcm8xx_regulator.c b/drivers/power/regulator/npcm8xx_regulator.c index 30d1b8945cb7e6430447464848abf74ad216b99b..fcd1058cdf521bd2fa2544e9fc979bc484745c2d 100644 --- a/drivers/power/regulator/npcm8xx_regulator.c +++ b/drivers/power/regulator/npcm8xx_regulator.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c index 2286eac93fbe5e850b910f7bb0c89a91d8958ae7..d615e9473403e4dc82b87666a7e947f9b2e20dee 100644 --- a/drivers/power/regulator/palmas_regulator.c +++ b/drivers/power/regulator/palmas_regulator.c @@ -6,6 +6,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/regulator/pbias_regulator.c b/drivers/power/regulator/pbias_regulator.c index 8f599cab68999500ccee1aebd8feb576be00d8ff..cf4e2858443da2771e287ce5088fc488c13fec1b 100644 --- a/drivers/power/regulator/pbias_regulator.c +++ b/drivers/power/regulator/pbias_regulator.c @@ -4,6 +4,7 @@ * Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/drivers/power/regulator/pca9450.c b/drivers/power/regulator/pca9450.c index 9faf1eab5f90739e85e901cdd52ce9aa2156d322..7ca20d1f7f87191c3493803b24d0573cfcd2c6ce 100644 --- a/drivers/power/regulator/pca9450.c +++ b/drivers/power/regulator/pca9450.c @@ -7,6 +7,7 @@ * ROHM BD71837 regulator driver */ +#include #include #include #include diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index bf3a7019411e764a19b5ceb0dc259dfd76152369..1d926689b3b012d55757f2cddb7c67709b3726bf 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -5,6 +5,7 @@ * Peng Fan */ +#include #include #include #include diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index ff738faadc52d0e7847d3e3f8b6e9167b25d82a8..ca59f3ae3e18ceae3f36a818c26548b17b29faf8 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -7,6 +7,7 @@ * Author: Lee Jones */ +#include #include #include #include diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 66fd531da043c867d2c836566cecbb19ef968272..77d101f262e2708ee5a8ea9375860b099c0814f2 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_REGULATOR +#include #include #include #include diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index e3565d32a019b3cd7a447d98afb29b2754a099b2..0116fa01bbfe19fe9ed2d40a3509ee13dcce2b87 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -4,6 +4,7 @@ * Sven Schwermer */ +#include #include #include #include diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index bf3af781527913af3845375de13ee3db1ac4600a..1bd4605d43a06c9c9cf8f77d4b6147ed08b5130c 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -8,6 +8,7 @@ * zyw */ +#include #include #include #include diff --git a/drivers/power/regulator/s2mps11_regulator.c b/drivers/power/regulator/s2mps11_regulator.c index 96de55065feb06fdb86d7b3f056b5a65f97dda16..987a1f9d8638af32bb4c28973cd494c2f885eb92 100644 --- a/drivers/power/regulator/s2mps11_regulator.c +++ b/drivers/power/regulator/s2mps11_regulator.c @@ -4,6 +4,7 @@ * Jaehoon Chung */ +#include #include #include #include diff --git a/drivers/power/regulator/s5m8767.c b/drivers/power/regulator/s5m8767.c index 0dcf0990802b8a946a91f0e14c819dc5e233d4c5..23575831f382e98d6843ae9a557daa39d873b709 100644 --- a/drivers/power/regulator/s5m8767.c +++ b/drivers/power/regulator/s5m8767.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/power/regulator/sandbox.c b/drivers/power/regulator/sandbox.c index 80a68f5a30d52e709295a2f06a1c098eaccf31f2..71ef0c5441afda9661f673144c816def70bb4783 100644 --- a/drivers/power/regulator/sandbox.c +++ b/drivers/power/regulator/sandbox.c @@ -4,6 +4,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 99f6506f162874f2b778795c104a3250a8c74f55..9c72c35d039e7e97d606700b69606553443967e7 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_REGULATOR +#include #include #include #include diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c index dd8a33f15bea08f4a261109118e85710daca18b1..c37998a4bac4b06313d098dfd6b2eeb95f016eaf 100644 --- a/drivers/power/regulator/stm32-vrefbuf.c +++ b/drivers/power/regulator/stm32-vrefbuf.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_REGULATOR +#include #include #include #include diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c index b5ffa1cd5895e3fa2f3979694ef20ce42d0ce058..4839d834316a8320eb2e9e57c5c99e22789464ad 100644 --- a/drivers/power/regulator/stpmic1.c +++ b/drivers/power/regulator/stpmic1.c @@ -4,6 +4,7 @@ * Author: Christophe Kerello */ +#include #include #include #include diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c index 9acc6b9054979852427823624476cc8c25af9c40..7014b1982d0012943fcfa9743fc10f349c8406b8 100644 --- a/drivers/power/regulator/tps62360_regulator.c +++ b/drivers/power/regulator/tps62360_regulator.c @@ -4,6 +4,7 @@ * Tero Kristo */ +#include #include #include #include diff --git a/drivers/power/regulator/tps65090_regulator.c b/drivers/power/regulator/tps65090_regulator.c index 2d414de149079daa8f83e080e1de9f8fcdc99361..fa15e61a10e013d935f10e535a5356a1cc4d4b37 100644 --- a/drivers/power/regulator/tps65090_regulator.c +++ b/drivers/power/regulator/tps65090_regulator.c @@ -3,10 +3,10 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include -#include #include #include #include diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index b7124fed02450249172a9aacd75d75ae9d9f2a01..f87d07e61fbff09f55ef7cac8da2c562e94e4e8a 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/power/regulator/tps65910_regulator.c b/drivers/power/regulator/tps65910_regulator.c index 562fd7db1908bef3d33b8f748248c02878dab6c4..a4b9d449274bc50f9effc29b55d42ce1e2f04920 100644 --- a/drivers/power/regulator/tps65910_regulator.c +++ b/drivers/power/regulator/tps65910_regulator.c @@ -3,6 +3,7 @@ * Copyright (C) EETS GmbH, 2017, Felix Brack */ +#include #include #include #include diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index bc4d153fd84437b79b4c8046a5664abbd285d2ab..5809a53fa214c5cb92980cf818f37060fe499f00 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -6,6 +6,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c index fb6028de71af34ae9df02dd7c4a5890a987ba0eb..45f47939869af317dd5df8313450457f7b97d139 100644 --- a/drivers/power/sy8106a.c +++ b/drivers/power/sy8106a.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 * Jelle van der Waa */ +#include #include #include diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 4034a9b49dd08dbad4de13857eacd0f2dd5d0051..37f1c459a6373333e0deb792a592819fdebb9763 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -4,12 +4,12 @@ * (C) Copyright 2010,2011 NVIDIA Corporation */ +#include #include #include #include #include #include -#include static struct udevice *tps6586x_dev; diff --git a/drivers/pwm/cros_ec_pwm.c b/drivers/pwm/cros_ec_pwm.c index b89f00f151b083f010d5b4b924ed1e18d15e180b..4a39c319aa2a704e04c73609c7b72567ac821fd8 100644 --- a/drivers/pwm/cros_ec_pwm.c +++ b/drivers/pwm/cros_ec_pwm.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/pwm/exynos_pwm.c b/drivers/pwm/exynos_pwm.c index 5ded60978f476ada941d338f4fb264cbd6fcafdf..609025d680d2cc7f4f8e1a9d817a96ffebd962ab 100644 --- a/drivers/pwm/exynos_pwm.c +++ b/drivers/pwm/exynos_pwm.c @@ -3,6 +3,7 @@ * Copyright 2016 Google Inc. */ +#include #include #include #include diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c index ebc9d9a89752f4b9c255e79ba48a26f80e18d9b4..b03472d2345ca5678a89f9fd1537a0b6f7d9f498 100644 --- a/drivers/pwm/pwm-aspeed.c +++ b/drivers/pwm/pwm-aspeed.c @@ -38,6 +38,7 @@ * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. */ +#include #include #include #include diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c index ffc37180eb42bb72627bcca73cbf1fb3612355f7..3ff1fb6d5c30b3c43cb1ec3a1b3598181d576d5b 100644 --- a/drivers/pwm/pwm-at91.c +++ b/drivers/pwm/pwm-at91.c @@ -9,6 +9,7 @@ * Based on drivers/pwm/pwm-atmel.c from Linux. */ #include +#include #include #include #include diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c index 767628833bc0660407337b2434ec1775f527ee51..d9f6736a7aee737824aadb277d4579ea19c9d4f0 100644 --- a/drivers/pwm/pwm-cadence-ttc.c +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PWM #include +#include #include #include #include diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 320ea7c4239ab605f1e50f01734d0767c9a597c8..8fbb40cc276708e2137f64ece59eb4e99a54920a 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -6,6 +6,7 @@ * Basic support for the pwm module on imx6. */ +#include #include #include #include diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index c2597d8b6698bb582248fbfd3fcd88a2bd509a6e..60959720dac8ad1d9f5ed3f98fac36036a67831c 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -16,6 +16,7 @@ * current period to complete first). */ +#include #include #include #include diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c index 9776a41ff48e36af5d88249067caca90e8613db3..ad845ed9662e5540a99f9d526cac720ba7534696 100644 --- a/drivers/pwm/pwm-mtk.c +++ b/drivers/pwm/pwm-mtk.c @@ -5,6 +5,7 @@ * Author: Sam Shih */ +#include #include #include #include diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index e9777c71f5e0b845bbaebdaf71185b5509059cf9..b9813a3b6bbeadda0990223af5d391375654a382 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -12,6 +12,7 @@ * - The hardware generates only inverted output. */ +#include #include #include #include diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c index 563109ef0f806e74fd6e15d952e1de5a91e0e3a8..fefa3c65ec450ae8795d834ce12c35f5da271c50 100644 --- a/drivers/pwm/pwm-ti-ehrpwm.c +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -7,6 +7,7 @@ * Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c */ +#include #include #include #include diff --git a/drivers/pwm/pwm-uclass.c b/drivers/pwm/pwm-uclass.c index 6543db1d623d1c0d86eb4ab7a5e841b6d9f893fd..648d0757ba620b51a9ddcb6d29ae618431c130be 100644 --- a/drivers/pwm/pwm-uclass.c +++ b/drivers/pwm/pwm-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PWM +#include #include #include diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 0a64eb01dc2bad5e1e7a9a4a65f929270564f764..1858d5973386095e13d3fe10812881874b637aae 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/pwm/sandbox_pwm.c b/drivers/pwm/sandbox_pwm.c index 0d798609ddafe45fc9d3ff9ef6de23dc7701bfdb..4df15f0a2e8fbfa76e1d39cd6ce935d36f897f22 100644 --- a/drivers/pwm/sandbox_pwm.c +++ b/drivers/pwm/sandbox_pwm.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c index 2140a05b6796bbcf1c99b5a5024103aa1102a48c..bb1bec05ec34a3c8ea23c029592c9658179c09ad 100644 --- a/drivers/pwm/sunxi_pwm.c +++ b/drivers/pwm/sunxi_pwm.c @@ -3,6 +3,7 @@ * Copyright (c) 2017-2018 Vasily Khoruzhick */ +#include #include #include #include diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index e3f1417f2ad050f295d20743ce134fb0de4822c6..87034706060c306704a17d7c9f7b543f7237776c 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -3,6 +3,7 @@ * Copyright 2016 Google Inc. */ +#include #include #include #include diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index 0d6ab79f96fc0535afefc96aec382cf6132cf2ce..dc466a88e71232f55ccde1c2ac73f53d99b9e55d 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -5,7 +5,7 @@ * Copyright 2016 Google, Inc */ -#include +#include #include #include #include diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 55e80fba3dc0beced1b7129310fd574ea1e626e4..d463933363ee4494e2261db37a20f13b829726b3 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -2,7 +2,7 @@ /* * Copyright (C) ASPEED Technology Inc. */ -#include +#include #include #include #include diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c index 760bebdbba04111f2a795dfac11a898bc535e531..98045248ecfb12403fc90afddd40cafe5fc6bb73 100644 --- a/drivers/ram/bmips_ram.c +++ b/drivers/ram/bmips_ram.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c index 0fa60e766a7e611734aeccf0c4292fcd69a35184..3e5959a84a37061fb7291beba6580bcf1d5131eb 100644 --- a/drivers/ram/cadence/ddr_ctrl.c +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -24,6 +24,7 @@ * bandwidth allocated to each AXI slave can be set. */ +#include #include #include #include diff --git a/drivers/ram/imxrt_sdram.c b/drivers/ram/imxrt_sdram.c index 3df106c9b79ad76055cb67fefa601d67767c9878..6a15242c20cc5327d9afb67845a7aa4736303837 100644 --- a/drivers/ram/imxrt_sdram.c +++ b/drivers/ram/imxrt_sdram.c @@ -4,6 +4,7 @@ * Author(s): Giulio Benetti */ +#include #include #include #include diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 21ff9d761e1bb17a34fd2c6446c78a7c7a0bc75a..cff8ffc89295d23c494fa0070fb64e3f17943b40 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -6,6 +6,7 @@ * Lokesh Vutla */ +#include #include #include #include diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 525b6d5b79fce18819946e1714e98290057ccccf..a5c9b82cf1dae59a5518c0f719d4169ad2838bdb 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -5,6 +5,7 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index c27c4593b9d90894d6864b51566da49c0cb22e93..f65fcf179cf65b4fd58647e6df482ee3aeabbb2f 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index 28a663289a23d0ecadaa2ff14987d6132e6f4569..11676d4fae7e1d44de1ff495230bfd02ea7b4080 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/ram/ram-uclass.c b/drivers/ram/ram-uclass.c index a33d583cc4486dd5bcd7e8edc826e8693a6c6add..4e21240fd4cb8f95415320afad68e8c5faf7f482 100644 --- a/drivers/ram/ram-uclass.c +++ b/drivers/ram/ram-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/renesas/rzn1/ddr_async.c b/drivers/ram/renesas/rzn1/ddr_async.c index 4d470aae1914c104f117107a45fa70bb32add21c..7a81497bc92b1c2e2fdb5bb8b29d3b7bf60e0c7f 100644 --- a/drivers/ram/renesas/rzn1/ddr_async.c +++ b/drivers/ram/renesas/rzn1/ddr_async.c @@ -7,6 +7,7 @@ * * Copyright (C) 2015 Renesas Electronics Europe Ltd */ +#include #include #include #include diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 42114a5aa917118f0978d8cf30da0afce86c2ba7..5279bf0a15485d7f4d612b77abbfa065dd35af61 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -3,7 +3,7 @@ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index b7a8fce607c8d9afb2ddbbbdfc9bfc7c0f3d0e8a..60fc90d0a5c02c0f9e68cb693fabcc055d18ed99 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -3,7 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_pctl_px30.c b/drivers/ram/rockchip/sdram_pctl_px30.c index 3ec98af536e8bd588ca34694e5611924aad7c1ca..e5c80fb83b3f3019c8222287fde1a686e9e008b7 100644 --- a/drivers/ram/rockchip/sdram_pctl_px30.c +++ b/drivers/ram/rockchip/sdram_pctl_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_phy_px30.c b/drivers/ram/rockchip/sdram_phy_px30.c index 5416eef387888401108eb2328d8d5d41c085c233..f7f6de1ba98bb322a377e5db9008f5a74da83556 100644 --- a/drivers/ram/rockchip/sdram_phy_px30.c +++ b/drivers/ram/rockchip/sdram_phy_px30.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index 37e621205047404729b6742d0873e8443c83beb3..21498e89570f666b3fa0e1d0ce70158168028f3b 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -3,7 +3,7 @@ * (C) Copyright 2018 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index a280e2d9fa1d585da7154db23f429167e8f8c0b2..562cf544c909e800fb6478fae7bd0292a94f08d3 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -6,7 +6,7 @@ * Adapted from the very similar rk3188 ddr init. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 66611f80b2dad90a374733eefa8f82eca9608794..ded65393806e00d6a5497af3b522dd474fbcc98c 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -3,7 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 618bce5c9f49ce7fda4434439f73292ebe48f384..e1b28c6e5933431a4d4d263fc092e36a708e2d94 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -6,7 +6,7 @@ * Adapted from the very similar rk3288 ddr init. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index a48a50911844d9c14e06a8bf8c50e3d58ab75a2e..5fc23c11193ffac5ed51bc390fe80dded4ee57a3 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index c9f61e933e9a45bb157d474ea29a2554bf556fe0..242d564a7d2663c6cc620a897624e5663c3f6aa2 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -6,7 +6,7 @@ * Adapted from coreboot. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 8071997f8d86abc13eaefbee0ada8cd2ab05f8fd..264366291cf8b1ef1a237b888ce32013840b7c7c 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -3,7 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 99690d67a501160fe3717f00e54860cb1714bbc2..b5ca8ca436f57990e5aa290b64e7732c57d595e3 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -2,7 +2,7 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index ef9a1824b2b338862266e0abc66da816bcc1bb64..02cc4a38cf0bd1152595a63059e1bed83c053cdc 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -5,7 +5,7 @@ * Adapted from coreboot. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c index a252d5c7010616ee88ecab2f60f23e09c5a39689..f661615c1b91efada8ab7e02dff4d36043dd71ac 100644 --- a/drivers/ram/rockchip/sdram_rk3568.c +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -3,7 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rk3588.c b/drivers/ram/rockchip/sdram_rk3588.c index a144b432d76ff5065af12b98b2561696d77603da..cf56e2a941218518ee0c8bd580540e6e559c44cf 100644 --- a/drivers/ram/rockchip/sdram_rk3588.c +++ b/drivers/ram/rockchip/sdram_rk3588.c @@ -3,7 +3,7 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c index 4fbb088a8d98cf8983231903e57d1766feaf6045..849e15a91932f527088e8392caf455560a68c27b 100644 --- a/drivers/ram/rockchip/sdram_rv1126.c +++ b/drivers/ram/rockchip/sdram_rv1126.c @@ -4,7 +4,7 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include +#include #include #include #include diff --git a/drivers/ram/sandbox_ram.c b/drivers/ram/sandbox_ram.c index 2097da565322c56c1153a456c13923223f51e407..910dce623e90d75b6342973ee91c983abe9c9cd1 100644 --- a/drivers/ram/sandbox_ram.c +++ b/drivers/ram/sandbox_ram.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c index bd2f438d7271be2a2eb98af8142a2d4f40b2ca94..4bd69a62be2b690c0e0db3f9f2b203ca76416e5a 100644 --- a/drivers/ram/sifive/sifive_ddr.c +++ b/drivers/ram/sifive/sifive_ddr.c @@ -6,6 +6,7 @@ * Pragnesh Patel */ +#include #include #include #include diff --git a/drivers/ram/starfive/ddrcsr_boot.c b/drivers/ram/starfive/ddrcsr_boot.c index 6764b3ed5cc918a56979c85d34c85f1a998ebd61..f2dd55f74a08ceef18df7083f988e76f28cd99da 100644 --- a/drivers/ram/starfive/ddrcsr_boot.c +++ b/drivers/ram/starfive/ddrcsr_boot.c @@ -4,6 +4,7 @@ * Author: Yanhong Wang */ +#include #include #include #include diff --git a/drivers/ram/starfive/ddrphy_start.c b/drivers/ram/starfive/ddrphy_start.c index efe3f8a181a54f0671efadbf0ea5eda78d761d83..479b6ef10418d250031030d59a926a8fad65ce91 100644 --- a/drivers/ram/starfive/ddrphy_start.c +++ b/drivers/ram/starfive/ddrphy_start.c @@ -4,6 +4,7 @@ * Author: Yanhong Wang */ +#include #include #include "starfive_ddr.h" diff --git a/drivers/ram/starfive/ddrphy_train.c b/drivers/ram/starfive/ddrphy_train.c index 0aff1e8727efc26934034c60c23de52c95c1e20c..0740f49be5bbcd124d18cd1dfc727cf029024924 100644 --- a/drivers/ram/starfive/ddrphy_train.c +++ b/drivers/ram/starfive/ddrphy_train.c @@ -4,7 +4,7 @@ * Author: Yanhong Wang */ -#include +#include #include static const u32 ddr_train_data[] = { diff --git a/drivers/ram/starfive/ddrphy_utils.c b/drivers/ram/starfive/ddrphy_utils.c index d6dd6ee7a859af770da5c3ecf5cbad4beaa4adc2..1c9fe0a78465635cb4715b45259b5f9e463ea55d 100644 --- a/drivers/ram/starfive/ddrphy_utils.c +++ b/drivers/ram/starfive/ddrphy_utils.c @@ -4,7 +4,7 @@ * Author: Yanhong Wang */ -#include +#include #include static const u32 ddr_phy_data[] = { diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index b31ed3bcf617326436e88440238c805ae0669b73..a0a3d6b33dc236a596013a677656f9a29c336ae7 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -4,6 +4,7 @@ * Author: Yanhong Wang */ +#include #include #include #include diff --git a/drivers/ram/starfive/starfive_ddr.h b/drivers/ram/starfive/starfive_ddr.h index c29d26b510c9c436cf7d4c0da8183cc4b569ea89..d0ec1c1da807195357349da40ed7d68f333807a6 100644 --- a/drivers/ram/starfive/starfive_ddr.h +++ b/drivers/ram/starfive/starfive_ddr.h @@ -7,8 +7,6 @@ #ifndef __STARFIVE_DDR_H__ #define __STARFIVE_DDR_H__ -#include - #define SEC_CTRL_ADDR 0x1000 #define PHY_BASE_ADDR 0x800 #define PHY_AC_BASE_ADDR 0x1000 diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 10dc05dd640418dfda9304afdc62577a13fa44dc..891f4137813ee08383a950ba5d61c3f61bd7be98 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index d7834b3229929e44bd55781d1f6a0d214b8d4b8c..8ee4e24f39df232d9517bfa05481007eabc3bdd7 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index 6340afbb87093313ef0e05ebad1cd36cd0d55d3d..2c19847c663343f8ce5c25d7fdb2cab6edc89f5c 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index debc458c0e2e9454a2552793ff3691527323798c..a82b1db7592df7fbd39ebd9f6c639a305f1982f6 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index 6108faa70730cea425568a331503c38fe7baad40..c5f33544144f1c1f80108cee02c39aa47255216f 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RAM +#include #include #include #include diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c index a1794032f3b8b8b1938168a93a9684b629ac8eca..38379281d73954973b9d7c5a02bbd4ea684935aa 100644 --- a/drivers/ram/sunxi/dram_sun20i_d1.c +++ b/drivers/ram/sunxi/dram_sun20i_d1.c @@ -13,7 +13,7 @@ */ #include -#include +#include #ifdef CONFIG_RAM #include #include diff --git a/drivers/reboot-mode/reboot-mode-gpio.c b/drivers/reboot-mode/reboot-mode-gpio.c index 22ee40c343338022a3c2921a779b32930748a653..305174736ede7a2d0a732fa6f1fa0bc9df6a4b10 100644 --- a/drivers/reboot-mode/reboot-mode-gpio.c +++ b/drivers/reboot-mode/reboot-mode-gpio.c @@ -3,6 +3,7 @@ * Copyright (c), Vaisala Oyj */ +#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-nvmem.c b/drivers/reboot-mode/reboot-mode-nvmem.c index b9af242520a0b312d7be72668a8f15b28103a20a..da41ca41d9a1c2dc1530d58efbc959acb06aee8a 100644 --- a/drivers/reboot-mode/reboot-mode-nvmem.c +++ b/drivers/reboot-mode/reboot-mode-nvmem.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Sean Anderson */ +#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-rtc.c b/drivers/reboot-mode/reboot-mode-rtc.c index 4f4ad63febc106acd7f40de8757fe0db95bf6bee..972d0cdbcb5b23ee0a088b184575732e16490747 100644 --- a/drivers/reboot-mode/reboot-mode-rtc.c +++ b/drivers/reboot-mode/reboot-mode-rtc.c @@ -3,6 +3,7 @@ * Copyright (c), Vaisala Oyj */ +#include #include #include #include diff --git a/drivers/reboot-mode/reboot-mode-uclass.c b/drivers/reboot-mode/reboot-mode-uclass.c index 7cbe02eb4ed487d97ca71877c898660ea440b19d..2b38aa26b859d72b6270151228db1f53a44672b5 100644 --- a/drivers/reboot-mode/reboot-mode-uclass.c +++ b/drivers/reboot-mode/reboot-mode-uclass.c @@ -3,6 +3,7 @@ * Copyright (c), Vaisala Oyj */ +#include #include #include #include diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c index 2ca78b550a7e8d8f9a8e2a195a576987cd0edf47..996e658e8718e71bfb83907eb6fa62bde9cdf472 100644 --- a/drivers/remoteproc/ipu_rproc.c +++ b/drivers/remoteproc/ipu_rproc.c @@ -8,6 +8,7 @@ * Keerthy */ +#include #include #include #include diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c index 71238a6058a4c711764817b53de9e6ff7b6ea061..071de40fbd6f782f77f43b604d9919b505318e88 100644 --- a/drivers/remoteproc/k3_system_controller.c +++ b/drivers/remoteproc/k3_system_controller.c @@ -6,6 +6,7 @@ * Lokesh Vutla */ +#include #include #include #include diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 9aec138637bc08fc00bc424df4f318a973265024..6ec55e27d9dd64f1a845c16a88b42f469ac3313f 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -6,6 +6,7 @@ * Keerthy */ +#include #include #include #include @@ -398,12 +399,10 @@ static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) { u32 mask2 = 0x38000; - if (device_is_compatible(dev, "ti,am654-rtu") || - device_is_compatible(dev, "ti,am642-rtu")) + if (device_is_compatible(dev, "ti,am654-rtu")) mask2 = 0x6000; - if (device_is_compatible(dev, "ti,am654-tx-pru") || - device_is_compatible(dev, "ti,am642-tx-pru")) + if (device_is_compatible(dev, "ti,am654-tx-pru")) mask2 = 0xc000; if ((priv->pru_iram & mask2) == mask2) @@ -449,9 +448,6 @@ static const struct udevice_id pru_ids[] = { { .compatible = "ti,am654-pru"}, { .compatible = "ti,am654-rtu"}, { .compatible = "ti,am654-tx-pru" }, - { .compatible = "ti,am642-pru"}, - { .compatible = "ti,am642-rtu"}, - { .compatible = "ti,am642-tx-pru" }, {} }; diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c index ab1836b3f0789c3f1d28a3e20c777391dca92aec..5e070e5076e1c06f37e0575bc52e40af1a420f0d 100644 --- a/drivers/remoteproc/rproc-elf-loader.c +++ b/drivers/remoteproc/rproc-elf-loader.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 3ba2b40dca38e0eefee27d5f2c847586c8b2cba6..aa7f7586a8141eb010fa0711fd9f555d2f5c9039 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_REMOTEPROC #define pr_fmt(fmt) "%s: " fmt, __func__ +#include #include #include #include diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c index ad575a7c10fdb399c77f4f01b8167a8ae71574a2..f76f68ebeb434112a12e61ed6b3f694abcb541a5 100644 --- a/drivers/remoteproc/sandbox_testproc.c +++ b/drivers/remoteproc/sandbox_testproc.c @@ -4,6 +4,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ +#include #include #include #include diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c index f45da9a68ac6eaeef0c5a563785a2b9433430b7e..3e322c4d7191a61c8d58b5d5d8c39b58f96b71e2 100644 --- a/drivers/remoteproc/stm32_copro.c +++ b/drivers/remoteproc/stm32_copro.c @@ -4,6 +4,7 @@ */ #define LOG_CATEGORY UCLASS_REMOTEPROC +#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c index d3eb957b2e4957f2dcbf3e7d4a5c8d1983f4dbda..767493c1383c2c08ed8fb7da9dbb43887de68ec6 100644 --- a/drivers/remoteproc/ti_k3_arm64_rproc.c +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 076b6f2acdbdc409849ab2acae6ee1f62c768e3c..ed13729c33a4861c7f7e3311e8b8d30d2b239041 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -7,6 +7,7 @@ * Suman Anna */ +#include #include #include #include diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 74bf0433e12ac765f191950e1f0911794376b68c..35835b2d61c23e25a6398c87c706d9ae45eaf4a1 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -7,6 +7,7 @@ * Suman Anna */ +#include #include #include #include diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c index cf150af4ef97897322f89fc18bc314812fac1eb6..f55df4a91195dcd9010b20345387020117110bc0 100644 --- a/drivers/remoteproc/ti_power_proc.c +++ b/drivers/remoteproc/ti_power_proc.c @@ -4,6 +4,7 @@ * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ +#include #include #include #include diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index 0ed5396b3e91ba912bca2e2d97d250d4ad40cc4d..d9cecf3a72e8aa59ad704654aac0dfc8a0145b8f 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -4,6 +4,7 @@ * Copyright 2020 ASPEED Technology Inc. */ +#include #include #include #include diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index ec7b9b6625dc5bb910a0dbd0bf08f45f8e36f32c..1732a450efc07a16569ca83578a2c323a87ad710 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -3,6 +3,7 @@ * Copyright 2020 ASPEED Technology Inc. */ +#include #include #include #include diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index 6f140574216d4a59a7b836b5ea7baa4f92498df6..5383f59ca375f6176585857c2912fdfdbc2e4da8 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -6,6 +6,7 @@ * Copyright (C) 2012 Jonas Gorski */ +#include #include #include #include diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index 2f0ec4c042f73d1da94b2eda16c57ed9d2cca401..05101a94f9bcc86a101ff07dae4526677ccbe236 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/reset/reset-hisilicon.c b/drivers/reset/reset-hisilicon.c index aca54cd6701c126dda873b7b9f308b2d2bcb6f05..85e02b296b02b0a9018542e62fa404813b2590db 100644 --- a/drivers/reset/reset-hisilicon.c +++ b/drivers/reset/reset-hisilicon.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c index 747e73b17fcb982fbc45fd5b6be2e51a95272430..74b1173e8878b26e2730b89effdb4569d79562e5 100644 --- a/drivers/reset/reset-hsdk.c +++ b/drivers/reset/reset-hsdk.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 65a352b71fd7698f5c35d090b7e7db952bf58352..a3b3132f2fae5712036aa1e8995b01c684698882 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/reset/reset-jh7110.c b/drivers/reset/reset-jh7110.c index adf722d5871ad4a95d1588cb4e8518ef42d6ccdd..d6bdf6bb00c4ac7808be49b2bc966ca42ad054bd 100644 --- a/drivers/reset/reset-jh7110.c +++ b/drivers/reset/reset-jh7110.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c index 4b3afab92ea7f2036264b4a56b4bb252aef7979f..97ed221f739a939f614b8f466ef1fad7da1e652d 100644 --- a/drivers/reset/reset-mediatek.c +++ b/drivers/reset/reset-mediatek.c @@ -6,6 +6,7 @@ * Weijie Gao */ +#include #include #include #include diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 6337cdaaffa2ba5b1d8ee72693ff752ff372fba5..9d0c8b354f4a0e182fdecc9bf31d17f48d2871c2 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c index 2db6766280f2934a060fa7934095af3c99a20a3c..7bb8469823c88c898889403366330942839bfae6 100644 --- a/drivers/reset/reset-mtmips.c +++ b/drivers/reset/reset-mtmips.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c index 1792f0813f79d7d1ca92a2301bcb53e4c596df5c..804e32b8dd140b21b18d1039e1a794984d9763b5 100644 --- a/drivers/reset/reset-raspberrypi.c +++ b/drivers/reset/reset-raspberrypi.c @@ -4,6 +4,7 @@ * * Copyright (C) 2020 Nicolas Saenz Julienne */ +#include #include #include #include diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c index 876eb7dddaa867ea840c52a395f41427b35ab5c6..6cabaa10a35badce22757bdc4254e66de8ae0543 100644 --- a/drivers/reset/reset-rockchip.c +++ b/drivers/reset/reset-rockchip.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c index 6dc1fcb336533e69c508d2fefae49c582504c455..b76711f0a8fb6f2825b05baeddcc821002c81cd3 100644 --- a/drivers/reset/reset-scmi.c +++ b/drivers/reset/reset-scmi.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RESET +#include #include #include #include diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c index 65f857149b963918850577603787a928797164ea..23513b2f541b4b0cbd30198f47a2b949efc24705 100644 --- a/drivers/reset/reset-sifive.c +++ b/drivers/reset/reset-sifive.c @@ -4,6 +4,7 @@ * Author: Sagar Kadam */ +#include #include #include #include diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 866437fd24fe829509bf9d8a419d292e381824a1..6e3f03e2484344ccb32073ced94ca55361bfe84f 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -12,6 +12,7 @@ * Maxime Ripard */ +#include #include #include #include diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index fd47e1f9e377e4e782cdc9c731f885a0f7b613e8..e484d1fff449ff22063eaf0b9ee53e33e963ebe3 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -4,6 +4,7 @@ * Author: Jagan Teki */ +#include #include #include #include diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c index 5be8c9492af247b68e976413b300ea6e688c21b6..ff387ab6b22f68d6af29b8fe53d70741a230c769 100644 --- a/drivers/reset/reset-syscon.c +++ b/drivers/reset/reset-syscon.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c index e69bcd41cbe88f1da8ebb7cd3ed1ac256eda5df2..fd654a08f13a2ec86dc1d6a8317dc1538644673b 100644 --- a/drivers/reset/reset-ti-sci.c +++ b/drivers/reset/reset-ti-sci.c @@ -8,6 +8,7 @@ * Loosely based on Linux kernel reset-ti-sci.c... */ +#include #include #include #include diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index fe4cebf54f1587b49ad527cf127079891867a682..b972faf01328313dcf75d7f4ea1d949a30b05396 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RESET +#include #include #include #include diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 49b001f05942e9acf74ea3e4c002bac284b3cea8..35e3ccebd72e6271ad49816be975139e86143a25 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -5,6 +5,7 @@ * Author: Kunihiko Hayashi */ +#include #include #include #include diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index b9c4f09fdfde9fbe0fefcd66c4e40a3b98039b91..87b4df5bf81accfe89610a88d2cf69bd09cbd595 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RESET +#include #include #include #include diff --git a/drivers/reset/rst-rk3588.c b/drivers/reset/rst-rk3588.c index eae2eb10de24ff51b9500a9b57f2cf89a29f2736..2c524e4c40332a48a56ca4b5a5082ada5ca2f45f 100644 --- a/drivers/reset/rst-rk3588.c +++ b/drivers/reset/rst-rk3588.c @@ -5,6 +5,7 @@ * Author: Sebastian Reichel */ +#include #include #include #include diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c index dfacb764bc775a641c70611959c218543b317626..51b79810c89ec1ba8bc911c2ae4e5566d71fd7b9 100644 --- a/drivers/reset/sandbox-reset-test.c +++ b/drivers/reset/sandbox-reset-test.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index adf9eedcba6dcd6cc8fae388756e0a909e343e99..97b1b92e4a6ca313d21fc78c01b3bd55f25b0087 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index 412a0c5b452bc4ad4a6a8b50a7f886da3cc3d728..5305270fbf20c10167c96cf88cb2d2c9aa20fa59 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 9d4f361b25193be84b0908be197fbd344e65b05a..0bbde29810b44f859d6ba6f9c4c4a945df4de2cb 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_RESET +#include #include #include #include diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c index e3ecc8d373577f2365dd7412e2cea50be4a559b1..501e9cab8f7c20662d0cdc018628116a80605317 100644 --- a/drivers/reset/tegra-car-reset.c +++ b/drivers/reset/tegra-car-reset.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c index 89624227c29383346eb366ec5802cb6fd6c05977..d43da454114ded3f3debfb78c5eea0fee0b5780a 100644 --- a/drivers/reset/tegra186-reset.c +++ b/drivers/reset/tegra186-reset.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/drivers/rtc/abx80x.c b/drivers/rtc/abx80x.c index 1235b840ab0418e684a632a6dc06872630c31f28..823aff03f5f02a86c43d4d25817271b3217c6ac7 100644 --- a/drivers/rtc/abx80x.c +++ b/drivers/rtc/abx80x.c @@ -12,6 +12,7 @@ * */ +#include #include #include #include diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index a20b73e1990a1df5c0226e9ebf556324caf168e1..c7ce41bbf5cc4a6017c06c215feda490eaa1afe0 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -4,6 +4,7 @@ * Heiko Schocher * Copyright (C) 2021 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index ba06ff9f0beed27b7e050e2876d63ef46d58f77b..0e9d3d24dd89721998a9fa7355499b4cc7c26b16 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -13,7 +13,7 @@ * based on ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 7eccf1cb8c54c203415405cb4649ebb57713ff45..2c780ab8edfadaaac853cb35de0ecb76a83b40be 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -11,7 +11,7 @@ * DS1337 Real Time Clock (RTC). */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 895dbbaf1c7499810f03cc2e9600e48d82e3f64e..89442f9386ba8b5e10d15ae3448d7ea769b62808 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -13,7 +13,7 @@ * based on ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index d6267d660d0d6c7247f0ef7f2bccd51e90c00bb7..bd32ed2dbf91b5a70b334de2aa18b0e037ce6c1f 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -14,7 +14,7 @@ * copied from ds1337.c */ -#include +#include #include #include #include diff --git a/drivers/rtc/ds3232.c b/drivers/rtc/ds3232.c index 7314ba219dac416c0b60264d1556538b97b9e36c..16501cfe5d3fc346879c0d870777eb33beb4fec4 100644 --- a/drivers/rtc/ds3232.c +++ b/drivers/rtc/ds3232.c @@ -3,6 +3,7 @@ * (C) Copyright 2019, Vaisala Oyj */ +#include #include #include #include diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 97a8d9bb7df50bb08de57b1374aa97b4a0efd075..6f47d82522baf83d0041eb2cbbef29dd28e57cfb 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -5,11 +5,11 @@ * This driver emulates a real time clock based on timer ticks. */ +#include #include #include #include #include -#include #include /** diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c index c202261e99990ea2392b864fce4a98707d9c9454..85fcee3e71e66ff9872420dda88104d8ec4782aa 100644 --- a/drivers/rtc/ht1380.c +++ b/drivers/rtc/ht1380.c @@ -15,6 +15,7 @@ * */ +#include #include #include #include diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index ea11c72c964c952b08a7354df0d003f66f316526..c307d6036dd5b87ca4fc256a47d3938ccdbb980e 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -13,6 +13,7 @@ * time-keeping. It does not change the system time. */ +#include #include #include #include diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c index 83db505afe9e9b1e2a3c423ac7c245c44bf038d6..59a60b75b3072cb533e8e94c1d41c6e420514e95 100644 --- a/drivers/rtc/isl1208.c +++ b/drivers/rtc/isl1208.c @@ -11,6 +11,7 @@ * ISL1208 Real Time Clock (RTC). */ +#include #include #include #include diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 7bfea9e0b3151e57fc6d7d29b6daf5f0e450734d..891fe09d311b31fc94af723c7826bda2b6f629b1 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -16,7 +16,7 @@ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/rtc/mc13xxx-rtc.c b/drivers/rtc/mc13xxx-rtc.c index 9e396bcdae95489583798019ef8d4eb236776849..6c2aef89758bbf5a65ef79fa91ebbcc5f9fed195 100644 --- a/drivers/rtc/mc13xxx-rtc.c +++ b/drivers/rtc/mc13xxx-rtc.c @@ -3,6 +3,7 @@ * Copyright (C) 2008, Guennadi Liakhovetski */ +#include #include #include #include diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index c0d86c6d063d6694de3d2e5fbd229605ae30c02c..03ce081d5764c7989ed0e0d44c6d144b5e0d308d 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -8,6 +8,7 @@ * Date & Time support for the MC146818 (PIXX4) RTC */ +#include #include #include #include diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index b5cc6b968816f6c67558795db6b8f444bd54a753..d2ac889c3095edba6a89440236696721199ec803 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -4,6 +4,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ +#include #include #include diff --git a/drivers/rtc/mvrtc.c b/drivers/rtc/mvrtc.c index f070c681b94e582e6faecda27a672dbb5b1dedeb..50240d57fa9e8da66ba456b265b2d3268d5fcfcd 100644 --- a/drivers/rtc/mvrtc.c +++ b/drivers/rtc/mvrtc.c @@ -8,6 +8,7 @@ * Date & Time support for Marvell Integrated RTC */ +#include #include #include #include diff --git a/drivers/rtc/mxsrtc.c b/drivers/rtc/mxsrtc.c index 69d22a4bdcb6b6019d9ea4e9448bcdb1fdc4f4ca..be899a925408c3f6ccfba9c9fab399fb89296926 100644 --- a/drivers/rtc/mxsrtc.c +++ b/drivers/rtc/mxsrtc.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c index 27a340f07d68bf0bb68b96c9e27e66f8b8f4a2bd..2f3fafb4968fac960c381c75ab35834d4490759a 100644 --- a/drivers/rtc/pcf2127.c +++ b/drivers/rtc/pcf2127.c @@ -5,6 +5,7 @@ /* #define DEBUG */ +#include #include #include #include diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 03bef68051ba4fa7ed732b253fce7a60465f8a35..91a412440b85124c14f1e3de0b3e3ee92dee8fe8 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -10,7 +10,7 @@ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index 855ee9134168c9c93be610262cf6f379626625aa..a1d376611d6578e2be63ebb376bcacec62f920de 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -6,6 +6,7 @@ * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c */ +#include #include #include #include diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index 79df07814a6b82231daceb258d1d351e8fc4f57a..e0a7bd3662fbda8316e3631b5f56920f8f6c2990 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -18,7 +18,7 @@ * It has 56 bytes of nonvolatile RAM. */ -#include +#include #include #include #include diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index 8f6c0c6a0a78702398e84207b5197ccab794fb95..e5ae6ea4d5f3cf4aa55ed5c771c64f91e0f7db9e 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_RTC +#include #include #include #include diff --git a/drivers/rtc/rv3029.c b/drivers/rtc/rv3029.c index a82acec6f7e5496940c06e3947adf9526f18d836..3afe5b2fdd678568b847c3606cd925f38d65897a 100644 --- a/drivers/rtc/rv3029.c +++ b/drivers/rtc/rv3029.c @@ -7,8 +7,10 @@ * Michael Buesch */ +#include #include #include +#include #include #include #include diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c index 82b43722ff514aa1ddca2e48039e06d1a2f2573a..06a4ae89fa961e788a5f8fc8f1385e6398ab288b 100644 --- a/drivers/rtc/rv8803.c +++ b/drivers/rtc/rv8803.c @@ -10,6 +10,7 @@ * */ +#include #include #include #include diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index 0d778f4c328e20f8d06b63fe5867740f0c6c1336..bf93b557748b96e3523caebc10245f8a5961cd7e 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -17,7 +17,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index c7895244283cf315207b9344484036f88402743f..1394c2306a445f5326ba29446fe0589340f24859 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -8,6 +8,7 @@ * Epson RX8025 RTC driver. */ +#include #include #include #include diff --git a/drivers/rtc/s35392a.c b/drivers/rtc/s35392a.c index 03fb9a0be9144344fef9596fda082a7c6a6c8fce..80f55c86233a7ad8c1184416a755f805e42962c9 100644 --- a/drivers/rtc/s35392a.c +++ b/drivers/rtc/s35392a.c @@ -18,6 +18,7 @@ */ #include +#include #include #include #include diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 4404501c2f65c3ac0ac2409bf8752d353bd93857..657e5c7be2cfb6d7e60c744753a76cbf50c383a1 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index ee70c11c8bcb4f181bea29cd02eeed88d739d5fa..ec7584c3d70c3af3dcabe1fe96aa1ccf62eeb49c 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RTC +#include #include #include #include diff --git a/drivers/rtc/zynqmp_rtc.c b/drivers/rtc/zynqmp_rtc.c index 15122a0483825263ac06f01e441de3739874c75b..ab9b93ca97933e52778365cf2a3d5195c4456a2c 100644 --- a/drivers/rtc/zynqmp_rtc.c +++ b/drivers/rtc/zynqmp_rtc.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_RTC +#include #include #include #include diff --git a/drivers/scsi/sandbox_scsi.c b/drivers/scsi/sandbox_scsi.c index 544a0247083d9da954a0679ae97ac65f536dfe9e..a7ac33cb1c4b17f8f2163bcb553bd7c8c4f4ca6a 100644 --- a/drivers/scsi/sandbox_scsi.c +++ b/drivers/scsi/sandbox_scsi.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_SCSI +#include #include #include #include diff --git a/drivers/scsi/scsi-uclass.c b/drivers/scsi/scsi-uclass.c index 1ee8236c05c8fba244371ae32788e7d9b5b69b9d..a7c1eaf0cf50d1ab85b9a7b8c3ef5cc1b61429b2 100644 --- a/drivers/scsi/scsi-uclass.c +++ b/drivers/scsi/scsi-uclass.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY UCLASS_SCSI +#include #include #include diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 73cb83548eb83de0d45e045aca7a2e7092f14d11..79ee400d12f0094eb8f4f894cce985c27db60bfc 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SCSI +#include #include #include #include diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c index 28e4612f337c4524637be2d185762e9ff0bcd73d..218221fa30622704c22ab29ab02121bb0095eef3 100644 --- a/drivers/scsi/scsi_bootdev.c +++ b/drivers/scsi/scsi_bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/scsi/scsi_emul.c b/drivers/scsi/scsi_emul.c index d1bb926b713a9b36d99d9131ee136d004f71b5e0..6b8468f79947ff43b5f7d93df350daacdbee06b7 100644 --- a/drivers/scsi/scsi_emul.c +++ b/drivers/scsi/scsi_emul.c @@ -11,6 +11,7 @@ #define LOG_CATEGORY UCLASS_SCSI +#include #include #include #include diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dbe598b74064805a1e451edc6df6bedc3eaea8c4..403ab1ded68a379359f2ca49660ad0d59cdbc2ca 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -65,4 +65,3 @@ obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o endif -obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 3f706e1839f2937dd6b86fa8fa73023c4626c9ec..9e39da7dd24619ca84a9e899dc200e5d69a7b43f 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -4,6 +4,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index 3c13ef25bb492a0a342c572b9fb3e11a6535ca54..35920480841a8beffa5ea6a26bb2bdc9476e18c9 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -4,6 +4,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 66af136695d086d1b7d74e9abf05c90417adf32b..a402a123b6d66c81d2689e960b54fb5e8b9f4265 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -15,6 +15,7 @@ * this file might be covered by the GNU General Public License. */ +#include #include #include diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 7e45a80969e8935b06064b0d6985a8acbb0a327d..9827c006fa88b3df1944445917a5d5dc056e0ecc 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -5,6 +5,7 @@ * Modified to support C structur SoC access by * Andreas Bießmann */ +#include #include #include #include diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 4963385dc1c17bdeaa922134617a02c480f7c61c..6deb1d8ddc56c59ebda43de19500deaf2e023058 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index ec0068e33d34696db5416cf2912ec0f9f5387d1b..f6ac3d228526a6cd59994e26f47deabb3a51cead 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -9,6 +9,7 @@ * U-Boot. */ +#include #include #include #include diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 84f02f7ac76a270c5836b3e5a0eef35a23f5702e..e4fa3933bc8ffc1744e665025cfb9f1897e0863e 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -5,7 +5,7 @@ #define LOG_CATEGORY UCLASS_SERIAL -#include +#include #include #include #include diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dc4bb06fa992edc0e6eeae22d340c8232fc34eec..787edd5360277ca0300edd22dcccfd0f0231494f 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c deleted file mode 100644 index 45f8315d0a07d90312ff6965f4e736cf217a27c3..0000000000000000000000000000000000000000 --- a/drivers/serial/serial_adi_uart4.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Converted to driver model by Nathan Barrett-Morrison - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - * - */ - -#include -#include -#include -#include -#include -#include - -/* - * UART4 Masks - */ - -/* UART_CONTROL */ -#define UEN BIT(0) -#define LOOP_ENA BIT(1) -#define UMOD (3 << 4) -#define UMOD_UART (0 << 4) -#define UMOD_MDB BIT(4) -#define UMOD_IRDA BIT(4) -#define WLS (3 << 8) -#define WLS_5 (0 << 8) -#define WLS_6 BIT(8) -#define WLS_7 (2 << 8) -#define WLS_8 (3 << 8) -#define STB BIT(12) -#define STBH BIT(13) -#define PEN BIT(14) -#define EPS BIT(15) -#define STP BIT(16) -#define FPE BIT(17) -#define FFE BIT(18) -#define SB BIT(19) -#define FCPOL BIT(22) -#define RPOLC BIT(23) -#define TPOLC BIT(24) -#define MRTS BIT(25) -#define XOFF BIT(26) -#define ARTS BIT(27) -#define ACTS BIT(28) -#define RFIT BIT(29) -#define RFRT BIT(30) - -/* UART_STATUS */ -#define DR BIT(0) -#define OE BIT(1) -#define PE BIT(2) -#define FE BIT(3) -#define BI BIT(4) -#define THRE BIT(5) -#define TEMT BIT(7) -#define TFI BIT(8) -#define ASTKY BIT(9) -#define ADDR BIT(10) -#define RO BIT(11) -#define SCTS BIT(12) -#define CTS BIT(16) -#define RFCS BIT(17) - -/* UART_EMASK */ -#define ERBFI BIT(0) -#define ETBEI BIT(1) -#define ELSI BIT(2) -#define EDSSI BIT(3) -#define EDTPTI BIT(4) -#define ETFI BIT(5) -#define ERFCI BIT(6) -#define EAWI BIT(7) -#define ERXS BIT(8) -#define ETXS BIT(9) - -DECLARE_GLOBAL_DATA_PTR; - -struct uart4_reg { - u32 revid; - u32 control; - u32 status; - u32 scr; - u32 clock; - u32 emask; - u32 emaskst; - u32 emaskcl; - u32 rbr; - u32 thr; - u32 taip; - u32 tsr; - u32 rsr; - u32 txdiv_cnt; - u32 rxdiv_cnt; -}; - -struct adi_uart4_platdata { - // Hardware registers - struct uart4_reg *regs; - - // Enable divide-by-one baud rate setting - bool edbo; -}; - -static int adi_uart4_set_brg(struct udevice *dev, int baudrate) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - struct uart4_reg *regs = plat->regs; - u32 divisor, uart_base_clk_rate; - struct clk uart_base_clk; - - if (clk_get_by_index(dev, 0, &uart_base_clk)) { - dev_err(dev, "Could not get UART base clock\n"); - return -1; - } - - uart_base_clk_rate = clk_get_rate(&uart_base_clk); - - if (plat->edbo) { - u16 divisor16 = (uart_base_clk_rate + (baudrate / 2)) / baudrate; - - divisor = divisor16 | BIT(31); - } else { - // Divisor is only 16 bits - divisor = 0x0000ffff & ((uart_base_clk_rate + (baudrate * 8)) / (baudrate * 16)); - } - - writel(divisor, ®s->clock); - return 0; -} - -static int adi_uart4_pending(struct udevice *dev, bool input) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - struct uart4_reg *regs = plat->regs; - - if (input) - return (readl(®s->status) & DR) ? 1 : 0; - else - return (readl(®s->status) & THRE) ? 0 : 1; -} - -static int adi_uart4_getc(struct udevice *dev) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - struct uart4_reg *regs = plat->regs; - int uart_rbr_val; - - if (!adi_uart4_pending(dev, true)) - return -EAGAIN; - - uart_rbr_val = readl(®s->rbr); - writel(-1, ®s->status); - - return uart_rbr_val; -} - -static int adi_uart4_putc(struct udevice *dev, const char ch) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - struct uart4_reg *regs = plat->regs; - - if (adi_uart4_pending(dev, false)) - return -EAGAIN; - - writel(ch, ®s->thr); - return 0; -} - -static const struct dm_serial_ops adi_uart4_serial_ops = { - .setbrg = adi_uart4_set_brg, - .getc = adi_uart4_getc, - .putc = adi_uart4_putc, - .pending = adi_uart4_pending, -}; - -static int adi_uart4_of_to_plat(struct udevice *dev) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - fdt_addr_t addr; - - addr = dev_read_addr(dev); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - plat->regs = (struct uart4_reg *)addr; - plat->edbo = dev_read_bool(dev, "adi,enable-edbo"); - - return 0; -} - -static int adi_uart4_probe(struct udevice *dev) -{ - struct adi_uart4_platdata *plat = dev_get_plat(dev); - struct uart4_reg *regs = plat->regs; - - /* always enable UART to 8-bit mode */ - writel(UEN | UMOD_UART | WLS_8, ®s->control); - - writel(-1, ®s->status); - - return 0; -} - -static const struct udevice_id adi_uart4_serial_ids[] = { - { .compatible = "adi,uart4" }, - { } -}; - -U_BOOT_DRIVER(serial_adi_uart4) = { - .name = "serial_adi_uart4", - .id = UCLASS_SERIAL, - .of_match = adi_uart4_serial_ids, - .of_to_plat = adi_uart4_of_to_plat, - .plat_auto = sizeof(struct adi_uart4_platdata), - .probe = adi_uart4_probe, - .ops = &adi_uart4_serial_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c index 4d92752690fc9d477c4401f615497ed017367284..4f9163497626f9cfea1a2c4c350c8311c355da36 100644 --- a/drivers/serial/serial_ar933x.c +++ b/drivers/serial/serial_ar933x.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index c0930cf7334ae2f95e7d09178f8ac27f2023c74e..c2fc8a901e257b34c62c3baebed277ef00ad23d3 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index 7fa26244b1cac30bf1a8e8ed8da545eda3e80956..7585f790d22a758d9aa1dbecee51262d252efd64 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -14,6 +14,7 @@ /* Simple U-Boot driver for the BCM283x mini UART */ +#include #include #include #include diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index 2abc1c4658f3c5b5fe0c2c0a59bec993b90375b0..09a9868a38f14b0abddbfade5e60e0bc0aa9ad37 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Alexander Graf */ +#include #include #include #include diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c index b1f69f6998cfa1fc6263a087a958509016902601..23066e4d05433b44179c4c379a072455869d5e6d 100644 --- a/drivers/serial/serial_coreboot.c +++ b/drivers/serial/serial_coreboot.c @@ -7,6 +7,7 @@ #define LOG_CATGEGORY UCLASS_SERIAL +#include #include #include #include diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c index 3ae8fb465848362b69378aeba6109d411d5daa6b..6dc81a775d3f0618550bb75efd2b89fd6eb426df 100644 --- a/drivers/serial/serial_cortina.c +++ b/drivers/serial/serial_cortina.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index 5733eaaf9d41cfeebd8dd189fb952ba00d8b4223..0067576389d16900af83cdbe6328bfb35fafdf09 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c index 2a93bbbcc9f8d534be5937180b9709e9f517f4ab..5d2bf0aaeba3d3fc3f082b0b0caae94774d9e9fb 100644 --- a/drivers/serial/serial_htif.c +++ b/drivers/serial/serial_htif.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ +#include #include #include #include diff --git a/drivers/serial/serial_intel_mid.c b/drivers/serial/serial_intel_mid.c index 4b528e4529266af30500b824b477d85c794b7918..bbf19057c4d12f76ce559ed9a7b35ee1f58eb875 100644 --- a/drivers/serial/serial_intel_mid.c +++ b/drivers/serial/serial_intel_mid.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c index ff66e69b9d7b15af517dda3b665e7b012d5ff17d..b449e55a6506fb5a92fd6ef1bc2441a985fd5dcb 100644 --- a/drivers/serial/serial_linflexuart.c +++ b/drivers/serial/serial_linflexuart.c @@ -3,6 +3,7 @@ * (C) Copyright 2013-2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index a06e6dc2505d8a4bf7404c65165c671abfa31354..3f2be72b830240fee20b8745dc5f29aec9fae57e 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -4,6 +4,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/serial/serial_mcf.c b/drivers/serial/serial_mcf.c index 76143575fa982a65f6e0147e7efc32b1db8c6b84..bb2afd0d8cd6baf0fad9924cb13887f8400246c7 100644 --- a/drivers/serial/serial_mcf.c +++ b/drivers/serial/serial_mcf.c @@ -15,6 +15,7 @@ * as serial console interface. */ +#include #include #include #include diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index bb79b9729579a661084425d6b3c5357da31dc3c0..be5f380f8500621af55bfb93910ceafa1e40f851 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Beniamino Galvani */ +#include #include #include #include diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index 9ce3fc3d9ec4319d3514e3bdd84ca77b6fd13d87..d82760c7f10adee337ee3bff7b8f93969be09799 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 757e5eaf974fc171c7a56006a218554be1425612..a472e0b3683399cfe6035595f6786254725b6fa7 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -8,6 +8,7 @@ * Based on Linux driver. */ +#include #include #include #include diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index cb6c09fdd09eecdcbdc7a9f6b53ce14e97a1919b..5260474fb9a4745e2ef7dac2743bf5418a2c67ef 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 3f569c68f22a2fb5dec24d1185792e17bb5f8d71..f146f2b006e898858f74767888e7bfc1a4f46e95 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -7,7 +7,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index 1a0b85e170ab01995c91b03f6c08cb90c55d10e4..b2017c645565fe6f567c7ee2a37fd57dc16339d9 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -4,6 +4,7 @@ * Copyright (C) 2021 Pali Rohár */ +#include #include #include #include diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index c5fd740be4deeacfdf178d813d6065ab6829c7f0..cc85a502726ecc46463b33ea2c3fade80dd419ce 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -3,6 +3,7 @@ * (c) 2007 Sascha Hauer */ +#include #include #include #include diff --git a/drivers/serial/serial_mxs.c b/drivers/serial/serial_mxs.c index 071bd09fef69a9cb4a5735f979e4e031bb8713c1..3659948b8728a84155a54f01d6c83f05fd6b728f 100644 --- a/drivers/serial/serial_mxs.c +++ b/drivers/serial/serial_mxs.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2023 Marek Vasut */ +#include #include #include #include diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c index 661daf1aefa3e51fc861a995baf1a380d10a993a..6bf3a943a2fc0e79adcbc29645e329d8f33a6a94 100644 --- a/drivers/serial/serial_npcm.c +++ b/drivers/serial/serial_npcm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 577864bc2195fe7e8e5ab333ee8245fb7cbc391f..4014f6820400d592916f8445a9581e16673a7bf6 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -4,7 +4,7 @@ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_nulldev.c b/drivers/serial/serial_nulldev.c index 78a9e0b195fa0db8dcc53b3d7d08fc8c2178ea03..f3ca7f525591ced618825073ebca4d3f829a15f2 100644 --- a/drivers/serial/serial_nulldev.c +++ b/drivers/serial/serial_nulldev.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 National Instruments */ +#include #include #include diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 94672655c288e364065df03401abc9828ef1e568..49ced8f9fae46ea8e35753f7f59e2df858915666 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -6,7 +6,7 @@ * Lokesh Vutla */ -#include +#include #include #include #include diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 8ce8aa32a21ea2c20a84c63d963e4dfc709bab4b..3b795785f780711291e72f36b1b7e2b8c95066e8 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -6,6 +6,7 @@ * Copyright (C) 2018 Manivannan Sadhasivam */ +#include #include #include #include diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c index a49c4139b5ae55739601e9b41500b87270ecb1a1..0a03a9a254971291d675dc6b42f84c05f2f1d8ed 100644 --- a/drivers/serial/serial_pic32.c +++ b/drivers/serial/serial_pic32.c @@ -3,6 +3,7 @@ * (c) 2015 Paul Thacker * */ +#include #include #include #include diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 80c35963b8f2988af861c1f02e6c368799c2e012..f04c21e0826487ae32d4da5d21752a700baa927b 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -10,6 +10,7 @@ /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ +#include #include /* For get_bus_freq() */ #include diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 8a15173f238f4f2abcfb33d834c3ed4571ca3ed8..f4e9422ed91c95e965f43b043f5be82db245586d 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/serial/serial_s5p4418_pl011.c b/drivers/serial/serial_s5p4418_pl011.c index 1fb954e80c2a5ff38b3655e9e8874693d2b0b014..e4492e662e927920c8dab08fb944f780b1913168 100644 --- a/drivers/serial/serial_s5p4418_pl011.c +++ b/drivers/serial/serial_s5p4418_pl011.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Stefan Bosch */ +#include #include #include #include diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c index 56a5ec72428afdd97eccad739a46189380ba3e76..cfa1ec3148c5a1d8d6cc3198b501fe76ee36ec64 100644 --- a/drivers/serial/serial_semihosting.c +++ b/drivers/serial/serial_semihosting.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Sean Anderson */ +#include #include #include #include diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c index e47828e4d6adbf8a80050085faa7a4ea992f0b95..c449f3fd02d90a72c945ec357270f042206e6b81 100644 --- a/drivers/serial/serial_sifive.c +++ b/drivers/serial/serial_sifive.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Anup Patel */ +#include #include #include #include diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index ef68e585dd6222d43590b65babd9dca04b32bad2..40381b57b08e4188925d113d89b570a0620b0fcd 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -6,6 +6,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 1ee58142b3f82535281460f1ebc901fef831e220..fb039546a41b73a3ba656e1ca12eaff3b628734d 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SERIAL +#include #include #include #include diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index a566ba7a47d5a880cd9b16c00216aa90afeeb2d3..27e4b92c39974fe1f5b111d5c6c3b61e7b2bc3d2 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -5,6 +5,7 @@ * Author: Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e05805f63726a399cfd030546939bc039627dd8c..ab318b06462bfd724bf010f4f94511b68c8b4c13 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -3,6 +3,7 @@ * (C) 2018 NXP * (C) 2020 EPAM Systems Inc. */ +#include #include #include #include diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index eb234108746d094a5bf5cbb6fc32a06c123f8d5f..35df413321fe695d5d5fc0dc220715c754191577 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 55f13c00ddf664387470f4f740540183392900d7..1847d1f6ecd23416aec899a9aa1a0605d101137c 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index ae3ac8070d3478f2e96461666236c8e3687f6b40..ecb6ba853df78f0737b405275d70a4e57f1d6b58 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -7,6 +7,7 @@ * Bryan O'Donoghue, bodonoghue@codehermit.ie */ +#include #include #include #include diff --git a/drivers/sm/meson-sm.c b/drivers/sm/meson-sm.c index 87eba1486db30ca90f982a81ed8aeacf45e5ff16..15b3b0e2672f6e714474df8ac3b7fc43faf3948c 100644 --- a/drivers/sm/meson-sm.c +++ b/drivers/sm/meson-sm.c @@ -5,6 +5,7 @@ * Author: Alexey Romanov */ +#include #include #include #include diff --git a/drivers/sm/sandbox-sm.c b/drivers/sm/sandbox-sm.c index a95e685494c27d53bed730909488500d05685350..109ddb2af55768223e18a31bc2cb50f026d120ea 100644 --- a/drivers/sm/sandbox-sm.c +++ b/drivers/sm/sandbox-sm.c @@ -5,6 +5,7 @@ * Author: Alexey Romanov */ +#include #include #include #include diff --git a/drivers/sm/sm-uclass.c b/drivers/sm/sm-uclass.c index abca0052e293185eb3c3f1cf36d516672f9c5356..6a8b70262937502b762d853f20c7637440da86c7 100644 --- a/drivers/sm/sm-uclass.c +++ b/drivers/sm/sm-uclass.c @@ -5,6 +5,7 @@ * Author: Alexey Romanov */ +#include #include #include #include diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c index ccd145f9afbb6a8f85921d38d0a69f805cd3db16..17ee6c837c6a705006aa421b640ca381b7281edb 100644 --- a/drivers/smem/msm_smem.c +++ b/drivers/smem/msm_smem.c @@ -5,6 +5,7 @@ * Copyright (c) 2018, Ramon Fried */ +#include #include #include #include diff --git a/drivers/smem/sandbox_smem.c b/drivers/smem/sandbox_smem.c index fec98e5611d6fba401fc8bf489561ec24086b6f4..7397e4407ad473c266f7c207fe21d177ef8571d1 100644 --- a/drivers/smem/sandbox_smem.c +++ b/drivers/smem/sandbox_smem.c @@ -3,6 +3,7 @@ * Copyright (c) 2018 Ramon Fried */ +#include #include #include #include diff --git a/drivers/smem/smem-uclass.c b/drivers/smem/smem-uclass.c index 4dea5cc4bf1c03737cc2d8b0867343bc20c5be08..8469076915e005928a60abf33906cb56873f6c32 100644 --- a/drivers/smem/smem-uclass.c +++ b/drivers/smem/smem-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SMEM +#include #include #include diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c index 744cdda2e187501847eae0b3180e1ba359e81152..8b3044fed8d223b21674d852084dd10bb349d96d 100644 --- a/drivers/soc/soc-uclass.c +++ b/drivers/soc/soc-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SOC +#include #include #include #include diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c index 8d621e88f5679709427d20f5694bb3da819ba45d..15fdd9930cb4c56446df9668f93848afc4cff244 100644 --- a/drivers/soc/soc_sandbox.c +++ b/drivers/soc/soc_sandbox.c @@ -6,6 +6,7 @@ * Dave Gerlach */ +#include #include #include diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index b585e47d46fe52019be674ecd36cccacb419cdd5..3a4e58bba6715239339e7afc5b7c1cdf656624a2 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -4,6 +4,7 @@ * Dave Gerlach */ +#include #include #include diff --git a/drivers/soc/soc_xilinx_versal.c b/drivers/soc/soc_xilinx_versal.c index 7427f8432c8b8f8043e2385ae6648d28253c30bd..3d8c25c19bb64738ca2b3260c41a9173ef388dcd 100644 --- a/drivers/soc/soc_xilinx_versal.c +++ b/drivers/soc/soc_xilinx_versal.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Xilinx, Inc. */ +#include #include #include #include diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c index d64fc366a6d10b12152e25e3aacfd7618406685c..146d068bb4ae5f0afc9ccfe42f14acbfa29a0f1f 100644 --- a/drivers/soc/soc_xilinx_versal_net.c +++ b/drivers/soc/soc_xilinx_versal_net.c @@ -5,6 +5,7 @@ * Copyright (C) 2022, Advanced Micro Devices, Inc. */ +#include #include #include #include diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a2d5b82fd34d1c6968c76fc9e484490f66420108..d8b4f172a39d27ed5fd01be4acd51ffbff7dd679 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -9,6 +9,7 @@ * Stefan Herbrechtsmeier */ +#include #include #include #include diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index d3f3d4761c2f4aca2da54dedae4ff6f5e98c34dd..ed39ff2fa4c72355d6d1332c7a48bfc1a22210b2 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com */ +#include #include #include #include diff --git a/drivers/soc/ti/keystone_serdes.c b/drivers/soc/ti/keystone_serdes.c index b19617997e1a3425e009e817c42cc73089a3b586..0e1bf8ff39dbb88d0a3de86489ecf57cb63cc3e0 100644 --- a/drivers/soc/ti/keystone_serdes.c +++ b/drivers/soc/ti/keystone_serdes.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index e3bb2ede554aae7c479ba26c29d5f93426f067ed..461390925d2ceac578622efdea2dc63163757a60 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -5,6 +5,7 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include #include #include #include @@ -204,7 +205,6 @@ static int pruss_probe(struct udevice *dev) static const struct udevice_id pruss_ids[] = { { .compatible = "ti,am654-icssg"}, - { .compatible = "ti,am642-icssg"}, {} }; diff --git a/drivers/sound/broadwell_i2s.c b/drivers/sound/broadwell_i2s.c index bc44b5ec7e1fd9a7cae31d7df778ec8cffd901b4..7f754e6567619fbe67c6c3b4fa1536119f7cecc3 100644 --- a/drivers/sound/broadwell_i2s.c +++ b/drivers/sound/broadwell_i2s.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_I2S +#include #include #include #include diff --git a/drivers/sound/broadwell_sound.c b/drivers/sound/broadwell_sound.c index 473f8d8f9771a89ee84fc4755fbbda102c91adb6..6e083fe1f6967f50987635f03995148184c4d5ba 100644 --- a/drivers/sound/broadwell_sound.c +++ b/drivers/sound/broadwell_sound.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/codec-uclass.c b/drivers/sound/codec-uclass.c index 1c1560619ea502279d2b9b42596512daa749444f..2cb233bd3060b6430afe3daa5711fb826602c07f 100644 --- a/drivers/sound/codec-uclass.c +++ b/drivers/sound/codec-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_AUDIO_CODEC +#include #include #include diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 5b9b3f65263fa559780bf85722dcacf5240ae480..c1edef4436082fcfca0b13ccd41c1bcc80afa6cd 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -6,6 +6,7 @@ * Parts taken from coreboot */ +#include #include #include #include diff --git a/drivers/sound/hda_codec.c b/drivers/sound/hda_codec.c index da8bde67de65645f9836f5b3064a1882e2faef07..af6148ef7240324af603f8f164c79898bacb5011 100644 --- a/drivers/sound/hda_codec.c +++ b/drivers/sound/hda_codec.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/i2s-uclass.c b/drivers/sound/i2s-uclass.c index 6263c4d707190fe09f837cfc814d669b2e192d41..fc4f686b516d6ad360ce7f6492ecd9d7329ad3a0 100644 --- a/drivers/sound/i2s-uclass.c +++ b/drivers/sound/i2s-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_I2S +#include #include #include diff --git a/drivers/sound/i8254_beep.c b/drivers/sound/i8254_beep.c index 7234ad4a07e567091e7ec27e5703b35133adb733..5572dc4d265d7db69db07022947d6cf030302fc6 100644 --- a/drivers/sound/i8254_beep.c +++ b/drivers/sound/i8254_beep.c @@ -3,6 +3,7 @@ * Copyright 2018 Google LLC */ +#include #include #include #include diff --git a/drivers/sound/ivybridge_sound.c b/drivers/sound/ivybridge_sound.c index aeeba1d267ecc4a21f772284a6318897a9f3358d..d982219e06de8ecded418a81c4ce3e6a2256d282 100644 --- a/drivers/sound/ivybridge_sound.c +++ b/drivers/sound/ivybridge_sound.c @@ -12,6 +12,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c index d9037641ca462a8d73f331278a79ef3966d57de5..c0463b8e8a62f3e611db06fa1ee2fe8859ff16b8 100644 --- a/drivers/sound/max98088.c +++ b/drivers/sound/max98088.c @@ -8,6 +8,7 @@ * following the changes made in max98095.c */ +#include #include #include #include diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index 18a3ffa85c8ed9896b8f8e222e01a723216c949f..a798762f1ee755920cb4d9d17ca6c0f57169193b 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -5,6 +5,7 @@ * Copyright 2011 Maxim Integrated Products */ +#include #include #include #include diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index 96e772cff21bd027e56839d17757f6509a5a6054..d0f701aaf105df9c6dce3cd51f649b57a166bbdc 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -7,6 +7,7 @@ * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com) */ +#include #include #include #include diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index da56ffdd6bb4e7d37b626cb2ea5153b47ceb6a06..bdf6dc236ec38db62b37b9a0315c4564b7312584 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -6,6 +6,7 @@ * Parts taken from coreboot */ +#include #include #include #include diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index 98f094c0e9adf96f02e365ad298ee75758567068..6553d9590472b93b2dd3e33ce3afd924e84f886c 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -5,6 +5,7 @@ * Copyright 2011 Maxim Integrated Products */ +#include #include #include #include diff --git a/drivers/sound/rockchip_i2s.c b/drivers/sound/rockchip_i2s.c index 5078dfbed07d4edf9588fe338dffdaa6909c0461..4e9e68aaac8165f3009dc6f586eb2ae6a297820c 100644 --- a/drivers/sound/rockchip_i2s.c +++ b/drivers/sound/rockchip_i2s.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_I2S +#include #include #include #include diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c index 418d2efd452678a44599b195c0b317ac31797696..94058e603d7d3fc5bc73e049543759d6c85cd11a 100644 --- a/drivers/sound/rockchip_sound.c +++ b/drivers/sound/rockchip_sound.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/rt5677.c b/drivers/sound/rt5677.c index b5c997c6dd53407fd56c2113ca28f73c197efa22..b655bb40b6426886f3b64edf4846badac5779173 100644 --- a/drivers/sound/rt5677.c +++ b/drivers/sound/rt5677.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index 42175fd7d28b9edaee730148eb79ceeff9312f1c..dc5a2789aeed8adf9842a964f3f3fa8433d8266e 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -4,11 +4,11 @@ * R. Chandrasekar */ +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c index 9150ad4a63ba1892f7b30ffaacd5f1d7175e681a..473cedf7e9749994d5667d9bd54872da5f36cdbd 100644 --- a/drivers/sound/samsung_sound.c +++ b/drivers/sound/samsung_sound.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/sound/sandbox.c b/drivers/sound/sandbox.c index 31ae153530e8832a185dc4dcd2bf270c7c3f67c9..c6cbd81fdbceb996da1cba50d058c1dc9978c07c 100644 --- a/drivers/sound/sandbox.c +++ b/drivers/sound/sandbox.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/sound-uclass.c b/drivers/sound/sound-uclass.c index b8a3dab447d9c5494637082bc79af45c45971deb..2ffc4fc7c1db7e76ec308c513c03f792563b4044 100644 --- a/drivers/sound/sound-uclass.c +++ b/drivers/sound/sound-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SOUND +#include #include #include #include diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index 4fde2989e04f5983106eb12b5121844639f865df..c0fc50c99dac5e6c7ec051a9b762415a0d3c6670 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -4,9 +4,9 @@ * R. Chandrasekar */ +#include #include #include -#include void sound_create_square_wave(uint sample_rate, unsigned short *data, int size, uint freq, uint channels) diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c index 8f1b0c009a8815d080357c51182695946ae0f41e..495a29c5137c4462780ca9934514ce0871216ba3 100644 --- a/drivers/sound/tegra_ahub.c +++ b/drivers/sound/tegra_ahub.c @@ -7,11 +7,11 @@ #define LOG_CATEGORY UCLASS_MISC +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/sound/tegra_i2s.c b/drivers/sound/tegra_i2s.c index 357aac36ceaae64d4f6423f173616c39a8aed3cd..932f737900e4f90879bd0961fcf8be674d1f917c 100644 --- a/drivers/sound/tegra_i2s.c +++ b/drivers/sound/tegra_i2s.c @@ -5,6 +5,7 @@ */ #define LOG_CATEGORY UCLASS_I2S +#include #include #include #include diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c index 152c929146f587834a36269941d173264227e362..aef6a2eb147555506e8b8d0db862dc5cb3056c32 100644 --- a/drivers/sound/tegra_sound.c +++ b/drivers/sound/tegra_sound.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_I2S +#include #include #include #include diff --git a/drivers/sound/wm8994.c b/drivers/sound/wm8994.c index 6b3091aa5de18eea58d6d1cb32b7657bbbaac921..fd646479b315a866823e998b8acac63f2b85b1f2 100644 --- a/drivers/sound/wm8994.c +++ b/drivers/sound/wm8994.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 Samsung Electronics * R. Chandrasekar */ +#include #include #include #include diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 8e227d187b0c214978ed9c8deb6bdee6112d7606..989679e881b5c28da24d45549a248fd34e913473 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -6,6 +6,7 @@ * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou */ +#include #include #include #include diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c index 5f94e9f7a74db914d8cb33eb6493c682c6ce6a6d..f35f5af1f6f8f6e3b0fbce4b8a3359ab2cc28523 100644 --- a/drivers/spi/apple_spi.c +++ b/drivers/spi/apple_spi.c @@ -4,6 +4,7 @@ * Copyright The Asahi Linux Contributors */ +#include #include #include #include diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 929bf90458c397cfcfefdbab8e8133bf3d2b3c44..70cb242cd31efc22947ad2569cfe731f0735c4c1 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -6,6 +6,7 @@ * Author: Rick Chen (rick@andestech.com) */ +#include #include #include #include diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c index faefac71260878393651fde315be1e9abad547e0..205567ef54dd57458de3a4bfa3b4c66791c99adf 100644 --- a/drivers/spi/ath79_spi.c +++ b/drivers/spi/ath79_spi.c @@ -3,6 +3,7 @@ * Copyright (C) 2015-2016 Wills Wang */ +#include #include #include #include diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 3efb661803b6c333cc10664811573aaaa0fbda2e..bd73e4fddf18033b352a69d6c69ce549f4f92bad 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 79f010013184f9d85ef5888332fe9af6750d19ba..d4f0c4c448367e070782cf16a81fd16d64945451 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2007 Atmel Corporation */ +#include #include #include #include diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 1aa43fd3a23854879bf12af72521251a4b581fba..23ac5bb76c049d96a5f6e95e4cc2fc47ae0e180e 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -7,6 +7,7 @@ * Copyright (C) 2012-2013 Jonas Gorski */ +#include #include #include #include diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c index 595b41c8ab8a52092788264d9b382f9cc18bc463..889ac1f966e3b96a4354e9f794c91b683a43c189 100644 --- a/drivers/spi/bcm63xx_spi.c +++ b/drivers/spi/bcm63xx_spi.c @@ -7,6 +7,7 @@ * Copyright (C) 2010 Tanguy Bouzeloc */ +#include #include #include #include diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c index eff9e1117d35a68fa8f494f393fcd5d9a233058b..af45882db0a70f6d80cf42609141d2d6bdc1426c 100644 --- a/drivers/spi/bcmbca_hsspi.c +++ b/drivers/spi/bcmbca_hsspi.c @@ -8,6 +8,7 @@ * Copyright (C) 2021 Broadcom Ltd */ +#include #include #include #include diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index a99a8a4485ab737bfccafbc8284f9b23caf2fead..38bddd38619ec912830bd64c909c57f206a80a74 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -7,6 +7,7 @@ * Author: PengPeng Chen */ +#include #include #include #include diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 222f828f54eca6535851079994027172bf6688bb..c2be307f1d87675beaf7debae9b8b4f58546fe6d 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 75e522320101a34352e06ad9c18e49b23ca353c3..f4593c47b8c557f892afc8ee6e39e6c4c11a86a4 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -4,6 +4,7 @@ * Altera Corporation */ +#include #include #include #include diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 93ab2b5635f3b14a9091e456f639923148091d62..fb905322178244d5f4bdeba88ae09ba16ee1949c 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -25,6 +25,7 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include #include #include #include diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 8234468b1d4364f1ffef81fef29adac5647865e7..1a841b5dcefca9e2f6ae5ef7e4ea73d09b5f5631 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -13,6 +13,7 @@ * TODO: fsl_dspi.c should work as a driver for the DSPI module. */ +#include #include #include #include diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 04c134be9edf5bc9294e7b36b8b9cea038537329..25f5e9fdebd5525564e7262bdeb24285ca960c66 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -8,7 +8,7 @@ * Copyright (C) 2007 Atmel Corporation */ -#include +#include #include #include #include diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 6bd48b1b3739ba85e0b048dc6f0a23f61ad37c00..22a79da2333eb2161ef5ee69aaf40c5f800e38d7 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,6 +11,7 @@ */ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 1b9bf004b7c1eb4c2d4275fa15cbcc1395dc115c..1bcc3ad318db2fc3fa7f54acb6dc560706b1d70d 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -4,6 +4,7 @@ * Padmavathi Venna */ +#include #include #include #include diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 1d4d90ce5aaf1ddf1a0bd1152cf1385e3653b151..9b3d5a94817f42b813654c6bd46d48ac2ae04e3b 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 2638ed2520014e2d2591932d823a9fb62b62df00..b1d964d79d0c5737e48b5683251eef1d85232528 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -8,7 +8,7 @@ * Chuanhua Han (chuanhua.han@nxp.com) */ -#include +#include #include #include #include diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 8a0a53cb372034b5ebb1ef39d094f135d6bb4fb3..3f97730bad0bbb8cfa2c7e7c73a3d57e058b85db 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -23,6 +23,7 @@ * Transition to spi-mem in spi-fsl-qspi.c */ +#include #include #include #include diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index e48ca65fe726ff2b6f90def2edd1295a0448c98c..9142ffd238701b92cd029394ec3159c259c8b78d 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c index 09f30c227023c06ea2aa95c8a359a3cfc9989d57..b5c274314b5b61749f0cda80f8689c13cedee2fd 100644 --- a/drivers/spi/iproc_qspi.c +++ b/drivers/spi/iproc_qspi.c @@ -3,6 +3,7 @@ * Copyright 2020-2021 Broadcom */ +#include #include #include #include diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 095cbea0fca9c6e12148d60067030c703728ac60..2bb7390bbfb74075fc98c82f99f40aef1e51ae01 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -7,7 +7,7 @@ * Derived from drivers/spi/mpc8xxx_spi.c */ -#include +#include #include #include #include diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c index d7ebb6bf1ac7f1fee6f47d93db3893018ed2d25e..d99a151406e607148cd40058e1e70f0e8d61f962 100644 --- a/drivers/spi/meson_spifc.c +++ b/drivers/spi/meson_spifc.c @@ -7,6 +7,7 @@ * Amlogic Meson SPI Flash Controller driver */ +#include #include #include #include diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index 234b168827261547642112bad334cdcc565fe94a..5fe0c8e1237e26f89a9712f951b43a875a0f2756 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -5,6 +5,7 @@ * Naga Sureshkumar Relli */ +#include #include #include #include diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 7e72fb9e23dc7d60e8d76709b375c5363e58d37f..e1448cc6196956281f3e72305e90ee98bf5079b8 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -16,6 +16,7 @@ * */ +#include #include #include #include diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index cd624f4d6f0be7eecfe30f8dac78d6d992213285..7d15390c56b327227ccc3d91bab27a98c0578961 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -4,6 +4,7 @@ * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers */ +#include #include #include #include diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c index ad4daeba3cd808ef39c3035aa762e819d55f6d47..95bea0da1b357477fc7aff22562ba8332237d41b 100644 --- a/drivers/spi/mscc_bb_spi.c +++ b/drivers/spi/mscc_bb_spi.c @@ -5,6 +5,7 @@ * Copyright (c) 2018 Microsemi Corporation */ +#include #include #include #include diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index e46942de2e3b99d75ba7555ca3db3d2d845740e2..3d0080998625632f5586741337c9cc30b4418bf3 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -8,6 +8,7 @@ * Copyright (C) 2014-2015 Felix Fietkau */ +#include #include #include #include diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c index 830424b31d6ae65744aed55103b3b847c12b8132..3decb3744de93ec9b38de7f0eda9724456410e7c 100644 --- a/drivers/spi/mtk_snfi_spi.c +++ b/drivers/spi/mtk_snfi_spi.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c index f202b2f49f587e765a02202ab8c56c6bf2051391..4b7d4a6e0741c2c4598c73e1f2463518c0886626 100644 --- a/drivers/spi/mtk_snor.c +++ b/drivers/spi/mtk_snor.c @@ -7,6 +7,7 @@ // Some parts are based on drivers/spi/spi-mtk-nor.c of linux version #include +#include #include #include #include diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index fde9b142fb89957d22e2a90e1c09cf1e00c323f1..bba2383a11167f300a3200d0a567f0d6bf0ee3ab 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -5,6 +5,7 @@ * Copyright (C) 2016 Stefan Roese */ +#include #include #include #include diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index ff61a14f095d0a7f122e08dee34212a04d4e64c4..e291092c481ab71bf57cd5453b5d2bc61e2203e3 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -3,7 +3,7 @@ * Copyright (C) 2008, Guennadi Liakhovetski */ -#include +#include #include #include #include diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index ad9e490faa9f0475542682615c2cdbcb2cbcde5d..773e26bbed74ca3804986a3f960dd5fea2e57964 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -12,6 +12,7 @@ * GPIO driven chipselects are not supported. */ +#include #include #include #include diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c index 7708a96971c2af3a0f8fb1babcf679bff4739a90..c9441304f5a2e3690637d28001621e8914e80b4a 100644 --- a/drivers/spi/npcm_pspi.c +++ b/drivers/spi/npcm_pspi.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology. */ +#include #include #include #include diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index fefdaaa9e90155deecc3c9388b1df770c8b9e9ee..5db27f9ae2c991a8e3e521afee79b523effd0dea 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -33,6 +33,7 @@ * Frieder Schrempf */ +#include #include #include #include diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 3d82fc74ff58fee46fc80ad6fb30cca99c34a24a..5cce6baa6213d5323509fd35481a3b4633cd29a5 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -16,9 +16,9 @@ * Modified by Ruslan Araslanov */ +#include #include #include -#include #include #include #include diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c index e11ae7fc7a4a4fb2fecb10c4d66a48b8b1a433f5..45f07f083da8f9576c7eb2f897507b7eb4d5d6fb 100644 --- a/drivers/spi/pic32_spi.c +++ b/drivers/spi/pic32_spi.c @@ -6,6 +6,7 @@ * Purna Chandra Mandal */ +#include #include #include #include diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index 1e20701d0d35484e6565152d9eb76fb7e2f3303b..e2b49ebd149a2579b2b5b35dde70e4d9910482e3 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index e6b602cf7b47b79e59be4ad762a12373940669bb..8aff22386458d85a7a88b074a84e7938a6fe6066 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 4571dc9f9b697be404bbb23c8690bdb53c1ca58b..c8694fdff954c90c86147f087ae1e4cd89af700b 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -10,6 +10,7 @@ * Peter, Software Engineering, . */ +#include #include #include #include diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index 4cc016138b11e68d1dab64d23535282e4278e780..f844597d04cf8287e6606c23cca60afedb8b4358 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index b7364a61929f19930cf6e4fb7ef3f4e5ac209921..72594993853bdd2048d99b3d17f88ab64d806c6e 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 9bdb4a5bff9bf9006c9e1b43c12714288dd6ba95..0fa14339bdcd95180e491372042cce7316cfec62 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -9,6 +9,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index d91d58da45966d4dea826972b90d3c610a46bd14..7d5f101a76621c32a51ae779250671e5d9a62cbf 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c index d92f36bd20e5f46681ea631ce4a935eede57ca16..64bc19c00112cf4f5cb2e6d6d66a982f90206edd 100644 --- a/drivers/spi/spi-emul-uclass.c +++ b/drivers/spi/spi-emul-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SPI_EMUL +#include #include #include #include diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 3579b7d7db589076b11fa56db7505043ff77e7f3..b7eca5835956fb8af01fcc74b6a45cc353343781 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -13,6 +13,7 @@ #include #include "internals.h" #else +#include #include #include #include diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index b98bcd9b6ba5551fe0432108c7d2c2a7b8fa5858..f663b9dcbb161c44e97660d4eb87f211755efa7a 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -6,6 +6,7 @@ * zhengxunli */ +#include #include #include #include diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 836c550b0bb64bb14ad1ab20c46a835ef0c09194..572cef1694c8bc2828403cc8a16d6fdf0a8014c1 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0c8666c05f94f49ed95f1460e6fc7a9bb7a1b159..ea372a05f8362ecaa2c106087d553ccbb0544754 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -6,6 +6,7 @@ * SiFive SPI controller driver (master mode only) */ +#include #include #include #include diff --git a/drivers/spi/spi-sn-f-ospi.c b/drivers/spi/spi-sn-f-ospi.c index fc82791006ec8de6a63a689ecd7297f6586b9a35..e3633a52608084ecc22318e3abfc56f177a5e9c6 100644 --- a/drivers/spi/spi-sn-f-ospi.c +++ b/drivers/spi/spi-sn-f-ospi.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 13725ee7a2dca6c014700b6e003406848308dadd..9ec6b359e227e1c78c7dd55e50de95d0f6f66a5a 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -18,6 +18,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index eb522fd7b3d99d65a45cad5de6fdce7e70d0de15..553f9687e3b3be4ea9f2d7b865e61763370e1323 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 6e28172523913ec2808e45125d1fa802aa8226ee..f4795e68672fedbdc1613409d025c6edddb79355 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 50a076a98be6ef55fcdc6316762ec8508ca18945..22910de0dd93581d3cddfd4f32e6d98acb96c812 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 2812a4da4113b92a081a46daff84b6f7a4b2e78c..2ffa201a66edf3c87b07aaece1e45edf2c7525cd 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index 97b83b171670b34804a417e02bca5799a15856c5..ddb410a94c010360879fd74637e0cb10060e9aed 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 57f1a8fc703fa0167526b0cffff80b909d778973..f0256d8e6641516f37384b5e9dcac04e1af38f41 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -5,6 +5,7 @@ * Copyright (c) 2010-2013 NVIDIA Corporation */ +#include #include #include #include diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c index 19114808e9df99d18dc4e6795415755579b8edbd..10e38cf839dc0949612fe5555385f20f011bcf19 100644 --- a/drivers/spi/tegra20_sflash.c +++ b/drivers/spi/tegra20_sflash.c @@ -5,6 +5,7 @@ * With more help from omap3_spi SPI driver */ +#include #include #include #include diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index d54a5049205b76f3d4e021b61624247ccc10fde6..d0e788539e0b92f4c56099d1dac29b68284d6eef 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -5,6 +5,7 @@ * Copyright (c) 2010-2013 NVIDIA Corporation */ +#include #include #include #include diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index b969a7993d40551cac96c64a18e74db716c35e3c..5c8c1859cc963026a739de11d231fee32bd66d01 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index a16412ec6fb9f5b39dd6252b17648efea2774405..99acb108823edb222d1954790f11b15d6f19f27a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -5,6 +5,7 @@ * Copyright (C) 2013, Texas Instruments, Incorporated */ +#include #include #include #include diff --git a/drivers/spi/uniphier_spi.c b/drivers/spi/uniphier_spi.c index 8f2c0fb4b8eedae2bd1d1dcbda68c41f231ac74d..6402acbf14a141029fe0883870cb97aa25352f93 100644 --- a/drivers/spi/uniphier_spi.c +++ b/drivers/spi/uniphier_spi.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 0e7fa3a4525d1092812ea7ea82f0c98160757ff4..94ddf4967eaf28c094733b6ccc053bfe5fab8cad 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index b71b9a6fd6c8ed73d182810034ab1057f40dff16..cb52c0f30721a4054aabbaf3b08cc32db2b89bad 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index ebcb5b6cc883107dd1be45aa0977d1178998059f..b3e0858eb94506a78910694569a21ebf84b9d827 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -6,6 +6,7 @@ * Xilinx Zynq PS SPI controller driver (master mode only) */ +#include #include #include #include diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 61349a4da53f708cec163186eaf839cde98a5aed..a323994fb2d3bfd4d6b6a8dda67b23d0e35f4c0d 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_SPI +#include #include #include #include diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index b0d6226041e5d1a68e27a1c2487a96f8db041546..244de69b3590ce4edea611c0391e474f54b972c0 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -7,6 +7,7 @@ * Loosely based on Little Kernel driver */ +#include #include #include #include diff --git a/drivers/spmi/spmi-sandbox.c b/drivers/spmi/spmi-sandbox.c index 992b08dd6120257cf9ce7e621c674dd6efbf8f3c..f6772946bca377397c2f9ef0f5f1aad0f61b61de 100644 --- a/drivers/spmi/spmi-sandbox.c +++ b/drivers/spmi/spmi-sandbox.c @@ -7,6 +7,7 @@ * (C) Copyright 2015 Mateusz Kulikowski */ +#include #include #include #include diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c index 34fe8f6644c3212f5c65de16ce1f2b1aa4626eab..9d9f46a37d832fa9ba2329a203fdb940ad5e4772 100644 --- a/drivers/spmi/spmi-uclass.c +++ b/drivers/spmi/spmi-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_SPMI +#include #include #include #include diff --git a/drivers/sysinfo/gazerbeam.c b/drivers/sysinfo/gazerbeam.c index a3c9d5354dd26b9905098acd243fdd66d5f4528e..c1fae6ccf2a63e4578203c037f29dfb37c33a897 100644 --- a/drivers/sysinfo/gazerbeam.c +++ b/drivers/sysinfo/gazerbeam.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c index aaca318419b0085c7ca73491bd6f955949cb951a..82f90303bb7094a57ccd88f3b49ae02bc8b2c47f 100644 --- a/drivers/sysinfo/gpio.c +++ b/drivers/sysinfo/gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Sean Anderson */ +#include #include #include #include diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index 37e2cccd9afecfbb259669c5940e83a3830a124f..7b127986da7e2e671af0bf17f6845b140545db82 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Marek Vasut */ +#include #include #include #include diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d39720958f0783c0d6af1106ad2059829900087c..d270a26aa4381d7bde9498bfc95b3883a2e87125 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index a7ac8e3f072a112dddc3e1ac13506721c5ea3b5a..80ebd1921d8ecd05ce07ef0cb3828f15793da6d6 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index d77d1e3ee44251677be768697a66c7b6b988052c..10194d0e14c358b3a1457a29f69452faf5654092 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SYSINFO +#include #include #include diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c index d9220024f470be539a9f48c3fb49a90dd841edad..ad04e4b1a85eee0359b156f292bc697e8982cd0e 100644 --- a/drivers/sysreset/poweroff_gpio.c +++ b/drivers/sysreset/poweroff_gpio.c @@ -11,6 +11,7 @@ * Copyright (C) 2012 Jamie Lentin */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c index 451fc5de7357bc50eb048f1837af692a3cae53b4..0de132633a8d8b78c098f3d48cdc1d226234cb92 100644 --- a/drivers/sysreset/sysreset-ti-sci.c +++ b/drivers/sysreset/sysreset-ti-sci.c @@ -6,6 +6,7 @@ * Andreas Dannenberg */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 0abb4042e0f2ec7df7232eaca25e28df49679b3f..6151b5fe03e4e7377cebaa56ffd526e6df06089d 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_SYSRESET +#include #include #include #include diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index ef09440bbeffa209ede9d70d595eca1a6154eb4d..92fad96871bde6cbe106cf5998053b881e289a59 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -3,6 +3,7 @@ * (C) Copyright 2016 Google, Inc */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c index 457042c7aae954112a3511a5a940bacc04a0f443..fc85f31ebf01174868ec9cd661288b40dc667701 100644 --- a/drivers/sysreset/sysreset_at91.c +++ b/drivers/sysreset/sysreset_at91.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c index 47018844a51ad28045eaa444fbd4f347049e2989..de42b5935424687e75df5cae93a23fd023c3ef14 100644 --- a/drivers/sysreset/sysreset_gpio.c +++ b/drivers/sysreset/sysreset_gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_microblaze.c b/drivers/sysreset/sysreset_microblaze.c index b81d82f046bd377c9c46977edc673a12d47369cb..83a7f77ac41f6710e5b703b60f2c9983625a8fa5 100644 --- a/drivers/sysreset/sysreset_microblaze.c +++ b/drivers/sysreset/sysreset_microblaze.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. - Michal Simek */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c index dca49299f77747199cf6fcee39321b6cfd61d42b..ca48328f7b58c3792fcc4053f023d616f4256c08 100644 --- a/drivers/sysreset/sysreset_mpc83xx.c +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c index c16223720e5abfd04122a8ed71b3bf062a125ab8..ebdea6ab66edfafc4492b62ebc3c8807f87f99a0 100644 --- a/drivers/sysreset/sysreset_octeon.c +++ b/drivers/sysreset/sysreset_octeon.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Stefan Roese */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c index 89b4f2dcaec41a61430c17ca7f2ba05918e07802..aa09d0b88271bff312ab1c38d15bb435ef7f4528 100644 --- a/drivers/sysreset/sysreset_psci.c +++ b/drivers/sysreset/sysreset_psci.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Masahiro Yamada */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c index fbe3999b96059120245de3065d88cea5281819e9..25bd5c9a7ff2725a705783e203f877f6d3fa6646 100644 --- a/drivers/sysreset/sysreset_resetctl.c +++ b/drivers/sysreset/sysreset_resetctl.c @@ -5,6 +5,7 @@ * Author: Weijie Gao */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c index 00308f9a33b7939cf7da1cd0e992a14c4b48f56b..f353f9b4c79dac081fa1beb1e7ccc1c84a3f53b3 100644 --- a/drivers/sysreset/sysreset_rockchip.c +++ b/drivers/sysreset/sysreset_rockchip.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 93179f90bbb8828e00b5eb5699afd56642d44523..c12eda81d03e7d6b96c6104c2005b554b664ac7b 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_sbi.c b/drivers/sysreset/sysreset_sbi.c index 458191206b2c89a05dc0be4880eb16c2df61122c..5e8090d62bfc7d66c487937eb78ec78b25b8918a 100644 --- a/drivers/sysreset/sysreset_sbi.c +++ b/drivers/sysreset/sysreset_sbi.c @@ -3,6 +3,7 @@ * Copyright 2021, Heinrich Schuchardt */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c index a07b0f4fd553779c598b4db0830f619f08882dfe..9b62dd5eab096e33394e71400463fb62f1fbb165 100644 --- a/drivers/sysreset/sysreset_socfpga.c +++ b/drivers/sysreset/sysreset_socfpga.c @@ -4,6 +4,7 @@ * Simon Goldschmidt */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 6f44792abb000edcc3274ae4e7e0030b8fd61487..9837aadf64b6d5373ebdc4a484d200bb659d146b 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -4,6 +4,7 @@ * Simon Goldschmidt */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c index 110b7e23afa191aadc5efa6c99b1fafe01605777..edd90aab061dafb9816c1c25e0f879fcd16dc12b 100644 --- a/drivers/sysreset/sysreset_sti.c +++ b/drivers/sysreset/sysreset_sti.c @@ -4,6 +4,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index 57144fa1e3bb25c7fa024c4ebbb5fb06befaefa8..e468dac0e90204150df7fad7317e8d098b71e49a 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -7,6 +7,7 @@ * Author: Feng Kan */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c index 49c061e08803e21619a36b8fea3eb76d25462198..6db5aa75b54173e73994df5b9b31dfaf7291fed6 100644 --- a/drivers/sysreset/sysreset_watchdog.c +++ b/drivers/sysreset/sysreset_watchdog.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Álvaro Fernández Rojas */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c index c2f28c65280f1d5b36bf818cbd013ec6051fe974..dc772b5ff9e34a5e80df503df9f49270e73a147f 100644 --- a/drivers/sysreset/sysreset_x86.c +++ b/drivers/sysreset/sysreset_x86.c @@ -5,6 +5,7 @@ * Generic reset driver for x86 processor */ +#include #include #include #include diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c index ab71ea11a0b20e78d6f0068c35892946cb8b7fd9..84fbc79016a0a51adc5b8fd53fe94b192683b670 100644 --- a/drivers/sysreset/sysreset_xtfpga.c +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -5,7 +5,7 @@ * (C) Copyright 2016 Cadence Design Systems Inc. */ -#include +#include #include #include #include diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c index fc2b0e227b2934584b4c8a6cef4ff5d178c924ed..3ec131cbc6e10993206928b2dd8953cb4d34cf2f 100644 --- a/drivers/thermal/imx_scu_thermal.c +++ b/drivers/thermal/imx_scu_thermal.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index ea1fcc3dcb295e5fcf66d1a2ed0c2d7d4ce09a0d..2f6343e7a18009be173dcae7491db6d672929cc4 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 70d002aee25ba94271d687c45bd1cc8833ebc31d..ea6c8329c0a6af384ad1447c779956d61140e831 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/thermal/thermal-uclass.c b/drivers/thermal/thermal-uclass.c index f0fe912e31314c6e7a574a68cd2554c8c4a5ed53..700df8af2549f20febbe6f367bb7b0eca57bbdf8 100644 --- a/drivers/thermal/thermal-uclass.c +++ b/drivers/thermal/thermal-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_THERMAL +#include #include #include #include diff --git a/drivers/thermal/thermal_sandbox.c b/drivers/thermal/thermal_sandbox.c index 9af0d0247cbdb6b4efb4f6d1336646cad726615c..7dc0d108b8ca6df35d363d1d3c153405bcf1e987 100644 --- a/drivers/thermal/thermal_sandbox.c +++ b/drivers/thermal/thermal_sandbox.c @@ -6,6 +6,7 @@ * Sandbox driver for the thermal uclass. */ +#include #include #include diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6b1de82ae38dd78e57ef96a8200f7345275be49c..60519c3b536cda11a0794c9979bab3fca46489a4 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -50,14 +50,6 @@ config TIMER_EARLY use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). -config ADI_SC5XX_TIMER - bool "ADI ADSP-SC5xx Timer Support" - depends on TIMER && (SC57X || SC58X || SC59X || SC59X_64) - help - gptimer based timer support on ADI's ADSP-SC5xx platforms. Available - but not required on sc59x-64-based platforms (598 and similar). - Required on 32-bit platforms (sc57x, sc58x, sc594 and earlier). - config ALTERA_TIMER bool "Altera timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fb95c8899e396a570e3c14a6f64132e4a33c6787..b93145e8d437097d3c3c8f5903e8732f9703fb41 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -3,7 +3,6 @@ # Copyright (C) 2015 Thomas Chou obj-y += timer-uclass.o -obj-$(CONFIG_ADI_SC5XX_TIMER) += adi_sc5xx_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o diff --git a/drivers/timer/adi_sc5xx_timer.c b/drivers/timer/adi_sc5xx_timer.c deleted file mode 100644 index 11c098434a8fae3575c368cf8dd23f8d278512eb..0000000000000000000000000000000000000000 --- a/drivers/timer/adi_sc5xx_timer.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Converted to driver model by Nathan Barrett-Morrison - * - * Author: Greg Malysa - * Additional Contact: Nathan Barrett-Morrison - * - * dm timer implementation for ADI ADSP-SC5xx SoCs - * - */ - -#include -#include -#include -#include -#include -#include - -/* - * Timer Configuration Register Bits - */ -#define TIMER_OUT_DIS 0x0800 -#define TIMER_PULSE_HI 0x0080 -#define TIMER_MODE_PWM_CONT 0x000c - -#define __BFP(m) u16 m; u16 __pad_##m - -struct gptimer3 { - __BFP(config); - u32 counter; - u32 period; - u32 width; - u32 delay; -}; - -struct gptimer3_group_regs { - __BFP(run); - __BFP(enable); - __BFP(disable); - __BFP(stop_cfg); - __BFP(stop_cfg_set); - __BFP(stop_cfg_clr); - __BFP(data_imsk); - __BFP(stat_imsk); - __BFP(tr_msk); - __BFP(tr_ie); - __BFP(data_ilat); - __BFP(stat_ilat); - __BFP(err_status); - __BFP(bcast_per); - __BFP(bcast_wid); - __BFP(bcast_dly); -}; - -#define MAX_TIM_LOAD 0xFFFFFFFF - -struct adi_gptimer_priv { - struct gptimer3_group_regs __iomem *timer_group; - struct gptimer3 __iomem *timer_base; - u32 prev; - u64 upper; -}; - -static u64 adi_gptimer_get_count(struct udevice *udev) -{ - struct adi_gptimer_priv *priv = dev_get_priv(udev); - - u32 now = readl(&priv->timer_base->counter); - - if (now < priv->prev) - priv->upper += (1ull << 32); - - priv->prev = now; - - return (priv->upper + (u64)now); -} - -static const struct timer_ops adi_gptimer_ops = { - .get_count = adi_gptimer_get_count, -}; - -static int adi_gptimer_probe(struct udevice *udev) -{ - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(udev); - struct adi_gptimer_priv *priv = dev_get_priv(udev); - struct clk clk; - u16 imask; - int ret; - - priv->timer_group = dev_remap_addr_index(udev, 0); - priv->timer_base = dev_remap_addr_index(udev, 1); - priv->upper = 0; - priv->prev = 0; - - if (!priv->timer_group || !priv->timer_base) { - dev_err(udev, "Missing timer_group or timer_base reg entries\n"); - return -ENODEV; - } - - ret = clk_get_by_index(udev, 0, &clk); - if (ret < 0) { - dev_err(udev, "Missing clock reference for timer\n"); - return ret; - } - - ret = clk_enable(&clk); - if (ret) { - dev_err(udev, "Failed to enable clock\n"); - return ret; - } - - uc_priv->clock_rate = clk_get_rate(&clk); - - /* Enable timer */ - writew(TIMER_OUT_DIS | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI, - &priv->timer_base->config); - writel(MAX_TIM_LOAD, &priv->timer_base->period); - writel(MAX_TIM_LOAD - 1, &priv->timer_base->width); - - /* We only use timer 0 in uboot */ - imask = readw(&priv->timer_group->data_imsk); - imask &= ~(1 << 0); - writew(imask, &priv->timer_group->data_imsk); - writew((1 << 0), &priv->timer_group->enable); - - return 0; -} - -static const struct udevice_id adi_gptimer_ids[] = { - { .compatible = "adi,sc5xx-gptimer" }, - { }, -}; - -U_BOOT_DRIVER(adi_gptimer) = { - .name = "adi_gptimer", - .id = UCLASS_TIMER, - .of_match = adi_gptimer_ids, - .priv_auto = sizeof(struct adi_gptimer_priv), - .probe = adi_gptimer_probe, - .ops = &adi_gptimer_ops, -}; diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c index ece246c23d2f6ed7493342ba54dac75fb26acd60..040dc65f48aaa27d5da68d1cbe8f1f92d89cb7db 100644 --- a/drivers/timer/altera_timer.c +++ b/drivers/timer/altera_timer.c @@ -7,6 +7,7 @@ * Scott McNutt */ +#include #include #include #include diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index 20baaf61307aa3f6a65165a5f17e7f36915634fc..42dd4b6231764fba87c06c0ab4d82cab3654260b 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -8,6 +8,7 @@ * associated with timer tick. */ +#include #include #include #include diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c index 413bcc32f01b17504840dc4e8d6a494f8d8e21c2..497f8a04155f4709ca8d63b2356a9ff49715e41b 100644 --- a/drivers/timer/arc_timer.c +++ b/drivers/timer/arc_timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Synopsys, Inc. All rights reserved. */ +#include #include #include #include diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index b8057929f997f61b4df10cd6c6547a349d1d121b..2e50d9fbc5804a4dd63f99c179329aed174accba 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -6,7 +6,7 @@ * ARM Cortext A9 global timer driver */ -#include +#include #include #include #include diff --git a/drivers/timer/arm_twd_timer.c b/drivers/timer/arm_twd_timer.c index 2b2f35911738f9f1f9e2d2717eb65ee51f56aef3..40ccd16587495d88a582b50f23b3b381fa2eab95 100644 --- a/drivers/timer/arm_twd_timer.c +++ b/drivers/timer/arm_twd_timer.c @@ -27,6 +27,7 @@ * Alex Zuepke */ +#include #include #include #include diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c index 6601cab7b1652bec378b9e274f841289255ef37b..78adc96cc5963e2ebb5d62c9ab0db77d6b8e3f3f 100644 --- a/drivers/timer/ast_timer.c +++ b/drivers/timer/ast_timer.c @@ -3,6 +3,7 @@ * Copyright 2016 Google Inc. */ +#include #include #include #include diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c index 0a367a5a7f4ae8e2d191d8d4fcbc8f066ed63812..5cf46f224ab00206283c9b55d65c15ade2172c5f 100644 --- a/drivers/timer/atmel_pit_timer.c +++ b/drivers/timer/atmel_pit_timer.c @@ -4,6 +4,7 @@ * Wenyou.Yang */ +#include #include #include #include diff --git a/drivers/timer/atmel_tcb_timer.c b/drivers/timer/atmel_tcb_timer.c index 3a328b2f6c726d416fcfd76362ecd35274c53766..8c17987c7d7442bcc448c2243768ef4417cbeea5 100644 --- a/drivers/timer/atmel_tcb_timer.c +++ b/drivers/timer/atmel_tcb_timer.c @@ -5,6 +5,7 @@ * Author: Clément Léger */ +#include #include #include #include diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 3cffb1bb88db59b7cc84821b73d73c06131e9fc7..2eff45060ad6811a71fb61a1cceb1f3b32a6b821 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. (Michal Simek) */ +#include #include #include #include diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 77ccb98cb8dfd3a3cd68e2dce8d1f751045c47ee..0607f751ca708792bb28d36aa4d641919a53b69c 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Marek Vasut */ +#include #include #include #include diff --git a/drivers/timer/fttmr010_timer.c b/drivers/timer/fttmr010_timer.c index c41bbfc1d57613077166ad0ade04987aac6ba017..b6289e64610999e352d2bb8a96e77f1d33bb9142 100644 --- a/drivers/timer/fttmr010_timer.c +++ b/drivers/timer/fttmr010_timer.c @@ -5,6 +5,7 @@ * * 23/08/2022 Port to DM */ +#include #include #include #include diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c index 07b9fdb5e18c50236bd302f2539da9775ac2b35c..9c3b64ae5b1b8753f04fb798dfde3de54644027d 100644 --- a/drivers/timer/imx-gpt-timer.c +++ b/drivers/timer/imx-gpt-timer.c @@ -4,7 +4,7 @@ * Author(s): Giulio Benetti */ -#include +#include #include #include #include diff --git a/drivers/timer/mchp-pit64b-timer.c b/drivers/timer/mchp-pit64b-timer.c index 1a5b2e6a0dc88aa6fc2951289d28945921e88a5c..c9806d7eeebd9cdd5f7cf36861d7d59dfb7dba81 100644 --- a/drivers/timer/mchp-pit64b-timer.c +++ b/drivers/timer/mchp-pit64b-timer.c @@ -7,6 +7,7 @@ * Author: Claudiu Beznea */ +#include #include #include #include diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 9da74479aaa678bfab861950a770b216b604c433..7814cb6a5d612bc158d7c2e4d32c420df854717a 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -4,7 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ -#include +#include #include #include #include diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c index 8216c289837375e524e2d38a9cabaeddd5be5573..223e63f6c1a23a438237beddbafcb2536eeba476 100644 --- a/drivers/timer/mtk_timer.c +++ b/drivers/timer/mtk_timer.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c index 9a05582c0d528c2813c5999b3f93ae2eee39ab99..4d24de14ae69f99b9828397cf677439a42bf2122 100644 --- a/drivers/timer/nomadik-mtu-timer.c +++ b/drivers/timer/nomadik-mtu-timer.c @@ -12,6 +12,7 @@ * Copyright (C) 2010 Linus Walleij for ST-Ericsson */ +#include #include #include #include diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c index 9463fd29ce81a597df8c1c395534b28e46993091..4562a6f2311b440189bb1f4e76be7731647d492e 100644 --- a/drivers/timer/npcm-timer.c +++ b/drivers/timer/npcm-timer.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index fda6356fdba8ece1e4e8c1fede73aa095143168a..9b6d97dae677cb61dd31277db89d122863cdb6ef 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -5,6 +5,7 @@ * Copyright (C) 2015, Texas Instruments, Incorporated */ +#include #include #include #include diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index 821b681a232602b599880bf7714eca7005e2c70e..9cab27f2e48b51ef3b6585c2b8889578385e5e7d 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include -#include +#include #include #include #include diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 314f956cdfb7a62dd103af4bc6b1f787127d2b68..3bf0d4647b58aa2de28b4a88e973436c09b2fac1 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -5,6 +5,7 @@ * Copyright (C) 2019 Marek Vasut */ +#include #include #include #include diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c index 35da1ea2fd2d3a2b8f2df4184052402b682d8281..73fb87912851ff60a5a4a4b20e19262982f4fc62 100644 --- a/drivers/timer/riscv_aclint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -4,7 +4,7 @@ * Copyright (C) 2018, Bin Meng */ -#include +#include #include #include #include diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 1f4980ceb38f6c726563a564de680c3b85613d84..169c03dcb5c1b90793ab8f350fd58805e41e6617 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -10,7 +10,7 @@ * This driver provides generic timer support for S-mode U-Boot. */ -#include +#include #include #include #include diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 96c010f4dcc803745ee4ec2694584b6da64f2a31..e66c49aa6bbd3e1e7ca1817a559010a055a1431d 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c index e8b54a02965f715a7c95447b2fed30b2eb3c357d..1da7e0c3a76865a1b374748fa442516cd5e14121 100644 --- a/drivers/timer/sandbox_timer.c +++ b/drivers/timer/sandbox_timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Thomas Chou */ +#include #include #include #include diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index a254e295cbfc95bc77e15c97d9e177ab2affe07d..8fd4afb15a5be469ab940fac04cbf8b2f0e33ce7 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -4,6 +4,7 @@ * Copyright (C) 2022 Arm Ltd. */ +#include #include #include #include diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c index 6b79c8858b5509ca535a020753f9b5a6f004350b..6ac7d7f1d0ee1caab45303b762afbdad7e9450a4 100644 --- a/drivers/timer/starfive-timer.c +++ b/drivers/timer/starfive-timer.c @@ -4,6 +4,7 @@ * Author: Kuan Lim Lee */ +#include #include #include #include diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index 1dc21c5c1bed85673d77e8415baa7254650b398e..1213a14ef19708d890e9e1d3fcbaff9ae9ec98d1 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -6,7 +6,7 @@ #define LOG_CATEGORY UCLASS_TIMER -#include +#include #include #include #include diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c index 3545424889d24b9c45f5cf10c8e1b6c8f6bc06b1..a867c649c3a8612ce9f20ca0a3974421f0dae9be 100644 --- a/drivers/timer/tegra-timer.c +++ b/drivers/timer/tegra-timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 8305f06d318724acd5923c138789c9af6cc348e7..60ff65529ab38b74d77ca6ae6c83a2254c020881 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_TIMER +#include #include #include #include diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 80c084f380d9ea01680e91c75ca4ae9bbc18c76e..f86a0b86921c4d9983b15b1e772e68dcad1b0013 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -6,6 +6,7 @@ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c */ +#include #include #include #include diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c index 54148aa1689be83a0bdfc0e2724ada933659491c..172fd9f9296e5267450b15ecc7ba2cae9ad07b11 100644 --- a/drivers/timer/xilinx-timer.c +++ b/drivers/timer/xilinx-timer.c @@ -7,6 +7,7 @@ * Michal SIMEK */ +#include #include #include #include diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 08ec179346e29d0dd3cb7da44b25b34d82e05a77..acf4c7859a9fa50afae18de3446bae974f4f1201 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -7,12 +7,12 @@ #define LOG_CATEGORY UCLASS_TPM +#include #include #include #include #include #include -#include #include #include #include diff --git a/drivers/tpm/sandbox_common.c b/drivers/tpm/sandbox_common.c index 596e0156389995a1274c96ae9d899cb01acd5fba..7e0b2502e35da3de02db0823efee686dc6a807d1 100644 --- a/drivers/tpm/sandbox_common.c +++ b/drivers/tpm/sandbox_common.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_TPM +#include #include #include #include diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index 0fade2dcc0ad8b8ce35f5f831fe7b03c9ef96808..b2286f7e7edc842e7e25f3cac6a39714e5395348 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -6,9 +6,9 @@ #define LOG_CATEGORY UCLASS_TPM +#include #include #include -#include #include #include #include diff --git a/drivers/tpm/tpm2_ftpm_tee.c b/drivers/tpm/tpm2_ftpm_tee.c index f2ced50c4eb7e3ca22da8daf6552595157750412..c61ff2c2af63c3563dcf305cc76502a8dca93386 100644 --- a/drivers/tpm/tpm2_ftpm_tee.c +++ b/drivers/tpm/tpm2_ftpm_tee.c @@ -13,6 +13,7 @@ * https://github.com/microsoft/ms-tpm-20-ref/tree/master/Samples/ARM32-FirmwareTPM/optee_ta/fTPM */ +#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c index 680a6409433e8abd4cf1714a424b2da8b10a5acd..81b9210056db962100d6ecdccb81901280a8462c 100644 --- a/drivers/tpm/tpm2_tis_core.c +++ b/drivers/tpm/tpm2_tis_core.c @@ -5,8 +5,8 @@ * Based on the Linux TIS core interface and U-Boot original SPI TPM driver */ +#include #include -#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_i2c.c b/drivers/tpm/tpm2_tis_i2c.c index 93efccc77575e486d744f7cc7cc06c09d7346635..99d1cf218dafc2fdc8e97b2841a3dbe6e7bf0510 100644 --- a/drivers/tpm/tpm2_tis_i2c.c +++ b/drivers/tpm/tpm2_tis_i2c.c @@ -3,6 +3,7 @@ * Copyright 2022 IBM Corp. */ +#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c index dee5503c055f810412b954b468b43522dceab07c..a646ce41ff4e05e8023eb10f7322de8ed5015c53 100644 --- a/drivers/tpm/tpm2_tis_mmio.c +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -5,6 +5,7 @@ * Specifications at www.trustedcomputinggroup.org */ +#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c index 50e308e711614b965512666b9b64c2efcc037e3d..d15a28d9fc82d943a4b7b34f039c190471904dd7 100644 --- a/drivers/tpm/tpm2_tis_sandbox.c +++ b/drivers/tpm/tpm2_tis_sandbox.c @@ -4,6 +4,7 @@ * Author: Miquel Raynal */ +#include #include #include #include diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 28079b5039a3b44518f9acf0fea0b16c699bd42d..de9cf8f21e078576da483631bce84736fffea44c 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -13,11 +13,11 @@ * It is based on the U-Boot driver tpm_tis_infineon_i2c.c. */ +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/tpm/tpm_atmel_twi.c b/drivers/tpm/tpm_atmel_twi.c index 05dd66525c77e8ee13a45238e2bfc8f166479ed7..fd2a45d34b03cf9942213844ec1bf0ab2e288b60 100644 --- a/drivers/tpm/tpm_atmel_twi.c +++ b/drivers/tpm/tpm_atmel_twi.c @@ -5,11 +5,11 @@ * Written by Dirk Eibach */ +#include #include #include #include #include -#include #include #include diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c index e2f6238cbc7115c97a580630384d2f309d01b460..16f4af0e331e11a7405d0c553ef3671e49c3b623 100644 --- a/drivers/tpm/tpm_tis_infineon.c +++ b/drivers/tpm/tpm_tis_infineon.c @@ -19,11 +19,11 @@ * Version: 2.1.1 */ +#include #include #include #include #include -#include #include #include #include diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index dec7acb0c7b16efd5f766978c2538829318816a5..13a133d58ebd1dbfea8c4d100041b986a0b8af7e 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -12,6 +12,7 @@ * slb9635), so this driver provides access to locality 0 only. */ +#include #include #include #include diff --git a/drivers/tpm/tpm_tis_sandbox.c b/drivers/tpm/tpm_tis_sandbox.c index 2bc7dc87ed30013f703412c8daa5a6d29bdcf452..7350e1c4d525dfefb895eeedb26cfea402249707 100644 --- a/drivers/tpm/tpm_tis_sandbox.c +++ b/drivers/tpm/tpm_tis_sandbox.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c b/drivers/tpm/tpm_tis_st33zp24_i2c.c index 1a265b28b22f8cf92b9b4fa9532d65de0174dd57..e0eeabb93371e0591f47ee4e8b63da14453a699a 100644 --- a/drivers/tpm/tpm_tis_st33zp24_i2c.c +++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c @@ -12,6 +12,7 @@ * STMicroelectronics Protocol Stack Specification version 1.2.0. */ +#include #include #include #include diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c b/drivers/tpm/tpm_tis_st33zp24_spi.c index 2cf690328d871fad1aad4aceb0fd16c9746f185e..f0de8a65b093d9b4bbfe8999e130df94ba6147d2 100644 --- a/drivers/tpm/tpm_tis_st33zp24_spi.c +++ b/drivers/tpm/tpm_tis_st33zp24_spi.c @@ -12,6 +12,7 @@ * STMicroelectronics Protocol Stack Specification version 1.2.0. */ +#include #include #include #include diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index 510a6a6aa5dd4702dfdd01712114931a5ba407e0..d1f346937c5d04ec3ffbcfd93ec9bcfa3aef7259 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c index c5c08610ffd0422c9cf9d8e85b0396e6102cb29a..1860e0dca299eff26155c7755045c8c2aad15598 100644 --- a/drivers/ufs/ti-j721e-ufs.c +++ b/drivers/ufs/ti-j721e-ufs.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c index 871f3f50f5caefdb4fc96c720810c337c482cf90..ad41358727a5c4c925e0aa96b89e7f0f2b4cd9fd 100644 --- a/drivers/ufs/ufs-pci.c +++ b/drivers/ufs/ufs-pci.c @@ -4,6 +4,7 @@ * Author: Bin Meng */ +#include #include #include #include diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index 334bfcfa06a429efcc04d099e7de978684c0490e..92fcdf4e6cb7008d9ec1d9810c74264ac127f733 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_UFS +#include #include "ufs.h" #include diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index be64bf971f169ee50ae9029e09f8fa071d17b186..e4400f319a785a601cdee1cbc51d71fc82639652 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h index 43042c294bba2f9db7e16c3d60c0062b87539f11..816a5ce0cafc5f87a5ea1e864b6cac97789feddf 100644 --- a/drivers/ufs/ufs.h +++ b/drivers/ufs/ufs.h @@ -2,7 +2,6 @@ #ifndef __UFS_H #define __UFS_H -#include #include "unipro.h" struct udevice; diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c index ac072260c30a72484aea62bbadc9ef250f4a608a..2e44aadea47b3eb24b3536cdc22c6235f6fb5e9f 100644 --- a/drivers/usb/cdns3/cdns3-ti.c +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -5,6 +5,7 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ +#include #include #include #include diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index b4e931646b886c344c47f571a51356afa41a7efc..12a741c6ea7c4e376494a3cc29bebe5323220021 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -11,6 +11,7 @@ * Roger Quadros */ +#include #include #include #include diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 7aa0c6b2beef70defb9a894712eb7cb2c373c624..d11175dc5b64fa8abcd99d6e03a47c13dd8e84ec 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -2325,6 +2325,9 @@ static void cdns3_gadget_config(struct cdns3_device *priv_dev) writel(USB_IEN_INIT, ®s->usb_ien); writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf); + /* Set the Fast access bit */ + writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr); + cdns3_configure_dmult(priv_dev, NULL); cdns3_gadget_pullup(&priv_dev->gadget, 1); @@ -2383,6 +2386,7 @@ static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) /* disable interrupt for device */ writel(0, &priv_dev->regs->usb_ien); + writel(0, &priv_dev->regs->usb_pwr); writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); return ret; diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 13e9a61072a973acc9a2a7096867bb6d26fe6123..7137a569d97c83a8f84c7c7ac2f45227e931eb9a 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -6,6 +6,7 @@ * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c index 6a68bd76c2742c89862c82a4106bf9b9c4db6c03..00b8cd368b1af569e5c50e2188628fad74dfa62b 100644 --- a/drivers/usb/common/fsl-dt-fixup.c +++ b/drivers/usb/common/fsl-dt-fixup.c @@ -7,6 +7,7 @@ * Author: Tor Krill tor@excito.com */ +#include #include #include #include diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 89ae73f2ba482ada9e215665a6e882f88529227c..9eb1d23067253ea1c489fc08a05396b0883004c9 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -5,6 +5,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index c443d56746dd5f342e39b9a982a126b3ddb8462b..96e850b7170f346051f46e30462551bbe7c11a36 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -13,6 +13,7 @@ * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA */ +#include #include #include #include diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 4162a682298904dc4ac26810348222e4e2193a26..7374ce950da8bdb27df0c7c45277938ea2ad4204 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -405,6 +405,8 @@ #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) +#define DWC3_DEPCMD_CMD(x) ((x) & 0xf) + /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ #define DWC3_DALEPENA_EP(n) (1 << n) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 8db678eb85d45da5ec7020312eaa6c06d1e24e7d..7a00529a2a8e055d471d21b8c90cd8829b7a2ff9 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -7,6 +7,7 @@ * Based on dwc3-omap.c. */ +#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-layerscape.c b/drivers/usb/dwc3/dwc3-layerscape.c index ff83bf71e89857dec27eee2847277eb0ce2a2f7d..c32df2396d74ab0e45563f03f6e40839ecf935ea 100644 --- a/drivers/usb/dwc3/dwc3-layerscape.c +++ b/drivers/usb/dwc3/dwc3-layerscape.c @@ -7,6 +7,7 @@ * Based on dwc3-generic.c. */ +#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 21e4f637bb150fb527c3f01fc641010c1eef5c74..1a3e9350c46dfe3c3e86cccd747ce6f4e98c7c06 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 3e693c5ff310ad5e7a513ff1849856117b26cf73..2ce915701a857dde9427cd0ed0be4fbbd2d30e1e 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -7,6 +7,7 @@ */ #define DEBUG +#include #include #include #include diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 4b219c35eb35229db55585ec8e5c27247083dcb2..53c4d4826b4544c967ab91729a8cc6f9daab4a77 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -13,6 +13,7 @@ * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete() */ +#include #include #include #include diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 117d38a0340b06248a70ce20cf4c1359b5bb1e54..1133cf82b1ae176267ef6e82f1f71176fc8d71a5 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -12,6 +12,7 @@ * * commit c00552ebaf : Merge 3.18-rc7 into usb-next */ +#include #include #include #include diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 4de007cb0c387fdfd14ab92178d16c50b78d309d..39c19d94de143aac067202573f7d19a347869778 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -13,6 +13,7 @@ * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier */ +#include #include #include #include @@ -300,8 +301,38 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) { u32 timeout = 500; + u32 saved_config = 0; u32 reg; + int ret = -EINVAL; + + /* + * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or + * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an + * endpoint command. + * + * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY + * settings. Restore them after the command is completed. + * + * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 + */ + if (dwc->gadget.speed <= USB_SPEED_HIGH || + DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { + saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + } + + if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { + saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + } + + if (saved_config) + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + } + dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); @@ -312,7 +343,8 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, if (!(reg & DWC3_DEPCMD_CMDACT)) { dev_vdbg(dwc->dev, "Command Complete --> %d\n", DWC3_DEPCMD_STATUS(reg)); - return 0; + ret = 0; + break; } /* @@ -320,11 +352,21 @@ int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, * interrupt context. */ timeout--; - if (!timeout) - return -ETIMEDOUT; + if (!timeout) { + ret = -ETIMEDOUT; + break; + } udelay(1); } while (1); + + if (saved_config) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= saved_config; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + } + + return ret; } static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, diff --git a/drivers/usb/dwc3/samsung_usb_phy.c b/drivers/usb/dwc3/samsung_usb_phy.c index 0a7713081636869b0c3df49d0c7dc95e55d1687f..abbd413689016d1a0b5ad60776b789045dbfcec8 100644 --- a/drivers/usb/dwc3/samsung_usb_phy.c +++ b/drivers/usb/dwc3/samsung_usb_phy.c @@ -7,7 +7,7 @@ * Author: Joonyoung Shim */ -#include +#include #include #include #include diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c index f0ecdea958ae2ec387b1204493e232c82f08e4ec..8ae130860f7931f771492f4bad670652d5cdad96 100644 --- a/drivers/usb/dwc3/ti_usb_phy.c +++ b/drivers/usb/dwc3/ti_usb_phy.c @@ -16,6 +16,7 @@ * and remove" for phy-omap-usb2.c */ +#include #include #include #include diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c index 24420e3d51e1225b45a4492642166c29ff261fdf..7c5c1ab3de739dedebce2d2b9fec6aefec26e7fc 100644 --- a/drivers/usb/emul/sandbox_flash.c +++ b/drivers/usb/emul/sandbox_flash.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_USB +#include #include #include #include diff --git a/drivers/usb/emul/sandbox_hub.c b/drivers/usb/emul/sandbox_hub.c index 3b3e59f978f7d1b2f4bf2575b53d2b5e24d3e34c..084cc16cc6838b856afe518c1284c76bfeee5f14 100644 --- a/drivers/usb/emul/sandbox_hub.c +++ b/drivers/usb/emul/sandbox_hub.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c index db769883ba3b740963b5f68ccffa59d9791fb499..5ec1e98e4ed42da28b840779462a4403a7516c49 100644 --- a/drivers/usb/emul/sandbox_keyb.c +++ b/drivers/usb/emul/sandbox_keyb.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c index cdc18d6cbb978c18406d0470efd4b67e321b5780..b31dc950e3abb6ab6c389d89ee6917e1e6230612 100644 --- a/drivers/usb/emul/usb-emul-uclass.c +++ b/drivers/usb/emul/usb-emul-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_USB_EMUL +#include #include #include #include diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index c5a01ec922be55cbb5ac6ca21fd7bf6f2a15f844..26dd312b7d0673b9e00d95f6e413a01b1ecd64fb 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -5,6 +5,7 @@ * Patched for AX88772B by Antmicro Ltd */ +#include #include #include #include diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 7bfd285b3aa4b8e0d8e42fed3385802aac4e830d..2e737e60668590664de2aea88d21ffffa9820a6f 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -5,6 +5,7 @@ * from the Linux AX88179_178a driver */ +#include #include #include #include diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index 199fb7a5d08e8d2a7b9b68a5c0ae8c5d2e64f395..d94204f22d5f0ade885405d169931e876b1ec548 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -9,6 +9,7 @@ * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices */ +#include #include #include #include diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index e3f20e08c33cac4f8520dc670d22a1be6f3f10e7..3c866f4f1e2d18c08cc2baa4d2b2d8f2f6bb2c1f 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c index 3159f30106020affb0fe8f00e18c769c123c4988..a41abed3069a7aad80bd5b94d3c1245a024b2ba5 100644 --- a/drivers/usb/eth/r8152_fw.c +++ b/drivers/usb/eth/r8152_fw.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. * */ +#include #include #include #include diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index b4fcb2c2bb0dbf4f85251aef2e40171c48185d78..de6586e62639fe1d2cd9704d96e4de57febb78e8 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -6,6 +6,7 @@ * Copyright (C) 2007-2008 SMSC (Steve Glendinning) */ +#include #include #include #include diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index 8bba3e0974e6cb3123de0b843ef834b7e3fa22b9..2e9af54fd63d992ad09c363de926d8c6af722a84 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -3,6 +3,7 @@ * Copyright (c) 2011 The Chromium OS Authors. */ +#include #include #include #include diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 86b2cbf3f6ae5c8d7fbe48052fe3e12655b37001..e573a03477b9e220ed6fcb3a83dbbf8c7ae2f1a1 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -13,6 +13,7 @@ #undef VERBOSE_DEBUG #undef PACKET_TRACE +#include #include #include #include diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index f99553df8d492f25caad08729ba31798227367fa..4c420747b0b68d49f775454f0d8701ae29b2ffe5 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c @@ -7,6 +7,7 @@ * Bo Shen */ +#include #include #include #include diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c index 9875191091ccff74a1de7e17b20d5b8380607e61..c89cd57c253d8ecfd83c54bcef2a2dcc9877e7b2 100644 --- a/drivers/usb/gadget/bcm_udc_otg_phy.c +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index bbe03cfff1fb877ce92afd71e38c0225311c2d12..750d4714879831386c3becd68a7246c28387448a 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -7,6 +7,7 @@ * Murray.Jensen@cmst.csiro.au, 27-Jan-01. */ +#include #include #include #include diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c index 1363ef9e73df556eb51900d218adeb3fea6665b7..e96782644f314c0d3ef011a929ce309253258d80 100644 --- a/drivers/usb/gadget/config.c +++ b/drivers/usb/gadget/config.c @@ -8,6 +8,7 @@ * Remy Bohmer */ +#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 6bd395a6235a7c8e43a112eb6a538001ea3c660d..27082f5152cbb935a8e8a4277d8b33edde8ae170 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -17,6 +17,7 @@ * Lukasz Majewski */ #undef DEBUG +#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg_phy.c b/drivers/usb/gadget/dwc2_udc_otg_phy.c index c7eea7b34421ad9bde86d42334852d2f21a133e8..7f8e9564b9e5d5259d4728420a7e4941d5f95916 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_phy.c +++ b/drivers/usb/gadget/dwc2_udc_otg_phy.c @@ -17,6 +17,7 @@ * Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 16b2a03f9e4b2be2ed8bff75feb9d77ea6408c72..1c34b753511d058f9e8ce8bc2e04df029bb7837a 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -17,6 +17,7 @@ * Lukasz Majewski */ +#include #include #include #include diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index 9d08640ff23ac4972512046589ef8a240c719060..c256cc31fbd2e0e56e335a35a7a6f7f1b13183f2 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -36,6 +36,7 @@ * XXX */ +#include #include #include diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 0a70035ce04b087d75db871bd64e9cf7d03b58b1..bb0d2971d06b0b7bdd19698011202e9eb04585e5 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -8,6 +8,7 @@ * Remy Bohmer */ +#include #include #include #include diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index b8b29d399b13176d7db1f3aae4364bbed3e0ba9d..36618f0bdf36ab0909642e1335bc312741a532ed 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -7,6 +7,7 @@ * Copyright (C) 2008 Nokia Corporation */ +#include #include #include #include diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c index f18c6a0a76110df62e925de1882316eed463b343..ba216128ab27b0242215958e1f860f0c810d0116 100644 --- a/drivers/usb/gadget/f_acm.c +++ b/drivers/usb/gadget/f_acm.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index ca8b36e077bc52f5ff433ac3b78b200f5a98b1cb..44877df4ec6b95877ba592be4de441ff1b45ca72 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -16,6 +16,7 @@ #include #include +#include #include #include diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 8df0e3f331d1938444ec8575fcceb3ae875d275b..09e740cc96224f75cb6c11e78af36d799c0f66dd 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -11,6 +11,7 @@ */ #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 89a96dbb7a740b32b936e9b586c71558799d0634..ef90c7ec7fb5a274e40eae2670343862d3d09eda 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -244,6 +244,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index d679cdae97c8d37f07cbc0f7d62ab0a474895ab3..98a7ffa2a752cac0db3cc4c5e5c1010e28c8b578 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 89496917a61f86fd3e50464fbbedaefbdc237d5e..ca2760c00d0d3379c55d2847ce4daa1c8f83b6c5 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 5437211834800a7db7c44bf45df4b9620ca7fd5b..0e7529dcdbb65df289d1077153fee3babfa56c77 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index b5b5f5d8c1182d0f8f4cb20ecb012345119d23da..afb7b74f3057047f21e580fca4808c8302247551 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -6,6 +6,7 @@ * Lukasz Majewski */ +#include #include #include diff --git a/drivers/usb/gadget/max3420_udc.c b/drivers/usb/gadget/max3420_udc.c index 5a227c0ffd99636bee2ea4aab0c25f154d1a9a2c..fa655c98dcc5c30f23262f0dfc23ae80c31fd73c 100644 --- a/drivers/usb/gadget/max3420_udc.c +++ b/drivers/usb/gadget/max3420_udc.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 5e6e5a054ca745a40ec0897d3fdce75b10147cd1..e7276ccd37a35950b67f4f2e30449a9d662f6bf0 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -18,6 +18,7 @@ * updates to merge with Linux 2.6, better match RNDIS spec */ +#include #include #include #include diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 6bb419ae2abc67482b65ec40cca9f6640578a23a..ba658d922966ea971562c028cc618deeca9b3f6a 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index 5dc23a55bb58b1c546e1e14ea164fa57ae4c900a..30ee1cab0668de0a7469525263ae5deaed535f6d 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_USB_GADGET_GENERIC +#include #include #include #include diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c index 4617a95bd0a7a8968fc5417110503fb2a951021c..e2464ad923f8cffc0cc91ef085920bd017c4e0e8 100644 --- a/drivers/usb/gadget/usbstring.c +++ b/drivers/usb/gadget/usbstring.c @@ -6,6 +6,7 @@ * Remy Bohmer */ +#include #include #include #include diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index a9dbb85f4e6c5a9122108eb64f77e99758b840e8..637eb2dd06f5394d491a11cf5d6675219ca07339 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -4,6 +4,7 @@ * Copyright (C) 2014 Marek Vasut */ +#include #include #include #include diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index d52e7d22d1a74cfdd5d751d460f878c999501fb3..f9df59d2e5d7041079f763884d340017b82f80ef 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -10,6 +10,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c index 3e6834e38e386bf2201263253e751d6e940f4611..4a3ab6111276e6239baf61afd696d5f92a31d792 100644 --- a/drivers/usb/host/dwc3-sti-glue.c +++ b/drivers/usb/host/dwc3-sti-glue.c @@ -6,6 +6,7 @@ * Author(s): Patrice Chotard, for STMicroelectronics. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index ee751224463a1319c6d306a2e28fe8a7c3376ea2..c6d50fd4551ab5682fce0e4393727c82a10c36f6 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -5,6 +5,7 @@ * Written-by: Bo Shen */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 1e4a5a0b6f6ce3ff7e14ec16a5250eddb5a13139..c1cdd4b0889aead5fad8c4e19f5a4c21bf2c3ce6 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -6,6 +6,7 @@ * Vivek Gautam */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index ee3eb065b142143717c38ef50d8688d137d56810..0569dd54fff937af7ac0f8fc32ed3609e7e73118 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -7,6 +7,7 @@ * Author: Tor Krill tor@excito.com */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 23c3ed25554f9acfeac840a132d99b92e3b8fafa..936e30438d9ff32e1d95fa04fbc861c31ebc94fe 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Alexey Brodkin */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 7d5519c65a9e1a0fc24345cdfe47f612a069ef71..9839aa17492d827b08e8560df74457165a1d80b9 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -6,6 +6,7 @@ * * All rights reserved. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index ca0ab57d49c278b71b28223e79b2a245e1a192a8..6093c8fb0b68629c79ae176b196d596552f08e76 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -5,6 +5,7 @@ * Written-by: Prafulla Wadaskar */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index a081f71b187d9ee63202f1b556f753f4e2bec9d6..98fe7bc3bcb169d04a1d0770bbdb7dc8e1153b19 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -7,6 +7,7 @@ * Based on Linux driver */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index fb912654097eacdaecac0bda80a13ea1640f2f4d..c11279867c7ca0d2412d9cea5105763419729df3 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -4,6 +4,7 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 31cd8a50f4a2258ce478db93848cbef2529564c3..a35fcca43a23a6abd2e6b806c1b063b4c97aaaf0 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -4,6 +4,7 @@ * Copyright (C) 2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 95af5c9254cbb26286636306c1419b3db70256c7..ddf7cc2d00a7b1881acdbd7903955fef9fd9a32e 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -6,6 +6,7 @@ * on behalf of DENX Software Engineering GmbH */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-npcm.c b/drivers/usb/host/ehci-npcm.c index d2a9965b4b4f6560d38513e91832ad38899ab6a3..357a5614edb7ddf98d20a75e413b72917bf8a69d 100644 --- a/drivers/usb/host/ehci-npcm.c +++ b/drivers/usb/host/ehci-npcm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index a95fcad02131c72709729afe396c3113e3910488..765336a3c42b2b5d13c687334fb1cd95f5ddde12 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -10,8 +10,8 @@ * */ +#include #include -#include #include #include #include diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 572686580cd56d7cca87a8c89aa259f65a3c4bcd..e98ab312618daac821c7dcf8485e251f27101d7f 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -4,6 +4,7 @@ * All rights reserved. */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 343893b9f19acba389263fade3ccc11a89a03adb..2cf16256703d0dd0e149c9be38325a84432c5e55 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -5,6 +5,7 @@ * Copyright (c) 2013 Lucas Stach */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 5afe28ea303321a15905c17778a9a6317a9064e9..648e136447d93e21998333429bde8f23d33cc90e 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -6,6 +6,7 @@ * Based on ehci-mx6 driver */ +#include #include #include #include diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c index dfaff5c60f4e46e7a2cf9f7d5394cfb8a5cd00c5..f7e458cb15a2b05e1f29e4571bdfc755ddd5277d 100644 --- a/drivers/usb/host/ehci-zynq.c +++ b/drivers/usb/host/ehci-zynq.c @@ -5,6 +5,7 @@ * USB Low level initialization(Specific to zynq) */ +#include #include #include #include diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index b170f26e6c6a846323f3c2b90837416499ae214d..9b955c1bd678eb70475b0a4002ed8457b1ec462a 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -4,6 +4,7 @@ * DENX Software Engineering */ +#include #include int usb_cpu_init(void) diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c index d321d147c2f957e6d54053f7c869514529803c90..d3d73d238442bba552f76d05375103d4f1960a9a 100644 --- a/drivers/usb/host/ohci-da8xx.c +++ b/drivers/usb/host/ohci-da8xx.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 Sughosh Ganu */ +#include #include #include #include diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c index f1325cd4953430ba98a2709461627c78f693667b..ceed1911a95a99dbdd893ba305bea3f517ba23f2 100644 --- a/drivers/usb/host/ohci-generic.c +++ b/drivers/usb/host/ohci-generic.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Alexey Brodkin */ +#include #include #include #include diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index c020d13c43d210c8524491ead131a544806db52e..3f4418198ccd7723597625e3fef23d53cc8fe3f6 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -27,7 +27,7 @@ * to activate workaround for bug #41 or this driver will NOT work! */ -#include +#include #include #include #include diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index ed04cae7afed81cd7eba2172c354923d11c25c81..a04b2961b9617d7688412966eb379323532b25b2 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -7,6 +7,7 @@ * Copyright (c) 2015 Tyco Fire Protection Products. */ +#include #include #include #include diff --git a/drivers/usb/host/ohci-npcm.c b/drivers/usb/host/ohci-npcm.c index ffeb6bc206a895d58ece3b99aba57b0324b116cd..9e1d52988099a9a5525c47fceda831ca0b2c9d37 100644 --- a/drivers/usb/host/ohci-npcm.c +++ b/drivers/usb/host/ohci-npcm.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ +#include #include #include #include diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c index f10f109242055aacdfc092413cb868cb7edac4ea..f061aec28966fc8cb709666efe6d0a5f019f9153 100644 --- a/drivers/usb/host/ohci-pci.c +++ b/drivers/usb/host/ohci-pci.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index f0b18bffba4123c8dfb33a8083f953b5c5514764..3ccbc16da379f1ff33dd43ea47e87c2565a3b2d2 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -5,6 +5,7 @@ * Copyright (C) 2008 Yoshihiro Shimoda */ +#include #include #include #include diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c index e26f0b292ed534f65644f9137a50b99618c155cc..3d4f8d653b5d214041dc531537250d9b4372fcc9 100644 --- a/drivers/usb/host/usb-sandbox.c +++ b/drivers/usb/host/usb-sandbox.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index cd3a07e4c374e322066afe290ff66f3157a2ed23..a1cd0ad2d669b7c2fa04148cec104fcbe8aa99ea 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_USB +#include #include #include #include diff --git a/drivers/usb/host/usb_bootdev.c b/drivers/usb/host/usb_bootdev.c index 362b46dc466ebc92af987d3031dcefa6c407c10f..7fa1c601dff52fdb166fa96be700a34ac7653748 100644 --- a/drivers/usb/host/usb_bootdev.c +++ b/drivers/usb/host/usb_bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-brcm.c b/drivers/usb/host/xhci-brcm.c index 2ffad148dea65a3597e45aff760e8396419a106e..fe17924028cd22ede5c28a79dd38c8fb9d9c64a8 100644 --- a/drivers/usb/host/xhci-brcm.c +++ b/drivers/usb/host/xhci-brcm.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Broadcom. */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index e3e0ceff43e6abdb8643f265819eff28c2c802f4..6cebe1cc30cb6512805f49b324ba0b2aa5b30ce5 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/host/xhci-exynos5.c b/drivers/usb/host/xhci-exynos5.c index 6a2d422c4b8e510bf485c3069287000f8cf77aef..270be934e7fc58e563aeb032acbf12832532c20c 100644 --- a/drivers/usb/host/xhci-exynos5.c +++ b/drivers/usb/host/xhci-exynos5.c @@ -12,6 +12,7 @@ * exynos5 specific PHY-init sequence. */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 3484ae1d21ee78ede669a945616081f643f139c1..e67e09e31e4af8a21296f8b30084ea5507c5588f 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -7,6 +7,7 @@ * Author: Ramneek Mehresh */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 045b0fba81281b5ae36e8e12db2abc82f3ea6bce..72b75306265083e932ea901ea880989c2f0134c8 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -13,6 +13,7 @@ * Vikas Sajjan */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 7e288f0575b6c8064e6c60a466519c0a1b10de86..63dfb793c6bdeac041da58edd5450357ac5d9cbb 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 1338b1021c644facb8243cd1caba0b0fb32f097c..46b89de85d1edf84a1c1270226c8890a71728936 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -5,6 +5,7 @@ * MVEBU USB HOST xHCI Controller */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c index 66da94c0709822fe10404ef4e018de4761929dbc..501129d769a2f99d0809a9e12917a1d4ea52de7d 100644 --- a/drivers/usb/host/xhci-omap.c +++ b/drivers/usb/host/xhci-omap.c @@ -8,6 +8,7 @@ * Author: Dan Murphy */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index f6972af7963d61e350e83d4061291165a9cfc66f..11f1c02000af6dc06f08d7792f145e6a1c649577 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -5,6 +5,7 @@ * All rights reserved. */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 38c5928faed502d66c25babd171c35178b278038..fedcf786929542ce7589802550b1f3fc7248dfb0 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -5,6 +5,7 @@ * Renesas RCar USB HOST xHCI Controller */ +#include #include #include #include diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 1360a5940fa05567bc288c4fc8056131bbb9c655..910c5f3352b805e1895f974aa6f23d8c7c7093e1 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -13,6 +13,7 @@ * Vikas Sajjan */ +#include #include #include #include diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d30725d3fcaae206cd91831befcc0b0b39027787..741e186ee05bc30e7255646ef03f009c234bbf48 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -19,6 +19,7 @@ * The quirk devices support hasn't been given yet. */ +#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c index 96c483fb9afa720ae3b45e41a8f5f87d35677e08..a6c4d97aee3f5af73f722ca424845433596c05db 100644 --- a/drivers/usb/isp1760/isp1760-hcd.c +++ b/drivers/usb/isp1760/isp1760-hcd.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-if.c b/drivers/usb/isp1760/isp1760-if.c index 54246b49d5fef2cdeb3d979773c938b973dca79d..c96ab459f93e66cc2d52930cff52f17163863d39 100644 --- a/drivers/usb/isp1760/isp1760-if.c +++ b/drivers/usb/isp1760/isp1760-if.c @@ -6,6 +6,7 @@ * (c) 2007 Sebastian Siewior */ +#include #include #include #include diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c index 8dcb7768a2c23fab8709f6fc2d588d32744719e4..203500a4cb7ffa9ef7f966e508b49b36635268d4 100644 --- a/drivers/usb/isp1760/isp1760-uboot.c +++ b/drivers/usb/isp1760/isp1760-uboot.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include diff --git a/drivers/usb/mtu3/mtu3_plat.c b/drivers/usb/mtu3/mtu3_plat.c index ca86b58dfcd72e4f5961ed87f1afa3a9d34ce361..b1b22b9357cef0211f79091899249f7ff599e372 100644 --- a/drivers/usb/mtu3/mtu3_plat.c +++ b/drivers/usb/mtu3/mtu3_plat.c @@ -5,6 +5,7 @@ * Author: Chunfeng Yun */ +#include #include #include diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index 42bc816e4f1e5ca0e6fa891c563fea65106e0b43..0a52e09e19f153cd0a40c66f147da4a5062c6449 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -24,6 +24,7 @@ #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/da8xx.c b/drivers/usb/musb-new/da8xx.c index 7caf03cc2e14016d7e0eac9c7ec64442b722a8bb..68fc0c36146d575f38f0031e1db9f33ba0acf791 100644 --- a/drivers/usb/musb-new/da8xx.c +++ b/drivers/usb/musb-new/da8xx.c @@ -13,6 +13,7 @@ * */ +#include #include #include #include diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c index 14b28bbae6b1dbc063a08107d2e328fcd2ee95e6..1e632dca046203baa9c8ca5ce461df33e4561673 100644 --- a/drivers/usb/musb-new/mt85xx.c +++ b/drivers/usb/musb-new/mt85xx.c @@ -9,6 +9,7 @@ * * This file is part of the Inventra Controller Driver for Linux. */ +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 257e7685cfa34200dd89c7c78f1c8377d0545898..00da554982fe519a99764b0ec92c79a1df49b368 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -79,6 +79,7 @@ #include #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index b73f3531ce24694d85631eff53d0b10084f3fe66..a8ff7434c9f7a100e77bd488672b9ceca19fdaea 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -31,6 +31,7 @@ #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index 29e225aa0f11b26ce4a8a6a4dca0a13c2b61d7c0..c6083963ede9a8fcf791412b85d315853c65c44d 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -22,6 +22,7 @@ #include #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 63eee31a6b3e5c016a8d34fc74987f31657b0894..55ce8de99bb17501b352d740eb528f1ffed8c617 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -18,6 +18,7 @@ #include #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 2f2fc7c1359b39e115a53118c867484cd592b2e6..e5905d90d66fb28140fbaccc636ef30646f8341b 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -21,6 +21,7 @@ #include #include #else +#include #include #include #include diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 43ab3245e5c3245540b3b980e3ae5ca4fa93ff8a..7cea9a2ed65c1594fb53bd8c309736ea092c4424 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index c8dd73050b2964a44cfb15eb40b52cf3dd5d8129..308eff832c9ed8d94baffbe990bc9980b5d48d6d 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -8,6 +8,7 @@ * * This file is part of the Inventra Controller Driver for Linux. */ +#include #include #include #include diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c index 0b25e5893b3cbaf9711eb36796c826a30b562bee..4ed5e6e90c6cc497fed7e7ce911918170e2fff2a 100644 --- a/drivers/usb/musb-new/pic32.c +++ b/drivers/usb/musb-new/pic32.c @@ -9,6 +9,7 @@ * Based on the dsps "glue layer" code. */ +#include #include #include #include diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index b577ba4187807f6cd350ec5859fb347030c58f6c..778b01b22ea78d2cc5ed3e5718d3972929e917ff 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -15,6 +15,7 @@ * * This file is part of the Inventra Controller Driver for Linux. */ +#include #include #include #include diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index 76e8b88369e31d9d02fb37b63a395e5c042bbb31..ed5e5194d8c917861f86b82bc69571df55a87122 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -5,6 +5,7 @@ * (C) Copyright 2016 * Texas Instruments Incorporated, */ +#include #include #include #include diff --git a/drivers/usb/musb-new/ux500.c b/drivers/usb/musb-new/ux500.c index 6b4ef3c85782ce2027865c82629b8d17d59083e3..57c7d5630d37e79344acd667e34d984f6702eba3 100644 --- a/drivers/usb/musb-new/ux500.c +++ b/drivers/usb/musb-new/ux500.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ +#include #include #include #include diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index 2c23043d40e965baa18909f3f4f10706a3f75844..f945f1f5e2c584c830c4f8a1a9e0678ef6420cb0 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -9,6 +9,7 @@ * Copyright (c) 2010 Texas Instruments Incorporated */ +#include #include #include "am35x.h" diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index 260552e4dbd424ce3375a6bd3a181ec9f1fc9c6e..9651f074a49d4c277cbdecab9496c3a6d33f160a 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -8,6 +8,7 @@ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments */ +#include #include #include "musb_core.h" diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index c95c6a4828126906f69ee49f520e5c091b22beeb..4676cabae0aa763c226c5613567f63ee2a26b0f2 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -7,6 +7,7 @@ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments */ +#include #include #include #include diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index 696855ee3a613bcb9cfaa0eb443df5a45bc510a5..2ffcb7caaad7b0417ecfc62d180cb332d58eab7b 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -37,6 +37,7 @@ * ------------------------------------------------------------------------- */ +#include #include #include #include diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c index 9ec5b2d172b875680c54895656f129079009248d..c46ad86d3d658afad4eaef930d3b5a8d741bcd8c 100644 --- a/drivers/usb/phy/rockchip_usb2_phy.c +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -3,6 +3,7 @@ * Copyright 2016 Rockchip Electronics Co., Ltd */ +#include #include #include #include diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c index 6f0c3eb154ee40ce57d6a4cf10613043060d87ca..1b01cd4c559f7b2e7b2b6df188b1cb2e391efe50 100644 --- a/drivers/usb/ulpi/omap-ulpi-viewport.c +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c @@ -7,6 +7,7 @@ * Author: Govindraj R */ +#include #include #include #include diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c index bac20a02f01834e9cee677694fb950109a53c4af..55a62808384dac39473d1adce27fdfe56a3afa65 100644 --- a/drivers/usb/ulpi/ulpi-viewport.c +++ b/drivers/usb/ulpi/ulpi-viewport.c @@ -13,6 +13,7 @@ * Copyright (C) 2011 Google, Inc. */ +#include #include #include #include diff --git a/drivers/usb/ulpi/ulpi.c b/drivers/usb/ulpi/ulpi.c index 128adcbde134bc5a3b3705c3ddd932b540b54cd4..b5d2c2c2d1c305e6e3ef457c7cbab2d8fd52d64c 100644 --- a/drivers/usb/ulpi/ulpi.c +++ b/drivers/usb/ulpi/ulpi.c @@ -19,6 +19,7 @@ * Freescale Semiconductors */ +#include #include #include #include diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index a149e6f5b95d46a8a178dd107903c87e6967fa5d..52b5988ba5f23e4f342342d140c4f27ea729e80b 100644 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -9,6 +9,7 @@ * interface for driving eDP TFT displays. */ +#include #include #include #include "anx98xx-edp.h" diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 89bc0eeb680acd72bcd891248fa6e09215a832d9..652ba1418018a154ecf069fbbdd6b1140b06c864 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -5,6 +5,7 @@ * Copyright (C) 2012 Atmel Corporation */ +#include #include #include #include diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 281c3a1d6632b2e4b97b9feed9038107ca4c1610..5a7a54ada70e1e7f2fd97c5a80ca907f31988327 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -5,6 +5,7 @@ * Copyright (C) 2007 Atmel Corporation */ +#include #include #include #include diff --git a/drivers/video/backlight-uclass.c b/drivers/video/backlight-uclass.c index 2a09b2da91063dc8c6ede1a2be084798618924fc..c14996d003c00041c7fe5a88b085d60b04717d7b 100644 --- a/drivers/video/backlight-uclass.c +++ b/drivers/video/backlight-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT +#include #include #include diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c index b26fa9a8acf1515876dd3728aaeb7e6d08bcb68d..eea824ab5e16ee263126c866c1173d3fa69252c8 100644 --- a/drivers/video/backlight_gpio.c +++ b/drivers/video/backlight_gpio.c @@ -4,6 +4,7 @@ * Author: Patrick Delaunay */ +#include #include #include #include diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 0c81e6066229049c8185d71bf8a3ca5e0364835a..63efa762db160abe5e15dcf80b10831b8bd9234c 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -3,6 +3,7 @@ * (C) Copyright 2012 Stephen Warren */ +#include #include #include #include diff --git a/drivers/video/bmp.c b/drivers/video/bmp.c index 291ed36440c8bf17ae2b4fadda785123951851fd..bab6fa7265af3ef5bf833336905bd2c7f3353568 100644 --- a/drivers/video/bmp.c +++ b/drivers/video/bmp.c @@ -8,6 +8,7 @@ * BMP handling routines */ +#include #include #include #include diff --git a/drivers/video/bochs.c b/drivers/video/bochs.c index 00e673a4db08bc65d36da0815035a5c6d923a85c..022ea38d4cfecc97403f16e2886a6fb4f7149029 100644 --- a/drivers/video/bochs.c +++ b/drivers/video/bochs.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_VIDEO +#include #include #include #include diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 8cee4c958bd8f17a97be9a738cce7127ec67328b..93fa25f16e31365eaddb465dc22c78d27a26f31c 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Vasily Khoruzhick */ +#include #include #include #include diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c index efd03752281c90cb710ad4f45596f16928f4fe53..d1d22a6e235cd842d946ad61a82f9c7eb183e205 100644 --- a/drivers/video/bridge/ps862x.c +++ b/drivers/video/bridge/ps862x.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c index 5851e1ef15e9a9608b92bcf5592578e579ee0733..4760f04108f7e46e6e183f11d580352aa63a8b0a 100644 --- a/drivers/video/bridge/ptn3460.c +++ b/drivers/video/bridge/ptn3460.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c index f978021c860e6e8637f5e57afdb2076ce815ae70..f0ef3dafb93b09be3c230f78b7840bf5fbc40ae2 100644 --- a/drivers/video/bridge/ssd2825.c +++ b/drivers/video/bridge/ssd2825.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index 2084a2e03ee830b0900b64fbd545a1bdb946dc6d..f389bc6b14753613f14e41e5a06adbc3242d4767 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_VIDEO_BRIDGE +#include #include #include #include diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c index a26154ab588f9b65073eaf1e86f765e38848499b..83b6c908a8db565ff6b97c64f5ef79eb8302e588 100644 --- a/drivers/video/broadwell_igd.c +++ b/drivers/video/broadwell_igd.c @@ -5,12 +5,12 @@ * Copyright (C) 2016 Google, Inc */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 6f4194a1814747bca85944b40835ebeb099b4826..34ef5a5229426840f0c100e2d5cb30c38ed19adc 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -6,6 +6,7 @@ * (C) Copyright 2023 Dzmitry Sankouski */ +#include #include #include #include diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index dc969836274108c9e1665f4d1154d6ec604358c3..e4303dfb364c48152206f60b52d40a5e856d8aea 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -6,6 +6,7 @@ * (C) Copyright 2023 Dzmitry Sankouski */ +#include #include #include #include diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index c435162d3f946f58792583e817be841ebfec060d..28665a327575708fde86eafcfaa80c290e3983e0 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -3,6 +3,7 @@ * Copyright (c) 2016 Google, Inc */ +#include #include #include #include diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c index 9aede2626423ea32569259e0a57b520a5e987efd..5b718ae3e5a5e409486b756348cabde4b9c57ed8 100644 --- a/drivers/video/coreboot.c +++ b/drivers/video/coreboot.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index 61a73e1bc2a629eae6a9210434641a9babaf9dea..2da3d1d14e958c9853f7a04edc5bc13492275e99 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_DISPLAY +#include #include #include #include diff --git a/drivers/video/dsi-host-uclass.c b/drivers/video/dsi-host-uclass.c index fde275ad7e2ed575b84382648c663be75544c275..6e5256eb1265402cb053e9e34bfe42475f584377 100644 --- a/drivers/video/dsi-host-uclass.c +++ b/drivers/video/dsi-host-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_DSI_HOST +#include #include #include diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index 35559cef22985fc243464a2942b7ef97c5b1eea3..c217af97878eabd4c85f3fa7364300d3a2cee896 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -5,14 +5,13 @@ * Copyright 2017 Jernej Skrabec */ +#include #include #include #include #include #include -#include #include -#include #include "dw_hdmi.h" struct tmds_n_cts { diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index c74fe678d12a5615ffaad4e14b371a8d45225da6..a7e0784596a985799bc0b101a26c0da3d2f03b6d 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -9,6 +9,7 @@ * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c. */ +#include #include #include #include diff --git a/drivers/video/efi.c b/drivers/video/efi.c index 78d123fad4be3ecd0570d7f954944d981298bf10..28ac15ff61b9484e545546c96936aeab750e2035 100644 --- a/drivers/video/efi.c +++ b/drivers/video/efi.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_EFI +#include #include #include #include diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c index d4ba4d8b6da64681e2806216a3727a0835ae2272..1bff641434e1980a7a7b51d551afdbe73f756c33 100644 --- a/drivers/video/endeavoru-panel.c +++ b/drivers/video/endeavoru-panel.c @@ -3,6 +3,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/video/exynos/exynos_dp.c b/drivers/video/exynos/exynos_dp.c index b0afb2338fb74b8a344d17e4b1f2e4d9453573c8..59838da6c9260e603a6aecc42e8fbaae674d42f3 100644 --- a/drivers/video/exynos/exynos_dp.c +++ b/drivers/video/exynos/exynos_dp.c @@ -5,6 +5,7 @@ * Author: Donghwa Lee */ +#include #include #include #include diff --git a/drivers/video/exynos/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c index f007b319b20e78d4d3b4b3306a81966c57a6d129..ae500a702804d0b3367f3860fb0d64e50d93bb6a 100644 --- a/drivers/video/exynos/exynos_dp_lowlevel.c +++ b/drivers/video/exynos/exynos_dp_lowlevel.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c index 0407a3f51b0d0b3dbb43e2979055208540d5549a..86970a6d5d20bdbcc7b58e2bca6ca21be224fc97 100644 --- a/drivers/video/exynos/exynos_fb.c +++ b/drivers/video/exynos/exynos_fb.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index edeb0a87bbb7bf88df705527102ae58688f6b399..804fcd0b248486cc4404152e2f0b6eb39c09f1f2 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -6,6 +6,7 @@ * Author: Donghwa Lee */ +#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c index fc2767adc38c2400d46fe072ef0f5b69135ec920..be67cebae7f2439ed36485f84e107fbff427ddb9 100644 --- a/drivers/video/exynos/exynos_mipi_dsi_common.c +++ b/drivers/video/exynos/exynos_mipi_dsi_common.c @@ -6,6 +6,7 @@ * Author: Donghwa Lee */ +#include #include #include #include diff --git a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c index 9f18b5da10262a45282fb4402fd847eae861b18e..8111acd9a0b592c31b0ff2011baef92c3a0add76 100644 --- a/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c +++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c @@ -6,6 +6,7 @@ * Author: Donghwa Lee */ +#include #include #include #include diff --git a/drivers/video/himax-hx8394.c b/drivers/video/himax-hx8394.c index cb7f93e9c997f488788e0759a9cb7f5f9cf5d771..63637b4db0223974ed06ef14bbb84fe16e1f9ba6 100644 --- a/drivers/video/himax-hx8394.c +++ b/drivers/video/himax-hx8394.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2022 Ondrej Jirman */ +#include #include #include #include diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c index 68f7b75eef99220730814c768036ffec9fdee0e0..95984fe3d3d1bab04d26a6165ef0415ed4bfc150 100644 --- a/drivers/video/hitachi_tx18d42vm_lcd.c +++ b/drivers/video/hitachi_tx18d42vm_lcd.c @@ -5,6 +5,7 @@ * (C) Copyright 2015 Hans de Goede */ +#include #include #include diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index 2491a32810e235c346142b9bd3d4c18819e03d12..6ee97cb4ff3a8ae344fae7ca766284ea384a865f 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -12,6 +12,7 @@ * */ +#include #include #include #include diff --git a/drivers/video/ihs_video_out.c b/drivers/video/ihs_video_out.c index bf4d4995c36c869d328e46e6f834eea29c190f5a..73b8f4bd1c9bd3919db032defe52c4e2f602d058 100644 --- a/drivers/video/ihs_video_out.c +++ b/drivers/video/ihs_video_out.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de */ +#include #include #include #include diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index d582fb8ad9d914c32081e5a0f09469042f6ea4ac..b0a99c9cd5d95670c680b3e432f5d01331f27ad6 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -11,7 +11,7 @@ */ /* #define DEBUG */ -#include +#include #include #include #include diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c index aaba7d135a4622a71fa99abf0f68b39ef6ad59d8..144322e4e26be127c81443cfb2538da4075c0462 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c @@ -12,6 +12,7 @@ /* #define DEBUG */ +#include #include #include #include diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 039b22086a93ca6498efafdff00a2393e70be687..7e60385bcfa512a68d88e9b2d8d94c217fe30a75 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -10,6 +10,7 @@ * (C) Copyright 2004-2010 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index ad688640733e98573ef9abc1e6e585d1259fac2e..c2cc976618a11149ba3cbf5e6b19e8c4f08cd22d 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Google, Inc */ +#include #include #include #include diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c index 6b51fa0628e4c152539968626c8f8f4ce7e24308..00297a09b7fcee613e723d34fa2c14462266d3fa 100644 --- a/drivers/video/lm3533_backlight.c +++ b/drivers/video/lm3533_backlight.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT #include +#include #include #include #include diff --git a/drivers/video/logicore_dp_tx.c b/drivers/video/logicore_dp_tx.c index 643a77a0f4e14e156aae61d12ec1cd39be0a264f..624084d38bcacefa4b4b7f13808c34f598da4a7f 100644 --- a/drivers/video/logicore_dp_tx.c +++ b/drivers/video/logicore_dp_tx.c @@ -9,6 +9,7 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */ +#include #include #include #include diff --git a/drivers/video/mali_dp.c b/drivers/video/mali_dp.c index c89212674624505d2f56f9c6633fd0c419f78b0d..dbb2f538617178afa6305f1ef966fcf612bb4856 100644 --- a/drivers/video/mali_dp.c +++ b/drivers/video/mali_dp.c @@ -5,6 +5,7 @@ * */ #define DEBUG +#include #include #include #include diff --git a/drivers/video/mcde_simple.c b/drivers/video/mcde_simple.c index 2ba5d0de1529180a830c664db5b4140df224af48..0924ceee3098ba141b1db9e982b6671ed8f07f92 100644 --- a/drivers/video/mcde_simple.c +++ b/drivers/video/mcde_simple.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright (C) 2019 Stephan Gerhold */ +#include #include #include #include diff --git a/drivers/video/meson/meson_canvas.c b/drivers/video/meson/meson_canvas.c index dd4c546222d57acc9312acc8c616ada0caf6364d..eccac2f8f24a4fd0866bdf3c7c1db0789cd88ba0 100644 --- a/drivers/video/meson/meson_canvas.c +++ b/drivers/video/meson/meson_canvas.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 587df7beb9b0d2c703de7afe1031ae1fce405f07..259af1b45717a3c1db263a5212f4679f20ac5abd 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -4,6 +4,7 @@ * Author: Jorge Ramirez-Ortiz */ +#include #include #include #include diff --git a/drivers/video/meson/meson_plane.c b/drivers/video/meson/meson_plane.c index 899ce22d067e36c030c63dcec2365d4ecb6fa04d..e3f784ecfe427ee67007c50d863ebcb19fafa3ef 100644 --- a/drivers/video/meson/meson_plane.c +++ b/drivers/video/meson/meson_plane.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/video/meson/meson_vclk.c b/drivers/video/meson/meson_vclk.c index 4761ff661e4ed5d3aa113bb43c123fab57f1b1e7..e718a0074ed6a70633209ee45e3471fd4870dcce 100644 --- a/drivers/video/meson/meson_vclk.c +++ b/drivers/video/meson/meson_vclk.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/video/meson/meson_venc.c b/drivers/video/meson/meson_venc.c index 1bc6aaf73055e58008b3764097f5f551eae20538..e7366dd2fdeaaee91041bf42ded707a677a53059 100644 --- a/drivers/video/meson/meson_venc.c +++ b/drivers/video/meson/meson_venc.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743b8b74407b2b42703180ef8f1102d2..67d4ce7b3b49a970ed33b2c7e28a47fe22d8aca1 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -6,6 +6,7 @@ * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/video/meson/meson_vpu_init.c b/drivers/video/meson/meson_vpu_init.c index 0e34cefd1002e71c0c81fabe3cb6ee0df8344e3c..c9808e1c63176a7e2c846ab13bb88ec73760fd0c 100644 --- a/drivers/video/meson/meson_vpu_init.c +++ b/drivers/video/meson/meson_vpu_init.c @@ -8,6 +8,7 @@ #define DEBUG +#include #include #include #include diff --git a/drivers/video/mipi_dsi.c b/drivers/video/mipi_dsi.c index dc949c8ae61f4268ae693625e0dd1871d4dbd658..ecacea1dbebdf549417dd375568bdebaf2580873 100644 --- a/drivers/video/mipi_dsi.c +++ b/drivers/video/mipi_dsi.c @@ -32,6 +32,7 @@ * */ +#include #include #include #include diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c index 3fc5640b71ec45fd9d5dbd93c8f21b0353748898..d3d07e5f83334ace424b13d514a25255fd391f4b 100644 --- a/drivers/video/mvebu_lcd.c +++ b/drivers/video/mvebu_lcd.c @@ -5,6 +5,7 @@ * Initialization of LCD interface and setup of SPLASH screen image */ +#include #include #include #include diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 792d6314d15ef50797c946aa4c3f0683eeec2ec6..515363f6a49bc808b810a2b6bc6c52abc9886881 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -4,6 +4,7 @@ * * Copyright (C) 2011-2013 Marek Vasut */ +#include #include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp.c b/drivers/video/nexell/s5pxx18_dp.c index 16a489b88dc299423bc90a12ae17abfca55b8ac5..2248f479057548052a025f0cc627587775734d8a 100644 --- a/drivers/video/nexell/s5pxx18_dp.c +++ b/drivers/video/nexell/s5pxx18_dp.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_hdmi.c b/drivers/video/nexell/s5pxx18_dp_hdmi.c index 109d9f28bb01d635377226f4381b82e418508ab0..3f1fb8a5757b279c2063e9c29d156076dc0760cb 100644 --- a/drivers/video/nexell/s5pxx18_dp_hdmi.c +++ b/drivers/video/nexell/s5pxx18_dp_hdmi.c @@ -6,6 +6,7 @@ */ #include +#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_lvds.c b/drivers/video/nexell/s5pxx18_dp_lvds.c index 5db8d2b73b142aaec35e0d490782d702d0575b65..f8ea63fdf1b38e0f7f8794ae33f04d732b76c3d2 100644 --- a/drivers/video/nexell/s5pxx18_dp_lvds.c +++ b/drivers/video/nexell/s5pxx18_dp_lvds.c @@ -6,8 +6,8 @@ */ #include +#include #include -#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_mipi.c b/drivers/video/nexell/s5pxx18_dp_mipi.c index 58493a825982b471c65e5413b29ffcfe66566b8d..670272b26802a74047127913f315344fa2f6244f 100644 --- a/drivers/video/nexell/s5pxx18_dp_mipi.c +++ b/drivers/video/nexell/s5pxx18_dp_mipi.c @@ -6,6 +6,7 @@ */ #include +#include #include #include diff --git a/drivers/video/nexell/s5pxx18_dp_rgb.c b/drivers/video/nexell/s5pxx18_dp_rgb.c index 6abb8b5e216b355f060a576256b6e8549d7f0af5..44e8edb02a22aa28208ee4c926a73eaafb0cc257 100644 --- a/drivers/video/nexell/s5pxx18_dp_rgb.c +++ b/drivers/video/nexell/s5pxx18_dp_rgb.c @@ -6,8 +6,8 @@ */ #include +#include #include -#include #include diff --git a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h index 4ad353256ebcb2fa7fa917e34ebbdfcf3674c166..c7bf5043e6053383951a3ebe58ea1ab98cafca67 100644 --- a/drivers/video/nexell/soc/s5pxx18_soc_disptop.h +++ b/drivers/video/nexell/soc/s5pxx18_soc_disptop.h @@ -8,7 +8,6 @@ #ifndef _S5PXX18_SOC_DISPTOP_H_ #define _S5PXX18_SOC_DISPTOP_H_ -#include #include "s5pxx18_soc_disptype.h" #define NUMBER_OF_DISPTOP_MODULE 1 diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index 7bda33fb16e10e57a91d485d3c03051028726ead..af2698ffca846a0581d12feab8395a0562d5511e 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index 0b7ce348d5ad8fa6a1b32c14ce95c98a49987051..432b16bfbfe796ed5fe22d354e087c60cbba434c 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -25,6 +25,7 @@ * MA 02111-1307 USA */ +#include #include #include diff --git a/drivers/video/orisetech_otm8009a.c b/drivers/video/orisetech_otm8009a.c index a29e909decc9800cd41c078bb0d7dd548079490f..848f174b6e48708976e05021e554d53ccd1a1e19 100644 --- a/drivers/video/orisetech_otm8009a.c +++ b/drivers/video/orisetech_otm8009a.c @@ -7,6 +7,7 @@ * This otm8009a panel driver is inspired from the Linux Kernel driver * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c. */ +#include #include #include #include diff --git a/drivers/video/panel-uclass.c b/drivers/video/panel-uclass.c index 52a3466dc8c1203731dfcb62ebf4e63ed390bbb4..1f7e20e0b50648b7062480039067074bd9f0125e 100644 --- a/drivers/video/panel-uclass.c +++ b/drivers/video/panel-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PANEL +#include #include #include diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c index a4576c888cf0244ff2733c2304479e372e552034..1c747d98d7acfdd1d3024d3523af94e01fceff5c 100644 --- a/drivers/video/pwm_backlight.c +++ b/drivers/video/pwm_backlight.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT +#include #include #include #include diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c index b8662ca22bf2995d2aa83f9f77ae988de104d766..f1fce55a2cb2f9e186fc98dc411554b97745a379 100644 --- a/drivers/video/raydium-rm68200.c +++ b/drivers/video/raydium-rm68200.c @@ -7,6 +7,7 @@ * This rm68200 panel driver is inspired from the Linux Kernel driver * drivers/gpu/drm/panel/panel-raydium-rm68200.c. */ +#include #include #include #include diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c index a3697bce5ee3a6de40edac9a7aaed3b0c68bf1a7..3f5859055c983d1c3a859db6955817a5fdaa3bd5 100644 --- a/drivers/video/renesas-r61307.c +++ b/drivers/video/renesas-r61307.c @@ -5,6 +5,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c index 9861c3fef11acc697574d54cebdaf49cb6d236e0..082f5bc3d0a01306188c3f66f8d977dde4146c7d 100644 --- a/drivers/video/renesas-r69328.c +++ b/drivers/video/renesas-r69328.c @@ -5,6 +5,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index fa512173510b1ee6f51e6269eb249e24d0e980f8..fb784636e8774c67223f60878122faaafc0fbb8f 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index 3d39f31a5ade309cd32e8f0675341cc280922186..efa87540340bb5ce4bad4454bdab57b389fea307 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 850fe310754959e6ce7e260ce35d911020ade153..9d42119c82611ac83d44553d8ffc0311bfa611a6 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -4,6 +4,7 @@ * Author: Eric Gao */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 282831eaac4466d99082b5f7fd863fbcb9a23e62..a4683852ea0c6093e624c3781667d2188ee4432f 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -5,6 +5,7 @@ * Copyright 2014 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c index c7630ccf55588ce9d5c41f429cceeb67e3e57b69..5f3f5d26886d14f9ab0fb9767f8e1347708c50a6 100644 --- a/drivers/video/rockchip/rk3399_hdmi.c +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -3,6 +3,7 @@ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 57e36eed6a999497c21223a019649c3749bccc9b..b62d80866745d21c034aea5b633ea496fec2c153 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -4,6 +4,7 @@ * Author: Eric Gao */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 17e1601e81444e4cf971ccd3ecc603504790d2bb..cb589c7537e697e90063edbb89bb0a1780c854ff 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -5,6 +5,7 @@ * Copyright 2014 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index eb881ba4b0efbdbe9cbfe4b135aacd7a67445334..5f68a610e4accddf218bb1b038c311dd49b68bc7 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -4,6 +4,7 @@ * Copyright 2014 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 0ac0a3a1ecd0d0d7b780e4af5b13f8ec1a593379..d31f6a4ff81b306d946cb58a253cc6893134baac 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -5,6 +5,7 @@ * Copyright 2014 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index c969dae30b6912b122a1a8ae0c2a4789c7015312..d0a015e31ee882af8c42bdf7dc1f5ea3b6adad83 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -3,6 +3,7 @@ * Copyright 2016 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 0a603083ba9a561501ab2d8f37e00ea98b734aa0..f14cbc6dbf7f9606e01720adbbec63963ebc8519 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -4,6 +4,7 @@ * Author: Eric Gao */ +#include #include #include #include diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index 17dfe62c9dae72a0f45544a82718a8aeafb50f84..acc02e5d7c7813122a06bdf091e8f9d930f8a453 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -4,6 +4,7 @@ * Copyright 2014 Rockchip Inc. */ +#include #include #include #include diff --git a/drivers/video/sandbox_dsi_host.c b/drivers/video/sandbox_dsi_host.c index 7025ac986e3ceb34f95264dcf7e40f9f3fa1a559..c84a27ee3be6f973dec32e6e303a7202eae3200f 100644 --- a/drivers/video/sandbox_dsi_host.c +++ b/drivers/video/sandbox_dsi_host.c @@ -3,6 +3,7 @@ * Copyright (C) 2019, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/drivers/video/sandbox_osd.c b/drivers/video/sandbox_osd.c index bedc32b7c80e5ba220949f7a76ad3c5440b4ec24..2a854d3958b7b6276e66112eb5ab0482a054ead4 100644 --- a/drivers/video/sandbox_osd.c +++ b/drivers/video/sandbox_osd.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 69dfa9302735b0f23bf3c4065516135ccb89d7f0..9081c7da62e4b52f1e8009b9c54d338176192618 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/drivers/video/seps525.c b/drivers/video/seps525.c index 86cd301c4b91398b9f804ac86fdc86023b1e8a61..74c8721e1e11d2a9997083b853515358b8cfd233 100644 --- a/drivers/video/seps525.c +++ b/drivers/video/seps525.c @@ -6,6 +6,7 @@ * Copyright (C) 2020 Xilinx Inc. */ +#include #include #include #include diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index b6c5b058b2e967bbbd47ab3c3ce5ca52c7804409..76a30427a59f2efa57230e54b0ce8a423aaa816f 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index cb518b149cb58b53a885882d475e20a2713878f3..33bb78bc3a3e44b8d3600c9046238200b99bfde3 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -3,6 +3,7 @@ * (C) Copyright 2017 Rob Clark */ +#include #include #include #include diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 4334bbd72353da3a33ead8cdc62e7f7aef677e36..948f5e74d0fee1e1715fb454eaea6778460161b9 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -9,6 +9,7 @@ * interface for driving a MIPI compatible TFT display. */ +#include #include #include #include diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 438ed41e8d5f03ab54b70c191acc0882cd8721ea..a18c1e027a87088cb7326b8ca4e1d025355cdd96 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY UCLASS_VIDEO_BRIDGE +#include #include #include #include diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 0a062c8939dbe49b11aa50f5ca9701bdbe5c5b0b..4f60ba8ebeeb49f72f14643c4a2c88daa3aeaee6 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_VIDEO +#include #include #include #include diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 264d775c1256ae5da7e430337995bb8cfd63c547..73033c3b858968ef242d3704bb6d8291f4dfd0e5 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -7,6 +7,7 @@ * (C) Copyright 2017 Jernej Skrabec */ +#include #include #include diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a699d0c57475a55789af8f791b92dc64..e02d359cd25930341434a852e473d2fd3f3406fa 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -5,6 +5,7 @@ * (C) Copyright 2017 Jernej Skrabec */ +#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2640a8b44c10dc767b6db42c864794..8da44a1bb6d8a0970f360e6d079174c67a23e617 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -6,7 +6,7 @@ * (C) Copyright 2014-2015 Hans de Goede */ -#include +#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index b9c03ea03864b6ba278e5e8a98d8cb8c8eac2e68..a5e8d39e98f87c173279bc2a7cf531c3429da699 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 953233fcd6838c58aa69f020ea0d7ba9e19c6280..7a01cc343cac3734a62aa5ca5f2d3a3e49865709 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -5,6 +5,7 @@ * (C) Copyright 2017 Vasily Khoruzhick */ +#include #include #include #include diff --git a/drivers/video/sunxi/tve_common.c b/drivers/video/sunxi/tve_common.c index 7bc2b3b29090ec5cc42718feba0d6d55a578906c..35251371d14f6c9244e65a2f6d71dc83953bf2a5 100644 --- a/drivers/video/sunxi/tve_common.c +++ b/drivers/video/sunxi/tve_common.c @@ -7,6 +7,7 @@ * (C) Copyright 2017 Jernej Skrabec */ +#include #include #include diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c index ebc8521c6edd811687006a69ad9240ee7dd4c5d0..2448743904547ced45697653c65d46350d8c281d 100644 --- a/drivers/video/tda19988.c +++ b/drivers/video/tda19988.c @@ -5,6 +5,7 @@ * Based on the Linux driver, (C) 2012 Texas Instruments */ +#include #include #include #include diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c index d772958f46eddeacc2383e24d63bfb376e90abae..273672db024af4b264c9d21bf18ccb7df035c4f2 100644 --- a/drivers/video/tdo-tl070wsh30.c +++ b/drivers/video/tdo-tl070wsh30.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 BayLibre, SAS * Author: Neil Armstrong */ +#include #include #include #include diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c index abe31e27d84d5a6ad273de655870f91185a83f3c..9261cc9384a2b628ae19dc5fafdeee2ba001cda1 100644 --- a/drivers/video/tegra124/display.c +++ b/drivers/video/tegra124/display.c @@ -5,6 +5,7 @@ * Extracted from Chromium coreboot commit 3f59b13d */ +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra124/dp.c index 763f7ee39fcdc00fb8d0c5bf35b9ecbb1c8f228b..b27b1633bab56538358d2a93a199eb501efea494 100644 --- a/drivers/video/tegra124/dp.c +++ b/drivers/video/tegra124/dp.c @@ -4,12 +4,12 @@ * Copyright 2014 Google Inc. */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c index 1ce5330c6bcf8750c5a5adb3c92ccd8743d01b59..258685182c7df75400fb422291431b39d246353d 100644 --- a/drivers/video/tegra124/sor.c +++ b/drivers/video/tegra124/sor.c @@ -3,6 +3,7 @@ * Copyright (c) 2011-2013, NVIDIA Corporation. */ +#include #include #include #include diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra20/mipi-phy.c index 576262e405d60bc2fc98f6ca0fd927cb1eb6561c..c3ebc4074b536165a2349bc39653681236a2b7d6 100644 --- a/drivers/video/tegra20/mipi-phy.c +++ b/drivers/video/tegra20/mipi-phy.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 NVIDIA Corporation */ +#include #include #include "mipi-phy.h" diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index 35a8e6c176b3ad1e87642a9c29554d828a74f351..13dae37806f1fcc92b1194a2c35ffdbe05e8741e 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -4,6 +4,7 @@ * Copyright (c) 2022 Svyatoslav Ryhel */ +#include #include #include #include diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c index 79d8a021a3ac1a6c60ac744e0f10d0a0f839f1f0..5f93f57fe9086bf2a55f9cf5a82727edcb01b2bd 100644 --- a/drivers/video/tegra20/tegra-pwm-backlight.c +++ b/drivers/video/tegra20/tegra-pwm-backlight.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT #include +#include #include #include #include diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c index d40765230600b7df02c4d2ebaa1c1e199b15b0fd..df95086a5151521f9c65d50fbf42a984921a743c 100644 --- a/drivers/video/ti/tilcdc-panel.c +++ b/drivers/video/ti/tilcdc-panel.c @@ -5,6 +5,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c index 493e2f18cd2df18252d789f3f8d9c6c6a59475f8..2734754ecde7574b6f247c64aa88c3a84144321f 100644 --- a/drivers/video/ti/tilcdc.c +++ b/drivers/video/ti/tilcdc.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Dario Binacchi */ +#include #include #include #include diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index 865d4bddb7f917c6b2dbf72cbb76ddaacf3cd53a..1380c6b69375b9ab225a02362e313e9c478067a2 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -9,6 +9,7 @@ * Author: Tomi Valkeinen */ +#include #include #include #include diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c index ab756ac8ea128b1c3ddf43f574df8fe5a9f2f6aa..50912c5c8bcadaeb1cf0edc1bdc56c2b99ba1146 100644 --- a/drivers/video/vesa.c +++ b/drivers/video/vesa.c @@ -3,6 +3,7 @@ * Copyright (C) 2016, Bin Meng */ +#include #include #include #include diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 80e7adf6a1a4fd42ec00e56fd1254ece1382e42d..5d06e51ff236b2acc0d7d40fd12c2dc171bc2bd5 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -9,6 +9,7 @@ #define LOG_CATEGORY UCLASS_VIDEO_CONSOLE +#include #include #include #include diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index ff1382f4a43b76869956ca971f5c77fe9c3e871a..7b5d1dfbb3bdb2ea0d35137c73674c040b6b8fca 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_VIDEO +#include #include #include #include diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index ad512d99a1b9133b4166fa63cf3b14751125e8f5..45f003c8251ae01861ecb812f83cc94774d110bf 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 Google, Inc */ +#include #include #include #include diff --git a/drivers/video/video_osd-uclass.c b/drivers/video/video_osd-uclass.c index 923686345ff7d36eac54d5417258af63cf8e09af..0d3aae4d82722d8d9fcd37dd7caaf459da41dc0b 100644 --- a/drivers/video/video_osd-uclass.c +++ b/drivers/video/video_osd-uclass.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_VIDEO_OSD +#include #include #include diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index d86d86798415852ad58e0109c7d588759db748b7..35955a5df7dd6de2ebfd6ef4029ea79c24f2d012 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -55,6 +55,7 @@ "myvideo" and setting the variable "videomode=myvideo".. ****************************************************************************/ +#include #include #include #include diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 1405b29cb8b904da628e73bd37bc5349269550f1..def4dcf6261a4ae36962459ca0faffe8c7c66421 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -6,6 +6,7 @@ * Xilinx displayport(DP) Tx Subsytem driver */ +#include #include #include #include diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index 1dbc1a56aa2159adb3ecccda640c018c07ff55f0..c5420162735212afe8099c2c5d548650b9d85dcc 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -17,6 +17,7 @@ #define LOG_CATEGORY UCLASS_VIRTIO +#include #include #include #include diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 3404f61eba5ffdb10f9ec64631c1c51e2eece2d5..95810582867c78185cac41831bca7309c3198f6e 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -6,6 +6,7 @@ #define LOG_CATEGORY UCLASS_VIRTIO +#include #include #include #include diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 1cd737aca2499272bc5aa1cd80991885b62f60a4..78c15c821b4edabb0a74c01b30f0537ce021648c 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -7,6 +7,7 @@ * Ported from Linux drivers/virtio/virtio_mmio.c */ +#include #include #include #include diff --git a/drivers/virtio/virtio_net.c b/drivers/virtio/virtio_net.c index 0e5367a085e4e75b659118930d88bf6696b15936..1794f73a8de832289b8e75a902b4c589badbec24 100644 --- a/drivers/virtio/virtio_net.c +++ b/drivers/virtio/virtio_net.c @@ -4,6 +4,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c index 15f8c6e7d257dd9d07b1edfdb5b9da50b61697c8..aa89604ae84dc80884126f0cb0489d88cec12bc0 100644 --- a/drivers/virtio/virtio_pci_legacy.c +++ b/drivers/virtio/virtio_pci_legacy.c @@ -6,6 +6,7 @@ * Ported from Linux drivers/virtio/virtio_pci*.c */ +#include #include #include #include diff --git a/drivers/virtio/virtio_pci_modern.c b/drivers/virtio/virtio_pci_modern.c index 5850e0c18c693941facbfc3a9b3ba90066a3c9e5..3cdc2d2d6fd3046915378d101599f37f8bd0982d 100644 --- a/drivers/virtio/virtio_pci_modern.c +++ b/drivers/virtio/virtio_pci_modern.c @@ -6,6 +6,7 @@ * Ported from Linux drivers/virtio/virtio_pci*.c */ +#include #include #include #include diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 306fa5b3f6816cac82b52946644f9120dae09f5e..c9adcce5c09ba18892fd8ec8291fcefa8b19041e 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c index 90a371a59cc73d33066d20e280fc42597ac9006c..786359a6e3641d76dd5dccf8f1d1bd8435d5e853 100644 --- a/drivers/virtio/virtio_rng.c +++ b/drivers/virtio/virtio_rng.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, Linaro Limited */ +#include #include #include #include diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c index 0f1ebef22e58692154881c4ff68fd6208d965fba..b34f1d60455e554cb3b2ddf0b7fd0bd357c9b163 100644 --- a/drivers/virtio/virtio_sandbox.c +++ b/drivers/virtio/virtio_sandbox.c @@ -5,6 +5,7 @@ * VirtIO Sandbox transport driver, for testing purpose only */ +#include #include #include #include diff --git a/drivers/w1-eeprom/ds24xxx.c b/drivers/w1-eeprom/ds24xxx.c index 413d8bc58814514178b53a29541a53562ad8bbbd..4be378b43d03540342cf1e0342b18ecac5abc7e5 100644 --- a/drivers/w1-eeprom/ds24xxx.c +++ b/drivers/w1-eeprom/ds24xxx.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c index db9f41e972692ef6eccb700da5c93149046c8da0..a67f5edd0febb010c4315a55eab9eb28fe5831fd 100644 --- a/drivers/w1-eeprom/ds2502.c +++ b/drivers/w1-eeprom/ds2502.c @@ -20,6 +20,7 @@ * Martin Fuzzey */ +#include #include #include #include diff --git a/drivers/w1-eeprom/eep_sandbox.c b/drivers/w1-eeprom/eep_sandbox.c index 2a69ca27de793299d33dbd1a548b908465f64fd7..27c7f9f1b6b85ce68dacd81476bad3d6927f0268 100644 --- a/drivers/w1-eeprom/eep_sandbox.c +++ b/drivers/w1-eeprom/eep_sandbox.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/w1-eeprom/w1-eeprom-uclass.c b/drivers/w1-eeprom/w1-eeprom-uclass.c index 3919aad3c8af8c96a54e9aa05c91906845b04fe5..70ba537243f81d48f6044b5a621988c265c6c6d4 100644 --- a/drivers/w1-eeprom/w1-eeprom-uclass.c +++ b/drivers/w1-eeprom/w1-eeprom-uclass.c @@ -12,6 +12,7 @@ #define LOG_CATEGORY UCLASS_W1_EEPROM +#include #include #include #include diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c index 9ebfc13c83aa57ed1e7041a8814f981b44e3e2c9..b96c1a00bf243d124ccdbbe47ec56db7fd1e968c 100644 --- a/drivers/w1/mxc_w1.c +++ b/drivers/w1/mxc_w1.c @@ -17,6 +17,7 @@ * Martin Fuzzey */ +#include #include #include #include diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c index 759f94e224e4e52f626b02cd49c3c56a4f0714e9..9346f810ce119402f5e872e77dce3d7f59971e60 100644 --- a/drivers/w1/w1-gpio.c +++ b/drivers/w1/w1-gpio.c @@ -7,6 +7,7 @@ * */ +#include #include #include #include diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c index 9637ed242573b78788f3ac34594a7b13bb350afd..a4247ecd62330e01ee4bc5d0db68ca21831fc968 100644 --- a/drivers/w1/w1-uclass.c +++ b/drivers/w1/w1-uclass.c @@ -14,6 +14,7 @@ #define LOG_CATEGORY UCLASS_W1 +#include #include #include #include diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 4b51178e1b8c8e6cb92287ad9ac9c27f4c839271..e09f5ac9e34ee3f60ba574f83e4cca4a2c1f4aee 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -5,6 +5,7 @@ * Marek Behún */ +#include #include #include #include diff --git a/drivers/watchdog/ast2600_wdt.c b/drivers/watchdog/ast2600_wdt.c index 190490f3692ba03e903701e2ed7812a097653e55..bc9842089bea031d996ff68823a8f4e32b069688 100644 --- a/drivers/watchdog/ast2600_wdt.c +++ b/drivers/watchdog/ast2600_wdt.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Aspeed Technology, Inc */ +#include #include #include #include diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index e61e13fdc49d71153f3c423693493b98c07b4664..f7b5a1adc1085459cc57ba9f440866c1d26be7b4 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -3,6 +3,7 @@ * Copyright 2017 Google, Inc */ +#include #include #include #include diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index c809a8936b8968c3322db4c86bc0571fbdfe3ae2..647ae325e9aecf04d6d1ccaf8f3a141911d7baee 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c index 6ebe901c2b82d1e871bf0a220d52228bd58aa5bf..677b1347ca7a093e308ead5aab34bcd17024d197 100644 --- a/drivers/watchdog/bcm6345_wdt.c +++ b/drivers/watchdog/bcm6345_wdt.c @@ -7,6 +7,7 @@ * Copyright (C) 2008 Florian Fainelli */ +#include #include #include #include diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index cb5a786c58914960c484a68556db0e82decb0d8f..743ab6487bcd115754a6bae9ca508ef43eaabab6 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -6,6 +6,7 @@ * Author(s): Shreenidhi Shedi */ +#include #include #include #include diff --git a/drivers/watchdog/cortina_wdt.c b/drivers/watchdog/cortina_wdt.c index 9f09ac0e15ff4c97d2652ffca518ff0612038de8..7ab9d7b2db97dd2ed060af1b14a6c805e44a2cbc 100644 --- a/drivers/watchdog/cortina_wdt.c +++ b/drivers/watchdog/cortina_wdt.c @@ -4,6 +4,7 @@ * */ +#include #include #include #include diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index bd9d7105366ba67cd136adc961c0e319a15b1567..b22e0ee06a4e5cf4386a4fc91feaf0a756963273 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include diff --git a/drivers/watchdog/ftwdt010_wdt.c b/drivers/watchdog/ftwdt010_wdt.c index 4769b967e52735238bddcb449eaec8957c6e1edb..1f5f301b125148236bf615368e4365581605914b 100644 --- a/drivers/watchdog/ftwdt010_wdt.c +++ b/drivers/watchdog/ftwdt010_wdt.c @@ -14,6 +14,7 @@ * 22/08/2022 Port to DM */ +#include #include #include #include diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index ea770217e5907c42536137dec4795fceed5665df..894158b304a73625652926efeefacfc2412be3c0 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -4,6 +4,7 @@ * Licensed under the GPL-2 or later. */ +#include #include #include #include diff --git a/drivers/watchdog/mcf_wdt.c b/drivers/watchdog/mcf_wdt.c index 5092a256af0ca00fed17e48f482b6c05b1b1034e..b36488bb5b96f8782d739e67eb2dc14c19fdaf60 100644 --- a/drivers/watchdog/mcf_wdt.c +++ b/drivers/watchdog/mcf_wdt.c @@ -6,7 +6,7 @@ * */ -#include +#include #include #include #include diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 036ff690d3fd49e5d5d48d70bb839877db47969b..f28636ca901550b76ea0df48e39c90b4e72dff42 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -3,6 +3,7 @@ * Copyright 2017 CS Systemes d'Information */ +#include #include #include #include diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 6308d9632a8115f83daf765ca860133c2fd340fa..f7d201b921a11a5c1c0fe6b402d01b10b1ac63f9 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -9,6 +9,7 @@ * Copyright (C) 2013 John Crispin */ +#include #include #include #include diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 706deb9da84626d8935a30d9cf6831289804d99d..368b36849c8d688d87b641d4d9d6c6cceb36aaaa 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -6,6 +6,7 @@ * Author: Ryder Lee */ +#include #include #include #include diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 5fd02ddf564f55cb247042721bc7f60dc790ff49..f0e57b4f7286bedf811c87cbb340232a69aed474 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -36,6 +36,7 @@ * Use the driver model and standard identifiers; handle bigger timeouts. */ +#include #include #include #include diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4562b2a37e3478da2f5b117f52a89051491653ff..127766df58af33dcd1e4ad2ffd6f3b5347e175bb 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -12,6 +12,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 99168d0cad03983e8c3b35b52b33bb11289cdb4d..8d93f19b984accce5b3b1a21160942a8addde50b 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -8,6 +8,7 @@ * Derived from linux/drivers/watchdog/rti_wdt.c */ +#include #include #include #include diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c index c244f15a8952ec0c6ac19d043ee17ef0dc8974ec..80524a00101b9167be3af6005b92181db83b5807 100644 --- a/drivers/watchdog/s5p_wdt.c +++ b/drivers/watchdog/s5p_wdt.c @@ -4,6 +4,7 @@ * Minkyu Kang */ +#include #include #include #include diff --git a/drivers/watchdog/sandbox_alarm-wdt.c b/drivers/watchdog/sandbox_alarm-wdt.c index 8dbbfc249e7c31b2e077e58eef9ed5eca4568cb4..71bb5d924ea59b8f63b3a61bd696b6920bb00e29 100644 --- a/drivers/watchdog/sandbox_alarm-wdt.c +++ b/drivers/watchdog/sandbox_alarm-wdt.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c index cd5eadbfd2132d2e93a3d2ccb1fcdb415f660775..535614f04d63c938901169d934c2a9ff2dfe08bb 100644 --- a/drivers/watchdog/sandbox_wdt.c +++ b/drivers/watchdog/sandbox_wdt.c @@ -3,6 +3,7 @@ * Copyright 2017 Google, Inc */ +#include #include #include #include diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 03585529bb636a763fcbd536646bbd453735d1bc..96d04665d52c1c0731c09f309d28cd5810bc6e89 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include diff --git a/drivers/watchdog/sl28cpld-wdt.c b/drivers/watchdog/sl28cpld-wdt.c index c5b4f8a9f665aefe5023773eb56987be7cbd9230..af5a6b1a28aca4c502cfde85b32cbed533886175 100644 --- a/drivers/watchdog/sl28cpld-wdt.c +++ b/drivers/watchdog/sl28cpld-wdt.c @@ -5,6 +5,7 @@ * Copyright (c) 2021 Michael Walle */ +#include #include #include #include diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index 10fe3e28232313a35eb357a1dfcb37a65f73657f..6d58fd3cfdab8a3e215d6c60967836da590029e1 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c index 97ab8cfe7ab133737c7318bc2d4a39c4e68e4713..7ebcd2552668e73222b9c060caed5ec8b4718742 100644 --- a/drivers/watchdog/stm32mp_wdt.c +++ b/drivers/watchdog/stm32mp_wdt.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_WDT +#include #include #include #include diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c index 8fbfac31b1e1d3dab4f6c3206e6fc4dd62f59b78..bdc65597dcff4aa4e46355494b638f1cf1fab277 100644 --- a/drivers/watchdog/tangier_wdt.c +++ b/drivers/watchdog/tangier_wdt.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017 Intel Corporation */ +#include #include #include #include diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 83f19dc0e86b332b43b47bd39efaedbd0f05fe24..0eea04ed2c6ed7ac0aef6a16b5863b84c5ce86c5 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 Freescale Semiconductor, Inc. */ +#include #include #include #include diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index c88312ec721887f464120e5b69bd6d25f29cd266..417e8d7eef95196db9e5218188f29b16c313a6dc 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -5,6 +5,7 @@ #define LOG_CATEGORY UCLASS_WDT +#include #include #include #include diff --git a/drivers/watchdog/xilinx_tb_wdt.c b/drivers/watchdog/xilinx_tb_wdt.c index 8a8e55370a0e4725f57f1a272cb211f34dc1f74e..b38c400016118630d4821a868c156a604d275858 100644 --- a/drivers/watchdog/xilinx_tb_wdt.c +++ b/drivers/watchdog/xilinx_tb_wdt.c @@ -8,6 +8,7 @@ * Copyright (c) 2011-2018 Xilinx Inc. */ +#include #include #include #include diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c index 41eff1a464505609bda2f7344ff4abd18bd5a653..963ab22fb452898507f2e13a3ba19847461983fa 100644 --- a/drivers/watchdog/xilinx_wwdt.c +++ b/drivers/watchdog/xilinx_wwdt.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include diff --git a/drivers/xen/events.c b/drivers/xen/events.c index fa8b13d2c61d6992aa9cc5efb2a71d75806c7e95..2ebe20dbf26e6886de768f5ec029d8db9b1a3d74 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c @@ -14,6 +14,7 @@ * * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ +#include #include #include diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c index 005694a5c626b902cbad71a73f8c6afd11b6333d..31e96e2939c079c15e0641fc09ca184625e4d995 100644 --- a/drivers/xen/gnttab.c +++ b/drivers/xen/gnttab.c @@ -14,6 +14,7 @@ * * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ +#include #include #include #include diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c index d28df823c684004bf3ee3d6ba0552a59357357bb..0b2311ba26756385e008a76d982534846cab212d 100644 --- a/drivers/xen/hypervisor.c +++ b/drivers/xen/hypervisor.c @@ -8,6 +8,7 @@ * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge * Copyright (c) 2020, EPAM Systems Inc. */ +#include #include #include #include diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c index 0e47ffb46a82be0584356d686d3703e65638f0f8..9fc51d203e5e3650ab216f36ac2593c6059a9559 100644 --- a/drivers/xen/pvblock.c +++ b/drivers/xen/pvblock.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_PVBLOCK #include +#include #include #include #include diff --git a/drivers/xen/xenbus.c b/drivers/xen/xenbus.c index 36de5255099781e5c45e8afafcb5e71f30dd2a7c..177d144723c1c7d4cfede3d2b5785ac1b58aa4d5 100644 --- a/drivers/xen/xenbus.c +++ b/drivers/xen/xenbus.c @@ -15,6 +15,7 @@ * [1] - http://xenbits.xen.org/gitweb/?p=mini-os.git;a=summary */ +#include #include #include diff --git a/env/Kconfig b/env/Kconfig index 9641abe371a0087ed8e3f5e2d12c8ad8e535c055..1f8e90af55e537577faf129fad000c654794120c 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -312,7 +312,7 @@ config ENV_IS_IN_NVRAM config ENV_IS_IN_ONENAND bool "Environment is in OneNAND" - depends on !CHAIN_OF_TRUST && CMD_ONENAND + depends on !CHAIN_OF_TRUST help Define this if you want to put your local device's environment in OneNAND. diff --git a/env/attr.c b/env/attr.c index fed5b212e2f93e5e6a55b034804b1aba42576f66..a958c714828315ad069b831a84992d152abe1a9f 100644 --- a/env/attr.c +++ b/env/attr.c @@ -4,13 +4,13 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ -#include #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */ #include +#include #include #else +#include #include -#include #endif #include diff --git a/env/callback.c b/env/callback.c index b7cbccd1175f7df8f2da78dc2186d1a5a7e88aa3..98ddba035ea74cf47ab68c31d02c366fb6418784 100644 --- a/env/callback.c +++ b/env/callback.c @@ -4,6 +4,7 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ +#include #include #include #include diff --git a/env/common.c b/env/common.c index d8c276dddfd9e2d0ae88d63ee7ec20d5ae406212..48a565107c1107d62ebe69e3242bc4e4c40a7587 100644 --- a/env/common.c +++ b/env/common.c @@ -7,6 +7,7 @@ * Andreas Heppel */ +#include #include #include #include diff --git a/env/eeprom.c b/env/eeprom.c index b290b1013e1c71906772446c9981c76443238e81..7ce7e9972b294c4a866fc020f21bfceb1ff22ae3 100644 --- a/env/eeprom.c +++ b/env/eeprom.c @@ -7,6 +7,7 @@ * Andreas Heppel */ +#include #include #include #include diff --git a/env/env.c b/env/env.c index bcc189e14db71bf178951205410b060ae9ff5da6..bae3f6482aea6a9abf41591d939ee2989c79a234 100644 --- a/env/env.c +++ b/env/env.c @@ -4,13 +4,13 @@ * Written by Simon Glass */ +#include #include #include #include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/env/ext4.c b/env/ext4.c index d92c844ea6c0d2b66387f15a72aab3a601f7a1d1..f21939186f015cd8e38c713343b75664d8effd93 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -18,6 +18,7 @@ * Manjunatha C Achar */ +#include #include #include diff --git a/env/fat.c b/env/fat.c index f3f8b7301eef6e494ba4bdcd5558f681cfe086e6..d87a47b10013370ab94603c2e600fbf15e6fc650 100644 --- a/env/fat.c +++ b/env/fat.c @@ -6,6 +6,7 @@ * Maximilian Schwerin */ +#include #include #include #include diff --git a/env/flags.c b/env/flags.c index 233fd460d84215224e1934e5c34085a4b50a58d8..e2866361dfe4f22b009a77b06f43fd2be9433dc0 100644 --- a/env/flags.c +++ b/env/flags.c @@ -8,9 +8,9 @@ #include #include -#include #ifdef USE_HOSTCC /* Eliminate "ANSI does not permit..." warnings */ #include +#include #include "fw_env_private.h" #include "fw_env.h" #include @@ -18,7 +18,7 @@ #define env_get fw_getenv #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #else -#include +#include #include #endif diff --git a/env/flash.c b/env/flash.c index 1bd6e7003d6ec86fd21e79e78a7a6143ba35f226..1e75f8c004ee79d0bbac218c0a6284f0a6b89c85 100644 --- a/env/flash.c +++ b/env/flash.c @@ -9,6 +9,7 @@ /* #define DEBUG */ +#include #include #include #include diff --git a/env/mmc.c b/env/mmc.c index 776df0786be55b43d917b7c69a91934a32e6daf5..7afb733e890f953b858f763d5ee84665e36a7675 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -5,6 +5,7 @@ /* #define DEBUG */ +#include #include #include diff --git a/env/nand.c b/env/nand.c index fef5697ec39d13b3dad263c7b03bde2302d477d3..df300b13179312babc6ee3c47e2cba1d165c30fb 100644 --- a/env/nand.c +++ b/env/nand.c @@ -13,6 +13,7 @@ * Andreas Heppel */ +#include #include #include #include diff --git a/env/nowhere.c b/env/nowhere.c index 326f27db2e9c5ddb64de637cbfb00ef1771942c5..9ebc357dbd785e7b9390e315f0d21319a7b0d92d 100644 --- a/env/nowhere.c +++ b/env/nowhere.c @@ -7,6 +7,7 @@ * Andreas Heppel */ +#include #include #include #include diff --git a/env/nvram.c b/env/nvram.c index d49cd0f337a05d5700f20e6de54971f29f799683..229c34f5367c636cb295526e1e5069f9c2746868 100644 --- a/env/nvram.c +++ b/env/nvram.c @@ -7,6 +7,7 @@ * Andreas Heppel */ +#include #include #include #include diff --git a/env/onenand.c b/env/onenand.c index 8c349ef5ce6cc0d92425bf97628c52c4962e0dc7..1faa2cb62a34ac99d2dd4ca048e5e2083b879d20 100644 --- a/env/onenand.c +++ b/env/onenand.c @@ -7,6 +7,7 @@ * Kyungmin Park */ +#include #include #include #include diff --git a/env/remote.c b/env/remote.c index 0cc383c23602e3fdf353a47c77bf1ee752988da6..166bebf52b5b577c7b8f2310b610e886199b4557 100644 --- a/env/remote.c +++ b/env/remote.c @@ -5,10 +5,10 @@ /* #define DEBUG */ +#include #include #include #include -#include #include #include diff --git a/env/sf.c b/env/sf.c index c747e175e31bd908b996060d72db14214ac370ac..8f5c03b00d338108b18454e8cbf82dcbc509a0cf 100644 --- a/env/sf.c +++ b/env/sf.c @@ -8,6 +8,7 @@ * * (C) Copyright 2008 Atmel Corporation */ +#include #include #include #include diff --git a/env/ubi.c b/env/ubi.c index 0c3e93c2bf2d6397c1a7fac4c7672c4f2b548c2d..445d34fedb893e9b447cb5c23b01567e599ee827 100644 --- a/env/ubi.c +++ b/env/ubi.c @@ -4,6 +4,7 @@ * Joe Hershberger */ +#include #include #include diff --git a/examples/api/demo.c b/examples/api/demo.c index 677d13b307a13e7701632abcbb5f0f926528b410..d586174ce8c92a820f45f6153e9dcc0b879e93bf 100644 --- a/examples/api/demo.c +++ b/examples/api/demo.c @@ -5,7 +5,7 @@ * Written by: Rafal Jaworowski */ -#include +#include #include #include #include diff --git a/examples/api/glue.c b/examples/api/glue.c index 08c21a8cb9c1da23eafeb02d93953a532e84ed00..075d307ae2611090fa4d0cb5ae71c019db4b5f55 100644 --- a/examples/api/glue.c +++ b/examples/api/glue.c @@ -3,6 +3,7 @@ * (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski */ +#include #include #include #include diff --git a/examples/api/libgenwrap.c b/examples/api/libgenwrap.c index bfd88e100d6ed7d5029dfa42028a5f3e4b3f1938..3aa222866ff50bbf5f6f37866348e282b30659af 100644 --- a/examples/api/libgenwrap.c +++ b/examples/api/libgenwrap.c @@ -9,6 +9,7 @@ * existing code e.g. operations on strings and similar. */ +#include #include #include #include diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c index ed0d7aeaadca98709c82d9d1cfc3f62b3caba593..dcb25da94986dfb501b53d0c018658293276356d 100644 --- a/examples/standalone/atmel_df_pow2.c +++ b/examples/standalone/atmel_df_pow2.c @@ -6,6 +6,7 @@ * Licensed under the 2-clause BSD. */ +#include #include #include #include diff --git a/examples/standalone/sched.c b/examples/standalone/sched.c index d507163f6f3447369e2428728c61c7797ce1a09c..1c529607132291effc308c24a55061c409181194 100644 --- a/examples/standalone/sched.c +++ b/examples/standalone/sched.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include /* diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 04e8acb8abe9e8554f4bac5b0b4a0538f0751845..65115570e8eb537892a6e4dfe375b03325f42ad1 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -1,3 +1,4 @@ +#include #include #include diff --git a/fs/btrfs/dev.c b/fs/btrfs/dev.c index e27a032c9f69252d0fbafa551e252641e9d474dc..cb3b9713a5f4d1b7c209e7b75d740f7296ac1daa 100644 --- a/fs/btrfs/dev.c +++ b/fs/btrfs/dev.c @@ -5,6 +5,7 @@ * 2017 Marek Behún, CZ.NIC, kabel@kernel.org */ +#include #include #include #include diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index e5bfaf461c2bcb6075f7dd9b43a3ba2f0e045462..7eaa7e949604f2b3f0e8c4a750f70974095b1e0f 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 8ec545eded7b275b7d2252f30d2daa7971b58faf..7d4095d9ca88d9933dd61a216bd91e875956f0d1 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include -#include +#include #include #include "ctree.h" #include "disk-io.h" diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c index ad5583233bb1163a60bfaa7bc6f7c1e11fdc8038..714f4baafc9e89434991ec2aec8dbfb0cbd67dd5 100644 --- a/fs/cbfs/cbfs.c +++ b/fs/cbfs/cbfs.c @@ -3,10 +3,10 @@ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. */ +#include #include #include #include -#include #include /* Offset of master header from the start of a coreboot ROM */ diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index 22148ff8fe2736882b48db236e970da7fafca76b..abb2de34eb05d4c2218d34002bbc6394a9aade86 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -24,7 +24,7 @@ * The actual compression is based on zlib, see the other files. */ -#include +#include #include #include #include diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c index 2141edf22e4ad3f22e685449c26258bd63941226..0d071b69f4cc560d439dec76807a7286b1b24698 100644 --- a/fs/cramfs/uncompress.c +++ b/fs/cramfs/uncompress.c @@ -20,7 +20,7 @@ * then is used by multiple filesystems. */ -#include +#include #include #include #include diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c index 3fd8980b1d69b21afd89b1ac325afe0b8f5fd553..168443de1ff7b36b68287048bb555f5355c2af0d 100644 --- a/fs/ext4/dev.c +++ b/fs/ext4/dev.c @@ -22,6 +22,7 @@ * fs/ext2/dev.c file in uboot. */ +#include #include #include #include diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 857c15d878e4b414607082bd7767c3aa32a8277d..2ff0dca2495e2b13192ad3ccf25978d3af1fdea7 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -18,6 +18,7 @@ * ext4write : Based on generic ext4 protocol. */ +#include #include #include #include diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index 02c4ac2cb931b866d690461da1dcbb6054b143f4..e80f797c8dc97a5600b4d3a040730bd664d8860a 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -13,6 +13,7 @@ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved */ +#include #include #include #include diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index 38da3923c477cf2c9811e874c795bf0c89532117..d057f6b5a794c01eb0d93d12cbfd79ecf05d8264 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -21,6 +21,7 @@ */ +#include #include #include #include diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index da59cb008fce46486384986430906113f7d500e5..33e200ffa3c5e1c7c5bc50aaeff1b8ec6a326d29 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -20,6 +20,7 @@ * ext4write : Based on generic ext4 protocol. */ +#include #include #include #include diff --git a/fs/fat/fat.c b/fs/fat/fat.c index e2570e81676875d54911ceec27a8d1bedc1c32d5..2dd9d4e72dcc679587ec6270855b068a06dc9174 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -10,6 +10,7 @@ #define LOG_CATEGORY LOGC_FS +#include #include #include #include diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index ea877ee9171bde4e6cbef505678ba5afe4c36435..c8e0fbf1a3b3d0b8e5458d10c5b2aa7af0a60681 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_FS +#include #include #include #include diff --git a/fs/fs.c b/fs/fs.c index bed1f7242f417fa6c8c6d7613d847f7fed00c66e..acf465bdd807fc079d7363c6d9f8936ef4c606a3 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -20,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/fs/fs_internal.c b/fs/fs_internal.c index 51c1719361b1f96e8d83a5da7a19d46dc2d466b9..111f91b355d1ff974d0953944464fc07c48bbe62 100644 --- a/fs/fs_internal.c +++ b/fs/fs_internal.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY LOGC_CORE +#include #include #include #include diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c index e1e3c15e75e1d229bb4fd944ab3358c229f7f842..d306b6dc4cfe8961c8d8f228087e04b2333904f5 100644 --- a/fs/jffs2/compr_zlib.c +++ b/fs/jffs2/compr_zlib.c @@ -35,6 +35,8 @@ * */ +#include +#include #include #include diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 5b7d7f4ae881cee34d97e000b8af651446e2bd0b..49ba82ef959690597dc31160eca02b0a4cd0d1af 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -111,6 +111,7 @@ */ +#include #include #include #include diff --git a/fs/jffs2/mergesort.c b/fs/jffs2/mergesort.c index 495937d792db0b28db4b084e8e04592e34324a4d..fca77aa651149fc80da4cd2405308f3f633134c6 100644 --- a/fs/jffs2/mergesort.c +++ b/fs/jffs2/mergesort.c @@ -7,6 +7,7 @@ * http://www.chiark.greenend.org.uk/~sgtatham/algorithms/listsort.html */ +#include #include "jffs2_private.h" int sort_list(struct b_list *list) diff --git a/fs/sandbox/host_bootdev.c b/fs/sandbox/host_bootdev.c index 3f74972a9f81a88ecc7efcf208ef2134840ce46f..3ef53627608af1f2429e86ee03eb16264d20d397 100644 --- a/fs/sandbox/host_bootdev.c +++ b/fs/sandbox/host_bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index 773b583fa43eebbd730c6e3f1cf92ec010f7b162..4ae41d5b4db19b0bdf61ec42698a2eb0af503522 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -3,7 +3,7 @@ * Copyright (c) 2012, Google Inc. */ -#include +#include #include #include #include diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c index 77e39ca407e4d240a1fd573497c5b6b908816454..3592338a6865ec06d64a000b89207c53a7e71dfd 100644 --- a/fs/semihostingfs.c +++ b/fs/semihostingfs.c @@ -4,7 +4,7 @@ * Copyright (c) 2012, Google Inc. */ -#include +#include #include #include #include diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 788f88f0495278d36ac112397a70cf6c0d721a2c..3e7160352e6cccf24860773bf22afed4fbd88040 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -29,6 +29,7 @@ #include #else +#include #include #include #include diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 75de01e95f7cb8b4cdb813b31124e3f401c11e96..a509584e5d714634a4df10ad71e0affd36ca1d26 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -11,6 +11,7 @@ * Adrian Hunter */ +#include #include #include #include diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c index 0eec22bc4a543d3facd2cb7cf9060c00f28613c0..50fed2d4b150f0db6ab65bc788d3d50782b27e60 100644 --- a/fs/yaffs2/yaffs_mtdif.c +++ b/fs/yaffs2/yaffs_mtdif.c @@ -12,6 +12,7 @@ */ /* XXX U-BOOT XXX */ +#include #include "yportenv.h" diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c index 2bf171f99f132345cc1a29bee73370e8721638a8..81a4d964f3e92777ebba6fb2f9213ec74e51f34f 100644 --- a/fs/yaffs2/yaffs_mtdif2.c +++ b/fs/yaffs2/yaffs_mtdif2.c @@ -14,6 +14,7 @@ /* mtd interface for YAFFS2 */ /* XXX U-BOOT XXX */ +#include #include #include diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c index deddbaac51eba4d46d1a251ae13a24914ce8113b..0a920561149a45ee0c8a8630ee424beea2a18a3c 100644 --- a/fs/yaffs2/yaffs_uboot_glue.c +++ b/fs/yaffs2/yaffs_uboot_glue.c @@ -19,6 +19,7 @@ * This version now uses the ydevconfig mechanism to set up partitions. */ +#include #include #include #include diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c index 722c6a86176c3618e0e310bda6f5a3f5adb47228..fcd9893b3ac2fb8798eff06c7d316b3496d9eb70 100644 --- a/fs/zfs/dev.c +++ b/fs/zfs/dev.c @@ -8,6 +8,7 @@ */ +#include #include #include #include diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 9906d553fa61df9aad7056f870d8546a0ccfbfb8..113b428a93819ef5d2edc73cb8d17cc064430789 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -10,6 +10,7 @@ * Copyright 2004 Sun Microsystems, Inc. */ +#include #include #include #include diff --git a/fs/zfs/zfs_fletcher.c b/fs/zfs/zfs_fletcher.c index b06c335626a466efe66981161dcc5912310579a4..008a303ec7962a323ecfe66b4d17cff31d508935 100644 --- a/fs/zfs/zfs_fletcher.c +++ b/fs/zfs/zfs_fletcher.c @@ -8,6 +8,7 @@ * Use is subject to license terms. */ +#include #include #include #include diff --git a/fs/zfs/zfs_lzjb.c b/fs/zfs/zfs_lzjb.c index e79c5b4278fd285a6f85d497e874fb8205f55a15..b42d4980129f86ada0fca1274416123ce2972bfe 100644 --- a/fs/zfs/zfs_lzjb.c +++ b/fs/zfs/zfs_lzjb.c @@ -8,6 +8,7 @@ * Use is subject to license terms. */ +#include #include #include #include diff --git a/fs/zfs/zfs_sha256.c b/fs/zfs/zfs_sha256.c index 602d75254ff962a7d84bdf0e09ef25187c72b5a8..cb5b1c06834d0f3c33712a54eb32c80a3ced8a62 100644 --- a/fs/zfs/zfs_sha256.c +++ b/fs/zfs/zfs_sha256.c @@ -8,6 +8,7 @@ * Use is subject to license terms. */ +#include #include #include #include diff --git a/include/acpi/acpi_s3.h b/include/acpi/acpi_s3.h index f7bea94185523c3249bd516686f14fbba47fabe1..d3f271f948ea8f01141974f96ea661b1b5db160c 100644 --- a/include/acpi/acpi_s3.h +++ b/include/acpi/acpi_s3.h @@ -37,9 +37,6 @@ #ifndef __ASSEMBLY__ -#include -#include - extern char __wakeup[]; extern int __wakeup_size; diff --git a/include/adc.h b/include/adc.h index 15e4cdb7dce761d6151c83fd1259077e6c201f27..0d1a666908f28fa83f25bc4412ce6144b4a9a72d 100644 --- a/include/adc.h +++ b/include/adc.h @@ -7,8 +7,6 @@ #ifndef _ADC_H_ #define _ADC_H_ -#include - /* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */ #define ADC_CHANNEL(x) (1 << x) diff --git a/include/android_ab.h b/include/android_ab.h index dbf20343da62447a237ec845e216517d34455ad3..1fee7582b90adc91e4b39b9b3720806d1cc277db 100644 --- a/include/android_ab.h +++ b/include/android_ab.h @@ -6,8 +6,6 @@ #ifndef __ANDROID_AB_H #define __ANDROID_AB_H -#include - struct blk_desc; struct disk_partition; diff --git a/include/api_public.h b/include/api_public.h index e89572c00a4b02607110a41fc6766c4802680291..5a4465ea893d97aadafca12cf05f6a4cfe4800f8 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -8,8 +8,6 @@ #ifndef _API_PUBLIC_H_ #define _API_PUBLIC_H_ -#include - #define API_EINVAL 1 /* invalid argument(s) */ #define API_ENODEV 2 /* no device */ #define API_ENOMEM 3 /* no memory */ diff --git a/include/atf_common.h b/include/atf_common.h index 5ae4509025232ffda704ab05161df80c18b3843a..d69892fac6cbc142c4830a45c55e69ff5a5ff2be 100644 --- a/include/atf_common.h +++ b/include/atf_common.h @@ -74,8 +74,6 @@ #ifndef __ASSEMBLY__ -#include - /******************************************************************************* * Structure used for telling the next BL how much of a particular type of * memory is available for its use and how much is already used. diff --git a/include/audio_codec.h b/include/audio_codec.h index a87b76c6f9ed6ca73cb8b42c2b54b5e12135f367..a81a315157651d5413f83ad6e5a9399d64271f47 100644 --- a/include/audio_codec.h +++ b/include/audio_codec.h @@ -7,8 +7,6 @@ #ifndef __AUDIO_CODEC_H__ #define __AUDIO_CODEC_H__ -#include - struct udevice; /* diff --git a/include/autoboot.h b/include/autoboot.h index c68bd79f8dca9e9b890358e578f5c2131ed324df..eb204995d079b7b893df1bb21f880426bbb5eb6b 100644 --- a/include/autoboot.h +++ b/include/autoboot.h @@ -12,7 +12,6 @@ #define __AUTOBOOT_H #include -#include #ifdef CONFIG_SANDBOX diff --git a/include/axi.h b/include/axi.h index 133a06ee27198ec1897fe832796751d25a88ff95..59fb0b2e4584c24816f21f464cea4d14cde0071f 100644 --- a/include/axi.h +++ b/include/axi.h @@ -7,8 +7,6 @@ #ifndef _AXI_H_ #define _AXI_H_ -#include - struct udevice; /** diff --git a/include/bmp_layout.h b/include/bmp_layout.h index eabbd25a3309c3da67277bce70770b64358b4460..a5c9498dc9fba6b3e167321b77f50c8b60009e72 100644 --- a/include/bmp_layout.h +++ b/include/bmp_layout.h @@ -10,8 +10,6 @@ #ifndef _BMP_H_ #define _BMP_H_ -#include - struct __packed bmp_color_table_entry { __u8 blue; __u8 green; diff --git a/include/bootmeth.h b/include/bootmeth.h index cd9517321c0a9ea2e1b5bf82d806c1552378d47a..0fc36104ece0ebcbe899a93e8df7ac1f2cd921a7 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -7,8 +7,6 @@ #ifndef __bootmeth_h #define __bootmeth_h -#include - struct blk_desc; struct bootflow; struct bootflow_iter; diff --git a/include/bootstd.h b/include/bootstd.h index ac756e98d84a892de26eb27b50dba61c4c65488c..99ce7b64e7c538968cae1c71d1771236bc371e90 100644 --- a/include/bootstd.h +++ b/include/bootstd.h @@ -10,8 +10,6 @@ #define __bootstd_h #include -#include -#include struct udevice; diff --git a/include/cedit.h b/include/cedit.h index a31b42452477aeca6735f5c8e51d93a0af48eb8c..f43cafa5aa240f732eeb96abacdefca91ff37151 100644 --- a/include/cedit.h +++ b/include/cedit.h @@ -7,15 +7,12 @@ #ifndef __CEDIT_H #define __CEDIT_H -#include #include -#include struct abuf; struct expo; struct scene; struct video_priv; -struct udevice; enum { /* size increment for writing FDT */ diff --git a/include/common.h b/include/common.h new file mode 100644 index 0000000000000000000000000000000000000000..a79c2bb49931578a3ffb2e34845e02d93ac9d14b --- /dev/null +++ b/include/common.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Common header file for U-Boot + * + * This file still includes quite a few headers that should be included + * individually as needed. Patches to remove things are welcome. + * + * (C) Copyright 2000-2009 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +#include +#include +#include +#include +#include +#include +#include +#include +#include /* boot information for Linux kernel */ +#include +#endif /* __ASSEMBLY__ */ + +/* Pull in stuff for the build system */ +#ifdef DO_DEPS_ONLY +# include +#endif + +#endif /* __COMMON_H_ */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index e6dba7071950c769e195a5d7a7a2581b01efcf35..bf2bc2d45c09994409bd6fe52b236d38c76d978d 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -14,6 +14,9 @@ #define CFG_SYS_INIT_SP_OFFSET 0x800000 +/* MMC */ +#define MMC_SUPPORTS_TUNING + /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CFG_SYS_NS16550_CLK 50000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 6f42cd32d80fbfc4e8923826d448da40e7f49b5c..fca234a1dc71a85f4982a49db4f1ab53e30b9ed7 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -11,6 +11,9 @@ #include +/* MMC */ +#define MMC_SUPPORTS_TUNING + /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index f415dffddbea0c9a46ca5267920adde7373b47e4..c4db38562d831ddcd7a5328b2ea2083f840282f9 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -19,4 +19,9 @@ "loadaddr=20080000\0" \ "ethrotate=yes\0" +#if defined(CONFIG_MMC_OCTEONTX) +#define MMC_SUPPORTS_TUNING +/** EMMC specific defines */ +#endif + #endif /* __OCTEONTX2_COMMON_H__ */ diff --git a/include/ddr_spd.h b/include/ddr_spd.h index c4d199fd7e14c86b8c66350299821f9b42b5c89a..fe163da43e562b06c19d5ba13a30faf96e0b9423 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -6,8 +6,6 @@ #ifndef _DDR_SPD_H_ #define _DDR_SPD_H_ -#include - /* * Format from "JEDEC Standard No. 21-C, * Appendix D: Rev 1.0: SPD's for DDR SDRAM diff --git a/include/display.h b/include/display.h index e8d8aaa15fbcbf0b2bcaeec0d612ad66346d28c3..3d01217644118a58786c96962dc761ffbd786910 100644 --- a/include/display.h +++ b/include/display.h @@ -6,8 +6,6 @@ #ifndef _DISPLAY_H #define _DISPLAY_H -#include - struct udevice; struct display_timing; diff --git a/include/dm/of.h b/include/dm/of.h index b7404c139d1912c87b4c06a332ec64e288b0b194..b1c934f610d35233f21039d12d580313f3396a18 100644 --- a/include/dm/of.h +++ b/include/dm/of.h @@ -7,6 +7,7 @@ #ifndef _DM_OF_H #define _DM_OF_H +#include #include /* integer value within a device tree property which references another node */ diff --git a/include/dm/test.h b/include/dm/test.h index 02737411a164051d76220cd697288dd401096705..b5937509212b54567c1a8428c3d80a9ad3ee73ae 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -6,8 +6,6 @@ #ifndef __DM_TEST_H #define __DM_TEST_H -#include - struct udevice; /** diff --git a/include/dt-bindings/clock/adi-sc5xx-clock.h b/include/dt-bindings/clock/adi-sc5xx-clock.h deleted file mode 100644 index 4a5373d11412b24d8b13f371a1465454e002ffd8..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/adi-sc5xx-clock.h +++ /dev/null @@ -1,271 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * (C) Copyright 2022 - Analog Devices, Inc. - * - * Written and/or maintained by Timesys Corporation - * - * Contact: Nathan Barrett-Morrison - * Contact: Greg Malysa - * - */ - -#ifndef DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H -#define DT_BINDINGS_CLOCK_ADI_SC5XX_CLOCK_H - -//ADSP-SC594 -#define ADSP_SC594_CLK_DUMMY 0 -#define ADSP_SC594_CLK_SYS_CLKIN0 1 -#define ADSP_SC594_CLK_SYS_CLKIN1 2 -#define ADSP_SC594_CLK_CGU1_IN 3 -#define ADSP_SC594_CLK_CGU0_PLL_IN 4 -#define ADSP_SC594_CLK_CGU1_PLL_IN 5 -#define ADSP_SC594_CLK_CGU0_VCO_OUT 6 -#define ADSP_SC594_CLK_CGU1_VCO_OUT 7 -#define ADSP_SC594_CLK_CGU0_PLLCLK 8 -#define ADSP_SC594_CLK_CGU1_PLLCLK 9 -#define ADSP_SC594_CLK_CGU0_CDIV 10 -#define ADSP_SC594_CLK_CGU0_SYSCLK 11 -#define ADSP_SC594_CLK_CGU0_DDIV 12 -#define ADSP_SC594_CLK_CGU0_ODIV 13 -#define ADSP_SC594_CLK_CGU0_S0SELDIV 14 -#define ADSP_SC594_CLK_CGU0_S1SELDIV 15 -#define ADSP_SC594_CLK_CGU0_S1SELEXDIV 16 -#define ADSP_SC594_CLK_CGU0_S1SEL 17 -#define ADSP_SC594_CLK_CGU1_CDIV 18 -#define ADSP_SC594_CLK_CGU1_SYSCLK 19 -#define ADSP_SC594_CLK_CGU1_DDIV 20 -#define ADSP_SC594_CLK_CGU1_ODIV 21 -#define ADSP_SC594_CLK_CGU1_S0SELDIV 22 -#define ADSP_SC594_CLK_CGU1_S1SELDIV 23 -#define ADSP_SC594_CLK_CGU1_S1SELEXDIV 24 -#define ADSP_SC594_CLK_CGU1_S1SEL 25 -#define ADSP_SC594_CLK_CGU0_CCLK0 26 -#define ADSP_SC594_CLK_CGU0_CCLK1 27 -#define ADSP_SC594_CLK_CGU0_OCLK 28 -#define ADSP_SC594_CLK_CGU0_DCLK 29 -#define ADSP_SC594_CLK_CGU0_SCLK1 30 -#define ADSP_SC594_CLK_CGU0_SCLK0 31 -#define ADSP_SC594_CLK_CGU1_CCLK0 32 -#define ADSP_SC594_CLK_CGU1_CCLK1 33 -#define ADSP_SC594_CLK_CGU1_OCLK 34 -#define ADSP_SC594_CLK_CGU1_DCLK 35 -#define ADSP_SC594_CLK_CGU1_SCLK1 36 -#define ADSP_SC594_CLK_CGU1_SCLK0 37 -#define ADSP_SC594_CLK_SHARC0_SEL 38 -#define ADSP_SC594_CLK_SHARC1_SEL 39 -#define ADSP_SC594_CLK_ARM_SEL 40 -#define ADSP_SC594_CLK_CDU_DDR_SEL 41 -#define ADSP_SC594_CLK_CAN_SEL 42 -#define ADSP_SC594_CLK_SPDIF_SEL 43 -#define ADSP_SC594_CLK_RESERVED_SEL 44 -#define ADSP_SC594_CLK_GIGE_SEL 45 -#define ADSP_SC594_CLK_LP_SEL 46 -#define ADSP_SC594_CLK_LPDDR_SEL 47 -#define ADSP_SC594_CLK_OSPI_SEL 48 -#define ADSP_SC594_CLK_TRACE_SEL 49 -#define ADSP_SC594_CLK_SHARC0 50 -#define ADSP_SC594_CLK_SHARC1 51 -#define ADSP_SC594_CLK_ARM 52 -#define ADSP_SC594_CLK_CDU_DDR 53 -#define ADSP_SC594_CLK_CAN 54 -#define ADSP_SC594_CLK_SPDIF 55 -#define ADSP_SC594_CLK_SPI 56 -#define ADSP_SC594_CLK_GIGE 57 -#define ADSP_SC594_CLK_LP 58 -#define ADSP_SC594_CLK_LPDDR 59 -#define ADSP_SC594_CLK_OSPI 60 -#define ADSP_SC594_CLK_TRACE 61 -#define ADSP_SC594_CLK_END 62 - -//ADSP-SC598 -#define ADSP_SC598_CLK_DUMMY 0 -#define ADSP_SC598_CLK_SYS_CLKIN0 1 -#define ADSP_SC598_CLK_SYS_CLKIN1 2 -#define ADSP_SC598_CLK_CGU0_PLL_IN 3 -#define ADSP_SC598_CLK_CGU0_VCO_OUT 4 -#define ADSP_SC598_CLK_CGU0_PLLCLK 5 -#define ADSP_SC598_CLK_CGU1_IN 6 -#define ADSP_SC598_CLK_CGU1_PLL_IN 7 -#define ADSP_SC598_CLK_CGU1_VCO_OUT 8 -#define ADSP_SC598_CLK_CGU1_PLLCLK 9 -#define ADSP_SC598_CLK_CGU0_CDIV 10 -#define ADSP_SC598_CLK_CGU0_SYSCLK 11 -#define ADSP_SC598_CLK_CGU0_DDIV 12 -#define ADSP_SC598_CLK_CGU0_ODIV 13 -#define ADSP_SC598_CLK_CGU0_S0SELDIV 14 -#define ADSP_SC598_CLK_CGU0_S1SELDIV 15 -#define ADSP_SC598_CLK_CGU0_S1SELEXDIV 16 -#define ADSP_SC598_CLK_CGU0_S1SEL 17 -#define ADSP_SC598_CLK_CGU1_CDIV 18 -#define ADSP_SC598_CLK_CGU1_SYSCLK 19 -#define ADSP_SC598_CLK_CGU1_DDIV 20 -#define ADSP_SC598_CLK_CGU1_ODIV 21 -#define ADSP_SC598_CLK_CGU1_S0SELDIV 22 -#define ADSP_SC598_CLK_CGU1_S1SELDIV 23 -#define ADSP_SC598_CLK_CGU1_S0SELEXDIV 24 -#define ADSP_SC598_CLK_CGU1_S1SELEXDIV 25 -#define ADSP_SC598_CLK_CGU1_S0SEL 26 -#define ADSP_SC598_CLK_CGU1_S1SEL 27 -#define ADSP_SC598_CLK_CGU0_CCLK2 28 -#define ADSP_SC598_CLK_CGU0_CCLK0 29 -#define ADSP_SC598_CLK_CGU0_OCLK 30 -#define ADSP_SC598_CLK_CGU0_DCLK 31 -#define ADSP_SC598_CLK_CGU0_SCLK1 32 -#define ADSP_SC598_CLK_CGU0_SCLK0 33 -#define ADSP_SC598_CLK_CGU1_CCLK0 34 -#define ADSP_SC598_CLK_CGU1_OCLK 35 -#define ADSP_SC598_CLK_CGU1_DCLK 36 -#define ADSP_SC598_CLK_CGU1_SCLK1 37 -#define ADSP_SC598_CLK_CGU1_SCLK0 38 -#define ADSP_SC598_CLK_CGU1_CCLK2 39 -#define ADSP_SC598_CLK_DCLK0_HALF 40 -#define ADSP_SC598_CLK_DCLK1_HALF 41 -#define ADSP_SC598_CLK_CGU1_SCLK1_HALF 42 -#define ADSP_SC598_CLK_SHARC0_SEL 43 -#define ADSP_SC598_CLK_SHARC1_SEL 44 -#define ADSP_SC598_CLK_ARM_SEL 45 -#define ADSP_SC598_CLK_CDU_DDR_SEL 46 -#define ADSP_SC598_CLK_CAN_SEL 47 -#define ADSP_SC598_CLK_SPDIF_SEL 48 -#define ADSP_SC598_CLK_SPI_SEL 49 -#define ADSP_SC598_CLK_GIGE_SEL 50 -#define ADSP_SC598_CLK_LP_SEL 51 -#define ADSP_SC598_CLK_LP_DDR_SEL 52 -#define ADSP_SC598_CLK_OSPI_REFCLK_SEL 53 -#define ADSP_SC598_CLK_TRACE_SEL 54 -#define ADSP_SC598_CLK_EMMC_SEL 55 -#define ADSP_SC598_CLK_EMMC_TIMER_QMC_SEL 56 -#define ADSP_SC598_CLK_SHARC0 57 -#define ADSP_SC598_CLK_SHARC1 58 -#define ADSP_SC598_CLK_ARM 59 -#define ADSP_SC598_CLK_CDU_DDR 60 -#define ADSP_SC598_CLK_CAN 61 -#define ADSP_SC598_CLK_SPDIF 62 -#define ADSP_SC598_CLK_SPI 63 -#define ADSP_SC598_CLK_GIGE 64 -#define ADSP_SC598_CLK_LP 65 -#define ADSP_SC598_CLK_LP_DDR 66 -#define ADSP_SC598_CLK_OSPI_REFCLK 67 -#define ADSP_SC598_CLK_TRACE 68 -#define ADSP_SC598_CLK_EMMC 69 -#define ADSP_SC598_CLK_EMMC_TIMER_QMC 70 -#define ADSP_SC598_CLK_3PLL_PLL_IN 71 -#define ADSP_SC598_CLK_3PLL_VCO_OUT 72 -#define ADSP_SC598_CLK_3PLL_PLLCLK 73 -#define ADSP_SC598_CLK_3PLL_DDIV 74 -#define ADSP_SC598_CLK_DDR 75 -#define ADSP_SC598_CLK_END 76 - -//ADSP-SC58X -#define ADSP_SC58X_CLK_DUMMY 0 -#define ADSP_SC58X_CLK_SYS_CLKIN0 1 -#define ADSP_SC58X_CLK_SYS_CLKIN1 2 -#define ADSP_SC58X_CLK_CGU0_PLL_IN 3 -#define ADSP_SC58X_CLK_CGU0_VCO_OUT 4 -#define ADSP_SC58X_CLK_CGU0_PLLCLK 5 -#define ADSP_SC58X_CLK_CGU1_IN 6 -#define ADSP_SC58X_CLK_CGU1_PLL_IN 7 -#define ADSP_SC58X_CLK_CGU1_VCO_OUT 8 -#define ADSP_SC58X_CLK_CGU1_PLLCLK 9 -#define ADSP_SC58X_CLK_CGU0_CDIV 10 -#define ADSP_SC58X_CLK_CGU0_SYSCLK 11 -#define ADSP_SC58X_CLK_CGU0_DDIV 12 -#define ADSP_SC58X_CLK_CGU0_ODIV 13 -#define ADSP_SC58X_CLK_CGU0_S0SELDIV 14 -#define ADSP_SC58X_CLK_CGU0_S1SELDIV 15 -#define ADSP_SC58X_CLK_CGU1_CDIV 16 -#define ADSP_SC58X_CLK_CGU1_SYSCLK 17 -#define ADSP_SC58X_CLK_CGU1_DDIV 18 -#define ADSP_SC58X_CLK_CGU1_ODIV 19 -#define ADSP_SC58X_CLK_CGU1_S0SELDIV 20 -#define ADSP_SC58X_CLK_CGU1_S1SELDIV 21 -#define ADSP_SC58X_CLK_CGU0_CCLK0 22 -#define ADSP_SC58X_CLK_CGU0_CCLK1 23 -#define ADSP_SC58X_CLK_CGU0_OCLK 24 -#define ADSP_SC58X_CLK_CGU0_DCLK 25 -#define ADSP_SC58X_CLK_CGU0_SCLK1 26 -#define ADSP_SC58X_CLK_CGU0_SCLK0 27 -#define ADSP_SC58X_CLK_CGU1_CCLK0 28 -#define ADSP_SC58X_CLK_CGU1_CCLK1 29 -#define ADSP_SC58X_CLK_CGU1_OCLK 30 -#define ADSP_SC58X_CLK_CGU1_DCLK 31 -#define ADSP_SC58X_CLK_CGU1_SCLK1 32 -#define ADSP_SC58X_CLK_CGU1_SCLK0 33 -#define ADSP_SC58X_CLK_OCLK0_HALF 34 -#define ADSP_SC58X_CLK_CCLK1_1_HALF 35 -#define ADSP_SC58X_CLK_SHARC0_SEL 36 -#define ADSP_SC58X_CLK_SHARC1_SEL 37 -#define ADSP_SC58X_CLK_ARM_SEL 38 -#define ADSP_SC58X_CLK_CDU_DDR_SEL 39 -#define ADSP_SC58X_CLK_CAN_SEL 40 -#define ADSP_SC58X_CLK_SPDIF_SEL 41 -#define ADSP_SC58X_CLK_RESERVED_SEL 42 -#define ADSP_SC58X_CLK_GIGE_SEL 43 -#define ADSP_SC58X_CLK_LP_SEL 44 -#define ADSP_SC58X_CLK_SDIO_SEL 45 -#define ADSP_SC58X_CLK_SHARC0 46 -#define ADSP_SC58X_CLK_SHARC1 47 -#define ADSP_SC58X_CLK_ARM 48 -#define ADSP_SC58X_CLK_CDU_DDR 49 -#define ADSP_SC58X_CLK_CAN 50 -#define ADSP_SC58X_CLK_SPDIF 51 -#define ADSP_SC58X_CLK_RESERVED 52 -#define ADSP_SC58X_CLK_GIGE 53 -#define ADSP_SC58X_CLK_LP 54 -#define ADSP_SC58X_CLK_SDIO 55 -#define ADSP_SC58X_CLK_END 56 - -//ADSP-SC57X -#define ADSP_SC57X_CLK_DUMMY 0 -#define ADSP_SC57X_CLK_SYS_CLKIN0 1 -#define ADSP_SC57X_CLK_SYS_CLKIN1 2 -#define ADSP_SC57X_CLK_CGU0_PLL_IN 3 -#define ADSP_SC57X_CLK_CGU0_PLLCLK 4 -#define ADSP_SC57X_CLK_CGU1_IN 5 -#define ADSP_SC57X_CLK_CGU1_PLL_IN 6 -#define ADSP_SC57X_CLK_CGU1_PLLCLK 7 -#define ADSP_SC57X_CLK_CGU0_CDIV 8 -#define ADSP_SC57X_CLK_CGU0_SYSCLK 9 -#define ADSP_SC57X_CLK_CGU0_DDIV 10 -#define ADSP_SC57X_CLK_CGU0_ODIV 11 -#define ADSP_SC57X_CLK_CGU0_S0SELDIV 12 -#define ADSP_SC57X_CLK_CGU0_S1SELDIV 13 -#define ADSP_SC57X_CLK_CGU1_CDIV 14 -#define ADSP_SC57X_CLK_CGU1_SYSCLK 15 -#define ADSP_SC57X_CLK_CGU1_DDIV 16 -#define ADSP_SC57X_CLK_CGU1_ODIV 17 -#define ADSP_SC57X_CLK_CGU1_S0SELDIV 18 -#define ADSP_SC57X_CLK_CGU1_S1SELDIV 19 -#define ADSP_SC57X_CLK_CGU0_CCLK0 20 -#define ADSP_SC57X_CLK_CGU0_CCLK1 21 -#define ADSP_SC57X_CLK_CGU0_OCLK 22 -#define ADSP_SC57X_CLK_CGU0_DCLK 23 -#define ADSP_SC57X_CLK_CGU0_SCLK1 24 -#define ADSP_SC57X_CLK_CGU0_SCLK0 25 -#define ADSP_SC57X_CLK_CGU1_CCLK0 26 -#define ADSP_SC57X_CLK_CGU1_CCLK1 27 -#define ADSP_SC57X_CLK_CGU1_OCLK 28 -#define ADSP_SC57X_CLK_CGU1_DCLK 29 -#define ADSP_SC57X_CLK_CGU1_SCLK1 30 -#define ADSP_SC57X_CLK_CGU1_SCLK0 31 -#define ADSP_SC57X_CLK_OCLK0_HALF 32 -#define ADSP_SC57X_CLK_CCLK1_1_HALF 33 -#define ADSP_SC57X_CLK_SHARC0_SEL 34 -#define ADSP_SC57X_CLK_SHARC1_SEL 35 -#define ADSP_SC57X_CLK_ARM_SEL 36 -#define ADSP_SC57X_CLK_CDU_DDR_SEL 37 -#define ADSP_SC57X_CLK_CAN_SEL 38 -#define ADSP_SC57X_CLK_SPDIF_SEL 39 -#define ADSP_SC57X_CLK_GIGE_SEL 40 -#define ADSP_SC57X_CLK_SDIO_SEL 41 -#define ADSP_SC57X_CLK_SHARC0 42 -#define ADSP_SC57X_CLK_SHARC1 43 -#define ADSP_SC57X_CLK_ARM 44 -#define ADSP_SC57X_CLK_CDU_DDR 45 -#define ADSP_SC57X_CLK_CAN 46 -#define ADSP_SC57X_CLK_SPDIF 47 -#define ADSP_SC57X_CLK_GIGE 48 -#define ADSP_SC57X_CLK_SDIO 49 -#define ADSP_SC57X_CLK_END 50 - -#endif diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h deleted file mode 100644 index d97840f9ee2e15e31cc2f93dcde4afe3c4a1e9e2..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rk3308-cru.h +++ /dev/null @@ -1,387 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Rockchip Electronics Co. Ltd. - * Author: Finley Xiao - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_VPLL0 3 -#define PLL_VPLL1 4 -#define ARMCLK 5 - -/* sclk (special clocks) */ -#define USB480M 14 -#define SCLK_RTC32K 15 -#define SCLK_PVTM_CORE 16 -#define SCLK_UART0 17 -#define SCLK_UART1 18 -#define SCLK_UART2 19 -#define SCLK_UART3 20 -#define SCLK_UART4 21 -#define SCLK_I2C0 22 -#define SCLK_I2C1 23 -#define SCLK_I2C2 24 -#define SCLK_I2C3 25 -#define SCLK_PWM0 26 -#define SCLK_SPI0 27 -#define SCLK_SPI1 28 -#define SCLK_SPI2 29 -#define SCLK_TIMER0 30 -#define SCLK_TIMER1 31 -#define SCLK_TIMER2 32 -#define SCLK_TIMER3 33 -#define SCLK_TIMER4 34 -#define SCLK_TIMER5 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_OTP 38 -#define SCLK_OTP_USR 39 -#define SCLK_CPU_BOOST 40 -#define SCLK_CRYPTO 41 -#define SCLK_CRYPTO_APK 42 -#define SCLK_NANDC_DIV 43 -#define SCLK_NANDC_DIV50 44 -#define SCLK_NANDC 45 -#define SCLK_SDMMC_DIV 46 -#define SCLK_SDMMC_DIV50 47 -#define SCLK_SDMMC 48 -#define SCLK_SDMMC_DRV 49 -#define SCLK_SDMMC_SAMPLE 50 -#define SCLK_SDIO_DIV 51 -#define SCLK_SDIO_DIV50 52 -#define SCLK_SDIO 53 -#define SCLK_SDIO_DRV 54 -#define SCLK_SDIO_SAMPLE 55 -#define SCLK_EMMC_DIV 56 -#define SCLK_EMMC_DIV50 57 -#define SCLK_EMMC 58 -#define SCLK_EMMC_DRV 59 -#define SCLK_EMMC_SAMPLE 60 -#define SCLK_SFC 61 -#define SCLK_OTG_ADP 62 -#define SCLK_MAC_SRC 63 -#define SCLK_MAC 64 -#define SCLK_MAC_REF 65 -#define SCLK_MAC_RX_TX 66 -#define SCLK_MAC_RMII 67 -#define SCLK_DDR_MON_TIMER 68 -#define SCLK_DDR_MON 69 -#define SCLK_DDRCLK 70 -#define SCLK_PMU 71 -#define SCLK_USBPHY_REF 72 -#define SCLK_WIFI 73 -#define SCLK_PVTM_PMU 74 -#define SCLK_PDM 75 -#define SCLK_I2S0_8CH_TX 76 -#define SCLK_I2S0_8CH_TX_OUT 77 -#define SCLK_I2S0_8CH_RX 78 -#define SCLK_I2S0_8CH_RX_OUT 79 -#define SCLK_I2S1_8CH_TX 80 -#define SCLK_I2S1_8CH_TX_OUT 81 -#define SCLK_I2S1_8CH_RX 82 -#define SCLK_I2S1_8CH_RX_OUT 83 -#define SCLK_I2S2_8CH_TX 84 -#define SCLK_I2S2_8CH_TX_OUT 85 -#define SCLK_I2S2_8CH_RX 86 -#define SCLK_I2S2_8CH_RX_OUT 87 -#define SCLK_I2S3_8CH_TX 88 -#define SCLK_I2S3_8CH_TX_OUT 89 -#define SCLK_I2S3_8CH_RX 90 -#define SCLK_I2S3_8CH_RX_OUT 91 -#define SCLK_I2S0_2CH 92 -#define SCLK_I2S0_2CH_OUT 93 -#define SCLK_I2S1_2CH 94 -#define SCLK_I2S1_2CH_OUT 95 -#define SCLK_SPDIF_TX_DIV 96 -#define SCLK_SPDIF_TX_DIV50 97 -#define SCLK_SPDIF_TX 98 -#define SCLK_SPDIF_RX_DIV 99 -#define SCLK_SPDIF_RX_DIV50 100 -#define SCLK_SPDIF_RX 101 -#define SCLK_I2S0_8CH_TX_MUX 102 -#define SCLK_I2S0_8CH_RX_MUX 103 -#define SCLK_I2S1_8CH_TX_MUX 104 -#define SCLK_I2S1_8CH_RX_MUX 105 -#define SCLK_I2S2_8CH_TX_MUX 106 -#define SCLK_I2S2_8CH_RX_MUX 107 -#define SCLK_I2S3_8CH_TX_MUX 108 -#define SCLK_I2S3_8CH_RX_MUX 109 -#define SCLK_I2S0_8CH_TX_SRC 110 -#define SCLK_I2S0_8CH_RX_SRC 111 -#define SCLK_I2S1_8CH_TX_SRC 112 -#define SCLK_I2S1_8CH_RX_SRC 113 -#define SCLK_I2S2_8CH_TX_SRC 114 -#define SCLK_I2S2_8CH_RX_SRC 115 -#define SCLK_I2S3_8CH_TX_SRC 116 -#define SCLK_I2S3_8CH_RX_SRC 117 -#define SCLK_I2S0_2CH_SRC 118 -#define SCLK_I2S1_2CH_SRC 119 -#define SCLK_PWM1 120 -#define SCLK_PWM2 121 -#define SCLK_OWIRE 122 - -/* dclk */ -#define DCLK_VOP 125 - -/* aclk */ -#define ACLK_BUS_SRC 130 -#define ACLK_BUS 131 -#define ACLK_PERI_SRC 132 -#define ACLK_PERI 133 -#define ACLK_MAC 134 -#define ACLK_CRYPTO 135 -#define ACLK_VOP 136 -#define ACLK_GIC 137 -#define ACLK_DMAC0 138 -#define ACLK_DMAC1 139 - -/* hclk */ -#define HCLK_BUS 150 -#define HCLK_PERI 151 -#define HCLK_AUDIO 152 -#define HCLK_NANDC 153 -#define HCLK_SDMMC 154 -#define HCLK_SDIO 155 -#define HCLK_EMMC 156 -#define HCLK_SFC 157 -#define HCLK_OTG 158 -#define HCLK_HOST 159 -#define HCLK_HOST_ARB 160 -#define HCLK_PDM 161 -#define HCLK_SPDIFTX 162 -#define HCLK_SPDIFRX 163 -#define HCLK_I2S0_8CH 164 -#define HCLK_I2S1_8CH 165 -#define HCLK_I2S2_8CH 166 -#define HCLK_I2S3_8CH 167 -#define HCLK_I2S0_2CH 168 -#define HCLK_I2S1_2CH 169 -#define HCLK_VAD 170 -#define HCLK_CRYPTO 171 -#define HCLK_VOP 172 - -/* pclk */ -#define PCLK_BUS 190 -#define PCLK_DDR 191 -#define PCLK_PERI 192 -#define PCLK_PMU 193 -#define PCLK_AUDIO 194 -#define PCLK_MAC 195 -#define PCLK_ACODEC 196 -#define PCLK_UART0 197 -#define PCLK_UART1 198 -#define PCLK_UART2 199 -#define PCLK_UART3 200 -#define PCLK_UART4 201 -#define PCLK_I2C0 202 -#define PCLK_I2C1 203 -#define PCLK_I2C2 204 -#define PCLK_I2C3 205 -#define PCLK_PWM0 206 -#define PCLK_SPI0 207 -#define PCLK_SPI1 208 -#define PCLK_SPI2 209 -#define PCLK_SARADC 210 -#define PCLK_TSADC 211 -#define PCLK_TIMER 212 -#define PCLK_OTP_NS 213 -#define PCLK_WDT 214 -#define PCLK_GPIO0 215 -#define PCLK_GPIO1 216 -#define PCLK_GPIO2 217 -#define PCLK_GPIO3 218 -#define PCLK_GPIO4 219 -#define PCLK_SGRF 220 -#define PCLK_GRF 221 -#define PCLK_USBSD_DET 222 -#define PCLK_DDR_UPCTL 223 -#define PCLK_DDR_MON 224 -#define PCLK_DDRPHY 225 -#define PCLK_DDR_STDBY 226 -#define PCLK_USB_GRF 227 -#define PCLK_CRU 228 -#define PCLK_OTP_PHY 229 -#define PCLK_CPU_BOOST 230 -#define PCLK_PWM1 231 -#define PCLK_PWM2 232 -#define PCLK_CAN 233 -#define PCLK_OWIRE 234 - -#define CLK_NR_CLKS (PCLK_OWIRE + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -/* cru_softrst_con1 */ -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_CORE_PRF 18 -#define SRST_CORE_GRF 19 -#define SRST_DDRUPCTL 20 -#define SRST_DDRUPCTL_P 22 -#define SRST_MSCH 23 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRPHY 28 -#define SRST_DDRPHY_DIV 29 -#define SRST_DDRPHY_P 30 - -/* cru_softrst_con2 */ -#define SRST_BUS_NIU_H 32 -#define SRST_USB_NIU_P 33 -#define SRST_CRYPTO_A 34 -#define SRST_CRYPTO_H 35 -#define SRST_CRYPTO 36 -#define SRST_CRYPTO_APK 37 -#define SRST_VOP_A 38 -#define SRST_VOP_H 39 -#define SRST_VOP_D 40 -#define SRST_INTMEM_A 41 -#define SRST_ROM_H 42 -#define SRST_GIC_A 43 -#define SRST_UART0_P 44 -#define SRST_UART0 45 -#define SRST_UART1_P 46 -#define SRST_UART1 47 - -/* cru_softrst_con3 */ -#define SRST_UART2_P 48 -#define SRST_UART2 49 -#define SRST_UART3_P 50 -#define SRST_UART3 51 -#define SRST_UART4_P 52 -#define SRST_UART4 53 -#define SRST_I2C0_P 54 -#define SRST_I2C0 55 -#define SRST_I2C1_P 56 -#define SRST_I2C1 57 -#define SRST_I2C2_P 58 -#define SRST_I2C2 59 -#define SRST_I2C3_P 60 -#define SRST_I2C3 61 -#define SRST_PWM0_P 62 -#define SRST_PWM0 63 - -/* cru_softrst_con4 */ -#define SRST_SPI0_P 64 -#define SRST_SPI0 65 -#define SRST_SPI1_P 66 -#define SRST_SPI1 67 -#define SRST_SPI2_P 68 -#define SRST_SPI2 69 -#define SRST_SARADC_P 70 -#define SRST_TSADC_P 71 -#define SRST_TSADC 72 -#define SRST_TIMER0_P 73 -#define SRST_TIMER0 74 -#define SRST_TIMER1 75 -#define SRST_TIMER2 76 -#define SRST_TIMER3 77 -#define SRST_TIMER4 78 -#define SRST_TIMER5 79 - -/* cru_softrst_con5 */ -#define SRST_OTP_NS_P 80 -#define SRST_OTP_NS_SBPI 81 -#define SRST_OTP_NS_USR 82 -#define SRST_OTP_PHY_P 83 -#define SRST_OTP_PHY 84 -#define SRST_GPIO0_P 86 -#define SRST_GPIO1_P 87 -#define SRST_GPIO2_P 88 -#define SRST_GPIO3_P 89 -#define SRST_GPIO4_P 90 -#define SRST_GRF_P 91 -#define SRST_USBSD_DET_P 92 -#define SRST_PMU 93 -#define SRST_PMU_PVTM 94 -#define SRST_USB_GRF_P 95 - -/* cru_softrst_con6 */ -#define SRST_CPU_BOOST 96 -#define SRST_CPU_BOOST_P 97 -#define SRST_PWM1_P 98 -#define SRST_PWM1 99 -#define SRST_PWM2_P 100 -#define SRST_PWM2 101 -#define SRST_PERI_NIU_A 104 -#define SRST_PERI_NIU_H 105 -#define SRST_PERI_NIU_p 106 -#define SRST_USB2OTG_H 107 -#define SRST_USB2OTG 108 -#define SRST_USB2OTG_ADP 109 -#define SRST_USB2HOST_H 110 -#define SRST_USB2HOST_ARB_H 111 - -/* cru_softrst_con7 */ -#define SRST_USB2HOST_AUX_H 112 -#define SRST_USB2HOST_EHCI 113 -#define SRST_USB2HOST 114 -#define SRST_USBPHYPOR 115 -#define SRST_UTMI0 116 -#define SRST_UTMI1 117 -#define SRST_SDIO_H 118 -#define SRST_EMMC_H 119 -#define SRST_SFC_H 120 -#define SRST_SFC 121 -#define SRST_SD_H 122 -#define SRST_NANDC_H 123 -#define SRST_NANDC_N 124 -#define SRST_MAC_A 125 -#define SRST_CAN_P 126 -#define SRST_OWIRE_P 127 - -/* cru_softrst_con8 */ -#define SRST_AUDIO_NIU_H 128 -#define SRST_AUDIO_NIU_P 129 -#define SRST_PDM_H 130 -#define SRST_PDM_M 131 -#define SRST_SPDIFTX_H 132 -#define SRST_SPDIFTX_M 133 -#define SRST_SPDIFRX_H 134 -#define SRST_SPDIFRX_M 135 -#define SRST_I2S0_8CH_H 136 -#define SRST_I2S0_8CH_TX_M 137 -#define SRST_I2S0_8CH_RX_M 138 -#define SRST_I2S1_8CH_H 139 -#define SRST_I2S1_8CH_TX_M 140 -#define SRST_I2S1_8CH_RX_M 141 -#define SRST_I2S2_8CH_H 142 -#define SRST_I2S2_8CH_TX_M 143 - -/* cru_softrst_con9 */ -#define SRST_I2S2_8CH_RX_M 144 -#define SRST_I2S3_8CH_H 145 -#define SRST_I2S3_8CH_TX_M 146 -#define SRST_I2S3_8CH_RX_M 147 -#define SRST_I2S0_2CH_H 148 -#define SRST_I2S0_2CH_M 149 -#define SRST_I2S1_2CH_H 150 -#define SRST_I2S1_2CH_M 151 -#define SRST_VAD_H 152 -#define SRST_ACODEC_P 153 - -#endif diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h deleted file mode 100644 index 555b4ff660ae6d3fa5b53bbf27d3b28a99d6a6c2..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rk3328-cru.h +++ /dev/null @@ -1,393 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_RTC32K 30 -#define SCLK_SDMMC_EXT 31 -#define SCLK_SPI 32 -#define SCLK_SDMMC 33 -#define SCLK_SDIO 34 -#define SCLK_EMMC 35 -#define SCLK_TSADC 36 -#define SCLK_SARADC 37 -#define SCLK_UART0 38 -#define SCLK_UART1 39 -#define SCLK_UART2 40 -#define SCLK_I2S0 41 -#define SCLK_I2S1 42 -#define SCLK_I2S2 43 -#define SCLK_I2S1_OUT 44 -#define SCLK_I2S2_OUT 45 -#define SCLK_SPDIF 46 -#define SCLK_TIMER0 47 -#define SCLK_TIMER1 48 -#define SCLK_TIMER2 49 -#define SCLK_TIMER3 50 -#define SCLK_TIMER4 51 -#define SCLK_TIMER5 52 -#define SCLK_WIFI 53 -#define SCLK_CIF_OUT 54 -#define SCLK_I2C0 55 -#define SCLK_I2C1 56 -#define SCLK_I2C2 57 -#define SCLK_I2C3 58 -#define SCLK_CRYPTO 59 -#define SCLK_PWM 60 -#define SCLK_PDM 61 -#define SCLK_EFUSE 62 -#define SCLK_OTP 63 -#define SCLK_DDRCLK 64 -#define SCLK_VDEC_CABAC 65 -#define SCLK_VDEC_CORE 66 -#define SCLK_VENC_DSP 67 -#define SCLK_VENC_CORE 68 -#define SCLK_RGA 69 -#define SCLK_HDMI_SFC 70 -#define SCLK_HDMI_CEC 71 -#define SCLK_USB3_REF 72 -#define SCLK_USB3_SUSPEND 73 -#define SCLK_SDMMC_DRV 74 -#define SCLK_SDIO_DRV 75 -#define SCLK_EMMC_DRV 76 -#define SCLK_SDMMC_EXT_DRV 77 -#define SCLK_SDMMC_SAMPLE 78 -#define SCLK_SDIO_SAMPLE 79 -#define SCLK_EMMC_SAMPLE 80 -#define SCLK_SDMMC_EXT_SAMPLE 81 -#define SCLK_VOP 82 -#define SCLK_MAC2PHY_RXTX 83 -#define SCLK_MAC2PHY_SRC 84 -#define SCLK_MAC2PHY_REF 85 -#define SCLK_MAC2PHY_OUT 86 -#define SCLK_MAC2IO_RX 87 -#define SCLK_MAC2IO_TX 88 -#define SCLK_MAC2IO_REFOUT 89 -#define SCLK_MAC2IO_REF 90 -#define SCLK_MAC2IO_OUT 91 -#define SCLK_TSP 92 -#define SCLK_HSADC_TSP 93 -#define SCLK_USB3PHY_REF 94 -#define SCLK_REF_USB3OTG 95 -#define SCLK_USB3OTG_REF 96 -#define SCLK_USB3OTG_SUSPEND 97 -#define SCLK_REF_USB3OTG_SRC 98 -#define SCLK_MAC2IO_SRC 99 -#define SCLK_MAC2IO 100 -#define SCLK_MAC2PHY 101 -#define SCLK_MAC2IO_EXT 102 - -/* dclk gates */ -#define DCLK_LCDC 120 -#define DCLK_HDMIPHY 121 -#define HDMIPHY 122 -#define USB480M 123 -#define DCLK_LCDC_SRC 124 - -/* aclk gates */ -#define ACLK_AXISRAM 130 -#define ACLK_VOP_PRE 131 -#define ACLK_USB3OTG 132 -#define ACLK_RGA_PRE 133 -#define ACLK_DMAC 134 -#define ACLK_GPU 135 -#define ACLK_BUS_PRE 136 -#define ACLK_PERI_PRE 137 -#define ACLK_RKVDEC_PRE 138 -#define ACLK_RKVDEC 139 -#define ACLK_RKVENC 140 -#define ACLK_VPU_PRE 141 -#define ACLK_VIO_PRE 142 -#define ACLK_VPU 143 -#define ACLK_VIO 144 -#define ACLK_VOP 145 -#define ACLK_GMAC 146 -#define ACLK_H265 147 -#define ACLK_H264 148 -#define ACLK_MAC2PHY 149 -#define ACLK_MAC2IO 150 -#define ACLK_DCF 151 -#define ACLK_TSP 152 -#define ACLK_PERI 153 -#define ACLK_RGA 154 -#define ACLK_IEP 155 -#define ACLK_CIF 156 -#define ACLK_HDCP 157 - -/* pclk gates */ -#define PCLK_GPIO0 200 -#define PCLK_GPIO1 201 -#define PCLK_GPIO2 202 -#define PCLK_GPIO3 203 -#define PCLK_GRF 204 -#define PCLK_I2C0 205 -#define PCLK_I2C1 206 -#define PCLK_I2C2 207 -#define PCLK_I2C3 208 -#define PCLK_SPI 209 -#define PCLK_UART0 210 -#define PCLK_UART1 211 -#define PCLK_UART2 212 -#define PCLK_TSADC 213 -#define PCLK_PWM 214 -#define PCLK_TIMER 215 -#define PCLK_BUS_PRE 216 -#define PCLK_PERI_PRE 217 -#define PCLK_HDMI_CTRL 218 -#define PCLK_HDMI_PHY 219 -#define PCLK_GMAC 220 -#define PCLK_H265 221 -#define PCLK_MAC2PHY 222 -#define PCLK_MAC2IO 223 -#define PCLK_USB3PHY_OTG 224 -#define PCLK_USB3PHY_PIPE 225 -#define PCLK_USB3_GRF 226 -#define PCLK_USB2_GRF 227 -#define PCLK_HDMIPHY 228 -#define PCLK_DDR 229 -#define PCLK_PERI 230 -#define PCLK_HDMI 231 -#define PCLK_HDCP 232 -#define PCLK_DCF 233 -#define PCLK_SARADC 234 -#define PCLK_ACODECPHY 235 -#define PCLK_WDT 236 - -/* hclk gates */ -#define HCLK_PERI 308 -#define HCLK_TSP 309 -#define HCLK_GMAC 310 -#define HCLK_I2S0_8CH 311 -#define HCLK_I2S1_8CH 312 -#define HCLK_I2S2_2CH 313 -#define HCLK_SPDIF_8CH 314 -#define HCLK_VOP 315 -#define HCLK_NANDC 316 -#define HCLK_SDMMC 317 -#define HCLK_SDIO 318 -#define HCLK_EMMC 319 -#define HCLK_SDMMC_EXT 320 -#define HCLK_RKVDEC_PRE 321 -#define HCLK_RKVDEC 322 -#define HCLK_RKVENC 323 -#define HCLK_VPU_PRE 324 -#define HCLK_VIO_PRE 325 -#define HCLK_VPU 326 -#define HCLK_BUS_PRE 328 -#define HCLK_PERI_PRE 329 -#define HCLK_H264 330 -#define HCLK_CIF 331 -#define HCLK_OTG_PMU 332 -#define HCLK_OTG 333 -#define HCLK_HOST0 334 -#define HCLK_HOST0_ARB 335 -#define HCLK_CRYPTO_MST 336 -#define HCLK_CRYPTO_SLV 337 -#define HCLK_PDM 338 -#define HCLK_IEP 339 -#define HCLK_RGA 340 -#define HCLK_HDCP 341 - -#define CLK_NR_CLKS (HCLK_HDCP + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NIU 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_A53_GIC 18 -#define SRST_DAP 19 -#define SRST_PMU_P 21 -#define SRST_EFUSE 22 -#define SRST_BUSSYS_H 23 -#define SRST_BUSSYS_P 24 -#define SRST_SPDIF 25 -#define SRST_INTMEM 26 -#define SRST_ROM 27 -#define SRST_GPIO0 28 -#define SRST_GPIO1 29 -#define SRST_GPIO2 30 -#define SRST_GPIO3 31 - -#define SRST_I2S0 32 -#define SRST_I2S1 33 -#define SRST_I2S2 34 -#define SRST_I2S0_H 35 -#define SRST_I2S1_H 36 -#define SRST_I2S2_H 37 -#define SRST_UART0 38 -#define SRST_UART1 39 -#define SRST_UART2 40 -#define SRST_UART0_P 41 -#define SRST_UART1_P 42 -#define SRST_UART2_P 43 -#define SRST_I2C0 44 -#define SRST_I2C1 45 -#define SRST_I2C2 46 -#define SRST_I2C3 47 - -#define SRST_I2C0_P 48 -#define SRST_I2C1_P 49 -#define SRST_I2C2_P 50 -#define SRST_I2C3_P 51 -#define SRST_EFUSE_SE_P 52 -#define SRST_EFUSE_NS_P 53 -#define SRST_PWM0 54 -#define SRST_PWM0_P 55 -#define SRST_DMA 56 -#define SRST_TSP_A 57 -#define SRST_TSP_H 58 -#define SRST_TSP 59 -#define SRST_TSP_HSADC 60 -#define SRST_DCF_A 61 -#define SRST_DCF_P 62 - -#define SRST_SCR 64 -#define SRST_SPI 65 -#define SRST_TSADC 66 -#define SRST_TSADC_P 67 -#define SRST_CRYPTO 68 -#define SRST_SGRF 69 -#define SRST_GRF 70 -#define SRST_USB_GRF 71 -#define SRST_TIMER_6CH_P 72 -#define SRST_TIMER0 73 -#define SRST_TIMER1 74 -#define SRST_TIMER2 75 -#define SRST_TIMER3 76 -#define SRST_TIMER4 77 -#define SRST_TIMER5 78 -#define SRST_USB3GRF 79 - -#define SRST_PHYNIU 80 -#define SRST_HDMIPHY 81 -#define SRST_VDAC 82 -#define SRST_ACODEC_p 83 -#define SRST_SARADC 85 -#define SRST_SARADC_P 86 -#define SRST_GRF_DDR 87 -#define SRST_DFIMON 88 -#define SRST_MSCH 89 -#define SRST_DDRMSCH 91 -#define SRST_DDRCTRL 92 -#define SRST_DDRCTRL_P 93 -#define SRST_DDRPHY 94 -#define SRST_DDRPHY_P 95 - -#define SRST_GMAC_NIU_A 96 -#define SRST_GMAC_NIU_P 97 -#define SRST_GMAC2PHY_A 98 -#define SRST_GMAC2IO_A 99 -#define SRST_MACPHY 100 -#define SRST_OTP_PHY 101 -#define SRST_GPU_A 102 -#define SRST_GPU_NIU_A 103 -#define SRST_SDMMCEXT 104 -#define SRST_PERIPH_NIU_A 105 -#define SRST_PERIHP_NIU_H 106 -#define SRST_PERIHP_P 107 -#define SRST_PERIPHSYS_H 108 -#define SRST_MMC0 109 -#define SRST_SDIO 110 -#define SRST_EMMC 111 - -#define SRST_USB2OTG_H 112 -#define SRST_USB2OTG 113 -#define SRST_USB2OTG_ADP 114 -#define SRST_USB2HOST_H 115 -#define SRST_USB2HOST_ARB 116 -#define SRST_USB2HOST_AUX 117 -#define SRST_USB2HOST_EHCIPHY 118 -#define SRST_USB2HOST_UTMI 119 -#define SRST_USB3OTG 120 -#define SRST_USBPOR 121 -#define SRST_USB2OTG_UTMI 122 -#define SRST_USB2HOST_PHY_UTMI 123 -#define SRST_USB3OTG_UTMI 124 -#define SRST_USB3PHY_U2 125 -#define SRST_USB3PHY_U3 126 -#define SRST_USB3PHY_PIPE 127 - -#define SRST_VIO_A 128 -#define SRST_VIO_BUS_H 129 -#define SRST_VIO_H2P_H 130 -#define SRST_VIO_ARBI_H 131 -#define SRST_VOP_NIU_A 132 -#define SRST_VOP_A 133 -#define SRST_VOP_H 134 -#define SRST_VOP_D 135 -#define SRST_RGA 136 -#define SRST_RGA_NIU_A 137 -#define SRST_RGA_A 138 -#define SRST_RGA_H 139 -#define SRST_IEP_A 140 -#define SRST_IEP_H 141 -#define SRST_HDMI 142 -#define SRST_HDMI_P 143 - -#define SRST_HDCP_A 144 -#define SRST_HDCP 145 -#define SRST_HDCP_H 146 -#define SRST_CIF_A 147 -#define SRST_CIF_H 148 -#define SRST_CIF_P 149 -#define SRST_OTP_P 150 -#define SRST_OTP_SBPI 151 -#define SRST_OTP_USER 152 -#define SRST_DDRCTRL_A 153 -#define SRST_DDRSTDY_P 154 -#define SRST_DDRSTDY 155 -#define SRST_PDM_H 156 -#define SRST_PDM 157 -#define SRST_USB3PHY_OTG_P 158 -#define SRST_USB3PHY_PIPE_P 159 - -#define SRST_VCODEC_A 160 -#define SRST_VCODEC_NIU_A 161 -#define SRST_VCODEC_H 162 -#define SRST_VCODEC_NIU_H 163 -#define SRST_VDEC_A 164 -#define SRST_VDEC_NIU_A 165 -#define SRST_VDEC_H 166 -#define SRST_VDEC_NIU_H 167 -#define SRST_VDEC_CORE 168 -#define SRST_VDEC_CABAC 169 -#define SRST_DDRPHYDIV 175 - -#define SRST_RKVENC_NIU_A 176 -#define SRST_RKVENC_NIU_H 177 -#define SRST_RKVENC_H265_A 178 -#define SRST_RKVENC_H265_P 179 -#define SRST_RKVENC_H265_CORE 180 -#define SRST_RKVENC_H265_DSP 181 -#define SRST_RKVENC_H264_A 182 -#define SRST_RKVENC_H264_H 183 -#define SRST_RKVENC_INTMEM 184 - -#endif diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h deleted file mode 100644 index 211faf8fa8917bf8ec18910abd60bbf1e14c6354..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rk3399-cru.h +++ /dev/null @@ -1,749 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Rockchip Electronics Co. Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H - -/* core clocks */ -#define PLL_APLLL 1 -#define PLL_APLLB 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define PLL_VPLL 7 -#define ARMCLKL 8 -#define ARMCLKB 9 - -/* sclk gates (special clocks) */ -#define SCLK_I2C1 65 -#define SCLK_I2C2 66 -#define SCLK_I2C3 67 -#define SCLK_I2C5 68 -#define SCLK_I2C6 69 -#define SCLK_I2C7 70 -#define SCLK_SPI0 71 -#define SCLK_SPI1 72 -#define SCLK_SPI2 73 -#define SCLK_SPI4 74 -#define SCLK_SPI5 75 -#define SCLK_SDMMC 76 -#define SCLK_SDIO 77 -#define SCLK_EMMC 78 -#define SCLK_TSADC 79 -#define SCLK_SARADC 80 -#define SCLK_UART0 81 -#define SCLK_UART1 82 -#define SCLK_UART2 83 -#define SCLK_UART3 84 -#define SCLK_SPDIF_8CH 85 -#define SCLK_I2S0_8CH 86 -#define SCLK_I2S1_8CH 87 -#define SCLK_I2S2_8CH 88 -#define SCLK_I2S_8CH_OUT 89 -#define SCLK_TIMER00 90 -#define SCLK_TIMER01 91 -#define SCLK_TIMER02 92 -#define SCLK_TIMER03 93 -#define SCLK_TIMER04 94 -#define SCLK_TIMER05 95 -#define SCLK_TIMER06 96 -#define SCLK_TIMER07 97 -#define SCLK_TIMER08 98 -#define SCLK_TIMER09 99 -#define SCLK_TIMER10 100 -#define SCLK_TIMER11 101 -#define SCLK_MACREF 102 -#define SCLK_MAC_RX 103 -#define SCLK_MAC_TX 104 -#define SCLK_MAC 105 -#define SCLK_MACREF_OUT 106 -#define SCLK_VOP0_PWM 107 -#define SCLK_VOP1_PWM 108 -#define SCLK_RGA_CORE 109 -#define SCLK_ISP0 110 -#define SCLK_ISP1 111 -#define SCLK_HDMI_CEC 112 -#define SCLK_HDMI_SFR 113 -#define SCLK_DP_CORE 114 -#define SCLK_PVTM_CORE_L 115 -#define SCLK_PVTM_CORE_B 116 -#define SCLK_PVTM_GPU 117 -#define SCLK_PVTM_DDR 118 -#define SCLK_MIPIDPHY_REF 119 -#define SCLK_MIPIDPHY_CFG 120 -#define SCLK_HSICPHY 121 -#define SCLK_USBPHY480M 122 -#define SCLK_USB2PHY0_REF 123 -#define SCLK_USB2PHY1_REF 124 -#define SCLK_UPHY0_TCPDPHY_REF 125 -#define SCLK_UPHY0_TCPDCORE 126 -#define SCLK_UPHY1_TCPDPHY_REF 127 -#define SCLK_UPHY1_TCPDCORE 128 -#define SCLK_USB3OTG0_REF 129 -#define SCLK_USB3OTG1_REF 130 -#define SCLK_USB3OTG0_SUSPEND 131 -#define SCLK_USB3OTG1_SUSPEND 132 -#define SCLK_CRYPTO0 133 -#define SCLK_CRYPTO1 134 -#define SCLK_CCI_TRACE 135 -#define SCLK_CS 136 -#define SCLK_CIF_OUT 137 -#define SCLK_PCIEPHY_REF 138 -#define SCLK_PCIE_CORE 139 -#define SCLK_M0_PERILP 140 -#define SCLK_M0_PERILP_DEC 141 -#define SCLK_CM0S 142 -#define SCLK_DBG_NOC 143 -#define SCLK_DBG_PD_CORE_B 144 -#define SCLK_DBG_PD_CORE_L 145 -#define SCLK_DFIMON0_TIMER 146 -#define SCLK_DFIMON1_TIMER 147 -#define SCLK_INTMEM0 148 -#define SCLK_INTMEM1 149 -#define SCLK_INTMEM2 150 -#define SCLK_INTMEM3 151 -#define SCLK_INTMEM4 152 -#define SCLK_INTMEM5 153 -#define SCLK_SDMMC_DRV 154 -#define SCLK_SDMMC_SAMPLE 155 -#define SCLK_SDIO_DRV 156 -#define SCLK_SDIO_SAMPLE 157 -#define SCLK_VDU_CORE 158 -#define SCLK_VDU_CA 159 -#define SCLK_PCIE_PM 160 -#define SCLK_SPDIF_REC_DPTX 161 -#define SCLK_DPHY_PLL 162 -#define SCLK_DPHY_TX0_CFG 163 -#define SCLK_DPHY_TX1RX1_CFG 164 -#define SCLK_DPHY_RX0_CFG 165 -#define SCLK_RMII_SRC 166 -#define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 - -#define DCLK_VOP0 180 -#define DCLK_VOP1 181 -#define DCLK_VOP0_DIV 182 -#define DCLK_VOP1_DIV 183 -#define DCLK_M0_PERILP 184 - -#define FCLK_CM0S 190 - -/* aclk gates */ -#define ACLK_PERIHP 192 -#define ACLK_PERIHP_NOC 193 -#define ACLK_PERILP0 194 -#define ACLK_PERILP0_NOC 195 -#define ACLK_PERF_PCIE 196 -#define ACLK_PCIE 197 -#define ACLK_INTMEM 198 -#define ACLK_TZMA 199 -#define ACLK_DCF 200 -#define ACLK_CCI 201 -#define ACLK_CCI_NOC0 202 -#define ACLK_CCI_NOC1 203 -#define ACLK_CCI_GRF 204 -#define ACLK_CENTER 205 -#define ACLK_CENTER_MAIN_NOC 206 -#define ACLK_CENTER_PERI_NOC 207 -#define ACLK_GPU 208 -#define ACLK_PERF_GPU 209 -#define ACLK_GPU_GRF 210 -#define ACLK_DMAC0_PERILP 211 -#define ACLK_DMAC1_PERILP 212 -#define ACLK_GMAC 213 -#define ACLK_GMAC_NOC 214 -#define ACLK_PERF_GMAC 215 -#define ACLK_VOP0_NOC 216 -#define ACLK_VOP0 217 -#define ACLK_VOP1_NOC 218 -#define ACLK_VOP1 219 -#define ACLK_RGA 220 -#define ACLK_RGA_NOC 221 -#define ACLK_HDCP 222 -#define ACLK_HDCP_NOC 223 -#define ACLK_HDCP22 224 -#define ACLK_IEP 225 -#define ACLK_IEP_NOC 226 -#define ACLK_VIO 227 -#define ACLK_VIO_NOC 228 -#define ACLK_ISP0 229 -#define ACLK_ISP1 230 -#define ACLK_ISP0_NOC 231 -#define ACLK_ISP1_NOC 232 -#define ACLK_ISP0_WRAPPER 233 -#define ACLK_ISP1_WRAPPER 234 -#define ACLK_VCODEC 235 -#define ACLK_VCODEC_NOC 236 -#define ACLK_VDU 237 -#define ACLK_VDU_NOC 238 -#define ACLK_PERI 239 -#define ACLK_EMMC 240 -#define ACLK_EMMC_CORE 241 -#define ACLK_EMMC_NOC 242 -#define ACLK_EMMC_GRF 243 -#define ACLK_USB3 244 -#define ACLK_USB3_NOC 245 -#define ACLK_USB3OTG0 246 -#define ACLK_USB3OTG1 247 -#define ACLK_USB3_RKSOC_AXI_PERF 248 -#define ACLK_USB3_GRF 249 -#define ACLK_GIC 250 -#define ACLK_GIC_NOC 251 -#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 -#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 -#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 -#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 -#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 -#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 -#define ACLK_ADB400M_PD_CORE_L 258 -#define ACLK_ADB400M_PD_CORE_B 259 -#define ACLK_PERF_CORE_L 260 -#define ACLK_PERF_CORE_B 261 -#define ACLK_GIC_PRE 262 -#define ACLK_VOP0_PRE 263 -#define ACLK_VOP1_PRE 264 - -/* pclk gates */ -#define PCLK_PERIHP 320 -#define PCLK_PERIHP_NOC 321 -#define PCLK_PERILP0 322 -#define PCLK_PERILP1 323 -#define PCLK_PERILP1_NOC 324 -#define PCLK_PERILP_SGRF 325 -#define PCLK_PERIHP_GRF 326 -#define PCLK_PCIE 327 -#define PCLK_SGRF 328 -#define PCLK_INTR_ARB 329 -#define PCLK_CENTER_MAIN_NOC 330 -#define PCLK_CIC 331 -#define PCLK_COREDBG_B 332 -#define PCLK_COREDBG_L 333 -#define PCLK_DBG_CXCS_PD_CORE_B 334 -#define PCLK_DCF 335 -#define PCLK_GPIO2 336 -#define PCLK_GPIO3 337 -#define PCLK_GPIO4 338 -#define PCLK_GRF 339 -#define PCLK_HSICPHY 340 -#define PCLK_I2C1 341 -#define PCLK_I2C2 342 -#define PCLK_I2C3 343 -#define PCLK_I2C5 344 -#define PCLK_I2C6 345 -#define PCLK_I2C7 346 -#define PCLK_SPI0 347 -#define PCLK_SPI1 348 -#define PCLK_SPI2 349 -#define PCLK_SPI4 350 -#define PCLK_SPI5 351 -#define PCLK_UART0 352 -#define PCLK_UART1 353 -#define PCLK_UART2 354 -#define PCLK_UART3 355 -#define PCLK_TSADC 356 -#define PCLK_SARADC 357 -#define PCLK_GMAC 358 -#define PCLK_GMAC_NOC 359 -#define PCLK_TIMER0 360 -#define PCLK_TIMER1 361 -#define PCLK_EDP 362 -#define PCLK_EDP_NOC 363 -#define PCLK_EDP_CTRL 364 -#define PCLK_VIO 365 -#define PCLK_VIO_NOC 366 -#define PCLK_VIO_GRF 367 -#define PCLK_MIPI_DSI0 368 -#define PCLK_MIPI_DSI1 369 -#define PCLK_HDCP 370 -#define PCLK_HDCP_NOC 371 -#define PCLK_HDMI_CTRL 372 -#define PCLK_DP_CTRL 373 -#define PCLK_HDCP22 374 -#define PCLK_GASKET 375 -#define PCLK_DDR 376 -#define PCLK_DDR_MON 377 -#define PCLK_DDR_SGRF 378 -#define PCLK_ISP1_WRAPPER 379 -#define PCLK_WDT 380 -#define PCLK_EFUSE1024NS 381 -#define PCLK_EFUSE1024S 382 -#define PCLK_PMU_INTR_ARB 383 -#define PCLK_MAILBOX0 384 -#define PCLK_USBPHY_MUX_G 385 -#define PCLK_UPHY0_TCPHY_G 386 -#define PCLK_UPHY0_TCPD_G 387 -#define PCLK_UPHY1_TCPHY_G 388 -#define PCLK_UPHY1_TCPD_G 389 -#define PCLK_ALIVE 390 - -/* hclk gates */ -#define HCLK_PERIHP 448 -#define HCLK_PERILP0 449 -#define HCLK_PERILP1 450 -#define HCLK_PERILP0_NOC 451 -#define HCLK_PERILP1_NOC 452 -#define HCLK_M0_PERILP 453 -#define HCLK_M0_PERILP_NOC 454 -#define HCLK_AHB1TOM 455 -#define HCLK_HOST0 456 -#define HCLK_HOST0_ARB 457 -#define HCLK_HOST1 458 -#define HCLK_HOST1_ARB 459 -#define HCLK_HSIC 460 -#define HCLK_SD 461 -#define HCLK_SDMMC 462 -#define HCLK_SDMMC_NOC 463 -#define HCLK_M_CRYPTO0 464 -#define HCLK_M_CRYPTO1 465 -#define HCLK_S_CRYPTO0 466 -#define HCLK_S_CRYPTO1 467 -#define HCLK_I2S0_8CH 468 -#define HCLK_I2S1_8CH 469 -#define HCLK_I2S2_8CH 470 -#define HCLK_SPDIF 471 -#define HCLK_VOP0_NOC 472 -#define HCLK_VOP0 473 -#define HCLK_VOP1_NOC 474 -#define HCLK_VOP1 475 -#define HCLK_ROM 476 -#define HCLK_IEP 477 -#define HCLK_IEP_NOC 478 -#define HCLK_ISP0 479 -#define HCLK_ISP1 480 -#define HCLK_ISP0_NOC 481 -#define HCLK_ISP1_NOC 482 -#define HCLK_ISP0_WRAPPER 483 -#define HCLK_ISP1_WRAPPER 484 -#define HCLK_RGA 485 -#define HCLK_RGA_NOC 486 -#define HCLK_HDCP 487 -#define HCLK_HDCP_NOC 488 -#define HCLK_HDCP22 489 -#define HCLK_VCODEC 490 -#define HCLK_VCODEC_NOC 491 -#define HCLK_VDU 492 -#define HCLK_VDU_NOC 493 -#define HCLK_SDIO 494 -#define HCLK_SDIO_NOC 495 -#define HCLK_SDIOAUDIO_NOC 496 - -#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) - -/* pmu-clocks indices */ - -#define PLL_PPLL 1 - -#define SCLK_32K_SUSPEND_PMU 2 -#define SCLK_SPI3_PMU 3 -#define SCLK_TIMER12_PMU 4 -#define SCLK_TIMER13_PMU 5 -#define SCLK_UART4_PMU 6 -#define SCLK_PVTM_PMU 7 -#define SCLK_WIFI_PMU 8 -#define SCLK_I2C0_PMU 9 -#define SCLK_I2C4_PMU 10 -#define SCLK_I2C8_PMU 11 - -#define PCLK_SRC_PMU 19 -#define PCLK_PMU 20 -#define PCLK_PMUGRF_PMU 21 -#define PCLK_INTMEM1_PMU 22 -#define PCLK_GPIO0_PMU 23 -#define PCLK_GPIO1_PMU 24 -#define PCLK_SGRF_PMU 25 -#define PCLK_NOC_PMU 26 -#define PCLK_I2C0_PMU 27 -#define PCLK_I2C4_PMU 28 -#define PCLK_I2C8_PMU 29 -#define PCLK_RKPWM_PMU 30 -#define PCLK_SPI3_PMU 31 -#define PCLK_TIMER_PMU 32 -#define PCLK_MAILBOX_PMU 33 -#define PCLK_UART4_PMU 34 -#define PCLK_WDT_M0_PMU 35 - -#define FCLK_CM0S_SRC_PMU 44 -#define FCLK_CM0S_PMU 45 -#define SCLK_CM0S_PMU 46 -#define HCLK_CM0S_PMU 47 -#define DCLK_CM0S_PMU 48 -#define PCLK_INTR_ARB_PMU 49 -#define HCLK_NOC_PMU 50 - -#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1) - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_CORE_L0 0 -#define SRST_CORE_B0 1 -#define SRST_CORE_PO_L0 2 -#define SRST_CORE_PO_B0 3 -#define SRST_L2_L 4 -#define SRST_L2_B 5 -#define SRST_ADB_L 6 -#define SRST_ADB_B 7 -#define SRST_A_CCI 8 -#define SRST_A_CCIM0_NOC 9 -#define SRST_A_CCIM1_NOC 10 -#define SRST_DBG_NOC 11 - -/* cru_softrst_con1 */ -#define SRST_CORE_L0_T 16 -#define SRST_CORE_L1 17 -#define SRST_CORE_L2 18 -#define SRST_CORE_L3 19 -#define SRST_CORE_PO_L0_T 20 -#define SRST_CORE_PO_L1 21 -#define SRST_CORE_PO_L2 22 -#define SRST_CORE_PO_L3 23 -#define SRST_A_ADB400_GIC2COREL 24 -#define SRST_A_ADB400_COREL2GIC 25 -#define SRST_P_DBG_L 26 -#define SRST_L2_L_T 28 -#define SRST_ADB_L_T 29 -#define SRST_A_RKPERF_L 30 -#define SRST_PVTM_CORE_L 31 - -/* cru_softrst_con2 */ -#define SRST_CORE_B0_T 32 -#define SRST_CORE_B1 33 -#define SRST_CORE_PO_B0_T 36 -#define SRST_CORE_PO_B1 37 -#define SRST_A_ADB400_GIC2COREB 40 -#define SRST_A_ADB400_COREB2GIC 41 -#define SRST_P_DBG_B 42 -#define SRST_L2_B_T 43 -#define SRST_ADB_B_T 45 -#define SRST_A_RKPERF_B 46 -#define SRST_PVTM_CORE_B 47 - -/* cru_softrst_con3 */ -#define SRST_A_CCI_T 50 -#define SRST_A_CCIM0_NOC_T 51 -#define SRST_A_CCIM1_NOC_T 52 -#define SRST_A_ADB400M_PD_CORE_B_T 53 -#define SRST_A_ADB400M_PD_CORE_L_T 54 -#define SRST_DBG_NOC_T 55 -#define SRST_DBG_CXCS 56 -#define SRST_CCI_TRACE 57 -#define SRST_P_CCI_GRF 58 - -/* cru_softrst_con4 */ -#define SRST_A_CENTER_MAIN_NOC 64 -#define SRST_A_CENTER_PERI_NOC 65 -#define SRST_P_CENTER_MAIN 66 -#define SRST_P_DDRMON 67 -#define SRST_P_CIC 68 -#define SRST_P_CENTER_SGRF 69 -#define SRST_DDR0_MSCH 70 -#define SRST_DDRCFG0_MSCH 71 -#define SRST_DDR0 72 -#define SRST_DDRPHY0 73 -#define SRST_DDR1_MSCH 74 -#define SRST_DDRCFG1_MSCH 75 -#define SRST_DDR1 76 -#define SRST_DDRPHY1 77 -#define SRST_DDR_CIC 78 -#define SRST_PVTM_DDR 79 - -/* cru_softrst_con5 */ -#define SRST_A_VCODEC_NOC 80 -#define SRST_A_VCODEC 81 -#define SRST_H_VCODEC_NOC 82 -#define SRST_H_VCODEC 83 -#define SRST_A_VDU_NOC 88 -#define SRST_A_VDU 89 -#define SRST_H_VDU_NOC 90 -#define SRST_H_VDU 91 -#define SRST_VDU_CORE 92 -#define SRST_VDU_CA 93 - -/* cru_softrst_con6 */ -#define SRST_A_IEP_NOC 96 -#define SRST_A_VOP_IEP 97 -#define SRST_A_IEP 98 -#define SRST_H_IEP_NOC 99 -#define SRST_H_IEP 100 -#define SRST_A_RGA_NOC 102 -#define SRST_A_RGA 103 -#define SRST_H_RGA_NOC 104 -#define SRST_H_RGA 105 -#define SRST_RGA_CORE 106 -#define SRST_EMMC_NOC 108 -#define SRST_EMMC 109 -#define SRST_EMMC_GRF 110 - -/* cru_softrst_con7 */ -#define SRST_A_PERIHP_NOC 112 -#define SRST_P_PERIHP_GRF 113 -#define SRST_H_PERIHP_NOC 114 -#define SRST_USBHOST0 115 -#define SRST_HOSTC0_AUX 116 -#define SRST_HOST0_ARB 117 -#define SRST_USBHOST1 118 -#define SRST_HOSTC1_AUX 119 -#define SRST_HOST1_ARB 120 -#define SRST_SDIO0 121 -#define SRST_SDMMC 122 -#define SRST_HSIC 123 -#define SRST_HSIC_AUX 124 -#define SRST_AHB1TOM 125 -#define SRST_P_PERIHP_NOC 126 -#define SRST_HSICPHY 127 - -/* cru_softrst_con8 */ -#define SRST_A_PCIE 128 -#define SRST_P_PCIE 129 -#define SRST_PCIE_CORE 130 -#define SRST_PCIE_MGMT 131 -#define SRST_PCIE_MGMT_STICKY 132 -#define SRST_PCIE_PIPE 133 -#define SRST_PCIE_PM 134 -#define SRST_PCIEPHY 135 -#define SRST_A_GMAC_NOC 136 -#define SRST_A_GMAC 137 -#define SRST_P_GMAC_NOC 138 -#define SRST_P_GMAC_GRF 140 -#define SRST_HSICPHY_POR 142 -#define SRST_HSICPHY_UTMI 143 - -/* cru_softrst_con9 */ -#define SRST_USB2PHY0_POR 144 -#define SRST_USB2PHY0_UTMI_PORT0 145 -#define SRST_USB2PHY0_UTMI_PORT1 146 -#define SRST_USB2PHY0_EHCIPHY 147 -#define SRST_UPHY0_PIPE_L00 148 -#define SRST_UPHY0 149 -#define SRST_UPHY0_TCPDPWRUP 150 -#define SRST_USB2PHY1_POR 152 -#define SRST_USB2PHY1_UTMI_PORT0 153 -#define SRST_USB2PHY1_UTMI_PORT1 154 -#define SRST_USB2PHY1_EHCIPHY 155 -#define SRST_UPHY1_PIPE_L00 156 -#define SRST_UPHY1 157 -#define SRST_UPHY1_TCPDPWRUP 158 - -/* cru_softrst_con10 */ -#define SRST_A_PERILP0_NOC 160 -#define SRST_A_DCF 161 -#define SRST_GIC500 162 -#define SRST_DMAC0_PERILP0 163 -#define SRST_DMAC1_PERILP0 164 -#define SRST_TZMA 165 -#define SRST_INTMEM 166 -#define SRST_ADB400_MST0 167 -#define SRST_ADB400_MST1 168 -#define SRST_ADB400_SLV0 169 -#define SRST_ADB400_SLV1 170 -#define SRST_H_PERILP0 171 -#define SRST_H_PERILP0_NOC 172 -#define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 - -/* cru_softrst_con11 */ -#define SRST_P_DCF 176 -#define SRST_CM0S_NOC 177 -#define SRST_CM0S 178 -#define SRST_CM0S_DBG 179 -#define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 -#define SRST_P_PERILP1_SGRF 182 -#define SRST_P_PERILP1_GRF 183 -#define SRST_CRYPTO1_S 184 -#define SRST_CRYPTO1_M 185 -#define SRST_CRYPTO1 186 -#define SRST_GIC_NOC 188 -#define SRST_SD_NOC 189 -#define SRST_SDIOAUDIO_BRG 190 - -/* cru_softrst_con12 */ -#define SRST_H_PERILP1 192 -#define SRST_H_PERILP1_NOC 193 -#define SRST_H_I2S0_8CH 194 -#define SRST_H_I2S1_8CH 195 -#define SRST_H_I2S2_8CH 196 -#define SRST_H_SPDIF_8CH 197 -#define SRST_P_PERILP1_NOC 198 -#define SRST_P_EFUSE_1024 199 -#define SRST_P_EFUSE_1024S 200 -#define SRST_P_I2C0 201 -#define SRST_P_I2C1 202 -#define SRST_P_I2C2 203 -#define SRST_P_I2C3 204 -#define SRST_P_I2C4 205 -#define SRST_P_I2C5 206 -#define SRST_P_MAILBOX0 207 - -/* cru_softrst_con13 */ -#define SRST_P_UART0 208 -#define SRST_P_UART1 209 -#define SRST_P_UART2 210 -#define SRST_P_UART3 211 -#define SRST_P_SARADC 212 -#define SRST_P_TSADC 213 -#define SRST_P_SPI0 214 -#define SRST_P_SPI1 215 -#define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 -#define SRST_SPI0 219 -#define SRST_SPI1 220 -#define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 - -/* cru_softrst_con14 */ -#define SRST_I2S0_8CH 224 -#define SRST_I2S1_8CH 225 -#define SRST_I2S2_8CH 226 -#define SRST_SPDIF_8CH 227 -#define SRST_UART0 228 -#define SRST_UART1 229 -#define SRST_UART2 230 -#define SRST_UART3 231 -#define SRST_TSADC 232 -#define SRST_I2C0 233 -#define SRST_I2C1 234 -#define SRST_I2C2 235 -#define SRST_I2C3 236 -#define SRST_I2C4 237 -#define SRST_I2C5 238 -#define SRST_SDIOAUDIO_NOC 239 - -/* cru_softrst_con15 */ -#define SRST_A_VIO_NOC 240 -#define SRST_A_HDCP_NOC 241 -#define SRST_A_HDCP 242 -#define SRST_H_HDCP_NOC 243 -#define SRST_H_HDCP 244 -#define SRST_P_HDCP_NOC 245 -#define SRST_P_HDCP 246 -#define SRST_P_HDMI_CTRL 247 -#define SRST_P_DP_CTRL 248 -#define SRST_S_DP_CTRL 249 -#define SRST_C_DP_CTRL 250 -#define SRST_P_MIPI_DSI0 251 -#define SRST_P_MIPI_DSI1 252 -#define SRST_DP_CORE 253 -#define SRST_DP_I2S 254 - -/* cru_softrst_con16 */ -#define SRST_GASKET 256 -#define SRST_VIO_GRF 258 -#define SRST_DPTX_SPDIF_REC 259 -#define SRST_HDMI_CTRL 260 -#define SRST_HDCP_CTRL 261 -#define SRST_A_ISP0_NOC 262 -#define SRST_A_ISP1_NOC 263 -#define SRST_H_ISP0_NOC 266 -#define SRST_H_ISP1_NOC 267 -#define SRST_H_ISP0 268 -#define SRST_H_ISP1 269 -#define SRST_ISP0 270 -#define SRST_ISP1 271 - -/* cru_softrst_con17 */ -#define SRST_A_VOP0_NOC 272 -#define SRST_A_VOP1_NOC 273 -#define SRST_A_VOP0 274 -#define SRST_A_VOP1 275 -#define SRST_H_VOP0_NOC 276 -#define SRST_H_VOP1_NOC 277 -#define SRST_H_VOP0 278 -#define SRST_H_VOP1 279 -#define SRST_D_VOP0 280 -#define SRST_D_VOP1 281 -#define SRST_VOP0_PWM 282 -#define SRST_VOP1_PWM 283 -#define SRST_P_EDP_NOC 284 -#define SRST_P_EDP_CTRL 285 - -/* cru_softrst_con18 */ -#define SRST_A_GPU 288 -#define SRST_A_GPU_NOC 289 -#define SRST_A_GPU_GRF 290 -#define SRST_PVTM_GPU 291 -#define SRST_A_USB3_NOC 292 -#define SRST_A_USB3_OTG0 293 -#define SRST_A_USB3_OTG1 294 -#define SRST_A_USB3_GRF 295 -#define SRST_PMU 296 - -/* cru_softrst_con19 */ -#define SRST_P_TIMER0_5 304 -#define SRST_TIMER0 305 -#define SRST_TIMER1 306 -#define SRST_TIMER2 307 -#define SRST_TIMER3 308 -#define SRST_TIMER4 309 -#define SRST_TIMER5 310 -#define SRST_P_TIMER6_11 311 -#define SRST_TIMER6 312 -#define SRST_TIMER7 313 -#define SRST_TIMER8 314 -#define SRST_TIMER9 315 -#define SRST_TIMER10 316 -#define SRST_TIMER11 317 -#define SRST_P_INTR_ARB_PMU 318 -#define SRST_P_ALIVE_SGRF 319 - -/* cru_softrst_con20 */ -#define SRST_P_GPIO2 320 -#define SRST_P_GPIO3 321 -#define SRST_P_GPIO4 322 -#define SRST_P_GRF 323 -#define SRST_P_ALIVE_NOC 324 -#define SRST_P_WDT0 325 -#define SRST_P_WDT1 326 -#define SRST_P_INTR_ARB 327 -#define SRST_P_UPHY0_DPTX 328 -#define SRST_P_UPHY0_APB 330 -#define SRST_P_UPHY0_TCPHY 332 -#define SRST_P_UPHY1_TCPHY 333 -#define SRST_P_UPHY0_TCPDCTRL 334 -#define SRST_P_UPHY1_TCPDCTRL 335 - -/* pmu soft-reset indices */ - -/* pmu_cru_softrst_con0 */ -#define SRST_P_NOC 0 -#define SRST_P_INTMEM 1 -#define SRST_H_CM0S 2 -#define SRST_H_CM0S_NOC 3 -#define SRST_DBG_CM0S 4 -#define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 -#define SRST_P_TIMER_0_1 8 -#define SRST_P_TIMER_0 9 -#define SRST_P_TIMER_1 10 -#define SRST_P_UART4 11 -#define SRST_UART4 12 -#define SRST_P_WDT 13 - -/* pmu_cru_softrst_con1 */ -#define SRST_P_I2C6 16 -#define SRST_P_I2C7 17 -#define SRST_P_I2C8 18 -#define SRST_P_MAILBOX 19 -#define SRST_P_RKPWM 20 -#define SRST_P_PMUGRF 21 -#define SRST_P_SGRF 22 -#define SRST_P_GPIO0 23 -#define SRST_P_GPIO1 24 -#define SRST_P_CRU 25 -#define SRST_P_INTR 26 -#define SRST_PVTM 27 -#define SRST_I2C6 28 -#define SRST_I2C7 29 -#define SRST_I2C8 30 - -#endif diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h deleted file mode 100644 index d29890865150d3c6e371e3fd589116db91c7764e..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rk3568-cru.h +++ /dev/null @@ -1,926 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H - -/* pmucru-clocks indices */ - -/* pmucru plls */ -#define PLL_PPLL 1 -#define PLL_HPLL 2 - -/* pmucru clocks */ -#define XIN_OSC0_DIV 4 -#define CLK_RTC_32K 5 -#define CLK_PMU 6 -#define CLK_I2C0 7 -#define CLK_RTC32K_FRAC 8 -#define CLK_UART0_DIV 9 -#define CLK_UART0_FRAC 10 -#define SCLK_UART0 11 -#define DBCLK_GPIO0 12 -#define CLK_PWM0 13 -#define CLK_CAPTURE_PWM0_NDFT 14 -#define CLK_PMUPVTM 15 -#define CLK_CORE_PMUPVTM 16 -#define CLK_REF24M 17 -#define XIN_OSC0_USBPHY0_G 18 -#define CLK_USBPHY0_REF 19 -#define XIN_OSC0_USBPHY1_G 20 -#define CLK_USBPHY1_REF 21 -#define XIN_OSC0_MIPIDSIPHY0_G 22 -#define CLK_MIPIDSIPHY0_REF 23 -#define XIN_OSC0_MIPIDSIPHY1_G 24 -#define CLK_MIPIDSIPHY1_REF 25 -#define CLK_WIFI_DIV 26 -#define CLK_WIFI_OSC0 27 -#define CLK_WIFI 28 -#define CLK_PCIEPHY0_DIV 29 -#define CLK_PCIEPHY0_OSC0 30 -#define CLK_PCIEPHY0_REF 31 -#define CLK_PCIEPHY1_DIV 32 -#define CLK_PCIEPHY1_OSC0 33 -#define CLK_PCIEPHY1_REF 34 -#define CLK_PCIEPHY2_DIV 35 -#define CLK_PCIEPHY2_OSC0 36 -#define CLK_PCIEPHY2_REF 37 -#define CLK_PCIE30PHY_REF_M 38 -#define CLK_PCIE30PHY_REF_N 39 -#define CLK_HDMI_REF 40 -#define XIN_OSC0_EDPPHY_G 41 -#define PCLK_PDPMU 42 -#define PCLK_PMU 43 -#define PCLK_UART0 44 -#define PCLK_I2C0 45 -#define PCLK_GPIO0 46 -#define PCLK_PMUPVTM 47 -#define PCLK_PWM0 48 -#define CLK_PDPMU 49 -#define SCLK_32K_IOE 50 - -#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) - -/* cru-clocks indices */ - -/* cru plls */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_VPLL 5 -#define PLL_NPLL 6 - -/* cru clocks */ -#define CPLL_333M 9 -#define ARMCLK 10 -#define USB480M 11 -#define ACLK_CORE_NIU2BUS 18 -#define CLK_CORE_PVTM 19 -#define CLK_CORE_PVTM_CORE 20 -#define CLK_CORE_PVTPLL 21 -#define CLK_GPU_SRC 22 -#define CLK_GPU_PRE_NDFT 23 -#define CLK_GPU_PRE_MUX 24 -#define ACLK_GPU_PRE 25 -#define PCLK_GPU_PRE 26 -#define CLK_GPU 27 -#define CLK_GPU_NP5 28 -#define PCLK_GPU_PVTM 29 -#define CLK_GPU_PVTM 30 -#define CLK_GPU_PVTM_CORE 31 -#define CLK_GPU_PVTPLL 32 -#define CLK_NPU_SRC 33 -#define CLK_NPU_PRE_NDFT 34 -#define CLK_NPU 35 -#define CLK_NPU_NP5 36 -#define HCLK_NPU_PRE 37 -#define PCLK_NPU_PRE 38 -#define ACLK_NPU_PRE 39 -#define ACLK_NPU 40 -#define HCLK_NPU 41 -#define PCLK_NPU_PVTM 42 -#define CLK_NPU_PVTM 43 -#define CLK_NPU_PVTM_CORE 44 -#define CLK_NPU_PVTPLL 45 -#define CLK_DDRPHY1X_SRC 46 -#define CLK_DDRPHY1X_HWFFC_SRC 47 -#define CLK_DDR1X 48 -#define CLK_MSCH 49 -#define CLK24_DDRMON 50 -#define ACLK_GIC_AUDIO 51 -#define HCLK_GIC_AUDIO 52 -#define HCLK_SDMMC_BUFFER 53 -#define DCLK_SDMMC_BUFFER 54 -#define ACLK_GIC600 55 -#define ACLK_SPINLOCK 56 -#define HCLK_I2S0_8CH 57 -#define HCLK_I2S1_8CH 58 -#define HCLK_I2S2_2CH 59 -#define HCLK_I2S3_2CH 60 -#define CLK_I2S0_8CH_TX_SRC 61 -#define CLK_I2S0_8CH_TX_FRAC 62 -#define MCLK_I2S0_8CH_TX 63 -#define I2S0_MCLKOUT_TX 64 -#define CLK_I2S0_8CH_RX_SRC 65 -#define CLK_I2S0_8CH_RX_FRAC 66 -#define MCLK_I2S0_8CH_RX 67 -#define I2S0_MCLKOUT_RX 68 -#define CLK_I2S1_8CH_TX_SRC 69 -#define CLK_I2S1_8CH_TX_FRAC 70 -#define MCLK_I2S1_8CH_TX 71 -#define I2S1_MCLKOUT_TX 72 -#define CLK_I2S1_8CH_RX_SRC 73 -#define CLK_I2S1_8CH_RX_FRAC 74 -#define MCLK_I2S1_8CH_RX 75 -#define I2S1_MCLKOUT_RX 76 -#define CLK_I2S2_2CH_SRC 77 -#define CLK_I2S2_2CH_FRAC 78 -#define MCLK_I2S2_2CH 79 -#define I2S2_MCLKOUT 80 -#define CLK_I2S3_2CH_TX_SRC 81 -#define CLK_I2S3_2CH_TX_FRAC 82 -#define MCLK_I2S3_2CH_TX 83 -#define I2S3_MCLKOUT_TX 84 -#define CLK_I2S3_2CH_RX_SRC 85 -#define CLK_I2S3_2CH_RX_FRAC 86 -#define MCLK_I2S3_2CH_RX 87 -#define I2S3_MCLKOUT_RX 88 -#define HCLK_PDM 89 -#define MCLK_PDM 90 -#define HCLK_VAD 91 -#define HCLK_SPDIF_8CH 92 -#define MCLK_SPDIF_8CH_SRC 93 -#define MCLK_SPDIF_8CH_FRAC 94 -#define MCLK_SPDIF_8CH 95 -#define HCLK_AUDPWM 96 -#define SCLK_AUDPWM_SRC 97 -#define SCLK_AUDPWM_FRAC 98 -#define SCLK_AUDPWM 99 -#define HCLK_ACDCDIG 100 -#define CLK_ACDCDIG_I2C 101 -#define CLK_ACDCDIG_DAC 102 -#define CLK_ACDCDIG_ADC 103 -#define ACLK_SECURE_FLASH 104 -#define HCLK_SECURE_FLASH 105 -#define ACLK_CRYPTO_NS 106 -#define HCLK_CRYPTO_NS 107 -#define CLK_CRYPTO_NS_CORE 108 -#define CLK_CRYPTO_NS_PKA 109 -#define CLK_CRYPTO_NS_RNG 110 -#define HCLK_TRNG_NS 111 -#define CLK_TRNG_NS 112 -#define PCLK_OTPC_NS 113 -#define CLK_OTPC_NS_SBPI 114 -#define CLK_OTPC_NS_USR 115 -#define HCLK_NANDC 116 -#define NCLK_NANDC 117 -#define HCLK_SFC 118 -#define HCLK_SFC_XIP 119 -#define SCLK_SFC 120 -#define ACLK_EMMC 121 -#define HCLK_EMMC 122 -#define BCLK_EMMC 123 -#define CCLK_EMMC 124 -#define TCLK_EMMC 125 -#define ACLK_PIPE 126 -#define PCLK_PIPE 127 -#define PCLK_PIPE_GRF 128 -#define ACLK_PCIE20_MST 129 -#define ACLK_PCIE20_SLV 130 -#define ACLK_PCIE20_DBI 131 -#define PCLK_PCIE20 132 -#define CLK_PCIE20_AUX_NDFT 133 -#define CLK_PCIE20_AUX_DFT 134 -#define CLK_PCIE20_PIPE_DFT 135 -#define ACLK_PCIE30X1_MST 136 -#define ACLK_PCIE30X1_SLV 137 -#define ACLK_PCIE30X1_DBI 138 -#define PCLK_PCIE30X1 139 -#define CLK_PCIE30X1_AUX_NDFT 140 -#define CLK_PCIE30X1_AUX_DFT 141 -#define CLK_PCIE30X1_PIPE_DFT 142 -#define ACLK_PCIE30X2_MST 143 -#define ACLK_PCIE30X2_SLV 144 -#define ACLK_PCIE30X2_DBI 145 -#define PCLK_PCIE30X2 146 -#define CLK_PCIE30X2_AUX_NDFT 147 -#define CLK_PCIE30X2_AUX_DFT 148 -#define CLK_PCIE30X2_PIPE_DFT 149 -#define ACLK_SATA0 150 -#define CLK_SATA0_PMALIVE 151 -#define CLK_SATA0_RXOOB 152 -#define CLK_SATA0_PIPE_NDFT 153 -#define CLK_SATA0_PIPE_DFT 154 -#define ACLK_SATA1 155 -#define CLK_SATA1_PMALIVE 156 -#define CLK_SATA1_RXOOB 157 -#define CLK_SATA1_PIPE_NDFT 158 -#define CLK_SATA1_PIPE_DFT 159 -#define ACLK_SATA2 160 -#define CLK_SATA2_PMALIVE 161 -#define CLK_SATA2_RXOOB 162 -#define CLK_SATA2_PIPE_NDFT 163 -#define CLK_SATA2_PIPE_DFT 164 -#define ACLK_USB3OTG0 165 -#define CLK_USB3OTG0_REF 166 -#define CLK_USB3OTG0_SUSPEND 167 -#define ACLK_USB3OTG1 168 -#define CLK_USB3OTG1_REF 169 -#define CLK_USB3OTG1_SUSPEND 170 -#define CLK_XPCS_EEE 171 -#define PCLK_XPCS 172 -#define ACLK_PHP 173 -#define HCLK_PHP 174 -#define PCLK_PHP 175 -#define HCLK_SDMMC0 176 -#define CLK_SDMMC0 177 -#define HCLK_SDMMC1 178 -#define CLK_SDMMC1 179 -#define ACLK_GMAC0 180 -#define PCLK_GMAC0 181 -#define CLK_MAC0_2TOP 182 -#define CLK_MAC0_OUT 183 -#define CLK_MAC0_REFOUT 184 -#define CLK_GMAC0_PTP_REF 185 -#define ACLK_USB 186 -#define HCLK_USB 187 -#define PCLK_USB 188 -#define HCLK_USB2HOST0 189 -#define HCLK_USB2HOST0_ARB 190 -#define HCLK_USB2HOST1 191 -#define HCLK_USB2HOST1_ARB 192 -#define HCLK_SDMMC2 193 -#define CLK_SDMMC2 194 -#define ACLK_GMAC1 195 -#define PCLK_GMAC1 196 -#define CLK_MAC1_2TOP 197 -#define CLK_MAC1_OUT 198 -#define CLK_MAC1_REFOUT 199 -#define CLK_GMAC1_PTP_REF 200 -#define ACLK_PERIMID 201 -#define HCLK_PERIMID 202 -#define ACLK_VI 203 -#define HCLK_VI 204 -#define PCLK_VI 205 -#define ACLK_VICAP 206 -#define HCLK_VICAP 207 -#define DCLK_VICAP 208 -#define ICLK_VICAP_G 209 -#define ACLK_ISP 210 -#define HCLK_ISP 211 -#define CLK_ISP 212 -#define PCLK_CSI2HOST1 213 -#define CLK_CIF_OUT 214 -#define CLK_CAM0_OUT 215 -#define CLK_CAM1_OUT 216 -#define ACLK_VO 217 -#define HCLK_VO 218 -#define PCLK_VO 219 -#define ACLK_VOP_PRE 220 -#define ACLK_VOP 221 -#define HCLK_VOP 222 -#define DCLK_VOP0 223 -#define DCLK_VOP1 224 -#define DCLK_VOP2 225 -#define CLK_VOP_PWM 226 -#define ACLK_HDCP 227 -#define HCLK_HDCP 228 -#define PCLK_HDCP 229 -#define PCLK_HDMI_HOST 230 -#define CLK_HDMI_SFR 231 -#define PCLK_DSITX_0 232 -#define PCLK_DSITX_1 233 -#define PCLK_EDP_CTRL 234 -#define CLK_EDP_200M 235 -#define ACLK_VPU_PRE 236 -#define HCLK_VPU_PRE 237 -#define ACLK_VPU 238 -#define HCLK_VPU 239 -#define ACLK_RGA_PRE 240 -#define HCLK_RGA_PRE 241 -#define PCLK_RGA_PRE 242 -#define ACLK_RGA 243 -#define HCLK_RGA 244 -#define CLK_RGA_CORE 245 -#define ACLK_IEP 246 -#define HCLK_IEP 247 -#define CLK_IEP_CORE 248 -#define HCLK_EBC 249 -#define DCLK_EBC 250 -#define ACLK_JDEC 251 -#define HCLK_JDEC 252 -#define ACLK_JENC 253 -#define HCLK_JENC 254 -#define PCLK_EINK 255 -#define HCLK_EINK 256 -#define ACLK_RKVENC_PRE 257 -#define HCLK_RKVENC_PRE 258 -#define ACLK_RKVENC 259 -#define HCLK_RKVENC 260 -#define CLK_RKVENC_CORE 261 -#define ACLK_RKVDEC_PRE 262 -#define HCLK_RKVDEC_PRE 263 -#define ACLK_RKVDEC 264 -#define HCLK_RKVDEC 265 -#define CLK_RKVDEC_CA 266 -#define CLK_RKVDEC_CORE 267 -#define CLK_RKVDEC_HEVC_CA 268 -#define ACLK_BUS 269 -#define PCLK_BUS 270 -#define PCLK_TSADC 271 -#define CLK_TSADC_TSEN 272 -#define CLK_TSADC 273 -#define PCLK_SARADC 274 -#define CLK_SARADC 275 -#define PCLK_SCR 276 -#define PCLK_WDT_NS 277 -#define TCLK_WDT_NS 278 -#define ACLK_DMAC0 279 -#define ACLK_DMAC1 280 -#define ACLK_MCU 281 -#define PCLK_INTMUX 282 -#define PCLK_MAILBOX 283 -#define PCLK_UART1 284 -#define CLK_UART1_SRC 285 -#define CLK_UART1_FRAC 286 -#define SCLK_UART1 287 -#define PCLK_UART2 288 -#define CLK_UART2_SRC 289 -#define CLK_UART2_FRAC 290 -#define SCLK_UART2 291 -#define PCLK_UART3 292 -#define CLK_UART3_SRC 293 -#define CLK_UART3_FRAC 294 -#define SCLK_UART3 295 -#define PCLK_UART4 296 -#define CLK_UART4_SRC 297 -#define CLK_UART4_FRAC 298 -#define SCLK_UART4 299 -#define PCLK_UART5 300 -#define CLK_UART5_SRC 301 -#define CLK_UART5_FRAC 302 -#define SCLK_UART5 303 -#define PCLK_UART6 304 -#define CLK_UART6_SRC 305 -#define CLK_UART6_FRAC 306 -#define SCLK_UART6 307 -#define PCLK_UART7 308 -#define CLK_UART7_SRC 309 -#define CLK_UART7_FRAC 310 -#define SCLK_UART7 311 -#define PCLK_UART8 312 -#define CLK_UART8_SRC 313 -#define CLK_UART8_FRAC 314 -#define SCLK_UART8 315 -#define PCLK_UART9 316 -#define CLK_UART9_SRC 317 -#define CLK_UART9_FRAC 318 -#define SCLK_UART9 319 -#define PCLK_CAN0 320 -#define CLK_CAN0 321 -#define PCLK_CAN1 322 -#define CLK_CAN1 323 -#define PCLK_CAN2 324 -#define CLK_CAN2 325 -#define CLK_I2C 326 -#define PCLK_I2C1 327 -#define CLK_I2C1 328 -#define PCLK_I2C2 329 -#define CLK_I2C2 330 -#define PCLK_I2C3 331 -#define CLK_I2C3 332 -#define PCLK_I2C4 333 -#define CLK_I2C4 334 -#define PCLK_I2C5 335 -#define CLK_I2C5 336 -#define PCLK_SPI0 337 -#define CLK_SPI0 338 -#define PCLK_SPI1 339 -#define CLK_SPI1 340 -#define PCLK_SPI2 341 -#define CLK_SPI2 342 -#define PCLK_SPI3 343 -#define CLK_SPI3 344 -#define PCLK_PWM1 345 -#define CLK_PWM1 346 -#define CLK_PWM1_CAPTURE 347 -#define PCLK_PWM2 348 -#define CLK_PWM2 349 -#define CLK_PWM2_CAPTURE 350 -#define PCLK_PWM3 351 -#define CLK_PWM3 352 -#define CLK_PWM3_CAPTURE 353 -#define DBCLK_GPIO 354 -#define PCLK_GPIO1 355 -#define DBCLK_GPIO1 356 -#define PCLK_GPIO2 357 -#define DBCLK_GPIO2 358 -#define PCLK_GPIO3 359 -#define DBCLK_GPIO3 360 -#define PCLK_GPIO4 361 -#define DBCLK_GPIO4 362 -#define OCC_SCAN_CLK_GPIO 363 -#define PCLK_TIMER 364 -#define CLK_TIMER0 365 -#define CLK_TIMER1 366 -#define CLK_TIMER2 367 -#define CLK_TIMER3 368 -#define CLK_TIMER4 369 -#define CLK_TIMER5 370 -#define ACLK_TOP_HIGH 371 -#define ACLK_TOP_LOW 372 -#define HCLK_TOP 373 -#define PCLK_TOP 374 -#define PCLK_PCIE30PHY 375 -#define CLK_OPTC_ARB 376 -#define PCLK_MIPICSIPHY 377 -#define PCLK_MIPIDSIPHY0 378 -#define PCLK_MIPIDSIPHY1 379 -#define PCLK_PIPEPHY0 380 -#define PCLK_PIPEPHY1 381 -#define PCLK_PIPEPHY2 382 -#define PCLK_CPU_BOOST 383 -#define CLK_CPU_BOOST 384 -#define PCLK_OTPPHY 385 -#define SCLK_GMAC0 386 -#define SCLK_GMAC0_RGMII_SPEED 387 -#define SCLK_GMAC0_RMII_SPEED 388 -#define SCLK_GMAC0_RX_TX 389 -#define SCLK_GMAC1 390 -#define SCLK_GMAC1_RGMII_SPEED 391 -#define SCLK_GMAC1_RMII_SPEED 392 -#define SCLK_GMAC1_RX_TX 393 -#define SCLK_SDMMC0_DRV 394 -#define SCLK_SDMMC0_SAMPLE 395 -#define SCLK_SDMMC1_DRV 396 -#define SCLK_SDMMC1_SAMPLE 397 -#define SCLK_SDMMC2_DRV 398 -#define SCLK_SDMMC2_SAMPLE 399 -#define SCLK_EMMC_DRV 400 -#define SCLK_EMMC_SAMPLE 401 -#define PCLK_EDPPHY_GRF 402 -#define CLK_HDMI_CEC 403 -#define CLK_I2S0_8CH_TX 404 -#define CLK_I2S0_8CH_RX 405 -#define CLK_I2S1_8CH_TX 406 -#define CLK_I2S1_8CH_RX 407 -#define CLK_I2S2_2CH 408 -#define CLK_I2S3_2CH_TX 409 -#define CLK_I2S3_2CH_RX 410 -#define CPLL_500M 411 -#define CPLL_250M 412 -#define CPLL_125M 413 -#define CPLL_62P5M 414 -#define CPLL_50M 415 -#define CPLL_25M 416 -#define CPLL_100M 417 -#define SCLK_DDRCLK 418 - -#define PCLK_CORE_PVTM 450 - -#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) - -/* pmu soft-reset indices */ -/* pmucru_softrst_con0 */ -#define SRST_P_PDPMU_NIU 0 -#define SRST_P_PMUCRU 1 -#define SRST_P_PMUGRF 2 -#define SRST_P_I2C0 3 -#define SRST_I2C0 4 -#define SRST_P_UART0 5 -#define SRST_S_UART0 6 -#define SRST_P_PWM0 7 -#define SRST_PWM0 8 -#define SRST_P_GPIO0 9 -#define SRST_GPIO0 10 -#define SRST_P_PMUPVTM 11 -#define SRST_PMUPVTM 12 - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_NCORERESET0 0 -#define SRST_NCORERESET1 1 -#define SRST_NCORERESET2 2 -#define SRST_NCORERESET3 3 -#define SRST_NCPUPORESET0 4 -#define SRST_NCPUPORESET1 5 -#define SRST_NCPUPORESET2 6 -#define SRST_NCPUPORESET3 7 -#define SRST_NSRESET 8 -#define SRST_NSPORESET 9 -#define SRST_NATRESET 10 -#define SRST_NGICRESET 11 -#define SRST_NPRESET 12 -#define SRST_NPERIPHRESET 13 - -/* cru_softrst_con1 */ -#define SRST_A_CORE_NIU2DDR 16 -#define SRST_A_CORE_NIU2BUS 17 -#define SRST_P_DBG_NIU 18 -#define SRST_P_DBG 19 -#define SRST_P_DBG_DAPLITE 20 -#define SRST_DAP 21 -#define SRST_A_ADB400_CORE2GIC 22 -#define SRST_A_ADB400_GIC2CORE 23 -#define SRST_P_CORE_GRF 24 -#define SRST_P_CORE_PVTM 25 -#define SRST_CORE_PVTM 26 -#define SRST_CORE_PVTPLL 27 - -/* cru_softrst_con2 */ -#define SRST_GPU 32 -#define SRST_A_GPU_NIU 33 -#define SRST_P_GPU_NIU 34 -#define SRST_P_GPU_PVTM 35 -#define SRST_GPU_PVTM 36 -#define SRST_GPU_PVTPLL 37 -#define SRST_A_NPU_NIU 40 -#define SRST_H_NPU_NIU 41 -#define SRST_P_NPU_NIU 42 -#define SRST_A_NPU 43 -#define SRST_H_NPU 44 -#define SRST_P_NPU_PVTM 45 -#define SRST_NPU_PVTM 46 -#define SRST_NPU_PVTPLL 47 - -/* cru_softrst_con3 */ -#define SRST_A_MSCH 51 -#define SRST_HWFFC_CTRL 52 -#define SRST_DDR_ALWAYSON 53 -#define SRST_A_DDRSPLIT 54 -#define SRST_DDRDFI_CTL 55 -#define SRST_A_DMA2DDR 57 - -/* cru_softrst_con4 */ -#define SRST_A_PERIMID_NIU 64 -#define SRST_H_PERIMID_NIU 65 -#define SRST_A_GIC_AUDIO_NIU 66 -#define SRST_H_GIC_AUDIO_NIU 67 -#define SRST_A_GIC600 68 -#define SRST_A_GIC600_DEBUG 69 -#define SRST_A_GICADB_CORE2GIC 70 -#define SRST_A_GICADB_GIC2CORE 71 -#define SRST_A_SPINLOCK 72 -#define SRST_H_SDMMC_BUFFER 73 -#define SRST_D_SDMMC_BUFFER 74 -#define SRST_H_I2S0_8CH 75 -#define SRST_H_I2S1_8CH 76 -#define SRST_H_I2S2_2CH 77 -#define SRST_H_I2S3_2CH 78 - -/* cru_softrst_con5 */ -#define SRST_M_I2S0_8CH_TX 80 -#define SRST_M_I2S0_8CH_RX 81 -#define SRST_M_I2S1_8CH_TX 82 -#define SRST_M_I2S1_8CH_RX 83 -#define SRST_M_I2S2_2CH 84 -#define SRST_M_I2S3_2CH_TX 85 -#define SRST_M_I2S3_2CH_RX 86 -#define SRST_H_PDM 87 -#define SRST_M_PDM 88 -#define SRST_H_VAD 89 -#define SRST_H_SPDIF_8CH 90 -#define SRST_M_SPDIF_8CH 91 -#define SRST_H_AUDPWM 92 -#define SRST_S_AUDPWM 93 -#define SRST_H_ACDCDIG 94 -#define SRST_ACDCDIG 95 - -/* cru_softrst_con6 */ -#define SRST_A_SECURE_FLASH_NIU 96 -#define SRST_H_SECURE_FLASH_NIU 97 -#define SRST_A_CRYPTO_NS 103 -#define SRST_H_CRYPTO_NS 104 -#define SRST_CRYPTO_NS_CORE 105 -#define SRST_CRYPTO_NS_PKA 106 -#define SRST_CRYPTO_NS_RNG 107 -#define SRST_H_TRNG_NS 108 -#define SRST_TRNG_NS 109 - -/* cru_softrst_con7 */ -#define SRST_H_NANDC 112 -#define SRST_N_NANDC 113 -#define SRST_H_SFC 114 -#define SRST_H_SFC_XIP 115 -#define SRST_S_SFC 116 -#define SRST_A_EMMC 117 -#define SRST_H_EMMC 118 -#define SRST_B_EMMC 119 -#define SRST_C_EMMC 120 -#define SRST_T_EMMC 121 - -/* cru_softrst_con8 */ -#define SRST_A_PIPE_NIU 128 -#define SRST_P_PIPE_NIU 130 -#define SRST_P_PIPE_GRF 133 -#define SRST_A_SATA0 134 -#define SRST_SATA0_PIPE 135 -#define SRST_SATA0_PMALIVE 136 -#define SRST_SATA0_RXOOB 137 -#define SRST_A_SATA1 138 -#define SRST_SATA1_PIPE 139 -#define SRST_SATA1_PMALIVE 140 -#define SRST_SATA1_RXOOB 141 - -/* cru_softrst_con9 */ -#define SRST_A_SATA2 144 -#define SRST_SATA2_PIPE 145 -#define SRST_SATA2_PMALIVE 146 -#define SRST_SATA2_RXOOB 147 -#define SRST_USB3OTG0 148 -#define SRST_USB3OTG1 149 -#define SRST_XPCS 150 -#define SRST_XPCS_TX_DIV10 151 -#define SRST_XPCS_RX_DIV10 152 -#define SRST_XPCS_XGXS_RX 153 - -/* cru_softrst_con10 */ -#define SRST_P_PCIE20 160 -#define SRST_PCIE20_POWERUP 161 -#define SRST_MSTR_ARESET_PCIE20 162 -#define SRST_SLV_ARESET_PCIE20 163 -#define SRST_DBI_ARESET_PCIE20 164 -#define SRST_BRESET_PCIE20 165 -#define SRST_PERST_PCIE20 166 -#define SRST_CORE_RST_PCIE20 167 -#define SRST_NSTICKY_RST_PCIE20 168 -#define SRST_STICKY_RST_PCIE20 169 -#define SRST_PWR_RST_PCIE20 170 - -/* cru_softrst_con11 */ -#define SRST_P_PCIE30X1 176 -#define SRST_PCIE30X1_POWERUP 177 -#define SRST_M_ARESET_PCIE30X1 178 -#define SRST_S_ARESET_PCIE30X1 179 -#define SRST_D_ARESET_PCIE30X1 180 -#define SRST_BRESET_PCIE30X1 181 -#define SRST_PERST_PCIE30X1 182 -#define SRST_CORE_RST_PCIE30X1 183 -#define SRST_NSTC_RST_PCIE30X1 184 -#define SRST_STC_RST_PCIE30X1 185 -#define SRST_PWR_RST_PCIE30X1 186 - -/* cru_softrst_con12 */ -#define SRST_P_PCIE30X2 192 -#define SRST_PCIE30X2_POWERUP 193 -#define SRST_M_ARESET_PCIE30X2 194 -#define SRST_S_ARESET_PCIE30X2 195 -#define SRST_D_ARESET_PCIE30X2 196 -#define SRST_BRESET_PCIE30X2 197 -#define SRST_PERST_PCIE30X2 198 -#define SRST_CORE_RST_PCIE30X2 199 -#define SRST_NSTC_RST_PCIE30X2 200 -#define SRST_STC_RST_PCIE30X2 201 -#define SRST_PWR_RST_PCIE30X2 202 - -/* cru_softrst_con13 */ -#define SRST_A_PHP_NIU 208 -#define SRST_H_PHP_NIU 209 -#define SRST_P_PHP_NIU 210 -#define SRST_H_SDMMC0 211 -#define SRST_SDMMC0 212 -#define SRST_H_SDMMC1 213 -#define SRST_SDMMC1 214 -#define SRST_A_GMAC0 215 -#define SRST_GMAC0_TIMESTAMP 216 - -/* cru_softrst_con14 */ -#define SRST_A_USB_NIU 224 -#define SRST_H_USB_NIU 225 -#define SRST_P_USB_NIU 226 -#define SRST_P_USB_GRF 227 -#define SRST_H_USB2HOST0 228 -#define SRST_H_USB2HOST0_ARB 229 -#define SRST_USB2HOST0_UTMI 230 -#define SRST_H_USB2HOST1 231 -#define SRST_H_USB2HOST1_ARB 232 -#define SRST_USB2HOST1_UTMI 233 -#define SRST_H_SDMMC2 234 -#define SRST_SDMMC2 235 -#define SRST_A_GMAC1 236 -#define SRST_GMAC1_TIMESTAMP 237 - -/* cru_softrst_con15 */ -#define SRST_A_VI_NIU 240 -#define SRST_H_VI_NIU 241 -#define SRST_P_VI_NIU 242 -#define SRST_A_VICAP 247 -#define SRST_H_VICAP 248 -#define SRST_D_VICAP 249 -#define SRST_I_VICAP 250 -#define SRST_P_VICAP 251 -#define SRST_H_ISP 252 -#define SRST_ISP 253 -#define SRST_P_CSI2HOST1 255 - -/* cru_softrst_con16 */ -#define SRST_A_VO_NIU 256 -#define SRST_H_VO_NIU 257 -#define SRST_P_VO_NIU 258 -#define SRST_A_VOP_NIU 259 -#define SRST_A_VOP 260 -#define SRST_H_VOP 261 -#define SRST_VOP0 262 -#define SRST_VOP1 263 -#define SRST_VOP2 264 -#define SRST_VOP_PWM 265 -#define SRST_A_HDCP 266 -#define SRST_H_HDCP 267 -#define SRST_P_HDCP 268 -#define SRST_P_HDMI_HOST 270 -#define SRST_HDMI_HOST 271 - -/* cru_softrst_con17 */ -#define SRST_P_DSITX_0 272 -#define SRST_P_DSITX_1 273 -#define SRST_P_EDP_CTRL 274 -#define SRST_EDP_24M 275 -#define SRST_A_VPU_NIU 280 -#define SRST_H_VPU_NIU 281 -#define SRST_A_VPU 282 -#define SRST_H_VPU 283 -#define SRST_H_EINK 286 -#define SRST_P_EINK 287 - -/* cru_softrst_con18 */ -#define SRST_A_RGA_NIU 288 -#define SRST_H_RGA_NIU 289 -#define SRST_P_RGA_NIU 290 -#define SRST_A_RGA 292 -#define SRST_H_RGA 293 -#define SRST_RGA_CORE 294 -#define SRST_A_IEP 295 -#define SRST_H_IEP 296 -#define SRST_IEP_CORE 297 -#define SRST_H_EBC 298 -#define SRST_D_EBC 299 -#define SRST_A_JDEC 300 -#define SRST_H_JDEC 301 -#define SRST_A_JENC 302 -#define SRST_H_JENC 303 - -/* cru_softrst_con19 */ -#define SRST_A_VENC_NIU 304 -#define SRST_H_VENC_NIU 305 -#define SRST_A_RKVENC 307 -#define SRST_H_RKVENC 308 -#define SRST_RKVENC_CORE 309 - -/* cru_softrst_con20 */ -#define SRST_A_RKVDEC_NIU 320 -#define SRST_H_RKVDEC_NIU 321 -#define SRST_A_RKVDEC 322 -#define SRST_H_RKVDEC 323 -#define SRST_RKVDEC_CA 324 -#define SRST_RKVDEC_CORE 325 -#define SRST_RKVDEC_HEVC_CA 326 - -/* cru_softrst_con21 */ -#define SRST_A_BUS_NIU 336 -#define SRST_P_BUS_NIU 338 -#define SRST_P_CAN0 340 -#define SRST_CAN0 341 -#define SRST_P_CAN1 342 -#define SRST_CAN1 343 -#define SRST_P_CAN2 344 -#define SRST_CAN2 345 -#define SRST_P_GPIO1 346 -#define SRST_GPIO1 347 -#define SRST_P_GPIO2 348 -#define SRST_GPIO2 349 -#define SRST_P_GPIO3 350 -#define SRST_GPIO3 351 - -/* cru_softrst_con22 */ -#define SRST_P_GPIO4 352 -#define SRST_GPIO4 353 -#define SRST_P_I2C1 354 -#define SRST_I2C1 355 -#define SRST_P_I2C2 356 -#define SRST_I2C2 357 -#define SRST_P_I2C3 358 -#define SRST_I2C3 359 -#define SRST_P_I2C4 360 -#define SRST_I2C4 361 -#define SRST_P_I2C5 362 -#define SRST_I2C5 363 -#define SRST_P_OTPC_NS 364 -#define SRST_OTPC_NS_SBPI 365 -#define SRST_OTPC_NS_USR 366 - -/* cru_softrst_con23 */ -#define SRST_P_PWM1 368 -#define SRST_PWM1 369 -#define SRST_P_PWM2 370 -#define SRST_PWM2 371 -#define SRST_P_PWM3 372 -#define SRST_PWM3 373 -#define SRST_P_SPI0 374 -#define SRST_SPI0 375 -#define SRST_P_SPI1 376 -#define SRST_SPI1 377 -#define SRST_P_SPI2 378 -#define SRST_SPI2 379 -#define SRST_P_SPI3 380 -#define SRST_SPI3 381 - -/* cru_softrst_con24 */ -#define SRST_P_SARADC 384 -#define SRST_P_TSADC 385 -#define SRST_TSADC 386 -#define SRST_P_TIMER 387 -#define SRST_TIMER0 388 -#define SRST_TIMER1 389 -#define SRST_TIMER2 390 -#define SRST_TIMER3 391 -#define SRST_TIMER4 392 -#define SRST_TIMER5 393 -#define SRST_P_UART1 394 -#define SRST_S_UART1 395 - -/* cru_softrst_con25 */ -#define SRST_P_UART2 400 -#define SRST_S_UART2 401 -#define SRST_P_UART3 402 -#define SRST_S_UART3 403 -#define SRST_P_UART4 404 -#define SRST_S_UART4 405 -#define SRST_P_UART5 406 -#define SRST_S_UART5 407 -#define SRST_P_UART6 408 -#define SRST_S_UART6 409 -#define SRST_P_UART7 410 -#define SRST_S_UART7 411 -#define SRST_P_UART8 412 -#define SRST_S_UART8 413 -#define SRST_P_UART9 414 -#define SRST_S_UART9 415 - -/* cru_softrst_con26 */ -#define SRST_P_GRF 416 -#define SRST_P_GRF_VCCIO12 417 -#define SRST_P_GRF_VCCIO34 418 -#define SRST_P_GRF_VCCIO567 419 -#define SRST_P_SCR 420 -#define SRST_P_WDT_NS 421 -#define SRST_T_WDT_NS 422 -#define SRST_P_DFT2APB 423 -#define SRST_A_MCU 426 -#define SRST_P_INTMUX 427 -#define SRST_P_MAILBOX 428 - -/* cru_softrst_con27 */ -#define SRST_A_TOP_HIGH_NIU 432 -#define SRST_A_TOP_LOW_NIU 433 -#define SRST_H_TOP_NIU 434 -#define SRST_P_TOP_NIU 435 -#define SRST_P_TOP_CRU 438 -#define SRST_P_DDRPHY 439 -#define SRST_DDRPHY 440 -#define SRST_P_MIPICSIPHY 442 -#define SRST_P_MIPIDSIPHY0 443 -#define SRST_P_MIPIDSIPHY1 444 -#define SRST_P_PCIE30PHY 445 -#define SRST_PCIE30PHY 446 -#define SRST_P_PCIE30PHY_GRF 447 - -/* cru_softrst_con28 */ -#define SRST_P_APB2ASB_LEFT 448 -#define SRST_P_APB2ASB_BOTTOM 449 -#define SRST_P_ASB2APB_LEFT 450 -#define SRST_P_ASB2APB_BOTTOM 451 -#define SRST_P_PIPEPHY0 452 -#define SRST_PIPEPHY0 453 -#define SRST_P_PIPEPHY1 454 -#define SRST_PIPEPHY1 455 -#define SRST_P_PIPEPHY2 456 -#define SRST_PIPEPHY2 457 -#define SRST_P_USB2PHY0_GRF 458 -#define SRST_P_USB2PHY1_GRF 459 -#define SRST_P_CPU_BOOST 460 -#define SRST_CPU_BOOST 461 -#define SRST_P_OTPPHY 462 -#define SRST_OTPPHY 463 - -/* cru_softrst_con29 */ -#define SRST_USB2PHY0_POR 464 -#define SRST_USB2PHY0_USB3OTG0 465 -#define SRST_USB2PHY0_USB3OTG1 466 -#define SRST_USB2PHY1_POR 467 -#define SRST_USB2PHY1_USB2HOST0 468 -#define SRST_USB2PHY1_USB2HOST1 469 -#define SRST_P_EDPPHY_GRF 470 -#define SRST_TSADCPHY 471 -#define SRST_GMAC0_DELAYLINE 472 -#define SRST_GMAC1_DELAYLINE 473 -#define SRST_OTPC_ARB 474 -#define SRST_P_PIPEPHY0_GRF 475 -#define SRST_P_PIPEPHY1_GRF 476 -#define SRST_P_PIPEPHY2_GRF 477 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h deleted file mode 100644 index b5616bca7b449b51946b3f7b83a888126831de47..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ /dev/null @@ -1,766 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang - * Author: Sebastian Reichel - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H - -/* cru-clocks indices */ - -#define PLL_B0PLL 0 -#define PLL_B1PLL 1 -#define PLL_LPLL 2 -#define PLL_V0PLL 3 -#define PLL_AUPLL 4 -#define PLL_CPLL 5 -#define PLL_GPLL 6 -#define PLL_NPLL 7 -#define PLL_PPLL 8 -#define ARMCLK_L 9 -#define ARMCLK_B01 10 -#define ARMCLK_B23 11 -#define PCLK_BIGCORE0_ROOT 12 -#define PCLK_BIGCORE0_PVTM 13 -#define PCLK_BIGCORE1_ROOT 14 -#define PCLK_BIGCORE1_PVTM 15 -#define PCLK_DSU_S_ROOT 16 -#define PCLK_DSU_ROOT 17 -#define PCLK_DSU_NS_ROOT 18 -#define PCLK_LITCORE_PVTM 19 -#define PCLK_DBG 20 -#define PCLK_DSU 21 -#define PCLK_S_DAPLITE 22 -#define PCLK_M_DAPLITE 23 -#define MBIST_MCLK_PDM1 24 -#define MBIST_CLK_ACDCDIG 25 -#define HCLK_I2S2_2CH 26 -#define HCLK_I2S3_2CH 27 -#define CLK_I2S2_2CH_SRC 28 -#define CLK_I2S2_2CH_FRAC 29 -#define CLK_I2S2_2CH 30 -#define MCLK_I2S2_2CH 31 -#define I2S2_2CH_MCLKOUT 32 -#define CLK_DAC_ACDCDIG 33 -#define CLK_I2S3_2CH_SRC 34 -#define CLK_I2S3_2CH_FRAC 35 -#define CLK_I2S3_2CH 36 -#define MCLK_I2S3_2CH 37 -#define I2S3_2CH_MCLKOUT 38 -#define PCLK_ACDCDIG 39 -#define HCLK_I2S0_8CH 40 -#define CLK_I2S0_8CH_TX_SRC 41 -#define CLK_I2S0_8CH_TX_FRAC 42 -#define MCLK_I2S0_8CH_TX 43 -#define CLK_I2S0_8CH_TX 44 -#define CLK_I2S0_8CH_RX_SRC 45 -#define CLK_I2S0_8CH_RX_FRAC 46 -#define MCLK_I2S0_8CH_RX 47 -#define CLK_I2S0_8CH_RX 48 -#define I2S0_8CH_MCLKOUT 49 -#define HCLK_PDM1 50 -#define MCLK_PDM1 51 -#define HCLK_AUDIO_ROOT 52 -#define PCLK_AUDIO_ROOT 53 -#define HCLK_SPDIF0 54 -#define CLK_SPDIF0_SRC 55 -#define CLK_SPDIF0_FRAC 56 -#define MCLK_SPDIF0 57 -#define CLK_SPDIF0 58 -#define CLK_SPDIF1 59 -#define HCLK_SPDIF1 60 -#define CLK_SPDIF1_SRC 61 -#define CLK_SPDIF1_FRAC 62 -#define MCLK_SPDIF1 63 -#define ACLK_AV1_ROOT 64 -#define ACLK_AV1 65 -#define PCLK_AV1_ROOT 66 -#define PCLK_AV1 67 -#define PCLK_MAILBOX0 68 -#define PCLK_MAILBOX1 69 -#define PCLK_MAILBOX2 70 -#define PCLK_PMU2 71 -#define PCLK_PMUCM0_INTMUX 72 -#define PCLK_DDRCM0_INTMUX 73 -#define PCLK_TOP 74 -#define PCLK_PWM1 75 -#define CLK_PWM1 76 -#define CLK_PWM1_CAPTURE 77 -#define PCLK_PWM2 78 -#define CLK_PWM2 79 -#define CLK_PWM2_CAPTURE 80 -#define PCLK_PWM3 81 -#define CLK_PWM3 82 -#define CLK_PWM3_CAPTURE 83 -#define PCLK_BUSTIMER0 84 -#define PCLK_BUSTIMER1 85 -#define CLK_BUS_TIMER_ROOT 86 -#define CLK_BUSTIMER0 87 -#define CLK_BUSTIMER1 88 -#define CLK_BUSTIMER2 89 -#define CLK_BUSTIMER3 90 -#define CLK_BUSTIMER4 91 -#define CLK_BUSTIMER5 92 -#define CLK_BUSTIMER6 93 -#define CLK_BUSTIMER7 94 -#define CLK_BUSTIMER8 95 -#define CLK_BUSTIMER9 96 -#define CLK_BUSTIMER10 97 -#define CLK_BUSTIMER11 98 -#define PCLK_WDT0 99 -#define TCLK_WDT0 100 -#define PCLK_CAN0 101 -#define CLK_CAN0 102 -#define PCLK_CAN1 103 -#define CLK_CAN1 104 -#define PCLK_CAN2 105 -#define CLK_CAN2 106 -#define ACLK_DECOM 107 -#define PCLK_DECOM 108 -#define DCLK_DECOM 109 -#define ACLK_DMAC0 110 -#define ACLK_DMAC1 111 -#define ACLK_DMAC2 112 -#define ACLK_BUS_ROOT 113 -#define ACLK_GIC 114 -#define PCLK_GPIO1 115 -#define DBCLK_GPIO1 116 -#define PCLK_GPIO2 117 -#define DBCLK_GPIO2 118 -#define PCLK_GPIO3 119 -#define DBCLK_GPIO3 120 -#define PCLK_GPIO4 121 -#define DBCLK_GPIO4 122 -#define PCLK_I2C1 123 -#define PCLK_I2C2 124 -#define PCLK_I2C3 125 -#define PCLK_I2C4 126 -#define PCLK_I2C5 127 -#define PCLK_I2C6 128 -#define PCLK_I2C7 129 -#define PCLK_I2C8 130 -#define CLK_I2C1 131 -#define CLK_I2C2 132 -#define CLK_I2C3 133 -#define CLK_I2C4 134 -#define CLK_I2C5 135 -#define CLK_I2C6 136 -#define CLK_I2C7 137 -#define CLK_I2C8 138 -#define PCLK_OTPC_NS 139 -#define CLK_OTPC_NS 140 -#define CLK_OTPC_ARB 141 -#define CLK_OTPC_AUTO_RD_G 142 -#define CLK_OTP_PHY_G 143 -#define PCLK_SARADC 144 -#define CLK_SARADC 145 -#define PCLK_SPI0 146 -#define PCLK_SPI1 147 -#define PCLK_SPI2 148 -#define PCLK_SPI3 149 -#define PCLK_SPI4 150 -#define CLK_SPI0 151 -#define CLK_SPI1 152 -#define CLK_SPI2 153 -#define CLK_SPI3 154 -#define CLK_SPI4 155 -#define ACLK_SPINLOCK 156 -#define PCLK_TSADC 157 -#define CLK_TSADC 158 -#define PCLK_UART1 159 -#define PCLK_UART2 160 -#define PCLK_UART3 161 -#define PCLK_UART4 162 -#define PCLK_UART5 163 -#define PCLK_UART6 164 -#define PCLK_UART7 165 -#define PCLK_UART8 166 -#define PCLK_UART9 167 -#define CLK_UART1_SRC 168 -#define CLK_UART1_FRAC 169 -#define CLK_UART1 170 -#define SCLK_UART1 171 -#define CLK_UART2_SRC 172 -#define CLK_UART2_FRAC 173 -#define CLK_UART2 174 -#define SCLK_UART2 175 -#define CLK_UART3_SRC 176 -#define CLK_UART3_FRAC 177 -#define CLK_UART3 178 -#define SCLK_UART3 179 -#define CLK_UART4_SRC 180 -#define CLK_UART4_FRAC 181 -#define CLK_UART4 182 -#define SCLK_UART4 183 -#define CLK_UART5_SRC 184 -#define CLK_UART5_FRAC 185 -#define CLK_UART5 186 -#define SCLK_UART5 187 -#define CLK_UART6_SRC 188 -#define CLK_UART6_FRAC 189 -#define CLK_UART6 190 -#define SCLK_UART6 191 -#define CLK_UART7_SRC 192 -#define CLK_UART7_FRAC 193 -#define CLK_UART7 194 -#define SCLK_UART7 195 -#define CLK_UART8_SRC 196 -#define CLK_UART8_FRAC 197 -#define CLK_UART8 198 -#define SCLK_UART8 199 -#define CLK_UART9_SRC 200 -#define CLK_UART9_FRAC 201 -#define CLK_UART9 202 -#define SCLK_UART9 203 -#define ACLK_CENTER_ROOT 204 -#define ACLK_CENTER_LOW_ROOT 205 -#define HCLK_CENTER_ROOT 206 -#define PCLK_CENTER_ROOT 207 -#define ACLK_DMA2DDR 208 -#define ACLK_DDR_SHAREMEM 209 -#define ACLK_CENTER_S200_ROOT 210 -#define ACLK_CENTER_S400_ROOT 211 -#define FCLK_DDR_CM0_CORE 212 -#define CLK_DDR_TIMER_ROOT 213 -#define CLK_DDR_TIMER0 214 -#define CLK_DDR_TIMER1 215 -#define TCLK_WDT_DDR 216 -#define CLK_DDR_CM0_RTC 217 -#define PCLK_WDT 218 -#define PCLK_TIMER 219 -#define PCLK_DMA2DDR 220 -#define PCLK_SHAREMEM 221 -#define CLK_50M_SRC 222 -#define CLK_100M_SRC 223 -#define CLK_150M_SRC 224 -#define CLK_200M_SRC 225 -#define CLK_250M_SRC 226 -#define CLK_300M_SRC 227 -#define CLK_350M_SRC 228 -#define CLK_400M_SRC 229 -#define CLK_450M_SRC 230 -#define CLK_500M_SRC 231 -#define CLK_600M_SRC 232 -#define CLK_650M_SRC 233 -#define CLK_700M_SRC 234 -#define CLK_800M_SRC 235 -#define CLK_1000M_SRC 236 -#define CLK_1200M_SRC 237 -#define ACLK_TOP_M300_ROOT 238 -#define ACLK_TOP_M500_ROOT 239 -#define ACLK_TOP_M400_ROOT 240 -#define ACLK_TOP_S200_ROOT 241 -#define ACLK_TOP_S400_ROOT 242 -#define CLK_MIPI_CAMARAOUT_M0 243 -#define CLK_MIPI_CAMARAOUT_M1 244 -#define CLK_MIPI_CAMARAOUT_M2 245 -#define CLK_MIPI_CAMARAOUT_M3 246 -#define CLK_MIPI_CAMARAOUT_M4 247 -#define MCLK_GMAC0_OUT 248 -#define REFCLKO25M_ETH0_OUT 249 -#define REFCLKO25M_ETH1_OUT 250 -#define CLK_CIFOUT_OUT 251 -#define PCLK_MIPI_DCPHY0 252 -#define PCLK_MIPI_DCPHY1 253 -#define PCLK_CSIPHY0 254 -#define PCLK_CSIPHY1 255 -#define ACLK_TOP_ROOT 256 -#define PCLK_TOP_ROOT 257 -#define ACLK_LOW_TOP_ROOT 258 -#define PCLK_CRU 259 -#define PCLK_GPU_ROOT 260 -#define CLK_GPU_SRC 261 -#define CLK_GPU 262 -#define CLK_GPU_COREGROUP 263 -#define CLK_GPU_STACKS 264 -#define PCLK_GPU_PVTM 265 -#define CLK_GPU_PVTM 266 -#define CLK_CORE_GPU_PVTM 267 -#define PCLK_GPU_GRF 268 -#define ACLK_ISP1_ROOT 269 -#define HCLK_ISP1_ROOT 270 -#define CLK_ISP1_CORE 271 -#define CLK_ISP1_CORE_MARVIN 272 -#define CLK_ISP1_CORE_VICAP 273 -#define ACLK_ISP1 274 -#define HCLK_ISP1 275 -#define ACLK_NPU1 276 -#define HCLK_NPU1 277 -#define ACLK_NPU2 278 -#define HCLK_NPU2 279 -#define HCLK_NPU_CM0_ROOT 280 -#define FCLK_NPU_CM0_CORE 281 -#define CLK_NPU_CM0_RTC 282 -#define PCLK_NPU_PVTM 283 -#define PCLK_NPU_GRF 284 -#define CLK_NPU_PVTM 285 -#define CLK_CORE_NPU_PVTM 286 -#define ACLK_NPU0 287 -#define HCLK_NPU0 288 -#define HCLK_NPU_ROOT 289 -#define CLK_NPU_DSU0 290 -#define PCLK_NPU_ROOT 291 -#define PCLK_NPU_TIMER 292 -#define CLK_NPUTIMER_ROOT 293 -#define CLK_NPUTIMER0 294 -#define CLK_NPUTIMER1 295 -#define PCLK_NPU_WDT 296 -#define TCLK_NPU_WDT 297 -#define HCLK_EMMC 298 -#define ACLK_EMMC 299 -#define CCLK_EMMC 300 -#define BCLK_EMMC 301 -#define TMCLK_EMMC 302 -#define SCLK_SFC 303 -#define HCLK_SFC 304 -#define HCLK_SFC_XIP 305 -#define HCLK_NVM_ROOT 306 -#define ACLK_NVM_ROOT 307 -#define CLK_GMAC0_PTP_REF 308 -#define CLK_GMAC1_PTP_REF 309 -#define CLK_GMAC_125M 310 -#define CLK_GMAC_50M 311 -#define ACLK_PHP_GIC_ITS 312 -#define ACLK_MMU_PCIE 313 -#define ACLK_MMU_PHP 314 -#define ACLK_PCIE_4L_DBI 315 -#define ACLK_PCIE_2L_DBI 316 -#define ACLK_PCIE_1L0_DBI 317 -#define ACLK_PCIE_1L1_DBI 318 -#define ACLK_PCIE_1L2_DBI 319 -#define ACLK_PCIE_4L_MSTR 320 -#define ACLK_PCIE_2L_MSTR 321 -#define ACLK_PCIE_1L0_MSTR 322 -#define ACLK_PCIE_1L1_MSTR 323 -#define ACLK_PCIE_1L2_MSTR 324 -#define ACLK_PCIE_4L_SLV 325 -#define ACLK_PCIE_2L_SLV 326 -#define ACLK_PCIE_1L0_SLV 327 -#define ACLK_PCIE_1L1_SLV 328 -#define ACLK_PCIE_1L2_SLV 329 -#define PCLK_PCIE_4L 330 -#define PCLK_PCIE_2L 331 -#define PCLK_PCIE_1L0 332 -#define PCLK_PCIE_1L1 333 -#define PCLK_PCIE_1L2 334 -#define CLK_PCIE_AUX0 335 -#define CLK_PCIE_AUX1 336 -#define CLK_PCIE_AUX2 337 -#define CLK_PCIE_AUX3 338 -#define CLK_PCIE_AUX4 339 -#define CLK_PIPEPHY0_REF 340 -#define CLK_PIPEPHY1_REF 341 -#define CLK_PIPEPHY2_REF 342 -#define PCLK_PHP_ROOT 343 -#define PCLK_GMAC0 344 -#define PCLK_GMAC1 345 -#define ACLK_PCIE_ROOT 346 -#define ACLK_PHP_ROOT 347 -#define ACLK_PCIE_BRIDGE 348 -#define ACLK_GMAC0 349 -#define ACLK_GMAC1 350 -#define CLK_PMALIVE0 351 -#define CLK_PMALIVE1 352 -#define CLK_PMALIVE2 353 -#define ACLK_SATA0 354 -#define ACLK_SATA1 355 -#define ACLK_SATA2 356 -#define CLK_RXOOB0 357 -#define CLK_RXOOB1 358 -#define CLK_RXOOB2 359 -#define ACLK_USB3OTG2 360 -#define SUSPEND_CLK_USB3OTG2 361 -#define REF_CLK_USB3OTG2 362 -#define CLK_UTMI_OTG2 363 -#define CLK_PIPEPHY0_PIPE_G 364 -#define CLK_PIPEPHY1_PIPE_G 365 -#define CLK_PIPEPHY2_PIPE_G 366 -#define CLK_PIPEPHY0_PIPE_ASIC_G 367 -#define CLK_PIPEPHY1_PIPE_ASIC_G 368 -#define CLK_PIPEPHY2_PIPE_ASIC_G 369 -#define CLK_PIPEPHY2_PIPE_U3_G 370 -#define CLK_PCIE1L2_PIPE 371 -#define CLK_PCIE4L_PIPE 372 -#define CLK_PCIE2L_PIPE 373 -#define PCLK_PCIE_COMBO_PIPE_PHY0 374 -#define PCLK_PCIE_COMBO_PIPE_PHY1 375 -#define PCLK_PCIE_COMBO_PIPE_PHY2 376 -#define PCLK_PCIE_COMBO_PIPE_PHY 377 -#define HCLK_RGA3_1 378 -#define ACLK_RGA3_1 379 -#define CLK_RGA3_1_CORE 380 -#define ACLK_RGA3_ROOT 381 -#define HCLK_RGA3_ROOT 382 -#define ACLK_RKVDEC_CCU 383 -#define HCLK_RKVDEC0 384 -#define ACLK_RKVDEC0 385 -#define CLK_RKVDEC0_CA 386 -#define CLK_RKVDEC0_HEVC_CA 387 -#define CLK_RKVDEC0_CORE 388 -#define HCLK_RKVDEC1 389 -#define ACLK_RKVDEC1 390 -#define CLK_RKVDEC1_CA 391 -#define CLK_RKVDEC1_HEVC_CA 392 -#define CLK_RKVDEC1_CORE 393 -#define HCLK_SDIO 394 -#define CCLK_SRC_SDIO 395 -#define ACLK_USB_ROOT 396 -#define HCLK_USB_ROOT 397 -#define HCLK_HOST0 398 -#define HCLK_HOST_ARB0 399 -#define HCLK_HOST1 400 -#define HCLK_HOST_ARB1 401 -#define ACLK_USB3OTG0 402 -#define SUSPEND_CLK_USB3OTG0 403 -#define REF_CLK_USB3OTG0 404 -#define ACLK_USB3OTG1 405 -#define SUSPEND_CLK_USB3OTG1 406 -#define REF_CLK_USB3OTG1 407 -#define UTMI_OHCI_CLK48_HOST0 408 -#define UTMI_OHCI_CLK48_HOST1 409 -#define HCLK_IEP2P0 410 -#define ACLK_IEP2P0 411 -#define CLK_IEP2P0_CORE 412 -#define ACLK_JPEG_ENCODER0 413 -#define HCLK_JPEG_ENCODER0 414 -#define ACLK_JPEG_ENCODER1 415 -#define HCLK_JPEG_ENCODER1 416 -#define ACLK_JPEG_ENCODER2 417 -#define HCLK_JPEG_ENCODER2 418 -#define ACLK_JPEG_ENCODER3 419 -#define HCLK_JPEG_ENCODER3 420 -#define ACLK_JPEG_DECODER 421 -#define HCLK_JPEG_DECODER 422 -#define HCLK_RGA2 423 -#define ACLK_RGA2 424 -#define CLK_RGA2_CORE 425 -#define HCLK_RGA3_0 426 -#define ACLK_RGA3_0 427 -#define CLK_RGA3_0_CORE 428 -#define ACLK_VDPU_ROOT 429 -#define ACLK_VDPU_LOW_ROOT 430 -#define HCLK_VDPU_ROOT 431 -#define ACLK_JPEG_DECODER_ROOT 432 -#define ACLK_VPU 433 -#define HCLK_VPU 434 -#define HCLK_RKVENC0_ROOT 435 -#define ACLK_RKVENC0_ROOT 436 -#define HCLK_RKVENC0 437 -#define ACLK_RKVENC0 438 -#define CLK_RKVENC0_CORE 439 -#define HCLK_RKVENC1_ROOT 440 -#define ACLK_RKVENC1_ROOT 441 -#define HCLK_RKVENC1 442 -#define ACLK_RKVENC1 443 -#define CLK_RKVENC1_CORE 444 -#define ICLK_CSIHOST01 445 -#define ICLK_CSIHOST0 446 -#define ICLK_CSIHOST1 447 -#define PCLK_CSI_HOST_0 448 -#define PCLK_CSI_HOST_1 449 -#define PCLK_CSI_HOST_2 450 -#define PCLK_CSI_HOST_3 451 -#define PCLK_CSI_HOST_4 452 -#define PCLK_CSI_HOST_5 453 -#define ACLK_FISHEYE0 454 -#define HCLK_FISHEYE0 455 -#define CLK_FISHEYE0_CORE 456 -#define ACLK_FISHEYE1 457 -#define HCLK_FISHEYE1 458 -#define CLK_FISHEYE1_CORE 459 -#define CLK_ISP0_CORE 460 -#define CLK_ISP0_CORE_MARVIN 461 -#define CLK_ISP0_CORE_VICAP 462 -#define ACLK_ISP0 463 -#define HCLK_ISP0 464 -#define ACLK_VI_ROOT 465 -#define HCLK_VI_ROOT 466 -#define PCLK_VI_ROOT 467 -#define DCLK_VICAP 468 -#define ACLK_VICAP 469 -#define HCLK_VICAP 470 -#define PCLK_DP0 471 -#define PCLK_DP1 472 -#define PCLK_S_DP0 473 -#define PCLK_S_DP1 474 -#define CLK_DP0 475 -#define CLK_DP1 476 -#define HCLK_HDCP_KEY0 477 -#define ACLK_HDCP0 478 -#define HCLK_HDCP0 479 -#define PCLK_HDCP0 480 -#define HCLK_I2S4_8CH 481 -#define ACLK_TRNG0 482 -#define PCLK_TRNG0 483 -#define ACLK_VO0_ROOT 484 -#define HCLK_VO0_ROOT 485 -#define HCLK_VO0_S_ROOT 486 -#define PCLK_VO0_ROOT 487 -#define PCLK_VO0_S_ROOT 488 -#define PCLK_VO0GRF 489 -#define CLK_I2S4_8CH_TX_SRC 490 -#define CLK_I2S4_8CH_TX_FRAC 491 -#define MCLK_I2S4_8CH_TX 492 -#define CLK_I2S4_8CH_TX 493 -#define HCLK_I2S8_8CH 494 -#define CLK_I2S8_8CH_TX_SRC 495 -#define CLK_I2S8_8CH_TX_FRAC 496 -#define MCLK_I2S8_8CH_TX 497 -#define CLK_I2S8_8CH_TX 498 -#define HCLK_SPDIF2_DP0 499 -#define CLK_SPDIF2_DP0_SRC 500 -#define CLK_SPDIF2_DP0_FRAC 501 -#define MCLK_SPDIF2_DP0 502 -#define CLK_SPDIF2_DP0 503 -#define MCLK_SPDIF2 504 -#define HCLK_SPDIF5_DP1 505 -#define CLK_SPDIF5_DP1_SRC 506 -#define CLK_SPDIF5_DP1_FRAC 507 -#define MCLK_SPDIF5_DP1 508 -#define CLK_SPDIF5_DP1 509 -#define MCLK_SPDIF5 510 -#define PCLK_EDP0 511 -#define CLK_EDP0_24M 512 -#define CLK_EDP0_200M 513 -#define PCLK_EDP1 514 -#define CLK_EDP1_24M 515 -#define CLK_EDP1_200M 516 -#define HCLK_HDCP_KEY1 517 -#define ACLK_HDCP1 518 -#define HCLK_HDCP1 519 -#define PCLK_HDCP1 520 -#define ACLK_HDMIRX 521 -#define PCLK_HDMIRX 522 -#define CLK_HDMIRX_REF 523 -#define CLK_HDMIRX_AUD_SRC 524 -#define CLK_HDMIRX_AUD_FRAC 525 -#define CLK_HDMIRX_AUD 526 -#define CLK_HDMIRX_AUD_P_MUX 527 -#define PCLK_HDMITX0 528 -#define CLK_HDMITX0_EARC 529 -#define CLK_HDMITX0_REF 530 -#define PCLK_HDMITX1 531 -#define CLK_HDMITX1_EARC 532 -#define CLK_HDMITX1_REF 533 -#define CLK_HDMITRX_REFSRC 534 -#define ACLK_TRNG1 535 -#define PCLK_TRNG1 536 -#define ACLK_HDCP1_ROOT 537 -#define ACLK_HDMIRX_ROOT 538 -#define HCLK_VO1_ROOT 539 -#define HCLK_VO1_S_ROOT 540 -#define PCLK_VO1_ROOT 541 -#define PCLK_VO1_S_ROOT 542 -#define PCLK_S_EDP0 543 -#define PCLK_S_EDP1 544 -#define PCLK_S_HDMIRX 545 -#define HCLK_I2S10_8CH 546 -#define CLK_I2S10_8CH_RX_SRC 547 -#define CLK_I2S10_8CH_RX_FRAC 548 -#define CLK_I2S10_8CH_RX 549 -#define MCLK_I2S10_8CH_RX 550 -#define HCLK_I2S7_8CH 551 -#define CLK_I2S7_8CH_RX_SRC 552 -#define CLK_I2S7_8CH_RX_FRAC 553 -#define CLK_I2S7_8CH_RX 554 -#define MCLK_I2S7_8CH_RX 555 -#define HCLK_I2S9_8CH 556 -#define CLK_I2S9_8CH_RX_SRC 557 -#define CLK_I2S9_8CH_RX_FRAC 558 -#define CLK_I2S9_8CH_RX 559 -#define MCLK_I2S9_8CH_RX 560 -#define CLK_I2S5_8CH_TX_SRC 561 -#define CLK_I2S5_8CH_TX_FRAC 562 -#define CLK_I2S5_8CH_TX 563 -#define MCLK_I2S5_8CH_TX 564 -#define HCLK_I2S5_8CH 565 -#define CLK_I2S6_8CH_TX_SRC 566 -#define CLK_I2S6_8CH_TX_FRAC 567 -#define CLK_I2S6_8CH_TX 568 -#define MCLK_I2S6_8CH_TX 569 -#define CLK_I2S6_8CH_RX_SRC 570 -#define CLK_I2S6_8CH_RX_FRAC 571 -#define CLK_I2S6_8CH_RX 572 -#define MCLK_I2S6_8CH_RX 573 -#define I2S6_8CH_MCLKOUT 574 -#define HCLK_I2S6_8CH 575 -#define HCLK_SPDIF3 576 -#define CLK_SPDIF3_SRC 577 -#define CLK_SPDIF3_FRAC 578 -#define CLK_SPDIF3 579 -#define MCLK_SPDIF3 580 -#define HCLK_SPDIF4 581 -#define CLK_SPDIF4_SRC 582 -#define CLK_SPDIF4_FRAC 583 -#define CLK_SPDIF4 584 -#define MCLK_SPDIF4 585 -#define HCLK_SPDIFRX0 586 -#define MCLK_SPDIFRX0 587 -#define HCLK_SPDIFRX1 588 -#define MCLK_SPDIFRX1 589 -#define HCLK_SPDIFRX2 590 -#define MCLK_SPDIFRX2 591 -#define ACLK_VO1USB_TOP_ROOT 592 -#define HCLK_VO1USB_TOP_ROOT 593 -#define CLK_HDMIHDP0 594 -#define CLK_HDMIHDP1 595 -#define PCLK_HDPTX0 596 -#define PCLK_HDPTX1 597 -#define PCLK_USBDPPHY0 598 -#define PCLK_USBDPPHY1 599 -#define ACLK_VOP_ROOT 600 -#define ACLK_VOP_LOW_ROOT 601 -#define HCLK_VOP_ROOT 602 -#define PCLK_VOP_ROOT 603 -#define HCLK_VOP 604 -#define ACLK_VOP 605 -#define DCLK_VOP0_SRC 606 -#define DCLK_VOP1_SRC 607 -#define DCLK_VOP2_SRC 608 -#define DCLK_VOP0 609 -#define DCLK_VOP1 610 -#define DCLK_VOP2 611 -#define DCLK_VOP3 612 -#define PCLK_DSIHOST0 613 -#define PCLK_DSIHOST1 614 -#define CLK_DSIHOST0 615 -#define CLK_DSIHOST1 616 -#define CLK_VOP_PMU 617 -#define ACLK_VOP_DOBY 618 -#define ACLK_VOP_SUB_SRC 619 -#define CLK_USBDP_PHY0_IMMORTAL 620 -#define CLK_USBDP_PHY1_IMMORTAL 621 -#define CLK_PMU0 622 -#define PCLK_PMU0 623 -#define PCLK_PMU0IOC 624 -#define PCLK_GPIO0 625 -#define DBCLK_GPIO0 626 -#define PCLK_I2C0 627 -#define CLK_I2C0 628 -#define HCLK_I2S1_8CH 629 -#define CLK_I2S1_8CH_TX_SRC 630 -#define CLK_I2S1_8CH_TX_FRAC 631 -#define CLK_I2S1_8CH_TX 632 -#define MCLK_I2S1_8CH_TX 633 -#define CLK_I2S1_8CH_RX_SRC 634 -#define CLK_I2S1_8CH_RX_FRAC 635 -#define CLK_I2S1_8CH_RX 636 -#define MCLK_I2S1_8CH_RX 637 -#define I2S1_8CH_MCLKOUT 638 -#define CLK_PMU1_50M_SRC 639 -#define CLK_PMU1_100M_SRC 640 -#define CLK_PMU1_200M_SRC 641 -#define CLK_PMU1_300M_SRC 642 -#define CLK_PMU1_400M_SRC 643 -#define HCLK_PMU1_ROOT 644 -#define PCLK_PMU1_ROOT 645 -#define PCLK_PMU0_ROOT 646 -#define HCLK_PMU_CM0_ROOT 647 -#define PCLK_PMU1 648 -#define CLK_DDR_FAIL_SAFE 649 -#define CLK_PMU1 650 -#define HCLK_PDM0 651 -#define MCLK_PDM0 652 -#define HCLK_VAD 653 -#define FCLK_PMU_CM0_CORE 654 -#define CLK_PMU_CM0_RTC 655 -#define PCLK_PMU1_IOC 656 -#define PCLK_PMU1PWM 657 -#define CLK_PMU1PWM 658 -#define CLK_PMU1PWM_CAPTURE 659 -#define PCLK_PMU1TIMER 660 -#define CLK_PMU1TIMER_ROOT 661 -#define CLK_PMU1TIMER0 662 -#define CLK_PMU1TIMER1 663 -#define CLK_UART0_SRC 664 -#define CLK_UART0_FRAC 665 -#define CLK_UART0 666 -#define SCLK_UART0 667 -#define PCLK_UART0 668 -#define PCLK_PMU1WDT 669 -#define TCLK_PMU1WDT 670 -#define CLK_CR_PARA 671 -#define CLK_USB2PHY_HDPTXRXPHY_REF 672 -#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 -#define CLK_REF_PIPE_PHY0_OSC_SRC 674 -#define CLK_REF_PIPE_PHY1_OSC_SRC 675 -#define CLK_REF_PIPE_PHY2_OSC_SRC 676 -#define CLK_REF_PIPE_PHY0_PLL_SRC 677 -#define CLK_REF_PIPE_PHY1_PLL_SRC 678 -#define CLK_REF_PIPE_PHY2_PLL_SRC 679 -#define CLK_REF_PIPE_PHY0 680 -#define CLK_REF_PIPE_PHY1 681 -#define CLK_REF_PIPE_PHY2 682 -#define SCLK_SDIO_DRV 683 -#define SCLK_SDIO_SAMPLE 684 -#define SCLK_SDMMC_DRV 685 -#define SCLK_SDMMC_SAMPLE 686 -#define CLK_PCIE1L0_PIPE 687 -#define CLK_PCIE1L1_PIPE 688 -#define CLK_BIGCORE0_PVTM 689 -#define CLK_CORE_BIGCORE0_PVTM 690 -#define CLK_BIGCORE1_PVTM 691 -#define CLK_CORE_BIGCORE1_PVTM 692 -#define CLK_LITCORE_PVTM 693 -#define CLK_CORE_LITCORE_PVTM 694 -#define CLK_AUX16M_0 695 -#define CLK_AUX16M_1 696 -#define CLK_PHY0_REF_ALT_P 697 -#define CLK_PHY0_REF_ALT_M 698 -#define CLK_PHY1_REF_ALT_P 699 -#define CLK_PHY1_REF_ALT_M 700 -#define ACLK_ISP1_PRE 701 -#define HCLK_ISP1_PRE 702 -#define HCLK_NVM 703 -#define ACLK_USB 704 -#define HCLK_USB 705 -#define ACLK_JPEG_DECODER_PRE 706 -#define ACLK_VDPU_LOW_PRE 707 -#define ACLK_RKVENC1_PRE 708 -#define HCLK_RKVENC1_PRE 709 -#define HCLK_RKVDEC0_PRE 710 -#define ACLK_RKVDEC0_PRE 711 -#define HCLK_RKVDEC1_PRE 712 -#define ACLK_RKVDEC1_PRE 713 -#define ACLK_HDCP0_PRE 714 -#define HCLK_VO0 715 -#define ACLK_HDCP1_PRE 716 -#define HCLK_VO1 717 -#define ACLK_AV1_PRE 718 -#define PCLK_AV1_PRE 719 -#define HCLK_SDIO_PRE 720 - -#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) - -/* scmi-clocks indices */ - -#define SCMI_CLK_CPUL 0 -#define SCMI_CLK_DSU 1 -#define SCMI_CLK_CPUB01 2 -#define SCMI_CLK_CPUB23 3 -#define SCMI_CLK_DDR 4 -#define SCMI_CLK_GPU 5 -#define SCMI_CLK_NPU 6 -#define SCMI_CLK_SBUS 7 -#define SCMI_PCLK_SBUS 8 -#define SCMI_CCLK_SD 9 -#define SCMI_DCLK_SD 10 -#define SCMI_ACLK_SECURE_NS 11 -#define SCMI_HCLK_SECURE_NS 12 -#define SCMI_TCLK_WDT 13 -#define SCMI_KEYLADDER_CORE 14 -#define SCMI_KEYLADDER_RNG 15 -#define SCMI_ACLK_SECURE_S 16 -#define SCMI_HCLK_SECURE_S 17 -#define SCMI_PCLK_SECURE_S 18 -#define SCMI_CRYPTO_RNG 19 -#define SCMI_CRYPTO_CORE 20 -#define SCMI_CRYPTO_PKA 21 -#define SCMI_SPLL 22 -#define SCMI_HCLK_SD 23 - -#endif diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h deleted file mode 100644 index 02e3d7fc1cce850e93c7406e5591c4918ac57669..0000000000000000000000000000000000000000 --- a/include/dt-bindings/power/rk3328-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__ -#define __DT_BINDINGS_POWER_RK3328_POWER_H__ - -/** - * RK3328 idle id Summary. - */ -#define RK3328_PD_CORE 0 -#define RK3328_PD_GPU 1 -#define RK3328_PD_BUS 2 -#define RK3328_PD_MSCH 3 -#define RK3328_PD_PERI 4 -#define RK3328_PD_VIDEO 5 -#define RK3328_PD_HEVC 6 -#define RK3328_PD_SYS 7 -#define RK3328_PD_VPU 8 -#define RK3328_PD_VIO 9 - -#endif diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h deleted file mode 100644 index 168b3bfbd6f5fbff4baca312897d2b279e2057cf..0000000000000000000000000000000000000000 --- a/include/dt-bindings/power/rk3399-power.h +++ /dev/null @@ -1,53 +0,0 @@ -#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ -#define __DT_BINDINGS_POWER_RK3399_POWER_H__ - -/* VD_CORE_L */ -#define RK3399_PD_A53_L0 0 -#define RK3399_PD_A53_L1 1 -#define RK3399_PD_A53_L2 2 -#define RK3399_PD_A53_L3 3 -#define RK3399_PD_SCU_L 4 - -/* VD_CORE_B */ -#define RK3399_PD_A72_B0 5 -#define RK3399_PD_A72_B1 6 -#define RK3399_PD_SCU_B 7 - -/* VD_LOGIC */ -#define RK3399_PD_TCPD0 8 -#define RK3399_PD_TCPD1 9 -#define RK3399_PD_CCI 10 -#define RK3399_PD_CCI0 11 -#define RK3399_PD_CCI1 12 -#define RK3399_PD_PERILP 13 -#define RK3399_PD_PERIHP 14 -#define RK3399_PD_VIO 15 -#define RK3399_PD_VO 16 -#define RK3399_PD_VOPB 17 -#define RK3399_PD_VOPL 18 -#define RK3399_PD_ISP0 19 -#define RK3399_PD_ISP1 20 -#define RK3399_PD_HDCP 21 -#define RK3399_PD_GMAC 22 -#define RK3399_PD_EMMC 23 -#define RK3399_PD_USB3 24 -#define RK3399_PD_EDP 25 -#define RK3399_PD_GIC 26 -#define RK3399_PD_SD 27 -#define RK3399_PD_SDIOAUDIO 28 -#define RK3399_PD_ALIVE 29 - -/* VD_CENTER */ -#define RK3399_PD_CENTER 30 -#define RK3399_PD_VCODEC 31 -#define RK3399_PD_VDU 32 -#define RK3399_PD_RGA 33 -#define RK3399_PD_IEP 34 - -/* VD_GPU */ -#define RK3399_PD_GPU 35 - -/* VD_PMU */ -#define RK3399_PD_PMU 36 - -#endif diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h deleted file mode 100644 index 6cc1af1a9d267e18d9d23e23a7b9fc7d7f0ef3d6..0000000000000000000000000000000000000000 --- a/include/dt-bindings/power/rk3568-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ -#define __DT_BINDINGS_POWER_RK3568_POWER_H__ - -/* VD_CORE */ -#define RK3568_PD_CPU_0 0 -#define RK3568_PD_CPU_1 1 -#define RK3568_PD_CPU_2 2 -#define RK3568_PD_CPU_3 3 -#define RK3568_PD_CORE_ALIVE 4 - -/* VD_PMU */ -#define RK3568_PD_PMU 5 - -/* VD_NPU */ -#define RK3568_PD_NPU 6 - -/* VD_GPU */ -#define RK3568_PD_GPU 7 - -/* VD_LOGIC */ -#define RK3568_PD_VI 8 -#define RK3568_PD_VO 9 -#define RK3568_PD_RGA 10 -#define RK3568_PD_VPU 11 -#define RK3568_PD_CENTER 12 -#define RK3568_PD_RKVDEC 13 -#define RK3568_PD_RKVENC 14 -#define RK3568_PD_PIPE 15 -#define RK3568_PD_LOGIC_ALIVE 16 - -#endif diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h deleted file mode 100644 index 1b92fec013cb617608d59fd3d37591e8d926f6a8..0000000000000000000000000000000000000000 --- a/include/dt-bindings/power/rk3588-power.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ -#define __DT_BINDINGS_POWER_RK3588_POWER_H__ - -/* VD_LITDSU */ -#define RK3588_PD_CPU_0 0 -#define RK3588_PD_CPU_1 1 -#define RK3588_PD_CPU_2 2 -#define RK3588_PD_CPU_3 3 - -/* VD_BIGCORE0 */ -#define RK3588_PD_CPU_4 4 -#define RK3588_PD_CPU_5 5 - -/* VD_BIGCORE1 */ -#define RK3588_PD_CPU_6 6 -#define RK3588_PD_CPU_7 7 - -/* VD_NPU */ -#define RK3588_PD_NPU 8 -#define RK3588_PD_NPUTOP 9 -#define RK3588_PD_NPU1 10 -#define RK3588_PD_NPU2 11 - -/* VD_GPU */ -#define RK3588_PD_GPU 12 - -/* VD_VCODEC */ -#define RK3588_PD_VCODEC 13 -#define RK3588_PD_RKVDEC0 14 -#define RK3588_PD_RKVDEC1 15 -#define RK3588_PD_VENC0 16 -#define RK3588_PD_VENC1 17 - -/* VD_DD01 */ -#define RK3588_PD_DDR01 18 - -/* VD_DD23 */ -#define RK3588_PD_DDR23 19 - -/* VD_LOGIC */ -#define RK3588_PD_CENTER 20 -#define RK3588_PD_VDPU 21 -#define RK3588_PD_RGA30 22 -#define RK3588_PD_AV1 23 -#define RK3588_PD_VOP 24 -#define RK3588_PD_VO0 25 -#define RK3588_PD_VO1 26 -#define RK3588_PD_VI 27 -#define RK3588_PD_ISP1 28 -#define RK3588_PD_FEC 29 -#define RK3588_PD_RGA31 30 -#define RK3588_PD_USB 31 -#define RK3588_PD_PHP 32 -#define RK3588_PD_GMAC 33 -#define RK3588_PD_PCIE 34 -#define RK3588_PD_NVM 35 -#define RK3588_PD_NVM0 36 -#define RK3588_PD_SDIO 37 -#define RK3588_PD_AUDIO 38 -#define RK3588_PD_SECURE 39 -#define RK3588_PD_SDMMC 40 -#define RK3588_PD_CRYPTO 41 -#define RK3588_PD_BUS 42 - -/* VD_PMU */ -#define RK3588_PD_PMU1 43 - -#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h deleted file mode 100644 index 738e56aead935056b5757a3b8d2697ac2c3b15e5..0000000000000000000000000000000000000000 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ /dev/null @@ -1,754 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ -/* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang - * Author: Sebastian Reichel - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H - -#define SRST_A_TOP_BIU 0 -#define SRST_P_TOP_BIU 1 -#define SRST_P_CSIPHY0 2 -#define SRST_CSIPHY0 3 -#define SRST_P_CSIPHY1 4 -#define SRST_CSIPHY1 5 -#define SRST_A_TOP_M500_BIU 6 - -#define SRST_A_TOP_M400_BIU 7 -#define SRST_A_TOP_S200_BIU 8 -#define SRST_A_TOP_S400_BIU 9 -#define SRST_A_TOP_M300_BIU 10 -#define SRST_USBDP_COMBO_PHY0_INIT 11 -#define SRST_USBDP_COMBO_PHY0_CMN 12 -#define SRST_USBDP_COMBO_PHY0_LANE 13 -#define SRST_USBDP_COMBO_PHY0_PCS 14 -#define SRST_USBDP_COMBO_PHY1_INIT 15 - -#define SRST_USBDP_COMBO_PHY1_CMN 16 -#define SRST_USBDP_COMBO_PHY1_LANE 17 -#define SRST_USBDP_COMBO_PHY1_PCS 18 -#define SRST_DCPHY0 19 -#define SRST_P_MIPI_DCPHY0 20 -#define SRST_P_MIPI_DCPHY0_GRF 21 - -#define SRST_DCPHY1 22 -#define SRST_P_MIPI_DCPHY1 23 -#define SRST_P_MIPI_DCPHY1_GRF 24 -#define SRST_P_APB2ASB_SLV_CDPHY 25 -#define SRST_P_APB2ASB_SLV_CSIPHY 26 -#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 -#define SRST_P_APB2ASB_SLV_VCCIO6 28 -#define SRST_P_APB2ASB_SLV_EMMCIO 29 -#define SRST_P_APB2ASB_SLV_IOC_TOP 30 -#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 - -#define SRST_P_CRU 32 -#define SRST_A_CHANNEL_SECURE2VO1USB 33 -#define SRST_A_CHANNEL_SECURE2CENTER 34 -#define SRST_H_CHANNEL_SECURE2VO1USB 35 -#define SRST_H_CHANNEL_SECURE2CENTER 36 - -#define SRST_P_CHANNEL_SECURE2VO1USB 37 -#define SRST_P_CHANNEL_SECURE2CENTER 38 - -#define SRST_H_AUDIO_BIU 39 -#define SRST_P_AUDIO_BIU 40 -#define SRST_H_I2S0_8CH 41 -#define SRST_M_I2S0_8CH_TX 42 -#define SRST_M_I2S0_8CH_RX 43 -#define SRST_P_ACDCDIG 44 -#define SRST_H_I2S2_2CH 45 -#define SRST_H_I2S3_2CH 46 - -#define SRST_M_I2S2_2CH 47 -#define SRST_M_I2S3_2CH 48 -#define SRST_DAC_ACDCDIG 49 -#define SRST_H_SPDIF0 50 - -#define SRST_M_SPDIF0 51 -#define SRST_H_SPDIF1 52 -#define SRST_M_SPDIF1 53 -#define SRST_H_PDM1 54 -#define SRST_PDM1 55 - -#define SRST_A_BUS_BIU 56 -#define SRST_P_BUS_BIU 57 -#define SRST_A_GIC 58 -#define SRST_A_GIC_DBG 59 -#define SRST_A_DMAC0 60 -#define SRST_A_DMAC1 61 -#define SRST_A_DMAC2 62 -#define SRST_P_I2C1 63 -#define SRST_P_I2C2 64 -#define SRST_P_I2C3 65 -#define SRST_P_I2C4 66 -#define SRST_P_I2C5 67 -#define SRST_P_I2C6 68 -#define SRST_P_I2C7 69 -#define SRST_P_I2C8 70 - -#define SRST_I2C1 71 -#define SRST_I2C2 72 -#define SRST_I2C3 73 -#define SRST_I2C4 74 -#define SRST_I2C5 75 -#define SRST_I2C6 76 -#define SRST_I2C7 77 -#define SRST_I2C8 78 -#define SRST_P_CAN0 79 -#define SRST_CAN0 80 -#define SRST_P_CAN1 81 -#define SRST_CAN1 82 -#define SRST_P_CAN2 83 -#define SRST_CAN2 84 -#define SRST_P_SARADC 85 - -#define SRST_P_TSADC 86 -#define SRST_TSADC 87 -#define SRST_P_UART1 88 -#define SRST_P_UART2 89 -#define SRST_P_UART3 90 -#define SRST_P_UART4 91 -#define SRST_P_UART5 92 -#define SRST_P_UART6 93 -#define SRST_P_UART7 94 -#define SRST_P_UART8 95 -#define SRST_P_UART9 96 -#define SRST_S_UART1 97 - -#define SRST_S_UART2 98 -#define SRST_S_UART3 99 -#define SRST_S_UART4 100 -#define SRST_S_UART5 101 -#define SRST_S_UART6 102 -#define SRST_S_UART7 103 - -#define SRST_S_UART8 104 -#define SRST_S_UART9 105 -#define SRST_P_SPI0 106 -#define SRST_P_SPI1 107 -#define SRST_P_SPI2 108 -#define SRST_P_SPI3 109 -#define SRST_P_SPI4 110 -#define SRST_SPI0 111 -#define SRST_SPI1 112 -#define SRST_SPI2 113 -#define SRST_SPI3 114 -#define SRST_SPI4 115 - -#define SRST_P_WDT0 116 -#define SRST_T_WDT0 117 -#define SRST_P_SYS_GRF 118 -#define SRST_P_PWM1 119 -#define SRST_PWM1 120 -#define SRST_P_PWM2 121 -#define SRST_PWM2 122 -#define SRST_P_PWM3 123 -#define SRST_PWM3 124 -#define SRST_P_BUSTIMER0 125 -#define SRST_P_BUSTIMER1 126 -#define SRST_BUSTIMER0 127 - -#define SRST_BUSTIMER1 128 -#define SRST_BUSTIMER2 129 -#define SRST_BUSTIMER3 130 -#define SRST_BUSTIMER4 131 -#define SRST_BUSTIMER5 132 -#define SRST_BUSTIMER6 133 -#define SRST_BUSTIMER7 134 -#define SRST_BUSTIMER8 135 -#define SRST_BUSTIMER9 136 -#define SRST_BUSTIMER10 137 -#define SRST_BUSTIMER11 138 -#define SRST_P_MAILBOX0 139 -#define SRST_P_MAILBOX1 140 -#define SRST_P_MAILBOX2 141 -#define SRST_P_GPIO1 142 -#define SRST_GPIO1 143 - -#define SRST_P_GPIO2 144 -#define SRST_GPIO2 145 -#define SRST_P_GPIO3 146 -#define SRST_GPIO3 147 -#define SRST_P_GPIO4 148 -#define SRST_GPIO4 149 -#define SRST_A_DECOM 150 -#define SRST_P_DECOM 151 -#define SRST_D_DECOM 152 -#define SRST_P_TOP 153 -#define SRST_A_GICADB_GIC2CORE_BUS 154 -#define SRST_P_DFT2APB 155 -#define SRST_P_APB2ASB_MST_TOP 156 -#define SRST_P_APB2ASB_MST_CDPHY 157 -#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 - -#define SRST_P_APB2ASB_MST_IOC_TOP 159 -#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 -#define SRST_P_APB2ASB_MST_CSIPHY 161 -#define SRST_P_APB2ASB_MST_VCCIO3_5 162 -#define SRST_P_APB2ASB_MST_VCCIO6 163 -#define SRST_P_APB2ASB_MST_EMMCIO 164 -#define SRST_A_SPINLOCK 165 -#define SRST_P_OTPC_NS 166 -#define SRST_OTPC_NS 167 -#define SRST_OTPC_ARB 168 - -#define SRST_P_BUSIOC 169 -#define SRST_P_PMUCM0_INTMUX 170 -#define SRST_P_DDRCM0_INTMUX 171 - -#define SRST_P_DDR_DFICTL_CH0 172 -#define SRST_P_DDR_MON_CH0 173 -#define SRST_P_DDR_STANDBY_CH0 174 -#define SRST_P_DDR_UPCTL_CH0 175 -#define SRST_TM_DDR_MON_CH0 176 -#define SRST_P_DDR_GRF_CH01 177 -#define SRST_DFI_CH0 178 -#define SRST_SBR_CH0 179 -#define SRST_DDR_UPCTL_CH0 180 -#define SRST_DDR_DFICTL_CH0 181 -#define SRST_DDR_MON_CH0 182 -#define SRST_DDR_STANDBY_CH0 183 -#define SRST_A_DDR_UPCTL_CH0 184 -#define SRST_P_DDR_DFICTL_CH1 185 -#define SRST_P_DDR_MON_CH1 186 -#define SRST_P_DDR_STANDBY_CH1 187 - -#define SRST_P_DDR_UPCTL_CH1 188 -#define SRST_TM_DDR_MON_CH1 189 -#define SRST_DFI_CH1 190 -#define SRST_SBR_CH1 191 -#define SRST_DDR_UPCTL_CH1 192 -#define SRST_DDR_DFICTL_CH1 193 -#define SRST_DDR_MON_CH1 194 -#define SRST_DDR_STANDBY_CH1 195 -#define SRST_A_DDR_UPCTL_CH1 196 -#define SRST_A_DDR01_MSCH0 197 -#define SRST_A_DDR01_RS_MSCH0 198 -#define SRST_A_DDR01_FRS_MSCH0 199 - -#define SRST_A_DDR01_SCRAMBLE0 200 -#define SRST_A_DDR01_FRS_SCRAMBLE0 201 -#define SRST_A_DDR01_MSCH1 202 -#define SRST_A_DDR01_RS_MSCH1 203 -#define SRST_A_DDR01_FRS_MSCH1 204 -#define SRST_A_DDR01_SCRAMBLE1 205 -#define SRST_A_DDR01_FRS_SCRAMBLE1 206 -#define SRST_P_DDR01_MSCH0 207 -#define SRST_P_DDR01_MSCH1 208 - -#define SRST_P_DDR_DFICTL_CH2 209 -#define SRST_P_DDR_MON_CH2 210 -#define SRST_P_DDR_STANDBY_CH2 211 -#define SRST_P_DDR_UPCTL_CH2 212 -#define SRST_TM_DDR_MON_CH2 213 -#define SRST_P_DDR_GRF_CH23 214 -#define SRST_DFI_CH2 215 -#define SRST_SBR_CH2 216 -#define SRST_DDR_UPCTL_CH2 217 -#define SRST_DDR_DFICTL_CH2 218 -#define SRST_DDR_MON_CH2 219 -#define SRST_DDR_STANDBY_CH2 220 -#define SRST_A_DDR_UPCTL_CH2 221 -#define SRST_P_DDR_DFICTL_CH3 222 -#define SRST_P_DDR_MON_CH3 223 -#define SRST_P_DDR_STANDBY_CH3 224 - -#define SRST_P_DDR_UPCTL_CH3 225 -#define SRST_TM_DDR_MON_CH3 226 -#define SRST_DFI_CH3 227 -#define SRST_SBR_CH3 228 -#define SRST_DDR_UPCTL_CH3 229 -#define SRST_DDR_DFICTL_CH3 230 -#define SRST_DDR_MON_CH3 231 -#define SRST_DDR_STANDBY_CH3 232 -#define SRST_A_DDR_UPCTL_CH3 233 -#define SRST_A_DDR23_MSCH2 234 -#define SRST_A_DDR23_RS_MSCH2 235 -#define SRST_A_DDR23_FRS_MSCH2 236 - -#define SRST_A_DDR23_SCRAMBLE2 237 -#define SRST_A_DDR23_FRS_SCRAMBLE2 238 -#define SRST_A_DDR23_MSCH3 239 -#define SRST_A_DDR23_RS_MSCH3 240 -#define SRST_A_DDR23_FRS_MSCH3 241 -#define SRST_A_DDR23_SCRAMBLE3 242 -#define SRST_A_DDR23_FRS_SCRAMBLE3 243 -#define SRST_P_DDR23_MSCH2 244 -#define SRST_P_DDR23_MSCH3 245 - -#define SRST_ISP1 246 -#define SRST_ISP1_VICAP 247 -#define SRST_A_ISP1_BIU 248 -#define SRST_H_ISP1_BIU 249 - -#define SRST_A_RKNN1 250 -#define SRST_A_RKNN1_BIU 251 -#define SRST_H_RKNN1 252 -#define SRST_H_RKNN1_BIU 253 - -#define SRST_A_RKNN2 254 -#define SRST_A_RKNN2_BIU 255 -#define SRST_H_RKNN2 256 -#define SRST_H_RKNN2_BIU 257 - -#define SRST_A_RKNN_DSU0 258 -#define SRST_P_NPUTOP_BIU 259 -#define SRST_P_NPU_TIMER 260 -#define SRST_NPUTIMER0 261 -#define SRST_NPUTIMER1 262 -#define SRST_P_NPU_WDT 263 -#define SRST_T_NPU_WDT 264 -#define SRST_P_NPU_PVTM 265 -#define SRST_P_NPU_GRF 266 -#define SRST_NPU_PVTM 267 - -#define SRST_NPU_PVTPLL 268 -#define SRST_H_NPU_CM0_BIU 269 -#define SRST_F_NPU_CM0_CORE 270 -#define SRST_T_NPU_CM0_JTAG 271 -#define SRST_A_RKNN0 272 -#define SRST_A_RKNN0_BIU 273 -#define SRST_H_RKNN0 274 -#define SRST_H_RKNN0_BIU 275 - -#define SRST_H_NVM_BIU 276 -#define SRST_A_NVM_BIU 277 -#define SRST_H_EMMC 278 -#define SRST_A_EMMC 279 -#define SRST_C_EMMC 280 -#define SRST_B_EMMC 281 -#define SRST_T_EMMC 282 -#define SRST_S_SFC 283 -#define SRST_H_SFC 284 -#define SRST_H_SFC_XIP 285 - -#define SRST_P_GRF 286 -#define SRST_P_DEC_BIU 287 -#define SRST_P_PHP_BIU 288 -#define SRST_A_PCIE_GRIDGE 289 -#define SRST_A_PHP_BIU 290 -#define SRST_A_GMAC0 291 -#define SRST_A_GMAC1 292 -#define SRST_A_PCIE_BIU 293 -#define SRST_PCIE0_POWER_UP 294 -#define SRST_PCIE1_POWER_UP 295 -#define SRST_PCIE2_POWER_UP 296 - -#define SRST_PCIE3_POWER_UP 297 -#define SRST_PCIE4_POWER_UP 298 -#define SRST_P_PCIE0 299 -#define SRST_P_PCIE1 300 -#define SRST_P_PCIE2 301 -#define SRST_P_PCIE3 302 - -#define SRST_P_PCIE4 303 -#define SRST_A_PHP_GIC_ITS 304 -#define SRST_A_MMU_PCIE 305 -#define SRST_A_MMU_PHP 306 -#define SRST_A_MMU_BIU 307 - -#define SRST_A_USB3OTG2 308 - -#define SRST_PMALIVE0 309 -#define SRST_PMALIVE1 310 -#define SRST_PMALIVE2 311 -#define SRST_A_SATA0 312 -#define SRST_A_SATA1 313 -#define SRST_A_SATA2 314 -#define SRST_RXOOB0 315 -#define SRST_RXOOB1 316 -#define SRST_RXOOB2 317 -#define SRST_ASIC0 318 -#define SRST_ASIC1 319 -#define SRST_ASIC2 320 - -#define SRST_A_RKVDEC_CCU 321 -#define SRST_H_RKVDEC0 322 -#define SRST_A_RKVDEC0 323 -#define SRST_H_RKVDEC0_BIU 324 -#define SRST_A_RKVDEC0_BIU 325 -#define SRST_RKVDEC0_CA 326 -#define SRST_RKVDEC0_HEVC_CA 327 -#define SRST_RKVDEC0_CORE 328 - -#define SRST_H_RKVDEC1 329 -#define SRST_A_RKVDEC1 330 -#define SRST_H_RKVDEC1_BIU 331 -#define SRST_A_RKVDEC1_BIU 332 -#define SRST_RKVDEC1_CA 333 -#define SRST_RKVDEC1_HEVC_CA 334 -#define SRST_RKVDEC1_CORE 335 - -#define SRST_A_USB_BIU 336 -#define SRST_H_USB_BIU 337 -#define SRST_A_USB3OTG0 338 -#define SRST_A_USB3OTG1 339 -#define SRST_H_HOST0 340 -#define SRST_H_HOST_ARB0 341 -#define SRST_H_HOST1 342 -#define SRST_H_HOST_ARB1 343 -#define SRST_A_USB_GRF 344 -#define SRST_C_USB2P0_HOST0 345 - -#define SRST_C_USB2P0_HOST1 346 -#define SRST_HOST_UTMI0 347 -#define SRST_HOST_UTMI1 348 - -#define SRST_A_VDPU_BIU 349 -#define SRST_A_VDPU_LOW_BIU 350 -#define SRST_H_VDPU_BIU 351 -#define SRST_A_JPEG_DECODER_BIU 352 -#define SRST_A_VPU 353 -#define SRST_H_VPU 354 -#define SRST_A_JPEG_ENCODER0 355 -#define SRST_H_JPEG_ENCODER0 356 -#define SRST_A_JPEG_ENCODER1 357 -#define SRST_H_JPEG_ENCODER1 358 -#define SRST_A_JPEG_ENCODER2 359 -#define SRST_H_JPEG_ENCODER2 360 - -#define SRST_A_JPEG_ENCODER3 361 -#define SRST_H_JPEG_ENCODER3 362 -#define SRST_A_JPEG_DECODER 363 -#define SRST_H_JPEG_DECODER 364 -#define SRST_H_IEP2P0 365 -#define SRST_A_IEP2P0 366 -#define SRST_IEP2P0_CORE 367 -#define SRST_H_RGA2 368 -#define SRST_A_RGA2 369 -#define SRST_RGA2_CORE 370 -#define SRST_H_RGA3_0 371 -#define SRST_A_RGA3_0 372 -#define SRST_RGA3_0_CORE 373 - -#define SRST_H_RKVENC0_BIU 374 -#define SRST_A_RKVENC0_BIU 375 -#define SRST_H_RKVENC0 376 -#define SRST_A_RKVENC0 377 -#define SRST_RKVENC0_CORE 378 - -#define SRST_H_RKVENC1_BIU 379 -#define SRST_A_RKVENC1_BIU 380 -#define SRST_H_RKVENC1 381 -#define SRST_A_RKVENC1 382 -#define SRST_RKVENC1_CORE 383 - -#define SRST_A_VI_BIU 384 -#define SRST_H_VI_BIU 385 -#define SRST_P_VI_BIU 386 -#define SRST_D_VICAP 387 -#define SRST_A_VICAP 388 -#define SRST_H_VICAP 389 -#define SRST_ISP0 390 -#define SRST_ISP0_VICAP 391 - -#define SRST_FISHEYE0 392 -#define SRST_FISHEYE1 393 -#define SRST_P_CSI_HOST_0 394 -#define SRST_P_CSI_HOST_1 395 -#define SRST_P_CSI_HOST_2 396 -#define SRST_P_CSI_HOST_3 397 -#define SRST_P_CSI_HOST_4 398 -#define SRST_P_CSI_HOST_5 399 - -#define SRST_CSIHOST0_VICAP 400 -#define SRST_CSIHOST1_VICAP 401 -#define SRST_CSIHOST2_VICAP 402 -#define SRST_CSIHOST3_VICAP 403 -#define SRST_CSIHOST4_VICAP 404 -#define SRST_CSIHOST5_VICAP 405 -#define SRST_CIFIN 406 - -#define SRST_A_VOP_BIU 407 -#define SRST_A_VOP_LOW_BIU 408 -#define SRST_H_VOP_BIU 409 -#define SRST_P_VOP_BIU 410 -#define SRST_H_VOP 411 -#define SRST_A_VOP 412 -#define SRST_D_VOP0 413 -#define SRST_D_VOP2HDMI_BRIDGE0 414 -#define SRST_D_VOP2HDMI_BRIDGE1 415 - -#define SRST_D_VOP1 416 -#define SRST_D_VOP2 417 -#define SRST_D_VOP3 418 -#define SRST_P_VOPGRF 419 -#define SRST_P_DSIHOST0 420 -#define SRST_P_DSIHOST1 421 -#define SRST_DSIHOST0 422 -#define SRST_DSIHOST1 423 -#define SRST_VOP_PMU 424 -#define SRST_P_VOP_CHANNEL_BIU 425 - -#define SRST_H_VO0_BIU 426 -#define SRST_H_VO0_S_BIU 427 -#define SRST_P_VO0_BIU 428 -#define SRST_P_VO0_S_BIU 429 -#define SRST_A_HDCP0_BIU 430 -#define SRST_P_VO0GRF 431 -#define SRST_H_HDCP_KEY0 432 -#define SRST_A_HDCP0 433 -#define SRST_H_HDCP0 434 -#define SRST_HDCP0 435 - -#define SRST_P_TRNG0 436 -#define SRST_DP0 437 -#define SRST_DP1 438 -#define SRST_H_I2S4_8CH 439 -#define SRST_M_I2S4_8CH_TX 440 -#define SRST_H_I2S8_8CH 441 - -#define SRST_M_I2S8_8CH_TX 442 -#define SRST_H_SPDIF2_DP0 443 -#define SRST_M_SPDIF2_DP0 444 -#define SRST_H_SPDIF5_DP1 445 -#define SRST_M_SPDIF5_DP1 446 - -#define SRST_A_HDCP1_BIU 447 -#define SRST_A_VO1_BIU 448 -#define SRST_H_VOP1_BIU 449 -#define SRST_H_VOP1_S_BIU 450 -#define SRST_P_VOP1_BIU 451 -#define SRST_P_VO1GRF 452 -#define SRST_P_VO1_S_BIU 453 - -#define SRST_H_I2S7_8CH 454 -#define SRST_M_I2S7_8CH_RX 455 -#define SRST_H_HDCP_KEY1 456 -#define SRST_A_HDCP1 457 -#define SRST_H_HDCP1 458 -#define SRST_HDCP1 459 -#define SRST_P_TRNG1 460 -#define SRST_P_HDMITX0 461 - -#define SRST_HDMITX0_REF 462 -#define SRST_P_HDMITX1 463 -#define SRST_HDMITX1_REF 464 -#define SRST_A_HDMIRX 465 -#define SRST_P_HDMIRX 466 -#define SRST_HDMIRX_REF 467 - -#define SRST_P_EDP0 468 -#define SRST_EDP0_24M 469 -#define SRST_P_EDP1 470 -#define SRST_EDP1_24M 471 -#define SRST_M_I2S5_8CH_TX 472 -#define SRST_H_I2S5_8CH 473 -#define SRST_M_I2S6_8CH_TX 474 - -#define SRST_M_I2S6_8CH_RX 475 -#define SRST_H_I2S6_8CH 476 -#define SRST_H_SPDIF3 477 -#define SRST_M_SPDIF3 478 -#define SRST_H_SPDIF4 479 -#define SRST_M_SPDIF4 480 -#define SRST_H_SPDIFRX0 481 -#define SRST_M_SPDIFRX0 482 -#define SRST_H_SPDIFRX1 483 -#define SRST_M_SPDIFRX1 484 - -#define SRST_H_SPDIFRX2 485 -#define SRST_M_SPDIFRX2 486 -#define SRST_LINKSYM_HDMITXPHY0 487 -#define SRST_LINKSYM_HDMITXPHY1 488 -#define SRST_VO1_BRIDGE0 489 -#define SRST_VO1_BRIDGE1 490 - -#define SRST_H_I2S9_8CH 491 -#define SRST_M_I2S9_8CH_RX 492 -#define SRST_H_I2S10_8CH 493 -#define SRST_M_I2S10_8CH_RX 494 -#define SRST_P_S_HDMIRX 495 - -#define SRST_GPU 496 -#define SRST_SYS_GPU 497 -#define SRST_A_S_GPU_BIU 498 -#define SRST_A_M0_GPU_BIU 499 -#define SRST_A_M1_GPU_BIU 500 -#define SRST_A_M2_GPU_BIU 501 -#define SRST_A_M3_GPU_BIU 502 -#define SRST_P_GPU_BIU 503 -#define SRST_P_GPU_PVTM 504 - -#define SRST_GPU_PVTM 505 -#define SRST_P_GPU_GRF 506 -#define SRST_GPU_PVTPLL 507 -#define SRST_GPU_JTAG 508 - -#define SRST_A_AV1_BIU 509 -#define SRST_A_AV1 510 -#define SRST_P_AV1_BIU 511 -#define SRST_P_AV1 512 - -#define SRST_A_DDR_BIU 513 -#define SRST_A_DMA2DDR 514 -#define SRST_A_DDR_SHAREMEM 515 -#define SRST_A_DDR_SHAREMEM_BIU 516 -#define SRST_A_CENTER_S200_BIU 517 -#define SRST_A_CENTER_S400_BIU 518 -#define SRST_H_AHB2APB 519 -#define SRST_H_CENTER_BIU 520 -#define SRST_F_DDR_CM0_CORE 521 - -#define SRST_DDR_TIMER0 522 -#define SRST_DDR_TIMER1 523 -#define SRST_T_WDT_DDR 524 -#define SRST_T_DDR_CM0_JTAG 525 -#define SRST_P_CENTER_GRF 526 -#define SRST_P_AHB2APB 527 -#define SRST_P_WDT 528 -#define SRST_P_TIMER 529 -#define SRST_P_DMA2DDR 530 -#define SRST_P_SHAREMEM 531 -#define SRST_P_CENTER_BIU 532 -#define SRST_P_CENTER_CHANNEL_BIU 533 - -#define SRST_P_USBDPGRF0 534 -#define SRST_P_USBDPPHY0 535 -#define SRST_P_USBDPGRF1 536 -#define SRST_P_USBDPPHY1 537 -#define SRST_P_HDPTX0 538 -#define SRST_P_HDPTX1 539 -#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 -#define SRST_P_USB2PHY_U3_0_GRF0 541 -#define SRST_P_USB2PHY_U3_1_GRF0 542 -#define SRST_P_USB2PHY_U2_0_GRF0 543 -#define SRST_P_USB2PHY_U2_1_GRF0 544 -#define SRST_HDPTX0_ROPLL 545 -#define SRST_HDPTX0_LCPLL 546 -#define SRST_HDPTX0 547 -#define SRST_HDPTX1_ROPLL 548 - -#define SRST_HDPTX1_LCPLL 549 -#define SRST_HDPTX1 550 -#define SRST_HDPTX0_HDMIRXPHY_SET 551 -#define SRST_USBDP_COMBO_PHY0 552 -#define SRST_USBDP_COMBO_PHY0_LCPLL 553 -#define SRST_USBDP_COMBO_PHY0_ROPLL 554 -#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 -#define SRST_USBDP_COMBO_PHY1 556 -#define SRST_USBDP_COMBO_PHY1_LCPLL 557 -#define SRST_USBDP_COMBO_PHY1_ROPLL 558 -#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 -#define SRST_HDMIHDP0 560 -#define SRST_HDMIHDP1 561 - -#define SRST_A_VO1USB_TOP_BIU 562 -#define SRST_H_VO1USB_TOP_BIU 563 - -#define SRST_H_SDIO_BIU 564 -#define SRST_H_SDIO 565 -#define SRST_SDIO 566 - -#define SRST_H_RGA3_BIU 567 -#define SRST_A_RGA3_BIU 568 -#define SRST_H_RGA3_1 569 -#define SRST_A_RGA3_1 570 -#define SRST_RGA3_1_CORE 571 - -#define SRST_REF_PIPE_PHY0 572 -#define SRST_REF_PIPE_PHY1 573 -#define SRST_REF_PIPE_PHY2 574 - -#define SRST_P_PHPTOP_CRU 575 -#define SRST_P_PCIE2_GRF0 576 -#define SRST_P_PCIE2_GRF1 577 -#define SRST_P_PCIE2_GRF2 578 -#define SRST_P_PCIE2_PHY0 579 -#define SRST_P_PCIE2_PHY1 580 -#define SRST_P_PCIE2_PHY2 581 -#define SRST_P_PCIE3_PHY 582 -#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 -#define SRST_PCIE30_PHY 584 - -#define SRST_H_PMU1_BIU 585 -#define SRST_P_PMU1_BIU 586 -#define SRST_H_PMU_CM0_BIU 587 -#define SRST_F_PMU_CM0_CORE 588 -#define SRST_T_PMU1_CM0_JTAG 589 - -#define SRST_DDR_FAIL_SAFE 590 -#define SRST_P_CRU_PMU1 591 -#define SRST_P_PMU1_GRF 592 -#define SRST_P_PMU1_IOC 593 -#define SRST_P_PMU1WDT 594 -#define SRST_T_PMU1WDT 595 -#define SRST_P_PMU1TIMER 596 -#define SRST_PMU1TIMER0 597 -#define SRST_PMU1TIMER1 598 -#define SRST_P_PMU1PWM 599 -#define SRST_PMU1PWM 600 - -#define SRST_P_I2C0 601 -#define SRST_I2C0 602 -#define SRST_S_UART0 603 -#define SRST_P_UART0 604 -#define SRST_H_I2S1_8CH 605 -#define SRST_M_I2S1_8CH_TX 606 -#define SRST_M_I2S1_8CH_RX 607 -#define SRST_H_PDM0 608 -#define SRST_PDM0 609 - -#define SRST_H_VAD 610 -#define SRST_HDPTX0_INIT 611 -#define SRST_HDPTX0_CMN 612 -#define SRST_HDPTX0_LANE 613 -#define SRST_HDPTX1_INIT 614 - -#define SRST_HDPTX1_CMN 615 -#define SRST_HDPTX1_LANE 616 -#define SRST_M_MIPI_DCPHY0 617 -#define SRST_S_MIPI_DCPHY0 618 -#define SRST_M_MIPI_DCPHY1 619 -#define SRST_S_MIPI_DCPHY1 620 -#define SRST_OTGPHY_U3_0 621 -#define SRST_OTGPHY_U3_1 622 -#define SRST_OTGPHY_U2_0 623 -#define SRST_OTGPHY_U2_1 624 - -#define SRST_P_PMU0GRF 625 -#define SRST_P_PMU0IOC 626 -#define SRST_P_GPIO0 627 -#define SRST_GPIO0 628 - -#define SRST_A_SECURE_NS_BIU 629 -#define SRST_H_SECURE_NS_BIU 630 -#define SRST_A_SECURE_S_BIU 631 -#define SRST_H_SECURE_S_BIU 632 -#define SRST_P_SECURE_S_BIU 633 -#define SRST_CRYPTO_CORE 634 - -#define SRST_CRYPTO_PKA 635 -#define SRST_CRYPTO_RNG 636 -#define SRST_A_CRYPTO 637 -#define SRST_H_CRYPTO 638 -#define SRST_KEYLADDER_CORE 639 -#define SRST_KEYLADDER_RNG 640 -#define SRST_A_KEYLADDER 641 -#define SRST_H_KEYLADDER 642 -#define SRST_P_OTPC_S 643 -#define SRST_OTPC_S 644 -#define SRST_WDT_S 645 - -#define SRST_T_WDT_S 646 -#define SRST_H_BOOTROM 647 -#define SRST_A_DCF 648 -#define SRST_P_DCF 649 -#define SRST_H_BOOTROM_NS 650 -#define SRST_P_KEYLADDER 651 -#define SRST_H_TRNG_S 652 - -#define SRST_H_TRNG_NS 653 -#define SRST_D_SDMMC_BUFFER 654 -#define SRST_H_SDMMC 655 -#define SRST_H_SDMMC_BUFFER 656 -#define SRST_SDMMC 657 -#define SRST_P_TRNG_CHK 658 -#define SRST_TRNG_S 659 - -#endif diff --git a/include/eeprom.h b/include/eeprom.h index e223e4c767074e7a46cdebe8b2658fb219cb3fad..f9c6542ba762b51c7b6f592d72715bfa837f1a82 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -8,8 +8,6 @@ #define __EEPROM_LEGACY_H #if defined(CONFIG_CMD_EEPROM) || defined(CONFIG_ENV_IS_IN_EEPROM) -#include - void eeprom_init(int bus); int eeprom_read(uint dev_addr, uint offset, uchar *buffer, uint cnt); int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env deleted file mode 100644 index d56b14f517264da97fa4ff588ca3361a3dc24a2f..0000000000000000000000000000000000000000 --- a/include/env/adi/adi_boot.env +++ /dev/null @@ -1,122 +0,0 @@ -/* - * A target board needs to set these variables for the commands below to work: - * - * - adi_stage2_offset, the location of stage2-boot.ldr on the SPI flash - * - adi_image_offset, location of the fitImage on the SPI flash - * - adi_rfs_offset, location of the RFS on the SPI flash - * - loadaddr, where you want to load things - * - jffs2file, name of the jffs2 file for update, ex adsp-sc5xx-tiny-adsp-sc573.jffs2 - */ - -#ifdef CONFIG_SC59X_64 -#define EARLY_PRINTK earlycon=adi_uart,0x31003000 -#else -#define EARLY_PRINTK earlyprintk=serial,uart0,CONFIG_BAUDRATE -#endif - -/* Config options */ -imagefile=fitImage -ethaddr=02:80:ad:20:31:e8 -eth1addr=02:80:ad:20:31:e9 -uart_console=CONFIG_UART_CONSOLE -#ifdef CONFIG_SC59X_64 -fdt_high=0xffffffffffffffff -initrd_high=0xffffffffffffffff -#else -fdt_high=0xffffffff -initrd_high=0xffffffff -#endif - -/* Helper routines */ -init_ethernet=mii info; - dhcp; - setenv serverip ${tftpserverip} - -/* Args for each boot mode */ -adi_bootargs=EARLY_PRINTK console=ttySC0,CONFIG_BAUDRATE vmalloc=512M -ramargs=setenv bootargs ${adi_bootargs} - -addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off - -/* Boot modes are selectable and should be defined in the board env before including */ -#if defined(USE_NFS) -// rootpath is set by CONFIG_ROOTPATH -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs} -nfsboot=run init_ethernet; - tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; - run nfsargs; - run addip; - bootm ${loadaddr} -#endif - -#if defined(USE_MMC) -mmcargs=setenv bootargs root=/dev/mmcblk0p1 rw rootfstype=ext4 rootwait ${adi_bootargs} -mmcboot=mmc rescan; - ext4load mmc 0:1 ${loadaddr} /boot/${imagefile}; - run mmcargs; - bootm ${loadaddr} -#endif - -#if defined(USE_SPI) || defined(USE_OSPI) -spiargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 ${adi_bootargs} -spiboot=run spiargs; - sf probe ${sfdev}; - sf read ${loadaddr} ${adi_image_offset} ${imagesize}; - bootm ${loadaddr} -#endif - -#if defined(USE_OSPI) -ospiboot=run spiboot -#endif - -#if defined(USE_RAM) -ramboot=run init_ethernet; - tftp ${loadaddr} ${tfpt_dir_prefix}${imagefile}; - run ramargs; - bootm ${loadaddr} -#endif - -/* Update commands */ -stage1file=stage1-boot.ldr -stage2file=stage2-boot.ldr - -#if defined(USE_SPI) || defined(USE_OSPI) -update_spi_uboot_stage1=tftp ${loadaddr} ${tftp_dir_prefix}${stage1file}; - sf probe ${sfdev}; - sf update ${loadaddr} 0x0 ${filesize} -update_spi_uboot_stage2=tftp ${loadaddr} ${tftp_dir_prefix}${stage2file}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_stage2_offset} ${filesize} -update_spi_uboot=run update_spi_uboot_stage1; - run update_spi_uboot_stage2; -update_spi_fit=tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_image_offset} ${filesize}; - setenv imagesize ${filesize} -update_spi_rfs=tftp ${loadaddr} ${tftp_dir_prefix}${jffs2file}; - sf probe ${sfdev}; - sf update ${loadaddr} ${adi_rfs_offset} ${filesize} - -start_update_spi=run init_ethernet; - run update_spi_uboot; - run update_spi_fit; - run update_spi_rfs; -start_update_spi_uboot_only=run init_ethernet; - run update_spi_uboot; -#endif - -#if defined(USE_SPI) -update_spi=setenv sfdev CONFIG_SC_BOOT_SPI_BUS:CONFIG_SC_BOOT_SPI_SSEL; - setenv bootcmd run spiboot; - setenv argscmd spiargs; - run start_update_spi; - saveenv -#endif - -#if defined(USE_OSPI) -update_ospi=setenv sfdev CONFIG_SC_BOOT_OSPI_BUS:CONFIG_SC_BOOT_OSPI_SSEL; - setenv bootcmd run ospiboot; - setenv argscmd spiargs; - run start_update_spi; - saveenv -#endif diff --git a/include/env_callback.h b/include/env_callback.h index 8e500aaaf806d7b95d5242c0e72c258a2da0f621..23bc650c162de4bd22813406ec1321dff3c204e7 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -7,7 +7,6 @@ #ifndef __ENV_CALLBACK_H__ #define __ENV_CALLBACK_H__ -#include #include #include #include diff --git a/include/env_default.h b/include/env_default.h index 076ffdd44e9bc8c5c30e57aed3bca0e00b897f19..8ee500d1709c15526dfb277c8be0d86d7a74e317 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -7,7 +7,6 @@ * Andreas Heppel */ -#include #include #include diff --git a/include/env_flags.h b/include/env_flags.h index 2476043b0e38abdb94662f34a45a31a3f1e4cbfb..d785f87cdcbe11f342a24206b6dc2c0bc74a2d16 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -7,8 +7,6 @@ #ifndef __ENV_FLAGS_H__ #define __ENV_FLAGS_H__ -#include - enum env_flags_vartype { env_flags_vartype_string, env_flags_vartype_decimal, diff --git a/include/extension_board.h b/include/extension_board.h index 87d404c007461f66dcd2a7d23dea044961fbf0d1..3b75b5ba9f7ca27cf2755e64aa42d78ee8277e9c 100644 --- a/include/extension_board.h +++ b/include/extension_board.h @@ -7,8 +7,6 @@ #ifndef __EXTENSION_SUPPORT_H #define __EXTENSION_SUPPORT_H -#include - struct extension { struct list_head list; char name[32]; diff --git a/include/flash.h b/include/flash.h index 0f7369774117c0cdf28635ac2aa96b5cf871d0f3..3710a2731b760b2500eba76b4b69ef271b451825 100644 --- a/include/flash.h +++ b/include/flash.h @@ -7,8 +7,6 @@ #ifndef _FLASH_H_ #define _FLASH_H_ -#include - /*----------------------------------------------------------------------- * FLASH Info: contains chip specific data, per FLASH bank */ diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 9f070726acb21c8bfcf06f97994394b702de8ba1..44547645df8793dbce5e1db3d13059e204600480 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -7,7 +7,7 @@ #define _FSL_ERRATA_H #if defined(CONFIG_PPC) -#include +#include #elif defined(CONFIG_ARCH_LS1021A) #include #elif defined(CONFIG_FSL_LAYERSCAPE) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 4991d93220074d7ea3d31b178b8afe9a694e2575..f9a0a7017d4a390657c42d58f6d80c60252fca07 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,8 +12,6 @@ #include #ifdef CONFIG_ARM #include -#else -#include #endif #define FSL_IFC_V1_1_0 0x01010000 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index 54d6e0ab3772e6637ff635db18c0280b1356dae9..5297c0b3f9b6ec19a152f81dbe6f87cca7a808d7 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -7,9 +7,6 @@ #ifndef __FSL_IMMAP_H #define __FSL_IMMAP_H - -#include - /* * DDR memory controller registers * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. diff --git a/include/fuse.h b/include/fuse.h index 4519821af7ea7437f6cddfe3b02c8ced418f1c7f..d48dcdfa64744abeca62447755680cd37143cccc 100644 --- a/include/fuse.h +++ b/include/fuse.h @@ -11,8 +11,6 @@ #ifndef _FUSE_H_ #define _FUSE_H_ -#include - /* * Read/Sense/Program/Override interface: * bank: Fuse bank diff --git a/include/gzip.h b/include/gzip.h index 5e0d0ec07fbccb7a14862efea44495e57619a7d0..e578b283edcd56f81217a4e029ae8823cf6f7f8f 100644 --- a/include/gzip.h +++ b/include/gzip.h @@ -7,8 +7,6 @@ #ifndef __GZIP_H #define __GZIP_H -#include - struct blk_desc; /** diff --git a/include/handoff.h b/include/handoff.h index c0ae7b19a75949ebfec5109131486d7bd1ef7041..0104b834f2c4cfbceb445d01bf90508bdf182b8a 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -10,7 +10,6 @@ #if CONFIG_IS_ENABLED(HANDOFF) -#include #include /** diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index 1fe32d2dd687aa9f3b4f6add7bcbcfbe749f77c5..cba991e3574f7402639428c8af54d41ddb4c486d 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -7,7 +7,6 @@ #define __I2C_EEPROM #include -#include struct udevice; diff --git a/include/init.h b/include/init.h index 2c10171359cf36b3baa0e015643459e14038e2d1..630d86729c4e3df102a364c027a8e92b061bb69c 100644 --- a/include/init.h +++ b/include/init.h @@ -401,8 +401,6 @@ void bdinfo_print_size(const char *name, uint64_t size); /* Show arch-specific information for the 'bd' command */ void arch_print_bdinfo(void); -struct cmd_tbl; - int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __ASSEMBLY__ */ diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h index fa4600e84fc0628392f7cd11ede664b3746cd5cc..9346d7ee9f1b6376097337181565f6202bc12f1b 100644 --- a/include/jffs2/load_kernel.h +++ b/include/jffs2/load_kernel.h @@ -10,7 +10,6 @@ *-----------------------------------------------------------------------*/ #include -#include /* mtd device types */ #define MTD_DEV_TYPE_NOR 0x0001 diff --git a/include/libata.h b/include/libata.h index fa39d21a44a0e8336beb12ca824f84fab61876c6..a55e9315a73010070c83694c6cb49caac1cc8c83 100644 --- a/include/libata.h +++ b/include/libata.h @@ -10,7 +10,6 @@ #ifndef __LIBATA_H__ #define __LIBATA_H__ -#include enum { /* various global constants */ diff --git a/include/linux/compat.h b/include/linux/compat.h index 6238145161759072ad47cb7249a16a286eb794c8..f8e3570d1ad2e5edd89d498d188d12718f0d1754 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -5,7 +5,6 @@ #include #include #include -#include #include diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h index 2dbf988863f9560226101f3f53a18429073850e8..f08e700a1daf66b65bf1e5b3c8d4d00dbec86f91 100644 --- a/include/linux/mtd/omap_gpmc.h +++ b/include/linux/mtd/omap_gpmc.h @@ -8,8 +8,6 @@ #ifndef __ASM_OMAP_GPMC_H #define __ASM_OMAP_GPMC_H -#include - /* Maximum Number of Chip Selects */ #define GPMC_CS_NUM 8 diff --git a/include/mailbox.h b/include/mailbox.h index e70266fb61c9455b68c2e32f248631878cf55e1c..323b6c2bc5d8f7983a6b4f5d2564c1bb64bd2f3d 100644 --- a/include/mailbox.h +++ b/include/mailbox.h @@ -6,8 +6,6 @@ #ifndef _MAILBOX_H #define _MAILBOX_H -#include - /** * A mailbox is a hardware mechanism for transferring small fixed-size messages * and/or notifications between the CPU on which U-Boot runs and some other diff --git a/include/mmc.h b/include/mmc.h index 7f1900363b91fc748795fa85f48da33b804f7148..4b8327f1f93b6bebdaa1c8e968b46df311afde73 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -18,6 +18,13 @@ struct bd_info; +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#define MMC_SUPPORTS_TUNING +#endif +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) +#define MMC_SUPPORTS_TUNING +#endif + /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ #define SD_VERSION_SD (1U << 31) #define MMC_VERSION_MMC (1U << 30) @@ -478,7 +485,7 @@ struct dm_mmc_ops { */ int (*get_wp)(struct udevice *dev); -#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) +#ifdef MMC_SUPPORTS_TUNING /** * execute_tuning() - Start the tuning process * diff --git a/include/mpc85xx.h b/include/mpc85xx.h index ff86c7c12e0c05918c3b60fd66b0abc2c3c99c0c..636734dd3c63afc8595b22e890e20579513a458b 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -6,7 +6,6 @@ #ifndef __MPC85xx_H__ #define __MPC85xx_H__ -#include #if defined(CONFIG_E500) #include #endif diff --git a/include/nand.h b/include/nand.h index cdba7384ad1439a08df0cb9fb39835f03a78bcae..220ffa202ef93436dfa3cd9d1b1ba72f70be5841 100644 --- a/include/nand.h +++ b/include/nand.h @@ -8,6 +8,8 @@ #ifndef _NAND_H_ #define _NAND_H_ +#include + extern void nand_init(void); void nand_reinit(void); unsigned long nand_size(void); diff --git a/include/netdev.h b/include/netdev.h index 2a06d9a261bbe78e4fa8a8492417cdca805bc3b6..2a7f40e5040ee0a88e589f16ad8bdadbd4ec650c 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -10,12 +10,9 @@ #ifndef _NETDEV_H_ #define _NETDEV_H_ - -#include #include struct udevice; -struct bd_info; /* * Board and CPU-specific initialization functions diff --git a/include/pci.h b/include/pci.h index ea3b73923d60c4ea55fdd15d01af019f86d3f40c..aad233769a3508d8e48323d31513f6014ebc6f98 100644 --- a/include/pci.h +++ b/include/pci.h @@ -520,7 +520,6 @@ #ifndef __ASSEMBLY__ -#include #include #ifdef CONFIG_SYS_PCI_64BIT diff --git a/include/phy_interface.h b/include/phy_interface.h index b74f4ccd84ad240c08c275c482b1f0f4a75d8d8d..31be3228c7c4e8a95fb31653f910c415249ca437 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -11,7 +11,6 @@ #define _PHY_INTERFACE_H #include -#include typedef enum { PHY_INTERFACE_MODE_NA, /* don't touch */ diff --git a/include/ram.h b/include/ram.h index 3600bb57a6cfbd6d6adabd68c10f3b156216c6be..2fc971df465a55783871ee02983343fab74acca8 100644 --- a/include/ram.h +++ b/include/ram.h @@ -7,8 +7,6 @@ #ifndef __RAM_H #define __RAM_H -#include - struct udevice; struct ram_info { diff --git a/include/s_record.h b/include/s_record.h index aab09d9c3c81deabb7c186b4bc41572badb81f6f..3ece695941d3f68e837d8579599b73b656562013 100644 --- a/include/s_record.h +++ b/include/s_record.h @@ -4,8 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include - /*-------------------------------------------------------------------------- * * Motorola S-Record Format: diff --git a/include/sm.h b/include/sm.h index fbc156ad68a75e1e50417150a410fa19daed34d6..afa9c89055e5c404086ca3bfe2110bfa78809285 100644 --- a/include/sm.h +++ b/include/sm.h @@ -19,7 +19,7 @@ * implementation of the driver you are using. */ -#include +#include #include struct udevice; diff --git a/include/splash.h b/include/splash.h index 83c6fa9767f04ff1a8ce3f0890d1760f3f80b65f..c3922375987da02ef0bb95d52b28299234fa60a8 100644 --- a/include/splash.h +++ b/include/splash.h @@ -23,7 +23,6 @@ #define _SPLASH_H_ #include -#include enum splash_storage { SPLASH_STORAGE_NAND, diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index c1e9f67068d4f194b5a15df6f51d580abaf096e1..09fee594d263fa94e1060cf113f9e603b521b99d 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -14,8 +14,6 @@ #ifndef _SHA1_H #define _SHA1_H -#include - #ifdef __cplusplus extern "C" { #endif diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index a4fe176c0b46a0a2ad86cb404f27b29a715e4864..9aa1251789a34f1b824fe0cd9f9c9445f4dde464 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -1,8 +1,6 @@ #ifndef _SHA256_H #define _SHA256_H -#include - #define SHA256_SUM_LEN 32 #define SHA256_DER_LEN 19 diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h index 90bd96a3f8c2065e36e5f627b1dba3a866cab318..516729d7750669bed525de86dea19b9355352a83 100644 --- a/include/u-boot/sha512.h +++ b/include/u-boot/sha512.h @@ -1,8 +1,6 @@ #ifndef _SHA512_H #define _SHA512_H -#include - #define SHA384_SUM_LEN 48 #define SHA384_DER_LEN 19 #define SHA512_SUM_LEN 64 diff --git a/include/virtio.h b/include/virtio.h index 17f894a79e3162d246ec9c160678386fd25ac023..8113a59d7958d691b1b56ddd8fc616a577612f4a 100644 --- a/include/virtio.h +++ b/include/virtio.h @@ -24,7 +24,6 @@ #include #include #include -#include #define VIRTIO_ID_NET 1 /* virtio net */ #define VIRTIO_ID_BLOCK 2 /* virtio block */ #define VIRTIO_ID_RNG 4 /* virtio rng */ diff --git a/include/xen/events.h b/include/xen/events.h index f0a8ef32d00b5e8909725c6e2b0800fc9d09cad7..82bd18b48c88dcb3a58ac5c572996b2338010941 100644 --- a/include/xen/events.h +++ b/include/xen/events.h @@ -15,7 +15,6 @@ #ifndef _EVENTS_H_ #define _EVENTS_H_ -#include #include #include diff --git a/net/arp.c b/net/arp.c index bc1e25f941f721d0d165cc185c62a49137885a9a..37848ad32fbd482591067b87152ed0516386b752 100644 --- a/net/arp.c +++ b/net/arp.c @@ -9,10 +9,10 @@ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de */ +#include #include #include #include -#include #include #include "arp.h" diff --git a/net/bootp.c b/net/bootp.c index 9dfb50749b499fd5a709050480fc566412158cea..86c56803c76eb146f42b42ad0da915d1ace51e11 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -8,6 +8,7 @@ * Copyright 2000-2004 Wolfgang Denk, wd@denx.de */ +#include #include #include #include diff --git a/net/cdp.c b/net/cdp.c index d4cfc587ee3563f23f6e0fc63319237dcae6c148..a8f890e75226f4b4198046fca67acd17ea8c2019 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -9,6 +9,7 @@ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de */ +#include #include #include "cdp.h" diff --git a/net/dhcpv6.c b/net/dhcpv6.c index 54619ee69836268c03be1709be353df401b3f64c..4aea779f6f24cd4ab1fe8dcefa6ddb5d3692bb35 100644 --- a/net/dhcpv6.c +++ b/net/dhcpv6.c @@ -7,6 +7,7 @@ /* Simple DHCP6 network layer implementation. */ +#include #include #include #include diff --git a/net/dns.c b/net/dns.c index c2f0ab98c8d040945551218ec4658412d8ec04c9..5b1fe5b0103747a0fe91c5c17bc69a8f2801dfb9 100644 --- a/net/dns.c +++ b/net/dns.c @@ -22,6 +22,7 @@ * this stuff is worth it, you can buy me a beer in return. */ +#include #include #include #include diff --git a/net/eth-uclass.c b/net/eth-uclass.c index e34d7af0229e2eafba9b6c84b069a1359cb74c88..193218a328b752007726ae487e71759c10d9010b 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -7,6 +7,7 @@ #define LOG_CATEGORY UCLASS_ETH +#include #include #include #include diff --git a/net/eth_bootdev.c b/net/eth_bootdev.c index 6ee54e3c79014b94023dfdc8968ae48bbf52dd80..869adf8cbbd31900339e432347417087937f949f 100644 --- a/net/eth_bootdev.c +++ b/net/eth_bootdev.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY UCLASS_BOOTSTD +#include #include #include #include diff --git a/net/eth_common.c b/net/eth_common.c index 89b5bb371897ee77e3de7cb50043aba90159123a..14d4c07b695d5d68076eafc146b4b0a0fd710bf3 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -5,6 +5,7 @@ * Joe Hershberger, National Instruments */ +#include #include #include #include diff --git a/net/fastboot_tcp.c b/net/fastboot_tcp.c index d1fccbc72386318824ac54abf90356bbb47c3d32..2eb52ea256796d217854afed3aab6a4ba62801bc 100644 --- a/net/fastboot_tcp.c +++ b/net/fastboot_tcp.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 The Android Open Source Project */ +#include #include #include #include diff --git a/net/fastboot_udp.c b/net/fastboot_udp.c index d1479510d61aa02f23bec74199531063a7e88b84..6fee441ab3b6e6476911a210bf28edc64bdc55da 100644 --- a/net/fastboot_udp.c +++ b/net/fastboot_udp.c @@ -3,6 +3,7 @@ * Copyright (C) 2016 The Android Open Source Project */ +#include #include #include #include diff --git a/net/link_local.c b/net/link_local.c index 179721333ffc3f0c3970dee13078a17b796cb36d..8aec3c79969b023e024820e0558072268a1e912e 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -11,6 +11,7 @@ * Licensed under the GPL v2 or later */ +#include #include #include #include diff --git a/net/mdio-mux-uclass.c b/net/mdio-mux-uclass.c index ee188b504d166ab8d64995e3832ae57755329edd..94b90e0657626b2cdbe342ac9d94f2893acb48a6 100644 --- a/net/mdio-mux-uclass.c +++ b/net/mdio-mux-uclass.c @@ -4,6 +4,7 @@ * Alex Marginean, NXP */ +#include #include #include #include diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 4f052ae432c659eb3c5ca5e10537eef2d9a62209..0ebfb2f1343a091f36169e5a05a5101ffee7faaf 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -4,6 +4,7 @@ * Alex Marginean, NXP */ +#include #include #include #include diff --git a/net/ndisc.c b/net/ndisc.c index d417c5987ac4a4de8fb544834f375ae6fa2ada62..d1cec0601c83ea10961f50bcc344399e0a3caa3b 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -9,6 +9,7 @@ /* Neighbour Discovery for IPv6 */ +#include #include #include #include diff --git a/net/net.c b/net/net.c index 23b5d3356afa1937ad8ef532026dde281d57c779..0fb2d2507734ebd8f4061f280d412fc3d36475e9 100644 --- a/net/net.c +++ b/net/net.c @@ -81,6 +81,7 @@ */ +#include #include #include #include diff --git a/net/net6.c b/net/net6.c index 4cff98df15cf15df21957c50419a77e8e6d12492..2dd64c0e1618a061ae424e0eea3fccd2c7e648ef 100644 --- a/net/net6.c +++ b/net/net6.c @@ -9,12 +9,12 @@ /* Simple IPv6 network layer implementation */ +#include #include #include #include #include #include -#include /* NULL IPv6 address */ struct in6_addr const net_null_addr_ip6 = ZERO_IPV6_ADDR; diff --git a/net/nfs.c b/net/nfs.c index acc7106f10d4564ddea80d1280ba2f8cf605ce43..c18282448ccd87bc11e09bfbdceb7e8ed9dddaf7 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -30,6 +30,7 @@ * September 27, 2018. As of now, NFSv3 is the default choice. If the server * does not support NFSv3, we fall back to versions 2 or 1. */ +#include #include #include #ifdef CONFIG_SYS_DIRECT_FLASH_NFS diff --git a/net/pcap.c b/net/pcap.c index c959e3e4e5114bda55e6a6d03b3a56466823661a..4036d8a3fa535c6e7246460449513acc89ed2386 100644 --- a/net/pcap.c +++ b/net/pcap.c @@ -3,10 +3,10 @@ * Copyright 2019 Ramon Fried */ +#include #include #include #include -#include #include #define LINKTYPE_ETHERNET 1 diff --git a/net/ping6.c b/net/ping6.c index 2479e08fd82f2d04fe48a8459608777ce4d54215..4882a17f510b72229aeed2f529f1772b31da114a 100644 --- a/net/ping6.c +++ b/net/ping6.c @@ -9,6 +9,7 @@ /* Simple ping6 implementation */ +#include #include #include #include "ndisc.h" diff --git a/net/rarp.c b/net/rarp.c index a6b564e314d47d2c5b55e2c3b4c5a3f1130b471f..231b6233c07a7f07e41d1a1842ee8780f556c063 100644 --- a/net/rarp.c +++ b/net/rarp.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ +#include #include #include #include diff --git a/net/sntp.c b/net/sntp.c index 73d1d87d38b1aff2b1cf66a17076510969e32859..dac0f8ceea1b9583a855b8f908f008df52962dc3 100644 --- a/net/sntp.c +++ b/net/sntp.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include diff --git a/net/tcp.c b/net/tcp.c index b0cc8a1fe3ed6d65ab244f497ac338ed2bb7a58a..a713e1dd6096134e45aa44367dce672167849dc8 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -17,6 +17,7 @@ * - TCP application (eg wget) * Next Step HTTPS? */ +#include #include #include #include diff --git a/net/tftp.c b/net/tftp.c index 6b16bdcbe4c2e685269177da4b7f9245d9ac7e57..2e335413492b714cdaaa594c2385553f0f19eca5 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -5,6 +5,7 @@ * Copyright 2011 Comelit Group SpA, * Luca Ceresoli */ +#include #include #include #include diff --git a/net/udp.c b/net/udp.c index 37162260d17528137f2680a5aa8045cd60453e91..a93822f511cdaa2da66f5415c3075e6caef7e469 100644 --- a/net/udp.c +++ b/net/udp.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Philippe Reynes */ +#include #include #include diff --git a/net/wget.c b/net/wget.c index f1dd7abeff69a75510f650f646ea71c932177b83..abab371e58edbcbddbf96cabb67af870f420b370 100644 --- a/net/wget.c +++ b/net/wget.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include diff --git a/net/wol.c b/net/wol.c index 96478ba5751e78c902275ed4da65303b292365fe..0a625668a992ef4fd6feb8c8cf4084b6020ccfd8 100644 --- a/net/wol.c +++ b/net/wol.c @@ -3,6 +3,7 @@ * Copyright 2018 Lothar Felten, lothar.felten@gmail.com */ +#include #include #include #include diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index 766eafa00e71b93bf32fbc68f2f73c0dce076a74..68da8ff417167f118934efabd06109ebb812f824 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -8,7 +8,7 @@ * Dave Liu */ -#include +#include #include #include #include diff --git a/post/drivers/flash.c b/post/drivers/flash.c index 21e2f940fe92185942d9ec77c20abf63a9c4fe7b..a1fcf1f135d901a6d2b30a6734fc61138ae09b30 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -7,7 +7,7 @@ */ #if CFG_POST & CFG_SYS_POST_FLASH -#include +#include #include #include #include diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 11c3c8323523f7e0aee25ffd35e5aa493f8e18d9..557d6329a4f0e815c65b06f9bf1ac4ead8d69f4c 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -21,7 +21,7 @@ * #endif */ -#include +#include #include #include #include diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 8d4ae6fc6f1ea37a0925531651d8d9a5325c58b0..1be2b41df45d2eb60eca42a59ced0114604bb614 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index 030954ef3dca8deec40182986b2e2f9876d124d8..cc7a49847ccdc1c0a051d98a211954f5d0cb8837 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include /* * RTC test diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index 3f525f516760340d7476afb2bcba4eab66106fe0..4f30216688005f6cf9a6ea6f084816ac52e49121 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index 9c9931c4f3a90f49bcbf24d7b3a1d1ec0885e793..0ec032dcb1529a7a36cdf12b25429cb350b595ca 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index 9237dd539979a187718d0b9e11015db84064d7f3..57f2b9694c332f792bb55684c9a8b293adb67bf2 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 6436586b2914871105b9c3a9d885995689113712..6e2bd636d74d019b9831aeddff27763ab3e26b00 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index 2899dece2c1d9004aa70a8dee6db4bb0b3df217a..751bce673785d24e98a34ece5999db4796024f3c 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index e41e6b3b97b11969b4e2b503f9a8a547c7ddb7c0..98a8c6392c3a22fa6ecc97353100b699a87e48a2 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 1e011f12159ebeeb78312fb6472aa6c94abc9244..3c7b611384675e46038f6c6bca08a46fa97f13ec 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index d6b7bc656f69368b8b25059afbbe6b1a17a63dab..9c1c886fc4f76e0af0f74a3ad6226a07948553bc 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 5e79c4c69843150ad113958f081a6d6a2965953f..01bac500383651f725643fb7370b33e80adaca64 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index a65ffcedb49a77914976217d271d3cbf048eb893..cc4aa0dca645901184222e4bad57e16131c81911 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 8ad256efa9f86a8c1bbd51f157c74bf221a1ac33..111a2013fb58d6785a4ef5a21c205cd67e8705c3 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 408c391ce42b84a6164aa91633cb605c295decba..63cc3eeafc3026b9b34a50da79409d7a38a8c7b4 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -7,7 +7,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index 4b8537ea3db3a709747bf9af64dfd5983013c813..4b4589664f1215a5c6a43c277c2abbd2b5d9d2c2 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -9,7 +9,7 @@ * This file is originally a part of the GCC testsuite. */ -#include +#include #include diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index 2afe27ab355958666f629f28f24a43e60d6efad9..59109f71e36a36e60df9a4b381fa01b175bb815c 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -6,7 +6,7 @@ * Author: Sergei Poselenov */ -#include +#include /* * FPU test diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index 6b86e55e409e26448af34b43d800cdfc182fcf4f..891aa95685fe8f2256c528a63024d933ce5983bb 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -9,7 +9,7 @@ * numbers) are rounded to within 0.5 ulp. PR other/14354. */ -#include +#include #include diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index 0a2a4222846c39485348880c966c9c32521dfb8a..e4ac6bf186f9e5db6a13d7d288baab740b62905c 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index 6f991443741c72bb110ff6c1b2a06f67c9ca94f1..4df45790ab65d0e95e91371ac7539aff680042b8 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index 35a9e9b83bf07bd17f0648b2e0bfdf57b70d7963..da2191322570f32eb65fa6c2fc539edaa99e8e38 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 2995eb358ef4d17d8433a0982461ceeae42dd0fd..b0b976f98af44b847c0d313e92d0f1ebb25f53b2 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 3ba3a7607ab3961c3751800dbfc981ff61a95acb..22cd4568fc88f12f3ed31b42bef61ddb56aaec14 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index bd59ac4f36b5c14feaf8aa8ee30bbe9fbd110865..a103df75eb1ab80e8345b616e4015b792ed0b84b 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 470ea37e77d0f7555f4b4d9b7805548ff10b1e55..71a4b6aba431b93733cfe15b5efa535939391b2c 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index c4ea5cf9ba9d0a565eb25b273651772db7822849..21e02bcb2664462fd01589152989c859eb524e4f 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index e65d7f023f9574753afb9964a70edff5e2d21a39..68339b05ef27b722473c67a207e0c06069620f5a 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index 0c3a2e6674b87b245c514472725e60959fb5c11c..885dd8cb095ec62f47ab0e337cbb7916cfa3901a 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 24ebc98d48df50a57b21f826ac04825525081282..62ac713ecff7fef0fb3899a34f8fe2940ae4b0c1 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index 28c70ec889775ebf4c8555d92e2f9d083484928e..7985669ba6eb7a02e6cebaca1940017dc820a38f 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 7f6a898d63972b0cc3fa23d9f33e4490f8aac1bb..33d1a1d8d91df4d17cf5f5d3c9e8ef2680727e9e 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include /* diff --git a/post/post.c b/post/post.c index 705f94ccc9190f9165e31e002fcaafdc9edf634a..946d9094d451fab9116fbc4d93061988fd985273 100644 --- a/post/post.c +++ b/post/post.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include +#include #include #include #include diff --git a/post/tests.c b/post/tests.c index 208710a48ba7ceed911a43a271d35876ed7a70b5..8cea428fcdc71f76b6e6e028bc7a1c32a83ddebe 100644 --- a/post/tests.c +++ b/post/tests.c @@ -4,8 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include -#include +#include #include diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index b42f9b525feab8fa0dbfeb4183c8cd0546ffa9ab..8208ffe2274411ccd89b6288e016f45afe7379aa 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -45,7 +45,7 @@ c_flags := $(KBUILD_CFLAGS) $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) \ quiet_cmd_autoconf_dep = GEN $@ cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M -MP $(c_flags) \ - -MQ include/config/auto.conf include/config.h > $@ || { \ + -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \ rm $@; false; \ } include/autoconf.mk.dep: include/config.h FORCE @@ -70,7 +70,7 @@ quiet_cmd_autoconf = GEN $@ quiet_cmd_u_boot_cfg = CFG $@ cmd_u_boot_cfg = \ - $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM include/config.h > $@.tmp && { \ + $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ grep 'define CONFIG_' $@.tmp | \ sed '/define CONFIG_IS_ENABLED(/d;/define CONFIG_IF_ENABLED_INT(/d;/define CONFIG_VAL(/d;' > $@; \ rm $@.tmp; \ diff --git a/scripts/gen_ll_addressable_symbols.sh b/scripts/gen_ll_addressable_symbols.sh index 13f670ae0ef047febafe0194debcfcb65b7594d5..d0864804aafba12454bf1241d5cbcdb94d0b05a4 100755 --- a/scripts/gen_ll_addressable_symbols.sh +++ b/scripts/gen_ll_addressable_symbols.sh @@ -10,6 +10,6 @@ set -e -echo '#include ' +echo '#include ' $@ 2>/dev/null | grep -oe '_u_boot_list_2_[a-zA-Z0-9_]*_2_[a-zA-Z0-9_]*' | \ sort -u | sed -e 's/^\(.*\)/extern char \1[];\n__ADDRESSABLE(\1);/' diff --git a/test/bloblist.c b/test/bloblist.c index 7c63682908a579c6427ecdfd9ccd4241f2afc71f..1c60bbac36c3a8e05de3cb36ef86732102899846 100644 --- a/test/bloblist.c +++ b/test/bloblist.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, Google Inc. All rights reserved. */ +#include #include #include #include diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 6e940002f8484c489b5bb7340a2893a45448f801..0702fccdae60077cf9635b6584085f39b495e3c6 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 4511cfa7f9bf77eddcf53a5a65a0180a3722dc83..674d4c05f83fd7ae5ab72d29e829ef079830d61d 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c index 113b789ea7936babc6e8d2a449afcd01fa225a3c..e498eee036eb993c6bea5601f8daf9ff207c5943 100644 --- a/test/boot/bootmeth.c +++ b/test/boot/bootmeth.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c index e50539500a02f5a96222165e1ab8cff670af7d2e..cc97e255e5cb08052af42564a1790d63ec96fbef 100644 --- a/test/boot/bootstd_common.c +++ b/test/boot/bootstd_common.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/cedit.c b/test/boot/cedit.c index fd19da0a0c0fcd4208d7772f7176fb14da0d77fa..aa4171904864529e3358faf7cc61d624d94146de 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/expo.c b/test/boot/expo.c index 6ea0184373d5016bc5fa3e7530e74b114978d287..714fdfa415d10c0dc8f95eff061be2ad5455da17 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/image.c b/test/boot/image.c index 0894e30587f173f22925769c669fec671a055aa3..2844b057859ef706410c8d19ce1173cb3d1d6773 100644 --- a/test/boot/image.c +++ b/test/boot/image.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/measurement.c b/test/boot/measurement.c index 29be495412d3b3e1d3f27c3da2f7ee5fa585571f..9db2ed324c2aa85b01c6ec5db2daee30d6c4ad87 100644 --- a/test/boot/measurement.c +++ b/test/boot/measurement.c @@ -6,6 +6,7 @@ * Written by Eddie James */ +#include #include #include #include diff --git a/test/boot/vbe_fixup.c b/test/boot/vbe_fixup.c index 540816e42b000c3b8b98c0a02b8f7079199e115c..eba5c4ebe6c0355c3576012686a2958e3f297bb5 100644 --- a/test/boot/vbe_fixup.c +++ b/test/boot/vbe_fixup.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c index 3672b744e5fb729e56a0a276a70ca4d4531dbd02..5e61840652cf365d2b0e1f80364d2a0e410960d9 100644 --- a/test/boot/vbe_simple.c +++ b/test/boot/vbe_simple.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/bootm.c b/test/bootm.c index 26c15552bf63569cc2d69dbac9d76015e447709e..4bb3ca0655cf8b0a7c5bb8ecd5297b90eb814aae 100644 --- a/test/bootm.c +++ b/test/bootm.c @@ -5,6 +5,7 @@ * Copyright 2020 Google LLC */ +#include #include #include #include diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c index 7b8f49fd3751abd1e84936525d96b397fa59a104..1eb5955db1726ab46cb470c69581071bcf490efd 100644 --- a/test/cmd/addrmap.c +++ b/test/cmd/addrmap.c @@ -5,6 +5,7 @@ * Copyright (C) 2021, Bin Meng */ +#include #include #include #include diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c index 38f40b72f5e4cc0b8407e59582632a5d29e662b5..9a44a397e8a0148213e1839604f6a730de8b96b8 100644 --- a/test/cmd/armffa.c +++ b/test/cmd/armffa.c @@ -8,6 +8,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 027848c3e24c0f5736e9d3919e54ffe5ca8056aa..4977d01f62d615507d35d2d3f0577fa683b13746 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -5,6 +5,7 @@ * Copyright 2023 Marek Vasut */ +#include #include #include #include diff --git a/test/cmd/exit.c b/test/cmd/exit.c index d310ec8531be1269e198088e84cf78e7d0e32b41..7e160f7e4bb79b9d0cfaac8427c8c7eaad7751fa 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -5,6 +5,7 @@ * Copyright 2022 Marek Vasut */ +#include #include #include #include diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index a0faf5aca904b7ae468c6048a264873874211479..5470855217586452172a4c6515dc48b188f6d886 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -5,6 +5,7 @@ * Copyright 2022 Google LLC */ +#include #include #include #include diff --git a/test/cmd/font.c b/test/cmd/font.c index a8905ce617e828945ea61947fe55c4ae9f790ada..1fe05c1ead51b87971a92db2416d674f064a2bd8 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -5,6 +5,7 @@ * Copyright 2022 Google LLC */ +#include #include #include #include diff --git a/test/cmd/history.c b/test/cmd/history.c index 6964bfa9e1ece15b077260c9b78cafa38ac7a2d2..06517fcdbb518cd22c757b7f47825f883245d898 100644 --- a/test/cmd/history.c +++ b/test/cmd/history.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c index dff8a97d1396d5f000b815711b591d6085a158c8..41e005ac59236407c3accaacf832e3513a2d9df8 100644 --- a/test/cmd/loadm.c +++ b/test/cmd/loadm.c @@ -9,6 +9,7 @@ * Rui Miguel Silva */ +#include #include #include #include diff --git a/test/cmd/mem.c b/test/cmd/mem.c index f1bbab6055be05444809b98a63032a336409d241..d76f47cf3115297bff68dc01faeb0e5028ff01c3 100644 --- a/test/cmd/mem.c +++ b/test/cmd/mem.c @@ -5,6 +5,7 @@ * Copyright 2020 Google LLC */ +#include #include #include #include diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c index 55ad2fac1e340c9a9729078ae927fdaf359949f7..f80c9c406873f243ffe85931fb9e6be163684a95 100644 --- a/test/cmd/mem_search.c +++ b/test/cmd/mem_search.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c index 2a64143eecd30ecef06b168ee6303673ae01494b..fd96f4fba6c464166e5824b0393e4fa591faf3e7 100644 --- a/test/cmd/pci_mps.c +++ b/test/cmd/pci_mps.c @@ -7,6 +7,7 @@ * Written by Stephen Carlson */ +#include #include #include #include diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c index 4253baa56466cbe7ed800a7b20cf686da27d4240..df40bb77435542adadd5547d66cf635b0c61ef32 100644 --- a/test/cmd/pinmux.c +++ b/test/cmd/pinmux.c @@ -5,6 +5,7 @@ * Copyright (C) 2021, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/test/cmd/rw.c b/test/cmd/rw.c index edd762e4d58f6f90867a9f936c21621f3c5c5f40..98302bf047b15ab4910ff98d06f98a2bba25406c 100644 --- a/test/cmd/rw.c +++ b/test/cmd/rw.c @@ -3,6 +3,7 @@ * Tests for read and write commands */ +#include #include #include #include diff --git a/test/cmd/seama.c b/test/cmd/seama.c index b60f6550b13c9b3403945196d2369254ff14927b..b1b56930c64645f891dee3788d0b25e1dcdf42e3 100644 --- a/test/cmd/seama.c +++ b/test/cmd/seama.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Linus Walleij */ +#include #include #include #include diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c index d50ce5803c39927e408186e621162ff8b9ace206..ee329e94b85b43f5b13d977d48fb4d03510e0d4a 100644 --- a/test/cmd/setexpr.c +++ b/test/cmd/setexpr.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/cmd/temperature.c b/test/cmd/temperature.c index 364972626b1fe2fdc6bc3a327f3be63700a76304..2a1ea0611dc453be95aa5f5484adac1551e62e04 100644 --- a/test/cmd/temperature.c +++ b/test/cmd/temperature.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Sartura Ltd. */ +#include #include #include #include diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c index cde74ebeb616228ce96a652da575019506fe0653..091e4f823c9081605ff27cf11029d0cb9fe90a70 100644 --- a/test/cmd/test_echo.c +++ b/test/cmd/test_echo.c @@ -5,6 +5,7 @@ * Copyright 2020, Heinrich Schuchadt */ +#include #include #include #include diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c index 3703290350b384a534135bf0621ee110bcf51369..2b85cce327100a6f5ca8e2f9c9c43ab9bc2563d3 100644 --- a/test/cmd/test_pause.c +++ b/test/cmd/test_pause.c @@ -5,6 +5,7 @@ * Copyright 2022, Samuel Dionne-Riel */ +#include #include #include #include diff --git a/test/cmd/wget.c b/test/cmd/wget.c index 356a4dcd8fadbf0e7b69f46b144f395d20a6952c..ed83fc94a5e21522b54c14b46f1b81a0201ad32e 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -6,6 +6,7 @@ * Ying-Chun Liu (PaulLiu) */ +#include #include #include #include diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 4e4aa8f1cb2702bbdac21493e7c17f4a42bb1dfb..0677ce0cd1741fd81c597f13ebcb6a3dbdbb02ff 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -4,9 +4,9 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ +#include #include #include -#include #include #include #include diff --git a/test/command_ut.c b/test/command_ut.c index 2b8d28d7ae325d7bd6ec9b001ccb1b372e6a9e2c..a74bd109e153edcd68160660fee2d777be7daa09 100644 --- a/test/command_ut.c +++ b/test/command_ut.c @@ -5,6 +5,7 @@ #define DEBUG +#include #include #include #include diff --git a/test/common/cmd_ut_common.c b/test/common/cmd_ut_common.c index 2f03a58af47c210e84eb646236c6cab41e3d0d42..2c0267801b239bf13d97e591660b6e80c9c06284 100644 --- a/test/common/cmd_ut_common.c +++ b/test/common/cmd_ut_common.c @@ -6,6 +6,7 @@ * Unit tests for common functions */ +#include #include #include #include diff --git a/test/common/cread.c b/test/common/cread.c index e159caed04196e5096e802451cfddb0f8b1540a3..4edc77396043cf60476174971156cf99f41bcad8 100644 --- a/test/common/cread.c +++ b/test/common/cread.c @@ -3,8 +3,8 @@ * Copyright 2023 Google LLC */ +#include #include -#include #include #include #include diff --git a/test/common/cyclic.c b/test/common/cyclic.c index 461f8cf91f45ed0e530e8648f91fc946b663bca0..6e758e89dbdb456b366385d581d51d52f6731067 100644 --- a/test/common/cyclic.c +++ b/test/common/cyclic.c @@ -3,6 +3,7 @@ * Copyright (C) 2022 Stefan Roese */ +#include #include #include #include diff --git a/test/common/event.c b/test/common/event.c index de433d34f22b0452c7c734ecd4ffe6b53b72adf0..b462694fc3b6973f68ad430eca8a09d6515758d7 100644 --- a/test/common/event.c +++ b/test/common/event.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/common/test_autoboot.c b/test/common/test_autoboot.c index 4ba1dcc8091c2f036c12f419dd6f2cb5c88a06b5..42a1e4ab1fa0ae39b114061e690a0d5b3f20b2e5 100644 --- a/test/common/test_autoboot.c +++ b/test/common/test_autoboot.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include diff --git a/test/compression.c b/test/compression.c index aa1d38bb7bc53b6124e6955c5e725f49b216a3e1..3df90819a1fb7611c32448e9f563ed7fa5cd46b4 100644 --- a/test/compression.c +++ b/test/compression.c @@ -3,6 +3,7 @@ * Copyright (c) 2013, The Chromium Authors */ +#include #include #include #include diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 4db2171a4b170e63789ef6903c8f5431fc894885..f14b3962f8457494081e3c3ca643262a11742cb6 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c index 87bd8ae6749b717c9e0b0c8bdf4aa27c7030b310..44bcabda6bc12083559c1cf0ba4220262997113d 100644 --- a/test/dm/acpi_dp.c +++ b/test/dm/acpi_dp.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 7113219792e602504f3677a707b7de36ce1025a9..15b2b6f64a0316a585b9b48d71e122eccb12b6d1 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/adc.c b/test/dm/adc.c index a26a677074a4dce5c83e2c293964a3d97476ca66..740167e16b8edf4c335e95f8d94c69d16d01ebc6 100644 --- a/test/dm/adc.c +++ b/test/dm/adc.c @@ -6,6 +6,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/test/dm/audio.c b/test/dm/audio.c index 3d1d821f3234b94893559444e2e8f26ce0b00e06..add15ae20e00e8f6487681c515eecd65b732ce38 100644 --- a/test/dm/audio.c +++ b/test/dm/audio.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/axi.c b/test/dm/axi.c index 0900a9b5485e213fd5773d4517ca6f9ed249f689..dc029df5e44373eddb04249f9b537a2281c2e5fc 100644 --- a/test/dm/axi.c +++ b/test/dm/axi.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/dm/blk.c b/test/dm/blk.c index d03aec32f6c73b1815b083081b076cc1ed6a20bc..799f1e4dc75b27aacc356b6a7bddb41c8cd2b993 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/blkmap.c b/test/dm/blkmap.c index 7581e62df3bb1b5d34cd5ad0073398b040a8983f..7a163d6eaef2e682b3acc02d2e44d339b4dad79c 100644 --- a/test/dm/blkmap.c +++ b/test/dm/blkmap.c @@ -4,6 +4,7 @@ * Author: Tobias Waldekranz */ +#include #include #include #include diff --git a/test/dm/bootcount.c b/test/dm/bootcount.c index 9cfc7d48aac0e77c828364b255daab14bf0b67d4..b77b472d1f2635ea7b577c9fff8bd169c7a49d07 100644 --- a/test/dm/bootcount.c +++ b/test/dm/bootcount.c @@ -3,6 +3,7 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/test/dm/bus.c b/test/dm/bus.c index a338c7f567c1183a622d9125d6be7ca3ff938561..89a6aa6554cbbfd9d0f571dcd659b3ed9644ff14 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -3,6 +3,7 @@ * Copyright (c) 2014 Google, Inc */ +#include #ifdef CONFIG_SANDBOX #include #include diff --git a/test/dm/button.c b/test/dm/button.c index 9157ec928783d84de929a6884e35189c89d2c7c6..830d96fbef345c5cdc4cff5294e0181d9e43217a 100644 --- a/test/dm/button.c +++ b/test/dm/button.c @@ -5,6 +5,7 @@ * Based on led.c */ +#include #include #include #include diff --git a/test/dm/cache.c b/test/dm/cache.c index d2f3bfe2caf326c94abd0b28772c8a259a193046..bbd8f98d007b04a6467f9376842aa837133bc628 100644 --- a/test/dm/cache.c +++ b/test/dm/cache.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Intel Corporation */ +#include #include #include diff --git a/test/dm/clk.c b/test/dm/clk.c index a966471dbd9621284675ea495cd8e99e440a9274..57fabbdce08b31a15506870c2466105ab8fa72e3 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 15fba31b962fed37c3c17f275e38df2495780681..61dad8d85273e9547e52d19956cdaa7294375135 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -4,6 +4,7 @@ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de */ +#include #include #include #include diff --git a/test/dm/core.c b/test/dm/core.c index 4741c81bcc1d6ae392c1bed14ba5713ba0ea5f0d..7f3f8d183bca4af336e60c32ad380e7d166f9d88 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -5,6 +5,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba810599666944682ee0bd8f10d545325632e5..5734cd0a92d3ff0325fde323c533b9d19f40faca 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/dm/cros_ec.c b/test/dm/cros_ec.c index ac0055f0acd6ef4671345573028a3fc9f3a5771e..30cb70e08826ab7f02872e16b1a4ed00467f30fc 100644 --- a/test/dm/cros_ec.c +++ b/test/dm/cros_ec.c @@ -3,6 +3,7 @@ * Copyright 2021 Google LLC */ +#include #include #include #include diff --git a/test/dm/cros_ec_pwm.c b/test/dm/cros_ec_pwm.c index f68ee6f33b8ce95bbd5ded6c63027f153f2ce959..f8d6e1e6c40f0150bf7d263e46310989483e5195 100644 --- a/test/dm/cros_ec_pwm.c +++ b/test/dm/cros_ec_pwm.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/test/dm/devres.c b/test/dm/devres.c index 95a470b9f1c128a94b4cae0fdd54175d78c67cc1..3df0f64362dc6c35aeaa3bb763327b9109b05bfa 100644 --- a/test/dm/devres.c +++ b/test/dm/devres.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/test/dm/dma.c b/test/dm/dma.c index 949710fdb4e3cdc399366b16961fdd4d6acb6716..cce47cb218039649519435c23b8a1a8e6c1232c4 100644 --- a/test/dm/dma.c +++ b/test/dm/dma.c @@ -6,6 +6,7 @@ * Grygorii Strashko */ +#include #include #include #include diff --git a/test/dm/dsi_host.c b/test/dm/dsi_host.c index 68686a40d9f9a45ab42ed658613fa1d508931261..6e0a5df704f583724b58915ea49e045d8faec472 100644 --- a/test/dm/dsi_host.c +++ b/test/dm/dsi_host.c @@ -4,6 +4,7 @@ * Author(s): Yannick Fertre for STMicroelectronics. */ +#include #include #include #include diff --git a/test/dm/efi_media.c b/test/dm/efi_media.c index 9d0ed0f075513675046bbc1593edd7c79486e50c..e343a0e9c85de0473ba3c9c3f4aeecb8a458d7d3 100644 --- a/test/dm/efi_media.c +++ b/test/dm/efi_media.c @@ -5,6 +5,7 @@ * Copyright 2021 Google LLC */ +#include #include #include #include diff --git a/test/dm/eth.c b/test/dm/eth.c index 820b8cbfc29d29aab0448602567fc1259abd799b..bb3dcc6b9540c5b1de7c3542e562e16c1dd9653c 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -6,6 +6,7 @@ * Joe Hershberger */ +#include #include #include #include diff --git a/test/dm/fastboot.c b/test/dm/fastboot.c index 5d938eb7f121ac3a843b6cb069a26cc0f3848965..758538d0e85e5a501ccb83c099cecc50d5ea9028 100644 --- a/test/dm/fastboot.c +++ b/test/dm/fastboot.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index b484414f5f07fd18d9771d385aa585081f3a927f..087d4846da89a082b7c4ba726cfbe577dd8e54b5 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include #include #include #include diff --git a/test/dm/ffa.c b/test/dm/ffa.c index fa6d54d00d616a4c6760862b42db9ae82c6917b1..6912666bb465a90724c475fdd4f7dd2bbb68b9d6 100644 --- a/test/dm/ffa.c +++ b/test/dm/ffa.c @@ -8,6 +8,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/test/dm/firmware.c b/test/dm/firmware.c index ec68e816999db6baba4242c6efcef3bf879fff9c..f37bccfe4a83336c2e72968fd326cd16fcbb616f 100644 --- a/test/dm/firmware.c +++ b/test/dm/firmware.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Xilinx, Inc. */ +#include #include #include #include diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c index 43ce3d0a9d874c1e8003de30a67e06d57abb7809..52018f610fe4764f2655f314069578ebd32489b5 100644 --- a/test/dm/fwu_mdata.c +++ b/test/dm/fwu_mdata.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/test/dm/gpio.c b/test/dm/gpio.c index 957ab25c8d34219e04c780240e37713ef3f145e2..0d88ec24bda226da95f61909f22f31eb99fa1868 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Google, Inc */ +#include #include #include #include diff --git a/test/dm/host.c b/test/dm/host.c index e514f8409cf6e42f6e287c8d307c2104971c53fe..ca05a36b3136fbb6e6edb8a40b2b1bec6cfb3e5d 100644 --- a/test/dm/host.c +++ b/test/dm/host.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c index a05b183b8bc1e00fcb7f9bb240eeb8302c83ef99..995759d4d7e2c0ce17dec42436664129f318a1dc 100644 --- a/test/dm/hwspinlock.c +++ b/test/dm/hwspinlock.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ +#include #include #include #include diff --git a/test/dm/i2c.c b/test/dm/i2c.c index e9cf9f7819a73cadb9940e86c2289eff937adadb..b46a22e79b140509eb2928c7797620f89d901d7b 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -5,6 +5,7 @@ * Note: Test coverage does not include 10-bit addressing */ +#include #include #include #include diff --git a/test/dm/i2s.c b/test/dm/i2s.c index a3d3a31b6fbc38fc8577ab61edf0d43e608a125c..c2bf4d5604b96757d1bc271cc65e75183adb343a 100644 --- a/test/dm/i2s.c +++ b/test/dm/i2s.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/iommu.c b/test/dm/iommu.c index acea5f289715c18f0781f439816ab4fef9805d92..62d38f1214ac7fee52b6adc1330456b095ffa3eb 100644 --- a/test/dm/iommu.c +++ b/test/dm/iommu.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Mark Kettenis */ +#include #include #include #include diff --git a/test/dm/irq.c b/test/dm/irq.c index d22772ab769331835e9dce4fa70e17269e056413..51dd5e4abb413acb415a9c38523fb4eaaeaddf1f 100644 --- a/test/dm/irq.c +++ b/test/dm/irq.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index 2a581499634d3284660881e15bd4b1b6f15cf17b..354720f61e2f09fa3fee2d1a98cef3f107aaa005 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ #include #include diff --git a/test/dm/led.c b/test/dm/led.c index c28fa044f459777fb371d2e1e5c951992b6e2064..eed3f4654c568aba8c1d9abdf4ec03f066875605 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c index 14f72d58d1cf2fc53119f73edd56accac8bd00a3..7ad8a1cbba282e482bdfd6d2972aa00f4ebcdca4 100644 --- a/test/dm/mailbox.c +++ b/test/dm/mailbox.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/test/dm/mdio.c b/test/dm/mdio.c index 7ececf37ccc02193ba2566f2cdba830958e56a22..f863c52645b257bf6fcf3273906eb71c1c791b87 100644 --- a/test/dm/mdio.c +++ b/test/dm/mdio.c @@ -4,6 +4,7 @@ * Alex Marginean, NXP */ +#include #include #include #include diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c index 33a7e9726094042a81596a8cede26a34f4db0d9a..bfe3518221f4742b008e484384c314649136e6ee 100644 --- a/test/dm/mdio_mux.c +++ b/test/dm/mdio_mux.c @@ -4,6 +4,7 @@ * Alex Marginean, NXP */ +#include #include #include #include diff --git a/test/dm/misc.c b/test/dm/misc.c index ad856fd01b6de4f286d0e25b19477f231798efb1..8bdd8c64bca2bd411efac6148b2f37aa7caec7d4 100644 --- a/test/dm/misc.c +++ b/test/dm/misc.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/dm/mmc.c b/test/dm/mmc.c index c0abea797d9def52a3780d34ddcc6320b04f4459..b1eb8bee2f9d5e56fa1e2ead2d8e184c108a8587 100644 --- a/test/dm/mmc.c +++ b/test/dm/mmc.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c index d4bb8befa3842e997cd34287e07bb285a08e5882..11c237b5da904acf8b02c537e6e3420ef228d7c4 100644 --- a/test/dm/mux-cmd.c +++ b/test/dm/mux-cmd.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Texas Instruments Inc. * Pratyush Yadav */ +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #define BUF_SIZE 256 diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c index febd521104afe814fd7fcaff670c58fd5f96621f..c6aeeb7e1f1b895bef82c6bed52083eaf3e4a6d9 100644 --- a/test/dm/mux-emul.c +++ b/test/dm/mux-emul.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * Pratyush Yadav */ +#include #include #include #include diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c index 3a871a19c7e277d0fdd23801e9a41743fb6bff69..27c881dabde2abe3a70df0999dda19acb0f6ef92 100644 --- a/test/dm/mux-mmio.c +++ b/test/dm/mux-mmio.c @@ -4,6 +4,7 @@ * Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/test/dm/nop.c b/test/dm/nop.c index 0c79431d9d80226aea8047b88622d5715d83ac95..f7d9a0f3df35fd265b3ee7818f4945568bac30f0 100644 --- a/test/dm/nop.c +++ b/test/dm/nop.c @@ -6,6 +6,7 @@ * Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c index 537959a0930caf8d76f15075470910e7b3ffd23e..f0ad47d4efe9313e480154f1da5e34c06db40eb4 100644 --- a/test/dm/nvmxip.c +++ b/test/dm/nvmxip.c @@ -8,6 +8,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/test/dm/of_extra.c b/test/dm/of_extra.c index 3c31bfcd31f99f1c47a29bddfa6519a5a7bc489a..ac2d886892d9bbd4afd75c7cebd14133fbc4e765 100644 --- a/test/dm/of_extra.c +++ b/test/dm/of_extra.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c index d4939e88516272ef6cba47f442b8d35778b5221a..a241c42793671de65db6e836417ab403bd2fb0ac 100644 --- a/test/dm/of_platdata.c +++ b/test/dm/of_platdata.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 39191d7f52b553f635ab20d99b0d3360bed57832..a5bc43aea4e76148bef524d89c382801051ea143 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -16,6 +16,7 @@ * behaviour of each ofnode function, since that is done by the normal ones. */ +#include #include #include #include diff --git a/test/dm/ofread.c b/test/dm/ofread.c index 69d03c4910738e8f01682098ea0ca816a7a158bf..3523860d2b312ad788209dfc290ef37e20bc2fea 100644 --- a/test/dm/ofread.c +++ b/test/dm/ofread.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include #include #include #include diff --git a/test/dm/osd.c b/test/dm/osd.c index cf4a3a545ed0c827c9f713ac3a8278bbc239c24b..6279b391ca5e9a40f81e42dbbd7d93847c927f58 100644 --- a/test/dm/osd.c +++ b/test/dm/osd.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c index 3ada1fcb3629e06f43f8199c749d3737092a7cc9..df24709141ad45599d01ea170c650805e24f7cdd 100644 --- a/test/dm/p2sb.c +++ b/test/dm/p2sb.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/test/dm/panel.c b/test/dm/panel.c index 8be7c397a46219886d808dbbed80db07b248545f..4d435a0d255c097f743f83e6298342693a707a68 100644 --- a/test/dm/panel.c +++ b/test/dm/panel.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/part.c b/test/dm/part.c index cabb31d18ca04236eed1ffaf4288eafdebd4f741..d6e4345812748f6d12e85db8061dce47a2b9c7cd 100644 --- a/test/dm/part.c +++ b/test/dm/part.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/test/dm/pch.c b/test/dm/pch.c index b37b856d5dacf862f403916a013e08af8aa506f4..53f7bbf180c9281a31e014bfd9875cdf5933a4ee 100644 --- a/test/dm/pch.c +++ b/test/dm/pch.c @@ -3,6 +3,7 @@ * Copyright 2018 Google LLC */ +#include #include #include #include diff --git a/test/dm/pci.c b/test/dm/pci.c index 9b97f2e0544f8d65f04fdfe7d682b0a96c6c5ea0..8c5e7da9e62906a4ea39e084b1dbd1880adad559 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c index e82fc53f84b1025599d5815663ccb5caf973893c..9941abd4cebc9cbf531cd45178d7bdf0e29e51d6 100644 --- a/test/dm/pci_ep.c +++ b/test/dm/pci_ep.c @@ -3,6 +3,7 @@ * Copyright (C) 2019 Ramon Fried */ +#include #include #include #include diff --git a/test/dm/phy.c b/test/dm/phy.c index d14117f6f7a91f10d9e4d6dc3cde44d7e74d8381..0cf3689fdecbf649eaceb04ef094c6aec155e3f4 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -4,6 +4,7 @@ * Written by Jean-Jacques Hiblot */ +#include #include #include #include diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c index 1ee2150482c6003aea12a52afd44ff15e0658ad6..342f2fa8ebaa92553312d8f2cd656e012ad09c85 100644 --- a/test/dm/phys2bus.c +++ b/test/dm/phys2bus.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Nicolas Saenz Julienne */ +#include #include #include #include diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c index cfbe3ef5d1eb9fcce4be4cf92ccb88f21690b5f4..6880b2d2cd9c970f542effdd66fc69a75da9c9eb 100644 --- a/test/dm/pinmux.c +++ b/test/dm/pinmux.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/test/dm/pmc.c b/test/dm/pmc.c index bbad1ee2741916e1bc5ae5ca84095d8306cb723b..e70227e7800bac539475a05abf8c53e77f2dceff 100644 --- a/test/dm/pmc.c +++ b/test/dm/pmc.c @@ -5,6 +5,7 @@ * Copyright 2019 Google LLC */ +#include #include #include #include diff --git a/test/dm/pmic.c b/test/dm/pmic.c index 53a6f0369e8701ed1e36b6dd1db179c61501d2ac..ce671202fbc60eacaaaf12398f5ecc3eb99c66d8 100644 --- a/test/dm/pmic.c +++ b/test/dm/pmic.c @@ -6,6 +6,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c index 120a9059c8e6d7424afc13749e723829b4da3424..8604b5d72dc0335f1601c4d8a4c32085e5412509 100644 --- a/test/dm/power-domain.c +++ b/test/dm/power-domain.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/test/dm/pwm.c b/test/dm/pwm.c index 80133347ec73a9004b61ee501f6d7a9c7843bf8a..dff626c771ac468ac6e7771aa61cb0a18b9abc93 100644 --- a/test/dm/pwm.c +++ b/test/dm/pwm.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 Google, Inc */ +#include #include #include #include diff --git a/test/dm/qfw.c b/test/dm/qfw.c index 3c354163ef3b11c65bc174b494631a9c19ee5ff4..f3f356898308e192b1a83f50cc9e51edabc1bef6 100644 --- a/test/dm/qfw.c +++ b/test/dm/qfw.c @@ -3,6 +3,7 @@ * Copyright 2021 Asherah Connor */ +#include #include #include #include diff --git a/test/dm/ram.c b/test/dm/ram.c index 188c7c327584f2d012a2d7f00178342ec0899522..f624343138d6bd569df873d7079be21c08e84b80 100644 --- a/test/dm/ram.c +++ b/test/dm/ram.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/read.c b/test/dm/read.c index 4ecf18110d0fba45b2e8a2786d5d473d82c11eb8..7768aa29688569fcece433ca434b6e259525e736 100644 --- a/test/dm/read.c +++ b/test/dm/read.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Nicolas Saenz Julienne */ +#include #include #include #include diff --git a/test/dm/reboot-mode.c b/test/dm/reboot-mode.c index 160b4da07f2029aaa8a50aa4e266d82aa86e047f..fbb9c3a5426a638704a5ce1bb828fcc6b7553975 100644 --- a/test/dm/reboot-mode.c +++ b/test/dm/reboot-mode.c @@ -3,6 +3,7 @@ * (C) 2018 Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/test/dm/regmap.c b/test/dm/regmap.c index 1398f8f6573ea15d5d7253ef68173dbd554bfbbf..8560f2afc2d1ffee953c44b989d4b499644ea364 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -3,13 +3,13 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/test/dm/regulator.c b/test/dm/regulator.c index 9e45fd177b944bd8ff35388c8326af383126b977..86f4862d9dd07cecda929609617d609f10c0bfb2 100644 --- a/test/dm/regulator.c +++ b/test/dm/regulator.c @@ -6,6 +6,7 @@ * Przemyslaw Marczak */ +#include #include #include #include diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index ef9e8e5a0df6d2a8af9252feff7ee5e6cea63045..f6f9e509e27a2489b7e30a6b726ee6ad1972b223 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -3,8 +3,7 @@ * (C) Copyright 2015 * Texas Instruments Incorporated - https://www.ti.com/ */ - -#include +#include #include #include #include diff --git a/test/dm/reset.c b/test/dm/reset.c index d3158bf4a72e1520f7280a78faed7a6565dc779b..e2d6f456230c758364e34f32a335608a854e3edd 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. */ +#include #include #include #include diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c index 3dc9ca1add11a8b60de81cea70cd038d7db94ae2..3c3e8efa92f2f6a76b990b70d84e150b982f1c3a 100644 --- a/test/dm/rkmtd.c +++ b/test/dm/rkmtd.c @@ -8,6 +8,7 @@ * Copyright (C) 2023 Johan Jonker */ +#include #include #include #include diff --git a/test/dm/rng.c b/test/dm/rng.c index c8ed6cadf586e1db0590d05fec909958e94d2037..6d1f68848d52eea6b999a31583c24151d350e290 100644 --- a/test/dm/rng.c +++ b/test/dm/rng.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, Linaro Limited */ +#include #include #include #include diff --git a/test/dm/rtc.c b/test/dm/rtc.c index a8aa41955c22e32557157d538b1f1f5debf93af9..bf97dbbd2f9efcd40ce0bffe0fb7af5ef1ac8e21 100644 --- a/test/dm/rtc.c +++ b/test/dm/rtc.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/scmi.c b/test/dm/scmi.c index 69fc900e342961ced985667981f502ac493aadec..adf36ffaab1dd52f7e2c9d4563eeaaec90d7051b 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -12,6 +12,7 @@ * unknown SCMI protocol ID. */ +#include #include #include #include diff --git a/test/dm/scsi.c b/test/dm/scsi.c index 5180159fb27dd0218bd4065ce8086900e168c84d..380cfc88baba2ab674279bd33f5d054466c2dad4 100644 --- a/test/dm/scsi.c +++ b/test/dm/scsi.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/serial.c b/test/dm/serial.c index 34c0d4db879acf0e55683f6a8bb701b5675d0888..34b783e062e1f3bbe3add5e4166d115edfffd283 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, STMicroelectronics */ +#include #include #include #include diff --git a/test/dm/sf.c b/test/dm/sf.c index 0e3a0f13f9ec42cb099c2c9198d57aff0dd841fc..17d43fef3bc3a10b9da50a8ab574ccef055e5b56 100644 --- a/test/dm/sf.c +++ b/test/dm/sf.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Google, Inc */ +#include #include #include #include diff --git a/test/dm/simple-bus.c b/test/dm/simple-bus.c index 8a730ba2fce4d3f43fdc634899ead786260ffdab..3530b47fac2f64aaa9a0a84feac316230c715c94 100644 --- a/test/dm/simple-bus.c +++ b/test/dm/simple-bus.c @@ -3,6 +3,7 @@ * Copyright (C) 2021, Bin Meng */ +#include #include #include #include diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c index 9949cb34d5964fe28fb9b00aaca8b3b2480d7e28..792c7450580627edc013e7e5c550701f34108135 100644 --- a/test/dm/simple-pm-bus.c +++ b/test/dm/simple-pm-bus.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/test/dm/sm.c b/test/dm/sm.c index 4d95c2ad75bd578e7242eed62c69a8d5487a0d6f..7ebb0c9c85ed437ae3ec64d479a9109493042d92 100644 --- a/test/dm/sm.c +++ b/test/dm/sm.c @@ -5,6 +5,7 @@ * Author: Alexey Romanov */ +#include #include #include #include diff --git a/test/dm/smem.c b/test/dm/smem.c index adcbfe574ab92b99f36520f40e5b20a9eabdf896..289fb59ba1367b44a97a95e200d95ab9c2db3c9e 100644 --- a/test/dm/smem.c +++ b/test/dm/smem.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Ramon Fried */ +#include #include #include #include diff --git a/test/dm/soc.c b/test/dm/soc.c index cb0ac1545f7fb43f32dbd7fb3eed6935dc9f14d4..8f6c97fa79086a9c4354619d81f69522e20b38b0 100644 --- a/test/dm/soc.c +++ b/test/dm/soc.c @@ -6,6 +6,7 @@ * Dave Gerlach */ +#include #include #include #include diff --git a/test/dm/sound.c b/test/dm/sound.c index f4e6215e683019bd88c6ee7bc82c13f56b01687f..15d545ab5a34294dc858860a62617e88d7671772 100644 --- a/test/dm/sound.c +++ b/test/dm/sound.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/spi.c b/test/dm/spi.c index 1ab2dd783249f42a453ef9379f9e12bc9c036a91..325799bbf104217a03b85959c79f5dd225829cc8 100644 --- a/test/dm/spi.c +++ b/test/dm/spi.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Google, Inc */ +#include #include #include #include diff --git a/test/dm/spmi.c b/test/dm/spmi.c index e10ae8db4d3085ba8e2a47e05834d0d626aa521b..97bb0eb30fc9b19319321844cd45e61fecf6416d 100644 --- a/test/dm/spmi.c +++ b/test/dm/spmi.c @@ -3,6 +3,7 @@ * (C) Copyright 2015 Mateusz Kulikowski */ +#include #include #include #include diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c index ba19504573f4faf79f43c19f24a0dc536924f778..eeaddf88392c7fed2e6d55c21e11275156ecb022 100644 --- a/test/dm/syscon-reset.c +++ b/test/dm/syscon-reset.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/test/dm/syscon.c b/test/dm/syscon.c index 04d324e87d442f76225a337adce636021d62eddb..be232972336255f91557515a6dd60e9d9f3b717a 100644 --- a/test/dm/syscon.c +++ b/test/dm/syscon.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c index 24a99dafb152bc147d30d2bb7c2b7b2dd130aa64..2e494b3f341280fe05791c4383f8753f2a685ff0 100644 --- a/test/dm/sysinfo-gpio.c +++ b/test/dm/sysinfo-gpio.c @@ -3,6 +3,7 @@ * Copyright (C) 2021 Sean Anderson */ +#include #include #include #include diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c index 7444a580df6eb402f177866be6ad7629904b49ae..96b3a8ebabac9ec50551402884d66ce60da7d8a4 100644 --- a/test/dm/sysinfo.c +++ b/test/dm/sysinfo.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c index f3a859be787802711483080df51eec8ec611b241..5aa69e046186a33af5406e1e38e0085969647144 100644 --- a/test/dm/sysreset.c +++ b/test/dm/sysreset.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/tag.c b/test/dm/tag.c index bce8a35acfb5da528a8ae35425a36fd2b1a49bdf..8ae8a1fcd65b8868284e6555630d46456def0186 100644 --- a/test/dm/tag.c +++ b/test/dm/tag.c @@ -6,6 +6,7 @@ * Author: AKASHI Takahiro */ +#include #include #include /* DM_TEST() */ #include /* struct unit_test_state */ diff --git a/test/dm/tee.c b/test/dm/tee.c index bb02a9b3c98b83adf348c4fd5d481b3262048026..7a11bf89138993172e9293c2c1723bce631b5937 100644 --- a/test/dm/tee.c +++ b/test/dm/tee.c @@ -3,6 +3,7 @@ * Copyright (C) 2018 Linaro Limited */ +#include #include #include #include diff --git a/test/dm/test-dm.c b/test/dm/test-dm.c index 4bc2c45db61cd38e85d5fecf8693037a1cd38c84..e73a1dd8f814e11ed7e06dcdc06819515fd4e506 100644 --- a/test/dm/test-dm.c +++ b/test/dm/test-dm.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include diff --git a/test/dm/test-driver.c b/test/dm/test-driver.c index 851177c3018ae5561787550c0caa42c8d96fb98d..02cb974b0f74eb68f60f554bf82789cd2bd2292c 100644 --- a/test/dm/test-driver.c +++ b/test/dm/test-driver.c @@ -6,6 +6,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 18c89eef43fce6a03dff7693e1b004e303737fa1..72d0eb57e21291e253dde55fad4e2675e82e50f8 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -3,6 +3,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #include diff --git a/test/dm/test-uclass.c b/test/dm/test-uclass.c index 9a80cc63667be95bc0f1cda5e618451f984824d8..067701734a08e20f0b6de0270d824f96d9727527 100644 --- a/test/dm/test-uclass.c +++ b/test/dm/test-uclass.c @@ -6,6 +6,7 @@ * Pavel Herrmann */ +#include #include #include #include diff --git a/test/dm/timer.c b/test/dm/timer.c index 7fcefc42e5954d5f3467844491935a9869aefbc2..9f94d47692003f0b45afdf98035fe93dfe9566c0 100644 --- a/test/dm/timer.c +++ b/test/dm/timer.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Thomas Chou */ +#include #include #include #include diff --git a/test/dm/tpm.c b/test/dm/tpm.c index 0e413c0eedd025db9a076d293fe01a757f16eef6..cde933ab28489467db46b55eb006d1f3f31e6760 100644 --- a/test/dm/tpm.c +++ b/test/dm/tpm.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/usb.c b/test/dm/usb.c index 9a571938b8163c9b2e51aab04b061a502dc7cfac..7671ef156d8476d35b51cec387e7d6b1a9af1965 100644 --- a/test/dm/usb.c +++ b/test/dm/usb.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Google, Inc */ +#include #include #include #include diff --git a/test/dm/video.c b/test/dm/video.c index 7dfbeb9555d15396f9322e49fda07e7404200275..d907f681600bace36d83b3335ae706cbc4e38b52 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/dm/virtio.c b/test/dm/virtio.c index 3efd7c74f4271c3c8a07acccb36a93fc892bbc0a..3e108cdc35d0485f9dd0d501f1e803355a86b298 100644 --- a/test/dm/virtio.c +++ b/test/dm/virtio.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c index 63dc53415b73d06d356acc616137214c16fdd841..fdda4da417813cc1740ffe5a73d1d75dbc5f414b 100644 --- a/test/dm/virtio_device.c +++ b/test/dm/virtio_device.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng */ +#include #include #include #include diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c index ab7d862d79ef5ea655b1dabc43b3f670fcb4fda5..8b9a04b1fdef727f0c9dcc049bea8b22d85e6ac1 100644 --- a/test/dm/virtio_rng.c +++ b/test/dm/virtio_rng.c @@ -4,6 +4,7 @@ * Written by Andrew Scull */ +#include #include #include #include diff --git a/test/dm/wdt.c b/test/dm/wdt.c index 1df2da23c6c76dad7c7cb0e12ea3770ce723accd..2bbebcdbf286f070eb0bae8d9a6dc4ce26f7ef52 100644 --- a/test/dm/wdt.c +++ b/test/dm/wdt.c @@ -3,9 +3,9 @@ * Copyright 2017 Google, Inc */ +#include #include #include -#include #include #include #include diff --git a/test/env/attr.c b/test/env/attr.c index de5d5d4ee27ca6dba226e726e876a0de70f22b53..8d5c0f1c3df49314f119b571cc5b682179feee0c 100644 --- a/test/env/attr.c +++ b/test/env/attr.c @@ -4,6 +4,7 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ +#include #include #include #include diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index 13e0998341e7e4ed3b59583b092cdfb4b74a6791..d65a32179ce10839a604eaad616a3d2c13e8a272 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -4,6 +4,7 @@ * Joe Hershberger, National Instruments, joe.hershberger@ni.com */ +#include #include #include #include diff --git a/test/env/fdt.c b/test/env/fdt.c index c495ac7b307c0a430184f4e370c24bbb7ec28fd2..30bfa88c35506036648c903937fd5b283d989da8 100644 --- a/test/env/fdt.c +++ b/test/env/fdt.c @@ -1,3 +1,4 @@ +#include #include #include #include diff --git a/test/env/hashtable.c b/test/env/hashtable.c index ccdf0138c4b8ef79b9426b3c010c242e67184587..70102f9121c271d00b851ed074ac9f4df11472f9 100644 --- a/test/env/hashtable.c +++ b/test/env/hashtable.c @@ -4,11 +4,11 @@ * Roman Kapl, SYSGO, rka@sysgo.com */ +#include #include #include #include #include -#include #include #include diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c index faa140433ff52805467fe5aa79b3b3be1922126d..d0bc7b8d7b760e4f742509bb535eb07c8f3c128c 100644 --- a/test/fuzz/cmd_fuzz.c +++ b/test/fuzz/cmd_fuzz.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include diff --git a/test/fuzz/virtio.c b/test/fuzz/virtio.c index 836eb9a2f660832fc05e2cc2929aa1a92606a9d1..8a47667e778540ea7b79999994e51698d37c2140 100644 --- a/test/fuzz/virtio.c +++ b/test/fuzz/virtio.c @@ -4,6 +4,7 @@ * Written by Andrew Scull */ +#include #include #include #include diff --git a/test/image/spl_load.c b/test/image/spl_load.c index 7cbad40ea0cde8d26b12fef50265114038fcf624..e1036eff28caf2d361fd1cb7bf8b2e671f32a9d5 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 Sean Anderson */ +#include #include #include #include diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 935078bf67b4ad090c15f0ca60481a0c3efc3483..a89189e1124c6e65a81a8f7ce71939bd2bd620e9 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 Sean Anderson */ +#include #include #include #include diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c index 4af6e21b8b98e6c4b3fbb05dced68244e1e1e5ea..9d067a7a592fed73a7ef8e9b6c18f7964a2ac2ef 100644 --- a/test/image/spl_load_net.c +++ b/test/image/spl_load_net.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 Sean Anderson */ +#include #include #include #include diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c index f53a6724e27fae5e200e774a58c1b81158b91ea1..de5686343b999f45d589b4499f7f0542820017a9 100644 --- a/test/image/spl_load_nor.c +++ b/test/image/spl_load_nor.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 Sean Anderson */ +#include #include #include #include diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 7d5fb9b07e05faebf4693d66122c471e9f629eef..26228a8a4a9ce851235757e19fd162891a640792 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c index 80836dc0dffa89993a7825b9b44fa405f0f2be5c..54a95465e239ec3bd9d35c72582cecccdc45e20a 100644 --- a/test/image/spl_load_spi.c +++ b/test/image/spl_load_spi.c @@ -3,6 +3,7 @@ * Copyright (C) 2023 Sean Anderson */ +#include #include #include #include diff --git a/test/lib/abuf.c b/test/lib/abuf.c index 7c0481ab610b5b22d199c4a1f7e89a32933f65c7..42803b20e2a1e4c5293588afd12ec441ce61e72e 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/lib/asn1.c b/test/lib/asn1.c index 4842b7058ac58f6a1587fb3808089e06636dde62..a66cdd77df0ad80f3acf66fec1a76ccc2c138f82 100644 --- a/test/lib/asn1.c +++ b/test/lib/asn1.c @@ -6,6 +6,7 @@ * Unit test for asn1 compiler and asn1 decoder function via various parsers */ +#include #include #include #include diff --git a/test/lib/cmd_ut_lib.c b/test/lib/cmd_ut_lib.c index f98cb9b3c572ed9cdd90ee55836768adb697c9ce..f1ac015b2c89786bb7dafdc27632009a3580229d 100644 --- a/test/lib/cmd_ut_lib.c +++ b/test/lib/cmd_ut_lib.c @@ -5,6 +5,7 @@ * Unit tests for library functions */ +#include #include #include #include diff --git a/test/lib/efi_device_path.c b/test/lib/efi_device_path.c index 290c8768fa4ccc7ca6e9bcba50cba8df32b10c08..24e2f23c5af5a585856a83d0c4b50af3fcde6aae 100644 --- a/test/lib/efi_device_path.c +++ b/test/lib/efi_device_path.c @@ -5,6 +5,7 @@ * Copyright (c) 2020 Heinrich Schuchardt */ +#include #include #include #include diff --git a/test/lib/efi_image_region.c b/test/lib/efi_image_region.c index 3ca49dc4a2eb959c29dbbe333ea29763148226a9..0b888f8433789264a5ebf5dcd8b8a6a99944c1f4 100644 --- a/test/lib/efi_image_region.c +++ b/test/lib/efi_image_region.c @@ -3,6 +3,7 @@ * (C) Copyright 2020, Heinrich Schuchardt */ +#include #include #include #include diff --git a/test/lib/getopt.c b/test/lib/getopt.c index 388a076200b38f304a957266d0e2259d2dcb6751..3c68b93c8a596d4b895336ed004630eb070ce7ab 100644 --- a/test/lib/getopt.c +++ b/test/lib/getopt.c @@ -6,6 +6,7 @@ * posix/tst-getopt-cancel.c */ +#include #include #include #include diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c index d531a830398de1422b2260ca3fca63f51f6295f7..5dccf4388663f3f4557865ae3517e24afb396430 100644 --- a/test/lib/hexdump.c +++ b/test/lib/hexdump.c @@ -4,6 +4,7 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#include #include #include #include diff --git a/test/lib/kconfig.c b/test/lib/kconfig.c index 0c463bb794a5e1f9f2db995d544bd723f5e59ca0..3914f699659fb5257e1681d774b8a544e6e2b2e0 100644 --- a/test/lib/kconfig.c +++ b/test/lib/kconfig.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/lib/kconfig_spl.c b/test/lib/kconfig_spl.c index 3bd8abdf4b8ef4545e45ef9129b5a329af732f72..8f8a3411b14fed40a04468156c6f93fb215342fb 100644 --- a/test/lib/kconfig_spl.c +++ b/test/lib/kconfig_spl.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 4b5b6e5e20984d6feae10fe12427f81f0045afc7..7e4368de22e29c6af090f5725bcb2d9a89aa20ba 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -3,6 +3,7 @@ * (C) Copyright 2018 Simon Goldschmidt */ +#include #include #include #include diff --git a/test/lib/longjmp.c b/test/lib/longjmp.c index 79d889bdd5fab293a620c9f605222c84617ed525..201367a5a3a2616f42ac6822a6d15a550baa0011 100644 --- a/test/lib/longjmp.c +++ b/test/lib/longjmp.c @@ -5,6 +5,7 @@ * Copyright (c) 2021, Heinrich Schuchardt */ +#include #include #include #include diff --git a/test/lib/rsa.c b/test/lib/rsa.c index 40f70010c78846fd73b8ec277e047af3c51db9b1..44f8ade226f42ebcdd3f5b312a2501c8c9cd0e07 100644 --- a/test/lib/rsa.c +++ b/test/lib/rsa.c @@ -6,6 +6,7 @@ * Unit test for rsa_verify() function */ +#include #include #include #include diff --git a/test/lib/sscanf.c b/test/lib/sscanf.c index 9fe5521749fd6801b9fb9a47981efe3d908f9e7b..772e4b9204256151493601ce3f790beadda364e1 100644 --- a/test/lib/sscanf.c +++ b/test/lib/sscanf.c @@ -9,6 +9,7 @@ * Unit tests for sscanf() function */ +#include #include #include #include diff --git a/test/lib/string.c b/test/lib/string.c index d08dbca92915c3f9b1abc7f801ae5f04a8ff9376..5dcf4d6db00389f6ed28bbb8add28409eeec7c7d 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -9,6 +9,7 @@ * This has to be considered in testing. */ +#include #include #include #include diff --git a/test/lib/strlcat.c b/test/lib/strlcat.c index d1a0293271b030cd5a53a003e8ca7bbe396769a1..d8453fe78e2c01c4ce192684f4a1e974a5cae221 100644 --- a/test/lib/strlcat.c +++ b/test/lib/strlcat.c @@ -6,6 +6,7 @@ * These tests adapted from glibc's string/test-strncat.c */ +#include #include #include #include diff --git a/test/lib/test_aes.c b/test/lib/test_aes.c index cfd9d8ca5a933b9795a01a49b7a5d701129390f9..cbc712f7eda3d19b06a1a93dfd053f2fcd65cf3c 100644 --- a/test/lib/test_aes.c +++ b/test/lib/test_aes.c @@ -5,6 +5,7 @@ * Unit tests for aes functions */ +#include #include #include #include diff --git a/test/lib/test_crypt.c b/test/lib/test_crypt.c index dcdadd992c15a4c388ff0b72718a72536f38515e..fb21edf9748467f3e58cbfc3a151779294a820b2 100644 --- a/test/lib/test_crypt.c +++ b/test/lib/test_crypt.c @@ -5,6 +5,7 @@ * Unit test for crypt-style password hashing */ +#include #include #include #include diff --git a/test/lib/test_errno_str.c b/test/lib/test_errno_str.c index 67f76442b2719b428bebf5ccfd6afe919377f91d..8a9f1fd9805abeb2cc5b8ee3494fdfc4165f314d 100644 --- a/test/lib/test_errno_str.c +++ b/test/lib/test_errno_str.c @@ -9,6 +9,7 @@ * This has to be considered in testing. */ +#include #include #include #include diff --git a/test/lib/test_print.c b/test/lib/test_print.c index c7fc50a1de17cd5e4b33ae5decb3d09a21091bf6..79b67c779321c279c48433750c0b4c8b49a751c2 100644 --- a/test/lib/test_print.c +++ b/test/lib/test_print.c @@ -5,6 +5,7 @@ * Copyright 2020, Heinrich Schuchadt */ +#include #include #include #include diff --git a/test/lib/uuid.c b/test/lib/uuid.c index 0914f2c47e77e142f7b934bacfb79d5dbcb23471..e24331a136682bfeb5990d59eedef07e1f117154 100644 --- a/test/lib/uuid.c +++ b/test/lib/uuid.c @@ -8,6 +8,7 @@ * Abdellatif El Khlifi */ +#include #include #include #include diff --git a/test/log/cont_test.c b/test/log/cont_test.c index 036d44b9d73d14345043b9fb6779cbf06b32920a..de7b7f064cd597cfcbb74ca35f496e27d695f5f2 100644 --- a/test/log/cont_test.c +++ b/test/log/cont_test.c @@ -5,6 +5,7 @@ * Test continuation of log messages. */ +#include #include #include #include diff --git a/test/log/log_filter.c b/test/log/log_filter.c index 9cc891dc48c1e7c1525b7bc0d108fdc80451f9be..b644b40a850dd590a15349cd495b03815cbeffd0 100644 --- a/test/log/log_filter.c +++ b/test/log/log_filter.c @@ -3,6 +3,7 @@ * Copyright (C) 2020 Sean Anderson */ +#include #include #include #include diff --git a/test/log/log_test.c b/test/log/log_test.c index 855353a9c40966dfad4ded9f7036e7c0bf9aeb27..c5abff80d11136185791bb6e8f7f19ee0f15c2ca 100644 --- a/test/log/log_test.c +++ b/test/log/log_test.c @@ -6,6 +6,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/log/log_ut.c b/test/log/log_ut.c index 6617ed8b15250c5fc101d4203a058fe2b73378c2..5aa3a1840045f18f6b0a76316acf30e15e368f24 100644 --- a/test/log/log_ut.c +++ b/test/log/log_ut.c @@ -5,6 +5,7 @@ * Logging function tests. */ +#include #include #include #include diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c index b714a16d2e7e0c7b1f4fedb212d27a495ee153cc..bd9a4f408e7b28f848b50e3e8f73efff62e21a36 100644 --- a/test/log/nolog_ndebug.c +++ b/test/log/nolog_ndebug.c @@ -5,6 +5,7 @@ * Logging function tests for CONFIG_LOG=n without #define DEBUG */ +#include #include #include #include diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index c4c0fa6cf81a055855daf84a8bc0a667825cbf20..4e52e5bed822af34e8bc4e3b6c63a3823dc83995 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -8,6 +8,7 @@ /* Needed for testing log_debug() */ #define DEBUG 1 +#include #include #include #include diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c index 30f30d98fe143ed955ac67809b5ab531b8163d61..df4520d28075c746dedf34052aa45e07b7912e39 100644 --- a/test/log/pr_cont_test.c +++ b/test/log/pr_cont_test.c @@ -5,6 +5,7 @@ * Test continuation of log messages using pr_cont(). */ +#include #include #include #include diff --git a/test/log/syslog_test.c b/test/log/syslog_test.c index c4180f775b95e8c81672d40a406addfa2c7c3e29..4db649db82267941216708e584c1e4a26b663023 100644 --- a/test/log/syslog_test.c +++ b/test/log/syslog_test.c @@ -10,6 +10,7 @@ /* Override CONFIG_LOG_MAX_LEVEL */ #define LOG_DEBUG +#include #include #include #include diff --git a/test/log/syslog_test_ndebug.c b/test/log/syslog_test_ndebug.c index b10e636812b56943ca490b418d395f66454dcf0f..4438791044d0bedd7fdbd3e95c2cf6d653871fdd 100644 --- a/test/log/syslog_test_ndebug.c +++ b/test/log/syslog_test_ndebug.c @@ -7,6 +7,7 @@ * Invoke the test with: ./u-boot -d arch/sandbox/dts/test.dtb */ +#include #include #include #include diff --git a/test/optee/cmd_ut_optee.c b/test/optee/cmd_ut_optee.c index c6f50e0995ac5af4077130b540a9b010f2b7f375..c3887ab11d925e507120e7dbe297576972b39348 100644 --- a/test/optee/cmd_ut_optee.c +++ b/test/optee/cmd_ut_optee.c @@ -3,6 +3,7 @@ * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH */ +#include #include #include #include diff --git a/test/overlay/cmd_ut_overlay.c b/test/overlay/cmd_ut_overlay.c index bcb29a26e216a55af8c28775355858ab845119ae..56a3df17138bfe9b7cd87a787d601db4842ce041 100644 --- a/test/overlay/cmd_ut_overlay.c +++ b/test/overlay/cmd_ut_overlay.c @@ -4,6 +4,7 @@ * Copyright (c) 2016 Free Electrons */ +#include #include #include #include diff --git a/test/print_ut.c b/test/print_ut.c index bded2b6ebe5adda45dedb1fc1823679263f6ffe6..bb844d2542b7038da1020da724d987bb6fd9fca3 100644 --- a/test/print_ut.c +++ b/test/print_ut.c @@ -3,6 +3,7 @@ * Copyright (c) 2012, The Chromium Authors */ +#include #include #include #include diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 3e01be110295daa8a80cfc5f5fbaa81b559cf92b..26b6de07f88faab105da816e0dcee577e23a8cbd 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -17,6 +17,7 @@ import u_boot_spawn # Regexes for text we expect U-Boot to send to the console. pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))') +pattern_u_boot_spl2_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))') pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))') pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ') pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'') @@ -28,6 +29,7 @@ PAT_RE = 1 bad_pattern_defs = ( ('spl_signon', pattern_u_boot_spl_signon), + ('spl2_signon', pattern_u_boot_spl2_signon), ('main_signon', pattern_u_boot_main_signon), ('stop_autoboot_prompt', pattern_stop_autoboot_prompt), ('unknown_command', pattern_unknown_command), @@ -150,20 +152,25 @@ class ConsoleBase(object): """ try: bcfg = self.config.buildconfig + config_spl = bcfg.get('config_spl', 'n') == 'y' config_spl_serial = bcfg.get('config_spl_serial', 'n') == 'y' env_spl_skipped = self.config.env.get('env__spl_skipped', False) - env_spl_banner_times = self.config.env.get('env__spl_banner_times', 1) + env_spl2_skipped = self.config.env.get('env__spl2_skipped', True) while loop_num > 0: loop_num -= 1 - while config_spl_serial and not env_spl_skipped and env_spl_banner_times > 0: + if config_spl and config_spl_serial and not env_spl_skipped: m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on SPL console: ' + self.bad_pattern_ids[m - 1]) - env_spl_banner_times -= 1 - + if not env_spl2_skipped: + m = self.p.expect([pattern_u_boot_spl2_signon] + + self.bad_patterns) + if m != 0: + raise Exception('Bad pattern found on SPL2 console: ' + + self.bad_pattern_ids[m - 1]) m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns) if m != 0: raise Exception('Bad pattern found on console: ' + diff --git a/test/stdint/int-types.c b/test/stdint/int-types.c index 9051e32c7ced8bdadce3b65af82d2168db747c42..f6d09e8643d6162782229b24dc5e908369889785 100644 --- a/test/stdint/int-types.c +++ b/test/stdint/int-types.c @@ -1,4 +1,4 @@ -#include +#include int test_types(void) { diff --git a/test/str_ut.c b/test/str_ut.c index 389779859a3d28a06c0152696e482839d086389b..fa9328ede501d4447c44fdd0923ca5ba41950f38 100644 --- a/test/str_ut.c +++ b/test/str_ut.c @@ -3,6 +3,7 @@ * Copyright 2020 Google LLC */ +#include #include #include #include diff --git a/test/test-main.c b/test/test-main.c index 3fa6f6e32ec84ee0d681e53cc88e093f9c7c32ec..b7015d9f38ddf6c308b6c6355c4ac02e0266c1fe 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/time_ut.c b/test/time_ut.c index 149c4b58f4a1f78be9df7f1021b42fba07ef8365..80b82dbfd8331af9b7fd35edaa5cf8a437eb5c2f 100644 --- a/test/time_ut.c +++ b/test/time_ut.c @@ -4,6 +4,7 @@ * Written by Simon Glass */ +#include #include #include #include diff --git a/test/unicode_ut.c b/test/unicode_ut.c index 13e29c9b9e323a59e981cea91f0f919be5ec2dba..47c3f52774cdd2798c5f364a93c486db0dd0b6d7 100644 --- a/test/unicode_ut.c +++ b/test/unicode_ut.c @@ -5,6 +5,7 @@ * Copyright (c) 2018 Heinrich Schuchardt */ +#include #include #include #include diff --git a/test/ut.c b/test/ut.c index ae99831ac8ff73854ff2239d47528a5b1f6948ea..628e9dc9805084ba4bdf90c6bd1525eabd1287c8 100644 --- a/test/ut.c +++ b/test/ut.c @@ -5,6 +5,7 @@ * Copyright (c) 2013 Google, Inc */ +#include #include #include #ifdef CONFIG_SANDBOX diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py index 89066e6403fcc8243946eb4110d67f7195ffe6b4..39f416cfd806abaf3f6a74d2c9fa044d8d832b64 100644 --- a/tools/dtoc/dtb_platdata.py +++ b/tools/dtoc/dtb_platdata.py @@ -835,6 +835,7 @@ class DtbPlatdata(): def generate_uclasses(self): self.out('\n') + self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') @@ -1058,6 +1059,7 @@ class DtbPlatdata(): self.out('/* Allow use of U_BOOT_DRVINFO() in this file */\n') self.out('#define DT_PLAT_C\n') self.out('\n') + self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') @@ -1090,6 +1092,7 @@ class DtbPlatdata(): See the documentation in doc/driver-model/of-plat.rst for more information. """ + self.out('#include \n') self.out('#include \n') self.out('#include \n') self.out('\n') diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py index c4a0889aebe73f7cef6783517bea9fba4e63fd55..597c93e8a8705c51cfd47991eb13cb6df64b1450 100755 --- a/tools/dtoc/test_dtoc.py +++ b/tools/dtoc/test_dtoc.py @@ -63,6 +63,7 @@ C_HEADER = C_HEADER_PRE + ''' /* Allow use of U_BOOT_DRVINFO() in this file */ #define DT_PLAT_C +#include #include #include ''' @@ -416,6 +417,7 @@ U_BOOT_DRVINFO(spl_test3) = { ''' uclass_text_inst = ''' +#include #include #include @@ -519,6 +521,7 @@ DM_UCLASS_INST(testfdt) = { * This was generated by dtoc from a .dtb (device tree binary) file. */ +#include #include #include